AMD Am29F010 Service Manual
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SUPPLEMENT
Am29F010 Known Good Die
1 Megabi t (128 K x 8-Bit)
CMOS 5.0 Volt-only, Uniform Sector Fla sh Memory—Die Revision 1
DISTINCTIVE CHARACTERISTICS
■ Single power supply operation
— 5.0 V ± 10% for read, erase, and program
operations
— Simplifies system-level power requirements
■ High performance
— 90 or 120 ns maximu m access time
■ Low power consumptio n
— 30 mA max active read current
— 50 mA max program/erase current
—<25 µA typical standby current
■ Flexible sector architecture
— Eig ht un i for m sec t or s
— Any combination of sectors can be erased
— Supports full chip erase
■ Sector protection
— Hardware-based feature that disables/re-
enables program and erase operations in any
combination of sectors
— Sector protection/unprotection can be
implemented using standard PROM
progr am min g eq ui pm e nt
■ Embedded Algorithms
— Embedded Erase a lgorithm automatically
pre-programs and erases the chi p or any
combination of designated sector
— Embedded Program algorithm automatically
programs and v erifies data at specified address
■ Minimum 100,000 program/erase cycles
guaranteed
■ Compatible with JEDEC standards
— Pinout and software compatible with
single-power-supply flash
— Superior inadvertent write protection
■ Data P olling and T oggle Bits
— Provides a software method of detecting
program or erase cycle completion
■ T ested to datasheet specifications at
temperature
■ Quality and reliability levels equivalent to
standard packaged components
1/13/98 Publication# 21116 Rev: B Amendment/0
Issu e Date: January 1998
SUPPLEMENT
GENERAL DESCRIPTION
The Am29F010 in Known Good Die (KGD) form is a 1
Mbit, 5.0 Volt-only Flash memory . AMD defines KGD as
standard product in die form, tested for functionality
and speed. AMD KGD products have the same reliability and quality as AMD products in packaged form.
Am29F010 Features
The Am29F010 device is organized as eight uniform
sectors of 16 Kbytes ea ch for fle x ible erase cap ab ilit y.
This de vice is desig ned t o be pr ogram med in- system
with the st andard system 5.0 V olt V
supply providing 12.0 Volt V
program or erase operations.
The Am29F010 in KGD form offers access times of 90
ns and 120 ns, allowing high speed microprocessors to
operat e witho ut wait s tates. To el imin ate bus con ten tion the device has separate chip enable (CE#), write
enable (WE#) and output enable (OE) controls.
The device requires only a single 5.0 volt power sup-
ply for both re ad an d write functions. Inte rn al ly g en er ated and r egulated voltages a re provided for th e
program and erase operations.
The device is entirely command set compatible with the
JEDEC single- power -supply F lash st andar d. Commands ar e w ri tt en to th e c om ma nd re gi s ter us i ng st a ndard micr opro cess or wr ite timi ngs. R egi ster c ont ents
serve a s i nput t o an in tern al st ate ma chi ne that c ont rols
the erase and programming circuitry. Write cycles also
intern ally latch a ddr es se s an d d at a ne ed ed for t he pr ogramming and erase operations. Readi ng data out of
the devic e is similar to r eading from other Flas h or
EPROM devices .
Device programming occurs by executing the program
command sequence. Thi s invokes the Embedded
supp ly. A power
CC
is not required for
PP
Program algorithm—an internal algorit hm that automatica lly time s the pr ogram pulse widths and ver ifies
proper cell margin.
Device erasure occurs by executing the erase command sequence. This invokes the Embedded Erase
algori thm —an i nte rnal a lgo ri thm th at a uto matic all y pr eprograms the array (if it is not already programmed) before executing the erase operation. During erase, the
device au tom a ticall y tim es th e e ra se pu ls e wi d ths an d
verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by reading the DQ7 (Data#
Polling) and DQ6 (toggle) status bits. After a program
or erase cycle has been completed, the device is ready
to read array data or accept another command.
The sector erase architecture allows me mory sect ors
to be er ased and reprog rammed withou t affecting the
data contents of other sectors. The device is erased
when shipped from the factory.
The har dware data protection measures include a
low V
detector automatically inhibits write operations
CC
during power transitions . The hardware sector protection feature disables both program and erase oper-
ations in any combination of the sectors of memory,
and is imp lemen ted usi ng sta ndar d EPR OM pro gram mers.
The system can place the device into the standby mode.
Power co nsu mpt i on i s gr ea tl y re duce d in thi s mo de.
ELECTRICAL SPECIFICATIONS
Refer to the Am29F010 data sheet, publication number
16736, for full electrical specifications for the
Am29F0 10 in KGD form.
2 Am29F010 Known Good Die 1/13/98
SUPPLEMENT
PRODUCT SELECTOR GUIDE
Family Part Number Am29F010 KGD
Speed Option (V
Max Access Time, t
Max CE# Access, t
Max OE# Access, t
= 5.0 V ± 10%) -90 -120
CC
(ns) 90 120
ACC
(ns) 90 120
CE
(ns) 35 50
OE
DIE PHOTOGRAPH
Orientation relative to
top left corner of
Gel-Pak
Orientation relative to
leading edge of tape
and reel
DIE PAD LOCATIONS
1234567
8
AMD logo location
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
2627282930
25
24
1/13/98 Am29F010 Known Good Die 3
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