AMD Advanced Micro Devices AM29F002T-70PC, AM29F002T-70JIB, AM29F002T-70JI, AM29F002T-70JC, AM29F002T-70EIB Datasheet
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PRELIMINARY
Publication# 20818 Rev: C Amendment/+2
Issue Date: March 1998
Am29F002/Am29F002N
2 Megabit (256 K x 8-Bit)
CMOS 5.0 Volt-onl y Boot Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
■ Single power supply operation
— 5.0 Volt-only operation for read, erase, and
program operations
— Minimizes system level requirements
■ High performance
— Access times as fast as 55 ns
■ Low power consumption (typical values at 5
MHz)
— 1 µA standby mode current
— 20 mA read current
— 30 mA program/erase current
■ Flexible sector architecture
— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and
three 64 Kbyte sectors
— Supports full chip erase
— Sector Protection features:
A hardware method of locking a sector to
prevent any program or erase operations within
that sector
Sectors can be locked via programming
equipment
T emporary Sector Unprotect feat ure allows code
changes in previously locked sectors
■ Top or bottom boot block configurations
available
■ Embedded Al gorithms
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
— Embedded Program algorithm automatically
writes and verifies data at specified addresses
■ Minimum 100,000 write cycle guarantee per
sector
■ Package option
— 32-pin PDIP
— 32-pin TSOP
— 32-pin PLCC
■ Compatibility with JEDEC standards
— Pinout and software compatible with single-
power supply Flash
— Superior inadvertent write protection
■ Data# Polling and toggle bits
— Provides a software method of detecting
program or erase operation completion
■ Erase Suspend/Erase Resume
— Suspends an erase operati on to read dat a from,
or program data to, a sector that is not being
erased, then resumes the erase operation
■ Hardware reset pin (RESET#)
— Hardware method to reset the de vice t o reading
array data (not available on Am29F002N)
2 Am29F002/Am29F002N
PRELIMINARY
GENERAL DESCRIPTION
The Am29F002 Family consists of 2 Mbit, 5.0 volt-only
Flash memory devices org anized as 262,144 bytes.
The Am29F002 offers the RESET# function, the
Am29F002N does not. The data appears on DQ7–
DQ0. The device is offered in 32-pin PLCC, 32-pin
TSOP, and 32-pin PDIP packages. This device is
designed to be programmed in-system with the
standard system 5.0 volt V
CC
supply. No VPP is
required for write or erase operations. The device can
also be programmed in standard EPROM programmers.
The standard device offers access times of 55, 70, 90,
and 120 ns, allowing high speed microprocessors to
operate without wait states. To eliminate bus contention
the device has separate chip enable (CE#), write
enable (WE#) and output enable (OE#) controls.
The device requires only a single 5. 0 v o lt po wer sup-
ply for both read and write functions. Internally generated and regulated voltages are provided for the
program and erase operations.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard. Commands are written to the command regis ter using
standard micropr ocessor wri te timings. Register co ntents serve as input to an internal state-machine that
controls the erase and programming circuitry. Write
cycles also internally latch addresses and data needed
for the programming and erase operations. Reading
data out of the device is similar to reading from other
Flash or EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm—an internal algorithm that automatically times the program pulse widths and verifies
proper cell margin.
Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase
algorithm—an in ternal algorithm that autom atically
preprograms the array (if it is not already prog rammed)
before e xecuting the erase operation. During erase, the
device automatically times the erase pulse widths and
verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by reading the DQ7 (Data#
Polling) and DQ6 (toggle) status bits. After a program
or erase cycle has been completed, the de vice is ready
to read array data or accept another command.
The sector erase ar chitecture allo ws memo ry secto rs
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection measures include a low
V
CC
detector that automatically in hibits write operations during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of the sectors of memory . This can be achie v ed via prog ramming equipment.
The Erase Suspend feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved.
The hardware RESET# pi n terminates any operation
in progress and resets the internal state machine to
reading array dat a. The RESET# pin ma y be tied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memor y.
(This feature is not available on the Am29F002N.)
The system can place the device into the standby
mode. Power consumption is greatly reduced in this
mode.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effectiveness. The device electrically erases all b its wit hin
a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron
injection.
Am29F002/Am29F002N 3
PRELIMINARY
PRODUCT SELECTOR GUIDE
Note: See “AC Characteristics” for full specifications.
BLOCK DIAGRAM
Family Part Number Am29F002/Am29F002N
Speed Option
VCC = 5.0 V ± 5% -55
VCC = 5.0 V ± 10% -70 -90 -120
Max access time, ns (t
ACC
) 55 70 90 120
Max CE# access time, ns (tCE) 55 70 90 120
Max OE# access time, ns (tOE) 30 30 35 50
Input/Output
Buffers
X-Decoder
Y-Decoder
Chip Enable
Output Enable
Logic
Erase Voltage
Generator
PGM Voltage
Generator
Timer
VCC Detector
State
Control
Command
Register
V
CC
V
SS
WE#
CE#
OE#
STB
STB
DQ0
–
DQ7
Sector Switches
RESET#
Data
Latch
Y-Gating
Cell Matrix
Address Latch
A0–A17
20818C-1
n/a Am29F00N
4 Am29F002/Am29F002N
PRELIMINARY
CONNECTION DIAGRAMS
3
4
5
2
1
9
10
11
12
13
27
26
25
24
23
7
8
22
21
6
32
31
20
14
30
29
28
15
16
19
18
17
A6
A5
A4
A3
A2
A1
A0
A16
DQ0
A15
A12
A7
DQ1
DQ2
V
SS
A8
A9
A11
OE#
A10
CE#
DQ7
V
CC
WE#
DQ6
A17
A14
A13
DQ5
DQ4
DQ3
NC
1
16
2
3
4
5
6
7
8
9
10
11
12
13
14
15
32
17
31
30
29
28
27
26
25
24
23
22
21
20
19
18
A11
A9
A8
A13
A14
A17
WE#
V
CC
RESET#
A16
A15
A12
A7
A6
A5
A4
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
V
SS
DQ2
DQ1
DQ0
A0
A1
A2
A3
1
31 30
2
3
4
5
6
7
8
9
10
11
12
13
17
18
19 2016
15
14
29
28
27
26
25
24
23
22
21
32
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
A12
A15
A16
RESET#
VCCWE#
A17
DQ1
DQ2
V
SS
DQ3
DQ4
DQ5
DQ6
20818C-2
PDIP
Standard TSOP
PLCC
NC on Am29F00N
NC on Am29F00N
NC on Am29F00N
RESET#
Am29F002/Am29F002N 5
PRELIMINARY
PIN CONFIGURATION
A0–A17 = 18 addresses
DQ0–DQ7 = 8 data inputs/outputs
CE# = Chip enable
OE# = Output enable
WE# = Write enable
RESET# = Hardware reset pin, active low
(not available on Am29F002N)
V
CC
= +5.0 V single power supply
(see Product Selector Guide for
device speed ratings and voltage
supply tolerances)
V
SS
= Device ground
NC = Pin not connected internally
LOGIC SYMBOL
20818C-3
18
8
DQ0–DQ7
A0–A17
CE#
OE#
WE#
RESET#
N/C on Am29F002N
6 Am29F002/Am29F002N
PRELIMINARY
ORDERING INFORMATION
Standard Pr od uct
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below.
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.
DEVICE NUMBER/DESCRIPTION
Am29F002/Am29F002N
2 Megabit (256 K x 8-Bit) CMOS Flash Memory
5.0 Volt-only Program and Erase
Am29F002 -70 P C
OPTIONAL PROCESSING
Blank = Standard Processing
B = Burn-In
Contact an AMD representative for more information.
TEMPERATURE RANGE
C = Commercial (0
°C to +70°C)
I = Industrial (-40
°C to +85°C)
E=Extended (–55
°C to +125°C)
PACKAGE TYPE
P = 32-Pin Plastic DIP (PD 032)
J = 32-Pin Rectangular Plastic Leaded Chip
Carrier (PL 032)
E = 32-Pin Thin Small Outline Package
(TSOP) Standard Pinout (TS 032)
SPEED OPTION
See Product Selector Guide and
Valid Combinations
BOOT CODE SECTOR ARCHITECTURE
T = Top sector
B = Bottom sector
B
T
Valid Combinations
Am29F002T-55
Am29F002B-55
Am29F002NT-55
Am29F002NB-55
PC, JC, JI, EC, EI
Am29F002T-70
Am29F002B-70
Am29F002NT-70
Am29F002NB-70
PC, PI, JC, JI, EC, EI
Am29F002T-90
Am29F002B-90
Am29F002NT-90
Am29F002NB-90
PC, PI, PE,
JC, JI, JE,
EC, EI, EE
Am29F002T-120
Am29F002B-120
Am29F002NT-120
Am29F002NB-120
Am29F002/Am29F002N 7
PRELIMINARY
DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal c ommand register. The command register itself does not occupy any addressable memory location. The register is composed of l atches that store the
commands, along with the address and data information needed to execute the command. The contents of
the register serve as inputs to the internal state machine. The state machine outputs dictate the function of
the device. The appropriate device bus operations
table lists the inputs and control le vels requ ired, and the
resulting output. The following subsections describe
each of these operations in further detail.
Table 1. Am29F002/Am29F002N Device Bus Operations
Legend:
L = Logic Low = V
IL
, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Care, DIN = Data In, D
OUT
= Data Out, AIN = Address In
Note: See the sections on Sector Protection and Temporary Sector Unprotect for more information. This function requires the
RESET# pin and is therefore not available on the Am29F002N device.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to V
IL
. CE# is the power
control and selects the device. OE# is the output control
and gates array data to the output pins. WE# should remain at V
IH
.
The internal state machin e is set for reading array
data upon device power-up, or after a hardware reset.
This ensures that no spurious alteration of the memory content occurs during the power transition. No
command is necessar y in this mode to obtain array
data. Standard microprocessor read cycles that assert valid addresses on the device address inputs
produce valid data on the device data outputs. The
device remains enabled for read access until the
command register contents are altered.
See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifications and to the Read Operations Timings diagram for
the timing waveforms. I
CC1
in the DC Characteristics
table represents the active current specification for
reading array data.
Writing Commands/Command Sequences
To write a command or command sequence (which includes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to V
IL
, and OE# to VIH.
An erase operation can erase one sect or, multiple sectors, or the entire de vice. The Sector Address Tables indicate the address space that each sector occupies. A
“sector address” consists of the address bits required
to uniquely select a sector. See the Command Definitions section for details on erasing a s ector or the entire
chip, or suspending/resuming the erase operation.
After the system writes the autoselect command sequence, the device enters the autoselect mode. The
system can then read autoselect codes from the internal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in this
mode. Refer to the “Autoselect Mode” and Autoselect
Command Sequence sections for more information.
I
CC2
in the DC Characteristics table represents the active current specification for the write mode. The “AC
Characteristics” section contains timing specification
tables and timing diagrams for write operations.
Program and Erase Operation Status
During an erase or program operation, the system ma y
check the status of the operation by reading the status
bits on DQ7–DQ0. Standard read cycle timings and I
CC
read specifica tions apply. Refer to “Write Ope ration
Operation CE# OE# WE#
RESET#
(n/a Am29F002N) A0–A17 DQ0–DQ7
Read L L H H A
IN
D
OUT
Write L H L H A
IN
D
IN
CMOS Standby VCC ± 0.5 V X X H X High-Z
TTL Standby H X X H X High-Z
Output Disable L H H H X High-Z
Reset (n/a on Am29F002N) X X X L X High-Z
Temporary Sector Unprotect
(See Note)
XXX V
ID
XX
8 Am29F002/Am29F002N
PRELIMINARY
Status” for more information, and to each AC Characteristics section for timing diagrams.
Standby Mode
When the system is not reading or writing to the device ,
it can place the device in the standby mode. In this
mode, current consumption is great ly reduc ed, and the
outputs are placed in the high impedance state, independent of the OE# input.
The device enters the CMOS standb y mode when CE#
and RESET# pins (CE# only on the Am29F002N) are
both held at V
CC
± 0.5 V. (Note that this is a more re-
stricted voltage range than V
IH
.) The device enters the
TTL standby mode when CE# and RESET# pins (CE#
only on the Am29F002N) are both held at V
IH
. The de-
vice requires st andard access time (t
CE
) for read access when the device is in eithe r of these standby
modes, before it is ready to read data.
The device also enters the standb y mode when the RESET# pin is driven low. Refer to the next section, “RESET#: Hardware Reset Pin”.
If the device is deselected during erasure or programming, the device draws active current until the
operation is completed.
In the DC Charac teristics tables, I
CC3
represents the
standby current specification.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
I
CC3
in the DC Characteristics tables represents the
standby current specification.
RESET#: Hardware Reset Pin
Note: The RESET# pin is not available on the
Am29F002N.
The RESET# pin provides a hardw are method of reset-
ting the device to readin g arr ay data. When the system
drives the RESET# pin low for at least a period of t
RP
,
the device immediately terminates any operation in
progress, tristates all data output pins, and ignores all
read/write attempts for the duration o f the RESET#
pulse. The device also resets the inter nal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready
to accept another command sequence, to ensure data
integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V
IL
, the device enters
the TTL standby mode; if RESET# is held at V
SS
±
0.5 V, the device enters the CMOS standby mode.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firmware from the Flash memory.
Refer to the AC Characteristics tables for RESET# parameters and timing diagram.
Output Disable Mode
When the OE# input is at VIH, output from the device is
disabled. The output pins are placed in t he high impedance state.
Table 2. Am29F002/Am29F002N Top Boot Block Sector Address Table
Sector A17 A16 A15 A14 A13
Sector Size
(Kbytes)
Address Range
(in hexadecimal)
SA0 0 0 X X X 64 00000h–0FFFFh
SA1 0 1 X X X 64 10000h–1FFFFh
SA2 1 0 X X X 64 20000h–2FFFFh
SA3 1 1 0 X X 32 30000h–37FFF h
SA4 1 1 1 0 0 8 38000h–39FFFh
SA5 1 1 1 0 1 8 3A000h–3BFFFh
SA6 1 1 1 1 X 16 3C000h–3FFFFh
Am29F002/Am29F002N 9
PRELIMINARY
Table 3. Am29F002/Am29F002N Bottom Boot Block Sector Address Table
Autoselect Mode
The autoselect mode provides manufacturer and device identification, and sector protection verification,
through identifier codes output on DQ7–DQ0. This
mode is primarily intended for progr amming equipment
to automatically match a device to be progr ammed with
its correspondi ng programming al gorithm. However,
the autoselect codes can also be accessed in-system
through the command register.
When using programming equipment, the autoselect
mode requires V
ID
(11.5 V to 12.5 V) on address pin
A9. Address pins A6, A1, and A0 must be as shown in
Autoselect Codes (High Voltage Method) table. In addition, when verifying sector protection, the sector ad-
dress must appear on the appropriate highest order
address bits. Refer to the corresponding Sector Address Tables. The Command Definitions table shows
the remaining address bits that are don’t c are. When all
necessary bits have been set as required, the programming equipment may then read the corresponding
identifier code on DQ7–DQ0.
To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in the Command Definitions table. This method does not require V
ID
. See
“Command Definitions” for details on using the autoselect mode.
Table 4. Am29F002/Am29F002N Autoselect Codes (High V o ltage Method)
L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.
Sector Protection/Unprotection
The hardware sector protection feature disables both
program and erase operations in any sector. The
hardware sector unprotection feature re-enables both
program and erase operations in previously protected sectors.
Sector protection/unprotection must be implemented
using programming equipment. The procedure requires a high voltage (V
ID
) on address pin A9 and the
control pins. Details on this method are provided in the
supplements, publication numbers 20819 and 21183.
Sector A 17 A16 A15 A14 A1 3
Sector Size
(Kbytes)
Address Range
(in hexadecimal)
SA00000X 16 00000h–03FFFh
SA1 0 0 0 1 0 8 04000h–05FFFh
SA2 0 0 0 1 1 8 06000h–07FFFh
SA3 0 0 1 X X 32 08000h–0FFFFh
SA4 0 1 X X X 64 10000h–1FFFFh
SA5 1 0 X X X 64 20000h–2FFFFh
SA6 1 1 X X X 64 30000h–3FFFFh
Description CE# OE# WE#
A17
to
A13
A12
to
A10 A9
A8
to
A7 A6
A5
to
A2 A1 A0
DQ7
to
DQ0
Manufacturer ID: AMD L L H X X V
ID
XLXLL 01h
Device ID:
Am29F002/Am29F0 02N
(Top Boot Block)
LLH
XXVIDXLXLH B0h
LLH
Device ID:
Am29F002/Am29F0 02N
(Bottom Boot Block)
LLH
XXVIDXLXLH 34h
LLH
Sector Protection Verification L L H SA X V
ID
XLXHL
01h
(protected)
00h
(unprotected)
10 Am29F002/Am29F002N
PRELIMINARY
Contact an AMD representative to obtain a copy of the
appropriate document.
The device is shipped with all sectors unprotected.
AMD offers the option of programming and protecting
sectors at its factory prior to shipping the device
through AMD’s ExpressFlash™ Servic e. Contact an
AMD representative for details.
It is possible to determine whether a sector is protected
or unprotected. See “Autoselect Mode” for details.
Temporary Sector Unprotect
Note: This feature requites the RESET# pin and is
therefore not available on the Am29F002N.
This feature allows temporary unprotection of previ-
ously protected sectors to change data in-system.
The Sector Unprotect mode is acti v ated b y setti ng the
RESET# pin to V
ID
. During this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. Once V
ID
is removed
from the RESET# pin, all the previously protected
sectors are protec ted again. Figure 1 shows the algorithm, and the Temporary Sector Unprotect diagram
shows the timing waveforms, for this feature.
Figure 1. Temporary Sector Unprotect Operation
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to the Command Definitions table). In addition, the following hardware data
protection measures pre vent a ccidental eras ure or programming, which might otherwise be caused by spurious system level signals during V
CC
power-up and
power-down transitions, or from system noise.
Low V
CC
Write Inhibit
When V
CC
is less than V
LKO
, the device does not ac-
cept any write cycles. This protects data during V
CC
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until V
CC
is greater than V
LKO
. The system must provide the
proper signals to the control pins to prevent unintentional writes when V
CC
is greater than V
LKO
.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
V
IL
, CE# = VIH or WE# = VIH. To initiate a write cycle,
CE# and WE# must be a logical zero while OE# is a
logical one.
Power-Up Write Inhibit
If WE# = CE# = V
IL
and OE# = VIH during power up , the
device does not accept commands on the rising edge
of WE#. The internal state mac hine is automatically
reset to reading array data on power-up.
START
Perform Erase or
Program Operations
RESET# = V
IH
Temporary Sector
Unprotect
Completed (Note 2)
RESET# = V
ID
(Note 1)
Notes:
1. All protected sectors unprotected.
2. All previously protected sectors are protected once
again.
20818C-4
Am29F002/Am29F002N 11
PRELIMINARY
COMMAND DEFINITIONS
Writing specific addre ss and data commands or sequences into the command register initiates device operations. The Command Definitions table defines the
valid register command sequences. Writing incorrect
address and data values or writing them in the im-
proper sequence resets the device to reading array
data.
All addresses are latched on the falling edge of WE# or
CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in the
“AC Characteristics” section.
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array
data after comp leting an Embe dded Program or Embedded Erase algorithm.
After the device accepts an Er ase Suspend command,
the device enters the Erase Suspend mode. The system can read array data using the standard read timings, except that if it reads at an address within erasesuspended sectors, the device outputs status data.
After completing a programming operation in the Erase
Suspend mode, the system may once agai n read arra y
data with the same exception. See “Erase Suspend/Erase Resume Commands” for more information
on this mode.
The system
must
issue the reset command to re-enable the dev ice f or reading arra y data if DQ5 goes high,
or while in the autoselect mode. See the “Reset Command” section, next.
See also “Requirements for Reading Arr a y Data” in the
“Device Bus Operations” section for more information.
The Read Operations table provides the read parameters, and Read Operation Timings diagram shows the
timing diagram.
Reset Command
Writing the reset command to the devi ce resets the device to reading array data. Address bits are don’t care
for this command.
The reset command may be written between the sequence cycles in an erase command sequence before
erasing begins. This resets the device to reading array
data. Once erasure begins, however, the device ignores reset commands until the operation is complete.
The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to
reading array data (also applies to programming in
Erase Suspend mode). Once programming begins,
however, the device ignores reset commands until the
operation is complete.
The reset command may be written between the sequence cycles in an autoselect command sequence.
Once in the autoselect mode, t he reset c ommand
must
be written to return to reading array data (also applies
to autoselect during Erase Suspend).
If DQ5 goes high during a program or erase operation,
writing the reset command returns the device to reading array data (also applies during Erase Suspend).
Autoselect Command Sequence
The autoselect c ommand sequenc e allows the host
system to access the manufacturer and devices codes,
and determine whether or not a sector is protected.
The Command Definitions table shows the address
and data requirements. This method is an a lternative to
that shown in the Autoselect Codes (High Voltage
Method) table, which is in tended for PROM programmers and requires V
ID
on address bit A9.
The autoselect command sequence is initiated by
writing two unlock cycles, followed by the autoselect
command. The device then en ters the autoselect
mode, and the system may read at any address any
number of times, without initiating another command
sequence.
A read cycle at address XX00h or retrieves the manufacturer code. A read cycle at address XX 01h returns
the device code. A read cycle containing a sector address (SA) and the address 02h in returns 01h if that
sector is protect ed, o r 0 0h if it i s unp rotec te d. Refer to
the Sector Address tables for valid sector addresses.
The system must write the reset command to exit the
autoselect mode and return to reading array data.
Byte Program Command Sequence
Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up
command. The program address and data are written
next, which in turn initiate the Embedded Program algorithm. The system is
not
required to provide further
controls or timings. The device automatically provides
internally generated program pulses and v erify the programmed cell margin. The Command Definitions take
shows the address and data requirements for the byte
program command sequence.
When the Embedded Program algorithm is complete,
the device then returns to reading array data and addresses are no longer latched. The system can determine the status of the prog ram oper ation b y using DQ7
or DQ6. See “Wr ite Operation Status” for information
on these status bits.
12 Am29F002/Am29F002N
PRELIMINARY
Any commands written to the device during the Embedded Program Algorithm are ignored. On the
Am29F002 only , note that a hard ware reset during the
sector erase operation immediately terminates the operation. The Sector Erase command sequence should
be reinitiated once the device has returned to reading
array data, to ensure data integrity.
Programming is allowed in any sequence an d across
sector boundaries. A bit cannot be programmed
from a “0” back to a “1”. Attempting to do so may halt
the operation and set DQ5 to “1”, or cause the Data#
Polling algorithm to indicate the op eration was successful. However, a succeeding read will show that the
data is still “0”. Only erase operations can convert a “0”
to a “1”.
Note: See the appropriate Command Definitions table for
program command sequence.
Figure 2. Program Operation
Chip Erase Command Sequence
Chip erase is a six-bus-cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does
not
require the system to
preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire
memory for an all zero data patter n prior to electr ical
erase. The system is not required to provide any controls or timings during these operations. The Command
Definitions table shows the address and data requirements for the chip erase command sequence.
Any commands written to the chip during the Embedded Erase algorithm are ignored. On the Am29F002
only, note that a hardware reset during the sector
erase operation immediately terminates the operation.
The Sector Erase command sequence should be reinitiated once the device has retu rned to reading array
data, to ensure data integrity.
The system can deter mine the status of the erase
operation by using DQ7, DQ6, or DQ2. See “Write
Operation Status” for information on these status
bits. When the Embedded Erase algorithm is complete, the device returns to reading array data and
addresses are no longer latched.
Figure 3 illustrates the algorithm for the erase operation. See the Erase/Program Operations tables in “AC
Characteristics” for p arameters , and to the Chip/Sector
Erase Operation Timings for t i ming waveforms.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the
address of the sector to be erased, and the sector
erase command . The Command Definitions table
shows the address and data requirements for the sector erase command sequence.
The device does
not
require the system to preprogram
the memory prior to erase. The Embedded Erase algorithm automatically programs and verifies the s ector for
an all zero data pattern prior to electrical erase. The
system is not required to provide a ny controls or timings during these operations.
After the command sequence is written, a sector erase
time-out of 50 µs begins. Du ring the time-ou t period,
additional sector addresses and sector erase commands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of sectors may be from one sector to all sector s. The time between these additional cycl es must be less than 50 µs,
otherwise the last address and command might not be
accepted, and erasure may begin. It is recommended
that processor interrupts be disab led during this time to
ensure all commands are accepted. The interrupts can
be re-enabled after the last Sector Erase command is
written. If the time between additional sector erase
START
Write Program
Command Sequence
Data Poll
from System
Verify Data?
No
Yes
Last Address?
No
Yes
Programming
Completed
Increment Address
Embedded
Program
algorithm
in progress
20818C-5
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