AMD 760 Software/BIOS Design Guide

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Preliminary Information

AMD-761™ System

Controller

Software/BIOS Design Guide

Publication # 24081 Rev: D Issue Date: February 2002

Preliminary Information

The contents of this document are provided in connection with Advanced Micro Devices, Inc. (“AMD”) products. AMD makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this publication. Except as set forth in AMD’s Standard Terms and Conditions of Sale, AMD assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right.

AMD’s products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any other application in which the failure of AMD’s product could create a situation where personal injury, death, or severe property or environmental damage may occur. AMD reserves the right to discontinue or make changes to its products at any time without notice.

Trademarks

AMD, the AMD logo, AMD Athlon, and combinations thereof, AMD-751, AMD-760, AMD-761, AMD-762, and AMD-766 are trademarks of Advanced Micro Devices, Inc.

Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

Preliminary Information

24081D—February 2002 AMD-761™ System Controller Software/BIOS Design Guide

1Overview 1

1.1 General BIOS Initialization Requirements . . . . . . . . . . . . . . . 2

1.1.1 AMD-761™ Configuration Spaces . . . . . . . . . . . . . . . . . . 2

1.1.2 Special Configuration Sequencing Requirements . . . . 2

1.1.3 Power-On Reset Initialization . . . . . . . . . . . . . . . . . . . . . 4

1.1.4 Programming Reserved Bits . . . . . . . . . . . . . . . . . . . . . . 7

1.1.5 Power Management Considerations . . . . . . . . . . . . . . . . 7

1.2 Recommended AMD Athlon™ Processor

SYS_CONFIG Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2 AMD-761™ System Controller Programmer’s Interface 9

2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.2 Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.2.1 Special Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.2.2 IACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.2.3 PCI Configuration Accesses . . . . . . . . . . . . . . . . . . . . . 15

2.3 Address Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.3.1 Socket2000 Address Decoding . . . . . . . . . . . . . . . . . . . 16

2.3.2 PCI/AGP Master Address Decoding . . . . . . . . . . . . . . . 17

2.4 Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.4.1 I/O Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.4.2 Configuration Register Access . . . . . . . . . . . . . . . . . . . 26

2.4.3 Device 0: PCI Configuration Registers . . . . . . . . . . . . . 27

2.4.4 Device 0, Function 1: DDR PDL

Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . 97

2.4.5 Device 1: PCI-to-PCI Bridge

Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . 117

2.5 Memory-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 138

2.5.1 AMD-761 System Controller GART Cache

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

2.5.2 Memory-Mapped Register Map . . . . . . . . . . . . . . . . . . 140

Table of Contents 3

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AMD-761™ System Controller Software/BIOS Design Guide 24081D —Februar y 2002

3 DDR SDRAM Interface 149

3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

3.2 DDR DIMMS and DDR SDRAMs . . . . . . . . . . . . . . . . . . . . . 150

3.2.1 DDR Speed Grades . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

3.2.2 DDR DIMM Data from Serial Presence

Detect (SPD) Device . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

3.3 Memory Space Configuration . . . . . . . . . . . . . . . . . . . . . . . . 152

3.4 DDR Memory DIMM Timings . . . . . . . . . . . . . . . . . . . . . . . . 157

3.4.1 Memory Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

3.5 Additional Memory Controller Settings . . . . . . . . . . . . . . . 161

3.6 DRAM Mode/Status Settings . . . . . . . . . . . . . . . . . . . . . . . . 165

3.7 ECC and Memory Scrubbing . . . . . . . . . . . . . . . . . . . . . . . . . 169

3.7.1 ECC and Memory Scrubbing Configuration . . . . . . . 172

3.8 Programmable Delay Lines (PDL) . . . . . . . . . . . . . . . . . . . . 174

3.8.1 Manual PDL Window Detection . . . . . . . . . . . . . . . . . 180

3.9 DDR I/O Drive Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

4 Power Management 185

4.1 C1 Halt State Requirements . . . . . . . . . . . . . . . . . . . . . . . . . 186

4.2 C2 Stop Grant State Requirements . . . . . . . . . . . . . . . . . . . 187

4.3 S1 Power-On Suspend State Requirements . . . . . . . . . . . . . 189

4.4 S3 Suspend to RAM State Requirements . . . . . . . . . . . . . . 190

4.4.1 STR Bit Control for S3 Support . . . . . . . . . . . . . . . . . . 191

4.5 Clock Throttling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

4.6 DDR DRAM Clock Enables . . . . . . . . . . . . . . . . . . . . . . . . . . 194

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5 PCI Bus Interface 195

5.1 Delayed Transactions and Ordering Rules Usage . . . . . . . 195

5.1.1 Delayed Transactions and Target Latency . . . . . . . . 196

5.1.2 Transaction Ordering Rules . . . . . . . . . . . . . . . . . . . . 199

5.1.3 Special Arbitration Considerations

for the Southbridge . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

5.2 PCI Performance Optimization Options . . . . . . . . . . . . . . . . 202

5.2.1 Read Prefetching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

5.2.2 PCI Chaining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

5.2.3 PCI Bus Parking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

6AGP Interface 205

6.1 AGP Dynamic Compensation Requirements . . . . . . . . . . . . 205

6.1.1 The AGP 4X Dynamic Compensation Register . . . . . 206

6.1.2 Selection of 1.5- or 3.3-V AGP Signalling . . . . . . . . . . 207

6.2 Feature Override Bits for AGP Cards . . . . . . . . . . . . . . . . . 208

6.3 BIOS Initialization Requirements . . . . . . . . . . . . . . . . . . . . 209

6.4 AGP Miniport Driver Requirements . . . . . . . . . . . . . . . . . . 210

7 Recommended BIOS Settings 211

7.1 PCI Bus 0, Device 0, Function 0 Registers . . . . . . . . . . . . . 212

7.1.1 Example Settings for Memory Timing . . . . . . . . . . . . 218

7.1.2 Examples: AGP Compensation Register Settings

(0xB4-0xBB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232

7.1.3 PCI Bus 0, Device 0, Function 1 Registers . . . . . . . . . 236

7.2 PCI Bus 0, Device 1, Function 0 Registers . . . . . . . . . . . . . 246

Table of Contents 5

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6 Table of Contents

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24081D—February 2002 AMD-761™ System Controller Software/BIOS Design Guide

List of Figures

Figure 1. AMD Athlon Processor Family Address Mapping . . . . . . . . . . 9

Figure 2. AMD Athlon Processor Family x86 Processor

Address Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 3. AMD-761 System Controller Logical Bus Hierarchy . . . . . . . 19

Figure 4. Two-Level GART Indexing . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Figure 5. Suspend to RAM (STR_Control) Bits Usage. . . . . . . . . . . . . 193

Figure 6. Example of System with Flag and Data Stored

across PCI Bus Domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

List of Figures 7

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AMD-761™ System Controller Software/BIOS Design Guide 24081D —Februar y 2002

8 List of Figures

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24081D—February 2002 AMD-761™ System Controller Software/BIOS Design Guide

List of Tables

Table 1. AMD-761 System Controller Configuration Register

Bits Unknown at RESET# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Table 2. Recommended Settings for AMD Athlon Processor

SYSCFG Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 3. AMD-761 System Controller Socket2000 Memory Map . . . . . 10

Table 4. AMD Athlon Processor Special Cycle Encodings . . . . . . . . . . . 12

Table 5. I/O Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 6. Device 0, Function 0 Configuration Register Map . . . . . . . . . . 27

Table 7. AMD-761 System Controller SERR# Assertion Control

and Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 8. Wait State Settings for DRAM Timing Register . . . . . . . . . . . . 55

Table 9. I/O Pad Drive Strength and Input Type. . . . . . . . . . . . . . . . . . . 90

Table 10. DDR Memory Base Address Register Locations . . . . . . . . . . . . 95

Table 11. AMD-761 DRAM Addressing Modes . . . . . . . . . . . . . . . . . . . . . 96

Table 12. Device 0, Function 1 Configuration Register Map . . . . . . . . . . 97

Table 13. PDL Calibration Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Table 14. DDR PDL Configuration Register Locations. . . . . . . . . . . . . . 101

Table 15. Device 1 Configuration Register Map . . . . . . . . . . . . . . . . . . . 117

Table 16. AMD-761 System Controller Memory-Mapped Registers . . . 140

Table 17. Typical CL Parameter Settings for PC1600 and PC2100 . . . . 151

Table 18. DIMM Bank Address Bit Definition. . . . . . . . . . . . . . . . . . . . . 152

Table 19. Memory Size Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

Table 20. Total Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

Table 21. AMD-761 System Controller DDR SDRAM

Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

Table 22. Memory Sizing Example, 128 Mbytes Total . . . . . . . . . . . . . . 156

Table 23. Memory Sizing Example, 320 Mbytes Total . . . . . . . . . . . . . . 157

Table 24. CAS Latency Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

Table 25. DDR Device Timing Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

Table 26. Dev 0:F0:0x54 Bit Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

Table 27. System Related Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

Table 28. Refresh Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

List of Tables 9

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AMD-761™ System Controller Software/BIOS Design Guide 24081D —Februar y 2002

Table 29. AMD-761 System Controller ECC Behavior

(with ECC Enabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

Table 30. Default DQS Delay versus System Clock Frequency . . . . . . . 176

Table 31. AMD-761 System Controller Power Management

Features for ACPI Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

Table 32. AMD-761 Processor System Controller PCI

Read Transaction Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

Table 33. Allowable AGP Rate versus Signalling Level . . . . . . . . . . . . . 207

Table 34. AGP I/O Settings for 1.5- and 3.3-V Signalling . . . . . . . . . . . . 210

10 List of Tables

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24081D—February 2002 AMD-761™ System Controller Software/BIOS Design Guide

Revision History

Date Rev Description

Text added in the following locations explaining that the registers must be saved and restored when entering and exiting the S3 state:



Section 1.1.5 on page 7, 2nd paragraph added



Section 4 on page 185, first Note expanded



Section 4.4 on page 190, paragraph two added



2/2002 D

The following additional changes were incorporated:

Section 7 on page 211, paragraph added directly after last bullet in bulleted list



Table 34 on page 210, values for PSlewXfer and NSlewXfer changed from 01 and 00, respectively, to 11 and 11



Updated “Revision History”

8/2001 C Public release. Added bidirectional WSC# feature configuration register description.

4/2001 B Modified descriptions for WSC# and WSC# feature additions. NDA version only.

3/2001 A Initial public release.

Revision History 11

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AMD-761™ System Controller Software/BIOS Design Guide 24081D —Februar y 2002

12 Revision History

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24081D—February 2002 AMD-761™ System Controller Software/BIOS Design Guide

1 Overview

The AMD Athlon™ processor powers the next generation in computing

platforms, delivering the ultimate performance for cutting-edge

applications and an unprecedented computing experience.

The AMD-761™ system controller provides standard Northbridge functionality for desktop personal computers using the AMD Athlon™ family of processors. This functionality includes the processor interface as well as PCI, AGP, and main memory interface implementing state of the art Double Data Rate (DDR) synchronous DRAM technology.

This document provides information typically required for development of the system BIOS and device drivers to properly program the AMD-761 system controller configuration registers. The document is organized as follows:



Section 1 provides an overview of the general BIOS requirements for initializing the AMD-761 system controller configuration registers.



Section 2 on page 9 contains a description of all AMD-761 system controller configuration registers.



Section 3 on page 149 contains additional information on setup of the DDR SDRAM interface configuration registers.



Section 4 on page 185 contains additional information on configuration of the power management features of the AMD-761 system controller.



Section 5 on page 195 contains additional information on setup of the PCI bus interface configuration registers.



Section 6 on page 205 contains additional information on setup of the AGP interface configuration registers.



Section 7 on page 211 contains a list of recommended settings for many of the AMD-761 system controller configuration registers.

Chapter 1 Overview 1

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AMD-761™ System Controller Software/BIOS Design Guide 24081D —Februar y 2002

1.1 General BIOS Initialization Requirements

The following sections provide general requirements for BIOS when programming the AMD-761 system controller configuration registers. Note that the register descriptions also include some specific programming notes.

1.1.1 AMD-761™ Configuration Spaces

The AMD-761 system controller contains both I/O and memorymapped configuration spaces as listed below.



I/O Mapped Space

• PCI configuration space address and data (CF8h, CFCh)

• Host bridge registers mapped in PCI configuration

space, device 0, function 0

• DDR interface PDL and I/O controls mapped in PCI configuration space to device 0, function 1

• PCI to PCI bridge/AGP registers mapped in PCI configuration space to device 1, function 0



GART Memory-Mapped Registers

• Mapped in memory space as defined by the programming of Base Address 1: GART Memory Mapped Register Base

1.1.2 Special Configuration Sequencing Requirements

This section outlines a few cases in the AMD-761 system controller configuration registers that require special handling for proper BIOS programming.

Configuration Cycles Enable

The AMD-761 system controller supports configuration address space as defined by the PCI Local Bus Specification, Revision 2.2, which defines a unique 256-byte space that is accessed through two 32-bit index registers mapped in I/O space.

As defined in the PCI specification, configuration cycles are generated on the PCI bus only when bit 31 of the Configuration Address register is set.

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24081D—February 2002 AMD-761™ System Controller Software/BIOS Design Guide

Function 1 Space The configuration registers that control the memory interface’s

Programmable Delay Lines (PDLs) and I/O drive strengths are mapped to device 0: function 1 in the host bridge. This configuration space is disabled by default and requires a write to the PCI Control register’s Func1_En (Dev 0:F0:0x4C, bit 0).

The intent of this separate configuration space is that it is configured at initial power-on, subsequently disabled, and essentially protected from further writes.



Note that the AMD-761 system controller does not report as a multifunction device (bit 7 is not set in the Header_Type field in the PCI Latency Timer and Header Type register in Dev 0:F0:0x0C).



Reads to the PCI header that normally occupies offsets 00h– 3Fh return all 1s—that is, the normal PCI header registers are not implemented.

Memory-Mapped BARs

Five DWORD registers are accessed by the AMD-761 system controller AGP miniport driver as memory-mapped space. This space is defined by the Base Address 1: GART MemoryMapped Register Base (Dev 0:F0:0x14), which provides address bits [31:12] of the memory-mapped space. Note that this space is defined as a 4-Kbyte region, hence the lower address bits [11:4] are 0s.

This register must be properly programmed by BIOS to allow the driver to access the memory-mapped space.

Memory Holes Legacy memory holes are decoded in the normal region of main

memory from 640 Kbyte to 1 Mbyte. The AMD-761 system controller does not allow PCI masters to access DRAM in this region unless the EV6_Mode bit is set in the PCI Arbitration Control Register. See “Bit Definitions PCI Arbitration Control (Dev0:F0:0x84)” on page 71.

AGP Override Bits for 4X Rate and Fast Writes

The AGP Status register (Dev 0:F0:0xA4) reports the AMD-761 system controller’s capability to support AGP fast writes and the AGP-4X rate. The operating system normally reads these bits along with the same bits in the AGP card’s status register, and uses this information to configure the AGP Command register (Dev 0:F0:0xA8) in the AMD-761 system controller and the AGP card.

Chapter 1 Overview 3

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AMD-761™ System Controller Software/BIOS Design Guide 24081D —Februar y 2002

The AMD-761 system controller provides BIOS the ability to override the reporting of fast write and 4X rate support. This override function is accomplished through a write to a separate register, which is required because the AGP Status register is specified as read-only in the AGP specification.

Refer to Section 6.2 on page 208 for details of this implementation.

Interrupt Pin Control R/W Attributes

Silicon Revisions The reader is advised to read the AMD-761™ System Controller

The Int_Pin field in the AGP/PCI Interrupt and Bridge Control register (Dev 1:F0:0x3C) is read-only by default and initializes to all 0s. If the BIOS is required to initialize this field to another value, it must first change this field to R/W by setting the Int_Pin_Cntl bit in the Miscellaneous Device 1 Control register (Dev 1:F0:0x40).

The AMD-761 system controller does not use the Int_Pin field internally, the register is provided for software compatibility only.

Revision Guide, order# 23613, for the most current information for the version of silicon being used. The silicon revision is available by reading the PCI revision ID and Class Code register in Dev 0:F0:0x08.

1.1.3 Power-On Reset Initialization

All of the AMD-761 system controller’s configuration registers must be initialized by BIOS after initial power-on, paying especially close attention to the registers that are not initialized to a known value.

The AMD-761 system controller is reset when the Southbridge’s PCIRST# pin is asserted, which occurs when transitioning from the Mechanical Off, S5, S4, or S3 sleep states.

To accommodate support of the Advanced Configuration and Power Interface (ACPI) S3 (suspend to RAM) power management state, the registers listed in Table 1 on page 5 are not initialized to a known state after reset (RESET# asserted), and they must be initialized by BIOS after initial power-on for proper operation. These registers retain the value programmed by BIOS after subsequent assertions of the RESET# pin when transitioning to and from the S3 sleep state.

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24081D—February 2002 AMD-761™ System Controller Software/BIOS Design Guide

Table 1. AMD-761™ System Controller Configuration Register Bits Unknown at RESET#

SERR_Enable [15:14]

ECC Mode/Status Dev 0:F0:0x48

DRAM Timing Dev 0:F0:0x54

DRAM Mode/Status Dev 0:F0:0x58

Status/Control Dev 0:F0:0x70 Self_Ref_En [18]

Dev 0:F0:0xC0

Memory Base Address 0–7

through

Dev 0:F0:0xDC

ECC_Diag [12]

ECC_Mode [11:10]

SBPWaitState [31] Addr_Timing_A [30] Addr_Timing_A [29]

RD_Wait_State [28] Reg_DIMM_En [27]

WTR

RRD

[26]

[25:24]

[23]

Idle_Cyc_Limit [18:16]

PH_Limit [15:14]

RCD

RAS

[11:9]

[8:7]

[6:4]

[3:2]

[1:0]

Burst_Ref_En [20]

Ref_Dis [19]

Reserved [18]

Cyc_Per_Ref [17:16] CS7_X4Mode [7] CS6_X4Mode [6] CS5_X4Mode [5] CS4_X4Mode [4] CS3_X4Mode [3] CS2_X4Mode [2] CS1_X4Mode [1] CS0_X4Mode [0]

CS_Base [31:23]

CS_Mask [15:7]

Addr_Mode [2:1]

CS_En [0]

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AMD-761™ System Controller Software/BIOS Design Guide 24081D —Februar y 2002

Table 1. AMD-761™ System Controller Configuration Register Bits Unknown at RESET# (Continued)

SW_Recal [7]

Use_Act_Dly [6]

DDR PDL Calibration Control Dev 0:F1:0x40

Dev 0:F1:0x44

DDR PDL Configuration 0–17

DDR DQS/MDAT Pad Configuration Dev 0:F1:0x8C

DDR CLK/CS Pad Configuration Dev 0:F1:0x90

DDR CMDB/CMDA Pad

Configuration

through

Dev 0:F1:0x88

Dev 0:F1:0x94

Auto_Cal_En [5]

Act_Dly_Inh [4]

Auto_Cal_Period [1:0]

Clk_Dly [31:24]

SW_Cal_Dly [23:16]

Cal_Dly [15:8] Act_Dly [7:0]

PSlewMDAT [29:27]

NSlewMDAT [26:24]

PDrvMDAT [19:18] NDrvMDAT [17:16]

PSlewDQS [13:11]

NSlewDQS [10:8]

PDrvDQS [3:2] NDrvDQS [1:0] PSlewCLK [29:27]

NSlewCLK [26:24]

PDrvCLK [19:18]

NDrvCLK [17:16]

PSlewCS [13:11]

NSlewCS [10:8]

PDrvCS [3:2]

NDrvCS [1:0] PSlewCMDB [29:27] NSlewCMDB [26:24]

PDrvCMDB [19:18]

NDrvCMDB [17:16] PSlewCMDA [13:11] NSlewCMDA [10:8]

PDrvCMDA [3:2]

NDrvCMDA [1:0]

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Table 1. AMD-761™ System Controller Configuration Register Bits Unknown at RESET# (Continued)

PSlewMAB [29:27]

NSlewMAB [26:24]

PDrvMAB [19:18]

DDR MAB/MAA Pad Configuration Dev 0:F1:0x98

NDrvMAB [17:16] PSlewMAA [13:11] NSlewMAA [10:8]

PDrvMAA [3:2]

NDrvMAA [1:0]

Refer to Section 7 on page 211 for suggested values for these configuration registers.

1.1.4 Programming Reserved Bits

The AMD-761 system controller has many bits that are specified as reserved and which may be used in future silicon revisions. BIOS must always write a 0 to these bits and not depend on the value read back.

1.1.5 Power Management Considerations

There are several requirements for BIOS initialization of the AMD-761 system controller’s configuration register when supporting power management. Refer to Section 4 on page 185 for further details of these requirements.

For any system enabling the S3 state, a number of core logic PCI configuration registers and processor MSRs must be saved or restored prior to suspending or restoring S3. Also, certain hidden bits must be unmasked. These requirements apply to all platforms regardless of segment and whether or not AMD PowerNow!™ is used.

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AMD-761™ System Controller Software/BIOS Design Guide 24081D —Februar y 2002

1.2 Recommended AMD Athlon™ Processor SYS_CONFIG Settings

Table 2 provides recommendations for settings in the AMD Athlon processor System Configuration register in systems that utilize the AMD-761 system controller.

Table 2. Recommended Settings for AMD Athlon™ Processor SYSCFG

Bit Field Name

[22] EvictEn 0

[17] SysUcLockEn 0

[16] ChxToDirtyDis 0

[13] SysFillValIsD1 0

[11] ClVicBlkEn 0

SetDirtyEnE 0 There are three set-to-dirty enables: Set-

SetDirtyEnO 0

[10:8]

SetDirtyEnS 0

BIOS

Setting

Comments

An Evict command, when set, is sent as part of an INVD instruction. The Evict command has no function in the AMD-761™ system controller.

A LockToggle command, when set, is sent as part of a LOCK instruction prefix and certain other instructions. LockToggle has no function in the AMD-761 system controller.

The AMD Athlon™ processor and the AMD-761 system controller support Change-To-Dirty commands.

ClVicBlkEn, when set, causes all evicted clean blocks to cause the CleanVictimBlk system interface command. This setting has no function with the AMD-761 system controller.

DirtyEnE, SetDirtyEnO, and SetDirtyEnS. If a given enable is set and a cache block must make a transition from E-to-M, O-toM, or S-to-M, then the AMD Athlon processor performs the action indicated by the setting of the ChxToDirtyDis field. However, if a given enable is cleared, the processor takes no externally visible action when the desired transition is performed. Change to dirty commands are not needed by the AMD-761 system controller.

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2 AMD-761™ System Controller

Programmer’s Interface

2.1 Overview

The AMD-760™ chipset supports both x86 and Alpha™ processors that conform to the Socket2000 bus specification. Both processors share a compatible view of system memory and peripherals. Legacy x86 (IBM PC-AT) memory mappings are implemented by x86 processors (AMD Athlon™ processor) as shown in Figure 1.

AMD Athlon™

Processor Family

x86 µProcessor

PC Memory View

Mapping Logic

Socket2000

Northbridge

AMD-761™ System Controller

PCI

Southbridge

AMD-766™ Peripheral Bus

Controller

AMD Athlon

Processor Family

Alpha µProcessor

Conventional Memory View

Same view of the system

Socket2000

Northbridge

AMD-761 System Controller

PCI

Southbridge

AMD-766 Peripheral Bus Controller

Figure 1. AMD Athlon™ Processor Family Address Mapping

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2.2 Address Map

Table 3 shows the address map implemented by the AMD-761™ system controller.

Table 3. AMD-761™ System Controller Socket2000 Memory Map

Address Space Start Address Space End Name/Command Description

SysAddOut MS B =0 &

1 FF000 0000 SysAddOut MS B =0

& 1 FE00 0000

SysAddOut MS B =0 &

1 FC00 0000

SysAddOut MS B =0 &

1 F800 0000

SysAddOut MS B =0 &

1 0000 0000

SysAddOut MS B =0 &

0 0000 0000

SysAddOut MS B =1 &

0 0000 0000 SysAddOut MS B =1

& 0 0000 0000

SysAddOut MS B =1 &

0 FF000 0000

SysAddOut MS B =0 &

0 0000 0000

SysAddOut MSB =0 &

3 FFFF FFFF SysAddOut MSB

=0 & 1 FEFF FFFF

SysAddOut MSB =0 &

1 FDFF FFFF

SysAddOut MSB =0 &

1 FBFF FFFF

SysAddOut MSB =0 &

1 F7FF FFFF

SysAddOut MSB =0 &

0 FFFF FFFF

SysAddOut MSB =1 &

3 FFFF FFFF SysAddOut MSB

=1 & 3 FFFF FFFF

SysAddOut MSB =1 &

3 FFFF FFFF

SysAddOut MSB = 0 &

3 FFFF FFFF

Reserved (Masked)

PCI Configuration Space

(Masked)

PCI I/O Space (Masked)

PCI IACK/Special Cycle Generation

(Masked)

Reserved (Masked)

PCI Memory Space (Masked)

Normal Memory (Masked Writes)

Reserved (Masked Reads)

Reserved (Blocks)

Normal Memory (Blocks)

May be used by the Northbridge for other purposes (used for EV6 Northbridges).

This space is used to create PCI configuration cycles using WrBytes, WrLWs, RdBytes, and RdLWs commands only. See Section 2.2.3 on page 15.

This space is used to create PCI I/O cycles using only WrBytesWrLWs, RdBytes and RdLWs commands.

WrLWs commands to this space are used to create PCI special cycles. The lower 16 bits of the data is passed on to the PCI bus as both the address and data with the special cycle PCI command. See Section 2.2.1 on page 12 for all special cycles generated by the AMD Athlon™ processor. RdBytes commands to this space are used to create PCI IACK. The lower 16 bits of these addresses are passed on unmodified to the PCI with the IACK PCI command. See Section 2.2.2 on page 15.

May be used by the Northbridge for other purposes (used for EV6 Northbridges).

The lower 32 bits of these addresses are forwarded unmodified to the PCI. Accessed only with Wr/RdBytes, Wr/RdLWs, Wr/RdQWs. The AMD-761™ system controller generates low-order address bit as required from the AMD Athlon processor system bus MASK field.

DRAM, accessed only with masked write commands WrBytes, WrLWs, WrQWs.

The AMD-761 system controller does not support masked reads to this address space.

May be used by the Northbridge for other purposes (used for EV6 Northbridges).

DRAM, accessed with read and write block commands. Note that the AMD-761 system controller only uses 32 address bits internally and the address space wraps. Address 1 0000 0000 is treated the same as 0 0000 0000.

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For reference, the x86 view of memory from the perspective of the AMD Athlon processor and the mapping to the Socket2000 memory map is shown in Figure 2.

Note: Not to scale.

I/O Space

CF8, CFC

x86 In and Out Address Space

(BAR0)

TOM

APIC Registers

PCI Memory

Reserved

AGP Virtual

Reserved

Extended

Memory

BIOS

VGA

GART

640–1-Mbyte addresses are sent to PCI or DRAM as a function of AMD Athlon processor MSRs.

Reserved

PCI Config

PCI I/O

PCI IACK/Special

PCI Memory

DRAM

DOS Memory

x86 Memory Address Space

Socket2000 Address Space

Figure 2. AMD Athlon™ Processor Family x86 Processor Address Mapping

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2.2.1 Special Cycles

Special cycles generated by the AMD Athlon processor are forwarded down to the PCI bus with specific values in the address and data fields of the PCI special cycle command. Table 4 defines these values. The AMD Athlon processor generates AMD Athlon processor system bus WrLWs commands to a single address (1 F8000 0000) with the data field specifying the desired special cycle. The AMD-761 system controller maps the AMD Athlon processor system bus data value onto the PCI for both address and data phases of the Special Cycle Transaction.

Table 4. AMD Athlon™ Processor Special Cycle Encodings

PCI Address and

Special Cycle

SHUTDOWN 0000 0000

HALT 0000 0001

Data Field

Contents

Processor Description

The AMD Athlon™ processor generates in response to a shutdown condition. AMD Athlon processor system bus WrLWs command: SysAddOut: MSB=0 & [33:0] = 1 F8000 0000

SysDatOut: [31:0] = 0000 0000

The AMD Athlon processor generates in response to executing a HALT instruction: WrLWs command: SysAddOut: MSB=0 & [33:0] = 1 F8000 0000

SysDatOut: [31:0] = 0000 0001

Northbridge and Southbridge

Description

The AMD-761™ system controller forwards onto the PCI bus the PCI special cycle command: AD[31:0] = 0000 0000 (address and data).

AMD-766™ peripheral bus controllers asserts INIT to processor.

The AMD-761 system controller waits for all queues to memory to be empty (assumes the PCI grant enable register is clear, “Dev0:F0:0x84” on page 70). AMD-761 system controller optionally (via “Dev0:F0:0x60” on page 61) initiates an AMD Athlon system bus disconnect to this specific CPU. The AMD-761 system controller forwards onto the PCI bus (after the optional AMD Athlon system bus disconnect).

PCI special cycle command: AD[31:0] = 0000 0001 (address and data)

AMD-766 peripheral bus controllers ignores.

The AMD-761 system controller forwards onto the PCI bus, PCI special cycle command: AD[31:0] = 0001 0002 (address and data).

AMD-766 peripheral bus controllers ignores.

INVALIDATE

0001 0002

The AMD Athlon processor generates in response to executing a WBINV instruction WrLWs command: SysAddOut: MSB=0 & [33:0] = 1 F8000 0000

SysDatOut: [31:0] = 0001 0002

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Table 4. AMD Athlon™ Processor Special Cycle Encodings (Continued)

PCI Address and

Special Cycle

INVALIDATE 0002 0002

FLUSHACK 0003 0002

CONNECT 0004 0002

Data Field

Contents

Processor Description

The AMD Athlon™ processor generates in response to executing an INVD instruction WrLWs command: SysAddOut: MSB=0 & [33:0] = 1 F8000 0000

SysDatOut: [31:0] = 0002 0002

The AMD Athlon processor generates in response to assertion of the FLUSH pin after all caches have been flushed to memory. WrLWs command: SysAddOut: MSB=0 & [33:0] = 1 F8000 0000

SysDatOut: [31:0] = 0003 0002

The AMD Athlon processor generates CONNECT as the first cycle after STOP/GRANT or HALT AMD Athlon system bus special cycle regardless of whether or not a disconnect is achieved (or even attempted).

WrLWs command: SysAddOut: MSB= 0 & [33: 0] = 1 F8000 0000 SysDatOut: [31: 0] = 0004 0002

Northbridge and Southbridge

Description

The AMD-761™ system controller forwards onto the PCI bus the PCI special cycle command: AD[31:0] = 0002 0002 (address and data).

AMD-766™ peripheral bus controllers ignores.

The AMD-761 system controller forwards onto the PCI bus, PCI special cycle command: AD[31:0] = 0003 0002 (address and data).

AMD-766 peripheral bus controllers ignores.

The AMD-761 system controller forwards onto the PCI bus, PCI special cycle command: AD[31: 0] = 0004 0002

(address and data) AMD-766 peripheral bus controllers

ignores.

The AMD Athlon processor generates an SMM ACK (ENTER) when entering a system management interrupt.

SMM ACK

(ENTER)

SMM ACK (EXIT)

0005 0002

0006 0002

WrLWs command: SysAddOut: MSB= 0 & [33: 0] = 1 F8000 0000 SysDatOut: [31: 0] = 0005 0002

The AMD Athlon processor generates SMM ACK (EXIT) when exiting from a system management interrupt.

WrLWs command: SysAddOut: MSB= 0 & [33: 0] = 1 F8000 0000 SysDatOut: [31: 0] = 0006 0002

The AMD-761 system controller forward onto the PCI bus, special cycle command: AD[31: 0] = 0005 0002.

The AMD-761 system controller forwards to the PCI bus.

Command: AD[31: 0] = 0006 0002.

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Table 4. AMD Athlon™ Processor Special Cycle Encodings (Continued)

PCI Address and

Special Cycle

STOP/GRANT 0012 0002

Data Field

Contents

Processor Description

AMD Athlon™ processor generates in response to assertion of the STPCLK. WrLWs command: SysAddOut: MSB=0 & [33:0] = 1 F8000 0000

SysDatOut: [31:0] = 0012 0002

Northbridge and Southbridge

Description

The AMD-761™ system controller waits for all queues to memory to be empty (assumes the PCI grant enable register is clear, “Dev0:F0:0x84” on page 70). The AMD-761 system controller system controller optionally (via “Dev0:F0:0x60” on page 61) initiates an AMD Athlon processor system bus disconnect to this specific processor. The AMD-761 system controller forwards onto the PCI bus (after the optional system bus disconnect) PCI special cycle command: AD[31:0] = 0012 0002 (address and data).

The AMD-766™ peripheral bus controllers receives and enters the appropriate power state. The AMD-766 peripheral bus controllers may then assert DCSTOP# to the Northbridge to signal that it should deassert CKE to DDR SDRAMs and stop its internal clocks.

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2.2.2 IACK

In x86 compatible Socket2000 systems, APIC is used as the interrupt controller. To fetch the appropriate vector during IACK cycles, x86 processors are required to assert their APIC ID (CPU ID) on bits [15:12] of the address field when reading the IACK generation space. IACK return data flushes all PCI and AGP/PCI write buffers to memory.

2.2.3 PCI Configuration Accesses

In legacy x86 PC systems, PCI configuration cycles are generated via an indirect method. A configuration address register is defined at I/O address 0CF8 that allows software to load a value that is asserted on the PCI address wires during the next configuration read/write cycle. A configuration data register is defined at I/O address 0CFC that allows software to generate configuration read and write cycles on the PCI using IN and OUT instructions. Data sent during OUT instructions to the Configuration Data register is asserted on the PCI data wires during the generated configuration write transaction. Data received in response to a generated configuration read transaction is returned to satisfy the IN from the Configuration Data register.

In Socket2000 systems, PCI configuration cycles are generated in one of two ways:



In EV6 Compatible mode, the x86 processor must detect IN and OUT instructions that reference 0CF8 and 0CFC and generate the appropriate, explicit RdBytes/Rd/LWs and WrBytes/WrLWs Socket2000 commands to a 16-Mbyte region as follows:

• When an OUT instruction is detected to 0CF8, the write data is saved into a register and the instruction retired.

• When an IN/OUT instruction is detected to 0CFC, an appropriate AMD Athlon system bus Rd/Wr transaction is launched with the SysAdd Field[23:0] taken from the register that saved the most recent write to 0CF8 (above).



In traditional mode, which the AMD-761 system controller implements, IN and OUT instructions that reference 0CF8 and 0CFC are passed normally on to the AMD Athlon processor system bus where the Northbridge generates the appropriate PCI configuration access.

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2.3 Address Decoding

A consistent view of memory and PCI devices is enforced by decoding logic in the AMD-761 system controller in the AMD Athlon processor system bus and PCI interfaces.

2.3.1 Socket2000 Address Decoding

The AMD-761 system controller must consider both the AMD Athlon processor system bus SysAddOut field and the command field when deciding what to do with a given command. This AMD Athlon processor system bus decoding is summarized as follows:



SysAddOut MSB = 0 and command is a block command, DRAM is accessed:

• If SysAddOut [31:0] falls between Dev0:BAR0 and Dev0:BAR0+Len, address is to AGP virtual address space and needs to passed through the GART before presentation to DRAM.



SysAddOut MSB = 1 and command is a masked write command (WrQWs, WrLWs, WrBytes), DRAM is accessed:

• If SysAddOut [31:0] falls between Dev0:BAR0 and Dev0:BAR0+Len, address is to AGP virtual address space and needs to passed through the GART before presentation to DRAM.



SysAddOut MSB = 0 and SysAddOut [35:32] = 0 and command is a masked command, PCI memory-mapped I/O is accessed:

• Using Dev0:F0:0x14, BAR1, send to the AMD-761 system controller memory-mapped GART control registers (see Section 2.5 on page 138).

• Memory range address decoding, send to either PCI or AGP/PCI using address bits [31:0] based on the following:

• Dev1:0x20, 0x24 (see “AGP/PCI Memory Limit and

Base (Dev1:0x20)” on page 131 and “AGP/PCI Prefetchable Memory Limit and Base (Dev1:0x24)” on page 133).

• Dev 0:F0:0x84 AGP VGA BIOS bits, see “Bit

Definitions PCI Arbitration Control (Dev0:F0:0x84)” on page 71).

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

SysAddOut MSB = 0 and SysAddOut [35:24] = 1F8 and command is RdBytes, an IACK special cycle is generated on the primary PCI. SysAddOut[15:0] are asserted on PCI AD[15:0] during this cycle. The data returned on the PCI is returned to the processor.



SysAddOut MSB = 0 and SysAddOut [35:24] = 1F8 and command is WrBytes, a PCI special cycle is generated on the primary PCI. SysAddOut[15:0] are asserted on PCI AD[15:0] during this cycle (address = data).



SysAddOut MSB = 0 and SysAddOut [35:24] = 1FC/1FD and command is RdBytes or WrBytes, a PCI I/O command is generated. SysAddOut[23:0] are asserted on PCI AD[23:0] with the PCI I/O read or write command.

• Using Dev1:0x1C, I/O range address decoding, send to either PCI or AGP/PCI.

Note: Low-order AMD Athlon processor system bus address bits, per

the AMD Athlon processor system bus specification, SysAddOut only goes down to PA[3]. For mask operations, the Mask[7:0] bits are encoded to logically create PA[2:0] in the above.

2.3.2 PCI/AGP Master Address Decoding

The PCI controllers in the AMD-761 system controller must consider the received PCI/AGP address in conjunction with the BAR registers and the memory configuration registers to route the transaction. The AMD-761 system controller does not allow PCI masters to access I/O regions or main memory from 640 Kbyte to 1 Mbyte (unless the EV6_Mode bit is set as described in “Bit Definitions PCI Arbitration Control (Dev0:F0:0x84)” on page 71). This decoding is summarized as follows:

1. AD[31:0] is less than the physical top of memory (from the memory controller), DRAM is accessed.

2. AD[31:0] is above the physical top of memory and it falls between Dev0:BAR0 and Dev0:BAR0+Len, address is to AGP virtual address space and needs to be passed through the GART before presentation to DRAM.

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3. Memory range address decoding, send to AGP/PCI using address bits [31:0] based on the following (for writes only from the primary PCI):

• Dev1:0x20, 0x24 (see “AGP/PCI Memory Limit and Base (Dev1:0x20)” on page 131 and “AGP/PCI Prefetchable Memory Limit and Base (Dev1:0x24)” on page 133).

• Dev 0:F0:0x84 AGP VGA BIOS bits (see “Bit Definitions PCI Arbitration Control (Dev0:F0:0x84)” on page 71).

4. Else, the primary PCI is accessed (for writes only from the AGP/PCI).

Note: GART Control register access. The AMD-761 system

controller does not allow access to the memory-mapped GART control registers from either PCI or AGP/PCI masters.

2.4 Configuration Registers

All functional registers in the AMD-761 system controller are implemented as PCI configuration registers. The AMD-761 system controller implements a standard PCI hierarchy that allows BIOS software to enumerate devices on the primary PCI, the AGP port, and future interfaces. See the logical bus hierarchy in Figure 3 on page 19.

Note that the AMD-761 system controller only responds to function 0 and 1, device 0 and function 0, device 1. All other configuration accesses return Fs. Function 1, device 0 accesses are ignored unless enabled by the appropriate bit in the PCI Control register (see “Dev0:F0:0x4C” on page 47).

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Processor

Host to PCI

Bridge

Device 0:F0/F1

PCI

PCI-to-PCI

Bridge

Device 1:F0

PCI-to-PCI

Bridge

Device 1:F1

Processor

(Future Interface)

Figure 3. AMD-761™ System Controller Logical Bus Hierarchy

2 Processor

System Only

PCI Devices

AGP

Southbridge

AGP

Master

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2.4.1 I/O Register Map

The AMD-761 system controller implements some I/O registers (accessed by processor I/O instructions). These registers, as presented in Table 5, are the Configuration Address and Configuration Data registers as specified in PCI Local Bus Specification, Revision 2.2.

Table 5. I/O Register Map

Configuration Address

Configuration Data

AMD Athlon™ Processor System Bus

Address

SysAddOut MSB =0 & 1 FC000 0CF8

SysAddOut MSB =0 & 1 FC000 0CFC

Reference

“I/O:0CF8” on page 21 and “I/O:0CF8” on page 23

“I/O:0CFC” on page 25

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Configuration Address Register Type 0 I/O:0CF8

31 30 29 28 27 26 25 24

Bit Config_En Reserved

Reset00000000

R/W R/W R

23 22 21 20 19 18 17 16

Bit PCI_Bus_Num

Reset00000000

R/W R/W

15 14 13 12 11 10 9 8

Bit Dev_Num Func_Num

Reset00000000

R/W R/W

7 6 5 4 3 2 1 0

Bit Reg_Num Reserved

Reset00000000

R/W R/W R

When writes to the configuration address register have [23:16] == 0h00, a Type 0 configuration access is specified.

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Bit Definitions Configuration Address Register Type 0 (I/O:0CF8)

Bit Name Function

31 Config_En Configuration Enable

0 = PCI configuration cycles are not generated.

1 = Accesses to the Configuration Data and Address registers are converted to

configuration cycles on the PCI.

30–24 Reserved Reserved

23—16 PCI_Bus_Num PCI Bus Number

This bit field defines which PCI bus in the system is referenced with this address. The AMD-761™ system controller logically implements two PCI buses. The main PCI bus normally enumerates as bus 0 and the AGP bus enumerates as bus 1.

15—11 Dev_Num Device Number

This bit field defines which device is accessed in the system. Devices are assigned numbers in a system by tying the device IDSEL wire to a specific PCI AD wire. The AMD-761 system controller decodes this field and asserts the appropriate AD wire during the address phase to select the defined device. In the AMD-761 system controller there are two “hard-wired” device numbers for the host to PCI bridge (0b00000) and P2P bridge (0b00001).

10—8 Func_Num Function Number

This bit field defines which function is accessed in a given device. The AMD-761 system controller responds to function 0 only (0b000) by default. Function 1 (DDR PDL registers) can be enabled via writing to the PCI Control register (Dev 0:F0:0x4C) as described on page 47.

7—2 Reg_Num Register Number

This bit field defines which specific PCI register is accessed in the device and function specified above. The register numbers for the AMD-761 system controller device 0 are listed in Table 6, “Device 0, Function 0 Configuration Register Map,” on page 27. The register numbers for the AMD-761 device 1 are listed in Table 15, “Device 1 Configuration Register Map,” on page 117.

1—0 Reserved Reserved

Programming Notes

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Configuration Address Register Type 1 I/O:0CF8

31 30 29 28 27 26 25 24

Bit Config_En Reserved

Reset00000000

R/W R/W R

23 22 21 20 19 18 17 16

Bit PCI_Bus_Num

Reset00000000

R/W R/W

15 14 13 12 11 10 9 8

Bit Dev_Num Func_Num

Reset00000000

R/W R/W

7 6 5 4 3 2 1 0

Bit Reg_Num Reserved

Reset00000000

R/W R/W R

When writes to the configuration address register have [23:16] ~= 0h00, a type 1 configuration access is specified.

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Bit Definitions Configuration Address Register Type 1 (I/O:0CF8)

Bit Name Function

31 Config_En Configuration Enable

0 = PCI configuration cycles are not generated.

1 = Accesses to the Configuration Data and Address registers are converted to

configuration cycles on the PCI.

30–24 Reserved Reserved

23—16 PCI_Bus_Num PCI Bus Number

15—11 Dev_Num Device Number

This bit field defines which device is accessed in the system on the target PCI bus. This field is passed on directly to the AD wires undecoded.

10—8 Func_Num Function Number

This bit field defines which function is accessed in a given device. This field is passed on directly to the AD wires undecoded.

7—2 Reg_Num Register Number

This bit field defines which specific PCI register is accessed in the device and function specified above.

1—0 Reserved Reserved

Programming Notes

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Configuration Data I/O:0CFC

31 30 29 28 27 26 25 24

Bit Config_Data

Resetxxxxxxxx

R/W R/W

23 22 21 20 19 18 17 16

Bit Config_Data

Resetxxxxxxxx

R/W R/W

15 14 13 12 11 10 9 8

Bit Config_Data

Resetxxxxxxxx

R/W R/W

7 6 5 4 3 2 1 0

Bit Config_Data

Resetxxxxxxxx

R/W R/W

Bit Definitions Configuration Data (I/O:0CFC)

Bit Name Function

31—0 Config_Data Configuration Data

This bit field is used to access the PCI configuration register specified in the Configuration Address register above.

Programming Notes

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2.4.2 Configuration Register Access

The AMD-761 system controller implements most registers as PCI configuration registers. The x86 software executes IN and OUT instructions to I/O addresses of 0CF8 and 0CFC to access all configuration registers. These are translated by the AMD Athlon™ processor into AMD Athlon processor system bus RdBytes and WrBytes commands with the lower 24 bits of the address field containing the logical contents of the ConfigAddr register (I/O address 0CF8). The format of this register is shown in “I/O:0CF8” on page 21 and “I/O:0CF8” on page 23.

Configuration accesses in the AMD-761 system controller conform to the following rules:



The AMD-761 system controller is defined to be function 0 and 1, device 0; and function 0, device 1. The IDSEL pin of all external PCI devices must be wired to 1 of AD[31:13] as logically [12:11] are assigned to device 0, 1 (AMD-761 system controller).



Function 1, device 0 configuration space contains only the DDR Programmable Delay Line (PDL) registers. This space is enabled only when the appropriate bit is set in the PCI Control register (see “Dev0:F0:0x4C” on page 47). Accesses to the normal reserved PCI space of function 1 yields all 1s. Accesses to function 1 are ignored when function 1 is not enabled.



Device 0 accesses correspond to the host to PCI bridge registers defined in Section 2.4.3 on page 27.



Device 1 accesses correspond to the PCI-to-PCI bridge registers defined in Section 2.4.5 on page 117.



Access can be byte, word or DWord in length and must be naturally aligned.

Northbridges are required to create type 0 and type 1 accesses as follows:



If SysAdd[23:16] = 0 (Bus# = 2'h00), a type 0 config cycle is generated and PCI AD[1:0] = 2'b00. Device#, SysAdd[15:11] is decoded and asserted on PCI AD[31:11] for IDSEL.



If SysAdd[23:16] != 0 (Bus# != 2'h00), a type 1 config cycle is generated and PCI AD[1:0] = 2'b01. Bus# and Device# fields are passed onto the PCI directly with no decoding. PCI AD[31:24] = 2'h00.

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2.4.3 Device 0: PCI Configuration Registers

In Table 6, the column entitled Offset consists of the register number specified in the Configuration Address register bits [7:2] concatenated with 0b00 to form a simple 1-byte offset. Reserved configuration registers return 0 when read.

Table 6. Device 0, Function 0 Configuration Register Map

Host to PCI Bridge (Device 0, Function 0) Offset Reference

Device ID Vendor ID 0x00–0x03

Status Command 0x04–0x07

Class Code = 0x060000 Revision ID 0x08–0x0B

Reserved Header Type Latency Timer Reserved 0x0C–0x0F

BAR0 - AGP Virtual Address Space 0x10–0x13

BAR1 - GART Memory-Mapped Control Registers Pointer 0x14–0x17

Reserved 0x18–0x1B

Reserved 0x1C–0x33

Reserved

Reserved 0x38–0x43

Extended BIU Control 0x44–0x53

ECC Mode/Status 0x48–0x4B

Capabilities

Pointer: A0

0x34–0x37

“Dev0:F0:0x00”

on page 30

“Dev0:F0:0x04”

on page 32

“Dev0:F0:0x08”

on page 35

“Dev0:F0:0x0C”

on page 36

“Dev0:F0:0x10”

on page 37

“Dev0:F0:0x14”

on page 39

“Dev0:F0:0x34”

on page 41

“Dev0:F0:0x44”

on page 42

“Dev0:F0:0x48”

on page 44

PCI Control 0x4C–0x4F

AMD Athlon™ Processor System Bus Dynamic Compensation 0x50–0x53

DRAM Timing 0x54–0x57

DRAM Mode/Status 0x58–0x5B

Reserved 0x5C–0x5F

BIU0 Status/Control 0x60–0x63

BIU0 SIP 0x64–0x67

“Dev0:F0:0x4C”

on page 47

“Dev0:F0:0x50”

on page 49

“Dev0:F0:0x54”

on page 51

“Dev0:F0:0x58”

on page 56

“Dev0:F0:0x60”

on page 61

“Dev0:F0:0x64”

on page 64

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Table 6. Device 0, Function 0 Configuration Register Map (Continued)

Host to PCI Bridge (Device 0, Function 0) Offset Reference

Reserved

Memory Status/Control 0x70–0x73

Reserved 0x74–0x77

Reserved 0x78–0x7B

Reserved 0x7C–0x7F

Reserved Boot Proc WHAMI 0x80–0x83

PCI Arbitration Control 0x84–0x87

Configuration Status 0x88–0x8B

Reserved 0x8C–0x8F

Reserved 0x90–0x93

Reserved 0x94–0x97

Reserved 0x98–0x9B

0x68–0x6B

0x6C–0x6F

“Dev0:F0:0x70”

on page 66

“Dev0:F0:0x80”

on page 68

“Dev0:F0:0x84”

on page 70

“Dev0:F0:0x88”

on page 74

PCI Top of Memory Reserved 0x9C–0x9F

AGP Capability Identifier 0xA0–0xA3

AGP Status 0xA4–0xA7

AGP Command 0xA8–0xAB

AGP Virtual Address Space Size 0xAC–0xAF

GART/AGP Mode Control 0xB0–0xB3

AGP 4X Dynamic Compensation 0xB4–0xB7

AGP Compensation Bypass 0xB8–0xBF

Memory Base Address 0 0xC0–0xC3

Memory Base Address 1 0xC4–0xC7

“Dev0:F0:0x9C”

on page 77

“Dev0:F0:0xA0”

on page 79

“Dev0:F0:0xA4”

on page 80

“Dev0:F0:0xA8”

on page 82

“Dev0:F0:0xAC”

on page 84

“Dev0:F0:0xB0”

on page 86

“Dev0:F0:0xB4”

on page 88

“Dev0:F0:0xB8”

on page 91

“Dev0:F0:0xC0”

on page 95

“Dev0:F0:0xC4”

on page 95

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Table 6. Device 0, Function 0 Configuration Register Map (Continued)

Host to PCI Bridge (Device 0, Function 0) Offset Reference

Memory Base Address 2 0xC8–0xCB

Memory Base Address 3 0xCC–0xCF

Memory Base Address 4 0xD0–0xD3

Memory Base Address 5 0xD4–0xD7

Memory Base Address 6 0xD8–0xDB

Memory Base Address 7 0xDC–0xDF

Reserved 0xE0–0xFF

“Dev0:F0:0xC8”

on page 95

“Dev0:F0:0xCC”

on page 95

“Dev0:F0:0xD0”

on page 95

“Dev0:F0:0xD4”

on page 95

“Dev0:F0:0xD8”

on page 95

“Dev0:F0:0xDC”

on page 95

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PCI ID Dev0:F0:0x00

31 30 29 28 27 26 25 24

Bit Dev_ID

Reset01110000

R/W R

23 22 21 20 19 18 17 16

Bit Dev_ID

Reset00001110

R/W R

15 14 13 12 11 10 9 8

Bit Vend_ID

Reset00010000

R/W R

7 6 5 4 3 2 1 0

Bit Vend_ID

Reset00100010

R/W R

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Bit Definitions PCI ID (Dev0:F0:0x00)

Bit Name Function

31 —16 D ev _I D Device Identifier

This 16-bit field is assigned by the device manufacturer and identifies the type of device. The current Northbridge device ID assignments are:

AMD-761™ system controller — AMD Athlon™ processor, 1P DDR 133 MHz 0x700E host to PCI bridge 0x700F PCI-to-PCI bridge (4-X AGP)

AMD-762™ system controller — AMD Athlon processor, 2P DDR 133 MHz 0x700C host to PCI bridge 0x700D PCI-to-PCI bridge (4-X AGP)

AMD-751™ system controller — AMD Athlon processor, 1P SDRAM-100 0x7006 host to PCI bridge 0x7007 PCI-to-PCI bridge (1X/2X AGP)

15—0 Vend_ID Vendor Identifier

This 16-bit field identifies the manufacturer of the device.

Programming Notes

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PCI Command and Status Dev0:F0:0x04

31 30 29 28 27 26 25 24

Bit PERR_Rcv SERR_Sent Mas_ABRT Trgt_ABRT

Reset00000010

R/W R R/W1C R/W1C R/W1C R R R

23 22 21 20 19 18 17 16

Bit Fast_B2B UDF 66M Cap_Lst Reserved

Reset00010000

R/W R

15 14 13 12 11 10 9 8

Bit Reserved FBACK SERR

Reset00000000

R/W R R/W

7 6 5 4 3 2 1 0

Bit STEP PERR VGA MWINV SCYC MSTR MEM I/O

Reset00000100

R/W R R/W R

Trg t_ ABRT _ Signaled

DEVSEL_Timing Data_PERR

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Bit Definitions PCI Command and Status (Dev0:F0:0x04)

Bit Name Function

31 PERR _Rcv Detected Parity Error

This bit is always 0 because the AMD-761™ system controller does not support data parity checking.

30 SERR_Sent Signaled System Error

This bit is set whenever the AMD-761 system controller generates a system error and asserts the SERR# line (ECC, GART error). This bit is cleared by writing a 1. Refer to Table 7 on page 34 for details about SERR# assertion and status.

29 Mas_ ABRT Received Master Abort

This bit is set whenever a CPU to PCI transaction (except for a special cycle) is terminated due to a master abort. This bit is cleared by writing a 1.

28 Trgt_ABRT Received Target Abort

This bit is set whenever a CPU to PCI transaction (except for a special cycle) is terminated due to a target abort. This bit is cleared by writing a 1.

27 Trgt_ABRT_

Signaled

26—25 DEVSEL_Timing DEVSEL# Timing

24 Data_PERR Data Parity Error

23 Fast B2B Fast Back-to-Back Capable

22 UDF User-Definable Features

21 66M 66-MHz Capable

20 Cap_Lst Capabilities List

19–10 Reserved Reserved

Signaled Target Abort

This bit is always 0 because the AMD-761 system controller does not terminate transactions with target aborts.

This bit field defines the timing of DEVSEL# on the AMD-761 system controller. The AMD-761 system controller supports medium DEVSEL# timing.

This bit is always 0 because the AMD-761 system controller does not report parity errors.

This bit is always 0, indicating that the AMD-761 system controller as a target is not capable of accepting fast back-to-back transactions when the transactions are not to the same agent.

This bit is always 0, indicating that UDF is not supported on the AMD-761 system controller.

This bit is always 0, indicating that the AMD-761 system controller is not 66-MHz capable.

This bit is set to indicate that this device’s configuration space supports a capabilities list.

9FBACK Fast Back-to-Back to Different Devices Enable

This bit is always 0, because the AMD-761 system controller does not allow generation of fast back-to-back transactions to different agents.

8 SERR System Error Enable

0 = SERR# driver disabled

1 = SERR# driver enabled

Refer to Table 7 for details about SERR# assertion and status.

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Bit Definitions (Continued) PCI Command and Status (Dev0:F0:0x04)

Bit Name Function

7 STEP Address Stepping

This bit is always 0 because the AMD-761™ system controller does not perform address stepping.

6PERR Parity Error Response

This bit is always 0 because the AMD-761 system controller does not report data parity errors.

5VGA VGA Palette Snoop Enable

This bit is always 0, indicating that the AMD-761 system controller does not snoop the VGA palette address range.

4MWINV Memory Write and Invalidate Enable

This bit is always 0 because the AMD-761 system controller does not generate memory write and invalidate commands.

3SCYC Special Cycle

This bit is always 0 because the AMD-761 system controller ignores PCI special cycles.

2 MSTR Bus Master Enable

This bit is always set, indicating that the AMD-761 system controller is allowed to act as a bus master on the PCI bus.

1MEM Memory Access Enable

0 = PCI memory accesses ignored

1 = PCI memory accesses responded to

0I/O I/O Access Enable

This bit is always 0 because the AMD-761 system controller does not respond to I/O cycles on the PCI bus.

Programming Notes

Table 7 lists the controls required to enable the assertion of the AMD-761 SERR# pin and the various status bits that can be read to determine when the SERR# and A_SERR# pins have been asserted.

Table 7. AMD-761™ System Controller SERR# Assertion Control and Status Bits

SERR# Source

GART or ECC error

A_SERR# assertion on AGP interface forwarded to SERR# pin

SERR# Pin

Assertion Control

Enabled by bit 8, Dev 0:F0:0x04, PCI Status/Command register.

Enabled by bit 8, Dev 1:F0:0x04, PCI Status/Command register, and bit 17, Dev 1:F0:0x3C, AGP/PCI Interrupt and Bridge Control.

Read bit 30, Dev 0:F0:0x04, PCI Status/Command register.

Read bit 30, Dev 1:F0:0x1C, AGP/PCI Status, I/O and Base Limit, and bit 30, Dev 1:F0:0x04, AGP/PCI Command/Status.

Signalled System

Error Status Bit

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PCI Revision ID and Class Code Dev0:F0:0x08

31 30 29 28 27 26 25 24

Bit Class_Code

Reset00000110

R/W R

23 22 21 20 19 18 17 16

Bit Sub-Class_Code

Reset00000000

R/W R

15 14 13 12 11 10 9 8

Bit Prog_I/F

Reset00000000

R/W R

7 6 5 4 3 2 1 0

Bit Rev_ID

Reset00010000

R/W R

(See Programming Notes below.)

Bit Definitions PCI Revision ID and Class Code (Dev0:F0:0x08)

Bit Name Function

31–24 Class_Code Class Code

Indicates a bridge device.

23–16 Sub-

Class_Code

Sub-Class Code

Indicates a Host/PCI bridge.

15–8 Prog_I/F Program Interface

Indicates a Host/PCI bridge.

7–0 Rev_ID Revision Identification

Identifies revision number of the device.

Programming Notes

Refer to the AMD-761™ System Controller Revision Guide, order# 23613, for details of the Rev_ID field for each silicon revision.

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PCI Latency Timer and Header Type Dev0:F0:0x0C

31 30 29 28 27 26 25 24

Bit Reserved

Reset00000000

R/W R

23 22 21 20 19 18 17 16

Bit Header_Type

Reset00000000

R/W R

15 14 13 12 11 10 9 8

Bit Lat_Timer

Reset00000000

R/W R/W

7 6 5 4 3 2 1 0

Bit Reserved

Reset00000000

R/W R

Bit Definitions PCI Latency Timer and Header type (Dev0:F0:0x0C)

Bit Name Function

31–24 Reserved Reserved 23–16 Header_Type Header Type

Bit 23 is always 0, indicating that the AMD-761™ system controller is a single function device. Bits [22:16] are 0, indicating that Type 00 configuration space header format is supported.

15–8 Lat_Timer Latency Timer

This bit field defines the minimum amount of time in PCI clock cycles that the bus master can retain ownership of the bus. This action is mandatory for masters that are capable of performing a burst consisting of more than two data phases.

7–0 Reserved Reserved

Programming Notes

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Base Address 0: AGP Virtual Address Space Dev0:F0:0x10

31 30 29 28 27 26 25 24

Bit Base_Addr_High

Reset00000000

R/W R/W R

23 22 21 20 19 18 17 16

Bit Base_Addr_Low

Reset00000000

R/W R

15 14 13 12 11 10 9 8

Bit Base_Addr_Low

Reset00000000

R/W R

7 6 5 4 3 2 1 0

Bit Base_Addr_Low Prefetchable Type Memory

Reset00001000

R/W R

Base-

Addr_Low

This register is used by system BIOS memory mapping software to allocate virtual address space for AGP.

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Bit Definitions Base Address 0: AGP Virtual Address Space (Dev0:F0:0x10)

Bit Name Function

31–25 Base_Addr_High Base Address High

This bit field forms the upper part of BAR0. This field is loaded by BIOS software. Note that when the GART enable bit in the AGP Virtual Address Space Size register is 0 (see “Dev0:F0:0xAC” on page 84), these bits always return 0s to indicate no address space should be allocated to AGP. Note that a write to this register must occur before a read returns 0s with the GART enable bit cleared.

This bit field corresponds to bits [3:1] of the AGP Virtual Address Space Size register. When bits [3:1] of that register are set, the R/W attributes in bits [30:25] in this register are automatically set. BIOS software writes all 1s to this BAR register and then reads back the register to determine how much memory is required for AGP as follows:

31 30 29 28 27 26 25 Memory

RW RW RW RW RW RW RW 32 Mbytes

RW RW RW RW RW RW R 64 Mbytes

RW RW RW RW RW R R 128 Mbytes

RW RW RW RW R R R 256 Mbytes

RW RW RW R R R R 512 Mbytes

RWRWRRRRR1 Gbyte

RWRRRRRR2 Gbytes

24–4 Base_Addr_Low Base Address Low

This bit field is hardwired to return 0s to indicate that the minimum allocated memory size is 32 Mbytes.

3 Prefetchable Prefetchable

This bit is hardwired to 1 to indicate that this range is prefetchable.

2–1 Type Type

This bit field is hardwired to indicate that this base register is 32 bits wide and mapping can be performed anywhere in the 32-bit address space.

0Memory Memory

This bit is hardwired to 0 to indicate that this base address register maps into memory space.

Programming Notes

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Base Address 1: GART Memory-Mapped Register Base Dev0:F0:0x14

31 30 29 28 27 26 25 24

Bit Base_Addr_High

Reset00000000

R/W R/W

23 22 21 20 19 18 17 16

Bit Base_Addr_High

Reset00000000

R/W R/W

15 14 13 12 11 10 9 8

Bit Base_Addr_High Base_Addr_Low

Reset00000000

R/W R/W R

7 6 5 4 3 2 1 0

Bit Base_Addr_Low Prefetchable Type Memory

Reset00001000

R/W R

This register provides the base address for the GART memory-mapped configuration register space (see “MemoryMapped Register Map” on page 140 for details).

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Bit Definitions Base Address 1: GART Memory-Mapped Register Base (Dev0:F0:0x14)

Bit Name Function

31–12 Base_Addr_High Base Address High

This bit field forms the upper part of BAR1. This field is loaded by BIOS software.

11–4 Base_Addr_Low Base Address Low

This bit field is hardwired to return 0s to indicate that 4 Kbytes are allocated to GART memory-mapped control registers and that the registers always reside in a 4-Kbyte boundary per PCI Local Bus Specification, Revision 2.2.

3 Prefetchable Prefetchable

This bit is hardwired to 1 to indicate that this range is prefetchable

2–1 Type Type

This bit field is hardwired to indicate that this base register is 32 bits wide and mapping can be performed anywhere in the 32-bit address space.

0Memory Memory

This bit is hardwired to 0 to indicate that this base address register maps into memory space.

Programming Notes

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AGP/PCI Capabilities Pointer Dev0:F0:0x34

31 30 29 28 27 26 25 24

Bit Reserved

Reset00000000

R/W R

23 22 21 20 19 18 17 16

Bit Reserved

Reset00000000

R/W R

15 14 13 12 11 10 9 8

Bit Reserved

Reset00000000

R/W R

7 6 5 4 3 2 1 0

Bit CAP_PTR

Reset10100000

R/W R

Bit Definitions AGP/PCI Capabilities Pointer (Dev0:0x34)

Bit Name Function

31–8 Reser ve d Reserved

7–0 CAP_PTR Capabilities Pointer

This field contains a byte offset into a device’s configuration space containing the first item in the capabilities list. The first item in the capabilities list is the AGP function.

Note that when the AGP valid bit in the PCI-to-PCI bridge virtual address space register is set to invalid, this capabilities pointer is set by the chipset to point to the next item in the linked list. If no next item exists, then it is set to null.

Programming Notes

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Extended BIU Control Dev0:F0:0x44

31 30 29 28 27 26 25 24

Bit Reserved

Reset00000000

R/W R

23 22 21 20 19 18 17 16

Bit Reserved Reserved

Reset00000000

R/W R

15 14 13 12 11 10 9 8

Bit Reserved Reserved P0_WrDataDly

Reset 0 0 0 SIP Stream

R/W R

7 6 5 4 3 2 1 0

Bit Reserved Reserved Reserved Reserved P0_2BitPF

Reset00000000

R/W R R R R/W R

This register provides controls for the processor interface, in addition to the BIU Control register at Dev 0:F0:0x60 for Processor 0.

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Bit Definitions Extended BIU Control (Dev0:F0:0x44)

Bit Name Function

31–11 Reserved Reserved

15–14 Reserved Reserved

10–8 P0_WrDataDly Write Data Delay

P0_WrDataDly is the time in SYSCLK periods from the launch of a SysDC WriteData command until the launch of the first data object by the processor. This value is a calculated part of the SIP stream. This value is not provided in the BIU SIP register and is thus provided here.

7-4 Reserved Reserved

3 P0_2BitPF Two Bit Times Per Frame Enable

This bit enables the use of the two bit time commands on the AMD Athlon™ processor system bus. This bit must be set when connected to an AMD Athlon processor and disabled when connected to an Alpha processor. For proper operation, BIOS must not clear this bit once it has been set.

0 = Two-bit time commands disabled

1 = Two-bit time commands enabled (AMD Athlon processor only)

2–0 Reserved Reserved

These bits must be written with 0 (cleared) for normal operation.

Programming Notes

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ECC Mode/Status Dev0:F0:0x48

31 30 29 28 27 26 25 24

Bit Reserved

Reset00000000

R/W R

23 22 21 20 19 18 17 16

Bit Reserved

Reset00000000

R/W R

15 14 13 12 11 10 9 8

Bit SERR_Enable Reserved ECC_Diag ECC_Mode ECC_Status

ResetXX0XXX00

R/W R/W R R/W R/W R/W1C

7 6 5 4 3 2 1 0

Bit ECC_CS_MED ECC_CS_SED

Reset00000000

R/W R R

This register provides ECC mode control and status reporting for the DRAM system.

Note that some bits of this register are not initialized at reset time, and all bits must be initialized by BIOS for proper operation. This action should be done prior to attempting DRAM access.

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Bit Definitions ECC Mode/Status (Dev0:F0:0x48)

Bit Name Function

31–16 Reserved Reserved

15-14 SERR_Enable System Error Enable

These bits control the AMD-761™ system controller’s reporting of ECC errors to the system via the SERR# pin on the PCI bus. Note that SERR# assertion is still subject to the normal PCI SERR# enable (bit 8 in Dev 0:F0:0x04). Refer to Table 7 on page 34 for details about SERR# assertion and status.

00 = SERR# assertion is disabled.

X1 = Multiple bit errors force SERR# assertion.

1X = Single bit errors force SERR# assertion.

13 Res erved Reserved

12 ECC_Diag Error Correcting Code Diagnostic Mode Enable

0 = ECC diagnostic mode disabled

1 = ECC diagnostic mode enabled

When the ECC diagnostic mode is enabled, the AMD-761 system controller always writes 0x00 to the ECC byte to aid testing of the ECC logic. During partial writes, the RMW sequence still occurs, but the ECC bits are always written to 0x00.

For reads, the ECC circuitry is unaffected by the ECC_Diag bit. The ECC code returned from memory is checked, and errors are reported in the ECC_Status bits as usual. Correction is not performed in this mode.

11–10 ECC_Mode Error Correcting Code Mode

00 = ECC disabled, no error detection or correction is performed.

01 = EC_HiPerf mode enabled. Error checking and status reporting is enabled. Data

destined for the PCI/AGP and memory (RMR) is not corrected.

10 = ECC_HiPerf mode enabled. Error checking and status reporting is enabled. Data

destined for the PCI/AGP and memory (RMR) is corrected.

11 = ECC_Scrub mode enabled. Error checking and status reporting is enabled. Data

destined for the PCI/AGP and memory (RMR) is corrected. The memory contents are corrected (scrubbed) after all reads with errors.

9–8 ECC_Status Error Correcting Code Status

This bit field indicates the status of the ECC detect logic as follows: 00 = No error

X1 = MED: multi-bit error detect

1X = SED: single-bit error detect

The ECC status bits and corresponding failing chip-select indicators are set by the first error detected of each type (SED or MED). The AMD-761 system controller does not log any new errors of each type or assert SERR# until software clears the associated ECC_Status bit by writing a 1.

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Bit Definitions (Continued) ECC Mode/Status (Dev0:F0:0x48)

Bit Name Function

7–4 ECC_CS_MED Multiple Bit Error Chip Select

These bits provide the binary encoded chip select for the first multiple-bit error detected by the AMD-761™ system controller.

3–0 ECC_CS_SED Single Bit Error Chip Select

These bits provide the binary encoded chip select for the first single-bit error detected by the AMD-761 system controller.

Programming Notes

System software is responsible for decoding the binary encoded, failing chip-select information and identifying a corresponding physical DIMM location.

Some bits in this register are not initialized at reset. BIOS must initialize all bits in this register prior to attempting DRAM access.

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PCI Control Dev0:F0:0x4C

31 30 29 28 27 26 25 24

Bit Reserved

Reset00000000

R/W R

23 22 21 20 19 18 17 16

Bit Reserved

Reset00000000

R/W R

15 14 13 12 11 10 9 8

Bit Reserved Reserved Reserved Reserved

Reset00000000

R/W R R R R

7 6 5 4 3 2 1 0

Bit Reserved Reserved Reserved

Reset00000000

R/W R R R/W R/W R/W R/W

WSC_DIR

(See Note.)

PCI_DT_En PCI_OR_En Func1_En

This register controls various functions in the primary PCI and AGP interfaces.

Note: The WSC_DIR configuration bit is implemented only in Revision B4 silicon and above. This bit is reserved and must be cleared in all previous silicon revisions.

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Bit Definitions PCI Control (Dev0:F0:0x4C)

Bit Name Function

31—4 Res erve d Reserved

3WSC_DIR Write Snoop Complete Direction Control

This bit controls the direction and function of the Write Snoop Complete (WSC#) pin. Refer to the AMD-761™ System Controller Datasheet, order# 24088, for a full description of the WSC# pin.

0 = Bidirectional mode for use with Southbridges that drive WSC# as an output and

sample WSC# as an input (such as the AMD-766™ peripheral bus controller). In this mode, the WSC# pin of the AMD-761 system controller defaults as an input and is driven by the Northbridge only after the pin is first asserted by the Southbridge.

1 = Unidirectional mode for use with Southbridges that only sample WSC# as an input.

In this mode, the WSC# pin is always driven by the AMD-761 system controller.

Note: This bit is implemented only in silicon revision B4 and above. It is reserved in all previous silicon revisions and must be cleared.

2 PCI_DT_En Delayed Transactions Enable (PCI)

0 = Delayed transactions disabled on the PCI interface

1 = Delayed transactions enabled on the PCI interface

1PCI_OR_En Ordering Rules Compliance Enable (PCI)

This bit controls how the AMD-761 system controller PCI bus interface orders transactions. 0 = PCI ordering rules compliance disabled

1 = PCI ordering rules compliance enabled

Programming Notes

If the target latency bit is set (bit 23 of Dev 0:F0:0x84), then the delayed transactions enable (bit 2) must be set when the front-side bus is clocked at 66 MHz.

When enabling PCI ordering rules compliance, it is recommended that delayed transactions be enabled simultaneously for optimal performance.

Refer to See Chapter 5, “PCI Bus Interface” on page 195 for more information on the transaction options in the AMD-761 system controller. Refer to See Chapter 7, “Recommended BIOS Settings” on page 211 for the recommended bit settings for these bits.

Func1_En

Function 1 Enable

This bit controls access to device 0, function 1 configuration space (DDR PDL registers). Refer to “Device 0, Function 1: DDR PDL Configuration Registers” on page 97 for more information on the function 1 registers.

0 = Device 0, function 1 disabled

1 = Device 0, function 1 enabled

Note that the WSC_DIR pin is implemented only in silicon revisions B4 and above and must be treated as Reserved (write a 0) in all other silicon revisions.

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AMD Athlon™ Processor System Bus Dynamic Compensation Dev0:F0:0x50

31 30 29 28 27 26 25 24

Bit Reserved

Reset00000000

R/W R

23 22 21 20 19 18 17 16

Bit PVal NVal

Reset00000000

R/W R

15 14 13 12 11 10 9 8

Bit BYP_P BYP_N

Reset00000000

R/W R/W

7 6 5 4 3 2 1 0

Bit SlewCntl BYP Reserved

Reset01100000

R/W R/W R/W R

Note that the default value of the BYP, BYP_P, and BYP_N fields of this register can be optionally controlled by SIP bits when loading the SIP stream from external ROM.

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Bit Definitions AMD Athlon™ System Bus Dynamic Compensation (Dev0:F0:0x50)

Bit Name Function

31–24 Reserved Reserved

23–20 Pval P Transistor Strength Value

This field reflects the P transistor strength value that was automatically written to the AMD Athlon™ processor system bus I/O pads by the auto-compensation circuit. In bypass mode (bit 4=1) this field returns the values in the BYP_P field (bits [15:12]). The P values are active Low.

19–16 NVal N Transistor Strength Value

This field reflects the N transistor strength value that was automatically written to the AMD Athlon processor system bus I/O pads by the auto-compensation circuit. In bypass mode (bit 4=1) this field returns the values in the BYP_N field (bits [11:8]). The N values are active High.

15–12 BYP_P Bypass Values P Driver

Bypass strength values for the P driver. The P values are active Low. A value of 0 on bit 3 for instance signifies that (2^3 + 1) or 9 legs of the P driver are active.

11–8 BYP_N Bypass Values N Driver

Bypass strength values for the N driver. The N values are active High. A value of 1 on bit 3, for instance signifies that (2^3 + 1) or 9 legs of the N driver are active.

7–5 SlewCntl Slew Rate Control

Slew rate control for AMD Athlon processor system bus. 000 = Slew rate 0 (slowest)

001 = Slew rate 1

010 = Sl e w rate 2

011 = Slew rate 3 (default)

100 = Slew rate 4

101= Sl e w rate 5

110 = Sl e w rate 6

111 = Slew rate 7 (fastest)

4BYP Bypass

Setting the bypass bit allows an external drive strength setting to be provided in the BYP_P and BYP_N fields. Clearing this bit causes the drive strength to be provided by the compensation circuit.

3-0 Reserved Reserved

Programming Notes

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DRAM Timing Dev0:F0:0x54

31 30 29 28 27 26 25 24

Bit SBPWaitState AddrTiming_A AddrTiming_B RD_Wait_State Reg_DIMM_En

ResetXXXXXXXX

R/W R/W

23 22 21 20 19 18 17 16

Bit

ResetX0000XXX

R/W R/W R R/W

Bit PH_Limit Reserved t

ResetXX00XXXX

R/W R/W R R/W

Bit t

ResetXXXXXXXX

R/W R/W

RRD

15 14 13 12 11 10 9 8

7 6 5 4 3 2 1 0

Reserved Idle_Cyc_Limit

RAS

WTR

RCD

This register defines the DRAM timing parameters for all banks. BIOS software must set appropriate values in this register before setting the SDRAM_Init bit (See “Bit Definitions DRAM Mode/Status (Dev0:F0:0x58)” on page 57) or attempting any DRAM accesses.

Note that this register is not initialized at reset time, and all bits must be initialized by BIOS for proper operation. This action should be done prior to attempting DRAM access.

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Bit Definitions DRAM Timing (Dev0:F0:0x54)

Bit Name Function

31 SBP_Wait_State Super Bypass Wait State

This bit forces a wait state on all super bypass reads. This bit should be set when the bus speed is 133 MHz (refer to Table 8 on page 55).

0 = No additional wait state on super bypass reads 1 = Add wait state on super bypass reads

30 AddrTiming_A Address Timing for Copy-A

This bit determines whether an extra delay is added to the address and command buses (MAA[14:0], RASA#, CASA#; WEA#, CKEA, CS[5:4, 1:0]#). This bit should be programmed depending on the loading presented to these pins.

0 = No extra delay

1 = XX ps delay

29 AddrTiming_B Address Timing for Copy-B

This bit determines whether an extra delay is added to the address and command buses (MAB[14:0], RASB#, CASB#; WEB#, CKEB, CS[7:6, 3:2]#). This bit should be programmed depending on the loading presented to these pins.

0 = No extra delay

1 = XX ps delay

28 RD_Wait_State Read Wait State

This bit determines whether a wait state must be added before returning the read data from the memory to the requester. This bit should be programmed depending on the overall round-trip timing.

Note that this bit must be set for 100-MHz and 133-MHz operation, but it must not be set for 66-MHz operation (refer to Table 8).

0 = No wait states

1 = One wait state

27 Reg_DIMM_En Registered DIMM Enable

This bit enables the use of registered DIMMs on the motherboard.

AMD-761™ system controller 0 = Unbuffered DIMMs

1 = Registered DIMMs

26 t

WTR

Write Data In to Read Command Delay

This bit controls the number of clock cycles that must occur between the last valid write operation and the next read command.

0 = t

1 = t

duration is 1 clock cycle.

WTR

duration is 2 clock cycles.

WTR

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Bit Definitions (Continued) DRAM Timing (Dev0:F0:0x54)

Bit Name Function

25-24 t

Write Recovery Time

This bit field controls the number of clock cycles that must occur from the last valid write operation to the earliest time a new precharge command can be asserted to the same bank.

00 = t

duration is 1 clock cycle.

01 = Re served

23 t

RRD

10 = t

11 = t

Activate Bank A to Activate Bank B Command Delay

duration is 2 clock cycles.

duration is 3 clock cycles.

This bit controls the number of clock cycles between successive activate commands to different banks.

0 = t

1 = t

duration is 2 clock cycles.

RRD

duration is 3 clock cycles.

RRD

22-19 Reserved Reserved

18–16 Idle_Cyc_Limit Idle Cycle Limit

This bit field controls the number of idle cycles to wait before precharging an idle bank. Idle cycles are defined as cycles in which no valid requests are asserted.

111 = Disable idle precharge 110 = 48 c ycles 101 = 32 c y cles 100 = 24 cycles 011 = 16 cyc l es 010 = 12 cyc l es 001 = 8 cycles (recommended “safe” configuration) 000 = 0 cycles

15–14 PH_Limit Page Hit Limit

This bit field controls the number of consecutive page hit requests to allow before choosing a non-PH request.

00 = 1 cycle 01 = 4 c yc le 10 = 8 cycles (recommended “safe” configuration) 11 = 16 c ycles

13–12 Reserved Reserved

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Bit Definitions (Continued) DRAM Timing (Dev0:F0:0x54)

Bit Name Function

11–9 t

8–7 t

6–4 t

RAS

This bit field indicates the tRC timing value (bank cycle time: minimum time from activate to activate of same bank).

111 = 10 cyc l es 110 = 9 c ycles 101 = 8 cycles (recommended “safe” configuration) 100 = 7 cycles 011 = 6 c ycles 010 = 5 c ycles 001 = 4 cycles 000 = 3 cycles

This bit field indicates the tRP timing value (precharge time: time from precharge to activate on the same bank).

00 = 3 cycles (recommended “safe” configuration) 01 = 2 c yc les 10 = 1 c yc les 11 = 4 c yc les

RAS

This bit field indicates the t

timing value (minimum bank active time: time from activate

RAS

to precharge of same bank). 111 = 9 c ycles 110 = 8 c ycles 101 = 7 cycles (recommended “safe” configuration) 100 = 6 cycles 011 = 5 c ycles 010 = 4 c ycles 001 = 3 cycles 000 = 2 cycles

3–2 t

CAS Latency of SDRAM

11 = Re served 10 = 2.5 cycles 01 = 2 cycles (recommended “safe” configuration) 00 = 3 cycles

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Bit Definitions (Continued) DRAM Timing (Dev0:F0:0x54)

Bit Name Function

1–0 t

RCD

This bit field (t

) is the timing value (RAS to CAS latency, delay from activate to RD/WR

RCD

command). 11 = 4 c yc les 10 = 3 cycles (recommended “safe” configuration) 01 = 2 c yc les 00 = 1 cycle

Programming Notes

This register is not initialized at reset. BIOS must initialize all bits in this register prior to setting the SDRAM_Init bit (See “Bit Definitions DRAM Mode/Status (Dev0:F0:0x58)” on page 57) or attempting DRAM access for correct operation.

The required settings for the wait state bits for SBP_Wait_State and Rd_Wait_State are listed in Table 8.

Table 8. Wait State Settings for DRAM Timing Register

DDR Interface

Frequency SBP_Wait_State [Bit 31] Rd_Wait_State [Bit 28]

66 MHz 0 0

100 MHz 0 1

133 MHz 1 1

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DRAM Mode/Status Dev0:F0:0x58

31 30 29 28 27 26 25 24

Bit Clk_Dis5 Clk_Dis4 Clk_Dis3 Clk_Dis2 Clk_Dis1 Clk_Dis0 SDRAM_Init Reserved

Reset00000000

R/W R/W R/W1S R

23 22 21 20 19 18 17 16

Mode_Reg

Bit

Reset000XXXXX

R/W R/W1S R/W

Bit Reserved

_ Status

15 14 13 12 11 10 9 8

STR_Control Burst_Ref_En Ref_Dis Cyc_Per_Ref

Reset00000000

R/W R

7 6 5 4 3 2 1 0

Bit CS7_X4Mode CS6_X4Mode CS5_X4Mode CS4_X4Mode CS3_X4Mode CS2_X4Mode CS1_X4Mode CS0_X4Mode

ResetXXXXXXXX

R/W R/W R/W R/W R/W R/W R/W R/W R/W

This register provides general mode control and status reporting of the DRAM system.

Note that some bits of this register are not initialized at reset time, and all bits must be initialized by BIOS for proper operation. This action should be done prior to attempting DRAM access.

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Bit Definitions DRAM Mode/Status (Dev0:F0:0x58)

Bit Name Function

31 Clk _Dis 5 Clock Disable

This bit controls the DDR CLKOUT5/CLKOUT5# differential clock pair: 0 = Clock pair enabled

1 = Clock pair disabled (three-stated)

Note: This bit is meant to disable the clock pair when it is not connected to anything.

This bit should not be used for memory sizing or power management uses.

30 Clk_Dis4 Clock Disable

This bit controls the DDR CLKOUT4/CLKOUT4# differential clock pair. 0 = Clock pair enabled 1 = Clock pair disabled (three-stated)

Note: This bit is meant to disable the clock pair when it is not connected to anything.

This bit should not be used for memory sizing or power management uses.

29 Clk_Dis3 Clock Disable

This bit controls the DDR CLKOUT3/CLKOUT3# differential clock pair. 0 = Clock pair enabled 1 = Clock pair disabled (three-stated)

Note: This bit is meant to disable the clock pair when it is not connected to anything.

This bit should not be used for memory sizing or power management uses.

28 Clk_Dis2 Clock Disable

This bit controls the DDR CLKOUT2/CLKOUT2# differential clock pair. 0 = Clock pair enabled 1 = Clock pair disabled (three-stated)

Note: This bit is meant to disable the clock pair when it is not connected to anything.

This bit should not be used for memory sizing or power management uses.

27 Clk_Dis1 Clock Disable

This bit controls the DDR CLKOUT1/CLKOUT1# differential clock pair. 0 = Clock pair enabled 1 = Clock pair disabled (three-stated)

Note: This bit is meant to disable the clock pair when it is not connected to anything.

This bit should not be used for memory sizing or power management uses.

26 Clk_Dis0 Clock Disable

This bit controls the DDR CLKOUT0/CLKOUT0# differential clock pair. 0 = Clock pair enabled 1 = Clock pair disabled (three-stated)

Note: This bit is meant to disable the clock pair when it is not connected to anything.

This bit should not be used for memory sizing or power management uses.

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Bit Definitions (Continued) DRAM Mode/Status (Dev0:F0:0x58)

Bit Name Function

25 SDRAM_Init SDRAM Initialization

This bit is used by the BIOS to tell the SDRAM controller to start the SDRAM initialization sequence. Once set, this bit cannot be reset. The BIOS should first program the SDRAM timing registers and set the output buffer drive strength. After that, it should set this bit.

24 Reserved Reserved

23 Mode_Reg_Status Mode Register Status

0 = Off/done

1 = Set

When clear, the Mode register write is disabled and/or Mode register write done. When set, the Mode register write is enabled. Configuration bits t asserted. BIOS software sets this bit for write to the SDRAM Mode register. The memory controller clears this bit when it has issued the Mode register write to the SDRAM.

22–21 STR_Control Suspend to RAM Control

These bits are used to allow the BIOS to communicate the power-up sequence to the AMD-761™ system controller memory controller and power management logic, as follows:

00 = Default. These bits are cleared to this state any time the RESET# pin is asserted.

The AMD-761 memory controller always drives the CKE pins inactive (Low) while these bits are Low.

01 = BIOS sets this pattern after the system resumes from S4 (suspend to disk), S5 (soft

off), or mechanical off states. This action causes the AMD-761 memory controller to assert the CKE pins and follow the normal sequence for DDR DRAM initialization after power-on.

1X = BIOS sets this pattern when the system is resuming from the S3 (suspend to RAM)

state. This action causes the AMD-761 memory controller to exit self-refresh while preserving all memory data.

must be set before this bit is

20 Burst_Ref_En Burst Refresh Enable

0 = AMD-761 system controller does not burst refreshes.

1 = AMD-761 system controller queues up to four refreshes before issuing.

Refreshes are only queued during long sequences of operations to the same memory device.

19 Ref _Dis Refresh Disable

This bit is provided for system debug, and should be cleared for normal operation. 0 = Refresh enabled (normal operation)

1 = Refresh disabled (debug only)

18 Reserved

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Bit Definitions (Continued) DRAM Mode/Status (Dev0:F0:0x58)

Bit Name Function

17—16 Cyc_Per_Ref Cycles Per Refresh

Refresh counter defines period of refresh requests. The following table shows the relationship between the values in this field and the

resultant refresh period for the different system clock frequencies:

Value 66 MHz 100 MHz 133 MHz

00 30.72 µs 20.48 µs 15.36 µs

01 23.04 µs15.36 µs11.52 µs

10 15 .3 6 µs10.24 µs 7.68 µs

11 7.68 µs 7.68 µs 3.84 µs

15–8 Reserved Reserved

7 CS7_X4Mode Chip-Select 7 X4Mode Enable

0 = This chip select consists of non-x4 devices (disabled).

1 = This chip select consists of x4 devices (enabled).

6 CS6_X4Mode Chip-Select 6 X4Mode Enable

0 = This chip select consists of non-x4 devices (disabled).

1 = This chip select consists of x4 devices (enabled).

5 CS5_X4Mode Chip-Select 5 X4Mode Enable

0 = This chip select consists of non-x4 devices (disabled).

1 = This chip select consists of x4 devices (enabled).

4 CS4_X4Mode Chip-Select 4 X4Mode Enable

0 = This chip select consists of non-x4 devices (disabled).

1 = This chip select consists of x4 devices (enabled).

3 CS3_X4Mode Chip-Select 3 X4Mode Enable

0 = This chip select consists of non-x4 devices (disabled).

1 = This chip select consists of x4 devices (enabled).

2 CS2_X4Mode Chip-Select 2 X4Mode Enable

0 = This chip select consists of non-x4 devices (disabled).

1 = This chip select consists of x4 devices (enabled).

1 CS1_X4Mode Chip-Select 1 X4Mode Enable

0 = This chip select consists of non-x4 devices (disabled).

1 = This chip select consists of x4 devices (enabled).

0 CS0_X4Mode Chip-Select 0 X4Mode Enable

0 = This chip select consists of non-x4 devices (disabled).

1 = This chip select consists of x4 devices (enabled).

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Programming Notes

Note that some bits of this register are not initialized at reset time, and all bits must be initialized by BIOS for proper operation. This action should be done prior to attempting DRAM access.

The Clk_Dis bits are cleared by RESET#, and therefore all DDR DRAM interface clock pairs are enabled when exiting the Advanced Configuration and Power Interface (ACPI) S3 sleep state (suspend to RAM). BIOS should disable any clock pairs that are connected to unpopulated DIMM slots upon exit of S3.

When a chip select is programmed to operate in x4 DIMM mode, the DM[8:0] pins become DQS pins for that chip select. The pad configuration for the DM[8:0] pins is automatically controlled by the DQS_Drive field (Dev 0:F0:0x40) instead of the MDAT_Drive field, when any chip select is configured for x4 DIMM mode.

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BIU0 Status/Control Dev0:F0:0x60

31 30 29 28 27 26 25 24

Bit Prb_En Reserved Reserved Reserved Xca_Prb_Cnt Xca_RD_Cnt

Reset00000000

R/W R/W

23 22 21 20 19 18 17 16

Bit Xca_RD_Cnt Xca_WR_Cnt Halt_Discon

_En

Reset00000000

R/W R/W

15 14 13 12 11 10 9 8

Bit Prb_Limit Ack_Limit Bypass_En

Reset0000110Pinstrapping

R/W R/W R R/W R

7 6 5 4 3 2 1 0

SysDC_Out

Bit

Reset Pinstrapping

R/W R

_Dly

SysDC_In_Dly WR2_RD RD2_WR

Stp_Grant

_Discon_En

Prb_Limit

SysDC_Out

_Dly

This register provides general status and control for the AMD Athlon™ processor system bus interface.

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Bit Definitions BIU0 Status/Control (Dev0:F0:0x60)

Bit Name Function

31 Prb _En Probe Enable

0 = Probes are not sent to this processor.

1 = Probes are sent to this processor. 30 Reserved This bit must be programmed to zero for normal operation. 29 Reserved This bit must be programmed to zero for normal operation. 28 Reserved This bit must be programmed to zero for normal operation.

27–25 Xca_Prb_Cnt Xca Probe Count

This bit field represents the maximum number of consecutive AMD Athlon™ processor

system bus grants for probe data movement types that are allowed before letting another

type have the bus.BIOS must program this field to a non-zero value for proper operation.

The recommended value to be loaded in this field by BIOS software is 0x2.

24–22 Xca_RD_Cnt Xca Read Count

This bit field represents the maximum number of consecutive AMD Athlon processor

system bus grants for read data movement types that are allowed before letting another

type have the bus.BIOS must program this field to a non-zero value for proper operation.

The recommended value to be loaded in this field by BIOS software is 0x6.

21–19 Xca_WR_Cnt Xca Write Count

This bit field represents the maximum number of consecutive AMD Athlon processor

system bus grants for write data movement types that are allowed before letting another

type have the bus.BIOS must program this field to a non-zero value for proper operation.

The recommended value to be loaded in this field by BIOS software is 0x6. 18 Halt_Discon_En Halt Disconnect Enable

0 = No AMD Athlon system bus disconnect is performed following HALT.

1 = AMD Athlon system bus disconnects after receiving a HALT special cycle. 17 Stp_Grant_

Discon_En

16–14 Prb_Limit Probe Limit

13–10 Ack_Limit Ack Limit

Stop Grant Disconnect Enable

0 = No AMD Athlon processor system bus disconnect is performed following STOP/GRANT.

1 = AMD Athlon processor system bus disconnects after receiving a STOP/GRANT special cycle.

BIOS software initializes this field with the maximum number of outstanding probes that

the given CPU can handle. The default is a single probe. Encoding is as follows:

0b000 = 1 probe

0b001 = 2 probes

................................

0b111 = 8 probes

BIOS software reads this field to determine how many outstanding unacknowledged

AMD Athlon processor system bus commands can be sent to the AMD-761™ system

controller. The AMD-761 system controller allows a maximum of four unacknowledged

commands. Encoding is as follows:

0b0000 = 1 unacknowledged command

0b0001 = 2 unacknowledged commands

..........................................................

0b1111 = 16 unacknowledged commands

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Bit Definitions (Continued) BIU0 Status/Control (Dev0:F0:0x60)

Bit Name Function

9 Bypass_En Bypass Enable

When set, the AMD-761™ system controller internally bypasses certain memory pipe

stages for optimal performance. This bit may be set only if both of the following are true:

1. System is single processor or it is two processors and only CPU0 is present, and

2. CPU clock multiplier is 4 or greater. See “Config Status” on page 74 to determine the clock multiplier (FID).

8–7 SysDC_Out_Dly SysDC Out Delay

This bit field specifies the number of SysClk cycles from a return of read data type SysDC command and the start of the corresponding data.

0b00 = Reserved

0b01 = 1 clock

0b10 = 2 clocks

0b11 = 3 clocks

This field is initialized by pinstrapping during reset.

6–3 SysDC_In_Dly SysDC In Delay

This bit field specifies the number of SysClk cycles from a write data type SysDC command and the start of the corresponding data.

0b0000 = 1 clock

0b0001 = 2 clocks

.............................

0b1111 = 16 clocks

This field is initialized by pinstrapping during reset.

2WR2_RD WR2 Read

This field defines the number of SysClk cycles that are inserted between write data and read data cycles to allow the AMD Athlon™ processor system bus data wires to turn around. This field is initialized by pinstrapping during reset.

1–0 RD2_WR RD2 Write

This field defines the number of SysClk cycles that are inserted between read data and write data cycles to allow the AMD Athlon processor system bus data wires to turn around. This field is initialized by pinstrapping during reset.

Programming Notes

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BIU0 SIP Dev0:F0:0x64

31 30 29 28 27 26 25 24

Bit Clk_Fwd_Offset Data_Init_Cnt Addr_Init_Cnt Sys_Data_Even_Clk_Dly

Reset 0 Pinstrapping

R/W R/W R

23 22 21 20 19 18 17 16

Bit Sys_Data_Odd_Clk_Dly Sys_Data_Even_Dly Sys_Data_Odd_Dly Sys_Addr_Dly

Reset Pinstrapping

R/W R

15 14 13 12 11 10 9 8

Bit Sys_Addr_Dly SysDC_Dly Sys_Addr_Clk_Dly

Reset Pinstrapping

R/W R

7 6 5 4 3 2 1 0

Bit Sys_Rst_Clk_Offset Sys_Data_Rec_Mux_PreLd Sys_Addr_Rec_Mux_PreLd

Reset 0 0 Pinstrapping

R/W R

This register provides visibility to the serial initialization packet delivered to the AMD Athlon™ processor during the AMD Athlon processor system bus connect protocol.

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Bit Definitions BIU0 SIP (Dev0:F0:0x64)

Bit Name Function

31 Clk_Fwd_Offset Clock Forward Offset

0 = The AMD-761™ system controller delays driving of the data and clock for

AMD Athlon™ processor system bus SysData bits [31:16] and [63:48] by ~1000 ps.

1 = All AMD Athlon system bus ClkFWD groups drive the same nominally SysClk edge.

30–29 Data_Init_Cnt Data Initialization Count

This value specifies the number of SysClks from the launch of data by the processor until it can be read from the AMD-761 system controller receive FIFO.

28–27 Addr_Init_Cnt Address Initialization Count

This value specifies the number of SysClks from the launch of a command by the processor until it can be read from the AMD-761 system controller

26–24 Sys_Data_Even

_Clk_Dly

23–21 Sys_Data_Odd

_Clk_Dly

20–19 Sys_Data_Even

_Dly

18–17 Sys_Data_Odd

_Dly

16–15 Sys_Addr_Dly System Address Delay -- AMD Athlon processor SIP[23:22]

14–11 SysDC_Dly SysDC Delay -- AMD Athlon processor SIP[19:16]

10–8 Sys_Addr_Clk

_Dly

7–6 Sys_Rst_Clk

_Offset

5–3 Sys_Data_Rec

_Mux_PreLd

2–0 Sys_Addr_Rec

_Mux_PreLd

System Data Even Clock Delay -- AMD Athlon processor SIP[33:31] This value specifies the number of processor XICLK phases between the nominal start of

bit time and the launch of the even clocks. System Data Odd Clock Delay -- AMD Athlon processor SIP[30:28]

This value specifies the number of processor XICLK phases between the nominal start of bit time and the launch of the odd clocks.

System Data Even Delay -- AMD Athlon processor SIP[27:26] This value specifies the number of processor XICLK phases between the nominal start of

bit time and the launch of the even data (SysData bits [31:16] and [63:48]). System Data Odd Delay -- AMD Athlon processor SIP[25:24]

This value specifies the number of processor XICLK phases between the nominal start of bit time and the launch of the odd data (SData bits [15:00] and [47:32]).

This value specifies the number of processor XICLK phases between the nominal start of bit time and the launch of the address (SysAddOut).

This value is an internal processor parameter that is used to cause SYSDC commands and their associated data to arrive in the processor core at the correct relative times.

System Addr Clock Delay -- AMD Athlon processor SIP[13:11] This value specifies the number of processor XICLK phases between the nominal start of

bit time and the launch of the SADDOUTCLK. System Reset Clock Offset -- AMD Athlon processor SIP[10:9] This value is an internal processor parameter that is used to properly time AMD Athlon

system bus data transfer. System Data Rec Mux PreLd -- AMD Athlon processor SIP[8:6]

This value specifies the number of SysClk phases from the launch of data by the AMD-761 system controller until it can be read from the AMD Athlon receive FIFO.

System Address Rec Mux PreLd -- AMD Athlon processor SIP[5:3] This value specifies the number of SysClk phases from the launch of address/command by

the AMD-761 system controller until it can be read from the AMD Athlon receive FIFO.

receive FIFO.

Programming Notes

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Memory Status/Control Dev0:F0:0x70

31 30 29 28 27 26 25 24

Bit Reserved

Reset00000000

R/W R

23 22 21 20 19 18 17 16

Bit Reserved Self_Ref_En

Reset00000X00

R/W R R/W

15 14 13 12 11 10 9 8

Bit Reserved PCI_Pipe_En

Reset00000000

R/W R/W R R/W R

7 6 5 4 3 2 1 0

Bit Reserved Reserved Reserved Reserved Reserved Reserved

Reset00000000

R/W R R R

PCI_Blk_WR

_En

Reserved

This register provides general status and control for the memory controller.

Note that the Self_Ref_En bit in this register is not initialized at reset time, but must be initialized by BIOS for proper operation. This action should be done prior to attempting DRAM access.

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Bit Definitions Memory Status/Control (Dev0:F0:0x70)

Bit Name Function

31–19 Reserved Reserved

18 Self_Ref_En Self-Refresh Enable

This bit enables self-refresh when entering certain power management states. This bit should normally be set, but the option to disable this function is provided to accommodate specific DIMMs that do not correctly support the self-refresh feature. Note that if this bit is not set, then DCSTOP# assertion (ACPI sleep states) must be inhibited.

0 = Self-refresh disabled

1 = Self-refresh enabled

17–14 Reserved

13 Reserved

12–11 Reserved Reserved

10 PCI_Pipe_En PCI Pipe Enable

0 = All PCI transactions, from either the PCI or AGP interfaces, force the memory

controller to check for outstanding read probes with a matching block address and stall until these probes are complete.

1 = Memory controller pipelines PCI transactions.

Setting this bit generally increases PCI throughput. This bit must be clear when the processor is allowed to issue CleanVictimBlock commands.

9PCI_Blk_WR_EnPCI Block Write Enable

0 = PCI full-block writes do RID/INV probes, forcing the memory controller to wait for

probe data movement.

1 = PCI full-block writes do NOP/INV probes. This bit must be clear when the AMD Athlon™ processor is allowed to issue

CleanVictimBlock commands.

8–1 Reserved Reserved

0 Reserved Reserved

Programming Notes

Note that the Self_Ref_En bit in this register is not initialized at reset time but must be initialized by BIOS for proper operation. This action should be done prior to attempting DRAM access.

DCSTOP# assertion (ACPI S1/S3) must not be enabled if the Self_Ref_En bit is cleared.

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Who Am I (WHAMI) Dev0:F0:0x80

31 30 29 28 27 26 25 24

Bit Reserved

Reset00000000

R/W R

23 22 21 20 19 18 17 16

Bit Reserved Reserved Reserved Reserved BIU0_Present

Reset0000000From CPU

R/W R

15 14 13 12 11 10 9 8

Bit FirstBusID

Reset00000000

R/W R

7 6 5 4 3 2 1 0

Bit WHAMI

Reset CPUID

R/W R

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Bit Definitions Who Am I (WHAMI) (Dev0:F0:0x80)

Bit Name Function

31-17 Reserved Reserved

16 BIU0 _P rese nt BIU0 Present

This bit, when set, indicates that a processor is installed on the specified AMD Athlon™ processor system bus port on the AMD-761™ system controller and it has requested a connect sequence (ProcRdy assertion).

15–8 FirstBusID First BusID

This field contains the AMD Athlon processor system bus ID of the first processor to read this register:

00h if CPU0 was the first to read WHAMI after reset,

01h if CPU1 was the first to read WHAMI after reset.

7–0 WHAMI Who Am I

This field returns the AMD Athlon processor system bus ID (below) of the processor that accesses it:

00h for CPU0,

Programming Notes

01h for CPU1.

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PCI Arbitration Control Dev0:F0:0x84

31 30 29 28 27 26 25 24

Bit AGP_VGA_BIOS

Reset00000000

R/W R/W

23 22 21 20 19 18 17 16

Bit Tgt_Latency Reserved Reserved AGP_Chain_En PCI_Chain_En

Reset00000000

R/W R/W R R R/W R/W

15 14 13 12 11 10 9 8

Bit MDA_Debug

Reset00000000

R/W R/W

7 6 5 4 3 2 1 0

Bit PM_Reg_En 15M_Hole 14M_Hole EV6_Mode

Reset00000000

R/W R/W

PCI_WR_Post

_Rtry

AGP_WR_Post

_Rtry

RD_Data_Err

_Dis

AGP_Erly_Prb

_Dis

Tgt_Lat_Tim

_Dis

PCI_Erly_Prb

_Dis

AGP_Pref_En PCI_Pref_En Park_PCI

AGP_Arb_Pipe

_Dis

SB_Lock_Dis

This register provides general PCI arbiter mode control.

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Bit Definitions PCI Arbitration Control (Dev0:F0:0x84)

Bit Name Function

31–24 AGP_VGA_BIOS AGP VGA BIOS

These bits when set indicate that the corresponding (16-KByte) segment should be mapped to the AGP PCI bus. Bit 24 corresponds to the addresses 0xC0000–0xC3FFF and bit 31 maps addresses 0xDC000–0xDFFFF to the AGP PCI interface. Set one or more of these bits if the AGP graphics card has a ROM BIOS.

23 Tgt_Latency Target Latency

This bit is designed to ensure that the AMD-761™ system controller is compliant to the PCI maximum target latency rule. Note that this compliance applies only to the PCI bus and not the AGP bus.

0 = AMD-751™ system controller-compatible, the AMD-761 system controller does not

disconnect a master when it cannot service a read request within 32 PCI clock periods (initial latency) or 8 clocks (subsequent data cycles).

1 = If the AMD-761 system controller cannot respond to a memory read within 32 clocks

for the initial access, or 8 clocks for each subsequent access, it forces a retry.

Note: To prevent potential deadlocks, set this bit and clear bit 3 (Tgt_Lat_Tim_Dis) if

the system has PCI to AGP traffic.

22–18 Reserved Reserved

17 AGP_Chain_En Enable AGP Chaining

When set, CPU writes to the AGP bus are chained together.

16 PCI_Chain_En Enable PCI Chaining

When set, CPU writes to PCI are chained together.

15 MDA_Debug MDA Debug

This bit allows monochrome display adapters (MDA) to be used simultaneously with AGP cards for debug of AGP device drivers. The behavior of the AMD-761 system controller display adapters is a function of this bit and the VGA Enable in (D1:0x3C[19]) as follows:

MDA address ranges:

Memory: 0B0000h–0B7FFFh I/O: 3B4h, 3B5h, 3B8h, 3B9h, 3BAh, 3BFh

VGA = 0, MDA = 0: all MDA and VGA references go to PCI

VGA = 0, MDA = 1: operation undefined

VGA = 1, MDA = 0: all VGA references go to AGP, MDA only (I/O 3BFh) goes to PCI

VGA = 1, MDA = 1: all VGA references go to AGP, all MDA (including memory) go to PCI

14 PCI _W R_Po st

_Rtry

13 AG P_ WR _Pos t

_Rtry

PCI Write Post Retry

When set, this bit enables retries on PCI if there are pending posted writes.

AGP Write Post Retry

When set, this bit enables retries on the AGP bus if there are pending posted writes.

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Bit Definitions (Continued) PCI Arbitration Control (Dev0:F0:0x84)

Bit Name Function

12 RD_Data_Err_

Dis

11 AG P_ Er ly_P rb_

Dis

10 PCI _E rly_ Prb_

Dis

9 AGP_Arb_Pipe_

Dis

8 SB_Lock_Dis Southbridge Lock Disable

Read Data Error Disable

Whenever a cycle from a processor to the PCI or AGP buses results in a master abort (except special cycles), the AMD-761™ system controller returns a read data error indicator to the processor. When set, this bit causes data value of all 1s to be returned. When clear, an AMD Athlon™ processor system bus read data error response is returned. The CPU response to read data error is determined by the settings of the Machine Check Architecture registers in the processor.

AGP Early Probe Disable

As soon as the AMD-761 system controller detects a PCI write cycle to memory from an external AGP master, it sends a “probe only” request to the processor that is used to flush data from the processor cache. After one or more data phases, a write request is sent to the memory, which also results in a probe. When set, this bit disables the early probe from an AGP master running a PCI write cycle to memory.

PCI Early Probe Disable

This bit is similar AGP_Erly_Prb_Dis and can disable early probe requests for write cycles from an external master on the standard PCI bus.

AGP Arbiter Pipe Disable

When set, this bit disables the AGP arbiter from pipelining grants onto the bus.

When the Southbridge makes a request for the PCI bus, the AMD-761 system controller makes sure that all the previous posted requests from the processors and PCI are completed by the memory before granting the bus to the Southbridge. When set, this bit disables this flushing of previous requests.

7 PM_Reg_En Power Management Register Enable

This bit, when set, enables reading from and writing to the power management register (at BAR2).

615M_Hole 15M Memory Hole

When set, this bit creates a hole in memory from 15 Mbytes to 16 Mbytes. This register is used by the PCI decode logic to know when to accept a cycle from an external PCI master. When set, the PCI decode logic does not assert a match for addresses falling in this range.

514M_Hole 14M Memory Hole

When set, this bit creates a hole in memory from 14 Mbytes to 15 Mbytes. This register is used by the PCI decode logic to know when to accept a cycle from an external PCI master. When set, the PCI decode logic does not assert a match for addresses falling in this range.

4 EV6_Mode EV6 Mode

When set, this bit indicates that the PCI interfaces have to decode memory hits in the EV6 mode. There are no memory holes and DMA can be done to any address that lies within the SDRAM map.

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Bit Definitions (Continued) PCI Arbitration Control (Dev0:F0:0x84)

Bit Name Function

3 Tgt_Lat_Tim_

Dis

2AGP_Pref_EnAGP Prefetch Enable

1PCI_Pref_En PCI Prefetch Enable

0Park_PCI Park PCI

Programming Notes

To avoid potential deadlocks for systems that use traffic from the PCI bus to the PCI bus of the AGP, clear the write target latency timer disable bit (bit 3, Tgt_Lat_Tim_Dis), and set the read target latency timer bit (bit 23, Tgt_Latency). Refer to the programming notes for the PCI Control register (Dev 0:F0:0x4C) for details on the recommended setting of the Tgt_Latency bit.

Target Latency Timer Disable

When the AMD-761™ system controller acts as a PCI target, it has a latency timer that retries the (write) cycle if it cannot respond within 8 bus clocks (16 clocks for the first transfer). When set, this bit disables the AMD-761 system controller’s target latency timer on both the standard PCI and AGP PCI interfaces.

Note: To prevent potential deadlocks caused by PCI to AGP traffic on the system, this

bit should be cleared and bit 23 (Tgt_Latency) must be set. Note also that setting this bit disables the Tgt_Latency function controlled by bit 23.

When set, this bit enables the AMD-761 system controller to prefetch data from the SDRAM when a PCI master on the standard AGP bus reads from the main memory.

When set, this bit enables the AMD-761 system controller to prefetch data from the SDRAM when a PCI master on the PCI bus reads from the main memory.

When set, this bit enables parking on an external PCI master. When clear, the PCI arbiter only parks on processor accesses to PCI.

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Config Status Dev0:F0:0x88

31 30 29 28 27 26 25 24

Bit AGP_Clk_Mux Sys_Clk_Mux Type_Det S2K_Thresh

Reset x (from PCI AD[14:12]) x (from PCI AD[7:5])

R/W R

23 22 21 20 19 18 17 16

Bit K7_PP_En IG_PP_En Clk_Speed Reserved S2K0_Bus_Len

Reset

R/W R

Reset

R/W R

Reset

R/W R

x (from PCI

C/BE[3]#)

15 14 13 12 11 10 9 8

Bit Tristate_En NAND_En Bypass_PLLs Dis_Divider Reserved

x (from PCI

AD[25])

7 6 5 4 3 2 1 0

Bit SIP_ROM_En GP_Strap In_Clk_En Out_Clk_En CPU0_Divider

x(from PCI

C/BE[0]#)

x (from PCI

C/BE[2]#)

x (from PCI

AD[23])

x (from PCI

AD[15])

x (from PCI AD[31:30]) x (from PCI AD[27:26]) x (from PCI AD[11:10])

x (from PCI

AD[9])

x (from PCI

AD[24])

x (from PCI

AD[29])

x (from PCI

AD[8])

x (from PCI AD[19:16])

x (from PCI AD[3:0])

x (from PCI

AD[20])

x (from PCI

AD[4])

This register allows BIOS software to determine what system initialization states have been programmed by resistor pinstrappings on the motherboard.

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Bit Definitions Config Status (Dev0:F0:0x88)

Bit Name Function

31–29 AGP_Clk_Mux AGP Clock Mux

For internal test only.

28–26 Sys_Clk_Mux System Clock Mux

For internal test only.

25 Type_Det Type Detect

0 = This installed card in the AGP slot uses 1.5-V signalling.

1 = This installed card in the AGP slot uses 3.3-V signalling.

24 S2K_Thresh AMD Athlon™ Processor System Bus Threshold

AMD Athlon™ processor system bus threshold range select for AMD Athlon™ system bus I/O cells. When Low, these AMD Athlon processor system bus inputs sense input thresholds between 1.35 V and 1.9 V. When High, the inputs sense thresholds between 2.0 V and 2.2 V.

23 K7_PP_En AMD Athlon Processor Push-Pull Driver Enable

When set, this bit indicates that the AMD Athlon processor push-pull drivers are enabled.

22 IG_PP_En AMD-761™ System Controller Push-Pull Driver Enable

When set, this bit indicates that the AMD-761 system controller push-pull drivers are enabled.

21–20 Clk_Speed Clock Speed

This bit field defines the speed of the system clock received by the AMD-761 system controller:

00 = 100 MHz

01 = 66 M H z

10 = Re served

11 = 133 M H z

19–18 Reserved Reserved

17–16 S2K0_Bus_Len AMD Athlon Processor System Bus Length

This bit field indicates the relative length of the AMD Athlon processor system bus trace routing on the motherboard.

00 = Short

01..............

10...............

1 = Long

15 Tristate_En Tristate Enable

For internal test only.

14 NAN D_ En NAND Enable

For internal test only.

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Bit Definitions (Continued) Config Status (Dev0:F0:0x88)

Bit Name Function

13 Bypass_PLLs Bypass PLLs

This bit is set for test and debug of the AMD-761™ system controller with the internal PLLs disabled.

0 = AMD-761 system controller PLLs enabled

1 = AMD-761 system controller

pins directly to internal clock trees

12 Dis_Divider Disable Divider

For internal test only.

11–8 Reserved Reserved

7 SIP_ROM_En SIP ROM Enabled

This bit indicates that the external SIP ROM is enabled and is read to create the SIP stream to the AMD Athlon processor, instead of the internally generated SIP table.

6GP_Strap General-Purpose Strap

This bit may be used as a general-purpose strap for communicating motherboard- specific information to BIOS. The AMD-761 system controller does not use this strap internally.

5In_Clk_En INCLK Enable

This bit indicates that the AMD-761 system controller delays the INCLK to the AMD Athlon processor. When reset, the motherboard is expected to provide delay in the etch to center the INCLK with the data.

4 Out_Clk_En OUTCLK Enable

This bit indicates that the AMD Athlon processor delays the OUTCLK to the AMD-761 system controller. When reset, the motherboard is expected to provide delay in the etch to center the OUTCLK with the data.

3–0 CPU0_Divider CPU Divider

This bit field contains the CPU clock multiplier field supplied by the processor. Together with the Clk_Speed field and the S2K0_Bus_Len field, these fields allow the AMD-761 system controller to properly program the AMD Athlon™ processor system bus initialization logic using the SIP protocol.

The clock multiplier field is also known as the Frequency Identification (FID) bits and the values are shown below.

PLLs bypassed; clocks driven from SYSCLK and AGPCLK

FID Value Multiplier FID Value Multiplier FID Value Multiplier FID Value Multiplier

0000 11.0 0100 5.0 1000 7.0 1100 9.0

0001 11. 5 0101 5. 5 1001 7.5 1101 9. 5

0010 12. 0 0110 6 .0 1010 8 .0 1110 10 .0

0011 12. 5 0111 6 .5 1011 8 .5 1111 10 .5

Programming Notes

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PCI Top of Memory Dev0:F0:0x9C

31 30 29 28 27 26 25 24

Bit PCI_Mem_Top

Reset10000000

R/W R/W

23 22 21 20 19 18 17 16

Bit Reserved

Reset00000000

R/W R

15 14 13 12 11 10 9 8

Bit Reserved

Reset00000000

R/W R

7 6 5 4 3 2 1 0

Bit Reserved

Reset00000000

R/W R

This register is used to define the top of main system memory. It is used to compare the memory addresses of an external PCI master to determine if it is in the range of the AMD-761™ system controller DRAM. If the address compares, then the AMD-761 system controller responds to the bus master access with DEVSEL# assertion.

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Bit Definitions PCI Top of Memory (Dev0:F0:0x9C)

Bit Name Function

31–24 PCI_Mem_Top PCI Memory Top

This 8-bit field is compared to the incoming PCI bus master address to determine if a memory cycle falls within the AMD-761™ system controller DRAM region, as follows:

31 30 29 28 27 26 25 24 PCIMemTop Field 31 30 29 28 27 26 25 24 PCI Address

BIOS should write to this field following completion of the memory sizing algorithm, after it has determined the total size of the installed memory.

23–0 Reserved Reserved

Programming Notes

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AGP Capability Identifier Dev0:F0:0xA0

31 30 29 28 27 26 25 24

Bit Reserved

Reset00000000

R/W R

23 22 21 20 19 18 17 16

Bit Major_Rev Minor_Rev

Reset00100000

R/W R

15 14 13 12 11 10 9 8

Bit Next_Pointer

Reset00000000

R/W R

7 6 5 4 3 2 1 0

Bit Cap_ID

Reset00000010

R/W R

Bit Definitions AGP Capability Identifier (Dev0:F0:0xA0)

Bit Name Function

31–24 Reserved Reserved

23–20 Major_Rev Major Revision

Major revision of the AGP interface specification conformed to by this device.

19–16 Minor_Rev Minor Revision

Minor revision of the AGP interface specification conformed to by this device.

15–8 Next_Pointer Next Pointer

Pointer to the next item in the capabilities list. Must be null for the final item on the list.

7–0 Cap_ID CapID

This value indicates that this list item pertains to AGP registers.

Programming Notes

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AGP Status Dev0:F0:0xA4

31 30 29 28 27 26 25 24

Bit Max_ReqQ_Depth

Reset00001111

R/W R

23 22 21 20 19 18 17 16

Bit Reserved

Reset00000000

R/W R

15 14 13 12 11 10 9 8

Bit Reserved SBA Reserved

Reset00000010

R/W R

7 6 5 4 3 2 1 0

Bit Reserved R4G FW Reserved Rates

Reset00000111

R/W R

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Bit Definitions AGP Status (Dev0:F0:0xA4)

Bit Name Function

31–24 Max_ReqQ_

Depth

23–10 Reserved Reserved

9SBA Sideband Addressing

8–6 Reserved Reserved

5R4G Address Limit

4FW Fast Write Transfer

3 Reserved Reserved

2–0 Rates Rate Transfers

Programming Notes

Maximum Command Requests

This field contains the maximum number of AGP command requests that this node can manage.

This field is always 1, indicating that the AMD-761™ system controller supports sideband addressing.

This bit is always 0, indicating that the AMD-761 system controller does not support addresses greater than 4 Gbytes.

This bit indicates supports of fast write transfers. 0 = Fast writes not supported 1 = Fast writes supported

This field indicates that the AMD-761 system controller supports 1x (bit[0]), 2x (bit[1]), and 4X (bit[2]) transfers.

Fast writes are disabled by default and are indicated in the status bit that reports this capability. Setting the FW_Enable bit in the AGP 4X Dynamic Compensation register (Dev 0:F0:0xB4, bit 7) sets the FW bit in this register to indicate support of this feature. Fast writes are enabled when both the FW_Enable bit (in the AGP 4X Dynamic Compensation register) and the Fast_Writes bit in the AGP Command register are set.

AGP 4X transfers are supported and the 4X status bit is set by default in this register. This bit can be overridden by setting the 4X_Override bit in the AGP 4X Dynamic Compensation register (Dev 0:F0:0xB4, bit 6).

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AGP Command Dev0:F0:0xA8

31 30 29 28 27 26 25 24

Bit Reserved

Reset00000000

R/W R

23 22 21 20 19 18 17 16

Bit Reserved

Reset00000000

R/W R

15 14 13 12 11 10 9 8

Bit Reserved SBA_En AGP_En

Reset00000000

R/W R R/W

7 6 5 4 3 2 1 0

Bit Reserved R4G_En Fast_Writes Reserved Data_Transfer_Mode

Reset00000000

R/W R R/W R R/W

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Bit Definitions AGP Command (Dev0:F0:0xA8)

Bit Name Function

31–10 Reserved Reserved

9 SBA_En Sideband Addressing Enable

When this bit is set, sideband addressing is enabled.

8AGP_En AGP Operations Enable

When this bit is set, the AMD-761™ system controller accepts AGP operations. When this bit is clear, the AMD-761 system controller ignores AGP operations.

7–6 Reserved Reserved

5R4G_En 4GB Address Indicator

This bit indicates that the AMD-761 system controller does not support addresses greater than 4 Gbytes. The AMD-761 system controller supports only 32-bit addresses.

4 Fast_Writes Fast Writes

0 = Fast writes disabled 1 = Fast writes enabled when the FW_Enable bit is also set in the AGP 4X Dynamic

Compensation register (Dev 0:F0:0xB4, bit 7)

3 Reserved Reserved

2–0 Data_Transfer

_Mode

Programming Notes

Data Transfer Mode

Only one bit must be set in this field to indicate the desired AGP data transfer rate. 001 = 1X AGP rate 010 = 2X AGP rate 100 = 4X AGP rate

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AGP Virtual Address Space Size Dev0:F0:0xAC

31 30 29 28 27 26 25 24

Bit Reserved

Reset00000000

R/W R

23 22 21 20 19 18 17 16

Bit Reserved Vga_IA_En

Reset00000000

R/W R R/W

15 14 13 12 11 10 9 8

Bit Reserved

Reset00000000

R/W R

7 6 5 4 3 2 1 0

Bit Reserved VA_Size GART_En

Reset00000000

R/W R R/W

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Bit Definitions AGP Virtual Address Space Size (Dev0:F0:0xAC)

Bit Name Function

31–17 Reserved Reserved

16 Vga_IA_En ISA Address Aliasing Enable

When set, this bit forces the AMD-761™ system controller to alias ISA addresses, which means that address bits [15:10] are not used in decoding. When clear, no ISA aliasing is performed and address bits [15:10] are used for decoding.

15–4 Reserved Reserved

3–1 VA_Size Virtual Address Size

This field defines the virtual address space size to be allocated to GART by the system BIOS. Prior to the execution of the system BIOS memory mapping software, system BIOS gets the amount of GART virtual address space required by the graphics controller. It sets these bits to the required value. Changing these bits automatically changes bits [30:25] in the host-PCI bridge (device 0) AGP Virtual Address Space register, offset 0x10 (see “Dev0:F0:0x10” on page 37).

The size of GART virtual address space is always greater than or equal to the amount of physical system memory allocated to AGP in non-contiguous 4-Kbyte blocks. The amount of physical memory allocated to AGP is determined by operating system software.

[3] [2] [1] VA_Size

0 0 0 32 Mbytes

0 0 1 64 Mbytes

0 1 0 128 Mbytes

0 1 1 256 Mbytes

1 0 0 512 Mbytes

1 0 1 1 Gbytes

1 1 0 2 Gbytes

0 GART_En GART Enable

When clear, GART is not valid in this system. System BIOS does not allocate virtual address space for GART because the host-PCI bridge (device 0) AGP virtual address space, offset 0x10 (see “Dev0:F0:0x10” on page 37) is set to 0. The PCI-PCI bridge (device 1) capabilities pointer is set to point to the next item in the linked list or null if there is no other item. This bit is set by BIOS PCI enumeration routines.

When set, GART is valid in this system. System BIOS allocates virtual address space for GART based upon the value in bits [3:1] above.

Programming Notes

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GART/AGP Mode Control Dev0:F0:0xB0

31 30 29 28 27 26 25 24

Bit Reserved

Reset00000000

R/W R

23 22 21 20 19 18 17 16

Bit Reserved

Reset00000000

R/W R R/W

15 14 13 12 11 10 9 8

Bit Reserved

Reset00000000

R/W R

7 6 5 4 3 2 1 0

Bit Reserved

Reset00000000

R/W R

NonGART

_Snoop

PDC_En Lv1_Index

This register provides bits to control specific features of the AMD-761™ system controller AGP implementation.

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Bit Definitions GART/AGP Mode Control (Dev0:F0:0xB0)

Bit Name Function

31–21 Reserved Reserved

20 Reserved

19 NonGART_Snoop NonGART Snoop

When set, this bit forces AGP accesses that are not in the GART range to cause AMD Athlon™ processor system bus probes to the processor(s). When clear, AGP addresses that fall outside of the GART range do not cause probes.

18 Reserved

17 P D C _ E n Gart Page Directory Cache Enable

This bit is used only in the two-level GART mode. It has no effect in the one-level GART mode. The GART directory is enabled only when both this bit and the AGP Features Control register (offset 02h of the memory-mapped Features and Capabilities register—see “Bar1 + 0x00” on page 141) bit 2, "GART Cache Enable", are 1s.

16 Lv1_Index Level 1 Index (GART Index Scheme Control)

When set to 1, this bit enables the one-level GART mode. When cleared to 0, two-level GART mode is enabled.

15–0 Reserved Reserved

Programming Notes

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AGP 4X Dynamic Compensation Dev0:F0:0xB4

31 30 29 28 27 26 25 24

Bit PVal NVal

ResetXXXXXXXX

R/W R

23 22 21 20 19 18 17 16

Bit Reserved DisStrb Quantum_Cnt

Reset00000001

R/W R R/W R/W

15 14 13 12 11 10 9 8

Bit Reserved Reserved

Reset00000000

R/W R

7 6 5 4 3 2 1 0

Bit

FW_Enable 4X_Override

Reset00000000

R/W R/W R R/W

Comp3.3 Reserved PCI

Always_

Compensate

Do_

Compensate

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AMD 760 Software/BIOS Design Guide

Specifications and Main Features

Frequently Asked Questions

User Manual

Contents

List of Figures

List of Tables

Revision History

1 Overview

1.1 General BIOS Initialization Requirements

1.1.2 Special Configuration Sequencing Requirements

Configuration Cycles Enable

Function 1 Space The configuration registers that control the memory interface’s

Memory-Mapped BARs

Memory Holes Legacy memory holes are decoded in the normal region of main

AGP Override Bits for 4X Rate and Fast Writes

Interrupt Pin Control R/W Attributes

Silicon Revisions The reader is advised to read the AMD-761™ System Controller

1.1.3 Power-On Reset Initialization

1.1.4 Programming Reserved Bits

1.1.5 Power Management Considerations

2.1 Overview

2.2 Address Map

Figure 2. AMD Athlon™ Processor Family x86 Processor Address Mapping

2.2.1 Special Cycles

2.2.2 IACK

2.2.3 PCI Configuration Accesses

2.3 Address Decoding

2.3.1 Socket2000 Address Decoding

2.3.2 PCI/AGP Master Address Decoding

2.4 Configuration Registers

2.4.1 I/O Register Map

Table 5. I/O Register Map

2.4.2 Configuration Register Access

2.4.3 Device 0: PCI Configuration Registers

Table 8. Wait State Settings for DRAM Timing Register