Altera SerialLite II IP Core User Manual
SerialLite II MegaCore Function User Guide
SerialLite II MegaCore Function
User Guide
101 Innovation Drive
San Jose, CA 95134
www.altera.com
UG-0705-1.14
Document last updated for Altera Complete Design Suite version:
Document publication date:
13.1
January 2014
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ISO
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Registered
January 2014 Altera Corporation SerialLite II MegaCore Function
User Guide
Contents
Chapter 1. About This MegaCore Function
Release Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
Device Family Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3
Performance and Resource Utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–5
Installation and Licensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–8
OpenCore Plus Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–9
OpenCore Plus Time-Out Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–9
Chapter 2. Getting Started
Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
Create a New Quartus II Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2
Launch the MegaWizard Plug-In Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2
Parameterize . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3
Set Up Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6
Generate Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6
Simulate the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–7
Instantiate the MegaCore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–7
Specify Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–7
Assign Virtual Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–7
Fitter Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–8
Timing Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–8
Compile and Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–8
Chapter 3. Parameter Settings
Link Consistency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2
Physical Layer Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2
Data Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2
Transfer size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3
Reference Clock Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3
Port Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–4
Self Synchronized Link Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–7
Number of Lanes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–8
Scramble . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–9
De-Scramble . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–9
Broadcast Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–9
Clock Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–10
Lane Polarity and Order Reversal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–10
Lane Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–10
Lane Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–11
Frequency Offset Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–11
Link Layer Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–11
Data Type:Packets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–11
Data Type:Streaming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–11
Regular Data Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–12
Priority Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–12
Retry-on-error Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–12
January 2014 Altera Corporation SerialLite II MegaCore Function
User Guide
iv Contents
Retry-on-error Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–12
Segment Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–12
Retry-on-error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–13
Retry-on-error Responses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–14
Retry-on-error Operation Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–15
Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–15
Flow Control Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–15
Flow Control Operation Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–17
Selecting the Proper Threshold Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–18
Selecting the Proper Pause Duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–19
External Flow Control (When RX FIFO Size is 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–20
Transmit/Receive FIFO Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–20
FIFO Buffer Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–20
FIFO Buffer Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–21
Data Integrity Protection: CRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–22
16-Bit Versus 32-Bit CRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–22
Transceiver Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–23
Voltage Output Differential (V
) Control Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–23
OD
Pre-Emphasis Control Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–24
Transmitter Buffer Power (V
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–24
CCH
Equalizer Control Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–25
Bandwidth Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–25
Starting Channel number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–25
Instantiating a Transceiver Reconfiguration Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–26
ALTGX Support Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–26
Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–27
Optimizing the Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–28
Improving Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–29
Feature Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–29
Running Different Seeds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–29
Limiting Fanout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–29
Floorplanning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–29
Minimizing Logic Utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–30
Minimizing Memory Utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–30
Chapter 4. Functional Description
Interface Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1
Atlantic Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2
High-Speed Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3
Clocks and Data Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–4
Aggregate Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–4
External Clock Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–5
SerialLite II Internal Clocking Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–5
SerialLite II Deskew Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–6
SerialLite II Clocking Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–7
Arria V, Cyclone V, and Stratix V Transceiver Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–13
SerialLite II MegaCore Pin-Out Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–13
Initialization and Restart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–17
Multiple Core Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–18
MegaCore Configuration for Arria V, Cyclone V, and Stratix V Devices . . . . . . . . . . . . . . . . . . . . . . . . 4–19
Design Consideration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–19
Compilation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–19
Testbench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–20
Simulation Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–20
SerialLite II MegaCore Function January 2014 Altera Corporation
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Contents v
Parameter Settings For SerialLite II MegaCore and Custom PHY IP Core . . . . . . . . . . . . . . . . . . . . 4–20
Extra Signals Between SerialLite II MegaCore and Custom PHY IP Core . . . . . . . . . . . . . . . . . . . . . 4–21
Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–22
MegaCore Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–32
Chapter 5. Testbench
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1
SerialLite II Testbench Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1
Testbench Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–2
Simulation Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–5
Running a Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–6
Simulation Pass and Fail Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–6
Value Change Dump (VCD) File Generation (For the Verilog HDL Testbench) . . . . . . . . . . . . . . . . 5–8
Testbench Time-Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–8
Special Simulation Configuration Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–8
Atlantic Receiver Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–9
Testbench Components Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–9
DUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–9
SISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–9
AGEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–9
Verilog HDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–9
VHDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–12
AMON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–12
Verilog HDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–12
VHDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–15
Status Monitors (pin_mon) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–15
Pin_mon Tasks - Verilog HDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–16
Clock and Reset Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–16
Custom PHY IP Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–16
Example Testbench – Verilog HDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–16
Additional Information
Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1
How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1
Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–2
January 2014 Altera Corporation SerialLite II MegaCore Function
User Guide
SerialLite II MegaCore function is a lightweight protocol suitable for packet and
streaming data in chip-to-chip, board-to-board, and backplane applications. The
SerialLite II protocol offers low gate count and minimum data transfer latency. It
provides reliable, high-speed transfers of packets between devices over serial links.
The protocol defines packet encapsulation at the link layer and data encoding at the
physical layer, and integrates transparently with existing networks without software
support.
Release Information
1. About This MegaCore Function
Tab le 1– 1 provides information about this release of the Altera® SerialLite II
MegaCore
Table 1–1. SerialLite II Release Information
Version 13.1
Release Date November 2013
Ordering Code IP-SLITE2
Product ID 00AD
Vendor ID 6AF7
Altera verifies that the current version of the Quartus
previous version of each MegaCore function. The MegaCore IP Library Release Notes
and Errata report any exceptions to this verification. Altera does not verify
compilation with MegaCore function versions older than one release.
®
Device Family Support
MegaCore functions provide the following support for Altera device families:
■ Preliminary support—Altera verifies the IP core with preliminary timing models for
this device family. The core meets all functional requirements, but might still be
undergoing timing analysis for the device family. It can be used in production
designs with caution.
function.
Item Description
®
II software compiles the
■ Final support—Altera verifies the IP core with final timing models for this device
family. The core meets all functional and timing requirements for the device family
and can be used in production designs.
January 2014 Altera Corporation SerialLite II MegaCore Function
User Guide
1–2 Chapter 1: About This MegaCore Function
Features
Tab le 1– 2 shows the level of support offered by the SerialLite II MegaCore function to
each Altera device family.
Table 1–2. Device Family Support
Device Family Support
®
II GX Final
Arria
Arria V Preliminary
Arria V GZ Preliminary
®
Cyclone
Stratix
V Preliminary
®
IV Final
Stratix V Preliminary
Other device families No support
Features
■ Physical layer features
■ 622 Mbps to 6.375 Gbps per lane
■ Single or multiple lane support (up to 16 lanes)
■ 8-, 16-, or 32-bit data path per lane
■ Symmetric, asymmetric, unidirectional/simplex or broadcast mode
■ Optional payload scrambling
■ Full-duplex or self-synchronizing link state machine (LSM)
■ Channel bonding scalable up to 16 lanes
■ Synchronous or asynchronous operation
■ Automatic clock rate compensation for asynchronous use
■ ±100 and ±300 parts per million (ppm)
■ Link layer features
■ Atlantic
■ Support for two user packet types: data packet and priority packet
■ Optional packet integrity protection using cyclic redundancy code (CRC-32 or
™
interface compliant
CRC-16)
■ Optional link management packets
■ Retry-on-error for priority packets
■ Individual port (data/priority) flow control
■ Unrestricted data and priority packet size
■ Support for TimeQuest timing analyzer
■ Polarity reversal
■ Lane order reversal
SerialLite II MegaCore Function January 2014 Altera Corporation
User Guide
Chapter 1: About This MegaCore Function 1–3
One or More
Lanes
Logical
Electrical
Physical Layer
Link Layer
Logical
Electrical
Physical Layer
Link Layer
User
Application
User
Application
General Description
■ IP functional simulation models for use in Altera-supported VHDL and Verilog
HDL simulators
■ Support for OpenCore
®
Plus evaluation
General Description
The SerialLite II MegaCore function is a simple, high-speed, low-latency, and
low-resource point-to-point serial data communication link.
The MegaCore function performs up to the following rates:
■ 3.75 Gbps in Arria II GX devices
■ 5 Gbps in Cyclone V devices
■ 6.375 Gbps in Stratix IV, Arria V, and Stratix V devices
The SerialLite II MegaCore function is highly configurable, and provides a wide range
of functionality suited to moving data in many different environments.
The SerialLite II MegaCore function provides a simple and lightweight way to move
data from one point to another reliably at high speeds. It consists of a serial link of up
to 16 bonded lanes, with logic to provide a number of basic and optional link support
functions. The Atlantic interface is the primary access for delivering and receiving
data.
The SerialLite II protocol specifies a link that is simple to build, uses as little logic as
possible, and requires little work for a logic designer to implement. The SerialLite II
MegaCore function uses all of the features available in the SerialLite II protocol. You
can parameterize the MegaCore function using the SerialLite II parameter editor.
A link built using the SerialLite II MegaCore function operates at 622 Mbps to 6.375
Gbps per lane. Link reliability is enhanced by the 8B10B encoding scheme and
optional CRC capabilities. You can achieve further reductions in the bit-error rate by
using the optional retry-on-error feature. Data rate and consumption mismatches can
be accommodated using the optional flow-control feature to ensure that no data is
lost.
Figure 1–1 shows that the SerialLite II MegaCore function is divided into two main
blocks: a protocol processing portion (data link layer) and a high-speed front end
(physical layer).
Figure 1–1. SerialLite II MegaCore Function High-Level Block Diagram
You can use the SerialLite II MegaCore function in the following applications:
■ Chip-to-chip connectivity
January 2014 Altera Corporation SerialLite II MegaCore Function
User Guide
1–4 Chapter 1: About This MegaCore Function
Memory
ASSP
Network
Processor
Stratix IV GX
FPGA
Stratix IV
FPGA
SPI-4.2
Interface
SPI-4.2
Interface
SerialLite II
Interface
Optical/
Electrical
Converter
Line Card
Stratix IV GX
FPGA
SerialLite II
Interface
Control Card
Sensor
Sensor
Sensor
Sensor
Sensor
Sensor
Sensor
Sensor
Sensor
Sensor
Sensor
General Description
■ Board-to-board connectivity
■ Shelf-to-shelf connectivity
■ Backplane communication
■ Bridging applications
■ Streaming video applications
■ Imaging applications
Figure 1–2 and Figure 1–3 show two examples of bridging applications.
Figure 1–2. Typical Application—Bridging Functions
Figure 1–3. Typical Application—Unidirectional Bridging Application
SerialLite II MegaCore Function January 2014 Altera Corporation
User Guide
Chapter 1: About This MegaCore Function 1–5
Performance and Resource Utilization
Performance and Resource Utilization
Tab le 1– 3 lists the resources and internal core speeds for a selection of variations using
a 1,024-byte first-in first-out (FIFO) buffer. These results were obtained using the
Quartus II software version 10.1 for the following device: Stratix II GX
(EP2GX90FF1508C3).
Table 1–3. Performance for Stratix II GX (Part 1 of 2)
Data
Flow
Full-
Duplex
Full-
Duplex
Full-
Duplex
Full-
Duplex
Full-
Duplex
Full-
Duplex
Full-
Duplex
Full-
Duplex
Full-
Duplex
Full-
Duplex
Full-
Duplex
Full-
Duplex
Full-
Duplex
Full-
Duplex
Full-
Duplex
Full-
Duplex
Full-
Duplex
Memory
Blocks
M512
M4
Throughp
f
MAX
(MHz)
Mbps
K
Numbe
r of
Lanes
Data/
Type
Parameters
Packet
Type
Tra nsf
er Size
(1)
CR
C
Flow
Contr
ol
Retry-
on-
Error
Combi
n-
ational
ALUTs
Logic
Reg.
1 Packet Data 1 No No No 756 741 9 10 267 1250
1 Packet Data 2 No No No 768 754 0 11 285 3125
1 Packet Data 4 No No No 863 818 11 11 273 6375
4 Packet Data 1 No No No 1215 1031 15 11 239 1250
4 Packet Data 2 No No No 1507 1113 15 22 249 3125
4 Packet Data 4 No No No 2089 1554 2 48 247 6375
16 Packet Data 2 No No No 4101 2809 17 87 199 3125
16 Packet Data 4 No No No 6347 4493 1 180 185 6375
1 Packet Data 1 32 Yes No 1077 1028 9 12 276 1250
1 Packet Data 2 32 Yes No 1181 1019 1 12 239 3125
1 Packet Data 4 32 Yes No 1381 1075 12 12 215 6375
4 Packet Data 1 32 Yes No 1787 1306 16 12 215 1250
4 Packet Data 2 32 Yes No 2387 1446 16 23 192 3125
4 Packet Data 4 32 Yes No 3384 1907 3 49 177 6375
1 Packet Priority 2 16 Yes Yes 1448 1236 1 22 228 3125
1 Packet Priority 4 16 Yes Yes 1675 1284 12 22 225 6375
4 Packet Priority 2 16 Yes Yes 2573 1659 17 41 212 3125
ut
(2)
January 2014 Altera Corporation SerialLite II MegaCore Function
User Guide
1–6 Chapter 1: About This MegaCore Function
Performance and Resource Utilization
Table 1–3. Performance for Stratix II GX (Part 2 of 2)
Parameters
Data
Flow
Full-
Duplex
Notes to Table 1–3:
(1) A transfer size of 1 is used for 1,250 Mbps, 2 is used for 3,125 Mbps, and 4 is used for 6,375 Mbps.
(2) Total throughput equals the value in the Throughput column multiplied by the value in the Number of Lanes column.
Numbe
r of
Lanes
Data/
Type
Packet
Type
4 Packet Priority 4 16 Yes Yes 3528 2110 17 41 160 6375
Tra nsf
er Size
(1)
CR
C
Flow
Contr
ol
Retry-
Error
on-
Combi
n-
ational
ALUTs
Logic
Reg.
Memory
Blocks
M512
Tab le 1– 4 lists the resources and internal core speeds for a selection of variations using
1,024-byte FIFO buffers. These results were obtained using the Quartus II software
version 10.1 for the following device: Stratix GX (EP1SGX40GF1020C5).
Table 1–4. Performance for Stratix GX (Part 1 of 3)
Memory
Blocks
M51
2
M4K
Data
Flow
Full-
Duplex
Full-
Duplex
Full-
Duplex
Full-
Duplex
Full-
Duplex
Full-
Duplex
Full-
Duplex
Full-
Duplex
Full-
Duplex
Full-
Duplex
Full-
Duplex
Parameters
Number
of
Lanes
Data Type
Packet
Type
Transfer
(1)
Size
CRC
Flow
Contro
l
Retry
- onError
LEs
1 Packet Data 1 No No No 1065 9 10 178 1250
1 Packet Data 2 No No No 1098 0 11 182 3125
4 Packet Data 1 No No No 1711 15 11 186 1250
4 Packet Data 2 No No No 2706 23 22 180 3125
16 Packet Data 2 No No No 8328 50 87 158 3125
1 Packet Data 1 32 Yes No 1687 10 10 172 1250
1 Packet Data 2 32 Yes No 1728 2 11 163 3125
4 Packet Data 1 32 Yes No 2496 17 11 151 1250
4 Packet Data 2 32 Yes No 3848 25 22 127 3125
Data
1 Packet
and
2 No Both No 2169 2 19 181 3125
Priority
Data
1 Packet
and
2 32 Both No 2538 2 19 165 3125
Priority
M4
Throughp
f
MAX
(MHz)
ut
Mbps
(2)
K
Throughp
f
MAX
(MHz)
ut
Mbps
(2)
SerialLite II MegaCore Function January 2014 Altera Corporation
User Guide
Chapter 1: About This MegaCore Function 1–7
Performance and Resource Utilization
Table 1–4. Performance for Stratix GX (Part 2 of 3)
Data
Flow
Full-
Duplex
Full-
Duplex
Full-
Duplex
Full-
Duplex
Full-
Duplex
Full-
Duplex
Full-
Duplex
Full-
Duplex
Full-
Duplex
Full-
Duplex
Full-
Duplex
Simplex
Tx
Simplex
Tx
Simplex
Rx
Simplex
Rx
Asymm
Tx
Asymm
Tx
Asymm
Tx
Memory
Blocks
M51
2
M4K
f
MAX
(MHz)
Number
of
Lanes
Data Type
Parameters
Packet
Type
Transfer
(1)
Size
CRC
Flow
Contro
l
Retry
- onError
LEs
Data
4 Packet
and
2 No Both No 3911 33 38 181 3125
Priority
Data
4 Packet
and
2 32 Both No 4797 33 38 125 3125
Priority
1 Packet Priority 2 No Yes No 1350 2 11 188 3125
4 Packet Priority 2 No Yes No 2993 24 22 173 3125
8 Packet Priority 2 No Yes No 4787 28 44 167 3125
1 Packet Priority 2 16 Yes Yes 2241 2 21 163 3125
4 Packet Priority 2 16 Yes Yes 4373 26 40 144 3125
1 Streaming Data 1 No No No 198 0 0 253 1250
1 Streaming Data 2 No No No 243 0 0 246 3125
4 Streaming Data 1 No No No 763 4 0 183 1250
4 Streaming Data 2 No No No 1681 12 0 194 3125
1 Streaming Data 1 No No No 27 0 0 422 1250
1 Streaming Data 2 No No No 35 0 0 422 3125
1 Streaming Data 1 No No No 98 0 0 282 1250
1 Streaming Data 2 No No No 128 0 0 240 3125
4 Packet Data 1 No No No 1392 8 11 177 1250
4 Packet Data 2 No No No 1908 17 17 168 3125
8 Packet Data 2 No No No 2292 13 29 169 3125
Throughp
ut
(2)
Mbps
January 2014 Altera Corporation SerialLite II MegaCore Function
User Guide
1–8 Chapter 1: About This MegaCore Function
Installation and Licensing
Table 1–4. Performance for Stratix GX (Part 3 of 3)
Parameters
Data
Flow
Asymm
Rx
Asymm
Rx
Broad-
cast Rx
Broad-
cast Rx
Broad-
cast Rx
Notes to Table 1–4:
(1) A transfer size of 1 is used for 1,250 Mbps and 2 is used for 3,125 Mbps.
(2) Total throughput equals the value in the Throughput column multiplied by the value in the Number of Lanes column.
Number
of
Lanes
Data Type
Packet
Type
Transfer
(1)
Size
CRC
4 Packet Data 1 No No No 1604 9 11 195 1250
4 Packet Data 2 No No No 2559 23 16 177 3125
4 Streaming Data 1 No No No 561 0 0 187 1250
4 Streaming Data 2 No No No 729 0 0 200 3125
8 Streaming Data 2 No No No 1359 0 0 181 3125
Flow
Contro
Retry
- on-
l
Error
LEs
Memory
Blocks
M51
2
M4K
Installation and Licensing
The SerialLite II MegaCore function is part of the MegaCore IP Library, which is
distributed with the Quartus II software and downloadable from the Altera
www.altera.com.
f
MAX
(MHz)
Throughp
ut
Mbps
website,
(2)
You can use Altera's free OpenCore Plus evaluation feature to evaluate the MegaCore
function in simulation and in hardware before you purchase a license. You need to
purchase a license for the MegaCore function only when you are satisfied with its
functionality and performance, and you want to take your design to production.
After you purchase a license for the SerialLite II MegaCore function, you can request a
license file from the Altera website at www.altera.com/licensing and install it on your
computer. When you request a license file, Altera emails you a license.dat file. If you
do not have internet access, contact your local Altera representative.
SerialLite II MegaCore Function January 2014 Altera Corporation
User Guide
Chapter 1: About This MegaCore Function 1–9
lib
Contains encrypted lower-level design files.
ip
Contains the Altera MegaCore IP Library and third-party IP cores.
<path>
Installation directory.
altera
Contains the Altera MegaCore IP Library.
common
Contains shared components.
seriallite_ii
Contains the SerialLite II MegaCore function files.
Installation and Licensing
Figure 1–4 shows the directory structure after you install the SerialLite II MegaCore
function, where
<
path> is the installation directory. The default installation directory
on Windows is c:\altera\<version>; on Linux, it is /opt/altera<version>.
Figure 1–4. SerialLite II MegaCore Function Directory Structure
f For details on installation and licensing, refer to Altera Software Installation & Licensing.
OpenCore Plus Evaluation
With Altera's free OpenCore Plus evaluation feature, you can perform the following
actions:
■ Simulate the behavior of a megafunction (Altera MegaCore function or AMPP
megafunction) within your system
■ Verify the functionality of your design, as well as evaluate its size and speed
quickly and easily
■ Generate time-limited device programming files for designs that include
megafunctions
■ Program a device and verify your design in hardware
OpenCore Plus Time-Out Behavior
OpenCore Plus hardware evaluation supports the following two operation modes:
■ Untethered—the design runs for a limited time.
■ Tethered—requires a connection between your board and the host computer. If
tethered mode is supported by all megafunctions in a design, the device can
operate for a longer time or indefinitely.
All megafunctions in a device time out simultaneously when the most restrictive
evaluation time is reached. If there is more than one megafunction in a design, a
specific megafunction's time-out behavior may be masked by the time-out behavior of
January 2014 Altera Corporation SerialLite II MegaCore Function
1 For MegaCore functions, the untethered time-out is 1 hour; the tethered time-out
the other megafunctions.
value is indefinite.
SM
User Guide
1–10 Chapter 1: About This MegaCore Function
Installation and Licensing
Your design stops working after the hardware evaluation time; the SerialLite II
MegaCore function is forced into reset.
f For more information on OpenCore Plus hardware evaluation, refer to AN 320:
OpenCore Plus Evaluation of Megafunctions.
SerialLite II MegaCore Function January 2014 Altera Corporation
User Guide
Design Flow
2. Getting Started
Figure 2–1 outlines the high-level steps required to create a design that includes the
SerialLite II MegaCore function. Each step is explained in detail in the walkthrough
below.
Figure 2–1. SerialLite II MegaCore Design Flow
Specify Parameters
Simulate with Testbench
Instantiate in a Design
Specify Constraints
Compile
Design
Program
Device
This chapter explains how to create a SerialLite II MegaCore function using the
SerialLite II parameter editor in the MegaWizard Plug-In Manager and the Quartus II
software. When you finish generating a custom variation of the SerialLite II MegaCore
function, you can incorporate it into your overall project.
This walkthrough requires the following steps:
1. Create a New Quartus II Project
2. Launch the MegaWizard Plug-In Manager
3. Parameterize
4. Set Up Simulation
5. Generate Files
January 2014 Altera Corporation SerialLite II MegaCore Function
User Guide
2–2 Chapter 2: Getting Started
Design Flow
Create a New Quartus II Project
You can create a new Quartus II project with the New Project Wizard, which specifies
the working directory for the project, assigns the project name, and designates the
name of the top-level design entity.
To create a new project follow these steps:
1. Choose Programs > Altera > Quartus II <version> (Windows Start menu) to run
the Quartus II software. Alternatively, you can use the Quartus II Web Edition
software.
2. On the File menu, click New Project Wizard.
3. Click Next in the New Project Wizard: Introduction page (the introduction does
not display if you turned it off previously).
4. In the New Project Wizard: Directory, Name, Top-Level Entity page, enter the
following information:
a. Specify the working directory for your project. For example, this walkthrough
uses the c:\altera\projects\slite2_project directory.
b. Specify the name of the project. This walkthrough uses example for the project
name.
1 The Quartus II software automatically specifies a top-level design entity
that has the same name as the project. This walkthrough assumes that the
names are the same.
5. Click Next to display the New Project Wizard: Add Files page.
1 When you specify a directory that does not already exist, a message
prompts you to create a specified directory. Click Yes to create the directory.
6. Click Next to close this page and display the New Project Wizard: Family and
Device Settings page.
7. On the New Project Wizard: Family and Device Settings page, choose the target
device family in the Family list.
8. The remaining pages in the New Project Wizard are optional. Click Finish to
complete the Quartus II project.
Launch the MegaWizard Plug-In Manager
To launch the MegaWizard Plug-In Manager in the Quartus II software, follow these
steps:
1. On the Tools menu, click MegaWizard Plug-In Manager.
1 Refer to Quartus II Help for more information on how to use the
MegaWizard Plug-In Manager.
2. Specify that you want to create a new custom megafunction variation and click
Next.
SerialLite II MegaCore Function January 2014 Altera Corporation
User Guide
Chapter 2: Getting Started 2–3
Parameterize
3. Under Installed Plug-Ins, expand Interfaces folder and then, click
SerialLite II<version>.
4. Select the output file type for your design; the MegaWizard Plug-In Manager
supports VHDL and Verilog HDL. For this example, select Verilog HDL.
5. The MegaWizard Plug-In Manager shows the project path that you specified in the
New Project Wizard. Append a variation name for the MegaCore function output
files <project path>\<variation name>. For this example, type
example
as the
variation name.
6. Click Next to display the Parameter Settings page for the SerialLite II MegaCore
function.
Parameterize
This section shows how to parameterize the example SerialLite II MegaCore function
and describes the results of various options. A comprehensive description of all
parameters is contained in Chapter 3, Parameter Settings.
1 The following parameters are ordered as they appear in the SerialLite II parameter
editor. Not all parameters are supported by, or are relevant for, every MegaCore
function variation.
To parameterize your MegaCore function, follow these steps:
1. Click Parameter Settings in the SerialLite II parameter editor. The Physical Layer
page appears.
2. Enter a data rate in megabits per second (Mbps). The SerialLite II MegaCore
function supports data rates of 622 to 6,375 Mbps per lane.
The data rate must be an acceptable range for the Transfer size. SerialLite II
returns a warning or an error message if you specify a data rate that is not within
the range for the specified Transfer size.
3. Choose a Transfer size. The Transfer size determines the number of contiguous
data columns. The Transfer size also determines the serialization/deserialization
(SERDES) factor and internal data path width:
■ A Transfer size of 1 equates to an internal data path of 8 bits (Recommended
for less than 2.5 gigabits per second (Gbps))
■ A Transfer size of 2 equates to an internal data path of 16 bits (Recommended
for less than or equal to 3.125 Gbps)
■ A Transfer size of 4 equates to an internal data path of 32 bits (Typically for
greater than 3.125 Gbps, and only available for Stratix IV devices)
4. Specify the Reference Clock Frequency. This option defines the frequency of the
reference clock for the Arria II GX or Stratix IV internal transceiver. You can select
any frequency supported by the transceiver. This option is not available in Arria V,
Cyclone V, and Stratix V configurations.
5. Select a Port Type. You have three choices: Bidirectional, Tr an sm it te r o nl y, and
Receiver only.
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User Guide
2–4 Chapter 2: Getting Started
Parameterize
1 If you choose Tr a ns m i t te r o n ly or Receiver only, the self-synchronized
link-up parameter (LSM) is enabled by default.
6. Turn on or off the Self-Synchronized Link-Up option. This parameter allows the
receiver on the far end of the link to synchronize itself to incoming data streams,
rather than on an exchange of status information with the transmitter. Note that
the Self-Synchronized Link-Up feature is only for single lane applications.
7. Under Transmitter Settings, select the number of lanes for the transmitter.
8. Turn on or off the Scramble and Broadcast mode options.
9. Under Receiver Settings, select the number of lanes for the receiver.
Tab le 2– 1 shows the allowable number of lanes depending on the chosen
parameters.
Table 2–1. Number of Transmit Lanes
Self-Synchronized Link-Up Broadcast Number of Lanes
vv2 – 16
v —1
— v 2 – 16
— — 1 – 16
10. Turn on or off the De-scramble option.
11. Turn on or off the Enable frequency offset tolerance option. If you turn on this
option, select an offset tolerance of ±100 or ±300 parts per million (ppm).
12. Click Configure Transceiver to display the Configure Transceiver page. Select the
following parameters on the Configure Transceiver page to configure the ALTGX
megafunction.
Refer to “Transceiver Configuration” on page 3–23 for a more detailed description
of the transceiver parameters.
SerialLite II MegaCore Function January 2014 Altera Corporation
User Guide
Chapter 2: Getting Started 2–5
Parameterize
1 The Configure Transceiver page is disabled when you select Arria V or
Stratix V as the target device family. To add a transceiver, you are required
to instantiate the Custom PHY IP core.
a. For the transmitter, select the Voltage Output Differential (V
) control
OD
setting value.
b. Under Pre-emphasis, select a value for Specify pre-emphasis control setting.
c. In the Bandwidth mode list, select high or low for the Tx PLL bandwidth.
d. Select a value for the Transmitter Buffer Power (V
CCH
).
e. Under Receiver Functionality, select a value for Specify equalizer control
setting.
f. In the Bandwidth mode list, select high, medium or low for the Rx PLL
bandwidth.
g. To reconfigure functionality settings, specify a Starting channel number.
h. Click Finish.
13. Click Next to open the Link Layer page.
14. Under Data Type, select Packets or Streaming.
15. If you select Packets, select a packet type: Priority packets and data packets,
Priority packets, or Data packets.
16. If you select a packet type that includes priority packets, follow these substeps;
otherwise, skip to Step 17.
a. Turn on or off the Retry-on-error option.
b. If you turned on Retry-on-error, specify a value for Timeout and Segment
size.
c. Under Buffer Size, specify a value for Transmitter and Receiver.
d. Turn on or off the Enable flow control option.
e. If you turned on Enable flow control, specify the values for the following
settings:
■ Pause quantum time
■ Threshold
■ Refresh period
1 If you selected Priority packets only, skip to Step 18.
17. If you selected a packet type that includes data packets, follow these substeps:
a. Turn on or off the Enable flow control option.
b. If you turned on flow control, specify the values for the following settings:
■ Pause quantum time
■ Threshold
■ Refresh period
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2–6 Chapter 2: Getting Started
1 For information on setting these parameters, refer to “Flow Control” on
page 3–15.
c. Select the transmitter and receiver buffer sizes (bytes).
18. If your transmitter or receiver requires cyclic redundancy code (CRC) checking,
turn on the Enable CRC option for your chosen packet type and specify a value
for CRC Type.
19. Click Next.
Parameterize
Set Up Simulation
An IP functional simulation model is a cycle-accurate VHDL or Verilog HDL model
produced by the Quartus II software. The model allows for fast functional simulation
of IP using industry-standard VHDL and Verilog HDL simulators.
c You may use these models only for simulation and not for synthesis or any other
purposes. Using these models for synthesis creates a nonfunctional design.
To generate an IP functional simulation model for your MegaCore function, follow
these steps:
1. On the EDA page, under Simulation Libraries, turn on Generate Simulation
Model.
2. Some third-party synthesis tools can use a netlist that contains only the structure
of the MegaCore function, but not detailed logic, to optimize performance of the
design that contains the MegaCore function. If your synthesis tool supports this
feature, turn on Generate netlist.
3. Click Next to display the Summary page.
Generate Files
You can use the check boxes on the Summary page to enable or disable the generation
of specified files. A gray checkmark indicates a file that is automatically generated;
other checkmarks indicate optional files.
To generate your parameterized MegaCore function, follow these steps:
1. Turn on the files you want to generate.
2. To generate the specified files and close the SerialLite II parameter editor, click
Finish. The generation phase can take several minutes to complete.
3. If you generate the MegaCore function instance in a Quartus II project, you are
prompted to add the Quartus II IP File (.qip) to the current Quartus II project.
1 The .qip file is generated by the SerialLite II parameter editor and contains
information about a generated IP core. In most cases, the .qip file contains
all of the necessary assignments and information required to process the
MegaCore or system in the Quartus II compiler. The SerialLite II parameter
editor generates a single .qip file for each MegaCore function.
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Chapter 2: Getting Started 2–7
Simulate the Design
4. After your review the generation report, <variation name>.html, in your project
directory, click Exit to close the SerialLite II parameter editor.
Simulate the Design
You can simulate your design using the MegaWizard-generated VHDL and
Verilog HDL IP functional simulation models.
f For more information on IP functional simulation models, refer to the Simulating
Altera IP in Third-Party Simulation Tools chapter in volume 3 of the Quartus II Handbook.
Altera also provides a Verilog HDL demonstration testbench that shows you how to
instantiate a model in a design for all configurations. Altera also provides a VHDL
demonstration testbench for a restricted number of configurations. The testbench
stimulates the inputs and checks the outputs of the interfaces of the SerialLite II
MegaCore function, allowing you to evaluate the MegaCore function’s basic
functionality. The testbench is described in detail in Chapter 5, Testbench.
Instantiate the MegaCore
You can now integrate your custom MegaCore function variation into your design
and simulate your complete design using your own custom testbench.
Specify Constraints
This example design applies constraints to create virtual pins and set up timing
analysis.
Assign Virtual Pins
If you are compiling the SerialLite II MegaCore function variation as a standalone
component, you must specify virtual pin assignments. The SerialLite II parameter
editor generates a tool command language (Tcl) script that automates this task. Follow
these steps to run the script:
1. On the Tools menu, click Tcl Scripts to open the Tcl Scripts dialog box.
2. In the project directory, select <variation_name>_constraints.
3. Click Run.
1 The script assumes the default names for the virtual pins. If you have connected the
pins to names other than the default names, you must edit this script and change the
virtual pin names when the core is still compiled in stand-alone mode.
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2–8 Chapter 2: Getting Started
Compile and Program
Fitter Constraints
The Tcl script also optimizes fitter settings to produce the best performance (f
Use this script as a guide to set constraints for the SerialLite II MegaCore function
variation in your design. The timing constraints are currently set for the SerialLite II
MegaCore function variation as a standalone component, thus you must update the
script with hierarchy information for your own design. The Tcl script also points to
the generated Synopsys Design Constraints (SDC) timing constraint script if the
TimeQuest timing analyzer is enabled. The Fitter optimizes your design based on the
requirements in the .sdc files in your project.
The script uses the
1 This fitter setting may conflict with your Quartus II software settings.
You can now integrate your MegaCore function variation into your design and
simulate and compile.
Timing Constraints
The SerialLite II MegaCore generates an ASCII file (with the .sdc extension) that
contains design constraints and timing assignments in the industry-standard SDC
format. The constraints in the .sdc file are described using the Tcl tool command
language and follow Tcl syntax rules.
To specify the TimeQuest timing analyzer as the default timing analyzer, on the
Assignments menu, click Timing Analysis Settings. In the Timing Analysis Settings
page, turn on Use TimeQuest Timing Analyzer during compilation.
FITTER_EFFORT "STANDARD FIT"
Fitter setting.
MAX
).
The TimeQuest timing constraints are currently set for the SerialLite II MegaCore
function variation as a standalone component. You must update the script with
hierarchy information if your own design is not a standalone component.
f Refer to the Quartus II TimeQuest Timing Analyzer chapter in volume 3 of the Quartus II
Handbook for more information on how to use the TimeQuest Timing Analyzer.
Compile and Program
Click Start Compilation on the Processing menu in the Quartus II software to compile
your design. After successfully compiling your design, program the targeted Altera
device with the Programmer (Tools menu) and verify the design in hardware.
SerialLite II MegaCore Function January 2014 Altera Corporation
User Guide
3. Parameter Settings
Tab le 3– 1 shows the function parameters, which can be set only in the SerialLite II
parameter editor (refer to “Parameterize” on page 2–3). The following sections
describe these parameters.
Table 3–1. Default SerialLite II Variation
Parameter Default Configuration
Physical Layer
Device family
Data rate 3,125 megabits per second (Mbps)
Transfer size 2 Columns
Reference Clock Frequency 156.25 MHz
Port Type Bidirectional
Self-Synchronized Link-Up Disabled
Number of lanes (Transmitter and Receiver Settings) 1
Scramble/De-Scramble Disabled
Broadcast mode Disabled
Enable frequency offset tolerance Disabled
Depends on the family specified in the
SerialLite II parameter editor
Link Layer
Data Type Packets
Packet type Data packets
Enable flow control Disabled
Buffer Size (Transmitter and Receiver) 1,024 bytes
CRC Generation (Transmitter and Receiver) Disabled
Configure Transceiver
Specify Voltage Output Differential (V
setting
) control
OD
0
Specify pre-emphasis control setting 0
Bandwidth mode (Transmitter and Receiver) Low
Transmitter Buffer Power (V
)1.5
CCH
Specify equalizer control setting 0
Starting channel number 0
To configure your own variation of the SerialLite II MegaCore function, you must
decide the following issues:
■ High-level link configuration
■ Bandwidth required
■ Whether to use CRC checking
January 2014 Altera Corporation SerialLite II MegaCore Function
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3–2 Chapter 3: Parameter Settings
FPGA 2
SerialLite II
System
FPGA 1
SerialLite II
MegaCore
System
Logic Logic
One or
more lanes
Tx
Rx
Rx
Tx
Atlantic InterfaceAtlantic Interface
High-Speed
Transceivers
High-Speed
Transceivers
Function
Variation
MegaCore
Function
Variation
■ Whether to implement flow control
■ How to size the FIFO buffers
Link Consistency
Link Consistency
A SerialLite II link consists of two instantiations of logic implementing the
SerialLite II protocol. Each end of the link has a transmitter and a receiver, as shown in
Figure 3–1.
Figure 3–1. Complete SerialLite II Link
Physical Layer Configuration
This section describes the options available to parameterize the physical layer of your
SerialLite II MegaCore function variation.
Data Rate
The SerialLite II MegaCore function supports a data rate range of 622 to 6,375 Mbps
per lane. In Arria II GX devices, the data rate must be less than 3,750 Mbps, and in
Stratix IV devices, less than 6,375 Mbps. The data rate range varies based on the
device and the transfer size (TSIZE) as Table 3–2 on page 3–2 illustrates.
Table 3–2. Data Rate Dependencies on Transfer Size (Part 1 of 2)
Devices
2.5 Gbps 3.125 Gbps 3.75 Gbps 5 Gbps 6.375 Gbps
Arria II GX TSIZE= 1, 2 TSIZE= 2 TSIZE= 2 Not Supported Not Supported
(1)
Arria V TSIZE= 1, 2 TSIZE= 2
Arria V GZ TSIZE= 1, 2 TSIZE= 2
, 4 TSIZE= 2
(1)
, 4 TSIZE= 2
Cyclone V TSIZE= 2 TSIZE= 2 TSIZE= 2 TSIZE= 4 Not Supported
Stratix IV TSIZE= 1, 2 TSIZE= 2 TSIZE= 2 TSIZE= 2
Data Rate
(1)
(1)
, 4 TSIZE= 4 TSIZE= 4
, 4 TSIZE= 4 TSIZE= 4
(1)
, 4 TSIZE= 4
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User Guide
Chapter 3: Parameter Settings 3–3
Physical Layer Configuration
Table 3–2. Data Rate Dependencies on Transfer Size (Part 2 of 2)
Devices
2.5 Gbps 3.125 Gbps 3.75 Gbps 5 Gbps 6.375 Gbps
Stratix V TSIZE= 1, 2 TSIZE= 2
Note to Table 3–2:
(1) Symmetric mode (p_RX_NUM_LANES == p_TX_NUM_LANES) only.
(1)
, 4 TSIZE= 2
The data rates for an individual Arria II GX device are limited to the respective speed
grades, refer to Tabl e 3– 3.
Table 3–3. Arria II GX Speed Grade-Data Rate Limits
Device Speed Grade Minimum Data Rate (Mbps) Maximum Data Rate (Mbps)
C4 600 3,750
C5 600 3,125
C6 600 3,125
Transfer si ze
The Transfer size parameter defines many important characteristics of the MegaCore
function variation. Transfer size determines the number of contiguous data columns
and the internal data path width per lane, where:
■ A transfer size of 1 equates to an internal data path of 8 bits (Recommended for
less than 2.5 Gbps)
Data Rate
(1)
, 4 TSIZE= 2
(1)
, 4 TSIZE= 4
■ A transfer size of 2 equates to an internal data path of 16 bits (Recommended for
less than or equal to 3.125 Gbps)
■ A transfer size of 4 equates to an internal data path of 32 bits (only available for
Stratix IV FPGA with transfer size greater than 3.125 Gbps, and must be used
when the data rate exceeds 5 Gbps)
A transfer size determines the width of the SERDES block, where:
■ A transfer size of 1 equates to a 10 bit-wide SERDES block
■ A transfer size of 2 equates to a 20 bit-wide SERDES block
■ A transfer size of 4 equates to a 40-bit wide SERDES block
Reference Clock Frequency
The Reference Clock Frequency parameter defines the frequency of the reference
clock for the Arria II GX or Stratix IV internal transceiver. Valid values change with
the data rate but the reference input clock frequency must be within 50 MHz and 622
MHz.
■ The general formula to determine frequency:
Frequency = p×Data Rate/(2×m), where p = 1 or 2, and m = 4, 5, 8, 10, 16, 20, or 25
Condition for frequency to be valid: (50×p) < Frequency < 622
■ This parameter is only applicable if you chose Arria II GX or Stratix IV devices.
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3–4 Chapter 3: Parameter Settings
One or more lanes
(up to N)
FPGA 1
Light-weight
Linklayer
PHY
Layer
FPGA 2
Light-weight
Linklayer
PHY
Layer
Atlantic
Interface
CDR
SERDES
CDR
SERDES
One or more lanes
(up to N)
Atlantic
Interface
■ If you select a reference clock frequency that is not equal to the
Physical Layer Configuration
data rate/(transfer size) * 10, the Clock Compensation option is disabled if the
Receiver only port type option is turned on.
Port Type
The Port Type parameter offers three options: Bidirectional, Transmitter only, and
Receiver only. If you turn on the Bidirectional option, you must specify values for
Transmitter Settings and Receiver Settings. Under Transmitter Settings, you need to
specify the Number of lanes, and select whether or not to enable the Scramble and
Broadcast mode. Under Receiver Settings, you must specify the settings for the
Number of lanes, and select whether or not to enable the De-Scramble option. If you
turn on Transmitter only option, you must specify values for Transmitter Settings
only, and if you turn on Receiver only option, you must specify values for Receiver
Settings only.
The Number of lanes parameter dictates the number of serial links, essentially the
number of external inputs and outputs (I/Os) for the MegaCore function.
If you set the Number of lanes for the transmitter and receiver settings to the same
value, you configure the MegaCore function to operate in symmetric, bidirectional
mode. Refer to Figure 3–2 and Figure 3–3 on page 3–5.
If you set the Port Type to Receiver only or Transmitter only, you configure the
MegaCore function to operate in unidirectional mode, transmitter, or receiver only.
Refer to Figure 3–4 and Figure 3–5 on page 3–6.
If you set the Port Type to Bidirectional, but have the number of lanes set to a value
other than zero, but not equal to the other function’s value, you configure the
MegaCore function to operate in asymmetric mode. Refer to Figure 3–6 and
Figure 3–7 on page 3–7.
Figure 3–2. Symmetric Mode Block Diagram
Notes to Figure 3–2:
(1) A full line indicates a mandatory lane.
(2) A dashed line indicates an optional lane.
SerialLite II MegaCore Function January 2014 Altera Corporation
User Guide
Chapter 3: Parameter Settings 3–5
One lane only
FPGA 1
Light-weight
Linklayer
PHY
Layer
FPGA 2
Light-weight
Linklayer
PHY
Layer
Atlantic
Interface
CDR
SERDES
CDR
SERDES
Atlantic
Interface
Physical Layer Configuration
Figure 3–3. Streaming Symmetric Mode Block Diagram
FPGA 1
Atlantic
Interface
PHY
Layer
Notes to Figure 3–3:
(1) A full line indicates a mandatory lane.
(2) A dashed line indicates an optional lane.
Figure 3–4. Simplex Mode Block Diagram
CDR
SERDES
One or more lanes
(up to N)
One or more lanes
(up to N)
CDR
SERDES
FPGA 2
PHY
Layer
Atlantic
Interface
Note to Figure 3–4:
(1) A full line indicates a mandatory lane.
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3–6 Chapter 3: Parameter Settings
One or more lanes
(up to N)
FPGA 1
Light-weight
Linklayer
PHY
Layer
FPGA 2
Light-weight
Linklayer
PHY
Layer
Atlantic
Interface
CDR
SERDES
CDR
SERDES
One or more lanes
(up to M, but
not equal to N)
Atlantic
Interface
Physical Layer Configuration
Figure 3–5. Streaming Simplex Mode Block Diagram
FPGA 1
Atlantic
Interface
PHY
Layer
CDR
SERDES
Note to Figure 3–5:
(1) A full line indicates a mandatory lane
Figure 3–6. Asymmetric Mode Block Diagram
One lane only
CDR
SERDES
FPGA 2
PHY
Layer
Atlantic
Interface
Notes to Figure 3–6:
(1) A full line indicates a mandatory lane.
(2) A dashed line indicates an optional lane.
SerialLite II MegaCore Function January 2014 Altera Corporation
User Guide
Chapter 3: Parameter Settings 3–7
One or more lanes
(up to N)
FPGA 1
PHY
Layer
FPGA 2
PHY
Layer
Atlantic
Interface
CDR
SERDES
CDR
SERDES
One or more lanes
(up to M, but
not equal to N)
Atlantic
Interface
Physical Layer Configuration
Figure 3–7. Streaming Asymmetric Mode Block Diagram
Notes to Figure 3–7:
(1) A full line indicates a mandatory lane.
(2) A dashed line indicates an optional lane.
Self Synchronized Link Up
The receiver on the far end must synchronize itself to incoming data streams. To do so,
it uses the self-synchronizing LSM, a light-weight implementation that is especially
useful when data is streaming. As there is no handshaking or exchange of status
information between the receiver and transmitter, this parameter uses considerably
fewer logic elements than the full-duplex LSM. The self-synchronizing LSM can be
used in all modes, except asymmetric mode, but this mode can only support one lane.
This parameter is enabled by default when the MegaCore function operates in
unidirectional mode because the duplex LSM cannot be used when there is no return
path.
The
ctrl_tc_force_train
Negate the signal once the adjacent receiver has locked, if this status information can
be made available, or after a user-defined period of time when the link status of the
adjacent receiver is not known or cannot be known. The LSM links up after receiving
64 consecutive valid, error-free characters. The link goes down after receiving four
consecutive errors; at this time, the
until the receiver relocks.
The required hold time for the
the ALTGX megafunction completes the power-on reset cycle. Therefore, the selfsynchronizing link-up state machine does not look at the incoming stream until the
transceiver reset is complete.
signal must be asserted for the training patterns to be sent.
ctrl_tc_force_train
ctrl_tc_force_train
signal should be reasserted
signal largely depends on when
For example, the following procedure shows the transceiver reset sequence in an
Arria or Stratix transceiver device:
1. Wait for the
pll_locked
signal (
stat_tc_pll_locked
) to be asserted, which
happens when the PLL in the ALTGX megafunction locks to the reference clock
(
trefclk
January 2014 Altera Corporation SerialLite II MegaCore Function
). The reference clock must be characterized; 10 ms or less is normal.
User Guide
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