Altera Serial Digital Interface MegaCore Function User Manual
Serial Digital Interface (SDI) MegaCore Function User
Guide
Serial Digital Interface (SDI) MegaCore Function
User Guide
101 Innovation Drive
San Jose, CA 95134
www.altera.com
UG-SDI1005-16.0
Document last updated for Altera Complete Design Suite version:
Document publication date:
12.1
February 2013
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ISO
9001:2008
Registered
February 2013 Altera Corporation Serial Digital Interface (SDI) MegaCore Function
User Guide
Contents
Chapter 1. About This MegaCore Function
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
Release Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2
Device Family Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3
OpenCore Plus Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–5
Resource Utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–6
Chapter 2. Getting Started
Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
SDI Walkthrough . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3
Creating a New Quartus II Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3
Launching MegaWizard Plug-In Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4
Parameterizing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5
Setting Up Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6
Generating Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6
Simulating the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–8
Testbench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–8
Simulate with IP Functional Simulation Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–9
Simulating with the ModelSim Simulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–9
Simulating in Third-Party Simulation Tools Using NativeLink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–10
Specifying Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–11
Single Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–11
Multiple Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–12
Compiling the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14
Programming a Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14
Setting Up Licensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–15
Chapter 3. Functional Description
Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2
Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2
HD-SDI LN Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–4
HD-SDI CRC Generation and Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–4
Scrambling and NRZI Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–5
Transceiver Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–5
Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–6
NRZI Decoding and Descrambling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–8
Word Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–8
Video Timing Flags Extraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–9
RP168 Switching Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–9
HD-SDI LN Extraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–10
HD-SDI CRC Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–10
Accessing Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–10
Transceiver Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–12
Transceiver—Soft-Logic Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–12
Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–12
Transmitter Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–12
Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–13
February 2013 Altera Corporation Serial Digital Interface (SDI) MegaCore Function
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Receiver Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–13
Transceiver—Stratix GX Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–13
Transmitter Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–13
Receiver Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–15
Transmitter Transceiver Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–16
Receiver Transceiver Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–17
Transceiver—Arria GX, Arria II GX, Arria V, Cyclone IV GX, Cyclone V, Stratix II GX, Stratix IV GX,
and Stratix V Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–18
Transmitter Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–19
Receiver Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–22
Transmitter Transceiver Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–23
Receiver Transceiver Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–24
Locking to the Incoming SDI Stream . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–25
Transceiver Dynamic Reconfiguration for Dual Standard and Triple Standard Receivers . . . . . . 3–27
Transceiver Dynamic Reconfiguration with Channel Reconfiguration Mode—Arria II GX,
HardCopy IV GX, Stratix GX, Stratix II GX, and
Stratix IV GX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–27
Transceiver Dynamic Reconfiguration with PLL Reconfiguration Mode—Cyclone IV GX . . . 3–33
Reset Requirement During Reconfiguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–36
OpenCore Plus Time-Out Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–39
Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–39
Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–56
MegaCore Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–57
Chapter 4. SDI Audio IP Cores
SDI Audio Embed MegaCore Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2
Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3
Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–4
Register Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–8
SDI Audio Extract MegaCore Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–10
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–10
Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–11
Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–12
Register Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–15
Clocked Audio Input MegaCore Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–17
Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–17
Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–17
Register Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–18
Clocked Audio Output MegaCore Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–19
Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–19
Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–19
Register Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–20
AES Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–21
Avalon-ST Audio Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–21
Instantiating the IP Cores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–23
Simulating the Testbench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–24
Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–25
Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–26
SDI Transmitter P0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–26
SDI Duplex . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–26
Audio Extract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–27
AES Output Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–27
AES Input Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–27
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Audio Embed P0/P1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–27
Video Pattern Generator P0/P1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–27
Audio Pattern Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–27
Ancillary Data Insertion P0/P1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–27
Transceiver Dynamic Reconfiguration Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–27
Hardware and Software Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–28
Hardware Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–28
Running the Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–30
Transmit SD-SDI with Embedding of Audio Group 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–30
Transmit HD-SDI with Embedding of Audio Group 1 and 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–31
Transmit 3G-SDI Level A with Embedding of Audio Group 1, 2 and 3 . . . . . . . . . . . . . . . . . . . . 4–32
Transmit 3G-SDI Level B with Embedding of Audio Group 1, 2, 3 and 4 . . . . . . . . . . . . . . . . . . 4–32
Appendix A. Constraints
Specifying TimeQuest Timing Analyzer Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–1
Specify Clock Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–4
Set Multicycle Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–5
Specify Clocks that are Exclusive or Asynchronous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–5
Define the Setup and Hold Relationship between 135-MHz Clocks and 337.5-MHz Zero-degree
Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–6
Minimize Timing Skew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–7
Constraints for the SDI Soft Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–7
Non Cyclone Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–8
Classic Timing Analyzer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–8
TimeQuest Timing Analyzer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–8
Cyclone Devices Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–9
Classic Timing Analyzer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–9
TimeQuest Timing Analyzer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–9
Appendix B. Clocking
Appendix C. Receive and Retransmit
Loopback FIFO Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C–1
Additional Information
Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1
How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–3
Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–3
February 2013 Altera Corporation Serial Digital Interface (SDI) MegaCore Function
User Guide
vi Contents
Serial Digital Interface (SDI) MegaCore Function February 2013 Altera Corporation
User Guide
1. About This MegaCore Function
This user guide describes the Altera® Serial Digital Interface (SDI) MegaCore
function and the accompanying SDI Audio IP cores.
The SDI MegaCore function implements a receiver, transmitter, or full-duplex SDI at
standard definition (SD), high definition (HD), or 3 gigabits per second (3G). The SDI
MegaCore function also supports dual standard (HD-SDI and SD-SDI) and triple
standard (SD-SDI, HD-SDI, and 3G-SDI). These modes provide automatic receiver
rate detection.
You can instantiate the SDI Audio IP cores with the SDI MegaCore function.
1 For more information about the SDI Audio cores, refer to “SDI Audio IP Cores” on
page 4–1.
Features
Tab le 1– 1 lists the features of the SDI MegaCore function.
Table 1–1. SDI MegaCore Function Features
Feature Description
■ Multiple SDI standards and video formats (refer to Table 1–5 and Table 1–6)
Support
Transmitter
Receiver
MegaWizard™ Plug-In Manager
IP functional simulation models ■ Use in Altera-supported VHDL and Verilog HDL simulators
■ RP168 video switch line requirement
■ OpenCore Plus evaluation
■ Cyclical redundancy check (CRC) encoding (HD only)
■ Line number (LN) insertion (HD only)
■ Word scrambling
■ Transmitter clock multiplexer (optional)
■ CRC decoding (HD only)
■ LN extraction (HD only)
■ Framing and extraction of video timing signals
■ Word alignment and descrambling
■ Easy-to-use parameter editor
®
February 2013 Altera Corporation Serial Digital Interface (SDI) MegaCore Function
User Guide
1–2 Chapter 1: About This MegaCore Function
Release Information
Release Information
Tab le 1– 2 lists information about this release of the SDI MegaCore function.
Table 1–2. Release Information
Item Description
Version 12.1
Release Date January 2013
Ordering Code IP-SDI
Product ID(s)
Vendor ID 6AF7
f For more information about this release, refer to the MegaCore IP Library Release Notes
and Errata.
00AE (SDI MegaCore function)
00EF (SDI Audio cores)
Altera verifies that the current version of the Quartus
previous version of each MegaCore function. The MegaCore IP Library Release Notes
and Errata report any exceptions to this verification. Altera does not verify
compilation with MegaCore function versions older than one release.
Device Family Support
Tab le 1– 3 defines the device support levels for Altera IP cores.
Table 1–3. Altera IP Core Device Support Levels
FPGA Device Families HardCopy Device Families
Preliminary support—The IP core is verified with
preliminary timing models for this device family. The IP core
meets all functional requirements, but might still be
undergoing timing analysis for the device family. It can be
used in production designs with caution.
Final support—The IP core is verified with final timing
models for this device family. The IP core meets all
functional and timing requirements for the device family and
can be used in production designs.
Tab le 1– 4 shows the level of support offered by the SDI MegaCore function for each
Altera device family.
®
II software compiles the
HardCopy Companion—The IP core is verified with
preliminary timing models for the HardCopy companion
device. The IP core meets all functional requirements, but
might still be undergoing timing analysis for the HardCopy
device family. It can be used in production designs with
caution.
HardCopy Compilation—The IP core is verified with final
timing models for the HardCopy device family. The IP core
meets all functional and timing requirements for the device
family and can be used in production designs.
Table 1–4. Device Family Support (Part 1 of 2)
Device Family Support
®
GX Final
Arria
Arria II (1) Final
Arria V
Serial Digital Interface (SDI) MegaCore Function February 2013 Altera Corporation
User Guide
Refer to the What’s New in Altera IP page of
the Altera website.
Chapter 1: About This MegaCore Function 1–3
General Description
Table 1–4. Device Family Support (Part 2 of 2)
Device Family Support
®
Cyclone
Final (3)
Cyclone II (2) Final
Cyclone III (2) Final
Cyclone III LS (2) Final
Cyclone IV GX (4) Final
Cyclone V (5)
HardCopy
®
III/ IV E HardCopy Compilation
Refer to the What’s New in Altera IP page of
the Altera website.
HardCopy IV GX HardCopy Compilation
®
Stratix
(2) Final
Stratix GX Final
Stratix II (2) Final
Stratix II GX Final
Stratix III (2) Final
Stratix IV (1) Final
Stratix V (1)
Refer to the What’s New in Altera IP page of
the Altera website.
Other device families No support
Notes to Table 1–4:
(1) If you have only 27 MHz to drive the SDI MegaCore function in SD-SDI mode, you require an additional PLL to
generate a 67.5-MHz reference clock.
(2) The Cyclone series of devices, and Stratix, Stratix II, and Stratix III devices only support soft
serializer /deserializer (SERDES).
(3) Cyclone device support is limited to –6 speed grade devices.
(4) Transceiver dynamic configuration with channel reconfiguration mode is not supported for dual and triple standard
in EP4CGX110 and EP4CGX150 devices. Use transceiver dynamic reconfiguration with PLL reconfiguration mode
instead.
(5) The Cyclone V devices does not support the SDI Audio IP cores.
General Description
The Society of Motion Picture and Television Engineers (SMPTE) have defined an SDI
that video system designers use widely as an interconnect between equipment in
video production facilities.
The SDI MegaCore function can handle the following SDI data rates:
■ 270 megabits per second (Mbps) SD-SDI, as defined by SMPTE259M-1997 10-Bit
4:2:2 Component Serial Digital Interface
■ 1.5-Gbps HD-SDI, as defined by SMPTE292M-1998 Bit-Serial Digital Interface for
High Definition Television Systems
■ 3-Gbps SDI, as defined by SMPTE425M-AB 2006 3Gb/s Signal/Data Serial Interface–
Source Image Format Mapping
■ Preliminary support for dual link SDI, as defined by SMPTE372M-Dual Link
1.5Gb/s Digital Interface for 1920×1080 and 2048×1080 Picture Formats
February 2013 Altera Corporation Serial Digital Interface (SDI) MegaCore Function
User Guide
1–4 Chapter 1: About This MegaCore Function
■ Dual standard support for 270-Mbps and 1.5-Gbps SDI
■ Triple standard support for 270-Mbps, 1.5-Gbps, and 3-Gbps SDI
■ SMPTE425M Level A support (direct source image formatting)
■ SMPTE425M Level B support (dual link mapping)
General Description
Tab le 1– 5 lists the SDI standard support for various devices.
Table 1–5. SDI Standard Support
(1)
SDI Standard
Device Family
SD-SDI HD-SDI 3G-SDI HD-SDI Dual Link
(2)
Dual Standard Triple Standard
Arria GX vv v v v v
Arria II GX vv v v v v
Arria V vv v v v v
Cyclone v —— — — —
Cyclone
Cyclone
Cyclone
(EP4CGX15,
II v —— — — —
III v —— — — —
IV GX
v
—— — — —
EP4CGX30)
Cyclone
IV GX
(EP4CGX30 (F484),
EP4CGX50,
EP4CGX75,
vv v v v v
EP4CGX110,
EP4CGX150)
Cyclone V
(3)
vv v v v v
HardCopy IV GX vv v v v v
Stratix v —— — — —
Stratix GX vv — vv—
Stratix
II v —— — — —
Stratix
II GX vv v v v v
Stratix
III v —— — — —
Stratix IV
Stratix V
Notes to Table 1–5:
(1) All standards, other than SD-SDI, require a transceiver based or “GX” device.
(2) The HD-SDI dual link supports timing difference up to 40 ns between link A and link B, fulfilling the SMPTE372M requirement.
(3) The 3G-SDI standard is not supported in Cyclone V devices with transceiver speed grade 7, due to the excessive data rate required. For more
(4) Only Stratix IV and Stratix V variants with transceivers support all SDI rates.
(4)
(4)
information about the Cyclone V device, refer to the Overview for Cyclone V Device Family chapter in volume 1 of the Cyclone V Device
Handbook.
vv v v v v
vv v v v v
Serial Digital Interface (SDI) MegaCore Function February 2013 Altera Corporation
User Guide
Chapter 1: About This MegaCore Function 1–5
General Description
Tab le 1– 6 lists the HD-SDI standard video format specification.
Table 1–6. HD-SDI Video Format Specification
SMPTE292M Video Format
Sample per
Active Line
(1) (2)
Active Line
per Frame
Sample per
Tot a l L i n e
Total Line
per Frame
Frame Rate
2200 1125 60 Yes
2640 1125 50 Yes
274M 1920 x 1080 1920 1080
2200 1125 30 Yes
2640 1125 25 Yes
2750 1125 24 Yes
1650 750 60 Yes
1980 750 50 Yes
296M 1280 x 720 1280 720
3300 750 30 Yes
3960 750 25 Yes
4125 750 24 Yes
260M 1920 x 1035 1920 1035 2200 1125 30 Yes
295M 1920 x 1080 1920 1080
Notes to Table 1–6:
(1) The video formats support 4:2:2(YC’BC’R)/10-bit, 4:4:4(RGB)/(YC’BC’R), 4:4:4:4 (RGB+A)/(YC’BC’R+A)/10-bit, 4:4:4(YC’BC’R)/12-bit,
4:4:4(RGB)/12-bit, and 4:2:2 (YC’
(2) 3G-SDI is similar to HD-SDI except the data bit rate is twice that of HD-SDI or approximately 3 Gbps.
)/12-bit mapping structures.
BC’R
2376 1250 25 Yes
2376 1250 50 Yes
SDI 11.1
Support
OpenCore Plus Evaluation
With Altera’s free OpenCore Plus evaluation feature, you can perform the following
actions:
■ Simulate the behavior of a megafunction (Altera MegaCore function or AMPP
megafunction) within your system.
■ Verify the functionality of your design and quickly evaluate its size and speed
with ease.
■ Generate time-limited device programming files for designs that include
MegaCore functions.
■ Program a device and verify your design in hardware.
You are required to obtain a license for the MegaCore function only when you are
completely satisfied with its functionality and performance, and want to take your
design to production.
f For more information about OpenCore Plus hardware evaluation using the SDI, refer
to “OpenCore Plus Time-Out Behavior” on page 3–39 and AN 320: OpenCore Plus
Evaluation of Megafunctions.
SM
February 2013 Altera Corporation Serial Digital Interface (SDI) MegaCore Function
User Guide
1–6 Chapter 1: About This MegaCore Function
Resource Utilization
Resource Utilization
Tab le 1– 7 lists the typical resource utilization for various parameters with the
Quartus II software, version 11.1.
1 The resource utilization of the MegaCore function is based on the bidirectional
interface settings unless otherwise specified.
Table 1–7. Resource Utilization (Part 1 of 2)
Device Video Standard LEs Combinational ALUTs Logic Registers
SD-SDI — 834 640
HD-SDI — 919 683
3G-SDI — 1,161 865
Arria GX
Arria II GX
Arria V
Cyclone SD-SDI 875 — —
Cyclone II SD-SDI 867 — —
Cyclone III SD-SDI 874 — —
Cyclone III LS SD-SDI 929 — —
Cyclone IV GX
(EP4CGX15,
EP4CGX30)
Dual link HD-SDI — 1,906 1,423
Dual standard receiver — 1,188 831
Dual standard transmitter — 247 185
Triple standard — 1,794 1,215
SD-SDI — 839 680
HD-SDI — 978 833
3G HD-SDI — 1,259 1,015
Dual-Link HD-SDI — 2,029 1,711
Dual standard receiver — 1,257 926
Dual standard transmitter — 267 180
Triple standard — 1,891 1,305
SD-SDI — 1,189 920
HD-SDI — 1,185 910
3G-SDI — 1,444 1,142
Dual link HD-SDI — 2,446 1,880
Dual standard receiver — 1,605 1,175
Dual standard transmitter — 349 269
Triple standard — 2,273 1,677
SD-SDI 916 — —
Serial Digital Interface (SDI) MegaCore Function February 2013 Altera Corporation
User Guide
Chapter 1: About This MegaCore Function 1–7
Resource Utilization
Table 1–7. Resource Utilization (Part 2 of 2)
Device Video Standard LEs Combinational ALUTs Logic Registers
SD-SDI — 1,129 671
Cyclone IV GX
(EP4CGX50,
EP4CGX75,
EP4CGX110, and
EP4CGX150)
HD-SDI — 1,164 670
3G-SDI — 1,409 790
Dual link HD-SDI — 2,515 1,467
Dual standard receiver — 1,479 755
Dual standard transmitter — 364 229
Triple standard — 2,235 1,121
SD-SDI — 1,140 832
HD-SDI — 1,122 808
3G-SDI — 1,402 997
Cyclone V
Dual link HD-SDI — 2,351 1,696
Dual standard receiver — 1,539 1,042
Dual standard transmitter — 352 260
Triple standard — 2,217 1,508
Stratix SD-SDI 875 — —
Stratix II SD-SDI — 581 533
Stratix III SD-SDI — 602 565
SD-SDI 1,182 — —
Stratix GX
HD-SDI 1,316 — —
Dual link HD-SDI 2,703 — —
Dual standard 1,819 — —
SD-SDI — 834 640
HD-SDI — 919 683
3G-SDI — 1,161 865
Stratix II GX
Dual link HD-SDI — 1,906 1,423
Dual standard receiver — 1,188 831
Dual standard transmitter — 247 185
Triple standard — 1,794 1,215
SD-SDI — 839 680
HD-SDI — 978 833
3G-SDI — 1,259 1,015
Stratix IV GX
Dual link HD-SDI — 2,029 1,711
Dual standard receiver — 1,257 926
Dual standard transmitter — 267 180
Triple standard — 1,891 1,305
SD-SDI — 913 707
Stratix V
HD-SDI — 955 703
3G-SDI — 1,126 823
Dual link HD-SDI — 2,049 1,522
February 2013 Altera Corporation Serial Digital Interface (SDI) MegaCore Function
User Guide
1–8 Chapter 1: About This MegaCore Function
Resource Utilization
Serial Digital Interface (SDI) MegaCore Function February 2013 Altera Corporation
User Guide
Design Flow
2. Getting Started
To evaluate the SDI MegaCore function using the OpenCore Plus feature, follow these
steps in your design flow:
1. Obtain and install the SDI MegaCore function.
The SDI MegaCore function is part of the MegaCore IP Library, which is
distributed with the Quartus II software and downloadable from the Altera
website at www.altera.com.
f For system requirements and installation instructions, refer to Altera
Software Installation & Licensing.
Figure 2–1 shows the directory structure after you install the SDI MegaCore function,
where
<
path> is the installation directory. The default installation directory on
Windows is c:\altera\<version>; on Linux, it is /opt/altera<version>.
February 2013 Altera Corporation Serial Digital Interface (SDI) MegaCore Function
User Guide
2–2 Chapter 2: Getting Started
ip
Contains the Altera MegaCore IP Library and third-party IP cores.
common
Contains shared components.
sdi
Contains the SDI MegaCore function files.
lib
Contains encrypted lower-level design files and other support files.
<path>
Installation directory.
simulation
Contains simulation files.
hdsdi_3g
Contains the HD-SDI 3 Gbps simulation files.
testbench
Contains the testbench files.
quartus
Contains the Quartus II NativeLink project.
pattern_gen
Contains the pattern generator files for the testbench.
testbench
Contains the testbench files.
quartus
Contains the Quartus II NativeLink project.
pattern_gen
Contains the pattern generator files for the testbench.
hdsdi_dual_link
Contains the HD-SDI dual link simulation files.
testbench
Contains the testbench files.
modelsim
Contains the ModelSim simulation files.
quartus
Contains the Quartus II NativeLink project.
pattern_gen
Contains the pattern generator files for the testbench.
hdsdi
Contains the HD-SDI simulation files.
altera
Contains the Altera MegaCore IP Library.
example
Contains design examples.
s2gx_tr
Contains a design example for Stratix II GX, see AN 339: Serial
Digital Interface Demonstration for Stratix II GX Devices.
a2gx_tr
Contains a design example for Arria II GX.
Figure 2–1. Directory Structure
Design Flow
Serial Digital Interface (SDI) MegaCore Function February 2013 Altera Corporation
User Guide
1. Create a custom variation of the SDI MegaCore function.
2. Implement the rest of your design using the design entry method of your choice.
3. Use the IP functional simulation model to verify the operation of your design.
f For more information on IP functional simulation models, refer to the
Simulating Altera Designs chapter in volume 3 of the Quartus II Handbook.
Chapter 2: Getting Started 2–3
SDI Walkthrough
4. Use the Quartus II software to compile your design.
1 You can also generate an OpenCore Plus time-limited programming file,
which you can use to verify the operation of your design in hardware.
5. Purchase a license for the SDI MegaCore function.
After you have purchased a license for the SDI MegaCore function, follow these
additional steps:
1. Set up licensing.
2. Generate a programming file for the Altera device or devices on your board.
3. Program the Altera device or devices with the completed design.
SDI Walkthrough
This walkthrough explains how to create an SDI design using the MegaWizard
Plug-In Manager and the Quartus II software. After you generate a custom variation
of the SDI MegaCore function, you can incorporate it into your overall project.
1 You can alternatively use the IP Advisor to help start your SDI MegaCore design. On
the Quartus II Tools menu, point to Advisors, and then click IP Advisor. The IP
Advisor guides you through a series of recommendations for selecting,
parameterizing, evaluating, and instantiating an SDI MegaCore function into your
design. It then guides you through a complete Quartus II compilation of your project.
This walkthrough requires the following steps:
1. “Creating a New Quartus II Project”
2. “Launching MegaWizard Plug-In Manager”
3. “Parameterizing”
4. “Setting Up Simulation”
5. “Generating Files”
Creating a New Quartus II Project
You must create a new Quartus II project with the New Project Wizard, which
specifies the working directory for the project, assigns the project name, and
designates the name of the top-level design entity. To create a new project, follow
these steps:
1. Choose Programs > Altera > Quartus II <version> (Windows Start menu) to run
the Quartus II software. Alternatively, you can use the Quartus II Web Edition
software.
2. On the File menu, click New Project Wizard.
3. Click Next in the New Project Wizard: Introduction page (the introduction page
does not display if you turned it off previously).
February 2013 Altera Corporation Serial Digital Interface (SDI) MegaCore Function
User Guide
2–4 Chapter 2: Getting Started
SDI Walkthrough
4. In the New Project Wizard: Directory, Name, Top-Level Entity page, enter the
following information:
a. Specify the working directory for your project. For example, this walkthrough
uses the c:\altera\projects\sdi_project directory.
1 The Quartus II software automatically specifies a top-level design entity
that has the same name as the project. This walkthrough assumes that the
names are the same.
b. Specify the name of the project. This walkthrough uses project for the project
name.
5. Click Next to close this page and display the New Project Wizard: Add Files page.
1 When you specify a directory that does not already exist, a message
prompts you to create a specified directory. Click Yes to create the directory.
6. If you installed the MegaCore IP Library in a different directory from where you
installed the Quartus II software, you must add the user libraries:
a. Click User Libraries.
b. Type <path>
\ip
into the Library name field, where <path> is the directory in
which you installed the SDI.
c. Click Add to add the path to the Quartus II project.
d. Click OK to save the library path in the project.
7. Click Next to close this page and display the New Project Wizard: Family &
Device Settings page.
8. On the New Project Wizard: Family & Device Settings page, choose the target
device family in the Family list.
9. The remaining pages in the New Project Wizard are optional. Click Finish to
complete the Quartus II project.
Launching MegaWizard Plug-In Manager
To launch the MegaWizard Plug-In Manager in the Quartus II software, follow these
steps:
1. On the Tools menu, click MegaWizard Plug-In Manager.
1 For more information about how to use the MegaWizard Plug-In Manager,
refer to Quartus II Help.
2. Specify that you want to create a new custom megafunction variation and click
Next.
3. Expand the Interfaces > SDI folder and click SDI <version>.
4. Select the output file type for your design; the wizard supports VHDL and Verilog
HDL.
Serial Digital Interface (SDI) MegaCore Function February 2013 Altera Corporation
User Guide
Chapter 2: Getting Started 2–5
SDI Walkthrough
5. The MegaWizard Plug-In Manager shows the project path that you specified in the
New Project Wizard. Append a variation name for the MegaCore function output
files <project path>\<variation name>.
6. Click Next to display the Parameter Settings page for the SDI MegaCore function.
1 You can change the page that the MegaWizard Plug-In Manager displays by
clicking Next or Back at the bottom of the dialog box. You can move
directly to a named page by clicking the Parameter Settings, EDA, or
Summary tab.
Also, you can directly display individual parameter settings by clicking on
the Protocol Options, Transceiver Options, or Receiver/Transmitter
Options tab.
Parameterizing
To parameterize your MegaCore function, follow these steps:
1. Select the video standard. Some of the standards may be grayed out, because they
are not supported on the currently selected device family.
2. Select Bidirectional, Receiver, or Tr an sm i tt e r interface direction.
3. Click the Transceiver Options tab.
4. Under Transceiver and Protocol, click Generate transceiver and protocol blocks.
5. For SD-SDI only, turn on Use soft logic for transceiver to implement the
transceiver in logic, rather than using Stratix GX, Stratix II GX or Stratix IV GX
transceivers.
6. Select the starting channel number.
7. Turn on Use PLL reconfiguration for transceiver dynamic reconfiguration if you
select an EP4CGX110 or EP4CGX150 device for Cyclone IV GX using dual and
triple standards. You may turn on this option for other Cyclone IV GX devices but
it is not recommended.
8. Turn on Enable TX PLL select for 1/1.000 and 1/1.001 data rate reconfiguration if
your design requires two serial input clocks to the TX block.
1 This feature is only available for the Arria II, Stratix IV GX, and
HardCopy IV GX device families.
9. Click the Receiver/Transmitter Options tab.
10. Turn on the required receiver options.
11. Turn on the required transmitter options.
12. Click Next (or the EDA tab) to display the EDA page.
f For more information about parameters, refer to “Parameters” on page 3–56 and, for
more information about the protocol options, refer to Table 3–20 on page 3–56.
For more information about the transceiver options, refer to Table 3–21 on page 3–56.
For more information about the receiver/transmitter options, refer to Table 3–22 on
page 3–57.
February 2013 Altera Corporation Serial Digital Interface (SDI) MegaCore Function
User Guide
2–6 Chapter 2: Getting Started
SDI Walkthrough
Setting Up Simulation
An IP functional simulation model is a cycle-accurate VHDL or Verilog HDL model
produced by the Quartus II software. The model allows for fast functional simulation
of IP using industry-standard VHDL and Verilog HDL simulators.
c You may only use these models for simulation and expressly not for synthesis or any
other purposes. Using these models for synthesis creates a nonfunctional design.
To generate an IP functional simulation model for your MegaCore function, follow
these steps:
1. Turn on Generate simulation model.
2. Some third-party synthesis tools can use a netlist that contains only the structure
of the MegaCore function, but not detailed logic, to optimize performance of the
design that contains the MegaCore function. If your synthesis tool supports this
feature, turn on Generate netlist.
3. Click Next (or the Summary tab) to display the Summary page.
Generating Files
You can use the check boxes on the Summary page to enable or disable the generation
of specified files. A gray checkmark indicates a file that is automatically generated; a
red checkmark indicates an optional file.
You can click Back to display the previous page, or click Parameters Settings, EDA,
or Summary, to change any of the MegaWizard options.
To generate the files, follow these steps:
1. Turn on the files you wish to generate.
1 At this stage, you can still click Back to display any of the other pages in the
2. To generate the specified files and close the MegaWizard Plug-In Manager, click
Finish.
1 The generation phase may take several minutes to complete.
1 The Quartus II IP File (.qip) is a file generated by the parameter editor, and
MegaWizard Plug-In Manager to change any of the parameters.
contains information about the generated IP core. You are prompted to add
this .qip file to the current Quartus II project at the time of file generation.
In most cases, the .qip file contains all of the necessary assignments and
information required to process the core or system in the Quartus II
compiler. Generally, a single .qip file is generated for each MegaCore
function or system in the Quartus II compiler.
3. Click Exit to close the Generation window.
Serial Digital Interface (SDI) MegaCore Function February 2013 Altera Corporation
User Guide
Chapter 2: Getting Started 2–7
SDI Walkthrough
Tab le 2– 1 describes the generated files and other files that may be in your project
directory. The names and types of files specified in the MegaWizard Plug-In Manager
report vary based on whether you created your design with VHDL or Verilog HDL.
Table 2–1. Generated Files
Extension Description
A MegaCore function variation file, which defines a VHDL or Verilog HDL description of
<variation name>.v or .vhd
the custom MegaCore function. Instantiate the entity defined by this file inside of your
design. Include this file when compiling your design in the Quartus II software.
<variation name>.cmp
<variation name>.bsf
A VHDL component declaration file for the MegaCore function variation. Add the
contents of this file to any VHDL architecture that instantiates the MegaCore function.
Quartus II symbol file for the MegaCore function variation. You can use this file in the
Quartus II block diagram editor.
<variation name>.html MegaCore function report file.
This XML file describes the MegaCore pin attributes to the Quartus II Pin Planner.
<variation name>.ppf
MegaCore pin attributes include pin direction, location, I/O standard assignments, and
drive strength. If you launch IP Toolbench outside of the Pin Planner application, you
must explicitly load this file to use Pin Planner.
<variation name>_sdi.sdc Contains timing constraints for your SDI variation.
Quartus II file that sets the Quartus II to use TimeQuest timing analyzer and patches the
<variation name>_constraints.tcl
generated .sdc script with a new clock name. If your top-level design clock pin names do
not match the default clock pin names or a prefixed version, edit the assignments in this
file.
<variation name>.vo or .vho VHDL or Verilog HDL IP functional simulation model.
<variation name>_bb.v
A Verilog HDL black-box file for the MegaCore function variation. Use this file when
using a third-party EDA tool to synthesize your design.
<variation name>.qip Contains Quartus II project information for your MegaCore function variations.
You can now integrate your custom MegaCore function variation into your design,
simulate, and compile.
February 2013 Altera Corporation Serial Digital Interface (SDI) MegaCore Function
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ALTGXB
RECONFIG (1)
- SD 270 Mbps
- HD 1.485 Gbps
- 3G 2.97 Gbps
SDI Pattern Generator
SDI IP CORE - Receiver
SDI IP CORE - Transmitter
SDI TRANSMIT TEST
DUT
SDI RECEIVE TEST
Transmitter Data
Descrambler
Transmitter TRS
Counter
Receiver TRS
Checker
Receiver Lock
Checker
Receiver Line
Checker
Simulating the Design
Simulating the Design
This section describes the following simulation techniques:
■ Simulate with IP Functional Simulation Models
■ Simulating with the ModelSim Simulator
■ Simulating in Third-Party Simulation Tools Using NativeLink
Testbench
In general, all testbenches are constructed in such a way that the serial transmit data is
looped back to receiver. Figure 2–2 shows how the serial transmit data is looped back
to the receiver in the testbench.
Figure 2–2. General Simulation Testbench
Serial Digital Interface (SDI) MegaCore Function February 2013 Altera Corporation
User Guide
Note to Figure 2–2:
(1) For dual or triple standard only.
Chapter 2: Getting Started 2–9
Simulating the Design
A testbench basically consists of transmit test and receive test. The transmit test
accepts the same serial data as the receive device under test (DUT), deserializes and
decodes the transmitted data, and computes the number of time reference signals
(TRS) seen. The receive test verifies the features that are supported by the SDI receiver
by monitoring the received data, status bits, line numbering and other related
features.
For dual and triple standard modes, the SDI receiver requires reconfiguration. The
SDI receiver reconfigures using transceiver dynamic reconfiguration to perform
autodetection and locking to different SDI video standards. For more details about
transceiver dynamic reconfiguration, refer to “Transceiver Dynamic Reconfiguration
for Dual Standard and Triple Standard Receivers” on page 3–27.
Simulate with IP Functional Simulation Models
You can simulate your design using the MegaWizard-generated VHDL and Verilog
HDL IP functional simulation models.
You can use the IP functional simulation model with any Altera-supported VHDL or
Verilog HDL simulator.
To use the IP functional simulation model that you created in “Setting Up Simulation”
on page 2–6, create a suitable testbench.
f For more information about IP functional simulation models, refer to the Simulating
Altera Designs chapter in volume 3 of the Quartus II Handbook.
Simulating with the ModelSim Simulator
For Arria and Stratix series of devices, Altera provides two fixed testbenches as
examples in the simulation\modelsim\<video standard>\modelsim directory, where
<video standard> is hdsdi or hdsdi_dual_link. The testbenches instantiate the design
and test the HD-SDI or dual link mode of operation. To use one of these testbenches
with the ModelSim
1. In a text editor, open the simulation batch file, simulation\modelsim\<video
standard>\modelsim\sdi_sim.bat. Edit it to point to your installation of the
ModelSim-Altera simulator and the Quartus II software, and edit the path:
set PATH = %MODELSIM_DIR%\win32aloem
set QUARTUS_ROOTDIR=c:\altera\81\quartus
For example, edit
1 Where <video standard> is hdsdi or hdsdi_dual_link.
2. Start the ModelSim-Altera simulator.
3. Run sdi_sim.bat in the simulation\modelsim\<video standard>\modelsim
directory. This file compiles the design and starts the ModelSim-Altera simulator.
A selection of signals appears on the waveform viewer. The simulation runs
automatically, providing a pass/fail indication on completion.
®
-Altera simulator, follow these steps:
QUARTUS_ROOTDIR=/tools/acds/11.0/157/linux32/quartus
.
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Simulating the Design
For Cyclone IV GX devices, Altera provides two new fixed testbenches in the
simulation\modelsim\<video standard>\<DPRIO mode>\modelsim directory, where
<video standard>\<DPRIO mode> is trsdi_c4gx\channel_reconfig or
trsdi_c4gx\pll_reconfig. The testbenches instantiate the design and test the triple
standard mode of operation using Cyclone IV GX devices. The testbenches also
demonstrate the transceiver dynamic reconfiguration with channel and phase-locked
loop (PLL) reconfiguration modes. To use one of these testbenches with the
ModelSim-Altera simulator, follow these steps:
1. In a text editor, open the simulation .do file,
simulation\modelsim\<video standard>\<DPRIO mode>\modelsim\sdi_sim.do.
Edit it to point to your installation of the ModelSim-Altera simulator, and edit the
path:
set QUARTUS_ROOTDIR = C:\altera\<version>\quartus
1 Where <version> is the version of the Quartus II software you are using.
2. Start the ModelSim-Altera simulator.
3. Run sdi_sim.do in the
simulation\modelsim\<video standard>\<DPRIO mode>\modelsim directory.
This file compiles the design and starts the ModelSim-Altera simulator. A selection
of signals appears on the waveform viewer.
To test the transmitter operation, the testbench generates a reference clock and parallel
video data. The design encodes and serializes this parallel video data. The serial
output is sampled, non-return to zero inverted (NRZI) decoded, descrambled, and
then reconstructed into parallel form. The testbench detects the presence of TRS
tokens (end of active video (EAV) and start of active video (SAV)) in the output to
check the correct operation.
To test the receiver operation, the testbench connects the serial transmitter data to the
receiver input. The testbench checks that the receiver achieves word alignment and
verifies that the extracted LN is correct.
Simulating in Third-Party Simulation Tools Using NativeLink
You can perform a simulation in a third-party simulation tool from within the
Quartus II software, using NativeLink.
f For more information about NativeLink, refer to the Simulating Altera Designs chapter
in volume 3 of the Quartus II Handbook.
Altera provides the following three Quartus II projects for use with NativeLink in the
ip\altera\sdi\simulation directory:
■ HD-SDI in the hdsdi directory
■ HD-SDI 3 Gbps in the hdsdi_3g directory
■ HD-SDI dual link in the hdsdi_dual_link directory
■ Triple standard SDI in the trsdi directory
Serial Digital Interface (SDI) MegaCore Function February 2013 Altera Corporation
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Chapter 2: Getting Started 2–11
SDI triple standard transmitter
starting_channel_number = 0
Transceiver Bank 1
SYSTEM TOP LEVEL
SDI triple standard receiver
starting_channel_number = 4
rx_serial_refclk_top1tx_serial_refclk_top1
Specifying Constraints
To set up simulation in the Quartus II software using NativeLink, follow these steps:
1. On the File menu, click Open Project. Browse to the desired directory: hdsdi,
hdsdi_3g, hdsdi_dual_link, or trsdi.
2. Open sdi_sim.qpf.
3. Check that the absolute path to your third-party simulator executable is set. On the
Tools menu, click Options and select EDA Tools Options.
4. On the Processing menu, point to Start and click Start Analysis & Elaboration.
5. On the Tools menu, point to Run EDA Simulation Tool and click EDA RTL
Simulation.
Specifying Constraints
You must apply the Altera-provided timing constraint file in Synopsys Design
Constraints File (.sdc) format and the additional Tcl Script File (.tcl) to ensure the SDI
MegaCore function meets the design timing requirements.
To ad d the .sdc file to your project, click Add/Remove Files in Project on the Project
menu and browse to select <variation name>_sdi.sdc file.
To add the additional .tcl file, you must compile your design and perform post
compilation timing analysis using the TimeQuest timing analyzer. On the
Assignments menu, click Use TimeQuest Timing Analyzer during compilation, and
click OK.
You may have to further edit your scripts if your design requires single channel or
multiple channels.
Single Channel
The following section describes what you must do if your design requires a single
channel using SDI triple standard transmitter and receiver instances as shown in
Figure 2–3 on page 2–11.
Figure 2–3. Instantiating Single Channel of SDI Instances
1 The SDI instances must have a unique starting channel number if they are merged
into a same quad or bank.
To specify the constraints, follow these steps:
1. Parameterize and generate your SDI MegaCore functions—SDI triple standard
transmitter and receiver.
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SDI triple standard transmitter A
starting_channel_number = 0
Transceiver Bank 1
SYSTEM TOP LEVEL
SDI triple standard transmitter B
starting_channel_number = 8
SDI triple standard receiver B
starting_channel_number = 12
SDI triple standard receiver A
starting_channel_number = 4
SDI triple standard transmitter A
starting_channel_number = 0
rx_serial_refclk_top1tx_serial_refclk_top1
SDI triple standard transmitter B
starting_channel_number = 8
SDI triple standard receiver B
starting_channel_number = 12
SDI triple standard receiver A
starting_channel_number = 4
Transceiver Bank 2
Specifying Constraints
2. Edit the Tcl script so that the transceiver top-level reference clock matches the
clock pin names that you have chosen for your design, for example
tx_serial_refclk_top1
to
tx_serial_refclk_top1
. Locate
.
tx_serial_refclk_name
in the script and change
1 The SDI triple standard transmitter has a transceiver top-level reference
clock,
tx_serial_refclk
.
3. Execute the Tcl script to patch the generated .sdc script with the new clock names.
1 A back-up copy of the .sdc script is created before the patch is made, and
any edits that were previously made to the .sdc script are preserved.
4. Execute the Tcl script in the Quartus II software, and follow these steps:
a. On the Tools menu, click Tcl script.
b. Select the Tcl script of the instance SDI triple standard transmitter, and click
Run.
5. Perform steps 2 to 4 for the SDI triple standard receiver instance.
Multiple Channels
The following section describes what you must do if your design requires multiple
channels using four instances of SDI triple standard transmitter and four instances of
SDI triple standard receiver. In this case, assume that you must fit all instances into
Transceiver Bank 1 and 2 as shown in Figure 2–4, and the SDI instances in both banks
have the same video standard. You do not have to regenerate the SDI instances in
Transceiver Bank 2.
Figure 2–4. Instantiating Multiple Channels of SDI Instances Sharing Same Reference Clock
Serial Digital Interface (SDI) MegaCore Function February 2013 Altera Corporation
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Chapter 2: Getting Started 2–13
tx_serial_refclk_top2
tx_serial_refclk_top1
SDI triple standard transmitter A
starting_channel_number = 0
Transceiver Bank 1
SYSTEM TOP LEVEL
SDI triple standard transmitter B
starting_channel_number = 8
SDI triple standard receiver B
starting_channel_number = 12
SDI triple standard receiver A
starting_channel_number = 4
SDI triple standard transmitter A
starting_channel_number = 0
rx_serial_refclk_top1
rx_serial_refclk_top2
SDI triple standard transmitter B
starting_channel_number = 8
SDI triple standard receiver B
starting_channel_number = 12
SDI triple standard receiver A
starting_channel_number = 4
Transceiver Bank 2
Specifying Constraints
To specify the constraints, perform the following steps:
1. Parameterize and generate your SDI MegaCore functions—SDI triple standard
transmitter A, SDI triple standard transmitter B, SDI triple standard receiver A,
and SDI triple standard receiver B—with their unique starting channel number.
2. Edit the Tcl script so that the transceiver top-level reference clock matches the
name of the clock pin connected to SDI triple standard transmitter A, for example
tx_serial_refclk_top1
to
tx_serial_refclk_top1
. Locate
.
tx_serial_refclk_name
in the script and change
3. Execute the Tcl script to patch the generated .sdc script with the new clock names.
1 A back-up copy of the .sdc script is created before the patch is made, and
any edits that were previously made to the .sdc script are preserved.
4. Execute the Tcl script in the Quartus II software, and perform the following steps:
a. On the Tools menu, click Tcl script.
b. Select the Tcl script of the instance SDI triple standard transmitter A, and click
Run.
5. Perform steps 2 to 4 for the other three instances.
Figure 2–5. Instantiating Multiple Channels of SDI Instances Sharing Multiple Reference Clocks
To specify constraints for multiple channels of SDI MegaCore function with multiple
top-level reference clocks as shown in Figure 2–5, perform the following steps:
1. For the SDI instances in Transceiver Bank 1, perform steps 1 to 5 you would do for
SDI instances sharing the same reference clock.
2. For the SDI instances in Transceiver Bank 2, duplicate an .sdc script for SDI triple
standard transmitter A and SDI triple standard receiver A in Transceiver Bank 2.
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1 You are not required to duplicate .sdc script for SDI triple standard
transmitter B and SDI triple standard receiver B in Transceiver Bank 2.
Instances with same video standard can share an .sdc script.
3. Edit the .sdc script so that the reference clock name matches the name of the clock
pin connected to SDI triple standard transmitter A, for example
tx_serial_refclk_top2
to
tx_serial_refclk_top2
4. Edit another .sdc script so that the reference clock name matches the name of the
clock pin connected to SDI triple standard receiver A, for example
rx_serial_refclk_top2
change to
5. Add these two duplicate .sdc scripts to your project. On the Project menu, click
Add/Remove Files in Project and browse to select the scripts.
rx_serial_refclk_top2
. Locate
.
. Locate
tx_serial_refclk_name
set rx_serial_refclk_name
.
in the script and change
Compiling the Design
in the script and
Compiling the Design
You can use the Quartus II software to compile your design. For instructions about
performing compilation, refer to Quartus II Help.
You can find an example design using an SDI MegaCore function in the
ip/sdi/example directory. This design is targeted at the Stratix II GX audio video
development kit.
f For more information about the example design, refer to AN 339: Serial Digital Interface
Demonstration for Stratix II GX Devices, and for information about the development kit,
refer to Audio Video Development Kit, Stratix II GX Edition.
Programming a Device
After you have compiled the example design, you can program your targeted Altera
device to verify the design in hardware.
With Altera's free OpenCore Plus evaluation feature, you can evaluate the SDI
MegaCore function before you obtain a license. OpenCore Plus evaluation allows you
to generate an IP functional simulation model, and produce a time-limited
programming file.
f For more information about OpenCore Plus hardware evaluation using the SDI
MegaCore function, refer to “OpenCore Plus Evaluation” on page 1–5, “OpenCore
Plus Time-Out Behavior” on page 3–39, and AN 320: OpenCore Plus Evaluation of
Megafunctions.
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Chapter 2: Getting Started 2–15
Setting Up Licensing
Setting Up Licensing
You must purchase a license for the MegaCore function only when you are completely
satisfied with its functionality and performance and want to take your design to
production.
After you purchase a license for SDI MegaCore function, you can request a license file
from the Altera website at www.altera.com/licensing and install it on your computer.
When you request a license file, Altera emails you a license.dat file. If you do not have
Internet access, contact your local Altera representative.
February 2013 Altera Corporation Serial Digital Interface (SDI) MegaCore Function
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Setting Up Licensing
Serial Digital Interface (SDI) MegaCore Function February 2013 Altera Corporation
User Guide
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