Altera Serial Digital Interface MegaCore Function User Manual

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Serial Digital Interface (SDI) MegaCore Function User Guide

Serial Digital Interface (SDI) MegaCore Function

User Guide

101 Innovation Drive San Jose, CA 95134

www.altera.com

UG-SDI1005-16.0

Document last updated for Altera Complete Design Suite version:

Document publication date:

12.1

February 2013

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© 2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

ISO

9001:2008

Registered

February 2013 Altera Corporation Serial Digital Interface (SDI) MegaCore Function

User Guide

Chapter 1. About This MegaCore Function

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1

Release Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2

Device Family Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3

OpenCore Plus Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–5

Resource Utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–6

Chapter 2. Getting Started

Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1

SDI Walkthrough . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3

Creating a New Quartus II Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3

Launching MegaWizard Plug-In Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4

Parameterizing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5

Setting Up Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6

Generating Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6

Simulating the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–8

Testbench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–8

Simulate with IP Functional Simulation Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–9

Simulating with the ModelSim Simulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–9

Simulating in Third-Party Simulation Tools Using NativeLink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–10

Specifying Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–11

Single Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–11

Multiple Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–12

Compiling the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14

Programming a Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14

Setting Up Licensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–15

Chapter 3. Functional Description

Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2

Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2

HD-SDI LN Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–4

HD-SDI CRC Generation and Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–4

Scrambling and NRZI Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–5

Transceiver Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–5

Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–6

NRZI Decoding and Descrambling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–8

Word Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–8

Video Timing Flags Extraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–9

RP168 Switching Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–9

HD-SDI LN Extraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–10

HD-SDI CRC Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–10

Accessing Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–10

Transceiver Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–12

Transceiver—Soft-Logic Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–12

Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–12

Transmitter Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–12

Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–13

February 2013 Altera Corporation Serial Digital Interface (SDI) MegaCore Function

User Guide

iv Contents

Receiver Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–13

Transceiver—Stratix GX Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–13

Transmitter Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–13

Receiver Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–15

Transmitter Transceiver Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–16

Receiver Transceiver Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–17

Transceiver—Arria GX, Arria II GX, Arria V, Cyclone IV GX, Cyclone V, Stratix II GX, Stratix IV GX,

and Stratix V Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–18

Transmitter Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–19

Receiver Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–22

Transmitter Transceiver Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–23

Receiver Transceiver Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–24

Locking to the Incoming SDI Stream . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–25

Transceiver Dynamic Reconfiguration for Dual Standard and Triple Standard Receivers . . . . . . 3–27

Transceiver Dynamic Reconfiguration with Channel Reconfiguration Mode—Arria II GX,

HardCopy IV GX, Stratix GX, Stratix II GX, and

Stratix IV GX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–27

Transceiver Dynamic Reconfiguration with PLL Reconfiguration Mode—Cyclone IV GX . . . 3–33

Reset Requirement During Reconfiguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–36

OpenCore Plus Time-Out Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–39

Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–39

Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–56

MegaCore Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–57

Chapter 4. SDI Audio IP Cores

SDI Audio Embed MegaCore Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2

Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3

Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–4

Register Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–8

SDI Audio Extract MegaCore Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–10

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–10

Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–11

Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–12

Register Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–15

Clocked Audio Input MegaCore Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–17

Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–17

Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–17

Register Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–18

Clocked Audio Output MegaCore Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–19

Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–19

Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–19

Register Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–20

AES Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–21

Avalon-ST Audio Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–21

Instantiating the IP Cores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–23

Simulating the Testbench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–24

Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–25

Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–26

SDI Transmitter P0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–26

SDI Duplex . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–26

Audio Extract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–27

AES Output Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–27

AES Input Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–27

Serial Digital Interface (SDI) MegaCore Function February 2013 Altera Corporation User Guide

Contents v

Audio Embed P0/P1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–27

Video Pattern Generator P0/P1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–27

Audio Pattern Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–27

Ancillary Data Insertion P0/P1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–27

Transceiver Dynamic Reconfiguration Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–27

Hardware and Software Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–28

Hardware Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–28

Running the Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–30

Transmit SD-SDI with Embedding of Audio Group 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–30

Transmit HD-SDI with Embedding of Audio Group 1 and 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–31

Transmit 3G-SDI Level A with Embedding of Audio Group 1, 2 and 3 . . . . . . . . . . . . . . . . . . . . 4–32

Transmit 3G-SDI Level B with Embedding of Audio Group 1, 2, 3 and 4 . . . . . . . . . . . . . . . . . . 4–32

Appendix A. Constraints

Specifying TimeQuest Timing Analyzer Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–1

Specify Clock Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–4

Set Multicycle Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–5

Specify Clocks that are Exclusive or Asynchronous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–5

Define the Setup and Hold Relationship between 135-MHz Clocks and 337.5-MHz Zero-degree

Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–6

Minimize Timing Skew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–7

Constraints for the SDI Soft Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–7

Non Cyclone Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–8

Classic Timing Analyzer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–8

TimeQuest Timing Analyzer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–8

Cyclone Devices Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–9

Classic Timing Analyzer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–9

TimeQuest Timing Analyzer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–9

Appendix B. Clocking

Appendix C. Receive and Retransmit

Loopback FIFO Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C–1

Additional Information

Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1

How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–3

Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–3

February 2013 Altera Corporation Serial Digital Interface (SDI) MegaCore Function

User Guide

vi Contents

Serial Digital Interface (SDI) MegaCore Function February 2013 Altera Corporation User Guide

1. About This MegaCore Function

This user guide describes the Altera® Serial Digital Interface (SDI) MegaCore function and the accompanying SDI Audio IP cores.

The SDI MegaCore function implements a receiver, transmitter, or full-duplex SDI at standard definition (SD), high definition (HD), or 3 gigabits per second (3G). The SDI MegaCore function also supports dual standard (HD-SDI and SD-SDI) and triple standard (SD-SDI, HD-SDI, and 3G-SDI). These modes provide automatic receiver rate detection.

You can instantiate the SDI Audio IP cores with the SDI MegaCore function.

1 For more information about the SDI Audio cores, refer to “SDI Audio IP Cores” on

page 4–1.

Features

Tab le 1– 1 lists the features of the SDI MegaCore function.

Table 1–1. SDI MegaCore Function Features

Feature Description

■ Multiple SDI standards and video formats (refer to Table 1–5 and Table 1–6)

Support

Transmitter

Receiver

MegaWizard™ Plug-In Manager

IP functional simulation models ■ Use in Altera-supported VHDL and Verilog HDL simulators

■ RP168 video switch line requirement

■ OpenCore Plus evaluation

■ Cyclical redundancy check (CRC) encoding (HD only)

■ Line number (LN) insertion (HD only)

■ Word scrambling

■ Transmitter clock multiplexer (optional)

■ CRC decoding (HD only)

■ LN extraction (HD only)

■ Framing and extraction of video timing signals

■ Word alignment and descrambling

■ Easy-to-use parameter editor

February 2013 Altera Corporation Serial Digital Interface (SDI) MegaCore Function

User Guide

1–2 Chapter 1: About This MegaCore Function

Release Information

Tab le 1– 2 lists information about this release of the SDI MegaCore function.

Table 1–2. Release Information

Item Description

Version 12.1

Release Date January 2013

Ordering Code IP-SDI

Product ID(s)

Vendor ID 6AF7

f For more information about this release, refer to the MegaCore IP Library Release Notes

and Errata.

00AE (SDI MegaCore function)

00EF (SDI Audio cores)

Altera verifies that the current version of the Quartus previous version of each MegaCore function. The MegaCore IP Library Release Notes

and Errata report any exceptions to this verification. Altera does not verify

compilation with MegaCore function versions older than one release.

Device Family Support

Tab le 1– 3 defines the device support levels for Altera IP cores.

Table 1–3. Altera IP Core Device Support Levels

FPGA Device Families HardCopy Device Families

Preliminary support—The IP core is verified with preliminary timing models for this device family. The IP core meets all functional requirements, but might still be undergoing timing analysis for the device family. It can be used in production designs with caution.

Final support—The IP core is verified with final timing models for this device family. The IP core meets all functional and timing requirements for the device family and can be used in production designs.

Tab le 1– 4 shows the level of support offered by the SDI MegaCore function for each

Altera device family.

II software compiles the

HardCopy Companion—The IP core is verified with preliminary timing models for the HardCopy companion device. The IP core meets all functional requirements, but might still be undergoing timing analysis for the HardCopy device family. It can be used in production designs with caution.

HardCopy Compilation—The IP core is verified with final timing models for the HardCopy device family. The IP core meets all functional and timing requirements for the device family and can be used in production designs.

Table 1–4. Device Family Support (Part 1 of 2)

Device Family Support

GX Final

Arria

Arria II (1) Final

Arria V

Serial Digital Interface (SDI) MegaCore Function February 2013 Altera Corporation User Guide

Refer to the What’s New in Altera IP page of

the Altera website.

Chapter 1: About This MegaCore Function 1–3

General Description

Table 1–4. Device Family Support (Part 2 of 2)

Device Family Support

Cyclone

Final (3)

Cyclone II (2) Final

Cyclone III (2) Final

Cyclone III LS (2) Final

Cyclone IV GX (4) Final

Cyclone V (5)

HardCopy

III/ IV E HardCopy Compilation

Refer to the What’s New in Altera IP page of

the Altera website.

HardCopy IV GX HardCopy Compilation

Stratix

(2) Final

Stratix GX Final

Stratix II (2) Final

Stratix II GX Final

Stratix III (2) Final

Stratix IV (1) Final

Stratix V (1)

Refer to the What’s New in Altera IP page of

the Altera website.

Other device families No support

Notes to Table 1–4:

(1) If you have only 27 MHz to drive the SDI MegaCore function in SD-SDI mode, you require an additional PLL to

generate a 67.5-MHz reference clock.

(2) The Cyclone series of devices, and Stratix, Stratix II, and Stratix III devices only support soft

serializer /deserializer (SERDES). (3) Cyclone device support is limited to –6 speed grade devices. (4) Transceiver dynamic configuration with channel reconfiguration mode is not supported for dual and triple standard

in EP4CGX110 and EP4CGX150 devices. Use transceiver dynamic reconfiguration with PLL reconfiguration mode

instead. (5) The Cyclone V devices does not support the SDI Audio IP cores.

General Description

The Society of Motion Picture and Television Engineers (SMPTE) have defined an SDI that video system designers use widely as an interconnect between equipment in video production facilities.

The SDI MegaCore function can handle the following SDI data rates:

■ 270 megabits per second (Mbps) SD-SDI, as defined by SMPTE259M-1997 10-Bit

4:2:2 Component Serial Digital Interface

■ 1.5-Gbps HD-SDI, as defined by SMPTE292M-1998 Bit-Serial Digital Interface for

High Definition Television Systems

■ 3-Gbps SDI, as defined by SMPTE425M-AB 2006 3Gb/s Signal/Data Serial Interface–

Source Image Format Mapping

■ Preliminary support for dual link SDI, as defined by SMPTE372M-Dual Link

1.5Gb/s Digital Interface for 1920×1080 and 2048×1080 Picture Formats

February 2013 Altera Corporation Serial Digital Interface (SDI) MegaCore Function

User Guide

1–4 Chapter 1: About This MegaCore Function

■ Dual standard support for 270-Mbps and 1.5-Gbps SDI

■ Triple standard support for 270-Mbps, 1.5-Gbps, and 3-Gbps SDI

■ SMPTE425M Level A support (direct source image formatting)

■ SMPTE425M Level B support (dual link mapping)

General Description

Tab le 1– 5 lists the SDI standard support for various devices.

Table 1–5. SDI Standard Support

(1)

SDI Standard

Device Family

SD-SDI HD-SDI 3G-SDI HD-SDI Dual Link

(2)

Dual Standard Triple Standard

Arria GX vv v v v v Arria II GX vv v v v v Arria V vv v v v v Cyclone v —— — — —

Cyclone

Cyclone (EP4CGX15,

II v —— — — — III v —— — — —

IV GX

—— — — —

EP4CGX30)

Cyclone

IV GX (EP4CGX30 (F484), EP4CGX50, EP4CGX75,

vv v v v v

EP4CGX110, EP4CGX150)

Cyclone V

(3)

vv v v v v

HardCopy IV GX vv v v v v Stratix v —— — — — Stratix GX vv — vv—

Stratix

II v —— — — —

Stratix

II GX vv v v v v

Stratix

III v —— — — —

Stratix IV

Stratix V

Notes to Table 1–5:

(1) All standards, other than SD-SDI, require a transceiver based or “GX” device. (2) The HD-SDI dual link supports timing difference up to 40 ns between link A and link B, fulfilling the SMPTE372M requirement. (3) The 3G-SDI standard is not supported in Cyclone V devices with transceiver speed grade 7, due to the excessive data rate required. For more

(4) Only Stratix IV and Stratix V variants with transceivers support all SDI rates.

(4)

information about the Cyclone V device, refer to the Overview for Cyclone V Device Family chapter in volume 1 of the Cyclone V Device Handbook.

vv v v v v vv v v v v

Serial Digital Interface (SDI) MegaCore Function February 2013 Altera Corporation User Guide

Chapter 1: About This MegaCore Function 1–5

General Description

Tab le 1– 6 lists the HD-SDI standard video format specification.

Table 1–6. HD-SDI Video Format Specification

SMPTE292M Video Format

Sample per Active Line

(1) (2)

Active Line

per Frame

Sample per

Tot a l L i n e

Total Line per Frame

Frame Rate

2200 1125 60 Yes

2640 1125 50 Yes

274M 1920 x 1080 1920 1080

2200 1125 30 Yes

2640 1125 25 Yes

2750 1125 24 Yes

1650 750 60 Yes

1980 750 50 Yes

296M 1280 x 720 1280 720

3300 750 30 Yes

3960 750 25 Yes

4125 750 24 Yes

260M 1920 x 1035 1920 1035 2200 1125 30 Yes

295M 1920 x 1080 1920 1080

Notes to Table 1–6:

(1) The video formats support 4:2:2(YC’BC’R)/10-bit, 4:4:4(RGB)/(YC’BC’R), 4:4:4:4 (RGB+A)/(YC’BC’R+A)/10-bit, 4:4:4(YC’BC’R)/12-bit,

4:4:4(RGB)/12-bit, and 4:2:2 (YC’

(2) 3G-SDI is similar to HD-SDI except the data bit rate is twice that of HD-SDI or approximately 3 Gbps.

)/12-bit mapping structures.

BC’R

2376 1250 25 Yes

2376 1250 50 Yes

SDI 11.1

Support

OpenCore Plus Evaluation

With Altera’s free OpenCore Plus evaluation feature, you can perform the following actions:

■ Simulate the behavior of a megafunction (Altera MegaCore function or AMPP

megafunction) within your system.

■ Verify the functionality of your design and quickly evaluate its size and speed

with ease.

■ Generate time-limited device programming files for designs that include

MegaCore functions.

■ Program a device and verify your design in hardware.

You are required to obtain a license for the MegaCore function only when you are completely satisfied with its functionality and performance, and want to take your design to production.

f For more information about OpenCore Plus hardware evaluation using the SDI, refer

to “OpenCore Plus Time-Out Behavior” on page 3–39 and AN 320: OpenCore Plus

Evaluation of Megafunctions.

February 2013 Altera Corporation Serial Digital Interface (SDI) MegaCore Function

User Guide

1–6 Chapter 1: About This MegaCore Function

Resource Utilization

Tab le 1– 7 lists the typical resource utilization for various parameters with the

Quartus II software, version 11.1.

1 The resource utilization of the MegaCore function is based on the bidirectional

interface settings unless otherwise specified.

Table 1–7. Resource Utilization (Part 1 of 2)

Device Video Standard LEs Combinational ALUTs Logic Registers

SD-SDI — 834 640

HD-SDI — 919 683

3G-SDI — 1,161 865

Arria GX

Arria II GX

Arria V

Cyclone SD-SDI 875 — —

Cyclone II SD-SDI 867 — —

Cyclone III SD-SDI 874 — —

Cyclone III LS SD-SDI 929 — —

Cyclone IV GX (EP4CGX15, EP4CGX30)

Dual link HD-SDI — 1,906 1,423

Dual standard receiver — 1,188 831

Dual standard transmitter — 247 185

Triple standard — 1,794 1,215

SD-SDI — 839 680

HD-SDI — 978 833

3G HD-SDI — 1,259 1,015

Dual-Link HD-SDI — 2,029 1,711

Dual standard receiver — 1,257 926

Dual standard transmitter — 267 180

Triple standard — 1,891 1,305

SD-SDI — 1,189 920

HD-SDI — 1,185 910

3G-SDI — 1,444 1,142

Dual link HD-SDI — 2,446 1,880

Dual standard receiver — 1,605 1,175

Dual standard transmitter — 349 269

Triple standard — 2,273 1,677

SD-SDI 916 — —

Serial Digital Interface (SDI) MegaCore Function February 2013 Altera Corporation User Guide

Chapter 1: About This MegaCore Function 1–7

Resource Utilization

Table 1–7. Resource Utilization (Part 2 of 2)

Device Video Standard LEs Combinational ALUTs Logic Registers

SD-SDI — 1,129 671

Cyclone IV GX (EP4CGX50, EP4CGX75, EP4CGX110, and EP4CGX150)

HD-SDI — 1,164 670

3G-SDI — 1,409 790

Dual link HD-SDI — 2,515 1,467

Dual standard receiver — 1,479 755

Dual standard transmitter — 364 229

Triple standard — 2,235 1,121

SD-SDI — 1,140 832

HD-SDI — 1,122 808

3G-SDI — 1,402 997

Cyclone V

Dual link HD-SDI — 2,351 1,696

Dual standard receiver — 1,539 1,042

Dual standard transmitter — 352 260

Triple standard — 2,217 1,508

Stratix SD-SDI 875 — —

Stratix II SD-SDI — 581 533

Stratix III SD-SDI — 602 565

SD-SDI 1,182 — —

Stratix GX

HD-SDI 1,316 — —

Dual link HD-SDI 2,703 — —

Dual standard 1,819 — —

SD-SDI — 834 640

HD-SDI — 919 683

3G-SDI — 1,161 865

Stratix II GX

Dual link HD-SDI — 1,906 1,423

Dual standard receiver — 1,188 831

Dual standard transmitter — 247 185

Triple standard — 1,794 1,215

SD-SDI — 839 680

HD-SDI — 978 833

3G-SDI — 1,259 1,015

Stratix IV GX

Dual link HD-SDI — 2,029 1,711

Dual standard receiver — 1,257 926

Dual standard transmitter — 267 180

Triple standard — 1,891 1,305

SD-SDI — 913 707

Stratix V

HD-SDI — 955 703

3G-SDI — 1,126 823

Dual link HD-SDI — 2,049 1,522

February 2013 Altera Corporation Serial Digital Interface (SDI) MegaCore Function

User Guide

1–8 Chapter 1: About This MegaCore Function

Resource Utilization

Serial Digital Interface (SDI) MegaCore Function February 2013 Altera Corporation User Guide

Design Flow

2. Getting Started

To evaluate the SDI MegaCore function using the OpenCore Plus feature, follow these steps in your design flow:

1. Obtain and install the SDI MegaCore function.

The SDI MegaCore function is part of the MegaCore IP Library, which is distributed with the Quartus II software and downloadable from the Altera website at www.altera.com.

f For system requirements and installation instructions, refer to Altera

Software Installation & Licensing.

Figure 2–1 shows the directory structure after you install the SDI MegaCore function,

where

path> is the installation directory. The default installation directory on

Windows is c:\altera\<version>; on Linux, it is /opt/altera<version>.

February 2013 Altera Corporation Serial Digital Interface (SDI) MegaCore Function

User Guide

2–2 Chapter 2: Getting Started

Contains the Altera MegaCore IP Library and third-party IP cores.

common

Contains shared components.

sdi

Contains the SDI MegaCore function files.

lib

Contains encrypted lower-level design files and other support files.

<path>

Installation directory.

simulation

Contains simulation files.

hdsdi_3g

Contains the HD-SDI 3 Gbps simulation files.

testbench

Contains the testbench files.

quartus

Contains the Quartus II NativeLink project.

pattern_gen

Contains the pattern generator files for the testbench.

testbench

Contains the testbench files.

quartus

Contains the Quartus II NativeLink project.

pattern_gen

Contains the pattern generator files for the testbench.

hdsdi_dual_link

Contains the HD-SDI dual link simulation files.

testbench

Contains the testbench files.

modelsim

Contains the ModelSim simulation files.

quartus

Contains the Quartus II NativeLink project.

pattern_gen

Contains the pattern generator files for the testbench.

hdsdi

Contains the HD-SDI simulation files.

altera

Contains the Altera MegaCore IP Library.

example

Contains design examples.

s2gx_tr

Contains a design example for Stratix II GX, see AN 339: Serial Digital Interface Demonstration for Stratix II GX Devices.

a2gx_tr

Contains a design example for Arria II GX.

Figure 2–1. Directory Structure

Design Flow

Serial Digital Interface (SDI) MegaCore Function February 2013 Altera Corporation User Guide

1. Create a custom variation of the SDI MegaCore function.

2. Implement the rest of your design using the design entry method of your choice.

3. Use the IP functional simulation model to verify the operation of your design.

f For more information on IP functional simulation models, refer to the

Simulating Altera Designs chapter in volume 3 of the Quartus II Handbook.

Chapter 2: Getting Started 2–3

SDI Walkthrough

4. Use the Quartus II software to compile your design.

1 You can also generate an OpenCore Plus time-limited programming file,

which you can use to verify the operation of your design in hardware.

5. Purchase a license for the SDI MegaCore function.

After you have purchased a license for the SDI MegaCore function, follow these additional steps:

1. Set up licensing.

2. Generate a programming file for the Altera device or devices on your board.

3. Program the Altera device or devices with the completed design.

SDI Walkthrough

This walkthrough explains how to create an SDI design using the MegaWizard Plug-In Manager and the Quartus II software. After you generate a custom variation of the SDI MegaCore function, you can incorporate it into your overall project.

1 You can alternatively use the IP Advisor to help start your SDI MegaCore design. On

the Quartus II Tools menu, point to Advisors, and then click IP Advisor. The IP Advisor guides you through a series of recommendations for selecting, parameterizing, evaluating, and instantiating an SDI MegaCore function into your design. It then guides you through a complete Quartus II compilation of your project.

This walkthrough requires the following steps:

1. “Creating a New Quartus II Project”

2. “Launching MegaWizard Plug-In Manager”

3. “Parameterizing”

4. “Setting Up Simulation”

5. “Generating Files”

Creating a New Quartus II Project

You must create a new Quartus II project with the New Project Wizard, which specifies the working directory for the project, assigns the project name, and designates the name of the top-level design entity. To create a new project, follow these steps:

1. Choose Programs > Altera > Quartus II <version> (Windows Start menu) to run

the Quartus II software. Alternatively, you can use the Quartus II Web Edition software.

2. On the File menu, click New Project Wizard.

3. Click Next in the New Project Wizard: Introduction page (the introduction page does not display if you turned it off previously).

February 2013 Altera Corporation Serial Digital Interface (SDI) MegaCore Function

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SDI Walkthrough

4. In the New Project Wizard: Directory, Name, Top-Level Entity page, enter the following information:

a. Specify the working directory for your project. For example, this walkthrough

uses the c:\altera\projects\sdi_project directory.

1 The Quartus II software automatically specifies a top-level design entity

that has the same name as the project. This walkthrough assumes that the names are the same.

b. Specify the name of the project. This walkthrough uses project for the project

name.

5. Click Next to close this page and display the New Project Wizard: Add Files page.

1 When you specify a directory that does not already exist, a message

prompts you to create a specified directory. Click Yes to create the directory.

6. If you installed the MegaCore IP Library in a different directory from where you installed the Quartus II software, you must add the user libraries:

a. Click User Libraries.

b. Type <path>

\ip

into the Library name field, where <path> is the directory in

which you installed the SDI.

c. Click Add to add the path to the Quartus II project.

d. Click OK to save the library path in the project.

7. Click Next to close this page and display the New Project Wizard: Family & Device Settings page.

8. On the New Project Wizard: Family & Device Settings page, choose the target device family in the Family list.

9. The remaining pages in the New Project Wizard are optional. Click Finish to complete the Quartus II project.

Launching MegaWizard Plug-In Manager

To launch the MegaWizard Plug-In Manager in the Quartus II software, follow these steps:

1. On the Tools menu, click MegaWizard Plug-In Manager.

1 For more information about how to use the MegaWizard Plug-In Manager,

refer to Quartus II Help.

2. Specify that you want to create a new custom megafunction variation and click Next.

3. Expand the Interfaces > SDI folder and click SDI <version>.

4. Select the output file type for your design; the wizard supports VHDL and Verilog HDL.

Serial Digital Interface (SDI) MegaCore Function February 2013 Altera Corporation User Guide

Chapter 2: Getting Started 2–5

SDI Walkthrough

5. The MegaWizard Plug-In Manager shows the project path that you specified in the New Project Wizard. Append a variation name for the MegaCore function output files <project path>\<variation name>.

6. Click Next to display the Parameter Settings page for the SDI MegaCore function.

1 You can change the page that the MegaWizard Plug-In Manager displays by

clicking Next or Back at the bottom of the dialog box. You can move directly to a named page by clicking the Parameter Settings, EDA, or Summary tab. Also, you can directly display individual parameter settings by clicking on the Protocol Options, Transceiver Options, or Receiver/Transmitter Options tab.

Parameterizing

To parameterize your MegaCore function, follow these steps:

1. Select the video standard. Some of the standards may be grayed out, because they are not supported on the currently selected device family.

2. Select Bidirectional, Receiver, or Tr an sm i tt e r interface direction.

3. Click the Transceiver Options tab.

4. Under Transceiver and Protocol, click Generate transceiver and protocol blocks.

5. For SD-SDI only, turn on Use soft logic for transceiver to implement the transceiver in logic, rather than using Stratix GX, Stratix II GX or Stratix IV GX transceivers.

6. Select the starting channel number.

7. Turn on Use PLL reconfiguration for transceiver dynamic reconfiguration if you select an EP4CGX110 or EP4CGX150 device for Cyclone IV GX using dual and triple standards. You may turn on this option for other Cyclone IV GX devices but it is not recommended.

8. Turn on Enable TX PLL select for 1/1.000 and 1/1.001 data rate reconfiguration if your design requires two serial input clocks to the TX block.

1 This feature is only available for the Arria II, Stratix IV GX, and

HardCopy IV GX device families.

9. Click the Receiver/Transmitter Options tab.

10. Turn on the required receiver options.

11. Turn on the required transmitter options.

12. Click Next (or the EDA tab) to display the EDA page.

f For more information about parameters, refer to “Parameters” on page 3–56 and, for

more information about the protocol options, refer to Table 3–20 on page 3–56. For more information about the transceiver options, refer to Table 3–21 on page 3–56. For more information about the receiver/transmitter options, refer to Table 3–22 on

page 3–57.

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SDI Walkthrough

Setting Up Simulation

An IP functional simulation model is a cycle-accurate VHDL or Verilog HDL model produced by the Quartus II software. The model allows for fast functional simulation of IP using industry-standard VHDL and Verilog HDL simulators.

c You may only use these models for simulation and expressly not for synthesis or any

other purposes. Using these models for synthesis creates a nonfunctional design.

To generate an IP functional simulation model for your MegaCore function, follow these steps:

1. Turn on Generate simulation model.

2. Some third-party synthesis tools can use a netlist that contains only the structure of the MegaCore function, but not detailed logic, to optimize performance of the design that contains the MegaCore function. If your synthesis tool supports this feature, turn on Generate netlist.

3. Click Next (or the Summary tab) to display the Summary page.

Generating Files

You can use the check boxes on the Summary page to enable or disable the generation of specified files. A gray checkmark indicates a file that is automatically generated; a red checkmark indicates an optional file.

You can click Back to display the previous page, or click Parameters Settings, EDA, or Summary, to change any of the MegaWizard options.

To generate the files, follow these steps:

1. Turn on the files you wish to generate.

1 At this stage, you can still click Back to display any of the other pages in the

2. To generate the specified files and close the MegaWizard Plug-In Manager, click Finish.

1 The generation phase may take several minutes to complete. 1 The Quartus II IP File (.qip) is a file generated by the parameter editor, and

MegaWizard Plug-In Manager to change any of the parameters.

contains information about the generated IP core. You are prompted to add this .qip file to the current Quartus II project at the time of file generation. In most cases, the .qip file contains all of the necessary assignments and information required to process the core or system in the Quartus II compiler. Generally, a single .qip file is generated for each MegaCore function or system in the Quartus II compiler.

3. Click Exit to close the Generation window.

Serial Digital Interface (SDI) MegaCore Function February 2013 Altera Corporation User Guide

Chapter 2: Getting Started 2–7

SDI Walkthrough

Tab le 2– 1 describes the generated files and other files that may be in your project

directory. The names and types of files specified in the MegaWizard Plug-In Manager report vary based on whether you created your design with VHDL or Verilog HDL.

Table 2–1. Generated Files

Extension Description

A MegaCore function variation file, which defines a VHDL or Verilog HDL description of

<variation name>.v or .vhd

the custom MegaCore function. Instantiate the entity defined by this file inside of your design. Include this file when compiling your design in the Quartus II software.

<variation name>.cmp

<variation name>.bsf

A VHDL component declaration file for the MegaCore function variation. Add the contents of this file to any VHDL architecture that instantiates the MegaCore function.

Quartus II symbol file for the MegaCore function variation. You can use this file in the Quartus II block diagram editor.

<variation name>.html MegaCore function report file.

This XML file describes the MegaCore pin attributes to the Quartus II Pin Planner.

<variation name>.ppf

MegaCore pin attributes include pin direction, location, I/O standard assignments, and drive strength. If you launch IP Toolbench outside of the Pin Planner application, you must explicitly load this file to use Pin Planner.

<variation name>_sdi.sdc Contains timing constraints for your SDI variation.

Quartus II file that sets the Quartus II to use TimeQuest timing analyzer and patches the

<variation name>_constraints.tcl

generated .sdc script with a new clock name. If your top-level design clock pin names do not match the default clock pin names or a prefixed version, edit the assignments in this file.

<variation name>.vo or .vho VHDL or Verilog HDL IP functional simulation model.

<variation name>_bb.v

A Verilog HDL black-box file for the MegaCore function variation. Use this file when using a third-party EDA tool to synthesize your design.

<variation name>.qip Contains Quartus II project information for your MegaCore function variations.

You can now integrate your custom MegaCore function variation into your design, simulate, and compile.

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ALTGXB

RECONFIG (1)

- SD 270 Mbps

- HD 1.485 Gbps

- 3G 2.97 Gbps

SDI Pattern Generator

SDI IP CORE - Receiver

SDI IP CORE - Transmitter

SDI TRANSMIT TEST

DUT

SDI RECEIVE TEST

Transmitter Data

Descrambler

Transmitter TRS

Counter

Receiver TRS

Checker

Receiver Lock

Checker

Receiver Line

Checker

Simulating the Design

This section describes the following simulation techniques:

■ Simulate with IP Functional Simulation Models

■ Simulating with the ModelSim Simulator

■ Simulating in Third-Party Simulation Tools Using NativeLink

Testbench

In general, all testbenches are constructed in such a way that the serial transmit data is looped back to receiver. Figure 2–2 shows how the serial transmit data is looped back to the receiver in the testbench.

Figure 2–2. General Simulation Testbench

Serial Digital Interface (SDI) MegaCore Function February 2013 Altera Corporation User Guide

Note to Figure 2–2:

(1) For dual or triple standard only.

Chapter 2: Getting Started 2–9

Simulating the Design

A testbench basically consists of transmit test and receive test. The transmit test accepts the same serial data as the receive device under test (DUT), deserializes and decodes the transmitted data, and computes the number of time reference signals (TRS) seen. The receive test verifies the features that are supported by the SDI receiver by monitoring the received data, status bits, line numbering and other related features.

For dual and triple standard modes, the SDI receiver requires reconfiguration. The SDI receiver reconfigures using transceiver dynamic reconfiguration to perform autodetection and locking to different SDI video standards. For more details about transceiver dynamic reconfiguration, refer to “Transceiver Dynamic Reconfiguration

for Dual Standard and Triple Standard Receivers” on page 3–27.

Simulate with IP Functional Simulation Models

You can simulate your design using the MegaWizard-generated VHDL and Verilog HDL IP functional simulation models.

You can use the IP functional simulation model with any Altera-supported VHDL or Verilog HDL simulator.

To use the IP functional simulation model that you created in “Setting Up Simulation”

on page 2–6, create a suitable testbench.

f For more information about IP functional simulation models, refer to the Simulating

Altera Designs chapter in volume 3 of the Quartus II Handbook.

Simulating with the ModelSim Simulator

For Arria and Stratix series of devices, Altera provides two fixed testbenches as examples in the simulation\modelsim\<video standard>\modelsim directory, where <video standard> is hdsdi or hdsdi_dual_link. The testbenches instantiate the design and test the HD-SDI or dual link mode of operation. To use one of these testbenches with the ModelSim

1. In a text editor, open the simulation batch file, simulation\modelsim\<video standard>\modelsim\sdi_sim.bat. Edit it to point to your installation of the ModelSim-Altera simulator and the Quartus II software, and edit the path:

set PATH = %MODELSIM_DIR%\win32aloem

set QUARTUS_ROOTDIR=c:\altera\81\quartus

For example, edit

1 Where <video standard> is hdsdi or hdsdi_dual_link.

2. Start the ModelSim-Altera simulator.

3. Run sdi_sim.bat in the simulation\modelsim\<video standard>\modelsim directory. This file compiles the design and starts the ModelSim-Altera simulator. A selection of signals appears on the waveform viewer. The simulation runs automatically, providing a pass/fail indication on completion.

-Altera simulator, follow these steps:

QUARTUS_ROOTDIR=/tools/acds/11.0/157/linux32/quartus

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Simulating the Design

For Cyclone IV GX devices, Altera provides two new fixed testbenches in the simulation\modelsim\<video standard>\<DPRIO mode>\modelsim directory, where <video standard>\<DPRIO mode> is trsdi_c4gx\channel_reconfig or trsdi_c4gx\pll_reconfig. The testbenches instantiate the design and test the triple standard mode of operation using Cyclone IV GX devices. The testbenches also demonstrate the transceiver dynamic reconfiguration with channel and phase-locked loop (PLL) reconfiguration modes. To use one of these testbenches with the ModelSim-Altera simulator, follow these steps:

1. In a text editor, open the simulation .do file, simulation\modelsim\<video standard>\<DPRIO mode>\modelsim\sdi_sim.do. Edit it to point to your installation of the ModelSim-Altera simulator, and edit the path:

set QUARTUS_ROOTDIR = C:\altera\<version>\quartus

1 Where <version> is the version of the Quartus II software you are using.

2. Start the ModelSim-Altera simulator.

3. Run sdi_sim.do in the simulation\modelsim\<video standard>\<DPRIO mode>\modelsim directory. This file compiles the design and starts the ModelSim-Altera simulator. A selection of signals appears on the waveform viewer.

To test the transmitter operation, the testbench generates a reference clock and parallel video data. The design encodes and serializes this parallel video data. The serial output is sampled, non-return to zero inverted (NRZI) decoded, descrambled, and then reconstructed into parallel form. The testbench detects the presence of TRS tokens (end of active video (EAV) and start of active video (SAV)) in the output to check the correct operation.

To test the receiver operation, the testbench connects the serial transmitter data to the receiver input. The testbench checks that the receiver achieves word alignment and verifies that the extracted LN is correct.

Simulating in Third-Party Simulation Tools Using NativeLink

You can perform a simulation in a third-party simulation tool from within the Quartus II software, using NativeLink.

f For more information about NativeLink, refer to the Simulating Altera Designs chapter

in volume 3 of the Quartus II Handbook.

Altera provides the following three Quartus II projects for use with NativeLink in the ip\altera\sdi\simulation directory:

■ HD-SDI in the hdsdi directory

■ HD-SDI 3 Gbps in the hdsdi_3g directory

■ HD-SDI dual link in the hdsdi_dual_link directory

■ Triple standard SDI in the trsdi directory

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Chapter 2: Getting Started 2–11

SDI triple standard transmitter

starting_channel_number = 0

Transceiver Bank 1

SYSTEM TOP LEVEL

SDI triple standard receiver

starting_channel_number = 4

rx_serial_refclk_top1tx_serial_refclk_top1

Specifying Constraints

To set up simulation in the Quartus II software using NativeLink, follow these steps:

1. On the File menu, click Open Project. Browse to the desired directory: hdsdi, hdsdi_3g, hdsdi_dual_link, or trsdi.

2. Open sdi_sim.qpf.

3. Check that the absolute path to your third-party simulator executable is set. On the Tools menu, click Options and select EDA Tools Options.

4. On the Processing menu, point to Start and click Start Analysis & Elaboration.

5. On the Tools menu, point to Run EDA Simulation Tool and click EDA RTL Simulation.

Specifying Constraints

You must apply the Altera-provided timing constraint file in Synopsys Design Constraints File (.sdc) format and the additional Tcl Script File (.tcl) to ensure the SDI MegaCore function meets the design timing requirements.

To ad d the .sdc file to your project, click Add/Remove Files in Project on the Project menu and browse to select <variation name>_sdi.sdc file.

To add the additional .tcl file, you must compile your design and perform post compilation timing analysis using the TimeQuest timing analyzer. On the Assignments menu, click Use TimeQuest Timing Analyzer during compilation, and click OK.

You may have to further edit your scripts if your design requires single channel or multiple channels.

Single Channel

The following section describes what you must do if your design requires a single channel using SDI triple standard transmitter and receiver instances as shown in

Figure 2–3 on page 2–11.

Figure 2–3. Instantiating Single Channel of SDI Instances

1 The SDI instances must have a unique starting channel number if they are merged

into a same quad or bank.

To specify the constraints, follow these steps:

1. Parameterize and generate your SDI MegaCore functions—SDI triple standard transmitter and receiver.

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SDI triple standard transmitter A

starting_channel_number = 0

Transceiver Bank 1

SYSTEM TOP LEVEL

SDI triple standard transmitter B

starting_channel_number = 8

SDI triple standard receiver B

starting_channel_number = 12

SDI triple standard receiver A starting_channel_number = 4

SDI triple standard transmitter A

starting_channel_number = 0

rx_serial_refclk_top1tx_serial_refclk_top1

SDI triple standard transmitter B

starting_channel_number = 8

SDI triple standard receiver B

starting_channel_number = 12

SDI triple standard receiver A starting_channel_number = 4

Transceiver Bank 2

Specifying Constraints

2. Edit the Tcl script so that the transceiver top-level reference clock matches the clock pin names that you have chosen for your design, for example

tx_serial_refclk_top1

. Locate

tx_serial_refclk_name

in the script and change

1 The SDI triple standard transmitter has a transceiver top-level reference

clock,

tx_serial_refclk

3. Execute the Tcl script to patch the generated .sdc script with the new clock names.

1 A back-up copy of the .sdc script is created before the patch is made, and

any edits that were previously made to the .sdc script are preserved.

4. Execute the Tcl script in the Quartus II software, and follow these steps:

a. On the Tools menu, click Tcl script.

b. Select the Tcl script of the instance SDI triple standard transmitter, and click

Run.

5. Perform steps 2 to 4 for the SDI triple standard receiver instance.

Multiple Channels

The following section describes what you must do if your design requires multiple channels using four instances of SDI triple standard transmitter and four instances of SDI triple standard receiver. In this case, assume that you must fit all instances into Transceiver Bank 1 and 2 as shown in Figure 2–4, and the SDI instances in both banks have the same video standard. You do not have to regenerate the SDI instances in Transceiver Bank 2.

Figure 2–4. Instantiating Multiple Channels of SDI Instances Sharing Same Reference Clock

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Chapter 2: Getting Started 2–13

tx_serial_refclk_top2

tx_serial_refclk_top1

SDI triple standard transmitter A

starting_channel_number = 0

Transceiver Bank 1

SYSTEM TOP LEVEL

SDI triple standard transmitter B

starting_channel_number = 8

SDI triple standard receiver B

starting_channel_number = 12

SDI triple standard receiver A starting_channel_number = 4

SDI triple standard transmitter A

starting_channel_number = 0

rx_serial_refclk_top1

rx_serial_refclk_top2

SDI triple standard transmitter B

starting_channel_number = 8

SDI triple standard receiver B

starting_channel_number = 12

SDI triple standard receiver A starting_channel_number = 4

Transceiver Bank 2

Specifying Constraints

To specify the constraints, perform the following steps:

1. Parameterize and generate your SDI MegaCore functions—SDI triple standard transmitter A, SDI triple standard transmitter B, SDI triple standard receiver A, and SDI triple standard receiver B—with their unique starting channel number.

2. Edit the Tcl script so that the transceiver top-level reference clock matches the name of the clock pin connected to SDI triple standard transmitter A, for example

tx_serial_refclk_top1

. Locate

tx_serial_refclk_name

in the script and change

3. Execute the Tcl script to patch the generated .sdc script with the new clock names.

1 A back-up copy of the .sdc script is created before the patch is made, and

any edits that were previously made to the .sdc script are preserved.

4. Execute the Tcl script in the Quartus II software, and perform the following steps:

a. On the Tools menu, click Tcl script.

b. Select the Tcl script of the instance SDI triple standard transmitter A, and click

Run.

5. Perform steps 2 to 4 for the other three instances.

Figure 2–5. Instantiating Multiple Channels of SDI Instances Sharing Multiple Reference Clocks

To specify constraints for multiple channels of SDI MegaCore function with multiple top-level reference clocks as shown in Figure 2–5, perform the following steps:

1. For the SDI instances in Transceiver Bank 1, perform steps 1 to 5 you would do for SDI instances sharing the same reference clock.

2. For the SDI instances in Transceiver Bank 2, duplicate an .sdc script for SDI triple standard transmitter A and SDI triple standard receiver A in Transceiver Bank 2.

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1 You are not required to duplicate .sdc script for SDI triple standard

transmitter B and SDI triple standard receiver B in Transceiver Bank 2. Instances with same video standard can share an .sdc script.

3. Edit the .sdc script so that the reference clock name matches the name of the clock pin connected to SDI triple standard transmitter A, for example

tx_serial_refclk_top2

4. Edit another .sdc script so that the reference clock name matches the name of the clock pin connected to SDI triple standard receiver A, for example

rx_serial_refclk_top2

change to

5. Add these two duplicate .sdc scripts to your project. On the Project menu, click Add/Remove Files in Project and browse to select the scripts.

rx_serial_refclk_top2

. Locate

tx_serial_refclk_name

set rx_serial_refclk_name

in the script and change

Compiling the Design

in the script and

Compiling the Design

You can use the Quartus II software to compile your design. For instructions about performing compilation, refer to Quartus II Help.

You can find an example design using an SDI MegaCore function in the ip/sdi/example directory. This design is targeted at the Stratix II GX audio video development kit.

f For more information about the example design, refer to AN 339: Serial Digital Interface

Demonstration for Stratix II GX Devices, and for information about the development kit,

refer to Audio Video Development Kit, Stratix II GX Edition.

Programming a Device

After you have compiled the example design, you can program your targeted Altera device to verify the design in hardware.

With Altera's free OpenCore Plus evaluation feature, you can evaluate the SDI MegaCore function before you obtain a license. OpenCore Plus evaluation allows you to generate an IP functional simulation model, and produce a time-limited programming file.

f For more information about OpenCore Plus hardware evaluation using the SDI

MegaCore function, refer to “OpenCore Plus Evaluation” on page 1–5, “OpenCore

Plus Time-Out Behavior” on page 3–39, and AN 320: OpenCore Plus Evaluation of

Megafunctions.

Serial Digital Interface (SDI) MegaCore Function February 2013 Altera Corporation User Guide

Chapter 2: Getting Started 2–15

Setting Up Licensing

You must purchase a license for the MegaCore function only when you are completely satisfied with its functionality and performance and want to take your design to production.

After you purchase a license for SDI MegaCore function, you can request a license file from the Altera website at www.altera.com/licensing and install it on your computer. When you request a license file, Altera emails you a license.dat file. If you do not have Internet access, contact your local Altera representative.

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Setting Up Licensing

Serial Digital Interface (SDI) MegaCore Function February 2013 Altera Corporation User Guide

3. Functional Description

The SDI MegaCore function implements a receiver, transmitter, or full-duplex interface. The SDI MegaCore function can handle SD, HD, and/or 3G SDIs.

The SDI MegaCore function consists of the following elements:

■ Protocol blocks

■ SDI receiver

■ SDI transmitter

■ A transceiver

■ A transceiver controller

In the MegaWizard Plug-In Manager, you can specify either protocol or transceiver blocks or both for your design. For example, if you have multiple protocol blocks in a design, you can multiplex them into one transceiver. The transceiver can be either a soft-logic implementation or a GX transceiver.

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Scrambler

en_sync_switch

SDI Out

SDI In

Parallel

Video Out

Parallel Video In

Parallelto-Serial

Transmitter

PLL

Receiver

PLL

Transceiver

(

)

Transmitter Protocol Blocks

Transmitter Transceiver

Transceiver

(

)

Receiver Protocol Blocks

Receiver Transceiver

Insert

CRC

DescramblerAligner

F, V, and H

HD-SDI Only

Serial-to-

Parallel

Receiver

Oversampler

Transmitter

Oversampler

Insert

Check

CRC

FIFO

Buffer

Extract

Detect

Format

Track

Ancilliary

TRS

Match

SD-SDI Only

Block Description

Figure 3–1 shows the SDI MegaCore function block diagram.

Figure 3–1. SDI MegaCore Function Block Diagram

Note to Figure 3–1:

(1) For SD-SDI designs only, you can have a soft-logic implementation of the transceiver.

Transmitte r

The transmitter contains the following elements:

■ SD/HD-SDI transmitter scrambler

■ HD-SDI transmitter data formatter, which includes a CRC and LN insertion

■ Transceiver, plus control, and interface logic with multirate (dual or triple

standard) SD/HD-SDI transmitter operation

■ Transmitter clock multiplexer (optional)

The transmitter performs the following functions:

■ HD-SDI LN insertion

■ HD-SDI CRC generation and insertion

■ Scrambling and NRZI coding

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Chapter 3: Functional Description 3–3

TRS Match

SDI TRANSMITTER

Protocol Block

Transceiver Interface Block

Transceiver Block

LN Insert

CRC (c)

CRC (y)

Scrambler

FIFO

GXB RX Sample

rst_tx

tx_pclk

reset

tx_serial_refclk

tx_serial_refclk1 (optional)

gxb4_cal_clk

sdi_reconfig_togxb[3:0]

sdi_gxb_powerdown

rst_tx

tx_pclk

txdata[19:0]

tx_std[1:0]

tx_trs

tx_ln[21:0]

enable_ln

enable_crc

tx_status

gxb_tx_clkout

sdi_tx (serial data)

sdi_reconfig_fromgxb[16

tx_data[19:0]

tx_clockout

tx_datain[19:0]

Block Description

■ Internal switching between two reference clock signals in the transmitter block.

This feature is optional and only available for Arria II GZ, Stratix IV GX , and HardCopy IV devices.

Figure 3–2 shows the top-level block diagram for the SDI transmitter.

Figure 3–2. SDI Transmitter Block Diagram

For HD-SDI, the transmitter accepts 20-bit parallel video data; for SD-SDI, 10-bit parallel data. For

txdata

bus definition, refer to Table 3–16 on page 3–41.

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Block Description

Tab le 3– 1 lists the bit allocation for

Table 3–1. Bit Allocation for txdata for Supported Video Standards

txdata SD-SDI HD-SDI 3G-SDI Level A 3G-SDI Level B

[19:10] Unused Y Y

[9:0]

Cb, Y, Cr, Y multiplex

txdata

Cb, Y, Cr, Y

multiplex (link A)

Cb, Y, Cr, Y

multiplex (link B)

For HD-SDI operation, the current video line number is inserted at the appropriate point in each line. A CRC is also calculated and inserted for the luma and chroma channels.

The parallel video data is scrambled and NRZI encoded according to the SDI specification.

The transceiver converts the encoded parallel data into the high-speed serial output (parallel-to-serial conversion).

HD-SDI LN Insertion

SMPTE292M section 5.4 defines the format of two words that are included in each HD-SDI video line to indicate the current line number. The HD-SDI LN insertion module takes the lower 11-bit output data. The HD-SDI LN insertion module accepts the current line number as an input.

tx_ln

, and formats and inserts it as two words in the

1 For more information about the line insertion for other video standards, refer to the

description for

tx_ln

signal in Table 3–16 on page 3–41.

The LN words (LN0 and LN1) overwrite the two words that follow the “XYZ” word of the EAV TRS sequence. The same value is included in the luma and chroma channels.

For correct LN insertion, you must assert the

tx_trs

signal must be asserted for the first word of both EAV and SAV TRSs (refer to Figure 3–31 on page 3–47 and

Figure 3–32 on page 3–48).

1 If the system does not know the line number, you can implement logic to detect the

output video format and then determine the current line. This function is outside the scope of this SDI MegaCore function.

HD-SDI CRC Generation and Insertion

SMPTE292M section 5.5 defines a CRC that is included in the chroma and luma channels for each HD-SDI video line. The HD-SDI CRC module generates, formats, and inserts the required CRC in the output data.

The HD-SDI CRC module identifies the words that you must include in the CRC calculation, and also determines where you must insert the words in the output data. The formatted CRC data words ( for the chroma channel) overwrite the two words that follow the line number words after the EAV. A separate calculation is provided for the luma and chroma channels.

YCR0

and

YCR1

for the luma channel,

CCR0

and

CCR1

Serial Digital Interface (SDI) MegaCore Function February 2013 Altera Corporation User Guide

Chapter 3: Functional Description 3–5

Protocol Block (Transmitter) Transceiver Interface Block Transceiver Block

ALTGXB

tx_pclk

encoded_data[19:0]

txdata[19:0]

tx_pclk

pll_inclk

pll_inclk1

cal_blk_clk

reconfig_clk

gxb_txword[19:0]

gxb_tx_core_clk

tx_clkout

(optional)

gxb_tx_clkout

sdi_tx

(serial data out)

tx_pclk

tx_serial_refclk

tx_serial_refclk1

gxb2_cal_clk

sdi_reconfig_clk

Block Description

The CRC is calculated for all words in the active digital line, starting with the first active word line and finishing with the final word of the line number (

LN1

). The initial value of the CRC is set to zero, then the polynomial generator equation CRC(X) = X

18+X5+X4

+ 1 is applied.

The HD-SDI CRC module implements the CRC calculation by iteratively applying the polynomial generator equation to each bit of the output data, processing the LSB first.

For correct CRC generation and insertion, the first word of both EAV and SAV TRS (refer to Figure 3–31 on page 3–47 and

Figure 3–32 on page 3–48).

Scrambling and NRZI Coding

SMPTE292M section 5 and SMPTE292M section 7 define a common channel coding that is used for both SDI and HD-SDI. This channel coding consists of a scrambling function (G

(X) = X9+X4+ 1) followed by NRZI encoding (G2(X) = X + 1). The

scrambling module implements this channel coding. You can configure the module to process either 10-bit or 20-bit parallel data.

The scrambling module implements the channel coding by iteratively applying the scrambling and NRZI encoding algorithm to each bit of the output data, processing the LSB first. Figure C.1 of SMPTE259M shows how the algorithm is implemented.

Transceiver Clock

Figure 3–3 shows the clocking scheme for the transmitter.

The

tx_serial_refclk1

Enable TX PLL select for 1/1.000 and 1/1.001 data rate reconfiguration in the SDI parameter editor.

Figure 3–3. Transmitter Clocking Scheme

tx_trs

signal must be asserted for the

is an optional port that is enabled when you turn on the

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3–6 Chapter 3: Functional Description

Block Description

Receiver

The receiver contains the following elements:

■ Transceiver, plus control, and interface logic with multirate (dual or triple

standard) SD/HD-SDI receiver operation

■ SD/HD-SDI receiver descrambler and word aligner

■ HD-SDI receiver CRC and LN extractor

■ Receiver framing, with extraction of video timing signals

■ Identification and tracking of ancillary data

The SDI receiver consists of the following functions:

■ NRZI decoding and descrambling

■ Word a lig n me n t

■ Video timing flags extraction

■ RP168 switching compliance

■ HD-SDI LN extraction

■ HD-SDI CRC

■ Accessing transceiver

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Chapter 3: Functional Description 3–7

Block Description

Figure 3–4 shows the top-level block diagram for the SDI receiver.

Figure 3–4. SDI Receiver Block Diagram

SDI RECEIVER

Protocol Block

rst_rx

en_sync_switch

rst_rx

rx_serial_refclk

enable_sd_search

enable_hd_search

enable_3g_search

sdi_reconfig_done

Descrambler

Aligner

LN Extract

CRC Extract

ANC Track

TRS Match

Format

rx_hd_sdi

word_valid

word[19:0]

Transceiver Interface Block

GXB RX Sample

GXB Control FSM

Triple Rate Detect

rx_clockout

rx_dataout[19:0]

lock_torefclk

rx_clk

lock_todata

digital_reset

analog_reset

rx_status[10:0]

rx_trs

rx_ln[21:0]

rxdata[19:0]

rx_data_valid_out[1:0]

crc_error_c[1:0]

crc_error_y[1:0]

rx_anc_data[19:0]

rx_anc_valid[3:0]

rx_anc_error[3:0]

rx_F[1:0]

rx_H[1:0]

rx_V[1:0]

rx_AP[1:0]

xyz_valid, rx_xyz, rx_eav

rx_clk

rx_std[1:0]

rx_std_flag_hd_sdn

sdi_start_reconfig

rst_rx

rx_serial_refclk

sdi_rx (serial data)

gxb4_cal_clk

sdi_reconfig_clk

sdi_reconfig_togxb[3:0]

sdi_gxb_powerdown

Transceiver Block

sdi_reconfig_fromgxb[16:0]

The received data is NRZI decoded and descrambled and then presented as a word-aligned parallel output—20 bit for HD-SDI; 10 bit for SD-SDI (refer to

Table 3–16 on page 3–41 for

February 2013 Altera Corporation Serial Digital Interface (SDI) MegaCore Function

rxdata

bus definition).

User Guide

3–8 Chapter 3: Functional Description

Block Description

Tab le 3– 2 lists the bit allocation for

Table 3–2. Bit Allocation for rxdata for Supported Video Standards

rxdata SD-SDI HD-SDI 3G-SDI Level A 3G-SDI Level B

[19:10] Unused Y Y

[9:0]

Cb, Y, Cr, Y

multiplex

rxdata

Cb, Y, Cr, Y

multiplex (link A)

Cb, Y, Cr, Y

multiplex (link B)

The receiver interface extracts and tracks the F, V, and H timing signals in the received data. Active picture and ancillary data words are also identified for your use.

For HD-SDI, the received CRC is checked for the luma and chroma channels. The LN is also extracted and provided as an output from the design.

NRZI Decoding and Descrambling

The descrambler module provides the channel decoding function that is common to both SDI and HD-SDI. It implements the NRZI decoding followed by the required descrambling. The algorithm indicated by SMPTE259M figure C.1 is iteratively applied to the receiver data, with the LSB processed first.

Word Alignment

The aligner word aligns the descrambled receiver data such that the bit order of the output data is the same as that of the original video data.

The EAV and SAV sequences determine the correct word alignment. Tab le 3 –3 lists the pattern for each standard.

Table 3–3. EAV and SAV Sequences

Video Standard EAV and SAV Sequences

SDI

HD-SDI

3G-SDI Level A

3G-SDI Level B

3FF 000 000

3FF 3FF 000 000 000 000

3FF 3FF 3FF 3FF 000 000 000 000 000 000 000 000

The aligner matches the selected pattern in the descrambled receiver data. If the pattern is detected at any of the possible word alignments, then a flag is raised and the matched alignment is indicated. This process is applied continuously to the receiver data.

The second stage of the aligner determines the correct word alignment for the data. It looks for three consecutive TRSs with the same alignment, and then stores that alignment. If two consecutive TRSs are subsequently detected with a different alignment, then this new alignment is stored.

The final stage of the aligner applies a barrel shift function to the received data to generate the correctly aligned parallel word output. For this SDI MegaCore function, the barrel shifter allows the design to instantly switch from one alignment to another.

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Chapter 3: Functional Description 3–9

tx_data

dead_time

(1)

switch

line

10200

00000H

40020H 10200H

10200H 10200H

10200H

10 11 12

12H03H

alignment

align_locked/rx_status[2]

rx_data

(2)

(4)

(3)

Block Description

Video Timing Flags Extraction

The TRS match module extracts the F, V, and H video timing flags from the received data. You can use these flags for receiver format detection, or in the implementation of a flywheel function.

The TRS match module also identifies the line number and CRC words for HD-SDI.

RP168 Switching Compliance

To meet the RP168 requirements, the transceiver must be able to recover by the end of the switching line. Table 3–4 lists the supported video switching type.

f For more information about the switching line and time for different video formats,

refer to RP168.

Table 3–4. Supported Video Switching Type

Standard/ Data Rate Format RP168 Support Switching Source

Fixed Switch (same format) Yes HD-1080i30 to HD-1080i30

Fixed Switch No HD-1080 to HD-720

Switch Fixed No HD-1080 to SD-525

Switch Switch No HD-1080 to SD-525

Figure 3–5 and Figure 3–6 show the behaviors of the aligner and format blocks during

the RP168 switching.

The aligner block immediately aligns to the next TRS timing based on the user input

en_sync_switch

Figure 3–5. Aligner Block Behavior

Notes to Figure 3–5:

(1) Mismatch in alignment. (2) New alignment on the next TRS. (3) Data aligned to new alignment. (4) Zero interrupt.

signal.

February 2013 Altera Corporation Serial Digital Interface (SDI) MegaCore Function

User Guide

3–10 Chapter 3: Functional Description

Block Description

The format block latches the user input realign to a new TRS alignment immediately. During switching, you see zero interrupt at downstream. The deasserted during sync switch.

Figure 3–6. Format Block Behavior

en_sync_switch

en_sync_switch_reg

line

eav_detect

eav_position

trs_locked/rx_status[3]

frame_locked/rx_status[4]

HD-SDI LN Extraction

The HD-SDI LN extraction module extracts and formats the LN words defined by SMPTE292M section 5.4 from the HD-SDI chroma channel. The design provides the LN as an output.

en_sync_switch

trs_locked

2200 2199 2200

11 12 13

(previous TRS timing) (new TRS timing)

and

frame_locked

signal for three lines to

signals never get

HD-SDI CRC Checking

The CRC module checks the CRC defined by SMPTE292M section 5.5 for the HD-SDI luma and chroma channels.

1 This module is common to the receiver and the transmitter.

The check is implemented by recalculating the CRCs for each received video line and then checking the results against the CRC data received. If the results differ, an error flag is asserted. There are separate error flags for the luma and chroma channels. The flag is held asserted until the next check is performed.

Accessing Transceiver

The Quartus II software enables you to access the transceiver through the unencrypted ALTGX wrapper file. You can access the ALTGX wrapper files for Arria II GX, Arria V, Cyclone IV GX, Stratix II GX, and Stratix IV GX configurations.

You can use one of the two following ways to access the ALTGX wrapper files:

■ Edit the ALTGX wrapper file, using legal range provided in the respective device

handbooks.

■ Use analog control through the ALTGX_RECONFIG megafunction.

c Do not reinstantiate the customized ALTGX wrapper file using the MegaWizard

Plug-In Manager so that you do not lose the default content of the wrapper file after regeneration.

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Chapter 3: Functional Description 3–11

Block Description

Editing the ALTGX Wrapper File

If you want to change the settings of the parameters, edit the legal ranges in the ALTGX wrapper file.

For example, if you want to change the voltage output differential control setting from 4 to 7, change the following line in the wrapper file:

alt4gxb_component.vod_ctrl_setting = 4

to this line:

alt4gxb_component.vod_ctrl_setting = 7

f To know the exact legal ranges for a specific Altera device, refer to the respective

device handbooks.

Using Analog Control

If you want the flexibility to access and control the ALTGX settings, use the ALTGX_RECONFIG megafunction to enable analog reconfiguration. You can use the analog control to edit the default settings of the following transceiver parameters:

■ Voltage output differential

■ Pre-emphasis control pre-tap

■ Pre-emphasis control 1st post-tap

■ Pre-emphasis control 2nd post-tap

■ Equalizer DC gain

■ Equalized DC control

The ALTGX_RECONFIG megafunction interfaces with the ALTGX using

reconfig_togxb[3:0]

and

reconfig_fromgxb[16:0]

ports for a single channel.

To enable the analog control and channel reconfiguration during run time, use the

reconfig_mode_sel

signal.

f For more information about how to use the analog control with the

ALTGX_RECONFIG megafunction, refer to the ALTGX_RECONFIG Megafunction User Guide in the respective device handbooks.

February 2013 Altera Corporation Serial Digital Interface (SDI) MegaCore Function

User Guide

3–12 Chapter 3: Functional Description

Protocol Block (Receiver) Transceiver Interface Block Transceiver Block

ALTGXB

rxclk

rxword[19:0]

rxdata[19:0]

rx_refclk rx_cruclk

cal_blk_clk

reconfig_clk

gxb_rxword[19:0] rx_dataout[19:0]

gxb_refclk rxclk

rx_clkout

rxclk

rx_serial_refclk

gxb2_cal_clk

sdi_reconfig_clk

sdi_rx

(serial data in)

Block Description

Transceiver Clock

Figure 3–7 shows the general clocking scheme for the receiver.

Figure 3–7. Receiver Clocking Scheme

Transceiver—Soft-Logic Implementation

The soft-logic implementation differs for the transmitter and the receiver.

Transmitter

For the transmitter, in the soft-logic transceiver a 10-bit parallel word is converted into a serial data output format. A 10-bit shift register loaded at the word rate from the encoder and unloaded at the bit rate of the LVDS output buffer is implemented for that function. A PLL that multiplies a 27-MHz reference clock by ten provides the bit-rate clock and enables jitter-controlled SDI transmit serialization.

Transmitter Clocks

The serializer requires a 270-MHz clock, which you can generate from an external source (

The 27-MHz parallel video clock ( input.

Transmitter Clock Multiplexer Option

This is a new feature introduced in version 11.1. The transmitter block has the option of receiving an additional reference clock to allow dynamic switching between the 1/1000 and 1/1.001 data rates. This feature is available in Arria II, Stratix IV, and HardCopy IV devices.

tx_sd_refclk_270

tx_pclk

) samples and processes the parallel video

By default, you can use the

tx_serial_refclk1

as an additional clock input parameter. You can then switch to the

clock source selected by using the transceiver dynamic reconfiguration.

Serial Digital Interface (SDI) MegaCore Function February 2013 Altera Corporation User Guide

tx_serial_refclk

for any normal SDI operations and the

Chapter 3: Functional Description 3–13

Block Description

Receiver

For the receiver, in the soft-logic transceiver the serial data stream from the LVDS input buffer is sampled using four different clocks phase-shifted by 90° from each other. Two out of these four clocks are created from an on-chip PLL. The two remaining clocks are created by inversion of the PLL clock outputs.

Samples are then all converted to the same clock domain and deserialized into a 10-bit parallel word. The serial clock that samples the bit stream must be 337.5 MHz, which is 5/4 of the incoming bit (270-bit rate × 5/4 × 4 sample per clock = 1,350 Mbps)

The parallel clock that extracts data from the deserializer is running at 135 MHz.

To achieve timing, you must correctly constrain your design, refer to “Constraints” on

page A–1.

Receiver Clocks

The deserializer requires three clocks (refer to Table 3–15 on page 3–41), which you can generate from an external source.

Transceiver—Stratix GX Devices

The Stratix GX transceiver deserializes the high-speed serial input. For HD-SDI, the clock data recovery (CDR) function performs the deserialization and locks the receiver PLL to the receiver data. For SD-SDI, the transceiver provides a fixed frequency oversample of the serial data with the receiver PLL constantly locked to a reference clock, which allows the transceiver to support the 270-Mbps data rate.

The transceiver can process either SD-SDI or HD-SDI data. The data rate can be automatically detected so that the interface can handle both SD-SDI and HD-SDI without the need for device reconfiguration.

In Stratix GX devices, the transmitters in a quad share a common reference clock, which prevents them from operating independently.

Receivers in a quad share a common training clock, but have independent receiver PLLs. Because the same training clock is used for SD-SDI and HD-SDI, receivers can accommodate the different standards within a single quad.

Transmitter Clocks

The transmitter requires two clocks: a parallel video clock ( reference clock (

tx_serial_refclk

The parallel video clock samples and processes the parallel video input. For SD-SDI, it is 27 MHz; for HD-SDI, it is 74.25 or 74.175 MHz.

The transceiver uses the transmitter reference clock to generate the high-speed serial output. The transceiver is configured for 20-bit operation, so the reference clock is

1/20

of the serial data rate.

tx_pclk

) and a transmitter

1 For SD-SDI, because of the oversampling implementation, the serial data rate is five

times the SDI bit rate (for example, 1,350 Mbps).

For HD-SDI operation,

February 2013 Altera Corporation Serial Digital Interface (SDI) MegaCore Function

pclk

can drive the transmitter reference clock.

User Guide

3–14 Chapter 3: Functional Description

SDI MegaCore

Function

74.XX MHz (

)

from reference clock

Serial Data

HD-SDI

SDI MegaCore

Function

67.5 MHz

from PLL or Pin

Serial Data

SD-SDI

SDI MegaCore

Function

67.5 MHz

74.XX MHz (

)

Serial Data

(

)

Dual Standard

Block Description

For SD-SDI operation, you can derive the transmitter reference clock from using one of the Stratix GX PLLs. The PLL can multiply the 27-MHz

pclk

signal by 5/2.

For dual standard operation, use an external multiplexer to select between the SD-SDI and HD-SDI reference clock.

The Stratix GX architecture allows each group of four transmitters (a transceiver quad) to have a separate transmitter reference clock.

Tab le 3– 5 lists frequencies of the transmitter clock,

tx_serial_refclk

, for Stratix GX

devices.

Table 3–5. Transmitter Clock Frequency—Stratix GX Devices

Video Standard

(1)

Clock Frequency (MHz)

SD-SDI 67.5

HD-SDI (including dual link) 74.175/74.25

HD-SDI with two times oversample 148.35/148.5

Dual standard 67.5/74.175/74.25

Notes to Table 3–5:

(1) Stratix GX devices do not support 3G and triple standard modes.

tx_serial_refclk

(2) The

signal must be externally multiplexed.

(2)

Figure 3–8 shows the transmitter clocks for different video standards.

Figure 3–8. Transmitter Clocks—Stratix GX Devices

Notes to Figure 3–8:

(1) This frequency can be either 74.175 or 74.25 MHz, to support 1.4835 or 1.485 Gbps HD-SDI respectively. (2) The multiplexer must not be in the device.

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Chapter 3: Functional Description 3–15

Block Description

Receiver Clocks

The transceiver requires a receiver reference clock, trains the receiver PLL in the transceiver.

For HD-SDI operation, the clock must be nominally 1/20 clock do not have to operate at the data rate, because it is only used for the training of the receiver PLL.

For SD-SDI operation, the clock must be nominally 1/4 example, 67.5 MHz). The clock do not have to be frequency-locked to the data.

For dual standard operation, the receiver reference clock must be 67.5 MHz, which allows the transceiver to sample the data for SD-SDI at the correct frequency. For HD-SDI, the receiver PLL trains with the 67.5-MHz reference, and then tracks to the actual incoming data rate.

All receiver interfaces can share a common receiver reference clock.

rx_serial_refclk

of the serial data rate. The

of the serial data rate (for

. This clock

Tab le 3– 6 lists the frequencies of the receiver clock,

rx_serial_refclk

devices.

Table 3–6. Receiver Clock Frequency—Stratix GX Devices

Video Standard

(1)

Clock Frequency (MHz)

SD-SDI 67.5

HD-SDI (including dual link) 74.175/74.25

Dual standard 67.5

Notes to Table 3–6:

(1) Stratix GX devices do not support 3G-SDI and triple standard modes.

rx_serial_refclk

(2) The

signal must be externally multiplexed.

, for Stratix GX

(2)

February 2013 Altera Corporation Serial Digital Interface (SDI) MegaCore Function

User Guide

3–16 Chapter 3: Functional Description

rx_clk

rx_data

rx_data_valid_out

V VVV

SDI MegaCore

Function

74.25/74.175 MHz

Serial Data

HD-SDI

rx_clk = 74.25 MHz

rx_data_valid_out

rx_clk

rx_data

rx_data_valid_out

V VV V

SDI MegaCore

Function

67.5 MHz

Serial Data

SD-SDI

rx_clk = 67.5 MHz

rx_data_valid_out

SDI MegaCore

Function

67.5 MHz

Serial Data

Dual Standard

rx_clk = 67.5 or 74 MHz

rx_data_valid_out

Block Description

Figure 3–9 shows the receiver clocks for different video standards.

Figure 3–9. Receiver Clocks

Transmitter Transceiver Interface

Altera provides a transceiver interface, which interfaces the transceiver to the SDI function. The transceiver interface implements the following functions:

■ Transmitter Retiming

■ HD-SDI Two-Times Oversampling

■ SD-SDI Transmitter Oversampling

1 When using the two-times oversampling transmitters in Stratix GX devices, you

cannot have HD-SDI receivers in the same quad. The quad requires the same frequency reference clocks for both the receivers and transmitters within a quad. HD-SDI receivers and two-times oversampling transmitters have different frequency reference clocks (refer to Table 3–5 and Table 3–6 on page 3–15).

Serial Digital Interface (SDI) MegaCore Function February 2013 Altera Corporation User Guide

Transmitter Retiming

The

txdata

aligned to the

parallel data input to the transceiver must be synchronous and phase

tx_coreclk

requires a retiming function, because of the oversampling logic. The transmitter uses a small 16 × 20 FIFO buffer for the retiming.

transceiver clock input. SD-SDI (and optionally HD-SDI)

Chapter 3: Functional Description 3–17

rx_clk (67.5MHz)

rxdata

rx_data_valid_out

DATA

Block Description

For HD-SDI, the FIFO buffer realigns the parallel video input to the transceiver

tx_coreclk

clock. It is written on every

tx_pclk

clock, and read on every

tx_coreclk

For SD-SDI, the FIFO buffer also provides the rate conversion required by the transmitter oversampling logic. It is written on every other data width conversion logic. It is read on every fifth

tx_pclk

tx_coreclk

, using the SD-SDI

. This operation ensures that the transmitter oversampling logic is provided with a word of parallel video data on every fifth clock.

HD-SDI Two-Times Oversampling

This mode performs two-times oversampling and runs the transceiver at double rate, which gives better output jitter performance. This mode requires a higher rate reference clock, refer to Table 3–5 on page 3–14.

SD-SDI Transmitter Oversampling

Receiver Transceiver Interface

Altera provides a transceiver interface, which interfaces the transceiver to the SDI function. The transceiver interface implements the following functions:

■ SD-SDI Receiver Oversampling

■ Tran s cei ver C ont r o lle r

1 When using the two-times oversampling transmitters in Stratix GX devices, you

SD-SDI Receiver Oversampling

The Stratix GX transceiver does not support CDR for data rates less than 500 Mbps. The receiver uses fixed frequency oversampling for the reception of 270-Mbps SD-SDI. The serial data is sampled by the transceiver at 1,350 Mbps and the original 270-Mbps data is extracted by the SD-SDI receiver oversampling logic.

Figure 3–10 shows an example of the receiver data timing.

Figure 3–10. Receiver Data Timing

February 2013 Altera Corporation Serial Digital Interface (SDI) MegaCore Function

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3–18 Chapter 3: Functional Description

Transceiver Controller

To achieve the desired receiver functionality for the SDI, the transceiver controller controls the transceiver.

When the interface receives SD-SDI, the transceiver receiver PLL locks to the receiver reference clock.

When the interface receives HD-SDI, the transceiver receiver PLL is first trained by locking to the receiver reference clock. When the PLL is locked, it can then track the actual receiver data rate. If a period of time passes without a valid SDI signal, the PLL is retrained with the reference clock and the process is repeated.

The transceiver controller allows the transceiver to support the reception of both SD-SDI and HD-SDI data by using an algorithm that alternately searches for one rate then the other. First, it looks for an HD-SDI signal, training the PLL then letting it track the serial data rate. If a valid HD-SDI signal is not seen within 0.1 s, the receiver path is reset and the PLL is trained for SD-SDI. Conversely, if a valid SD-SDI signal is not seen within 0.1 s, the receiver path is reset and the process repeated. The transceiver controller also resets and starts searching again if the SDI receiver indicates that the signal is no longer valid.

For HD-SDI operation, if 100 consecutive bits with the same value are seen, the receiver is reset and the PLL is retrained. The maximum legal run length for HD-SDI is 59 bits.

Block Description

f For more information on the Stratix GX transceiver, refer to the Stratix GX Device

Handbook.

Transceiver—Arria GX, Arria II GX, Arria V, Cyclone IV GX, Cyclone V, Stratix II GX, Stratix IV GX, and Stratix V Devices

The Arria GX, Arria II GX, Arria V, Cyclone IV GX, Stratix II GX, Stratix IV GX, or Stratix V transceiver deserializes the high-speed serial input. For HD-SDI, the CDR function performs the deserialization and locks the receiver PLL to the receiver data. For SD-SDI, the transceiver provides a fixed frequency oversample of the serial data with the receiver PLL constantly locked to a reference clock, which allows the transceiver to support the 270-Mbps data rate.

Arria GX, Arria II GX, Arria V, Stratix II GX, Stratix IV GX, and Stratix V devices have two transmitter PLLs per quad. Each quad allows two independent transmitter rates. Receivers in a quad share a common training clock, but have independent receiver PLLs. Because the same training clock is used for SD-SDI and HD-SDI, receivers can accommodate the different standards within a single quad.

Arria II GX (including Arria II GZ) and Stratix IV GX devices also provide the option for you to enable an additional serial reference clock port. This additional clock port allows you to have two different clock rates for different data rates using a single transceiver block, with the ability to switch between the desired clock rates (for example, 148.5 MHz and 148.35 MHz).

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Chapter 3: Functional Description 3–19

Block Description

Cyclone IV GX devices—EP4CGX30 (F484), EP4CGX50, EP4CGX75, EP4CGX110, and EP4CGX150—have eight regular transceiver channels from the upper and lower quads. There are four MPLLs and two GPLLs that you can use to clock the transceiver channels. Each receiver in EP4CGX50 and EP4CGX75 devices has a clock divider, which allows one MPLL to drive all the receiver channels. The receiver in EP4CGX110 and EP4CGX150 devices does not have a clock divider, which limits each MPLL to drive only one receiver channel to accommodate the different standards within a single quad.

You must supply two receive reference clocks (for example, 148.5 MHz and

148.35 MHz) to the SDI receiver. Implement the PPM detection function in the user logic to detect the ppm difference between the receive reference clock and the recovered clock. Based on the difference detected, you must switch between the two receive reference clocks by toggling the

rx_serial_refclk_clkswitch

signal,

(Table 3–16 on page 3–41).

f For more information about the Cyclone IV GX transceiver architecture, refer to

Cyclone IV Transceivers Architecture chapter in volume 2 of the Cyclone IV Device

Handbook.

Cyclone V devices have up to 12 transceiver channels. The SDI support for Cyclone V transceivers requires the use of the Cyclone V Transceiver Native PHY IP Core. The native PHY is a thin IP layer with an embedded transceiver PLL.

The Cyclone V Transceiver Native PHY IP Core provides direct access to all control and status signals of the transceiver channels. Unlike other PHY IP cores, the Native PHY IP Core does not include an Avalon Memory-Mapped (Avalon-MM) interface. Instead, it exposes all signals directly as ports. The Cyclone V Transceiver Native PHY IP Core includes the Standard PCS. You can select the PCS functions and control and status port that your transceiver PHY requires. The Native Transceiver PHY does not include an embedded reset controller.

f For more information about the Cyclone V Transceiver Native PHY IP Core, refer to

the Altera Transceiver PHY IP Core User Guide.

Transmitter Clocks

The transmitter requires two clocks: a parallel video clock ( reference clock (

tx_serial_refclk

The parallel video clock samples and processes the parallel video input. For SD-SDI, it is 27 MHz; for HD-SDI, it is 74.25 or 74.175 MHz; for 3G-SDI, it is 148.5 or 148.35 MHz.

The transceiver uses the transmitter reference clock to generate the high-speed serial output. The transceiver is configured for 20-bit operation, so the reference clock is

1/20

of the serial data rate.

1 For SD-SDI, because of the oversampling implementation, the serial data rate is five

times the SDI bit rate (for example, 1,350 Mbps); for the triple-standard SDI, the oversampling rate is 11.

tx_pclk

) and a transmitter

For SD-SDI operation, the transmitter reference clock can be derived from using one of the transceiver PLLs. The PLL can multiply the 27-MHz

pclk

signal by

5/2.

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3–20 Chapter 3: Functional Description

Block Description

For all other standards, use an external multiplexer to select between the alternative reference clocks.

Tab le 3– 7 lists the frequencies of the transmitter clock,

tx_serial_refclk

, for Arria GX, Arria II GX, Arria V, Cyclone IV GX, Cyclone V, Stratix II GX, Stratix IV, and Stratix V devices.

Table 3–7. Transmitter Clock Frequency—Arria GX, Arria II GX, Arria V, Cyclone IV GX, Cyclone V, Stratix II GX, Stratix IV, and Stratix V Devices

Video Standard Clock Frequency (MHz)

SD-SDI 67.5

HD-SDI (including dual link) 74.175/74.25

HD-SDI with two times oversample 148.35/148.5

Dual standard 67.5/74.175/74.25

Triple standard 148.35/148.5

3G-SDI 148.35/148.5

Note to Tab le 3– 7:

(1) The

tx_serial_refclk

for serial reference clock, external multiplier is no longer required.

signal must be externally multiplexed. If additional input reference clock port is enabled

(1)

Serial Digital Interface (SDI) MegaCore Function February 2013 Altera Corporation User Guide

SDI MegaCore

Function

74.XX MHz (

)

from reference clock

Serial Data

HD-SDI

SDI MegaCore

Function

148.XX MHz (

)

from reference clock

Serial Data

3G-SDI or Triple Standard

SDI MegaCore

Function

67.5 MHz

from PLL or Pin

Serial Data

SD-SDI

SDI MegaCore

Function

67.5 MHz

74.XX MHz (

)

Serial Data

(

)

Dual Standard

SDI MegaCore

Function

148.35 MHz (4)

Serial Data

3G-SDI or Triple Standard (with additional reference clock port)

148.5 MHz

Chapter 3: Functional Description 3–21

Block Description

Figure 3–11 shows the transmitter clocks for different video standards.

Figure 3–11. Transmitter Clocks—Arria GX, Arria II GX, Arria V, Cyclone IV GX, Cyclone V, Stratix II GX, Stratix IV, and Stratix V Devices

Notes to Figure 3–11:

(1) This frequency can be either 74.175 or 74.25 MHz, to support 1.4835 or 1.485 Gbps HD-SDI respectively. (2) The multiplexer must not be in the device. (3) This frequency can be either 148.35 or 148.5 MHz, to support 2.967 or 2.970 Gbps HD-SDI respectively. (4) You can source both 148.5 MHz and 148.35 MHz together if the additional clock port is enabled.

February 2013 Altera Corporation Serial Digital Interface (SDI) MegaCore Function

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3–22 Chapter 3: Functional Description

Block Description

Receiver Clocks

The transceiver requires a receiver reference clock, trains the receiver PLL in the transceiver.

For HD-SDI operation, the clock must be nominally 1/20 clock does not have to be frequency locked to the data, because the design only uses it for the training of the receiver PLL.

For SD-SDI operation, the clock must be nominally 1/4 (for example, 67.5 MHz). The clock does not have to be frequency locked to the data.

For dual or triple standard operation, the receiver reference clock must be 148.5 MHz. In this mode, the transceiver oversamples the SD-SDI signals by a factor of 11.

All receiver interfaces can share a common receiver reference clock.

rx_serial_refclk

of the serial data rate. The

of the serial data rate

. This clock

Tab le 3– 8 shows the receiver clock

rx_serial_refclk

frequencies.

Table 3–8. Receiver Clock Frequency—Arria GX, Arria II GX, Arria V, Cyclone IV GX, Cyclone V, Stratix II GX, Stratix IV, and Stratix V Devices

Video Standard Clock Frequency (MHz)

SD-SDI 67.5

HD-SDI (including dual link) 74.175/74.25

Dual or triple standard 148.35/148.5

3G-SDI 148.35/148.5

Notes to Table 3–8:

(1) You can use either reference clock for training. (2) Must be 148.5 MHz for correct SD-SDI operation.

(1)

(1), (2)

(1)

Serial Digital Interface (SDI) MegaCore Function February 2013 Altera Corporation User Guide

Chapter 3: Functional Description 3–23

rx_clk

rx_data

rx_data_valid_out

V VVV

SDI MegaCore

Function

74.25 or 74.175 MHz

Serial Data

HD-SDI

rx_clk = 74.175 or 74.25 MHz

rx_data_valid_out

SDI MegaCore

Function

148.5 MHz

Serial Data

3G-SDI or Dual Standard or Triple Standard

rx_clk = 148.5 MHz (or 74.xx MHz when receiving HD)

rx_data_valid_out

rx_clk

rx_data

rx_data_valid_out

V VV V

SDI MegaCore

Function

67.5 MHz

Serial Data

SD-SDI

rx_clk = 67.5 or 74 MHz

rx_data_valid_out

Block Description

Figure 3–12 shows the receiver clocks for different video standards.

Figure 3–12. Receiver Clocks

February 2013 Altera Corporation Serial Digital Interface (SDI) MegaCore Function

Transmitter Transceiver Interface

Altera provides a transceiver interface, which interfaces the transceiver to the SDI function. The transceiver interface implements the following functions:

■ Retiming from the parallel video clock domain to the transceiver transmitter clock

domain

■ Optional two-times oversampling for HD

■ Transmitter oversampling for SD

Transmitter Retiming

The

txdata

aligned to the

parallel data input to the transceiver must be synchronous and phase

tx_coreclk

requires a retiming function, because of the oversampling logic. The transmitter uses a small 16 × 20 FIFO buffer for the retiming.

For HD-SDI, the FIFO buffer realigns the parallel video input to the transceiver

tx_coreclk

clock. It is written on every

transceiver clock input. SD-SDI (and optionally HD-SDI)

tx_pclk

clock, and read on every

tx_coreclk

User Guide

3–24 Chapter 3: Functional Description

rx_clk (67.5MHz)

rxdata

rx_data_valid_out

DATA

Block Description

For SD-SDI, the FIFO buffer also provides the rate conversion required by the transmitter oversampling logic. It is written on every other data width conversion logic. It is read on every fifth or eleventh

tx_pclk

tx_coreclk

, using the SD-SDI

. This operation ensures that the transmitter oversampling logic is provided with a word of parallel video data on every fifth or eleventh clock.

HD-SDI Two-Times Oversampling

SD-SDI Transmitter Oversampling

SD-SDI requires a 270-Mbps serial data rate, which is achieved by transmitting a 1,350 Mbps signal with each bit repeated five times. This process ensures that the transceiver runs at a supported frequency. In triple standard mode, bit are transmitted at 2,970 Mbps with each bit repeated 11 times.

Receiver Transceiver Interface

Altera provides a transceiver interface, which interfaces the transceiver to the SDI function. The transceiver interface implements the following functions:

■ SD-SDI Receiver Oversampling

■ Tran s cei ver C ont r o lle r

SD-SDI Receiver Oversampling

Arria GX and Stratix II GX transceivers do not support CDR for data rates less than 622 Mbps. Arria II GX, Arria V, Stratix IV, and Stratix V transceivers do not support CDR for data rates less than 600 Mbps. The receiver uses fixed frequency oversampling for the reception of 270-Mbps SD-SDI. The transceiver samples the serial data at 1,350 or 2,970 Mbps and the SD-SDI receiver oversampling logic extracts the original 270 Mbps data.

Figure 3–13 shows an example of the receiver data timing.

Figure 3–13. Receiver Data Timing

Transceiver Controller

To achieve the desired receiver functionality for the SDI, the transceiver controller controls the transceiver.

When the interface receives SD-SDI, the transceiver receiver PLL locks to the receiver reference clock.

Serial Digital Interface (SDI) MegaCore Function February 2013 Altera Corporation User Guide

Chapter 3: Functional Description 3–25

trs_strobe

word count

trs_loose_lock

New TRS reasserts

n-th missing EAV

Block Description

First, the transceiver controller makes a coarse rate detection of the incoming data stream. Then, the transceiver is reprogrammed using transceiver dynamic reconfiguration (refer to “Transceiver Dynamic Reconfiguration for Dual Standard

and Triple Standard Receivers” on page 3–27 and “Transceiver Dynamic Reconfiguration with PLL Reconfiguration Mode—Cyclone IV GX” on page 3–33) to

the correct rate for the standard that has been detected. After the reprogramming, the transceiver attempts to lock to the incoming stream. If no valid data is seen in 0.1 s, the receiver path is reset and the rate detection is performed again.

At the start of the rate detection process, the level of the three sampled. The level of these signals and the knowledge of the currently programmed state of the transceiver determines if the transceiver requires programming. This process ensures that the transceiver is reprogrammed only when necessary.

Locking to the Incoming SDI Stream

The transceiver control state machine uses the presence (or absence) of TRSs on the stream to determine if SDI is being correctly received. A single, valid TRS indicates to the control state machine that the receiver is acquiring some valid SDI samples. The control state machine only deasserts this flag when it does not detect any EAV sequences within the number of consecutive lines you specified. At this point, the controller state machine resets and performs the relock algorithm, refer to

Figure 3–14.

Figure 3–14. Locking Algorithm

Because the aligner realigns to a new alignment if two consecutive TRSs with the same alignment are detected, this scheme allows for an SDI source switch and an alignment change without affecting the transceiver reset state machine.

enable_xx

signals is

The SDI MegaCore function also monitors the incoming EAV and SAV signals to ensure their spacing is consistent over a number of lines. The MegaCore function monitors by incrementing a counter on each incoming SDI word and storing the count values at which an EAV or SAV is detected. If the EAV and SAV spacing is consistent over 6 video lines, the MegaCore function indicates

trs_locked

on the

rx_status[3]

output.

An enhancement in the current SDI MegaCore function allows a number of missing EAV or SAV that you specify to be tolerated without deasserting the

trs_locked

signal.

For example, when you specify the Tolerance to consecutive missed EAV/SAV parameter to 2, one or two consecutive missing EAVs set a “missed” flag but do not cause the

trs_locked

signal to deassert. A good EAV in the correct position resets the

“missed” flag.

The operation of this missing or misplaced TRS tolerance is shown in Figure 3–15,

Figure 3–16, and Figure 3–17.

February 2013 Altera Corporation Serial Digital Interface (SDI) MegaCore Function

User Guide

3–26 Chapter 3: Functional Description

data

trs_strobe

prev_eav_missed

g host_eav

trs_locked

EAV SAV

1st error in EAV

SAV

2nd error in EAV SAV

3rd error in EAV SAV

Block Description

Figure 3–15 and Figure 3–16 show how one or two consecutive missing EAVs do not

cause the

trs_locked

signal to deassert.

Figure 3–15. Single Missing EAV Signal

Error in EAV SAV

data

EAV SAV

trs_strobe

prev_eav_missed

g host_eav

trs_locked

EAV SAV

Figure 3–16. Two Consecutive Missing EAV Signal

1st error in EAV SAV

data

EAV SAV

trs_strobe

prev_eav_missed

g host_eav

trs_locked

2nd error in EAV SAV

Figure 3–17 shows how three consecutive missing EAVs cause the

trs_locked

signal

to deassert.

Figure 3–17. Three Consecutive Missing EAV Signal

The

frame_locked

signal detects TRS EAV, inspects the transition of field (F) and vertical (V) synchronizations, and then counts the line number. The inspecting transitions on the F and V synchronizations provide the frame timing. The line count value is stored if there is a rising or falling edge on the F and V synchronizations through the frame. The stored count values are compared over multiple frames to make sure they are stable, before the

The

frame_locked

signal deasserts when there are bad F or V synchronizations, or when there is a rising edge from frame to frame. The deasserts when the

When the

frame_locked

trs_locked

signal is zero, the frame is invalid, and the receiver is not

frame_locked

signal deasserts.

signal is asserted.

frame_locked

signal also

considered to receive reliable video data.

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Chapter 3: Functional Description 3–27

Block Description

Transceiver Dynamic Reconfiguration for Dual Standard and Triple Standard Receivers

Dual standard and triple standard SDI receivers (or receivers of duplex SDIs) require the transceiver dynamic reconfiguration feature of Arria GX, Arria II GX, Cyclone IV GX, Stratix II GX, and Stratix IV devices to perform autodetection and locking to different SDI rates.

Tab le 3– 9 lists the transceiver dynamic reconfiguration support for Arria II GX,

Cyclone IV GX, HardCopy IV GX, Stratix GX, Stratix II GX, and Stratix IV GX devices.

Table 3–9. Transceiver Dynamic Reconfiguration Support for Altera Devices

Transceiver Dynamic

Reconfiguration Support

Channel Reconfiguration Yes Yes No

PLL Reconfiguration No Yes Yes

Transceiver Reconfiguration No No No

Note to Table 3–9:

(1) The SDI MegaCore function versions 10.1 and later do not support MIF generation for EP4CGX30 (F484), EP4CGX50, and EP4CGX75. (2) The ALTGX_RECONFIG is required for offset cancellation purposes for all transceiver instances.

Arria II GX, HardCopy IV GX, Stratix GX,

Stratix II GX,

and Stratix IV GX

(1)

Cyclone IV GX

(EP4CGX50, EP4CGX75)

Cyclone IV GX

(EP4CGX110,

EP4CGX150)

f For more information about transceiver dynamic reconfiguration, refer to the

Arria GX Device Handbook, Arria II GX Device Handbook, Cyclone IV Device Handbook, Stratix II GX Device Handbook, and Stratix IV Device Handbook.

Transceiver Dynamic Reconfiguration with Channel Reconfiguration Mode— Arria II GX, HardCopy IV GX, Stratix GX, Stratix II GX, and Stratix IV GX

Transceiver dynamic reconfiguration allows you to change the settings of the device transceivers (ALT2GXB or ALTGX) at any time. Transceiver dynamic reconfiguration reprograms the transceivers to support the three SDI rates.

(2)

The triple standard SDI uses 11 times oversampling for receiving SD-SDI. Hence, only Arria II GX or Stratix II GX transceiver configurations are required as the rates for 3G-SDI and SD-SDI 11 times are the same.

February 2013 Altera Corporation Serial Digital Interface (SDI) MegaCore Function

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3–28 Chapter 3: Functional Description

Block Description

Tab le 3– 10 lists the transceiver dynamic reconfiguration requirements.

Table 3–10. Transceiver Dynamic Reconfiguration Requirements

SDI Standard Receiver Transmitter

(1)

Duplex

(1)

SD-SDI No Yes Yes

HD-SDI No Yes Yes

3G-SDI No Yes Yes

Dual link No Yes Yes

Dual standard Yes Yes Yes

Triple standard Yes Yes Yes

Note to Tab le 3– 10:

(1) If the additional serial reference clock feature is enabled, the transmitters require dynamic reconfiguration to

enable toggling switching between the two input clocks.

Tab le 3– 11 lists the rates for the different SDI standards.

Table 3–11. SDI Standard Rates

Transceiver

Reference Clock

(MHz)

rx_clk Rate

SDI Standard Data Rate Oversampling

Transceiver

Rate (MHz)

SD-SDI 270 Mbps 11 times 2,970 148.5 148.5

HD-SDI 1.485 Gbps None 1,485 148.5

3G-SDI 2.970 Gbps None 2,970 148.5

Note to Tab le 3– 11:

(1) Also supports the 1/1.001 rates for all supported devices, except Cyclone IV GX devices. For Cyclone IV GX

devices, the transceiver reference clock must be 148.35 MHz to support the 1/1.001 rates.

(1)

74.25

148.5

To reprogram the transceivers, you must include the ALT2GXB_RECONFIG or ALTGX_RECONFIG megafunction in your design. However, to reprogram Arria II GX or Stratix IV device family, you require an ALTGX_RECONFIG megafunction. You can get this parameterization from the example\a2gx_tr\source\sdi_dprio_siv directory in the example design. Similarly, to reprogram Cyclone IV GX device family with channel reconfiguration mode, you require a slightly different configuration of the ALTGX_RECONFIG megafunction. You can get this parameterization from the simulation\modelsim\trsdi_c4gx\channel_reconfig\testbench\pattern_gen directory in the example simulation.

f For more information about the ALT2GXB_RECONFIG megafunction, refer to the

Stratix II GX ALT2GXB_RECONFIG Megafunction User Guide. For more information

about the ALTGX_RECONFIG megafunction, refer to the Stratix IV

ALTGX_RECONFIG Megafunction User Guide.

(1)

Serial Digital Interface (SDI) MegaCore Function February 2013 Altera Corporation User Guide

Chapter 3: Functional Description 3–29

Block Description

Transceiver Reconfiguration for Transmitter Clock Multiplexer

The transmitter reconfiguration requires its own Memory Initialization Files (.mif) that is stored in the device. The .mif contains information about the default selection of the TX PLL that is based on the

logical_tx_pll_sel

and

logical_tx_pll_sel_en

pins. These pins are available in the transceiver port when you enable the transmitter clock multiplexer feature. By toggling the values in these ports and reconfiguring the transmitter megafunction, you can internally switch the TX PLL to select different reference clock inputs. For Arria II and Stratix IV devices, these are 19-words by 16bits files. The following are the sequence of events that occur during the SDI transmitter clock toggling:

1. SDI MegaCore function detects a change request to the serial reference clock.

2. The ALTGX_RECONFIG block reads the appropriate ROM, sets the

logical_tx_pll_sel

and

logical_tx_pll_sel_en

ports to the required value, and

reprograms the ALTGX in the transmitter block.

3. When step 2 is completed, the SDI transmitter begins locking on the new serial

reference clock.

1 User logic is required in handling the handshaking between the SDI MegaCore

function and the ALTGX_RECONFIG block.

1 By default, the receiver reconfiguration has higher priority than the transmitter

reconfiguration.

Transceiver Reconfiguration for Receiver

The ROMs store the alternative setups for the transceiver settings within the device. These setups are 28 words by 16 bits for Arria GX and Stratix II GX devices, and 38 words by 16 bits for Arria II and Stratix IV devices. The ALT2GXB megafunction has a serial reprogramming interface, so the ALT2GXB_RECONFIG block must serialize this parallel data before loading.

The following sequence of events occur during an SDI receiver rate change:

1. SDI MegaCore function detects the incoming video rate and requests

reprogramming.

2. The ALT2GXB_RECONFIG block reads the appropriate ROM, serializes the data,

and applies the serial data to the correct transceiver instance.

3. When step 2 is completed, the ALT2GXB_RECONFIG block indicates to the SDI

that reprogramming is complete.

4. The SDI starts the process of locking to the incoming data.

1 Some user logic is required to handle the handshaking between the SDI

MegaCore function and the ALT2GXB_RECONFIG megafunction. For example, refer to the example design in the example\s2gx_tr\source\sdi_dprio directory.

February 2013 Altera Corporation Serial Digital Interface (SDI) MegaCore Function

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3–30 Chapter 3: Functional Description

Block Description

Figure 3–19 shows a flow chart of the SDI dynamic reconfiguration process for

transceiver-based devices.

Figure 3–18. Dynamic Reconfiguration Process Flow for Transceiver-based Devices

ALT2GXB_RECONFIG Control Logic

Idle

SDI MegaCore (Receiver/Duplex)

Normal Operation

Data

Rate Change?

Ye s

Start DPRIO

Reconfiguration

in Process

Reconfiguration

Done?

Ye s

Notes to Figure 3–18:

(1) SDI MegaCore (Receiver/Duplex) asserts

transceiver is being reconfigured.

rx_analogreset

(2) The

signal deasserts when

signal deasserts when the transceiver is completely reconfigured, and

rx_pll

is stable.

SDI_START_RECONFIG

SDI_RECONFIG_DONE

rx_analogreset

and

rx_digitalreset

Reconfiguration

in Process

ALT2GXB_RECONFIG

Busy?

Write to ALT2GXB

Last ROM

Address?

Ye s

Reconfiguration

Done

signals to transceiver when the

Ye s

rx_digitalreset

Serial Digital Interface (SDI) MegaCore Function February 2013 Altera Corporation User Guide

Chapter 3: Functional Description 3–31

ALT2GXB

RECONFIG_INST

RECONFIG Control

and Intercept

User Logic

ALT2GXB_INST

Protocol

SDI IP Core - Receiver

RECONFIG_TOGXB[2:0]

ROM_CLK_ENABLE

ROM_ADDRESS

ROM_DATA_OUT

if (ROM_ADDRESS = RX PMA)

select_hd

User Logic

Encrypted RECONFIG Megafunction

Encrypted SDI IP Core

HD: M, L value

3G/SD: M, L value

ROM (Hold MIF)

3G by default

RECONFIG_FROMGXB[0]

SDI_RECONFIG_DONE (1)

SDI_START_RECONFIG (1)

RX_STD

ALT2GXB_INST

Protocol

SDI IP Core - Duplex

ALT2GXB_INST

Protocol

SDI IP Core - Transmitter

Block Description

Figure 3–19 shows the block diagram of how the SDI MegaCore function and the

ALT2GXB_RECONFIG megafunction are connected.

Figure 3–19. Transceiver Dynamic Reconfiguration for Receiver Block Diagram

Note to Figure 3–19:

(1) The

SDI_START_RECONFIG

and

SDI_RECONFIG_DONE

signals are not connected to the SDI MegaCore transmitter.

The ALT2GXB_RECONFIG block handles the programming of the ROM contents into the transceiver megafunction. It performs data serialization and also handles protection of certain data bits in the serial stream. You can only connect this block to the reprogramming ports of the transceiver instance.

The ROM holds the transceiver setting information for the 3G-SDI video standard. As the setup for SD-SDI is similar to 3G-SDI, only two settings are required: one for SD-SDI and 3G-SDI, and one for HD-SDI.

The reconfiguration control and intercept user logic selects the correct transceiver setting and also provides the handshaking between the SDI MegaCore function and the ALT2GXB_RECONFIG block. The logic modifies the ROM read data when it reads word 23 for all devices, barring Arria II GX and Stratix IV devices. For Arria II GX and Stratix IV devices, the logic modifies the ROM read data when it reads word 29. For examples, refer to the intercept logic,

example\s2gx_tr\source\sdi_dprio\sdi_mif_intercept.v and example\a2gx_tr\source\sdi_dprio_siv\sdi_mif_intercept_siv.v.

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3–32 Chapter 3: Functional Description

ALT2GXB

RECONFIG_INST

RECONFIG Control

and Intercept

User Logic

RECONFIG_TOGXB[2:0]

ROM_CLK_ENABLE

ROM_ADDRESS

ROM_DATA_OUT

TX_PLL_SELECT

Transmitter

only

User Logic

Encrypted RECONFIG Megafunction

Encrypted SDI IP Core

ROM (Hold MIF)

RECONFIG_FROMGXB[0]

SDI_RECONFIG_DONE

SDI_START_RECONFIG

ALT2GXB_INST

Protocol

SDI IP Core - Duplex

ALT2GXB_INST

Protocol

SDI IP Core - Transmitter

Block Description

The transceiver megafunction is embedded inside the SDI MegaCore function. The reprogramming ports (

reconfig_togxb[3:0]

and

reconfig_fromgxb[<(N×16)-1>:0]

for the transceiver megafunction are brought to the top-level interfaces of the MegaCore function. This interface only connects to the ALT2GXB_RECONFIG or ALTGX_RECONFIG block.

Figure 3–19 shows the block diagram of how the SDI MegaCore function and the

ALT2GXB_RECONFIG megafunction are connected when you use the transmitter clock multiplexer feature.

Figure 3–20. Transceiver Dynamic Reconfiguration for Transmitter Clock Multiplexer Block Diagram

)

Serial Digital Interface (SDI) MegaCore Function February 2013 Altera Corporation User Guide

When enabling the transmitter clock multiplexer feature, the ALT2GXB_RECONFIG block handles the programming of the ROM contents to the transceiver megafunction. The ROM holds the information setting for the default reference clock selection of the TX PLL in the transmitter, as well as the values of the

logical_tx_pll_sel_en

pins. The reconfiguration control and intercept user logic

block detects changes in the trigger port, sets the

logical_tx_pll_sel_en

to the corresponding value, and initiates the reprogramming

logical_tx_pll_sel

and

of the transmitter megafunction.

ALT2GXB_RECONFIG Connections for Receiver

The between the SDI MegaCore function and the user logic. The

SDI_START_RECONFIG

and

SDI_RECONFIG_DONE

signals handle the handshaking

RX_STD

signal must select

the correct transceiver setting.

1 Table 3–19 on page 3–54 lists the five signals that handle transceiver dynamic

reconfiguration.

Chapter 3: Functional Description 3–33

SDI MegaCore Ports

SDI_START_RECONFIG

RX_STD[1:0]

SDI_RECONFIG_DONE

ALT2GXB_RECONFIG Ports

RECONFIG_DATA

ROM_ADDRESS

CHANNEL_RECONFIG_DONE

RECONFIG_TO_GXB

VALID

0 1 ... 26 2727

3452

Block Description

Figure 3–21 shows the handshaking between the SDI MegaCore function and the user

logic, and the expected output of some of the

ALT2GXB_RECONFIG

signals.

Figure 3–21. Handshaking Between SDI MegaCore Function and ALT2GXB_RECONFIG Signals

The following sequence of events occur for handshaking to the reconfiguration logic:

1. The SDI MegaCore function sets

rx_std[1:0]

to the desired video standard. This

action is performed as part of the video standards detection algorithm.

2. The SDI MegaCore function asserts

SDI_START_RECONFIG

to make a

reconfiguration request.

3. The user logic sets

SDI_RECONFIG_DONE

to 0, which indicates to the MegaCore

function that the reconfiguration is in progress.

4. When the reconfiguration has been performed, the user logic sets the

SDI_RECONFIG_DONE

to logic 1, which indicates to the SDI MegaCore function to

start locking to the incoming data.

5. The SDI MegaCore function sets the

SDI_START_RECONFIG

line to 0 to indicate that

the request is completed and acknowledged.

1 The CRC error signal is asserted during the reconfiguration of the

transceiver in the receiver. The assertion of the CRC error signal is normal during receiver reconfiguration as the receiver protocol is interrupted.

Transceiver Dynamic Reconfiguration with PLL Reconfiguration Mode— Cyclone IV GX

To implement transceiver dynamic reconfiguration for dual and triple standard SDI using Cyclone IV GX devices, you can also use PLL reconfiguration mode. To reprogram Cyclone IV GX device family with PLL reconfiguration mode, you must include the ALTPLL_RECONFIG megafunction in your design. You can get this parameterization from the simulation\modelsim\trsdi_c4gx\pll_reconfig\testbench\pattern_gen directory in the example simulation.

February 2013 Altera Corporation Serial Digital Interface (SDI) MegaCore Function

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3–34 Chapter 3: Functional Description

ALTPLL_RECONFIG

RECONFIG

Control Logic

ALTGX_INST

Protocol

SDI IP Core - Receiver

User Logic

Encrypted RECONFIG Megafunction

Encrypted SDI IP Core

ROM 3G

ROM HD

pll_areset pll_configupdate pll_scanclk pll_scanclkena pll_scandata

sdi_start_reconfig rx_std

pll_scandataout pll_scandone

rom_address_out write_rom_enable

write_from_rom reconfig

rom_address_out

rom_data_in

Block Description

Figure 3–22 shows the block diagram of how the SDI MegaCore function and the

ALTPLL_RECONFIG megafunction are connected.

Figure 3–22. Transceiver Dynamic Reconfiguration Block Diagram Using PLL Reconfiguration Mode

The ALTPLL_RECONFIG block handles the programming of the ROM contents into the transceiver megafunction. The ROM holds the transceiver setting information for 3G-SDI video standard. As the setup for SD-SDI is similar to 3G-SDI, only two settings are required: one for SD-SDI and 3G-SDI, and one for HD-SDI.

The reconfiguration control logic selects the correct transceiver setting and also provides the handshaking between the SDI MegaCore function and the ALTPLL_RECONFIG block. The PLL reprogramming signals for the transceiver are brought to the top-level interface of the SDI MegaCore function. This interface is only available when you select Use PLL reconfiguration for transceiver dynamic reconfiguration option in the SDI parameter editor. You must connect this interface only to the ALTPLL_RECONFIG block.

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Chapter 3: Functional Description 3–35

SDI_START_RECONFIG

RX_STD[1:0]

11 01

PLL_ARESET

PLL_CONFIGUPDATE

PLL_SCANCLK

PLL_SCANCLKENA

PLL_SCANDATA

PLL_SCANDATAOUT

PLL_SCANDONE

PLL_RECONFIG

RESET_ROM_ADDRESS

ROM_DATA_IN

WRITE_FROM_ROM

BUSY

WRITE_ROM_ENA

ROM_ADDRESS_OUT

34 5

Block Description

ALTPLL_RECONFIG Connections

Figure 3–21 shows the handshaking between the SDI MegaCore function and the

reconfig control logic, and the expected output of some of the

ALTPLL_RECONFIG

signals.

Figure 3–23. Handshaking between SDI MegaCore Function and ALTPLL_RECONFIG Signals

The following sequence of events occur for handshaking to the reconfiguration logic:

1. The SDI MegaCore function sets

rx_std[1:0]

to the desired video standard. This

action is performed as part of the video standards detection algorithm.

2. The SDI MegaCore function asserts

SDI_START_RECONFIG

to make a

reconfiguration request.

3. The reconfig control logic sets

WRITE_FROM_ROM

line to 1, and signals the

ALTPLL_RECONFIG megafunction to write from the ROM.

4. The reconfig control logic asserts the

PLL_RECONFIG

line to 1, and signals the

ALTPLL_RECONFIG megafunction to start the reconfiguration process.

5. When the reconfiguration has been performed, the transceiver’s PLL asserts the

output signal,

PLL_SCANDONE

, to the ALTPLL_RECONFIG megafunction indicating

that the PLL is reconfigured, and internally indicates to the SDI MegaCore

February 2013 Altera Corporation Serial Digital Interface (SDI) MegaCore Function

function to start locking to the incoming data.

6. The SDI MegaCore function sets the

SDI_START_RECONFIG

the request is completed and acknowledged.

line to 0 to indicate that

User Guide

3–36 Chapter 3: Functional Description

Block Description

Reset Requirement During Reconfiguration

When a receiver, placed in the same channel with a transmitter, detects a video format change, the receiver goes through a reset sequence for reconfiguration. However, as both the receiver and transmitter work independently, the IP core does not reset the transmitter during the receiver reconfiguration. If you require the transmitter to go through a reset sequence, you can reset it externally.

To reset the transmitter externally, you must instantiate a separate transmitter and receiver at the Interface Settings option. Then, connect the signal from the receiver instance to the

rst

input port in the corresponding transmitter instance, while the dynamic reconfiguration controller reconfigures the receiver, refer to Figure 3–24.

Figure 3–24. Resetting Transmitter Externally During Receiver Reconfiguration

Receiver and Transmitter in One Channel

SDI_START_RECONFIG

sdi_reset

SDI_START_RECONFIG

rst

Receiver Instance

(SDI MegaCore)

Transmitter Instance

(SDI MegaCore)

rst

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Chapter 3: Functional Description 3–37

sdi_start_reconfig

Reconfiguration

In Progress

Reconfiguration

Complete

sdi_reconfig_done

(Input to SDI

MegaCore Function)

analog_reset

(Rx GXB)

digital_reset

(Rx GXB)

PLL_LOCK

(Active Low)

Block Description

Figure 3–25 shows a timing diagram of the receiver reset sequence.

Figure 3–25. Reset Sequence of the Receiver During Reconfiguration

The following sequence of events occur for the reset sequence of the receiver:

1. The SDI MegaCore function resets the Rx transceiver (analog and digital reset are

asserted) after detecting a change in the data rate.

2. The SDI MegaCore function asserts

SDI_START_RECONFIG

to make a reconfiguration request to the ALT2GXB_RECONFIG block. The ALT2GXB_RECONFIG block sets

SDI_RECONFIG_DONE

to 0, which indicates to the

MegaCore function that the reconfiguration is in progress.

3. When the reconfiguration has been performed, the ALT2GXB_RECONFIG block sets the

SDI_RECONFIG_DONE

to logic 1, which indicates to the SDI MegaCore function to start locking to the incoming data. The analog reset of the SDI MegaCore function receiver is deasserted.

4. When the CDR PLL locks to the received data (HD/3G mode) or reference clock (SD mode) successfully, the digital reset of the SDI MegaCore function receiver is deasserted so that the receiver can continue to process valid data.

5. The SDI MegaCore function sets the

SDI_START_RECONFIG

line to 0 to indicate that

the request is completed and acknowledged.

Generation of ROM Contents

For Arria GX and Stratix II GX devices, the contents of the ROM are set by .mif. The Quartus II software outputs the .mif for the configuration settings of the ALT2GXB instance that is set by the design.

1 This file generation is not performed by default. You must adjust the Fitter settings.

On the Assignments menu, click Settings. In the Settings dialog box, click Fitter Settings, and then click More Settings. In the Name list, select Generate GXB Reconfig MIF and in the Setting list, select On.

February 2013 Altera Corporation Serial Digital Interface (SDI) MegaCore Function

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3–38 Chapter 3: Functional Description

Block Description

For the SDI MegaCore function, the Quartus II-generated .mif is for 3G-SDI setup.

1 These .mif files relate to a specific ALT2GXB instance in the device. Therefore, you

cannot use the same .mif files or ROMs for multiple ALT2GXBs in the same device.

For the SDI MegaCore function, the differences between the ALT2GXB setups are very small. Only three bits of the ROM change between the HD-SDI and SD-SDI, or 3G-SDI setups. The three bits are in word 23 and you can see in the following examples of the .mif files (Example 3–1 and Example 3–2).

Example 3–1. 3G-SDI ROM Content Example

....

22 : 1010100000011111; 23 : 0111110000010100; 24 : 0001000101101000;

....

Example 3–2. HD-SDI ROM Content Generated from 3G-SDI Version

....

22 : 1010100000011111; 23 : 0111110000001101; 24 : 0001000101101000;

....

This particular word is static over all SDI ALT2GXB instances in the device. You can generate the .mif for the HD-SDI ROM from the .mif that the Quartus II software generates by modifying this memory word within the .mif.

Starting Channel Number

To correctly address each transceiver by the ALT2GXB_RECONFIG block, you must specify a starting channel number for each transceiver instance in the parameter editor. This starting channel number must meet certain criteria for the transceiver dynamic reconfiguration.

f For more information about the criteria, refer to the Arria GX Device Handbook,

Arria II GX Device Handbook, Stratix II GX Device Handbook, and Stratix IV Device Handbook.

Quartus II Design Flow

For Arria GX and Stratix II GX devices, SDI MegaCore function designs using transceiver dynamic reconfiguration require a two-pass compilation. The first compilation writes the ALT2GXB setup as a .mif. During this compilation, you must set the .mif ROMs in the design to have a dummy .mif for their initialization.

Before the second compilation, set the initialization .mif files of the ROMs to be generated in the first compilation. This second compilation, therefore sets up the ROMs to have the correct settings for the ALT2GXB megafunction.

This process requires the following steps:

1. Set the reconfiguration ROMs in the designs with a dummy .mif.

2. Run the Quartus II compilation and ensure that the software writes the .mif files.

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Signals

3. Copy and modify the .mif files for the HD-SDI ROMs and edit word 23.

4. Set the appropriate ROMs to use the .mif files generated in steps 2 and 3.

5. Run the Quartus II compilation.

For Arria II GX and Stratix IV devices, you must set the ROMs to use the fixed .mif in the example\a2gx_tr\source\sdi_dprio_siv directory and compile once. Ensure that you use the supporting reconfiguration code in the same directory for your design.

OpenCore Plus Time-Out Behavior

OpenCore Plus hardware evaluation can support the following two modes of operation:

■ Untethered—the design runs for a limited time

■ Tethered—requires a connection between your board and the host computer. If

tethered mode is supported by all megafunctions in a design, the device can operate for a longer time or indefinitely

All megafunctions in a device time out simultaneously when the most restrictive evaluation time is reached. If there is more than one megafunction in a design, a specific megafunction’s time-out behavior may be masked by the time-out behavior of the other megafunctions.

1 For MegaCore functions, the untethered time-out is 1 hour; the tethered time-out

value is indefinite.

Your design stops working after the hardware evaluation time expires and the signal goes high.

f For more information on OpenCore Plus hardware evaluation, refer to “OpenCore

Plus Evaluation” on page 1–5 and AN320: OpenCore Plus Evaluation of Megafunctions.

Signals

Tab le 3– 12 lists the receiver clock signals.

Table 3–12. Receiver Clock Signals (Part 1 of 2)

Signal Direction Description

gxb2_cal_clk

gxb4_cal_clk

rx_sd_oversample_clk_in

rx_serial_refclk

rx_serial_refclk1

(1)

Input Calibration clock for Arria GX and Stratix II GX transceivers only.

Input

Input 67.5-MHz oversample clock input. SD-SDI only.

Input

rst

Calibration clock for Arria II GX, Arria V, Cyclone IV GX, HardCopy IV, and Stratix IV transceivers only.

Transceiver training clock for HD-SDI, dual standard and triple standard.

Secondary transceiver training clock. Clock frequency of

74.175 MHz for HD-SDI, or clock frequency of 148.35 MHz for 3G-SDI, dual standard and triple standard. Available only when you use a Cyclone IV GX device.

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Signals

Table 3–12. Receiver Clock Signals (Part 2 of 2)

Signal Direction Description

Receiver controller clock input. For Cyclone IV GX devices only. The

rx_coreclk

Input

frequency of this clock must be the same as

rx_serial_refclk

Because of hardware constraint, the transceiver PLL and core logic

cannot share the same clock input pin if they use transceiver PLL6 and PLL7.

refclk_rate

This signal is related to the

(2)

Input

received video standard. Set input to 0 for a 148.35-MHz receiver serial reference clock. Set input to 1 for 148.5-MHz RX serial

rx_video_format

signal. Detects the

reference clock.

Transmitter clock out of transceiver. This clock is the output of the

gxb_tx_clkout

Output

voltage-controlled oscillator (VCO) and is used as a parallel clock for the transmitter. It connects internally to the

tx_clkout

signal of the

ALTGX or ALT2GXB megafunction.

rx_clk

rx_sd_oversample_clk_out

rx_video_format

Output Transceiver CDR clock.

Output

67.5-MHz oversample clock output for cascading MegaCore functions. SD-SDI only.

This signal is related to the format for the received video. The

Output

after the frame locked signal is asserted.

refclk_rate

rx_video_format

signal. Indicates the

value is valid

For more information about the video specification, refer to

Table 3–17.

Notes to Table 3–12:

(1) You must tie the

devices.

(2) For Cyclone IV GX devices, set the

tx_serial_refclk

refclk_rate

and

rx_serial_refclk

according to the

signals together if you generate an SDI duplex using the Stratix V or Arria V

rx_coreclk

frequency.

Tab le 3– 13 lists the transmitter clock signals.

Table 3–13. Transmitter Clock Signals

Signal Direction Description

tx_pclk

tx_serial_refclk

(1)

tx_serial_refclk1

Note to Table 3–13:

(1) You must tie the

devices.

tx_serial_refclk

and

Input

Transmitter parallel clock input. For SD-SDI = 27 MHz; for HD-SDI = 74 MHz and for 3G-SDI = 148.5 MHz.

Input Transceiver reference clock input. Low jitter. Refer to Table 3–5.

Optional port for transceiver reference clock input. Low jitter. Similar

Input

tx_serial_refclk

. Only available for Arria II, Stratix IV GX, and

HardCopy IV GX devices.

rx_serial_refclk

signals together if you generate an SDI duplex using Arria V or Stratix V

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Signals

Tab le 3– 14 lists the transceiver PHY management clock and reset signals.

Table 3–14. Transceiver PHY Management Signals

(1)

Signal Direction Description

Avalon-MM clock input for the transceiver PHY management

phy_mgmt_clk

Input

interface. Use the same clock for the PHY management interface and transceiver reconfiguration. The frequency range is 100-125 MHz to meet the specification of the transceiver reconfiguration clock.

Reset signal for the transceiver PHY management interface. This signal is active high and level sensitive. This signal can be tied to the

tx_rst

rx_rst

phy_mgmt_clk_reset

Input

same reset port as

In duplex mode, this reset signal acts as a global reset for both the transmitter and receiver. If you require a different reset for the transmitter and receiver, separate this signal from the

rx_rst

signal.

Note to Table 3–14:

(1) The transceiver PHY management clock and reset signals are available for Stratix V and Arria V devices only.

Tab le 3– 15 lists the soft transceiver clock signals.

Table 3–15. Soft Transceiver Clock Signals

Signal Direction Description

rx_sd_refclk_337

rx_sd_refclk_337_90deg

rx_sd_refclk_135

tx_sd_refclk_270

Input Soft transceiver 337.5-MHz sampling clock.

Input Soft transceiver 337.5-MHz sampling clock with 90° phase shift.

Input Soft transceiver 135-MHz parallel clock for receiver.

Input Soft transceiver 270-MHz parallel clock for transmitter.

signal in simplex mode.

tx_rst

and

Tab le 3– 16 lists the interface signals.

Table 3–16. Interface Signals (Part 1 of 5)

Signal Width Direction Description

enable_crc

[(N – 1):0] Input Enables CRC insertion for HD-SDI and 3G-SDI.

enable_hd_search

enable_sd_search

enable_3g_search

enable_ln

[(N – 1):0] Input

en_sync_switch

rst_rx

1 Input

Enables search for HD-SDI signal in dual or triple standard mode.

Enables search for SD-SDI signal in dual or triple standard mode.

1 Input Enables search for 3G-SDI signal in triple standard mode.

Enables line number insertion for HD-SDI and 3G-SDI modes.

1 Input

Enables aligner and format blocks to realign immediately so that the downstream is completely non-disruptive.

Reset signal, which holds the receiver in reset. It must be synchronous to

rx_serial_refclk

clock domain for the

receiver. Issues a reset to the SDI MegaCore function after

1 Input

power-up to ensure reliable operation. Refer to

Figure 3–29.

For HD-SDI dual link receiver, assert this signal when both link A and link B are ready for the first time.

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Signals

Table 3–16. Interface Signals (Part 2 of 5)

Signal Width Direction Description

Reset signal, which holds the transmitter in reset. The reset synchronization for the transmitter is handled within

tx_std

) and

rst_tx

1 Input

the SDI MegaCore function. The video mode ( clocks must be set up and stable before device bring-up or core reset. Issues a reset to the SDI MegaCore function after power-up to ensure reliable operation. Refer to

Figure 3–30.

Reference clock switching. Available only when you use a

rx_serial_refclk_clkswitch

rx_protocol_clk

1 Input

[(N – 1):0] Input External clock for protocol data.

Cyclone IV GX device.

Toggle between

rx_serial_refclk

rx_serial_refclk1

and

at every positive edge triggered.

Selection of HD-SDI or SD-SDI processing for dual or triple standard protocol block. This signal only appears on dual or triple standard protocol blocks and indicates

rx_protocol_hd_sdn

[(N – 1):0] Input

3G-SDI(1), HD-SDI(1) or SD-SDI(0) data on the

rx_protocol_in

rx_std_flag_hd_sdn

the

signal. You must connect this signal to

output of the transceiver block

in a split protocol/transceiver design.

rx_protocol_in

[(20N – 1):0] Input External data in for protocol only mode.

Input to transceiver control logic. When active, this signal

rx_protocol_locked

[(N – 1):0] Input

indicates to the transceiver control logic that the protocol blocks are locked, to stop the transceiver search algorithm at the current rate.

Reset for the protocol block. This signal resets the

rx_protocol_rst

[(N – 1):0] Input

protocol blocks. You can connect this signal to the

rx_status[1]

pin (

sdi_reset

) in a split

transceiver/protocol design.

rx_protocol_valid

[(N – 1):0] Input External data valid in for protocol only mode.

Input to the protocol block. This signal indicates the received video standard to the protocol block. However, this signal does not distinguish between 3G-SDI Level A

rx_protocol_rate

[1:0] Input

and 3G-SDI Level B streams. The aligner block in the protocol block distinguishes the 3G-SDI Level A and 3G-SDI Level B streams. You must connect this signal to

rx_std

the

port of the transceiver block in a split

transceiver/protocol design.

Input to transceiver control logic. You must connect this

rx_xcvr_trs_lock

[(N – 1):0] Input

signal to the

rx_status[3]

pin (

trs_locked

) of the

protocol only receiver block.

sdi_rx

[(N – 1):0] Input Serial input.

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Signals

Table 3–16. Interface Signals (Part 3 of 5)

Signal Width Direction Description

User-supplied transmitter parallel data. SD-SDI uses 9:0; HD-SDI uses 20N – 1:0.

SD: bits 19:10 unused; bits 9:0 Cb, Y, Cr, Y multiplex

HD: bits 19:10 Y; bits 9:0 C

txdata

[(20N – 1):0] Input

Dual link: bits 39:30 Y link B; bits 29:20 C link B; bits 19:10 Y link A, bits 9:0 C link A

3G-SDI Level A: bits 19:10 Y; bits 9:0 C

3G-SDI Level B: bits 19:10 Cb, Y, Cr, Y multiplex (link A); bits 9:0 Cb, Y, Cr, Y multiplex (link B)

Transmitter line number. For use in HD-SDI and 3G-SDI line number insertion.

HD-SDI: bits 21:11 11’d0; bits 10:0 LN

tx_ln

[21:0] Input

Dual link: bits 21:11 LN link B; bits 10:0 LN link A

3G-SDI Level A: bits 21:11 11’d0; bits 10:0 LN

3G-SDI Level B: bits 21:11 LN link A; bits 10:0 LN link B

Refer to Figure 3–31 and Figure 3–32.

Transmitter TRS input. For use in HD-SDI LN and CRC

tx_trs

[(N – 1):0] Input

insertion. Assert on first word of both EAV and SAV TRSs. Refer to Figure 3–31 and Figure 3–32.

Transmitter standard. 00 for SD-SDI; 01 for HD-SDI; 11 for

tx_std

[1:0] Input

3G-SDI Level A, and 10 for 3G-SDI Level B. This signal must be set up and stable prior to device bring-up or core reset. Refer to Figure 3–31 and Figure 3–32.

TRS locking signal for protocol only receiver mode. You

trs_loose_lock

[(N – 1):0] Output

can connect this signal to the

rx_protocol_locked

of the transceiver only receiver block.

CRC error on luma channel.

crc_error_y

[1:0] Output

HD-SDI: bit 1 unused; bit 0

Dual link: bit 1 link B

crc_error_y

3G-SDI Level A: bit 1 unused; bit 0

3G-SDI Level B: bit 1 link A bit 0 link B

crc_error_y

; bit 0 link A

crc_error_y

;

Refer to Figure 3–33.

CRC error on chroma channel.

crc_error_c

[1:0] Output

HD-SDI: bit 1 unused; bit 0

Dual link: bit 1 link B

crc_error_c

3G-SDI Level A: bit 1 unused; bit 0

3G-SDI Level B: bit 1 link A bit 0 link B

crc_error_c

; bit 0 link A

crc_error_c

;

Refer to Figure 3–33.

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Signals

Table 3–16. Interface Signals (Part 4 of 5)

Signal Width Direction Description

This is an active picture interval timing signal. The receiver aserts this signal when the active picture interval is active.

rx_ap

; bit 0 link B

rx_ap

rx_AP

[1:0] Output

HD-SDI/SD-SDI: bit 1 unused; bit 0

Dual link: bit 1 link B unused; bit 0 link A

3G-SDI Level A: bit 1 unused; bit 0

3G-SDI Level B: bit 1 link A

Receiver parallel data. SD-SDI uses 9:0; HD-SDI uses 20N – 1:0.

SD-SDI bits 19:10 unused; bits 9:0 Cb, Y, Cr, Y multiplex

HD-SDI bits 19:10 Y; bits 9:0 C

rxdata

[(20N – 1):0] Output

Dual link: bits 39:30 Y link B; bits 29:20 C link B; bits 19:10 Y link A, bits 9:0 C link A

3G-SDI Level A: bits 19:10 Y; bits 9:0 C

3G-SDI Level B: bits 19:10 Cb, Y, Cr, Y multiplex (link A); bits 9:0 Cb, Y, Cr, Y multiplex (link B)

Data valid from the oversampling logic. Asserted to indicate current data on

Bit 0 of this bus indicates valid data on

rxdata

is valid.

rxdata

. When

receiving SMPTE 425M-B signals in 3G-SDI or triple

rx_data_valid_out

[1:0] Output

standard, bit 1 indicates that data on

rxdata

is from

virtual link A; bit 0 indicates the data is from virtual link B.

Refer to Figure 3–34 and Figure 3–35, and SMPTE425M-B

2006 3Gb/s Signal/Data Serial Interface – Source Image Format Mapping.

This is a field bit timing signal. This signal indicates which video field is currently active. For interlaced frame, 0 means first field (F0) while 1 means second field (F1). For progressive frame, the value is always 0.

rx_F

[1:0] Output

HD-SDI/SD: bit 1 unused; bit 0

Dual link: bit 1 unused; bit 0

rx_f

3G-SDI Level A: bit 1:0 unused

3G-SDI Level B: bit 1:0 unused

This is a horizontal blanking interval timing signal. The receiver asserts this signal when the horizontal blanking interval is active.

rx_h

; bit 0 link B

rx_h

rx_H

[1:0] Output

HD-SDI/SD-SDI: bit 1 unused; bit 0

Dual link: bit 1 unused; bit 0

3G-SDI Level A: bit 1 unused; bit 0

3G-SDI Level B: bit 1 link A

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Signals

Table 3–16. Interface Signals (Part 5 of 5)

Signal Width Direction Description

Receiver line number output.

HD-SDI: bits 21:11 unused; bits 10:0 LN

rx_ln

[21:0] Output

Dual link: bits 21:11 unused; bits 10:0 LN

3G-SDI Level A: bits 21:11 unused; bits 10:0 LN

3G-SDI Level B: bits 21:11 LN link A; bits 10:0 LN link B

rx_std_flag_hd_sdn

1 Output

Indicates received standard for dual or triple standard only. HD-SDI = 1; SD-SDI = 0.

This is a vertical blanking interval timing signal. The receiver asserts this signal when the vertical blanking interval is active.

rx_v

; bit 0 link B

rx_v

rx_V

rx_xyz

xyz_valid

rx_eav

rx_trs

sdi_tx

tx_protocol_out

[1:0] Output

HD-SDI/SD-SDI: bit 1 unused; bit 0

Dual link: bit 1 unused; bit 0

3G-SDI Level A: bit 1 unused; bit 0

3G-SDI Level B: bit 1 link A

1 Output Receiver output that indicates current word is XYZ word.

1 Output

Receiver output that indicates current TRS format is legal (XYZ word is correct).

1 Output Receiver output that indicates current TRS is EAV.

1 Output

Receiver output that indicates current word is TRS. This signal is asserted at the first word of 3FF 000 000 TRS.

[(N – 1):0] Output Serial output.

[(20N – 1):0] Output Data out (protocol only mode).

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Figure 3–26 through Figure 3–28 illustrate the input and output signals in Tab le 3 –1 6

for SDI triple standard instances.

Figure 3–26. Interface Signals for SDI Triple Standard Receiver

SDI Triple Standard Receiver Instance

rx_clk

rst_rx

rx_serial_refclk

refclk_rate

sdi_rx[0:0]

en_sync_switch

enable_hd_search

enable_sd_search

enable_3g_search

sdi_reconfig_clk

gxb2_cal_clk/gxb4_cal_clk

sdi_reconfig_togxb[3:0]

sdi_reconfig_done

sdi_gxb_powerdown

rx_std_flag_hd_sdn[0:0]

sdi_reconfig_fromgxb[16:0]

rxdata[19:0]

rx_data_valid_out[1:0]

rx_status[10:0]

rx_std[1:0]

rx_trs

rx_eav

rx_xyz

xyz_valid

rx_anc_data[19:0]

rx_anc_valid[3:0]

rx_anc_error[3:0]

rx_video_format[7:0]

sdi_start_reconfig

Figure 3–27. Interface Signals for SDI Triple Standard Transmitter

SDI Triple Standard Transmitter Instance

rst_tx

tx_pclk

tx_serial_refclk

tx_serial_refclk1 (optional)

txdata[19:0]

tx_std[1:0]

tx_trs[0:0]

tx_ln[21:0]

enable_ln[0:0]

enable_crc[0:0]

gxb2_cal_clk/gxb4_cal_clk

sdi_reconfig_clk

sdi_reconfig_togxb[3:0]

sdi_gxb_powerdown

sdi_reconfig_fromgxb[16:0]

sdi_tx[0:0]

tx_status[0:0]

gxb_tx_clkout[0:0]

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Chapter 3: Functional Description 3–47

tx_trs

txdata[19:10]

txdata[9:0]

tx_std[1:0]

tx_ln[21:11]

tx_pclk

3FF(Y) 000(Y) 000(Y) XYZ(Y)

3FF(C11) 000(C) 000(C XYZ(C)

11’d0

tx_ln[10:0]

11’d1 11’d2

000(Y) 000(Y) XYZ(Y)

000(C) 000(C XYZ(C)

3FF(Y)

3FF(C)

000(Y) 000(Y) XYZ(Y)

000(C) 000(C XYZ(C)

3FF(Y)

3FF(C)

EAV SAV

EAV

Signals

Figure 3–28. Interface Signals for SDI Triple Standard Duplex Instance

SDI Triple Standard Duplex Instance

rst_rx

rst_tx

rx_serial_refclk

refclk_rate

tx_serial_refclk

tx_serial_reflclk1 (optional)

tx_pclk

sdi_rx[0:0]

en_sync_switch

enable_hd_search

enable_sd_search

enable_3g_search

txdata[19:0]

tx_std[1:0]

tx_trs[0:0]

tx_ln[21:0]

enable_ln[0:0]

enable_crc[0:0]

gxb2_cal_clk/gxb4_cal_clk

sdi_reconfig_clk

sdi_reconfig_togxb[3:0]

sdi_reconfig_done

sdi_gxb_powerdown

rx_data_valid_out[1:0]

rx_std_flag_hd_sdn[0:0]

rx_anc_data[19:0]

rx_video_format[7:0]

gxb_tx_clkout[0:0]

sdi_reconfig_fromgxb[16:0]

sdi_start_reconfig

rx_clk

rxdata[19:0]

rx_status[10:0]

rx_std[1:0]

rx_trs

rx_eav

rx_xyz

xyz_valid

rx_anc_valid[3:0]

rx_anc_error[3:0]

sdi_tx[0:0]

tx_status[0:0]

Figure 3–29 through Figure 3–37 show the behavior of some signals in Tab le 3 –1 6.

Figure 3–29. Power-up Reset for the Receiver

rst_rx

rx_serial_refclk (74.25MHz)

Figure 3–30. Power-up Reset for the Transmitter

rst_tx

tx_pclk(74.25MHz)

tx_std[1:0]

rst_tx_sync (1)

Note to Figure 3–30:

(1) Internally synchronized reset for the transmit circuits.

Figure 3–31. Behavior of tx_std, tx_trs, and tx_ln Signals—425MA

0100

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tx_pclk

EAV

SAV

EAV

tx_trs

txdata[19:10]

txdata[9:0]

3FF(C) 3FF(Y) 000(C) 000(Y) 000(C) 000(Y) XYZ(C) XYZ(Y)

3FF(C) 3FF(Y) 000(C)10000(Y) 000(C) 000(Y) XYZ(C) XYZ(Y)

tx_std[1:0]

tx_ln[21:11]

tx_ln[10:0]

3FF(C) 3FF(Y) 000(C) 000(Y) 000(C) 000(Y) XYZ(C) XYZ(Y)

11’d2

11’d3

11’d4

11’d1

rx_clk (148.5 MHz)

rxdata[19:10]

rxdata[9:0]

rx_data_valid_out[0]

rx_data_valid_out[1]

3FF(Y) 000(Y) 000(Y) XYZ(Y)000(Y)

3FF(C) 000(C) 000(C) XYZ(C)000(C)

Signals

Figure 3–32. Behavior of tx_std, tx_trs, and tx_ln Signals—425MB

Figure 3–33. Behavior of crc_error_y and crc_error_c Signals

(1)

rx_clk

rxdata[19:0]

rxdata[9:0]

3FF XYZ CRC1

000

3FF

000

LN2

LN1

XYZ CRC1 CRC2

LN1

CRC2

LN2

000

rx_V

rx_H

rx_ln

000001a

crc_error_y

crc_error_c

(2) (3)

Notes to Figure 3–33:

(1) When a CRC error occurs, the

crc_error_y[0]

and

crc_error_y[1]

and

(2) The CRC error signals are asserted after the CRC data checked, when the

crc_error_y

crc_error_c[0]

and

crc_error_c[1]

crc_error_c

signal goes high until the next line. For HD, Dual Link, and 3G Level A, only

signals are used. For 3G Level B,

signals are used for link A.

rx_H

crc_error_y[0]

signal is high. A high CRC signal indicates that there is error in the

previous line data. In this case, both Y and C have CRC error.

(3) The CRC error signals are deasserted on the next line after the CRC data is checked.

Figure 3–34. Behavior of rx_data_valid Signal—425MA

LN2

000 000

3FF XYZ CRC1 CRC2

3FF

000

and

LN1

000

XYZ CRC1 CRC2

LN2

LN1

crc_error_c[0]

000001b

signals are used for link B,

Figure 3–35. Behavior of rx_data_valid Signal—425MB

rx_clk (148.5 MHz)

rxdata[19:10]

rxdata[9:0]

rx_data_valid_out[0]

rx_data_valid_out[1]

Serial Digital Interface (SDI) MegaCore Function February 2013 Altera Corporation User Guide

3FF(C) 3FF(Y) 000(C) 000(Y) 000(C) 000(Y) XYZ(C)000(Y)

Chapter 3: Functional Description 3–49

rxdata[19:10]

rx_clk (148.5 MHz)

rxdata[9:0]

rx_trs

rx_xyz

xyz_valid

rx_eav

3FF

000 0001C4 3FF

380

3FF

000 0001C4 3FF

380

Signals

Figure 3–36. Behavior of rx_trs, rx_xyz, xyz_valid and rx_eav Signals—425MA

Figure 3–37. Behavior of rx_trs, rx_xyz, xyz_valid and rx_eav Signals—425MB

rx_clk (148.5 MHz)

rxdata[19:10]

rxdata[9:0]

rx_trs

rx_xyz

xyz_valid

rx_eav

3FF 000 0001C4

3FF

380

Tab le 3– 17 lists the 8-bit receiving video format specification.

Table 3–17. Receiving Video Format Specification (Part 1 of 2)

Video

Standard

Total Active

Lines

Word per

Total Line

Rate

rx_video_format

[7:5]

rx_video_format

[4]

Progressive/

rx_video_format

Interlace

720p60

720p59.94 59.94 6

—— 0 0 8

1650

720p50 1980 50 5

720p30

720p29.97 29.97 3

720

3300

30 4

720p25 3960 25 2

720p24

720p23.97 23.97 0

1035i30

1035i29.97 29.97 3 0 3

1035 2200

1080i25

1080i60

1080i59.94 59.94 6

1080i50 2640 50 5

1080

1080i24

1080i23.97 23.97 0

4125

2376 25 4

2200

2750

24 1

30 3 0 4

24 1

[3:0]

Frame Rate

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Signals

Table 3–17. Receiving Video Format Specification (Part 2 of 2)

Video

Standard

Total Active

Lines

Word per

Total Line

Rate

rx_video_format

[7:5]

rx_video_format

[4]

Progressive/

rx_video_format

Interlace

1080p60

1080p59.94 59.94 6

1080

2200

1080p50 2640 50 5

1080p30

1080p29.97 29.97 3

1080p25 2640 25 2

1080

1080p24

1080p23.97 23.97 0

2200

2750

24 1

Tab le 3– 18 lists the status signals.

Table 3–18. Status Signals (Part 1 of 2)

Signal Width Direction Description

Received ancillary data.

SD-SDI: bits 19:10 unused; bits 9:0 Cb, Y, Cr, Y multiplex

HD-SDI: bits 19:10 Y; bits 9:0 C

rx_anc_data

[(20N – 1):0] Output

Dual link: bits 39:30 Y (link B); bits 29:20 C (link B); bits 19:10 Y (link A); bits 9:0 C (link A)

3G-SDI Level A: bits 19:10 Y; bits 9:0 C

3G-SDI Level B: bits 19:10 Cb, Y, Cr, Y multiplex (link A); bits 9:0 Cb, Y, Cr, Y multiplex (link B)

Ancillary data or checksum error.

SD-SDI: bits 3:1 unused; bit 0

rx_anc_error

HD-SDI: bits 3:2 unused; bit 1 Y; bit 0 C

rx_anc_error

[3:0] Output

Dual link: bit 3 Y (link B); bit 2 C (link B); bit 1 Y (link A); bit 0 C (link A)

3G-SDI Level A: bits 3:2 unused; bit 1 Y; bit 0 C

3G-SDI Level B: bit 3 Y (link A); bit 2 C (link A); bit 1 Y (link B); bit 0 C (link B)

Ancillary data valid. Asserted to accompany data ID (DID), secondary data ID/data block number (SDID/DBN), data

rx_anc_valid

[3:0] Output

count (DC), and user data words (UDW) on

SD-SDI: bits 3:1 unused; bit 0

rx_anc_valid

HD-SDI: bits 3:2 unused; bit 1 Y; bit 0 C

Dual link: bit 3 Y (link B); bit 2 C (link B); bit 1 Y (link A);

rx_anc_data

bit 0 C (link A)

3G-SDI Level A: bits 3:2 unused; bit 1 Y; bit 0 C

3G-SDI Level B: bit 3 Y (link A); bit 2 C (link A); bit 1 Y (link B); bit 0 C (link B)

[3:0]

Frame Rate

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Signals

Table 3–18. Status Signals (Part 2 of 2)

Signal Width Direction Description

Receiver status:

■

rx_status[10]

■

rx_status[9]

■

rx_status[8]

dual link ports aligned

link B frame locked

link B TRS locked (six consecutive TRSs

with same timing)

■

rx_status[7]

link B alignment locked (a TRS has been

spotted and word alignment performed)

■

rx_status[6]

■

rx_status[5]

■

rx_status[4]

■

rx_status[3]

link B receiver in reset

link B transceiver PLL locked

link A Frame locked

link A TRS locked (six consecutive TRSs

with same timing)

■

rx_status[2]

link A alignment locked (a TRS has been

spotted and word alignment performed)

rx_status

[10:0] Output

■

rx_status[1]

■

rx_status[0]

link A receiver in reset

link A transceiver PLL locked

For non HD-SDI dual link versions, only bits

[4:0]

are

active.

For transceiver only receiver block in HD-SDI dual link

[6:5]

and

[1:0]

versions, only bits

are active.

This signal is active high for Stratix GX devices and active low for other Altera transceiver-based device families. This signal indicates lock of the PLL when the transceiver is

refclk

training from a

source. This signal may oscillate when the transceiver is correctly locked to the incoming data in HD-SDI or 3G-SDI modes. In SD-SDI modes, remain this signal at PLL locked at all times.

rx_status[3]

For

and

rx_status[8]

, the TRS spacing is not required to meet a particular SMPTE standard, but it must be consistent over time for this signal to remain active.

Transmitter status, which indicates the transmitter PLL has

tx_status

[(N – 1):0] Output

locked to the active high for Stratix GX devices and active low for other

tx_serial_refclk

signal. This signal is

Altera transceiver-based device families.

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rx_anc_data[19:10]

000 3FF 179 000 20F 055 1FC

000 3FF 179 20F 055 1FC

rx_clk (148.5 Hz)

rx_anc_data[9:10]

rx_anc_valid[3]

rx_anc_valid[2]

rx_anc_valid[1]

rx_anc_valid[0]

rx_anc_error[3]

rx_anc_error[2]

rx_anc_error[1]

rx_anc_error[0]

(1)(2)

(3)

(4) (5)

rx_anc_data[19:10]

rx_clk (148.5 MHz)

rx_anc_data[9:10]

rx_anc_valid[3]

rx_anc_valid[2]

rx_anc_valid[1]

rx_anc_valid[0]

rx_anc_error[3]

rx_anc_error[2]

rx_anc_error[1]

rx_anc_error[0]

(1) (4)(2) (3) (6) (7)(5)

000

3FF 179 20F 055 1FC

000 000

3FF 179 20F 055 1FC

Signals

Figure 3–38 and Figure 3–42 show the behavior of the

rx_anc_data

signal in

Table 3–18 on page 3–50.

Figure 3–38. Behavior of rx_anc_data/valid/error Signals—425MA

Notes to Figure 3–38:

(1) Sequence starts with Data Indentifier (DID), followed by Secondary Data Indentifier (SDID) or Data Block Number

(DBN). (2) The Y channel goes wrong. (3) Data Count (DC). (4) User data word (UDW) up to 255 words. (5) Checksum word.

Figure 3–39. Behavior of rx_anc_data/valid/error Signals—425MB

Notes to Figure 3–39:

(1) 000 (C), 000 (Y) (2) 3FF (C), 3FF (Y), 3FF (C), 3FF (Y) (3) Sequence starts with Data Indentifier (DID), followed by Secondary Data Indentifier (SDID) or Data Block Number

(DBN). (4) The Y channel of Link B goes wrong. (5) Data Count (DC) word.

Serial Digital Interface (SDI) MegaCore Function February 2013 Altera Corporation User Guide

(6) User data word (UDW) up to 255. (7) Checksum word.

Chapter 3: Functional Description 3–53

rx_anc_data[19:10]

000 3FF 179 000 20F 055 1FC

000 3FF 179 20F 055 1FC

rx_clk (148.5 Hz)

rx_anc_data[9:10]

rx_anc_valid[3]

rx_anc_valid[2]

rx_anc_valid[1]

rx_anc_valid[0]

rx_anc_error[3]

rx_anc_error[2]

rx_anc_error[1]

rx_anc_error[0]

(1)(2)

(3)

(4) (5)

Signals

Figure 3–40. Behavior of rx_anc_data/valid/error Signals—HD

Notes to Figure 3–40:

(1) Sequence starts with Data Indentifier (DID), followed by Secondary Data Indentifier (SDID) or Data Block Number

(DBN). (2) The Y channel goes wrong. (3) Data Count (DC) word. (4) User data word (UDW) up to 255 words. (5) Checksum word.

Figure 3–41. Behavior of rx_anc_data/valid/error Signals Without Error —SD

rx_clk (67.5 MHz)

rx_anc_data[9:0]

rx_anc_valid[0]

rx_anc_error[0]

000 3FF 3FF

179 000

20F

055

Figure 3–42. Behavior of rx_anc_data/valid/error Signals With Error—SD

rx_clk (67.5 MHz)

rx_anc_data[9:0]

rx_anc_valid[0]

rx_anc_error[0]

000 3FF 3FF

179 000

20F

055

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Signals

Tab le 3– 19 lists the signals that handle the transceiver dynamic reconfiguration

operation.

Table 3–19. Transceiver Dynamic Reconfiguration Signals (Part 1 of 2)

Signal Direction Description

SDI_RECONFIG_DONE

Input

Indicates back to MegaCore function that reconfiguration has finished. This signal is not required for PLL reconfiguration.

Data input for the embedded transceiver instance.

(2), (5)

Data width:

■ For all devices except Arria V, Cyclone V, and Stratix V =

SDI_RECONFIG_TOGXB

(1), (3), (4)

Input

SDI_RECONFIG_TOGXB[3:0]

■

SDI_RECONFIG_TOGXB[3]

is negligible for Arria GX and

Stratix II GX.

■ For Arria V, Cyclone V, and Stratix V devices =

SDI_RECONFIG_TOGXB[(140N-1)]:0] SDI_RECONFIG_TOGXB[(70N-1)]:0]

—if the receiver in the

interface settings is selected.

(2)

SDI_RECONFIG_CLK

(3)

Input

Clock input for the embedded transceiver instance.

This signal is not applicable for Arria V, Cyclone V, and Stratix V devices.

(6)

SDI_GXB_POWERDOWN

Input

Powers down and resets circuits in all transceiver instance.

This signal is not applicable for Arria V, Cyclone V, and Stratix V devices.

SDI_START_RECONFIG

Output Request from MegaCore function to start reconfiguration.

Data output from embedded transceiver instance.

(2), (5)

Data width:

■ For all devices except Arria V, Cyclone V, and Stratix V =

SDI_RECONFIG_FROMGXB[(17N-1):0]

■

SDI_RECONFIG_FROMGXB

(1), (3), (4)

Output

SDI_RECONFIG_FROMGXB[16:1]

and Stratix II GX

■

SDI_RECONFIG_FROMGXB[16:5]

are negligible for Arria GX

are negligible for

Cyclone IV GX

■ For Arria V, Cyclone V, and Stratix V devices =

SDI_RECONFIG_FROMGXB[(92N-1):0] SDI_RECONFIG_FROMGXB[(46N-1):0]

or if the receiver in the

interface settings is selected.

Receive video standard. 00 = SD-SDI, 01 = HD-SDI, 10 = 3G-SDI.

The SDI MegaCore function can recover both SMPTE 425M-A and

RX_STD[1:0]

PLL_ARESET

(7), (8), (9)

PLL_CONFIGUPDATE

(7), (8), (9)

Output

Input

425M-B formatted streams. The receiver indicates which format it detects by setting the level of the

■

rx_std[1:0]

■

rx_std[1:0]

Drives the

= 2’b11 = 425M-A

= 2’b10 = 425M-B

areset

signal on the transceiver PLL to be

rx_std

bus:

reconfigured. This signal indicates that the transceiver PLL must be reset.

Drives the

configupdate

signal on the transceiver PLL to be

reconfigured.

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Chapter 3: Functional Description 3–55

Signals

Table 3–19. Transceiver Dynamic Reconfiguration Signals (Part 2 of 2)

Signal Direction Description

PLL_SCANCLK

(7), (8), (9)

Input

Drives the reconfigured.

scanclk

signal on the transceiver PLL to be

PLL_SCANCLKENA

(7), (8), (9)

PLL_SCANDATA

(7), (8), (9)

PLL_SCANDONE

(7), (8), (9)

PLL_SCANDATAOUT

(7), (8), (9)

Notes to Table 3–19:

(1) These signals must be connected directly to a reconfiguration megafunction. (2) The transceivers are available for Arria GX, Arria II GX, Arria V, Cyclone IV GX, Cyclone V, Hardcopy IV GX, Stratix II GX, Stratix IV, and Stratix V

devices only.

(3) SDI transmitters do not require the use of transceiver dynamic reconfiguration but to enable the cores to merge into a transceiver quad that has

transceiver dynamic reconfiguration enabled, you must connect these ports correctly.

(4) In the Quartus II software version 8.1 and later, the Stratix IV transceivers requires receiver buffer calibration through an

(transceiver dynamic reconfiguration) controller. The additional RECONFIG port bits are used for receiver buffer calibration. You must connect these ports to the

Dynamic Reconfiguration chapter in volume 2 of the Stratix IV Device Handbook. If you are using the Quartus II software version 10.1, make

sure to upgrade the SDI MegaCore function to version 10.1 as well.

(5) N represents the number of channels instantiated.

SDI_GXB_POWERDOWN

(6) The

(same input or same logic). Any difference in the driving logic prevents the instances from being combined in a single transceiver block.

(7) This signal must be connected directly to the ALTPLL_RECONFIG megafunction, and only exposed to the top level when you select the Use PLL

reconfiguration for transceiver dynamic reconfiguration option in the SDI parameter editor.

(8) The transceivers are available for Cyclone IV GX devices only. (9) You require

ALTGX_RECONFIG

rx_std

and

controller externally. For further information on the receiver buffer calibration, refer to the Stratix IV

signal of all the instances that are to be combined in a single transceiver block must be connected to a single point

sdi_start_reconfig

Input

Output Determines when the transceiver PLL is reconfigured.

Output

signals for PLL reconfiguration.

Acts as a clock enable for the

scanclk

signal on the transceiver

PLL to be reconfigured.

Drives the

scandata

signal on the transceiver PLL to be reconfigured. This signal holds the scan data input to the transceiver PLL for the dynamically reconfigurable bits.

This signal holds the transceiver PLL scan data output from the dynamically reconfigurable bits.

ALTGX_RECONFIG

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Parameters

The parameters can only be set in the MegaWizard Plug-In Manager (refer to

“Parameterizing” on page 2–5).

Tab le 3– 20 lists the protocol options.

Table 3–20. Protocol Options

Parameter Value Description

Selection of HD-SDI or SD-SDI.

Selecting HD-SDI switches in LN insertion and extraction and CRC generation and extraction blocks; selecting SD-SDI switches out LN insertion and extraction and CRC generation and extraction blocks.

Selecting SD-SDI also includes oversampling logic.

Selecting dual or triple standard SDI includes the processing blocks for both SD-SDI and HD-SDI standards. In addition, logic for bypass paths and logic to automatically switch between the input standards is included.

Selects the ports to be receiver, transmitter, or bidirectional. It switches in or out the receiver and transmitter supporting logic appropriately.

The same setting is applied to all channels in the variation.

If you want some to be transmitter and some to be duplex, simply create two different MegaCore variations.

Video standard

Interface settings

SD-SDI, HD-SDI, 3G-SDI,

HD-SDI dual link, dual or

triple standard SDI

Bidirectional, receiver,

transmitter

Tab le 3– 21 lists the transceiver options.

Table 3–21. Transceiver Options

Parameter Value Description

Transceiver and protocol

Use soft logic for transceiver

Starting channel number

Generate transceiver and protocol blocks, generate transceiver block only, or

generate protocol block only

On or off

0, 4, 8, ..., 156

Selects transceiver or protocol blocks or both. When non-GX device is chosen, only SD-SDI protocol block is permitted. If you want to generate HD-SDI or 3G-SDI protocol block, you must select a GX device.

Uses soft logic to implement the transceiver logic, rather than using Stratix II GX, Stratix IV or Stratix GX transceivers. SD-SDI only.

For example, if you run out of hard transceivers in your device, you can implement the function in soft logic. If you have spare transceivers in a device, you may wish to use them.

Dual or triple standard only. Each dual or triple standard SDI must have a unique starting channel number. This parameter is not applicable for Stratix V, Arria V, and Cyclone V devices.

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MegaCore Verification

Table 3–21. Transceiver Options

Parameter Value Description

Use PLL reconfiguration for transceiver dynamic

On or off

Dual or triple standard, and Cyclone IV GX devices only. You must turn on this option if you select an EP4CGX110 or EP4CGX150 device.

reconfiguration

Enable TX PLL select for 1/1.000 and 1/1.001 data rate

On or off

Enables an additional input port for transmitter serial reference clock. Available for Arria II, Stratix IV, and HardCopy IV devices only.

reconfiguration

Tab le 3– 22 shows the receiver/transmitter options.

Table 3–22. Receiver/Transmitter Options

Parameter Value Description

CRC error output On or off Turns on or off CRC monitoring (HD-SDI and 3G-SDI only).

SDI synchronization output On or off Provides synchronization outputs.

Receiver protocol only. Allows you to set the number of consecutive

Tolerance to consecutive missed EAV/SAV

0, 1, 2, ..., 15

missing EAVs to be tolerated in the incoming video. Specify a higher value if you want the receiver core to tolerate more errors.

If you want the receiver core not to tolerate any errors, set this option to

HD-SDI transmitter only. When turned on, runs the transceiver at twice

Two times oversample mode On or off

the rate and has improved jitter performance. Requires 148.5-MHz

tx_serial_refclk

reference clock.

MegaCore Verification

The MegaCore verification involves testing to the following standards:

■ For the SD-SDI to SMPTE259M-1997 10-Bit 4:2:2 Component Serial Digital Interface

■ For the HD-SDI to SMPTE292M-1998 Bit-Serial Digital Interface for High Definition

Television Systems

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MegaCore Verification

Serial Digital Interface (SDI) MegaCore Function February 2013 Altera Corporation User Guide

The SDI Audio IP cores ease the development of video and image processing designs. For some instances, you combine the audio and video into one digital signal, and at other times you process the audio and video signals separately.

You can use the following cores to embed, extract or convert audio:

■ SDI Audio Embed MegaCore Function

■ SDI Audio Extract MegaCore Function

■ Clocked Audio Input MegaCore Function

■ Clocked Audio Output MegaCore Function

You can instantiate the SDI Audio with the SDI MegaCore function, and configure each SDI Audio core at run time using an Avalon-MM slave interface.

SDI Audio Embed MegaCore Function

4. SDI Audio IP Cores

The SDI Audio Embed MegaCore function embeds audio into the SD-, HD-, and 3G-SDI video standards. The format of the embedded audio is in accordance with the SMPTE272M standard for the SD-SDI video standard, or in accordance with the SMPTE299M standard for HD-SDI and provisionally for 3G-SDI video standard. This MegaCore function supports AES audio format for 48-kHz sampling rate.

The SDI Audio Embed MegaCore function embeds up to 16 channels or 8 channel pairs. The input audio can be any of the sample rates permitted by the SMPTE272M-A and SMPTE299M standards; synchronous to the video. If you want to embed audio pairs together in a sample audio group, the audio pairs must be synchronous with each other.

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Avalon-ST Audio to Audio Embed with Avalon Only

FIFO FIFO FIFO FIFO FIFO FIFO FIFO FIFO

Audio

Embedder

SD/HD/3G-SDI SD/HD/3G-SDI

Avalon-MM

Audio Embed or Audio Embed with Avalon

SD/HD Audio Embedder

Packet

Creation

Packet

Distribution

Channel

Status RAM

SDI Audio Embed MegaCore Function

Functional Description

Figure 4–1 shows a block diagram of the SDI Audio Embed MegaCore function.

Figure 4–1. SDI Audio Embed MegaCore Function Block Diagram

The SDI Audio Embed MegaCore function consists of an encrypted audio embedder core and a register interface block that provides support for an Avalon-MM control bus.

The audio embedder accepts the audio in AES format, and stores each channel pair in an input FIFO buffer. As the embedder places the audio sample in the FIFO buffer, it also records and stores the video clock phase information.

When accepting the audio in AES format, the SDI Audio Embed MegaCore function either maintains the channel-status details or replaces the details with the default or the RAM versions.

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Chapter 4: SDI Audio IP Cores 4–3

SDI Audio Embed MegaCore Function

Parameters

Tab le 4– 1 lists the parameters for the SDI Audio Embed MegaCore function.

Table 4–1. SDI Audio Embed MegaCore Function Parameters

Parameter Value Description

Specifies the maximum number of audio groups supported.

Number of supported audio groups

1, 2, 3, 4

Async Audio Interface On or Off

Frequency of fix_clk

0, 24.576, 25, 50, 100,

200

Channel status RAM 0, 1, 2

Frequency sine wave generator On or Off

Include clock On or Off

Include Avalon-ST interface On or Off

Include Avalon-MM control interface

On or Off

Each audio group consists of 4 audio channels (2 channel pairs). You must specify all the four channels to the same sample frequencies.

Turn on to enable the Asynchronous input. In this mode, the audio clock provides higher than 64* sample rate.

Specifies the frequency of the

fix_clk

signal.

Enables storage of the custom channel status data.

Select 1 to generate a single channel status RAM, or 2 to generate separate RAMs for each input audio pair.

Turn on to enable a four-frequency sine wave generator. You can use the four-frequency sine wave generator as a test source for the audio embedder.

Turn on to enable a 48-kHz pulse generator synchronous to the video clock. You can use the 48-kHz pulse generator to request data from a sample rate convertor.

When you turn on the Frequency Sine Wave Generator parameter, the core automatically includes this pulse generator.

Turn on to include the SDI Clocked Audio Output MegaCore.

When you turn on this parameter, the Avalon-ST interface signals in Table 4–14 appear at the top level. Otherwise, the audio input signals in Table 4–4 appear at the top level.

Turn on to include the Avalon-MM control interface.

When you turn on this parameter, the register interface signals in Table 4–7 appear at the top level. Otherwise, the direct control interface signals in Table 4–6 appear at the top level.

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SDI Audio Embed MegaCore Function

Signals

Tab le 4– 2 lists the general input and output signals for the SDI Audio Embed

MegaCore function.

Table 4–2. General Input and Output Signals

Signal Width Direction Description

reset

fix_clk

vid_std_rate

vid_clk48

[0:0] Input This signal resets the system.

This signal provides the frequency reference used when detecting the difference between video standards using 1 and 1/1.001 clock rates. If its frequency is 0, the signal only

[0:0] Input

detects either one of the clock rates.

The core limits the possible frequencies for this signal to

24.576 MHz, 25 MHz, 50 MHz, 100 MHz, and 200 MHz. Set the required frequency using the Frequency of fix_clk parameter.

If you set the Frequency of fix_clk parameter to 0, you must drive this signal high to detect a video frame rate of 1/1.001

[0:0] Input

and low to detect a video frame rate of 1. For other settings of the Frequency of fix_clk parameter, the core automatically detects these frame rates and drives this signal low.

The 48 kHz output clock that is synchronous to the video.

[0:0] Output

This clock signal is only available when you turn on the Frequency Sine Wave Generator or Include Clock parameter.

Tab le 4– 3 lists the video input and output signals for the SDI Audio Embed

MegaCore function.

Table 4–3. Video Input and Output Signals (Part 1 of 2)

Signal Bits Direction Description

vid_clk

vid_std

vid_datavalid

[0:0] Input

[1:0] Input

[0:0] Input Assert this signal when the video data is valid.

The video clock that is typically 27 MHz for SD-SDI,

74.25 MHz or 74.17 MHz for HD-SDI, or 148.5 MHz or 148.35 MHz for 3G-SDI standards. You can use higher clock rates with the

vid_datavalid

signal.

Set this signal to indicate the following formats:

■ [00] for10-bit SD-SDI

■ [01] for 20-bit HD-SDI

■ [10] for 3G-SDI Level B

■ [11] for 3G-SDI Level A

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SDI Audio Embed MegaCore Function

Table 4–3. Video Input and Output Signals (Part 2 of 2)

Signal Bits Direction Description

This signal carries luma and chroma information.

SD-SDI:

■ [19:10] Unused

■ [9:0] Cb,Y, Cr, Y multiplex

vid_data

[19:0] Input

HD-SDI and 3G-SDI Level A:

■ [19:10] Y

■ [9:0] C

3G-SDI Level B:

■ [19:10] Cb,Y, Cr, Y multiplex (link A)

■ [9:0] Cb,Y, Cr, Y multiplex (link B)

vid_out_datavalid

[0:0] Output

The core drives this signal high during valid output video clock cycles.

The core drives this signal high during the first 3FF clock cycle of a video timing reference signal; the

vid_out_trs

[0:0] Output

first two 3FF cycles for 3G-SDI Level B. This signal provides easy connection to the Altera SDI MegaCore function.

vid_out_ln

vid_out_data

[10:0] Output

[19:0] Output The video output signal.

The video line signal that provides for easy connection to the Altera SDI MegaCore function.

Tab le 4– 4 lists the audio input signals for the SDI Audio Embed MegaCore function.

Table 4–4. Audio Input Signals

Signal Width Direction Description

aud_clk

aud_de

aud_ws

aud_data

Note to Table 4–4:

(1) N represents the number of audio groups.

[2N–1:0] Input

Set this clock to 3.072 MHz that is synchronous to the extracted audio. In asynchronous mode, set this to any frequency above 3.072 MHz. Altera recommends that you set this clock to 50 MHz.

For SD-SDI inputs, this mode of operation limits the core to extracting audio that is synchronous to the video. For HD-SDI inputs, this clock must either be generated from the optional 48 Hz output or the audio must be synchronous to the video.

Assert this data enable signal to indicate valid information on the

aud_ws

and

aud_data

signals. In synchronous mode,

the core ignores this signal.

Assert this word select signal to provide framing for deserialization and to indicate left or right sample of channel pair.

Internal AES data signal from the AES input module. Refer to

Figure 4–9.

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SDI Audio Embed MegaCore Function

Tab le 4– 5 lists the Avalon-ST audio signals when you instantiate the SDI Audio

Embed MegaCore function in SOPC Builder.

Table 4–5. Avalon-ST Audio Signals for SDI Audio Embed MegaCore Function

Signal Width Direction Description

aud(n)_clk

aud(n)_ready

aud(n)_valid

[0:0] Input

[0:0] Output

[0:0] Input

Clocked audio clock. All the audio input signals are synchronous to this clock.

Avalon-ST ready signal. Assert this signal when the device is able to receive data.

Avalon-ST valid signal. The MegaCore function asserts this signal when it receives data.

Avalon-ST start of packet signal. The MegaCore

aud(n)_sop

[0:0] Input

function asserts this signal when it is starting a new frame.

aud(n)_eop

aud(n)_channel

aud(n)_data

Note to Table 4–5:

(1) (n) represents the channel number.

[0:0] Input

[7:0] Input

[23:0] Input Avalon-ST data bus. This bus transfers data.

Avalon-ST end of packet signal. The MegaCore function asserts this signal when it is ending a frame.

Avalon-ST select signal. Use this signal to select a specific channel.

Tab le 4– 6 lists the direct control interface signals. These signals are exposed as ports if

you turn off the Include Avalon-MM Control Interface parameter.

Table 4–6. Direct Control Interface Signals (Part 1 of 2)

Signal Width Direction Description

reg_clk

audio_control

extended_control

video_status

audio_status

cs_control

sine_freq_ch1

sine_freq_ch2

sine_freq_ch3

sine_freq_ch4

csram_addr

[0:0] Input Clock for the direct control interface.

[7:0] Input

[7:0] Output

[15:0] Input

[7:0] Input

[5:0] Input Channel status RAM address.

This signal does the same function as the audio control register in Table 4– 9.

This signal does the same function as the extended control register in Table 4– 9.

This signal does the same function as the video status register in Table 4– 9.

This signal does the same function as the audio status register in Table 4– 9.

This signal does the same function as the channel status control registers in Table 4–9.

This signal does the same function as the sine channel 1 frequency register in Table 4–9.

This signal does the same function as the sine channel 2 frequency register in Table 4–9.

This signal does the same function as the sine channel 3 frequency register in Table 4–9.

This signal does the same function as the sine channel 4 frequency register in Table 4–9.

Serial Digital Interface (SDI) MegaCore Function February 2013 Altera Corporation User Guide

Chapter 4: SDI Audio IP Cores 4–7

SDI Audio Embed MegaCore Function

Table 4–6. Direct Control Interface Signals (Part 2 of 2)

Signal Width Direction Description

csram_we

[0:0] Input

Drive this signal high for a single cycle of load the value of the

csram_data

status RAM at the address on the

port into the channel

csram_addr

If each input audio pair gets separate channel status RAMs,

reg_clk

port.

signal to

this signal addresses the RAM selected by the

csram_data

[7:0] Input

extended_control

Channel status data. This signal does the same function as the channel status RAM register in Ta ble 4– 9.

port.

Tab le 4– 7 lists the register interface signals. The register interface is a standard 8-bit

wide Avalon-MM slave.

Table 4–7. Register Interface Signals

Signal Width Direction Description

reg_clk

reg_reset

reg_base_addr

reg_burst_count

reg_waitrequest

reg_write

reg_writedata

reg_read

reg_readdatavalid

reg_readdata

[0:0] Input Clock for the Avalon-MM register interface.

[0:0] Input Reset for the Avalon-MM register interface.

[5:0] Input Address in target region of first byte of transfer

[5:0] Input Transfer size in bytes

[0:0] Output Wait request

[0:0] Input Write request

[7:0] Input Data to be written to target

[0:0] Input Read request

[0:0] Output Requested read data valid after read latency

[7:0] Output Data read from target

February 2013 Altera Corporation Serial Digital Interface (SDI) MegaCore Function

User Guide

4–8 Chapter 4: SDI Audio IP Cores

SDI Audio Embed MegaCore Function

Register Maps

Tab le 4– 8 and Ta bl e 4 –9 lists the register maps for SDI Audio Embed MegaCore

function.

Table 4–8. SDI Audio Embed MegaCore Function Register Map

Bytes Offset Name

00h Audio Control Register

01h Extended Control Register

02h Video Status Register

03h Audio Status Register

04h Channel Status Control Registers (3:0)

05h Channel Status Control Registers (7:4)

06h–07h Reserved

08h Sine Channel 1 Frequency

09h Sine Channel 2 Frequency

0Ah Sine Channel 3 Frequency

0Bh Sine Channel 4 Frequency

0Ch–0Fh Reserved

10h–3Fh Channel Status RAM (0×00), (0×01), ... (0×2F)

Table 4–9. SDI Audio Embed MegaCore Function Register Map

Bit Name Access Description

Audio Control Register

Enables the embedding of each audio group. When working with HD-SDI or 3G-SDI video, embedding of the audio control packet is also enabled when one or more audio groups are enabled.

The following bits correspond to the number of audio groups you

3:0 Audio group enable RW

specify:

■ Bit [0] = Audio group 1

■ Bit [1] = Audio group 2

■ Bit [2] = Audio group 3

■ Bit [3] = Audio group 4

7:4 Unused — Reserved for future use.

Extended Control Register

When you specify the Channel Status RAM parameter to 2, this field

2:0

Channel status RAM select

selects the channel pair for the RAM written to by registers 10h to 3Fh. If you specify the Channel Status RAM parameter to 0 or 1, ignore this signal.

3 Unused — Reserved for future use.

Test sine generator

enable

When set to

, this bit ignores the audio inputs and uses the output

of the sine generator as the data for each audio group.

7:5 Unused — Reserved for future use.

Serial Digital Interface (SDI) MegaCore Function February 2013 Altera Corporation User Guide

Chapter 4: SDI Audio IP Cores 4–9

SDI Audio Embed MegaCore Function

Table 4–9. SDI Audio Embed MegaCore Function Register Map

Bit Name Access Description

Video Status Register

Reports the detected video input standard.

Bits[7:5] = Picture structure code.

Defined values for picture structure code are:

001b

= 486 or 576 line SD-SDI

100b

= 720 line HD-SDI

101b

= 1080 line HD-SDI

010b

= 1080 line 3G-SDI

Bit[4] = 0b—Interlace or segmented frame, 1b—Progressive.

7:0 Active channels RO

Bits[3:0] = Frame rate code.

Defined values for frame rate code (in Hz) are:

0010b

= 23.97

0011b

= 24

0101b

= 25

0110b

= 29.97

0111b

= 30

1001b

= 50

1010b

= 59.94

1011b

= 60

Audio Status Register

7:0 Unused — Reserved for future use.

Channel Status Control Registers

00b

When set to

, the core keeps the existing channel status data.

01b

, the core replaces the channel status data with

default values.

When set to

10b

, the core replaces the data with the contents of the

appropriate channel status RAM.

7:0 CS mode select RW

The following bits correspond to the number of audio groups you specify:

■ Bit [1:0] = Audio group 1

■ Bit [3:2] = Audio group 2

■ Bit [5:4] = Audio group 3

■ Bit [7:6] = Audio group 4

Sine Channel n Frequency

7:0 Sine channel frequency RW Defines the frequency of the generated audio.

Channel Status RAM

Write accesses within the address range 10h to 3Fh to the channel

7:0 Channel status data WO

status RAM. This field returns the 24 bytes of channel status for X channels starting at address 10h to 27h, and the 24 bytes of channel status for Y channels starting at address 28h to 3Fh.

February 2013 Altera Corporation Serial Digital Interface (SDI) MegaCore Function

User Guide

4–10 Chapter 4: SDI Audio IP Cores

Sample FIFO

Clock Recovery

Audio Extract or Audio Extract with Avalon

Avalon-MM

48 KHz Clock

Core

Error Detection

Packet Find

and

Extract

AES

Avalon-ST Audio

(Audio Extract

with Avalon Only)

Channel

Status RAM

aud_clk

internal AES

Avalon-ST

Audio

vid_clk

SD/HD/3G-SDI

SDI Audio Extract MegaCore Function

The SDI Audio Extract MegaCore function accepts the SD-, HD-, and 3G-SDI from the SDI MegaCore and extracts one channel pair of embedded audio.

The format of the embedded audio is in accordance with the SMPTE272M-A standard for the SD-SDI video standard, or in accordance with the SMPTE299M standard for HD-SDI and provisionally for 3G-SDI video standard. If you are extracting more than one channel pair, you must use multiple instances of the component. This MegaCore function supports AES audio format for 48-kHz sampling rate.

Functional Description

Figure 4–2 shows a block diagram of the SDI Audio Extract MegaCore function.

Figure 4–2. SDI Audio Extract MegaCore Function Block Diagram

The SDI Audio Extract MegaCore function consists of the audio extraction core and a register interface block that provides support for an Avalon-MM control bus.

The clock recovery block recreates a 64 × sample rate clock, which you can use to clock

Serial Digital Interface (SDI) MegaCore Function February 2013 Altera Corporation User Guide

the audio output logic. As the component recreates this clock from a 200-MHz reference clock, the created clock may have a higher jitter than is desirable.

Chapter 4: SDI Audio IP Cores 4–11

SDI Audio Extract MegaCore Function

A digital PLL synchronizes this created clock to a 24-kHz reference source. For the HD-SDI embedded audio, the 24-kHz reference source is the embedded clock phase information. For the SD-SDI embedded audio, where the embedded clock phase data is not present, you can create the 24-kHz reference signal directly from the video clock.

Figure 4–3 shows the clock recovery block diagram.

Figure 4–3. Clock Recovery Block Diagram

Video standard

vid_clk

Extracted

audio data

Programmable

Divide

Clock Phase

Recovery

24 KHz

Digital

PLL

3.072 MHz Output

/128

Parameters

Tab le 4– 10 lists the parameters for the SDI Audio Extract MegaCore function.

Table 4–10. SDI Audio Extract MegaCore Function Parameters

Parameter Value Description

Channel status RAM On or off Turn on to store the received channel status data.

Include error checking On or off

Include status register On or off

Include clock On or off

Include Avalon-ST interface On or off

Include Avalon-MM control interface

On or off

Turn on to enable extra error-checking logic to use the error status register.

Turn on to enable extra logic to report the audio FIFO status on

fifo_status

the

port or register.

Turn on to enable the logic to recover both a sample rate clock and a 64 × sample rate clock.

With HD-SDI inputs, the core generates the output by using the embedded clock phase information.

With SD-SDI inputs, the core generates this output by using the counters running on the 27MHz video clock. This generation limits the SD-SDI embedded audio to being synchronous to the video.

Turn on to include the SDI Clocked Audio Input MegaCore.

When you turn on this parameter, the Avalon-ST interface signals in Table 4–14 appear at the top level. Otherwise, the audio input signals in Table 4–17 appear at the top level.

Turn on to include the Avalon-MM control interface.

When you turn on this parameter, the register interface signals in Table 4–7 appear at the top level. Otherwise, the direct control interface signals in Table 4–15 appear at the top level.

February 2013 Altera Corporation Serial Digital Interface (SDI) MegaCore Function

User Guide

4–12 Chapter 4: SDI Audio IP Cores

SDI Audio Extract MegaCore Function

Signals

Tab le 4– 11 lists the clock recovery input and output signals for the SDI Audio Extract

MegaCore function.

Table 4–11. Clock Recovery Input and Output Signals

Signal Width Direction Description

reset

fix_clk

aud_clk_out

aud_clk48_out

[0:0] Input This signal resets the system.

[0:0] Input

Assert this 200 MHz reference clock when you turn on the Include Clock parameter.

The core asserts this 64 × sample rate clock (3.072 MHz audio clock) when you turn on the Include Clock parameter.

[0:0] Output

You use this clock to clock the audio interface in synchronous mode.

As the core creates this clock digitally, it is prone to higher levels of jitter.

[0:0] Output

The core asserts this sample rate clock when you turn on the Include Clock parameter.

Tab le 4– 12 shows the video input signals for the SDI Audio Extract MegaCore

function.

Table 4–12. Video Input Signals

Signal Width Direction Description

vid_clk

vid_std

vid_datavalid

vid_data

vid_locked

The video clock that is typically 27 MHz for SD-SDI,

[0:0] Input

[1:0] Input

74.25 MHz or 74.17 MHz for HD-SDI, or 148.5 MHz or 148.35 MHz for 3G-SDI standards. You can use higher clock rates with the

Set this signal to formats,

01b

00b

for 20-bit HD-SDI formats,

Level A formats, and

vid_datavalid

to indicate 10-bit SD-SDI

11b

10b

for 3G-SDI Level B formats.

[0:0] Input Assert this signal when the video data is valid.

This signal carries luma and chroma information.

SD-SDI:

■ [19:10] Unused

■ [9:0] Cb,Y, Cr, Y multiplex

[19:0] Input

HD-SDI and 3G-SDI Level A:

■ [19:10] Y

■ [9:0] C

3G-SDI Level B:

■ [19:10] Cb,Y, Cr, Y multiplex (link A)

■ [9:0] Cb,Y, Cr, Y multiplex (link B)

[0:0] Input Assert this signal when the video is locked.

signal.

for 3G

Serial Digital Interface (SDI) MegaCore Function February 2013 Altera Corporation User Guide

Altera Serial Digital Interface MegaCore Function User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Contents

1. About This MegaCore Function

Features

Release Information

Device Family Support

General Description

OpenCore Plus Evaluation

Resource Utilization

Design Flow

2. Getting Started

SDI Walkthrough

Creating a New Quartus II Project

Launching MegaWizard Plug-In Manager

Parameterizing

Setting Up Simulation

Generating Files

Simulating the Design

Testbench

Simulate with IP Functional Simulation Models

Simulating with the ModelSim Simulator

Simulating in Third-Party Simulation Tools Using NativeLink

Specifying Constraints

Single Channel

Multiple Channels

Compiling the Design

Programming a Device

Setting Up Licensing

3. Functional Description

Transmitter

Block Description

HD-SDI LN Insertion

HD-SDI CRC Generation and Insertion

Scrambling and NRZI Coding

Transceiver Clock

Receiver

NRZI Decoding and Descrambling

Word Alignment

Video Timing Flags Extraction

RP168 Switching Compliance

HD-SDI LN Extraction

HD-SDI CRC Checking

Accessing Transceiver

Transceiver Clock

Transceiver—Soft-Logic Implementation

Transmitter

Transmitter Clocks

Receiver

Receiver Clocks

Transceiver—Stratix GX Devices

Transmitter Clocks

Receiver Clocks

Transmitter Transceiver Interface

Receiver Transceiver Interface

Transceiver—Arria GX, Arria II GX, Arria V, Cyclone IV GX, Cyclone V, Stratix II GX, Stratix IV GX, and Stratix V Devices

Transmitter Clocks

Receiver Clocks

Transmitter Transceiver Interface

Receiver Transceiver Interface

Locking to the Incoming SDI Stream

Transceiver Dynamic Reconfiguration for Dual Standard and Triple Standard Receivers

Transceiver Dynamic Reconfiguration with Channel Reconfiguration Mode— Arria II GX, HardCopy IV GX, Stratix GX, Stratix II GX, and Stratix IV GX

Transceiver Dynamic Reconfiguration with PLL Reconfiguration Mode— Cyclone IV GX

Reset Requirement During Reconfiguration

Signals

OpenCore Plus Time-Out Behavior

Parameters

MegaCore Verification

SDI Audio Embed MegaCore Function

4. SDI Audio IP Cores

Functional Description

Parameters

Signals

Register Maps

SDI Audio Extract MegaCore Function

Functional Description

Parameters