Altera SDI II MegaCore User Manual
SDI II IP Core User Guide
Last updated for Altera Complete Design Suite: 15.0
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TOC-2
Contents
SDI II IP Core Quick Reference..........................................................................1-1
SDI II IP Core Overview......................................................................................2-1
SDI II IP Core Getting Started............................................................................3-1
General Description.....................................................................................................................................2-1
SMPTE372 Dual Link Support.......................................................................................................2-2
SMPTE RP168 Switching Support.................................................................................................2-6
SD 20-Bit Interface for Dual/Triple Standard..............................................................................2-6
Dynamic TX Clock Switching........................................................................................................2-7
Resource Utilization.................................................................................................................................... 2-9
Installation and Licensing...........................................................................................................................3-1
Design Walkthrough................................................................................................................................... 3-1
Creating a New Quartus II Project................................................................................................3-2
Launching IP Catalog......................................................................................................................3-2
Parameterizing the IP Core............................................................................................................ 3-3
Generating a Design Example and Simulation Testbench.........................................................3-3
Simulating the SDI II IP Core Design...........................................................................................3-3
Compiling the SDI II IP Core Design.......................................................................................................3-4
Programming an FPGA Device................................................................................................................. 3-5
Design Reference..........................................................................................................................................3-5
SDI II IP Core Parameters..............................................................................................................3-6
SDI II IP Core Component Files....................................................................................................3-9
Design Examples..............................................................................................................................3-9
Video Pattern Generator Signals................................................................................................. 3-22
Transceiver Reconfiguration Controller Signals.......................................................................3-23
Reconfiguration Management Parameters.................................................................................3-26
Reconfiguration Router Signals...................................................................................................3-27
SDI II IP Core Functional Description...............................................................4-1
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Protocol......................................................................................................................................................... 4-2
Transmitter.......................................................................................................................................4-2
Receiver............................................................................................................................................. 4-6
Transceiver..................................................................................................................................................4-12
Submodules.................................................................................................................................................4-14
Insert Line.......................................................................................................................................4-14
Insert/Check CRC..........................................................................................................................4-15
Insert Payload ID........................................................................................................................... 4-15
Match TRS...................................................................................................................................... 4-17
Scrambler........................................................................................................................................ 4-17
TOC-3
TX Sample.......................................................................................................................................4-18
Clock Enable Generator................................................................................................................4-18
RX Sample.......................................................................................................................................4-19
Detect Video Standard..................................................................................................................4-21
Detect 1 and 1/1.001 Rates............................................................................................................4-21
Transceiver Controller..................................................................................................................4-21
Descrambler....................................................................................................................................4-22
TRS Aligner.....................................................................................................................................4-23
3Gb Demux.....................................................................................................................................4-24
Extract Line.....................................................................................................................................4-24
Extract Payload ID.........................................................................................................................4-24
Detect Format.................................................................................................................................4-24
Sync Streams...................................................................................................................................4-25
Convert SD Bits..............................................................................................................................4-26
Insert Sync Bits...............................................................................................................................4-26
Clocking Scheme........................................................................................................................................4-27
SDI II IP Core Signals................................................................................................................................4-27
Additional Information......................................................................................A-1
Document Revision History......................................................................................................................A-1
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SDI II IP Core Quick Reference
1
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The Altera® Serial Digital Interface (SDI) II MegaCore® function is the next generation SDI intellectual
property (IP).
The SDI II IP core is part of the MegaCore IP Library, which is distributed with the Quartus® II software
and downloadable from the Altera website at www.altera.com.
Note:
For system requirements and installation instructions, refer to Altera Software Installation &
Licensing.
Table 1-1: Brief Information About the SDI II IP Core
Item Description
Version 15.0
Release Date May 2015
Release
Information
Ordering Code IP-SDI-II
Product ID(s) 0111
Vendor ID 6AF7
SDI Data Rate
Support
• 270-Mbps SD-SDI, as defined by SMPTE259M specification
• 1.485-Gbps or 1.4835-Gbps HD-SDI, as defined by
SMPTE292M specification
• 2.97-Gbps or 2.967-Gbps 3G-SDI, as defined by SMPTE424M
specification
• 5.94-Gbps or 5.934-Gbps 6G-SDI, as defined by SMPTEST2081
IP Core
Information
specification
• 11.88-Gbps or 11.868-Gbps 12G-SDI, as defined by
SMPTEST2082 specification
• Dual link HD-SDI, as defined by SMPTE372M specification
• Dual standard support for SD-SDI and HD-SDI
• Triple standard support for SD-SDI, HD-SDI, and 3G-SDI
• Multi standard support for SD-SDI, HD-SDI, 3G-SDI, 6G-SDI,
and 12G-SDI
©
2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
1-2
SDI II IP Core Quick Reference
Item Description
Features • 20-bit interface support for SD-SDI
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• Multiple SDI standards and video formats
• Payload identification packet insertion and extraction
• Clock enable generator
• Video rate detection
• Cyclical redundancy check (CRC) encoding and decoding
(except SD)
• Line number (LN) insertion and extraction (except SD)
• Word scrambling and descrambling
• Word alignment
• Framing and extraction of video timing signals
• Dual link data stream synchronization (except SD)
• Transceiver dynamic reconfiguration
• RP168 support for synchronous video switching
• Dynamic TX clock switching
• OpenCore Plus evaluation
• SMPTE425M level A support (direct source image formatting)
• SMPTE425M level B support (dual link mapping)
Application • Digital video equipment
• Mixing and recording equipment
Device Family
Support
Arria® 10 (preliminary), Arria V GX, Arria V GZ, Cyclone® V,
and Stratix® V FPGA device families.
Refer to the device support table and What’s New in Altera page of
the Altera website for detailed information.
Design Tools • IP Catalog in the Quartus II software for design creation and
compilation
• ModelSim®-Altera, Riviera-Pro, and VCS/VCS MX software
for design simulation or synthesis
Related Information
• Altera Software Installation and Licensing
• What's New in Altera IP
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SDI II IP Core Overview
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The SDI II IP core implements a transmitter, receiver, or full-duplex SDI at standard definition (SD), high
definition (HD), or 3 gigabits per second (3G) to 12G rate as defined by the Society of Motion Picture and
Television Engineers (SMPTE). The SDI II IP core supports dual standard (SD-SDI and HD-SDI), triple
standard (SD-SDI, HD-SDI, and 3G-SDI) and multi standard (SD-SDI, HD-SDI, 3G-SDI, 6G-SDI, and
12G-SDI). These modes provide automatic receiver rate detection and transceiver dynamic reconfigura‐
tion.
The SDI II IP core highlights the following new features:
• Supports 28 nm devices and beyond.
• Arria V GX and Stratix V from Quartus II version 12.1 onwards
• Arria V GZ and Cyclone V from Quartus II version 13.0 onwards
• Arria 10 from Quartus II version 14.0A10 onwards
• Improved integration with Altera tools (hw.tcl).
• IEEE encryption for functional simulation.
• Dynamic generation of user simulation testbench that matches the IP configuration.
• Dynamic generation of design example that serves as common entity for simulation and hardware
verification.
General Description
The SMPTE defines a SDI standard that is widely used as an interconnect between equipment in video
production facilities. The SDI II IP core can handle the following SDI data rates:
• 270 megabits per second (Mbps) SD-SDI, as defined by SMPTE259M-1997 10-Bit 4:2:2 Component
Serial Digital Interface
• 1.485 gigabits per second (Gbps) or 1.4835-Gbps HD-SDI, as defined by SMPTE292M-1998 Bit-Serial
Digital Interface for High Definition Television Systems
• 2.97-Gbps or 2.967-Gbps 3G SDI, as defined by SMPTE424M
• 5.94-Gbps or 5.934-Gbps 6G-SDI, as defined by SMPTEST2081
• 11.88-Gbps or 11.868-Gbps 12G-SDI, as defined by SMPTEST2082
• Dual link HD-SDI, as defined by SMPTE372M-Dual Link 1.5Gb/s Digital Interface for 1920×1080 and
2048×1080 Picture Formats
• Dual standard support for SD-SDI and HD-SDI
©
2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
2-2
SMPTE372 Dual Link Support
• Triple standard support for SD-SDI, HD-SDI, and 3G-SDI
• Multi standard support for SD-SDI, HD-SDI, 3G-SDI, 6G-SDI, and 12G-SDI
• SMPTE425M level A support (direct source image formatting)
• SMPTE425M level B support (dual link mapping)
• SMPTE RP168 switching support
Table 2-1: SDI Standard Support
Table below lists the SDI standard support for various FPGA devices.
SDI Standard
Single Standard Multiple Standards
Device Family
SD-SDI HD-SDI 3G-SDI Dual Link
HD-SDI
Dual
Standard
(up to HD)
Triple
Standard
(up to 3G)
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Multi Standard
(up to 12G)
Arria V
Yes Yes Yes Yes Yes Yes No
GX
Arria V
Yes Yes Yes Yes Yes Yes No
GZ
Stratix V Yes Yes Yes Yes Yes Yes No
Cyclone V Yes Yes Yes Yes Yes Yes No
Arria 10 No Yes Yes Yes No Yes Yes
SMPTE372 Dual Link Support
Recording studios support HD 1080p format by using a dual-link connection (SMPTE372) from cameras
to the mixing and recording equipment. The SMPTE 372 specification defines a way of interconnecting
digital video equipment with a dual link HD-SDI, based upon the SMPTE292 specification data structure.
The total data rate of the dual link connection is 2.97 Gbps or 2.97/1.001 Gbps.
HD-SDI Dual Link to 3G-SDI (Level B) Conversion
To interface between a HD-SDI dual link receiver and 3G-SDI single link transmitter equipment, perform
a HD-SDI dual link to 3G-SDI (level B) conversion. Level B is defined as 2× SMPTE292 HD-SDI
mapping, including SMPTE372 dual link mapping.
This conversion takes either two 1.485 Gbps dual link signals or two separate co-timed HD signals and
combines them into a single 3G-SDI stream.
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3FFh(C1)
3FFh(Y1)
000h(C1)
000h(Y1)
XYZ(C1)
XYZ(Y1)
LN0(C1)
LN0(Y1)
LN1(C1)
LN1(Y1)
3FFh(C2)
3FFh(Y2)
000h(C2)
000h(Y2)
XYZ(C2)
XYZ(Y2)
LN0(C2)
LN0(Y2)
LN1(C2)
LN1(Y2)
000h(C1)
000h(Y1)
000h(C2)
000h(Y2)
Multiplexing
Data Stream 1
Data Stream 2
3G-SDI Level B
Interleaved Stream
3FFh(C2)
3FFh(C1)
3FFh(Y2)
3FFh(Y1)
000h(C2)
000h(C1)
000h(Y2)
000h(Y1)
XYZ(C2)
XYZ(C1)
XYZ(Y2)
XYZ(Y1)
LN0(C2)
LN0(C1)
LN0(Y2)
LN0(Y1)
LN1(C2)
LN1(C1)
LN1(Y2)
LN1(Y1)
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HD-SDI Dual Link to 3G-SDI (Level B) Conversion
Figure 2-1: Example of HD-SDI Dual Link to 3G-SDI (Level B) Conversion
The figure shows the conversion of two HD-SDI data streams to 3G-SDI (level B) data streams.
2-3
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Transceiver
HD Link A
Protocol FIFO
rxdataA rxdataA rdreq
Transceiver
HD Link B
Protocol FIFO
rxdataB rxdataB
rdreq
Divide
Clock
rx_clkin_smpte372
(148.5 MHz or 148.35 MHz)
rx_dataout[19:0]
rdclk_3gb_div2 =
1H1L1H1L
xcvr_refclk (74.25 MHz or 74.175 MHz)
rx_clkout
(74.25 MHz or 74.175 MHz)
rx_clkout_b
(74.25 MHz or 74.175 MHz)
Sync Stream
HD Dual-Link Receiver
Y1 Y1 Y1 Y1
C1 C1 C1 C1
Y2 Y2 Y2 Y2
C2 C2 C2 C2
rx_clkout
rxdataA[19:10]
rxdataA[9:0]
rx_clkout_b
rxdataB[19:10]
rxdataB[9:0]
rx_clkin_smpte372
rdclk_3gb_div2
rx_dataout[19:10]
rx_dataout[9:0]
C1 C1 C1 C1Y1 Y1 Y1 Y1
C2 C2 C2 C2Y2 Y2 Y2 Y2
2-4
3G-SDI (Level B) to HD-SDI Dual Link Conversion
Figure 2-2: Implementation of HD-SDI Dual Link to 3G-SDI (Level B) Conversion
The figure shows a block diagram of HD-SDI dual link to 3G-SDI (level B) conversion.
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3G-SDI (Level B) to HD-SDI Dual Link Conversion
To interface between 3-Gbps single link receiver and HD-SDI dual link transmitter equipment, perform a
3G-SDI (level B) to HD-SDI dual link conversion. This conversion takes a single 3G-SDI signal and
separates the signal into two 1.485 Gbps signals, which can either be a dual link 1080p signal or two
separate co-timed HD data streams.
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3FFh(C2)
Demux
3FFh(C1)
3FFh(Y2)
3FFh(Y1)
000h(C2)
000h(C1)
000h(Y2)
000h(Y1)
XYZ(C2)
XYZ(C1)
XYZ(Y2)
XYZ(Y1)
LN0(C2)
LN0(C1)
LN0(Y2)
LN0(Y1)
LN1(C2)
LN1(C1)
LN1(Y2)
LN1(Y1)
3FFh(C1)
3FFh(Y1)
000h(C1)
000h(Y1)
XYZ(C1)
XYZ(Y1)
LN0(C1)
LN0(Y1)
LN1(C1)
LN1(Y1)
3FFh(C2)
3FFh(Y2)
000h(C2)
000h(Y2)
XYZ(C2)
XYZ(Y2)
LN0(C2)
LN0(Y2)
LN1(C2)
LN1(Y2)
000h(C1)
000h(Y1)
000h(C2)
000h(Y2)
3G-SDI Level B Interleaved Stream
Data Stream 1
HD-SDI Link A (10-bit)
HD-SDI Link B (10-bit)
Data Stream 2
Transceiver
3-GB Signal
Protocol
3-GB
Demux
rxdata
rx_clkin_smpte372
(74.25 MHz or 74.175 MHz)
rx_dataout[19:0]
rdclk_3gb_div2 =
1H1L1H1L
xcvr_refclk (148.5 MHz or 148.35 MHz)
rx_clkout
(148.5 MHz or 148.35 MHz)
FIFO
rx_dataout_b[19:0]
rx_dataout[19:0]
rx_dataout_b[19:0]
wrreq
rxdata[19:0]
rx_trs
3-GB Receiver
rx_clkout
rx_trs
rxdata[19:10]
rxdata[9:0]
C1 C1 C1 C1Y1 Y1 Y1 Y1
C2 C2 C2 C2Y2 Y2 Y2 Y2
Y1 Y1 Y1 Y1
C1 C1 C1 C1
Y2 Y2 Y2 Y2
C2 C2 C2 C2
rx_clkin_smpte372
rx_dataout[19:10]
rx_dataout[9:0]
rx_clkdiv2
rx_dataout_b[19:10]
rx_dataout_b[9:0]
rx_clkout
rx_trs
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3G-SDI (Level B) to HD-SDI Dual Link Conversion
Figure 2-3: Example of 3G-SDI (Level B) to HD-SDI Dual Link Conversion
The figure shows the conversion of 3G-SDI (level B) data to two HD-SDI data streams.
Figure 2-4: Implementation of 3G-SDI (Level B) to HD-SDI Dual Link Conversion
2-5
The figure shows a block diagram of 3G-SDI (level B) to HD-SDI dual link conversion.
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rx_clkout(148.5 MHz)
rx_dataout[19:10]
rx_dataout[9:0]
rx_dataout_valid
Don’t Care
Cb Y Cr Y Cb
rx_clkout(148.5 MHz)
rx_dataout[19:10]
rx_dataout[9:0]
rx_dataout_valid
Cb
Y
Cr
Y Y
Cb
2-6
SMPTE RP168 Switching Support
SMPTE RP168 Switching Support
The SMPTE RP168 standard defines the requirements for synchronous switching between two video
sources to take place with minimal interference to the receiver. The RP168 standard has restrictions for
which lines the source switching can occur.
The SDI II IP core has flexibility and does not restrict you to switch at only a particular line defined in the
RP168 standard. You can perform switching at any time between different video sources as long as the
source has similar standard and format. After switching, all the status output signals, including the
rx_trs_locked, rx_frame_locked, and rx_align_locked signals, remain unchanged. You should
should not see any interrupts at downstream.
SD 20-Bit Interface for Dual/Triple Standard
For a common SD interface, the serial data format is 10 bits wide, whereas for HD or 3G, the data format
is 20 bits wide, divided into two parallel 10-bit datastreams (known as Y and C).
To make the interface bit width common for all standards in the dual standard or triple standard SDI
mode:
• The receiver can extract the data and align them in 20-bit width
• The transmitter can accept SD data in 20-bit width and retransmit them successfully
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The timing diagrams below show a comparison of data arrangement between 10-bit and 20-bit interface.
Figure 2-5: SD 10-Bit Interface
• The upper 10 bits of rx_dataout are insignificant data.
• The lower 10 bits of rx_dataout are Luma (Y) and chroma (Cb, Cr) channels (interleaved).
• The 1H 4L 1H 5L cadence of rx_dataout_valid repeats indefinitely (ideal).
Figure 2-6: SD 20-Bit Interface
Altera Corporation
• The upper 10 bits of rx_dataout are Luma (Y) channel and the lower 10 bits are Chroma (Cb, Cr)
channel.
• The 1H 10L cadence of rx_dataout_valid repeats indefinitely (ideal).
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Dynamic TX Clock Switching
The dynamic TX clock switching feature allows you to dynamically switch between NTSC and PAL
transceiver data rates for all video standards except SD-SDI. The dynamic TX clock switching enables an
SDI video equipment to operate on NTSC or PAL.
You can choose to switch the TX clocks through one of these two methods:
• Instantiate an alternate TX PLL and supply two different clocks to the two PLLs. Switch between the
primary PLL and the alternate PLL for transmission.
• Use the primary PLL with two reference input clocks. The PLL switches between these two clocks for
transmission.
To implement this feature, you are required to provide two reference clocks (xcvr_refclk and
xcvr_refclk_alt) to the SDI II IP core. The frequency of the reference clocks must be assigned to 148.5
MHz and 148.35 MHz in any assignment order.
The TX PLL select signal (ch1_{tx/du}_tx_pll_sel) is an input control signal that you provide to the
core and the transceiver reconfiguration controller to select the desired clock input for the hard
transceiver.
• Set ch1_{tx/du}_tx_pll_sel to 0 to select xcvr_refclk
• Set ch1_{tx/du}_tx_pll_sel to 1 to select xcvr_refclk_alt
Dynamic TX Clock Switching
2-7
To dynamically switch between the two reference clocks, you need to implement a simple handshaking
mechanism. The handshake is initiated when the reconfiguration request signal (ch1_{tx/
du}_tx_start_reconfig) is asserted high. This signal must remain asserted until the reconfiguration
process completes. The reconfiguration process completes when the reconfiguration done signal
(ch1_{tx/du}_tx_reconfig_done) is asserted high. The TX PLL select signal (ch1_{tx/
du}_tx_pll_sel) needs to be stable throughout the reconfiguration process.
To complete the handshaking process, you must deassert the reconfiguration request signal (ch1_{tx/
du}_tx_start_reconfig) upon assertion of the reconfiguration done signal (ch1_{tx/
du}_tx_reconfig_done). The dynamic TX clock switching only takes effect after the tx_rst is asserted
high and deasserted low accordingly.
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TX Protocol
TX PHY
Management
PHY Adapter
Transceiver
PHY Reset
Controller
Transceiver
Reconfiguration
Controller
Reconfiguration
Management
Reconfiguration
Router
TX Transceiver
Channel
TX PLL0 TX PLL1
Parallel Video In
(tx_datain and
tx_datain_b for
HD-SDI Dual Link)
Primary Reference Clock (xcvr_refclk)
Alternative Reference Clock (xcvr_refclk_alt)
Reset
(tx_rst)
Tx PLL Switching
Handshaking
Signals
Reconfiguration Acknowledge
(ch1_{tx/du}_tx_reconfig_done)
Reconfiguration Request
(ch1_{tx/du}_tx_start_reconfig)
TX PLL Select (ch1_{tx/du}_tx_pll_sel)
Avalon-MM
Control Interface
TX Clock Out (tx_clkout)
(148.5 or 148.35 MHz)
SDI Out
(sdi_tx and sdi_tx_b for
HD-SDI Dual Link)
Altera Transceiver
Analog Reset
Digital Reset
PLL Powerdown
PLL Locked
Cal Busy
TX PLL Select
SDI TX (All Video Standard Modes except SD-SDI)
Altera PHY
IP Core
Data
Control/Status
Clock
Reset
Legend
148.5 MHz
148.35 MHz
148.5 MHz
Case 1 Case 2 Case 3
148.35 MHz 148.5 MHz 148.35 MHz
xcvr_refclk
xcvr_refclk_alt
tx_rst
ch1_{tx/du}_tx_pll_sel
ch1_{tx/du}_tx_start_reconfig
ch1_{tx/du}_tx_reconfig_done
tx_clkout
2-8
Dynamic TX Clock Switching
Figure 2-7: Hardware Implementation of the Dynamic TX Clock Switching Feature
The figure shows the TX clock switching feature with two TX PLLs.
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Figure 2-8: Dynamic TX Clock Switching Timing Diagram
The table below describes the behavior of the dynamic switching feature when you initiate a handshaking
process (with reference to the timing diagram).
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Table 2-2: Dynamic Switching Behavior During a Handshaking Process
Case Description
1 The handshaking process attempts to switch to select xcvr_refclk_alt. tx_clkout success‐
fully locks to xcvr_refclk_alt (148.35 MHz).
2 The handshaking process attempts to switch to select xcvr_refclk. tx_clkout successfully
locks to xcvr_refclk (148.5 MHz).
3 The handshaking process attempts to switch to select xcvr_refclk_alt. The switching fails
because ch1_{tx/du}_tx_pll_sel changes from 1 to 0 prior to the assertion of ch1_{tx/
du}_tx_start_reconfig. Therefore tx_clkout is still locked to xcvr_refclk (148.5MHz).
Resource Utilization
The tables below list the typical resource utilization for the SDI II IP core with the Quartus II software,
version 15.0.
Note:
The resource utilization data was obtained by using the most common configurations for each
video standard and from one specific family device.
Resource Utilization
2-9
Table 2-3: Resource Utilization for Each Video Standard (Arria V, Cyclone V, and Stratix V Devices)
Standard ALM Needed Primary Logic
Registers
Secondary Logic
Registers
Block Memory Bits
SD-SDI TX 95 126 10 0
SD-SDI RX 528 641 48 60
HD-SDI TX 141 159 10 0
HD-SDI RX 557 821 60 0
HD Dual Link TX 447 478 43 0
HD Dual Link RX 1,305 1,897 155 4,608
3G-SDI TX 444 414 12 0
3G-SDI RX 826 1307 125 0
Dual Rate TX 242 237 4 0
Dual Rate RX 924 1,209 84 0
Triple Rate TX 496 528 8 0
Triple Rate RX 1,064 1,583 98 0
Table 2-4: Resource Utilization for Each Video Standard (Arria 10 Devices)
Standard ALM Needed Primary Logic
HD-SDI TX 106 124 23 0
HD-SDI RX 523 765 66 0
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Registers
Secondary Logic
Registers
Block Memory Bits
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2-10
Resource Utilization
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Standard ALM Needed Primary Logic
Registers
Secondary Logic
Registers
Block Memory Bits
HD Dual Link TX 367 410 60 0
HD Dual Link RX 1,239 1,780 177 4,608
3G-SDI TX 407 380 13 0
3G-SDI RX 808 1,261 93 0
Triple Rate TX 475 492 9 0
Triple Rate RX 1024 1,535 86 0
Multi Rate (Up to 12G-
1,807 1,742 24 0
SDI) TX
Multi Rate (Up to 12G-
3,581 4,734 270 0
SDI) RX
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Installation and Licensing
To evaluate the SDI II IP core using the OpenCore Plus feature, follow these steps in your design flow:
1. Install the SDI II IP core.
2. Create a custom variation of the SDI II IP core.
3. Implement the rest of your design using the design entry method of your choice.
4. Use the IP functional simulation model to verify the operation of your design.
5. Compile your design in the Quartus II software. You can also generate an OpenCore Plus time-limited
programming file, which you can use to verify the operation of your design in hardware.
For more information on IP functional simulation models, refer to the Simulating Altera Designs
Note:
chapter in volume 3 of the Quartus II Handbook.
The default installation directory for the SDI II IP core on Windows is c:\altera\<version>; on Linux, it is /
opt/ altera<version>.
You can obtain a license for the IP core only when you are completely satisfied with its functionality and
performance, and want to take your design to production. After you purchase a license for the SDI II IP
core, follow these steps:
1. Set up licensing.
2. Generate a programming file for the Altera device or devices on your board.
3. Program the Altera device or devices with the completed design.
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Related Information
Simulating Altera Designs
Design Walkthrough
This walkthrough explains how to create an SDI II IP core design using the Quartus II software and IP
Catalog. After you generate a custom variation of the SDI II IP core, you can incorporate it into your
overall project.
©
2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
3-2
Creating a New Quartus II Project
This walkthrough includes the following steps:
1. Creating a New Quartus II Project on page 3-2
2. Launching IP Catalog on page 3-2
3. Parameterizing the IP Core on page 3-3
4. Generating a Design Example and Simulation Testbench on page 3-3
5. Simulating the SDI II IP Core Design on page 3-3
Creating a New Quartus II Project
Before you begin
You need to create a new Quartus II project with the New Project Wizard, which specifies the working
directory for the project, assigns the project name, and designates the name of the top-level design entity.
To create a new project, perform the following the steps.
1. From the Windows Start menu, select Programs > Altera > Quartus II <version> to run the Quartus
II software. Alternatively, you can use the Quartus II Web Edition software.
2. On the File menu, click New Project Wizard.
3. In the New Project Wizard: Directory, Name, Top-Level Entity page, specify the working directory,
project name, and top-level design entity name. Click Next.
4. In the New Project Wizard: Add Files page, select the existing design files (if any) you want to include
in the project.
5. In the New Project Wizard: Family & Device Settings page, select the device family and specific
device you want to target for compilation. Click Next.
6. In the EDA Tool Settings page, select the EDA tools you want to use with the Quartus II software to
develop your project.
7. The last page in the New Project Wizard window shows the summary of your chosen settings. Click
Finish to complete the Quartus II project creation.
(1)
Click Next.
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Launching IP Catalog
To launch the IP Catalog in the Quartus II software, follow these steps:
1. On the Tools menu, click IP Catalog.
2. Expand the Interface Protocols> Audio & Video folder and double-click SDI II to launch the
parameter editor.
The parameter editor prompts you to specify your IP variation name, optional ports, architecture
features, and output file generation options. The parameter editor generates a top-level .qsys or .qip
file representing the IP core in your project.
3. Click OK to display the SDI II IP core parameter editor.
(1)
To include existing files, you must specify the directory path to where you installed the SDI II IP core. You
must also add the user libraries if you installed the MegaCore IP Library in a different directory from where
you installed the Quartus II software.
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Parameterizing the IP Core
To parameterize your IP core, follow these steps:
1. Select the video standard.
2. Select Bidirectional, Transmitter, or Receiver interface direction.
3. Select Combined Transceiver and Protocol, Separate Transceiver or Separate Protocol, (for Arria V,
Cyclone V, and Stratix V devices only).
4. Turn on the necessary transceiver options, (for Arria V, Cyclone V, and Stratix V devices only).
5. Turn on the necessary receiver options.
Some options may be grayed out, because they are not supported in the currently selected configura‐
tion.
6. Turn on the necessary transmitter options.
Some options may be grayed out, because they are not supported in the currently selected configura‐
tion.
7. Select the example design options, (if you are generating the design example for Arria 10 devices).
8. Click Finish.
Related Information
SDI II IP Core Parameters on page 3-6
Parameterizing the IP Core
3-3
Generating a Design Example and Simulation Testbench
After you have parameterized the IP core, click Generate Example Design to create the following entities:
• design example— serves as a common entity for simulation and hardware verification.
• simulation testbench—consists of the design example entity and other non-synthesizable components.
The example testbench and the automated script are located in the <variation name>_example/
simulation/verilog or <variation name>_example/simulation/vhdl directory.
Note:
Generating a design example can increase processing time.
You can now integrate your custom IP core variation into your design, simulate, and compile.
Simulating the SDI II IP Core Design
After design generation, the files located in the <variation name>_example/simulation/verilog or
<variation name>_example/simulation/vhdl directory are available for you to simulate your design.
The SDI II IP core supports the following EDA simulators listed in the table below.
Table 3-1: Supported EDA Simulators
Simulator Supported Platform Supported Language
ModelSim-SE Windows/Linux VHDL and Verilog HDL
ModelSim-Altera Windows/Linux Verilog
VCS/VCS MX Windows/Linux Verilog
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3-4
Timing Violation
Simulator Supported Platform Supported Language
Aldec Riviera-PRO Linux Verilog
To simulate the design using the ModelSim-SE or ModelSim-Altera simulator, follow these steps:
1. Start the simulator.
2. On the File menu, click Change Directory > Select <variation name>_example_design/simulation/
verilog/mentor (for Verilog HDL language) or _example_design/simulation/vhdl/mentor (for
VHDL language).
3. Run the provided run_sim.tcl script. This file compiles the design and runs the simulation automati‐
cally. It provides a pass/fail indication on completion.
To simulate the design using the VCS/VCS MX simulator (in Linux), follow these steps:
1. Start the VCS/VCS MX simulator.
2. On the File menu, click Change Directory > Select <variation name>_example_design/sdi_ii/
simulation/verilog/synopsys.
3. Run the provided run_vcs.sh (in VCS) or run_vcsmx.sh (in VCSMX) script. This file compiles the design
and runs the simulation automatically. It provides a pass/fail indication on completion.
To simulate the design using the Aldec Riviera-PRO simulator, follow these steps:
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1. Start the Aldec Riviera-PRO simulator.
2. On the File menu, click Change Directory > Select <variation name>_example_design/sdi_ii/
simulation/verilog/aldec.
3. Run the provided run_riviera.tcl script. This file compiles the design and runs the simulation automati‐
cally. It provides a pass/fail indication on completion.
Timing Violation
After you create a new project, the Quartus II software generates a Quartus II Settings File (.qsf). Add the
following assignments to .qsf to avoid timing violation from the synchronizers.
set_instance_assignment -name GLOBAL_SIGNAL OFF -to *|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out
Compiling the SDI II IP Core Design
To compile your design, click Start Compilation on the Processing menu in the Quartus II software. You
can use the generated .qip file to include relevant files into your project.
You can find the design examples of the SDI II IP core in the <variation name>_example_design/
example_design/<variation name>_example_design directory. For the design example illustrations, refer
to the Design Examples section.
To create a new project using the generated design example, follow the steps in the Creating a New
Note:
Quartus II Project section and add the design example .qip file in step 4.
Related Information
• Creating a New Quartus II Project on page 3-2
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• Design Examples on page 3-9
Each design example provided with the SDI II IP core is synthesizable.
• Quartus II Help
More information about compilation in Quartus II software.
Programming an FPGA Device
After successfully compiling your design, program the targeted Altera device with the Quartus II
Programmer and verify the design in hardware.
For instructions on programming the FPGA device, refer to the Device Programming section in volume 3
of the Quartus II Handbook.
Related Information
Device Programming
Design Reference
This section describes the SDI II IP core parameters, signals, and files to help you configure your design.
This section includes detailed description about the SDI II IP core design examples.
Programming an FPGA Device
3-5
SDI II IP Core Getting Started
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3-6
SDI II IP Core Parameters
SDI II IP Core Parameters
Table 3-2: SDI II IP Core Parameters
Parameter Value Description
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Configuration
Options
Video standard
SD-SDI, HD-SDI,
3G-SDI, HD-SDI
dual link, Dual
rate (up to HDSDI), Triple rate
(up to 3G-SDI),
Multi rate (up to
12G-SDI)
SD interface bit
10, 20 Selects the SD interface bit width. Only applicable
width
Direction Birectional,
Receiver,
Transmitter
Sets the video standard.
• SD-SDI—disables option for line insertion
and extraction, and CRC generation and
extraction
• HD-SDI—enables option for in line insertion
and extraction and CRC generation and
extraction
• Dual, triple or multi rate SDI—includes the
processing blocks for both SD-SDI and HDSDI standards. Logics for bypass paths and to
automatically switch between the input
standards are included.
Note:
SD-SDI and Dual rate (up to HDSDI) options are not available for
Arria 10 devices. Multi rate (up to
12G-SDI) option is not available for
Arria V, Cyclone V, and Stratix V
devices.
for dual standard and triple standard.
Sets the port direction. The selection enables or
disables the receiver and transmitter supporting
logic appropriately.
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Transceiver and/
or Protocol
Combined,
Transceiver,
Protocol
• Bidirectional—instantiates both the SDI
transmitter and receiver.
• Receiver—instantiates the SDI receiver
• Transmitter—instantiates the SDI transmitter.
Selects the components.
• Transceiver—includes tx/rx_phy_mgmt/phy_
adapter and hard transceiver. This option is
useful if you want to use the same transceiver
component to support both SDI and ASI IP
cores.
• Protocol.
Note: This option is available only for Arria
V, Cyclone V, and Stratix V devices.
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SDI II IP Core Parameters
Parameter Value Description
3-7
Transceiver
Options
(2)
Dynamic Tx clock
switching
Transceiver
reference clock
frequency
TX PLL type
Off, Tx PLLs
switching, Tx PLL
reference clocks
switching
• Off: Disable dynamic switching
• Tx PLLs switching: Instantiates two PLLs,
each with a reference input clock
• Tx PLL reference clocks switching: Instanti‐
ates a PLL with two reference input clocks.
Note: This option is not available if you
select ATX PLL.
Turn on this option to allow dynamic switching
between 1 and 1/1.001 data rates.
Note: This option is only available for TX or
bidirectional ports, and all video
standards except SD-SDI.
148.5/148.35
MHz,
74.25/74.175
MHz,
Selects the transceiver reference clock frequency.
The 74.25/74.175 MHz option is available only
for HD-SDI and HD-SDI dual link video
standards, and if you select CMU as the TX PLL.
CMU, ATX Selects the transmitter PLL for TX or bidirec‐
tional ports.
ATX PLL is useful for bidirectional channels—
you can use the ATX PLL as the transmitter PLL
instead of the CMU PLL from another channel.
ATX PLL is only available in the Stratix V and
Arria V GZ families
Increase error
tolerance level
On, Off • On: Error tolerance level = 15
• Off: Error tolerance level = 4
Turn on this option to increase the error
tolerance level for consecutive missed end of
Receiver
Options
active videos (EAVs), start of active videos
(SAVs), or erroneous frames.
CRC error output On, Off • On: CRC monitoring (Not applicable for SD-
SDI mode)
• Off: No CRC monitoring (saves logic)
(2)
These options are available only for Arria V, Cyclone V, and Stratix V devices.
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SDI II IP Core Parameters
Parameter Value Description
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Transmitter
Options
Extract Payload
ID (SMPTE
352M)
Convert HD-SDI
dual link to 3GSDI (level B)
Convert 3G-SDI
(level B) to HDSDI dual link
Insert payload ID
(SMPTE 352M)
On, Off • On: Extract payload ID
• Off: No payload ID extraction (saves logic)
It is compulsory to turn on this option for 3GSDI, HD SDI dual link, and triple standard
modes. The extracted payload ID is required for
consistent detection of the 1080p format.
On, Off • On: Converts to level B (2 × SMPTE 292M
HD-SDI mapping, including SMPTE 372M
dual link mapping) for HD-SDI dual link
receiver output.
• Off: No conversion
This option is only available for HD-SDI dual
link receiver.
On, Off • On: Converts to HD-SDI dual link (direct
image format mapping) for 3G-SDI receiver
output.
• Off: No conversion
This option is only available for 3G-SDI receiver.
On, Off • On: Insert payload ID
• Off: No payload ID insertion (saves logic)
TX PLL type CMU, ATX Sets the transmitter PLL type for transmit and
Example
Design
Dynamic Tx
clocks switching
Options
(3)
(3)
These options are available only for Arria 10 devices.
Off, Tx PLLs
switching, Tx PLL
reference clocks
switching
bidirectional ports.
ATX PLL is useful for bidirectional channels—
you can use the ATX PLL as the transmitter PLL
instead of the CMU PLL from another channel.
• Off: Disable dynamic switching
• Tx PLLs switching: Instantiates two PLLs,
each with a reference input clock
• Tx PLL reference clocks switching: Instanti‐
ates a PLL with two reference input clocks.
Turn on this option to allow dynamic switching
between 1 and 1/1.001 data rates.
Note: This option is only available for TX or
bidirectional ports, and all video
standards except SD-SDI.
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SDI II IP Core Component Files
SDI II IP Core Component Files
Table 3-3: Generated Files
Table below describes the generated files and other files that might be in your project directory. The names and
types of files vary depending on whether you create your design with VHDL or Verilog HDL.
Extension Description
<variation name>.v or .sv An IP core variation file, which defines a Verilog HDL description of the
custom IP core. Instantiate the entity defined by this file inside your design.
Include this file when compiling your design in the Quartus II software.
<variation name>.sdc Contains timing constraints for your SDI variation.
<variation name>.qip Contains Quartus II project information for your IP core variations.
<variation name>.tcl Tcl script file to run in Quartus II software.
Design Examples
Each design example provided with the SDI II IP core is synthesizable.
3-9
Design Examples for Arria 10 Devices
The figure below illustrates the generated design example entity and simulation testbench for Arria 10
devices. This design example consists of two SDI channels, a video pattern generator, a reconfiguration
controller, and a loopback path.
The IP core configures the device under test (DUT) block according to your parameterization. For
example, if you choose to generate an SDI RX, the software instantiates an SDI TX block to serve as a
video source.
The loopback block (SDI duplex) is always instantiated in the design example for parallel loopback
demonstrations.
The PHY adapter in the generated example design is not included in the figure below so that you can
observe how the signals are physically connected without the adapter. You may bypass the adapter in your
own design to make the design simpler.
For Arria 10 devices, the transceiver is no longer wrapped inside the IP core, and the TX PLL is no longer
wrapped inside the Transceiver PHY. You must generate these blocks separately in the example design.
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Loopback
Path
Ch0 Loopback
(SDI TX + RX)
Arria 10 Native
PHY (Duplex)
Ch0 RX
Transceiver
Reset Controller
Pattern
Generator
Ch1 DUT
(SDI TX)
Arria 10 Native
PHY (TX)
Ch1 RX
Transceiver
Reset Controller
Ch0 TX
Transceiver
Reset Controller
Ch1 TX
Transceiver
Reconfiguration
Controller
Ch0 TX
PLL
Ch1 Test
(SDI RX)
Arria 10 Native
PHY (RX)
Ch0 TX
Transceiver
Reset Controller
Ch0 Duplex
Transceiver
Reconfiguration
Controller
Ch0 TX
PLL
Ch1 RX
Transceiver
Reconfiguration
Controller
TX Checker
RX
Checker
Test
Control
Testbench
Example Design
Data
Control
SDI II IP Core
Arria 10 Native PHY IP Core
Transceiver PHY Reset Controller IP Core
Arria 10 Transceiver CMU/ATX PLL IP Core
3-10
Design Examples for Arria 10 Devices
Figure 3-1: Design Example Entity and Simulation Testbench for Arria 10 Devices
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This design generates two transceiver PHY reset controllers—one for TX and one for RX. These reset
controllers are connected to the transceiver to control the reset sequence. The PHY adapter controls the
rx_manual and rx_is_lockedtodata input signals of the reset controller. If you want to bypass the PHY
adapter, you must copy the assignment of these input signals in the sdi_ii_phy_adapter.v file to your design.
The table below describes how you should connect the input signals.
Table 3-4: Connecting Input Signals
Input Signal Connection
rx_manual Connect this signal to the rx_ready port of the PHY reset controller to
rx_is_lockedtodata Connect this signal to an output from a multiplexer between rx_is_
Note: The Transceiver Reconfiguration Controller that was used in the design examples for Arria V,
Cyclone V, and Stratix V devices are not applicable for Arria 10 devices. The reconfiguration
interface is now integrated into the transceiver. Each transceiver should pair with a reconfiguration
controller if it requires reconfiguration.
Design Examples for Arria V, Cyclone V, and Stratix V Devices
avoid any disturbance from short interference after the receiver is
locked.
lockedtoref and rx_is_lockedtodata ports from the transceiver,
with the rx_set_locktoref acting as the selector. The receiver operates
in locktoref mode when it receives SD video data. rx_is_lockedto-
data is not stable in this mode.
3-11
Design Examples for Arria V, Cyclone V, and Stratix V Devices
Figure below illustrates the generated design example entity and simulation testbench for Arria V,
Cyclone V, and Stratix V devices. This design example consists of a video pattern generator, transceiver
reconfiguration controller, reconfiguration management, loopback path, and various SDI blocks
occupying two transceiver channels.
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Loopback
Path
Ch0
Loopback
(SDI Duplex)
Reconfiguration
Management/Router
Ch1 Test
(SDI RX)
Ch1 DUT
(SDI TX)
Transceiver
Reconfiguration
Controller
Video Pattern
Generator
TX
Checker
RX
Checker
Test
Control
Data
Control
SDI II IP Core
Design Example
Testbench
3-12
Design Examples for Arria V, Cyclone V, and Stratix V Devices
Figure 3-2: Design Example Entity and Simulation Testbench
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