Altera SDI HSMC User Manual
SDI HSMC Reference Manual
101 Innovation Drive
San Jose, CA 95134
www.altera.com
Document Version: 1.0
Document Date: July 2009
Copyright © 2009 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other
words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other
countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty,
but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of
any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of
device specifications before relying on any published information and before placing orders for products or services.
MNL-01046-1.0
Contents
Chapter 1. Overview
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
Board Component Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
Development Board Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2
SDI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2
AES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3
Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3
Handling the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4
Chapter 2. Board Components
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
Board Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
Supported Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4
Configuration, Status, and Setup Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5
Status Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5
Clock Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6
SDI Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6
Host Board Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–10
Loop Back Reference Clock From SDI Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–11
Studio Reference Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–11
Studio Reference Video Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–11
AES3 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–11
Audio/Video Input and Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14
SDI RX Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14
SDI TX Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–15
AES3 RX Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17
AES3 TX Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17
General User Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18
Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18
Components and Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–19
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–24
Restoring Board to Factory Defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–25
Additional Information
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1
How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1
Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–2
© July 2009 Altera Corporation SDI HSMC Reference Manual
iv
SDI HSMC Reference Manual © July 2009 Altera Corporation
General Description
This manual provides information about the hardware features of the serial digital
interface (SDI) high-speed mezzanine card (HSMC). You can use the SDI HSMC to
design and implement SDI and Audio Engineering Society (AES) systems based on
transceiver-supported host boards with HSMC interfaces. Altera
transceiver supported host boards with high speed serial HSMC interfaces, including
the Stratix II
®
GX, Arria® GX, Stratix IV GX, and Arria II GX device families.
This manual includes detailed pinout information that enables you to create custom
FPGA designs on host adapters with HSMC interfaces.
Board Component Blocks
The SDI HSMC features the following major component blocks:
■ Power
1. Overview
®
offers several
■ High frequency switching regulator (LT3480) for 12-V to 5-V power conversion
■ Three linear regulators (LT3080) for 5-V to 3.3-V low noise power conversion
■ FDTIM analysis for power distribution network (PDN) decoupling
■ SDI
■ Two SDI receive (RX) channels with SDI cable equalizers (LMH0344)
■ Two SDI transmit (TX) channels with SDI cable tri-speed drivers (LMH0302)
■ Two 75-Ω BNC SDI RX interfaces
■ Two 75-Ω BNC SDI TX interfaces
■ AES3
■ Two RS422 transceivers (LTC2851) for AES3 TX and AES3 RX channels
■ Two 75-Ω BNC AES3 RX interfaces
■ Two 75-Ω BNC AES3 TX interfaces
■ Clocks
■ One SDI multi-frequency VCXO femto clock video PLL (ICS810001-21)
■ 98.304 MHz/90.3168 MHz/122.88 MHz/112.896 MHz voltage-controlled
crystal oscillator (VCXO) based phase-locked loop (PLL) (ICS275-22)
■ One LVPECL differential clock buffer (SY58012) with two differential
outputs—HSMC and SMA
■ Four digital audio isolation transformers
■ One multi-format video sync separator (LMH1981)
■ One HSMC connector interface using high speed transceiver channels
© July 2009 Altera Corporation SDI HSMC Reference Manual
1–2 Chapter 1: Overview
Board Component Blocks
Figure 1–1 shows the SDI HSMC connected to an Altera FPGA development board.
f Refer to the Audio Video Development Kit, Stratix IV GX Edition User Guide for an
example of connecting the SDI HSMC to a host board.
f For detailed information about the board components and interfaces of the Stratix IV
GX FPGA development board, refer to the Stratix IV GX FPGA Development Board
Reference Manual.
Figure 1–1. SDI HSMC Connected to the Stratix IV GX FPGA Development Board
SDI HSMC
Stratix IV GX FPGA Development Board
Development Board Block Diagram
Figure 1–2 shows the functional block diagram of the SDI HSMC. The board has three
distinct areas of interest:
■ SDI
■ AES
■ Clocking
SDI
The SDI includes two high-speed output interfaces from the HSMC to the cable
drivers and to two single-ended 75-Ω BNC output interfaces. There are also two
receive paths which input signals to two 75-Ω BNC connectors to receive equalizers.
The differential signals are then output to the HSMC connector.
SDI HSMC Reference Manual © July 2009 Altera Corporation
Chapter 1: Overview 1–3
Board Component Blocks
AES
The AES includes two input and two output interfaces. The interface to the host board
is 2.5-V CMOS signaling. The differential RS 422 line transceivers convert the
single-ended signal to balanced differential outputs which drive the audio isolation
transformers.
Clocking
Clocking is the third area of interest on the board. Clocking for the SDI interfaces is
supported by a dual SDI multi-frequency VCXO femto clock video PLL
(ICS810001-21) from Integrated Device Technology (IDT). The chipset supports
various inputs related to common video signals from the bit rate clocks or horizontal
sync signals. The output of the chipset is fed into a differential clock buffer. The
differential signal is then output to the HSMC connector and SMA connectors. Two
crystal oscillators are used in this chipset — 27 MHz and 27/1.001 MHz (26.973 MHz).
The PLL is used to supply 74.25 MHz or 148.5 MHz reference clocks to the transceiver
on the host board.
Clocking for the AES interfaces is implemented by using the VCXO PLL (ICS275-22),
a pre-programmed IDT part. As applied in the AES interface, a 16.384-MHz crystal is
used in the VCXO section and followed by a PLL to produce the supported
frequencies of 98.304 MHz, 90.3168 MHz, 122.88 MHz, and 112.896 MHz.
Table 1–1 shows the frequency setup of the VCXO PLL.
Table 1–1. Frequency Setup of the VCXO PLL
Frequency (MHz)
S [2:0]
000 98.304 98.304
001 90.3168 90.3168
010 122.88 122.88
011 112.896 112.896
100 98.304 122.88
101 90.3168 112.896
110 98.304 90.3168
111 122.88 112.896
Pin 5 Pin 6
© July 2009 Altera Corporation SDI HSMC Reference Manual
1–4 Chapter 1: Overview
TX 1 DATA
SDI T X 1
EQ 1 SDI RX 1
Video Sync
Separator
Video In
148.5 MHz
HSYNC
VSYNC
Buffer
PLL
PLL Ref / Rec CLK
TX 2 DATA
SDI T X 2
RX 1 DATA
EXT CLK
IN
SDI CLK
OUT (P)
DRV 1
DRV 2
EQ 2 SDI RX 2
RX 2 DATA
AES RX 1
AES TX DATA
AES TX 1
AES RX DAT A
AES Passive
Circuit
AES Passive
Circuit
AES RX 2
AES TX DATA
AES TX 2
AES RX DAT A
AES Passive
Circuit
AES Passive
Circuit
FRAME
SDI CLK
OUT (N)
TX
RX
TX
RX
AES Loop
Filter
VCXO
xtal
AES CLK
SMA
16.384 MHz
AES CLK
down
up
Handling the Board
Figure 1–2. SDI HSMC Block Diagram
Handling the Board
c Static Discharge Precaution: Without proper anti-static handling, the board can be
When handling the board, it is important to observe the following precaution:
damaged. Therefore, use anti-static handling precautions when touching the board.
The SDI HSMC must be stored between –40° C and 100° C. The recommended
operating temperature is between 0° C and 55° C.
SDI HSMC Reference Manual © July 2009 Altera Corporation
Introduction
1 A complete set of schematics, physical layout database, and fabrication files for the
f For an example on powering up the board and installing the demonstration software,
2. Board Components
This chapter introduces the important components on the SDI HSMC and provides
their operational and connectivity details.
board is shipped with the board and also resides in the Audio Video Development Kit
Stratix IV GX Edition installation directory.
refer to the Audio Video Development Kit, Stratix IV GX Edition User Guide.
This chapter consists of the following sections:
■ “Board Overview”
■ “Supported Protocols” on page 2–4
■ “Configuration, Status, and Setup Elements” on page 2–5
■ “Clock Circuitry” on page 2–6
■ “General User Input/Output” on page 2–18
■ “Components and Interfaces” on page 2–19
■ “Power Supply” on page 2–24
■ “Restoring Board to Factory Defaults” on page 2–25
Board Overview
This section provides an overview of the SDI HSMC, including an annotated board
image and component descriptions. Figure 2–1 shows the top-view of the SDI HSMC,
including its components and interface locations.
© July 2009 Altera Corporation SDI HSMC Reference Manual
2–2 Chapter 2: Board Components
SMA SDI
Clock Input (J16)
LVPECL
Differential
Clock
Buffer
(J62)
Equalizer Bypass Jumper (J7)
High Frequency
Switching
Regulator (U5)
AES VCXO PLL (U3)
SDI Input
Channel 2 (J2)
Multi-format Video
Sync Separator (U4)
SMA SDI
Clock
Output
(P)
(J17)
SDI
Multi-frequency
VCXO
Femto Clock
Video PLL (U6)
SDI Cable
Tri-speed Driver (U1)
AES Output
Channel 1 (J3)
AES Input
Channel 1 (J10)
AES Output
Channel 2 (J14)
AES Input
Channel 2 (J15)
SDI Output
Channel 2 (J1)
Carrier Detect — Mute Jumper (J4)
SDI Input
Channel 1 (J9)
Carrier Detect — Mute Jumper (J6)
Equalizer Bypass Jumper (J5)
SDI Output
Channel 1 (J8)
SDI Cable
Tri-speed Driver (U2)
SMA SDI
Clock
Output
(N)
(J18)
SMA AES
Clock Output (J12)
Board Overview
Figure 2–1. Top View of the SDI HSMC
Figure 2–2 shows the bottom view of the SDI HSMC.
Figure 2–2. Bottom View of the SDI HSMC (HSMC Connector View)
SDI Cable
Equalizer (U8)
RS422 Transceiver (U9)
Equalizer (U10)
Linear Regulator (U11)
RS422 Transceiver (U16)
SDI Cable
Linear
Regulator
(U12)
Linear
Regulator
(U13)
Single Gate
Tr i-state
Buffer (U14)
Single Gate
Tr i-state
Buffer (U15)
HSMC
Connector (J19)
SDI HSMC Reference Manual © July 2009 Altera Corporation
Chapter 2: Board Components 2–3
Board Overview
Table 2–1 describes the components and lists their corresponding board references.
Table 2–1. SDI HSMC Components (Part 1 of 2)
Board Reference Name Description
Devices
U1, U2 SDI cable tri-speed driver Input signal to this driver is from the HSMC high-speed
serializer/deserializer (SERDES) section. The DC blocking caps are in
series with the connector and the integrated circuit (IC).
U3 AES VCXO PLL Programmed VCXO from Integrated Computer Solutions (ICS) to
produce frequencies of 98.304 MHz, 90.3168 MHz, 122.88 MHz, and
112.896 MHz.
U4 Multi-format video sync
separator
U5 High frequency switching
regulator
U6 SDI multi-frequency VCXO
Signals ODDEVEN, VFORMAT, VSYNC, HSYNC from this device are
available to the host board through the HSMC connector.
IC switching power supply configured for a 5 V output. The input
voltage is 12 V from the HSMC connector.
Low jitter femto clock, multi-crystal SDI video PLL.
femto clock video PLL
U7 LVPECL differential clock
buffer
Differential clock signals available at the SMA outputs and HSMC
connector.
U8, U10 SDI cable equalizer Equalizes data transmitted over the cable.
U9, U16 RS422 transceiver Used as a differential line driver and receiver for the AES interface.
U11, U12, U13 Linear regulator Regulator with an input of 5 V and output of 3.3 V.
U14, U15 Single gate tri-state buffer For AES VCXO control.
SDI Inputs/Outputs
J1 SDI output channel 2 Output is through a BNC connector driven from the SDI cable driver.
J8 SDI output channel 1 Output is through a BNC connector driven from the SDI cable driver.
J2 SDI input channel 2 The signal from this channel is input to a cable equalizer. This equalizer
can be bypassed.
J9 SDI input channel 1 The signal from this channel is input to a cable equalizer. This equalizer
can be bypassed.
AES Inputs/Outputs
J3 AES output channel 1 Transformer-coupled output with 75-Ω driver impedance.
J10 AES input channel 1 A 75-Ω transformer coupled with AES input channel.
J14 AES output channel 2 Transformer-coupled output with 75-Ω driver impedance.
J15 AES input channel 2 A 75-Ω transformer coupled with AES input channel.
Clocks
J16 SMA SDI clock input This signal is input to the SDI clock PLL (CMOS). There is a 49.9-Ω
termination to ground at the pin.
J17 SMA SDI clock output (P) An ECL compatible output. The ECL bias includes a 130-Ω pull-up to
3.3 V and a 82-Ω pull-down to ground.
J18 SMA SDI clock output (N) An ECL compatible output. The ECL bias includes a 130-Ω pull-up to
3.3 V and a 82-Ω pull-down to ground.
J12 SMA AES clock output This signal is output to the SMA AES clock (CMOS) and has a 33-Ω
series termination resistor.
© July 2009 Altera Corporation SDI HSMC Reference Manual
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