Altera SDI Audio IP Cores User Manual
SDI Audio IP Cores User Guide
Last updated for Altera Complete Design Suite: 14.0
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SDI Audio IP Cores User Guide
Contents
SDI Audio IP Overview.......................................................................................1-1
SDI Audio IP Getting Started.............................................................................2-1
SDI Audio IP Functional Description................................................................3-1
Installing and Licensing IP Cores..............................................................................................................2-1
OpenCore Plus IP Evaluation........................................................................................................2-1
IP Catalog and Parameter Editor...............................................................................................................2-2
Specifying IP Core Parameters and Options................................................................................2-3
Simulating Altera IP Cores in other EDA Tools.....................................................................................2-4
SDI Audio Embed IP Core.........................................................................................................................3-1
SDI Audio Embed Parameters.......................................................................................................3-2
SDI Audio Extract IP Core.........................................................................................................................3-4
SDI Audio Extract Parameters.......................................................................................................3-5
SDI Clocked Audio Input IP Core.............................................................................................................3-6
SDI Audio Clocked Audio Input Parameters..............................................................................3-6
SDI Clocked Audio Output IP Core..........................................................................................................3-7
SDI Audio Clocked Audio Output Parameters...........................................................................3-7
AES Format...................................................................................................................................................3-7
Avalon-ST Audio Interface.........................................................................................................................3-8
Instantiating the SDI Audio IP Cores.....................................................................................................3-10
Simulating the Testbench.........................................................................................................................3-10
Guidelines.......................................................................................................................................3-11
SDI Audio IP Interface Signals...........................................................................4-1
SDI Audio IP Registers........................................................................................5-1
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SDI Audio Embed Signals...........................................................................................................................4-1
SDI Audio Extract Signals...........................................................................................................................4-5
SDI Audio Clocked Input Signals..............................................................................................................4-8
SDI Audio Clocked Output Signals...........................................................................................................4-9
SDI Audio IP Register Interface Signals.................................................................................................4-10
SDI Audio IP Cores User Guide
SDI Audio Embed Registers.......................................................................................................................5-1
SDI Audio Extract Registers.......................................................................................................................5-4
SDI Clocked Audio Input Registers..........................................................................................................5-8
SDI Clocked Audio Output Registers.......................................................................................................5-9
TOC-3
SDI Audio IP Design Example............................................................................6-1
Components of Design Example...............................................................................................................6-1
SDI Transmitter P0..........................................................................................................................6-2
SDI Duplex........................................................................................................................................6-2
Audio Extract....................................................................................................................................6-2
AES Input Module...........................................................................................................................6-2
AES Output Module........................................................................................................................6-2
Audio Embed P0/P1........................................................................................................................6-2
Video Pattern Generator P0/P1.....................................................................................................6-2
Audio Pattern Generator................................................................................................................6-2
Ancillary Data Insertion P0/P1......................................................................................................6-2
Transceiver Dynamic Reconfiguration Control Logic...............................................................6-3
Hardware and Software Requirements.....................................................................................................6-3
Running the Design Example.....................................................................................................................6-4
Transmit SD-SDI with Embedding of Audio Group 1...............................................................6-5
Transmit HD-SDI with Embedding of Audio Group 1 and 2...................................................6-5
Transmit 3G-SDI Level A with Embedding of Audio Group 1, 2 and 3..................................6-6
Transmit 3G-SDI Level B with Embedding of Audio Group 1, 2, 3 and 4..............................6-6
Additional Information......................................................................................7-1
Document Revision History.......................................................................................................................7-1
How to Contact Altera................................................................................................................................7-1
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SDI Audio IP Overview
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The Altera®SDI Audio MegaCore®functions ease the development of video and image processing designs.
For some instances, you combine the audio and video into one digital signal, and at other times you process
the audio and video signals separately.
The SDI Audio IP cores are part of the MegaCore IP Library, which is distributed with the Quartus®II
software and downloadable from the Altera website at www.altera.com.
You can use the following cores to embed, extract or convert audio:
• Audio Embed IP core
• Audio Extract IP core
• Clocked Audio Input IP core
• Clocked Audio Output IP core
You can instantiate the SDI Audio IP cores with the SDI and SDI II IP cores, and configure each Audio IP
core at run time using an Avalon-MM slave interface.
Table 1-1: Brief Information About the SDI Audio IP Cores
14.0Version
DescriptionItem
June 2014Release Date
Release
Informa-
IP-SDIOrdering Code
tion
00E6Product ID(s)
6AF7Vendor ID
Device FamilyIP Core
Information
Arria®II GX, Arria V, Cyclone®IV GX, Cyclone V, and Stratix®IV
GX, and Stratix V FPGA device families.
Refer to the What’s New in Altera IP page of the Altera website for
detailed information.
©
2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words
and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other
words and logos identified as trademarks or service marks are the property of their respective holders as described at
www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with
Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes
no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly
agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
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SDI Audio IP Overview
Related Information
• Serial Digital Interface (SDI) IP Core User Guide
For information about SDI IP core.
• SDI II IP Core User Guide
For information about SDI II IP core.
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SDI Audio IP Overview
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acds
quartus - Contains the Quartus II software
ip - Contains the Altera IP Library and third-party IP cores
altera - Contains the Altera IP Library source code
<IP core name> - Contains the IP core source files
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SDI Audio IP Getting Started
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Installing and Licensing IP Cores
The Quartus II software includes the Altera IP Library. The library provides many useful IP core functions
for production use without additional license. You can fully evaluate any licensed Altera IP core in simulation
and in hardware until you are satisfied with its functionality and performance. Some Altera IP cores, such
as MegaCore®functions, require that you purchase a separate license for production use. After you purchase
a license, visit the Self Service Licensing Center to obtain a license number for any Altera product.
Figure 2-1: IP Core Installation Path
Note:
The default IP installation directory on Windows is <drive>:\altera\<version number>; on Linux it
is <home directory>/altera/ <version number>.
Related Information
• Altera Licensing Site
• Altera Software Installation and Licensing Manual
OpenCore Plus IP Evaluation
Altera's free OpenCore Plus feature allows you to evaluate licensed MegaCore IP cores in simulation and
hardware before purchase. You need only purchase a license for MegaCore IP cores if you decide to take
your design to production. OpenCore Plus supports the following evaluations:
• Simulate the behavior of a licensed IP core in your system.
• Verify the functionality, size, and speed of the IP core quickly and easily.
• Generate time-limited device programming files for designs that include IP cores.
©
2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words
and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other
words and logos identified as trademarks or service marks are the property of their respective holders as described at
www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with
Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes
no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly
agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
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IP Catalog and Parameter Editor
• Program a device with your IP core and verify your design in hardware
OpenCore Plus evaluation supports the following two operation modes:
• Untethered—run the design containing the licensed IP for a limited time.
• Tethered—run the design containing the licensed IP for a longer time or indefinitely. This requires a
connection between your board and the host computer.
All IP cores using OpenCore Plus in a design time out simultaneously when any IP core times out.Note:
IP Catalog and Parameter Editor
The Quartus II IP Catalog (Tools > IP Catalog) and parameter editor help you easily customize and integrate
IP cores into your project. You can use the IP Catalog and parameter editor to select, customize, and generate
files representing your custom IP variation.
The IP Catalog automatically displays the IP cores available for your target device. Double-click any IP core
name to launch the parameter editor and generate files representing your IP variation. The parameter editor
prompts you to specify your IP variation name, optional ports, architecture features, and output file generation
options. The parameter editor generates a top-level .qsys or .qip file representing the IP core in your project.
Alternatively, you can define an IP variation without an open Quartus II project. When no project is open,
select the Device Family directly in IP Catalog to filter IP cores by device.
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Note:
The IP Catalog is also available in Qsys (View > IP Catalog). The Qsys IP Catalog includes exclusive
system interconnect, video and image processing, and other system-level IP that are not available in
the Quartus II IP Catalog.
Use the following features to help you quickly locate and select an IP core:
• Filter IP Catalog to Show IP for active device family or Show IP for all device families.
• Search to locate any full or partial IP core name in IP Catalog. Click Search for Partner IP, to access
partner IP information on the Altera website.
• Right-click an IP core name in IP Catalog to display details about supported devices, installation location,
and links to documentation.
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Search and filter IP for your target device
Double-click to customize, right-click for information
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Figure 2-2: Quartus II IP Catalog
Specifying IP Core Parameters and Options
2-3
Note:
The IP Catalog and parameter editor replace the MegaWizard™Plug-In Manager in the Quartus II
software. The Quartus II software may generate messages that refer to the MegaWizard Plug-In
Manager. Substitute "IP Catalog and parameter editor" for "MegaWizard Plug-In Manager" in these
messages.
Specifying IP Core Parameters and Options
Follow these steps to specify IP core parameters and options.
1. In the IP Catalog (Tools > IP Catalog), locate and double-click the name of the IP core to customize.
The parameter editor appears.
2. Specify a top-level name for your custom IP variation. This name identifies the IP core variation files in
your project. If prompted, also specify the target Altera device family and output file HDL preference.
Click OK.
3. Specify parameters and options for your IP variation:
• Optionally select preset parameter values. Presets specify all initial parameter values for specific
applications (where provided).
• Specify parameters defining the IP core functionality, port configurations, and device-specific features.
• Specify options for generation of a timing netlist, simulation model, testbench, or example design
(where applicable).
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Simulating Altera IP Cores in other EDA Tools
• Specify options for processing the IP core files in other EDA tools.
4. Click Finish or Generate to generate synthesis and other optional files matching your IP variation
specifications. The parameter editor generates the top-level .qip or .qsys IP variation file and HDL files
for synthesis and simulation. Some IP cores also simultaneously generate a testbench or example design
for hardware testing.
5. To generate a simulation testbench, click Generate > Generate Testbench System. Generate Testbench
System is not available for some IP cores that do not provide a simulation testbench.
6. To generate a top-level HDL example for hardware verification, click Generate > HDL Example.
Generate > HDL Example is not available for some IP cores.
The top-level IP variation is added to the current Quartus II project. Click Project > Add/Remove Files in
Project to manually add a .qip or .qsys file to a project. Make appropriate pin assignments to connect ports.
Simulating Altera IP Cores in other EDA Tools
The Quartus II software supports RTL- and gate-level design simulation of Altera IP cores in supported
EDA simulators. Simulation involves setting up your simulator working environment, compiling simulation
model libraries, and running your simulation.
You can use the functional simulation model and the testbench or example design generated with your IP
core for simulation. The functional simulation model and testbench files are generated in a project
subdirectory. This directory may also include scripts to compile and run the testbench. For a complete list
of models or libraries required to simulate your IP core, refer to the scripts generated with the testbench.
You can use the Quartus II NativeLink feature to automatically generate simulation files and scripts.
NativeLink launches your preferred simulator from within the Quartus II software.
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Figure 2-3: Simulation in Quartus II Design Flow
Note:
Altera IP supports a variety of simulation models, including simulation-specific IP functional
simulation models and encrypted RTL models, and plain text RTL models. These are all cycle-accurate
models. The models support fast functional simulation of your IP core instance using industrystandard VHDL or Verilog HDL simulators. For some cores, only the plain text RTL model is
generated, and you can simulate that model. Use the simulation models only for simulation and not
for synthesis or any other purposes. Using these models for synthesis creates a nonfunctional design.
Related Information
Simulating Altera Designs
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SDI Audio IP Functional Description
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The following sections describe the block diagrams and components for the SDI Audio IP cores.
• Audio Embed IP core
• Audio Extract IP core
• Clocked Audio Input IP core
• Clocked Audio Output IP core
SDI Audio Embed IP Core
The SDI Audio Embed Audio IP core embeds audio into the SD-, HD-, and 3G-SDI video standards.
The format of the embedded audio is in accordance with the following standards:
• SMPTE272M-ABCD standard for SD-SDI
• SMPTE299M standard for HD-SDI
• SMPTE299M standard for 3G-SDI (provisional)
This IP core supports AES audio format for 48-kHz sampling rate
This figure shows a block diagram of the SDI Audio Embed IP core.
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©
2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words
and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other
words and logos identified as trademarks or service marks are the property of their respective holders as described at
www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with
Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes
no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly
agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
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Avalon-ST Audio to Audio Embed with Avalon Only
FIFO FIFO FIFO FIFO FIFO FIFO FIFO FIFO
Audio
Embedder
SD/HD/3G-SDI SD/HD/3G-SDI
Avalon-MM
Audio Embed or Audio Embed with Avalon
SD/HD Audio Embedder
Packet
Creation
Packet
Distribution
Channel
Status RAM
Register Interface
3-2
SDI Audio Embed Parameters
Figure 3-1: SDI Audio Embed IP Core Block Diagram
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The SDI Audio Embed IP core embeds up to 16 channels or 8 channel pairs. The input audio can be any of
the sample rates permitted by the SMPTE272M-ABCD and SMPTE299M standards; synchronous to the
video. If you want to embed audio pairs together in a sample audio group, the audio pairs must be synchronous
with each other.
The SDI Audio Embed IP core consists of the following components:
• An encrypted audio embedder core
• A register interface block that provides support for an Avalon-MM control bus
The audio embedder accepts the audio in AES format, and stores each channel pair in an input FIFO buffer.
As the embedder places the audio sample in the FIFO buffer, it also records and stores the video clock phase
information.
When accepting the audio in AES format, the SDI Audio Embed IP core does one of the following operations:
• maintains the channel-status details
• replaces the channel-status details with the default or the RAM versions
SDI Audio Embed Parameters
The following table lists the parameters for the SDI Audio Embed IP core.
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Table 3-1: SDI Audio Embed Parameters
SDI Audio Embed Parameters
DescriptionValueParameter
3-3
supported audio
groups
Interface
Frequency of fix_
clk
24-bit support
existing audio
1, 2, 3, 4Number of
On or OffAsync Audio
0, 24.576, 25, 50, 100,
200
On or OffInclude SD-SDI
0,1, 2Cleanly remove
Specifies the maximum number of audio groups supported.
Each audio group consists of 4 audio channels (2 channel pairs)
. You must specify all the four channels to the same sample
frequencies.
Turn on to enable the Asynchronous input.
In this mode, the audio clock provides higher than 64* sample
rate.
Sets the expected frequency of the fix_clk input; used as
frequency reference when detecting the difference between video
rate of 1/1.000 or 1/1.001.
Setting this parameter to 0 drives fix_clk low.
Enables the embedding of SD-SDI Extended Data Packets (EDP)
for each audio group.
Enables the removal of existing embedded audio data.
When set to 1, the system requires extra storage to delay the video
and remove any existing audio from SD-SDI, HD-SDI, or 3GSDI Level A standard.
When set to 2, the system includes extra storage to remove the
existing audio from 3G-SDI Level B standard.
RAM
wave generator
ST interface
Select 0 to turn off this parameter.
0,1, 2Channel status
Enables storage of the custom channel status data.
Select 1 to generate a single channel status RAM, or 2 to generate
separate RAMs for each input audio pair.
Select 0 to turn off this parameter.
On or OffFrequency sine
Turn on to enable a four-frequency sine wave generator.
You can use the four-frequency sine wave generator as a test
source for the audio embedder.
On or OffInclude clock
Turn on to enable a 48-kHz pulse generator synchronous to the
video clock. You can use the 48-kHz pulse generator to request
data from a sample rate convertor.
When you turn on the Frequency Sine Wave Generator
parameter, the core automatically includes this pulse generator.
On or OffInclude Avalon-
Turn on to include the SDI Clocked Audio Output IP core.
When you turn on this parameter, the Avalon-ST interface signals
appear at the top level. Otherwise, the audio input signals appear
at the top level.
SDI Audio IP Functional Description
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Sample FIFO
Clock Recovery
Audio Extract or Audio Extract with Avalon
Avalon-MM
48 KHz Clock
Core
Error Detection
Packet Find
and
Extract
AES
to
Avalon-ST Audio
(Audio Extract
with Avalon Only)
Channel
Status RAM
Register Interface
aud_clk
internal AES
Avalon-ST
Audio
vid_clk
SD/HD/3G-SDI
3-4
SDI Audio Extract IP Core
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DescriptionValueParameter
On or OffInclude AvalonMM control
interface
Related Information
SDI Audio Embed Signals on page 4-1
SDI Audio Extract IP Core
The SDI Audio Extract IP core accepts the SD-, HD-, and 3G-SDI from the SDI IP cores and extracts one
channel pair of embedded audio.
The format of the embedded audio is in accordance with the following standards:
• SMPTE272M-ABCD standard for SD-SDI
• SMPTE299M standard for HD-SDI
• SMPTE299M standard for 3G-SDI (provisional)
If you are extracting more than one channel pair, you must use multiple instances of the component. This
IP core supports AES audio format for 48-kHz sampling rate.
This figure shows a block diagram of the SDI Audio Extract IP core.
Turn on to include the Avalon-MM control interface.
When you turn on this parameter, the register interface signals
appear at the top level. Otherwise, the direct control interface
signals appear at the top level.
Figure 3-2: SDI Audio Extract IP Core Block Diagram
The SDI Audio Extract IP core consists of the following components:
• An audio extraction core
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Programmable
Divide
Digital
PLL
Clock Phase
Recovery
vid_clk
Video standard
3.072 MHz Output
24 KHz
200 MHz
Extracted
audio data
/128
SD
HD
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SDI Audio Extract Parameters
• A register interface block that provides support for an Avalon-MM control bus
The clock recovery block recreates a 64 × sample rate clock, which you can use to clock the audio output
logic. As the component recreates this clock from a 200-MHz reference clock, the created clock may have a
higher jitter than is desirable.
A digital PLL synchronizes this created clock to a 24-kHz reference source.
For the HD-SDI embedded audio, the 24-kHz reference source is the embedded clock phase information.
For the SD-SDI embedded audio, where the embedded clock phase data is not present, you can create the
24-kHz reference signal directly from the video clock.
This figure shows the clock recovery block diagram.
Figure 3-3: Clock Recovery Block Diagram
3-5
SDI Audio Extract Parameters
The following table lists the parameters for the SDI Audio Extract IP core.
Table 3-2: SDI Audio Extract Parameters
Include SD-SDI 24-bit
support
Channel status RAM
Include error checking
Include status register
SDI Audio IP Functional Description
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On or
Off
Off
Off
On or
Off
DescriptionValueParameter
Enables the extra logic to recover the EDP ancillary packets from SD-SDI
inputs.
Turn on to store the received channel status data.On or
Turn on to enable extra error-checking logic to use the error status register.On or
Turn on to enable extra logic to report the audio FIFO status on the fifo_
status port or register.
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SDI Clocked Audio Input IP Core
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DescriptionValueParameter
Include clock
On or
Off
Turn on to enable the logic to recover both a sample rate clock and a 64 ×
sample rate clock.
With HD-SDI inputs, the core generates the output by using the embedded
clock phase information.
With SD-SDI inputs, the core generates this output by using the counters
running on the 27-MHz video clock. This generation limits the SD-SDI
embedded audio to being synchronous to the video.
Include Avalon-ST
interface
On or
Off
Turn on to include the SDI Clocked Audio Input IP core.
When you turn on this parameter, the Avalon-ST interface signals appear
at the top level. Otherwise, the audio input signals appear at the top level.
Include Avalon-MM
control interface
On or
Off
Turn on to include the Avalon-MM control interface.
When you turn on this parameter, the register interface signals appear at
the top level. Otherwise, the direct control interface signals appear at the
top level.
Related Information
SDI Audio Extract Signals on page 4-5
SDI Clocked Audio Input IP Core
The Clocked Audio Input IP core converts clocked audio in AES formats to Avalon-ST audio.
For a typical AES input, for each channel, the clocked audio input function does the following operations:
• Creates a 192-bit validity word, user word and channel status word
• Presents the words as a control packet after the audio data packet
SDI Audio Clocked Audio Input Parameters
The following table lists the parameters for the SDI Clocked Audio Input IP cores.
Table 3-3: SDI Clocked Audio Input Parameters
Defines the internal FIFO depth.
For example, a value of 3 means 2³ = 8.
Turn on to include the Avalon-MM control interface.
When you turn on this parameter, the register interface signals appear at
the top level. Otherwise, the direct control interface signals appear at the
top level.
Include Avalon-MM
control interface
3–10FIFO size
On or
Off
DescriptionValueParameter
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