Altera SCFIFO User Manual
2014.12.17
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SCFIFO and DCFIFO IP Cores User Guide
UG-MFNALT_FIFO
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Altera provides FIFO functions through the parameterizable single-clock FIFO (SCFIFO) and dual-clock
FIFO (DCFIFO) megafunction IP cores The FIFO functions are mostly applied in data buffering
applications that comply with the first-in-first-out data flow in synchronous or asynchronous clock
domains.
The specific names of the IP cores are as follows:
• SCFIFO: single-clock FIFO
• DCFIFO: dual-clock FIFO (supports same port widths for input and output data)
• DCFIFO_MIXED_WIDTHS: dual-clock FIFO (supports different port widths for input and output
data)
Note: The term “DCFIFO” refers to both the DCFIFO and DCFIFO_MIXED_WIDTHS IP cores, unless
specified.
Configuration Methods
You can configure and build the FIFO IP cores with the following methods:
Table 1: Configuration Methods
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Method Description
Using the FIFO parameter editor. Altera recommends using this method to build your
FIFO IP cores. It is an efficient way to configure and
build the FIFO IP cores. The FIFO parameter editor
provides options that you can easily use to
configure the FIFO IP cores.
Manually instantiating the FIFO IP cores. Use this method only if you are an expert user. This
method requires that you know the detailed specifi‐
cations of the IP cores. You must ensure that the
input and output ports used, and the parameter
values assigned are valid for the FIFO IP cores you
instantiate for your target device.
Related Information
Introduction to Altera IP Cores
Provides general information about the Quartus II Parameter Editor
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SCFIFO
data[7..0]
wrreq
rdreq
sclr
aclr
clock
almost_full
almost_empty
usedw[7..0]
empty
full
q[7..0]
DCFIFO
data[7..0]
wrreq
rdreq
wrempty
aclr
rdempty
rdusedw[8..0]
wrclk wrusedw[8..0]
q[7..0]
rdfull
wrfull
rdclk
2
Specifications
Specifications
Verilog HDL Prototype
You can locate the Verilog HDL prototype in the Verilog Design File (.v) altera_mf.v in the <Quartus II
installation directory>\eda\synthesis directory.
VHDL Component Declaration
The VHDL component declaration is located in the <Quartus II installation directory>\libraries\vhdl\altera_mf\
altera_mf_components.vhd
VHDL LIBRARY-USE Declaration
The VHDL LIBRARY-USE declaration is not required if you use the VHDL Component Declaration.
LIBRARY altera_mf;
USE altera_mf_altera_mf_components.all;
SCFIFO and DCFIFO Signals
This section provides diagrams of the SCFIFO and DCFIFO blocks to help in visualizing their input and
output ports. This section also describes each port in detail to help in understanding their usages,
functionality, or any restrictions. For better illustrations, some descriptions might refer you to a specific
section in this user guide.
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Figure 1: SCFIFO and DCFIFO IP Cores Input and Output Signals
For the SCFIFO block, the read and write signals are synchronized to the same clock; for the DCFIFO
block, the read and write signals are synchronized to the rdclk and wrclk clocks respectively. The
prefixes wr and rd represent the signals that are synchronized by the wrclk and rdclk clocks respectively.
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SCFIFO and DCFIFO Signals
Table 2: Input and Output Ports Description
This table lists the signals of the IP cores. The term “series” refers to all the device families of a particular device.
For example, “Stratix series” refers to the Stratix®, Stratix GX, Stratix II, Stratix II GX, Stratix III, and new devices,
unless specified otherwise.
Port Type Required Description
(1)
clock
wrclk
(2)
Input Yes Positive-edge-triggered clock.
Input Yes Positive-edge-triggered clock.
Use to synchronize the following ports:
• data
• wrreq
• wrfull
• wrempty
• wrusedw
(2)
rdclk
Input Yes Positive-edge-triggered clock.
Use to synchronize the following ports:
• q
• rdreq
• rdfull
• rdempty
• rdusedw
3
(3)
data
Input Yes Holds the data to be written in the FIFO IP core when the
wrreq signal is asserted. If you manually instantiate the
FIFO IP core, ensure the port width is equal to the lpm_
width parameter.
(1)
Only applicable for the SCFIFO IP core.
(2)
Applicable for both of the DCFIFO IP cores.
(3)
Applicable for the SCFIFO, DCFIFO, and DCFIFO_MIXED_WIDTH IP cores.
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SCFIFO and DCFIFO Signals
Port Type Required Description
(3)
wrreq
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Input Yes Assert this signal to request for a write operation.
Ensure that the following conditions are met:
• Do not assert the wrreq signal when the full (for
SCFIFO) or wrfull (for DCFIFO) port is high. Enable
the overflow protection circuitry or set the overflow_
checking parameter to ON so that the FIFO IP core
can automatically disable the wrreq signal when it is
full.
• The wrreq signal must meet the functional timing
requirement based on the full or wrfull signal.
• Do not assert the wrreq signal during the deassertion
of the aclr signal. Violating this requirement creates a
race condition between the falling edge of the aclr
signal and the rising edge of the write clock if the
wrreq port is set to high. For both the DCFIFO IP
cores that target Stratix and Cyclone series (except
Stratix, Stratix GX, and Cyclone devices), you have the
option to automatically add a circuit to synchronize
the aclr signal with the wrclk clock, or set the write_
aclr_synch parameter to ON. Use this option to
ensure that the restriction is obeyed.
rdreq
sclr
aclr
(1)
(3)
(3)
Input Yes Assert this signal to request for a read operation. The
rdreq signal acts differently in normal mode and show-
ahead mode.
Ensure that the following conditions are met:
• Do not assert the rdreq signal when the empty (for
SCFIFO) or rdempty (for DCFIFO) port is high.
Enable the underflow protection circuitry or set the
underflow_checking parameter to ON so that the
FIFO IP core can automatically disable the rdreq
signal when it is empty.
• The rdreq signal must meet the functional timing
requirement based on the empty or rdempty signal.
Input No Assert this signal to clear all the output status ports, but
the effect on the q output may vary for different FIFO
configurations.
There are no minimum number of clock cycles for aclr
signals that must remain active.
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q
full
wrfull
rdfull
Port Type Required Description
(3)
Output Yes Shows the data read from the read request operation.
For the SCFIFO IP core and DCFIFO IP core, the width
of the q port must be equal to the width of the data port.
If you manually instantiate the IP cores, ensure that the
port width is equal to the lpm_width parameter.
For the DCFIFO_MIXED_WIDTHS IP core, the width of
the q port can be different from the width of the data
port. If you manually instantiate the IP core, ensure that
the width of the q port is equal to the lpm_width_r
parameter. The IP core supports a wide write port with a
narrow read port, and vice versa. However, the width
ratio is restricted by the type of RAM block, and in
general, are in the power of 2.
(1)
(2)
(2)
, (4)
(4),
Output No When asserted, the FIFO IP core is considered full. Do
not perform write request operation when the FIFO IP
core is full.
In general, the rdfull signal is a delayed version of the
wrfull signal. However, for Stratix III devices and later,
the rdfull signal function as a combinational output
instead of a derived version of the wrfull signal.
Therefore, you must always refer to the wrfull port to
ensure whether or not a valid write request operation can
be performed, regardless of the target device.
SCFIFO and DCFIFO Signals
5
(1)
empty
wrempty
(4)
rdrempty
almost_full
almost_empty
(2)
, (4)
(1)
(1)
(2)
,
Output No When asserted, the FIFO IP core is considered empty. Do
not perform read request operation when the FIFO IP
core is empty.
In general, the wrempty signal is a delayed version of the
rdempty signal. However, for Stratix III devices and later,
the wrempty signal function as a combinational output
instead of a derived version of the rdempty signal.
Therefore, you must always refer to the rdempty port to
ensure whether or not a valid read request operation can
be performed, regardless of the target device.
Output No Asserted when the usedw signal is greater than or equal to
the almost_full_value parameter. It is used as an early
indication of the full signal.
Output No Asserted when the usedw signal is less than the almost_
empty_value parameter. It is used as an early indication
of the empty signal.
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SCFIFO and DCFIFO Parameters
Port Type Required Description
usedw
wrusedw
rdusedw
(1)
(2)
(2)
, (4)
, (4)
Output No Show the number of words stored in the FIFO.
Ensure that the port width is equal to the lpm_widthu
parameter if you manually instantiate the SCFIFO IP core
or the DCFIFO IP core. For the DCFIFO_MIXED_
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WIDTH IP core, the width of the wrusedw and rdusedw
ports must be equal to the LPM_WIDTHU and lpm_widthu_
r parameters respectively.
For Stratix, Stratix GX, and Cyclone devices, the FIFO IP
core shows full even before the number of words stored
reaches its maximum value. Therefore, you must always
refer to the full or wrfull port for valid write request
operation, and the empty or rdempty port for valid read
request operation regardless of the target device.
The DCFIFO IP core rdempty output may momentarily glitch when the aclr input is asserted. To
prevent an external register from capturing this glitch incorrectly, ensure that one of the following is true:
• The external register must use the same reset which is connected to the aclr input of the DCFIFO IP
core, or
• The reset connected to the aclr input of the DCFIFO IP core must be asserted synchronous to the
clock which drives the external register.
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The output latency information of the FIFO IP cores is important, especially for the q output port,
because there is no output flag to indicate when the output is valid to be sampled.
SCFIFO and DCFIFO Parameters
This table lists the parameters for the SCFIFO and DCFIFO IP cores.
Parameter Type Requir
ed
lpm_width Integer Yes Specifies the width of the data and q ports for the
SCFIFO IP core and DCFIFO IP core. For the
DCFIFO_MIXED_WIDTHS IP core, this parameter
specifies only the width of the data port.
lpm_width_r Integer Yes Specifies the width of the q port for the DCFIFO_
MIXED_WIDTHS IP core.
lpm_widthu Integer Yes Specifies the width of the usedw port for the SCFIFO IP
core, or the width of the rdusedw and wrusedw ports
for the DCFIFO IP core. For the DCFIFO_MIXED_
WIDTHS IP core, it only represents the width of the
wrusedw port.
lpm_widthu_r
(4)
Integer Yes Specifies the width of the rdusedw port for the
DCFIFO_MIXED_WIDTHS IP core.
Description
(4)
Only applicable for the DCFIFO_MIXED_WIDTHS IP core.
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SCFIFO and DCFIFO Parameters
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Parameter Type Requir
ed
lpm_numwords Integer Yes Specifies the depths of the FIFO you require. The value
Description
must be at least 4.
The value assigned must comply with this equation,
2LPM_WIDTHU
lpm_showahead String Yes Specifies whether the FIFO is in normal mode (OFF) or
show-ahead mode (ON).
For normal mode, the FIFO IP core treats the rdreq
port as a normal read request that only performs read
operation when the port is asserted.
For show-ahead mode, the FIFO IP core treats the
rdreq port as a read-acknowledge that automatically
outputs the first word of valid data in the FIFO IP core
(when the empty or rdempty port is low) without
asserting the rdreq signal. Asserting the rdreq signal
causes the FIFO IP core to output the next data word, if
available.
If you set the parameter to ON, you may reduce
performance.
lpm_type
String No Identifies the library of parameterized modules (LPM)
entity name. The values are SCFIFO and DCFIFO.
maximize_speed Integer No Specifies whether or not to optimize for area or speed.
The values are 0 through 10. The values 0, 1, 2, 3, 4,
and 5 result in area optimization, while the values 6, 7,
8, 9, and 10 result in speed optimization.
This parameter is applicable for Cyclone II and
Stratix II devices only.
overflow_checking String No Specifies whether or not to enable the protection
circuitry for overflow checking that disables the wrreq
port when the FIFO IP core is full. The values are ON
or OFF. If omitted, the default is ON.
underflow_checking String No Specifies whether or not to enable the protection
circuitry for underflow checking that disables the rdreq
port when the FIFO IP core is empty. The values are
ON or OFF. If omitted, the default is ON.
Note that reading from an empty SCFIFO gives
unpredictable results.
(5)
Only applicable for the DCFIFO IP core.
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SCFIFO and DCFIFO Parameters
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Parameter Type Requir
delay_rdusedw
delay_wrusedw
(5)
(5)
ed
String No Specify the number of register stages that you want to
internally add to the rdusedw or wrusedw port using
the respective parameter.
Description
The default value of 1 adds a single register stage to the
output to improve its performance. Increasing the value
of the parameter does not increase the maximum
system speed. It only adds additional latency to the
respective output port.
add_usedw_msb_bit String No Increases the width of the rdusedw and wrusedw ports
by one bit. By increasing the width, it prevents the
FIFO IP core from rolling over to zero when it is full.
The values are ON or OFF. If omitted, the default value
is OFF.
This parameter is only applicable for Stratix and
Cyclone series (except for Stratix, Stratix GX, and
Cyclone devices).
rdsync_delaypipe
wrsync_delaypipe
(5)
(5)
Integer No Specify the number of synchronization stages in the
cross clock domain. The value of the rdsync_
delaypipe parameter relates the synchronization
stages from the write control logic to the read control
logic; the wrsync_delaypipe parameter relates the
synchronization stages from the read control logic to
the write control logic. Use these parameters to set the
number of synchronization stages if the clocks are not
synchronized, and set the clocks_are_synchronized
parameter to FALSE.
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The actual synchronization stage implemented relates
variously to the parameter value assigned, depends on
the target device.
For Cyclone II and Stratix II devices and later, the
values of these parameters are internally reduced by
two. Thus, the default value of 3 for these parameters
corresponds to a single synchronization stage; a value
of 4 results in two synchronization stages, and so on.
For these devices, choose at least 4 (two synchroniza‐
tion stages) for metastability protection.
String No Specifies whether or not the FIFO IP core is
constructed using the RAM blocks. The values are ON
or OFF.
Setting this parameter value to OFF yields the FIFO IP
core implemented in logic elements regardless of the
type of the TriMatrix memory block type assigned to
the ram_block_type parameter.
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SCFIFO and DCFIFO Parameters
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Parameter Type Requir
write_aclr_synch
(5)
ed
String No Specifies whether or not to add a circuit that causes the
aclr port to be internally synchronized by the wrclk
Description
clock. Adding the circuit prevents the race condition
between the wrreq and aclr ports that could corrupt
the FIFO IP core.
The values are ON or OFF. If omitted, the default value
is OFF. This parameter is only applicable for Stratix and
Cyclone series (except for Stratix, Stratix GX, and
Cyclone devices).
read_aclr_synch String No Specifies whether or not to add a circuit that causes the
aclr port to be internally synchronized by the rdclk
clock. Adding the circuit prevents the race condition
between the rdreq and aclr ports that could corrupt
the FIFO IP core.
The values are ON or OFF. If omitted, the default value
is OFF. This parameter is only applicable for families
beginning from Stratix III series.
clocks_are_synchron-
(5)
ized
String No Specifies whether or not the write and read clocks are
synchronized which in turn determines the number of
internal synchronization stages added for stable
operation of the FIFO. The values are TRUE and
FALSE. If omitted, the default value is FALSE. You
must only set the parameter to TRUE if the write clock
and the read clock are always synchronized and they
are multiples of each other. Otherwise, set this to
FALSE to avoid metastability problems.
ram_block_type
SCFIFO and DCFIFO IP Cores User Guide
If the clocks are not synchronized, set the parameter to
FALSE, and use the rdsync_delaypipe and wrsync_
delaypipe parameters to determine the number of
synchronization stages required.
String No Specifies the target device’s Trimatrix Memory Block to
be used. To get the proper implementation based on
the RAM configuration that you set, allow the
Quartus II software to automatically choose the
memory type by ignoring this parameter and set the
use_eab parameter to ON. This gives the compiler the
flexibility to place the memory function in any available
memory resource based on the FIFO depth required.
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