Alliance Semiconductor Corporation AS4LC1M16E5-60TI, AS4LC1M16E5-60TC, AS4LC1M16E5-60JI, AS4LC1M16E5-60JC, AS4LC1M16E5-50TI Datasheet

3V 1M×16 CMOS DRAM (EDO)

Features

• Organization: 1,048,576 words × 16 bits

• High speed

- 50/60 ns RAS access time

- 20/25 ns hyper page cycle time

- 12/15 ns CAS

• Low power consumption

- Active: 500 mW max (-60)

- Standby: 3.6 mW max, CMOS DQ

• Extended data out

• 1024 refresh cycles, 16 ms refresh interval

-RAS-only or CAS-before-RAS refresh or self-refresh

access time

AS4LC1M16E5

®

•Read-modify-write

• TTL-compatible, three-state DQ

• JEDEC standard package and pinout

- 400 mil, 42-pin SOJ

- 400 mil, 44/50-pin TSOP II

• 3V power supply (AS4LC1M16E5)

• 5V tolerant I/Os; 5.5V maximum V

• Industrial and commercial temperature available

IH

Pin arrangement

TSOP II

V

1

CC

2
3
4
5

CC

6
7
8
9
10
11

15
16
17
18
19
20
21

A0

22

A1
A2

23

A3

24
25

CC

50

SS

DQ16

49

DQ15

48

DQ14

47

DQ13

46

V

45

SS

DQ12

44

DQ11

43

DQ10

42

DQ9

41

NC

40

NC

36

LCAS

35

UCAS

34

OE

33
32

A9

31

A8

30

A7

29

A6
A5

28

A4

27

V

26

SS

Vcc
DQ1
DQ2
DQ3

DQ4

Vcc
DQ5
DQ6
DQ7
DQ8

NC
NC

WE

RAS

NC
NC

A0
A1
A2
A3

SOJ

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

SS

41

DQ16

40

DQ15

39

DQ14

38

DQ13

37

V

SS

36

DQ12

35

DQ11

34

DQ10

33

DQ9

32

NC

31

LCAS

30

UCAS

29

OE

28

A9

27

A8

26

A7

25

A6

24

A5

23

A4

2221Vcc

V

SS

V

42

V
DQ1
DQ2
DQ3
DQ4

V
DQ5

DQ6
DQ7
DQ8

NC

NC
NC

WE

RAS

NC
NC

V

Selection guide

Maximum RAS

Maximum column address access time t

Maximum CAS

Maximum output enable (OE

Minimum read or write cycle time t

Minimum hyper page mode cycle time t

Maximum operating current I

Maximum CMOS standby current I

Shaded areas indicate advance information.

access time t

access time t

) access time t

Pin designation

Pin(s) Description

A0 to A9 Address inputs

RAS

DQ1 to DQ16 Input/output

OE

WE

UCAS

LCAS

V

CC

V

SS

Symbol -50 -60 Unit

RAC

AA

CAC

OEA

RC

HPC

CC1

CC5

Row address strobe

Output enable

Write enable

Column address strobe, upper byte

Column address strobe, lower byte

Power

Ground

50 60 ns

25 30 ns

10 12 ns

10 12 ns

80 100 ns

20 25 ns

140 120 mA

1.0 1.0 mA

4/11/01; v.1.0

Alliance Semiconductor P. 1 of 22

Alliance Semiconductor

Copyright © Alliance Semiconductor. All rights reserved.

AS4LC1M16E5

®

Functional description

The AS4LC1M16E5 is a high performance 16-megabit CMOS Dynamic Random Access Memory (DRAM) organized as 1,048,576 words × 16
bits. The device is fabricated using advanced CMOS technology and innovative design techniques resulting in high speed, extremely low power
and wide operating margins at component and system levels. The Alliance 16Mb DRAM family is optimized for use as main memory in
personal and portable PCs, workstations, and multimedia and router switch applications.

The AS4LC1M16E5 features hyper page mode operation where read and write operations within a single row (or page) can be executed at very
high speed by toggling column addresses within that row. Row and column addresses are alternately latched into input buffers using the falling
edge of RAS
addresses prior to xCAS

Extended data out (EDO), also known as 'hyper-page mode,' enables high speed operation. In contrast to 'fast-page mode' devices, data remains
active on outputs after xCAS
and prevent bus contention during read-modify-write and shared bus applications. Outputs also go to high impedance at the last occurrance of
RAS and xCAS going high.

Refresh on the 1024 address combinations of A0 to A9 must be performed every 16 ms using:

•RAS-only refresh: RAS is asserted while xCAS is held high. Each of the 1024 rows must be strobed. Outputs remain high impedence.

• Hidden refresh: xCAS

•CAS-before-RAS refresh (CBR): At least one xCAS is asserted prior to RAS. Refresh address is generated internally.
Outputs are high-impedence (OE

• Normal read or write cycles refresh the row being accessed.

• Self-refresh cycles

The AS4LC1M16E5 is available in the standard 42-pin plastic SOJ and 44/50-pin TSOP II packages, respectively. The AS4LC1M16E5 device
operates with a single power supply of 3V ± 0.3V and provides TTL compatible inputs and outputs.

and xCAS inputs, respectively. Also, RAS is used to make the column address latch transparent, enabling application of column

assertion. The AS4LC1M16E5 provides dual UCAS and LCAS for independent byte control of read and write access.

is de-asserted high, giving system logic more time to latch the data. Use OE and WE to control output impedance

is held low while RAS is toggled. Outputs remain low impedence with previous valid data.

and WE are don't care).

Logic block diagram

Data

DQ

buffers

Substrate bias

DQ1 to DQ16

OE

generator

RAS

UCAS

LCAS

WE

RAS clock
generator

CAS clock
generator

WE clock
generator

V

GND

CC

Refresh

controller

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9

Address buffers

Row decoder

Column decoder

Sense amp

1024 × 1024 × 16

Array

(16,777,216)

Recommended operating conditions

Parameter Symbol Min Nominal Max Unit

V

Supply voltage

CC

GND 0.0 0.0 0.0 V

V

Input voltage

IH

V

IL

Commercial

Ambient operating temperature

Industrial -40 – 85

†

VIL min -3.0V for pulse widths less than 5 ns.

Recommended operating conditions apply throughout this document unless otherwise specified.

T

A

3.0 3.3 3.6 V

2.0 – 5.5 V

†

–0.5

–0.8V

0–70

°C

4/11/01 Alliance Semiconductor 2

AS4LC1M16E5

®

Absolute maximum ratings

Parameter Symbol Min Max Unit

Input voltage V

Power supply voltage V

Storage temperature (plastic) T

Soldering temperature

time T

×

Power dissipation P

Short circuit output current I

DQ

CC

STG

SOLDER

D

out

-1.0 +5.5 V

-1.0 +4.0 V

-65 +150 °C

– 260 × 10

o

C × sec

–0.6W

–50mA

Truth table

Addresses

Operation RAS

LCAS UCAS WE OE

R

Standby H H to X H to X X X X X High-Z

Wo r d re a d LL LHLROWCOL Data out

Lower byte
read

Upper byte
read

Wo r d
(early) write

Lower byte
(early) write

Upper byte
(early) write

LLHHLROWCOL

LH LHLROWCOL

LL LLXROWCOL Data in

LLHLXROWCOL

LH L LXROWCOL

Read write L L L H to L L to H ROW COL Data out, Data in 1,2

1st cycle L H to L H to L H L ROW COL Data out 2

EDO read

2nd cycle L H to L H to L H L n/a COL Data out 2

Any cycle L L to H L to H H L n/a n/a Data out 2

1st cycle L H to L H to L L X ROW COL Data in 1

EDO write

EDO
read write

only

RAS
refresh

2nd cycle L H to L H to L L X n/a COL Data in 1

1st cycle L H to L H to L H to L L to H ROW COL Data out, Data in 1,2

2nd cycle L H to L H to L H to L L to H n/a COL Data out, Data in 1,2

L H H X X ROW n/a High Z

CBR refresh H to L L L H X X X High Z 3

Self refresh H to L L L H X X X High Z 3

t

C

DQ0 to DQ15 Notest

Lower byte,

Upper byte, Data out

Lower byte,

Data out, Upper byte

Lower byte, Data in, Upper byte, High-Z

Lower byte, High-Z,

Upper byte, Data in

4/11/01 Alliance Semiconductor 3

DC electrical characteristics

Parameter Symbol Test conditions

Input leakag

urrent I

e c

Output leakage current I

Operating power
supply current

TTL standby power
supply current

I

I

Average power supply
current, RAS

refresh

I

mode or CBR

EDO page mode average
power supply current

CMOS standby power
supply current

I

I

V

Output voltage

V

before RAS refresh

CAS
current

I

Self refresh current I

Shaded areas indicate advance information.

0V ≤ Vin ≤ V

IL

Pins not under test = 0V

D

OL

disabled, 0V ≤ V

OUT

RAS, UCAS, LCAS, Address cycling;

CC1

t

=min

RC

RAS = UCAS = LCAS ≥ V

CC2

all other inputs at V

RAS cycling, UCAS = LCAS ≥ V

CC3

t

= min of RAS low after XCAS low.

RC

RAS = VIL, UCAS or LCAS,

CC4

address cycling: t

RAS = UCAS = LCAS = VCC - 0.2V,

CC5

F = 0

OHIOUT

OLIOUT

CC6

= -5.0 mA 2.4 –2.4– V

= 4.2 mA – 0.4 – 0.4 V

RAS, UCAS or LCAS cycling, tRC = min – 80 – 70

RAS = UCAS = LCAS ≤ 0.2V,

WE

CC7

= OE ≥ V

all other inputs at 0.2V or
V

- 0.2V

CC

(max)

CC

CC

IH

= min

HPC

- 0.2V,

out

or V

®

-50 -60

Min Max Min Max

-2 +2 -2 +2

≤ V

(max) -2 +2 -2 +2

CC

– 140 – 130 mA 4,5

,

IH

IL

,

IH

– 2.0 – 2.0 mA

– 80 – 70 mA 4

– 85 – 75 mA 4, 5

– 1–1mA

– 0.5 – 0.5

AS4LC1M16E5

Unit Notes

A

µ

A

µ

mA

mA

4/11/01 Alliance Semiconductor 4

AS4LC1M16E5

®

AC parameters common to all waveforms

-50 -60

Symbol Parameter

t

RC

t

RP

t

RAS

t

CAS

t

RCD

t

RAD

t

RSH

t

CSH

t

CRP

t

ASR

t

RAH

t

T

t

REF

t

CP

t

RAL

Column address setup time 0 –0–ns

t

ASC

t

Column address hold time 8 –10–ns

CAH

Shaded areas indicate advance information.

Random read or write cycle time 80 –100–ns

RAS precharge time 30 –40–ns

RAS pulse width 50 10K 60 10K ns

CAS pulse width 8 10K 10 10K ns

RAS to CAS delay time 15 35 15 43 ns 9

RAS to column address delay time 9 25 10 30 ns 10

CAS to RAS hold time 10 –10–ns

RAS to CAS hold time 40 –50–ns

CAS to RAS precharge time 5 –5–ns

Row address setup time 0 –0–ns

Row address hold time 8 –10–ns

Transition time (rise and fall) 1 50150ns7,8

Refresh period – 16 – 16 ms 6

CAS precharge time 8 –10–ns

Column address to RAS lead time 25 –30–ns

Min Max Min Max

Unit Notes

Read cycle

Symbol Parameter

t

RAC

t

CAC

t

AA

t

RCS

t

RCH

t

RRH

Shaded areas indicate advance information.

Access time from RAS – 50 – 60 ns 9

Access time from CAS – 12 – 15 ns 9,16

Access time from address – 25 – 30 ns 10,16

Read command setup time 0 –0–ns

Read command hold time to CAS 0 –0–ns12

Read command hold time to RAS 0 –0–ns12

-50 -60

Min Max Min Max

Unit Notes

4/11/01 Alliance Semiconductor 5

AS4LC1M16E5

®

Write cycle

-50 -60

Symbol Parameter

t

Write command setup time 0 –0–ns14

WCS

t

Write command hold time 10 –10– ns14

WCH

t

Write command pulse width 10 –10– ns

WP

t

Write command to RAS lead time 10 –10– ns

RW L

t

Write command to CAS lead time 8 –10– ns

CWL

Data-in setup time 0 –0–ns15

t

DS

t

Data-in hold time 8 –10– ns15

DH

Shaded areas indicate advance information.

Min Max Min Max

Unit Notes

Read-modify-write cycle

-50 -60

Symbol Parameter

t

Read-write cycle time 113 –135– ns

RW C

t

RAS to WE delay time 67 – 77 – ns 14

RW D

CAS to WE delay time 32 – 35 – ns 14

t

CWD

t

Column address to WE delay time 42 – 47 – ns 14

AW D

Shaded areas indicate advance information.

Min Max Min Max

Unit Notes

Refresh cycle

-50 -60

Symbol Parameter

t

CAS setup time (CAS-before-RAS

CSR

t

CAS hold time (CAS-before-RAS) 8 –10– ns6

CHR

t

RAS precharge to CAS hold time 0 –0–ns

RPC

precharge time

t

CPT

Shaded areas indicate advance information.

CAS
(CBR counter test)

)

Min Max Min Max

5 –5–ns6

10 –10– ns

Unit Notes

4/11/01 Alliance Semiconductor 6

Hyper page mode cycle

Symbol Parameter

t

CPWD

t

CPA

t

RASP

t

DOH

t

REZ

t

WEZ

t

OEZ

t

HPC

t

HPRWC

t

RHCP

Shaded areas indicate advance information.

CAS precharge to WE delay time 45 –52–ns

Access time from CAS precharge – 28 – 35 ns 16

RAS pulse width 50 100K 60 100K ns

Previous data hold time from CAS 5 –5–ns

Output buffer turn off delay from RAS 0 13 0 15 ns

Output buffer turn off delay from WE 0 13 0 15 ns

Output buffer turn off delay from OE 0 13 0 15 ns

Hyper page mode cycle time 20 –25–ns

Hyper page mode RMW cycle 47 –56– ns

RAS hold time from CAS 30 –35– ns

Output enable

Symbol Parameter

t

CLZ

t

ROH

t

OEA

t

OED

t

OEZ

t

OEH

t

OLZ

t

OFF

Shaded areas indicate advance information.

CAS to output in Low Z 0 –0–ns11

RAS hold time referenced to OE 8 –10–ns

OE access time – 13 – 15 ns

OE to data delay 13 –15–ns

Output buffer turnoff delay from OE 0 13015ns11

OE command hold time 10 –10– ns

OE to output in Low Z 0 –0–ns

Output buffer turn-off time 0 13 0 15 ns 11,13

®

-50 -60

Min Max Min Max

-50 -60

Min Max Min Max

AS4LC1M16E5

Unit Notes

Unit Notes

Self refresh cycle

-50 -60

Std Symbol Parameter

t

RASS

t

RPS

t

CHS

Shaded areas indicate advance information.

4/11/01 Alliance Semiconductor 7

RAS pulse width
(CBR self refresh)

RAS precharge time
(CBR self refresh)

hold time

CAS

(CBR self refresh)

Min Max Min Max

100 –100– µs

90 –105– ns

8 –10– ns

Unit Notes