Alliance Semiconductor Corporation AS4C4M4F1-60TC, AS4C4M4F1-60JI, AS4C4M4F1-60JC, AS4C4M4F1-50TI, AS4C4M4F1-50TC Datasheet

5V 4M×4 CMOS DRAM (Fast Page mode)

Features

• Organization: 4,194,304 words × 4 bits

• High speed

- 50/60 ns RAS access time

- 25/30 ns column address access time

- 12/15 ns CAS

• Low power consumption

- Active: 908 mW max

- Standby: 5.5 mW max, CMOS I/O

•Fast page mode

•Refresh

- 4096 refresh cycles, 64 ms refresh interval for
AS4C4M4F0

- 2048 refresh cycles, 32 ms refresh interval for
AS4C4M4F1

-RAS

-only or CAS-before-RAS refresh or self-refresh

access time

AS4C4M4F0
AS4C4M4F1

®

• TTL-compatible, three-state I/O

• JEDEC standard package

- 300 mil, 24/26-pin SOJ

- 300 mil, 24/26-pin TSOP

• Latch-up current ≥ 200 mA

• ESD protection ≥ 2000 mV

• Industrial and commercial temperature available

Pin arrangement

SOJ

V

CC

1

I/O0

2

I/O1

3

WE

4

RAS

*NC/A11 A9

5
621

A10

8

AS4C4M4F0

9

A0

10

A1

11

A2

12

A3

13

V

CC

*NC on 2K refresh version; A11 on 4K refresh version

GND

26

I/O3

25

I/O2

24

CAS

23

OE

22

A8

19

A7

18

A6

17

A5

16
15

A4

14

GND

V
I/O0

I/O1

WE

RAS

*NC/A11 A9

A10

V

A0
A1
A2
A3

CC

TSOP

CC

1
2
3
4
5
6

8

AS4C4M4F0

9
10
11
12
13

Selection guide

Maximum RAS

Maximum column address access time t

Maximum CAS

Maximum output enable (OE

Minimum read or write cycle time t

Minimum fast page mode cycle time t

Maximum operating current I

Maximum CMOS standby current I

access time t

access time t

) access time t

26
25
24
23
22
21

19
18
17
16
15
14

Symbol

RAC

CAA

CAC

OEA

RC

PC

CC1

CC5

GND
I/O3
I/O2
CAS
OE

A8
A7
A6
A5
A4

GND

Pin designation

Pin(s) Description

A0 to A11 Address inputs

RAS

CAS

WE

I/O0 to I/O3 Input/output

OE

V

CC

GND Ground

AS4C4M4F0-50
AS4C4M4F1-50

50 60 ns

25 30 ns

12 15 ns

13 15 ns

85 100 ns

25 30 ns

135 120 mA

1.0 1.0 mA

Row address strobe

Column address strobe

Write enable

Output enable

Power

AS4C4M4F0-60
AS4C4M4F1-60 Unit

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Copyright © Alliance Semiconductor. All rights reserved.

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AS4C4M4F0
AS4C4M4F1

®

Functional description

The AS4C4M4F0 and AS4C4M4F1 are high performance 16-megabit CMOS Dynamic Random Access Memory (DRAM) devices organized as
4,194,304 words × 4 bits. The devices are fabricated using advanced CMOS technology and innovative design techniques resulting in high
speed, extremely low power and wide operating margins at component and system levels. The Alliance 16Mb DRAM family is optimized for
use as main memory in PC, workstation, router and switch applications.

These devices feature a high speed page mode operation where read and write operations within a single row (or page) can be executed at
very high speed by toggling column addresses within that row. Row and column addresses are alternately latched into input buffers using the
falling edge of RAS
column addresses prior to CAS

Refresh on the 4096 address combinations of A0 to A11 must be performed every 64 ms using:

-only refresh: RAS is asserted while CAS is held high. Each of the 4096 rows must be strobed. Outputs remain high impedence.

•RAS

• Hidden refresh: CAS
previous valid data.

-before-RAS refresh (CBR): CAS is asserted prior to RAS. Refresh address is generated internally.

•CAS
Outputs are high-impedence (OE

• Normal read or write cycles refresh the row being accessed.

• Self-refresh cycles

Refresh on the 2048 address combinations of A0 to A10 must be performed every 32 ms using:

-only refresh: RAS is asserted while CAS is held high. Each of the 2048 rows must be strobed. Outputs remain high impedence.

•RAS

• Hidden refresh: CAS
previous valid data.

-before-RAS refresh (CBR): CAS is asserted prior to RAS. Refresh address is generated internally.

•CAS
Outputs are high-impedence (OE

• Normal read or write cycles refresh the row being accessed.

• Self-refresh cycles

The AS4C4M4F0 and AS4C4M4F1 are available in the standard 24/26-pin plastic SOJ and 24/26-pin plastic TSOP packages. The
AS4C4M4F0 and AS4C4M4F1 operate with a single power supply of 5V ± 0.5V and provide TTL compatible inputs and outputs.

and CAS inputs respectively. Also, RAS is used to make the column address latch transparent, enabling application of

assertion.

is held low while RAS is toggled. Refresh address is generated internally. Outputs remain low impedence with

and WE are don't care).

is held low while RAS is toggled. Refresh address is generated internally. Outputs remain low impedence with

and WE are don't care).

Logic block diagram for 4K refresh

V

CC

GND

RAS

CAS

WE

RAS clock generator

CAS clock
generator

WE clock
generator

A0
A1
A2
A3
A4
A5
A6
A7
A8

A9
A10
A11

4/11/01; v.0.9 Alliance Semiconductor

Refresh

controller

Address buffers

Row decoder

Column decoder

Sense amp

4096 × 1024 × 4

Array

(16,777,216)

Data

I/O

buffers

I/O0 to I/O3

OE

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Logic block diagram for 2K refresh

AS4C4M4F0
AS4C4M4F1

®

Data

I/O

buffers

I/O0 to I/O3

OE

Substrate bias

generator

RAS

CAS

WE

RAS clock generator

CAS clock
generator

WE clock
generator

V

GND

CC

Refresh

controller

A0
A1
A2
A3
A4
A5
A6

A10

A7
A8

A9

Address buffers

Row decoder

Column decoder

Sense amp

2048 × 2048 × 4

Array

(16,777,216)

Recommended operating conditions

Parameter Symbol Min Nominal Max Unit

V

Supply voltage

CC

GND 0.0 0.0 0.0 V

V

Input voltage

IH

V

IL

Commercial

Ambient operating temperature

Industrial -40 – 85

†

VIL min -3.0V for pulse widths less than 5 ns. Recommended operating conditions apply throughout this document unlesss otherwise specified.

T

A

4.5 5.0 5.5 V

2.4 – V

†

–0.5

–0.8V

CC

V

0–70

°C

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AS4C4M4F0
AS4C4M4F1

®

Absolute maximum ratings

Parameter Symbol Min Max Unit

Input voltage V

Input voltage (DQs) V

Power supply voltage V

Storage temperature (plastic) T

Soldering temperature × time T

Power dissipation P

Short circuit output current I

in

DQ

CC

STG

SOLDER

D

out

-1.0 +7.0 V

-1.0 VCC + 0.5 V

-1.0 +7.0 V

-55 +150 °C

–260 × 10

o

–1W

–50mA

DC electrical characteristics

-50 -60

Parameter Symbol Test conditions

Input leakage current I

Output leakage current I

Operating power
supply current

TTL standby power
supply current

Average power supply
current, RAS

refresh

mode or CBR

Fast page mode average
power supply current

CMOS standby power
supply current

Output voltage

CAS

before RAS refresh

current

I

I

I

I

I

V

V

I

IL

OL

CC1

CC2

CC3

CC4

CC5

OH

OL

CC6

0V ≤ Vin ≤ +5.5V,

Pins not under test = 0V

D

disabled, 0V ≤ V

OUT

RAS, CAS Address cycling; tRC=min – 135 – 120 mA 1,2

RAS = CAS ≥ V

RAS cycling, CAS ≥ V

t

= min of RAS low after XCAS low.

RC

RAS = VIL, CAS,
address cycling: t

RAS = CAS = VCC - 0.2V – 1.0 – 1.0 mA

I

= -5.0 mA 2.4 – 2.4 – V

OUT

I

= 4.2 mA – 0.4 – 0.4 V

OUT

RAS, CAS cycling, tRC = min – 120 – 110 mA

RAS = UCAS = LCAS ≤ 0.2V,

WE

Self refresh current I

CC7

= OE ≥ V

all other inputs at 0.2V or
V

- 0.2V

CC

IH

- 0.2V,

CC

HPC

-5 +5 -5 +5 µA

≤ +5.5V -5 +5 -5 +5 µA

out

–2.0 – 2.0mA

,

IH

= min

–120 –110mA 1

– 130 – 120 mA 1, 2

–0.6 – 0.6

Unit NotesMin Max Min Max

mA

C × sec

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®

AC parameters common to all waveforms

-50 -60

Symbol Parameter

t

RC

t

RP

t

RAS

t

CAS

t

RCD

t

RAD

t

RSH

t

CSH

t

CRP

t

ASR

t

RAH

t

T

t

REF

t

CP

t

RAL

t

ASC

t

CAH

Random read or write cycle time 80 – 100 – ns

RAS precharge time 30 – 40 – ns

RAS pulse width 50 10K 60 10K ns

CAS pulse width 8 10K 10 10K ns

RAS to CAS delay time 15 35 15 43 ns 6

RAS to column address delay time 12 25 12 30 ns 7

CAS to RAS hold time 10 – 10 – ns

RAS to CAS hold time 40 – 50 – ns

CAS to RAS precharge time 5 – 5 – ns

Row address setup time 0 – 0 – ns

Row address hold time 8 – 10 – ns

Transition time (rise and fall) 1 50 1 50 ns 4,5

Refresh period – 64 – 64 ms 3

CAS precharge time 8 – 10 – ns

Column address to RAS lead time 25 – 30 – ns

Column address setup time 0 – 0 – ns

Column address hold time 8 10 – ns

AS4C4M4F0
AS4C4M4F1

Unit NotesMinMaxMinMax

Read cycle

Symbol Parameter

t

RAC

t

CAC

t

AA

t

RCS

t

RCH

t

RRH

Access time from RAS – 50 – 60 ns 6

Access time from CAS – 12 – 15 ns 6,13

Access time from address – 25 – 30 ns 7,13

Read command setup time 0 – 0 – ns

Read command hold time to CAS 0–0–ns9

Read command hold time to RAS 0–0–ns9

-50 -60

Unit NotesMin Max Min Max

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®

Write cycle

-50 -60

Symbol Parameter

t

Write command setup time 0 – 0 – ns 11

WCS

t

Write command hold time 10 – 10 – ns 11

WCH

t

Write command pulse width 10 – 10 – ns

WP

t

Write command to RAS lead time 10 – 10 – ns

RW L

t

Write command to CAS lead time 8 – 10 – ns

CWL

Data-in setup time 0 – 0 – ns 12

t

DS

t

Data-in hold time 8 – 10 – ns 12

DH

Unit NotesMin Max Min Max

Read-modify-write cycle

-50 -60

Symbol Parameter

Read-write cycle time 113 – 135 – ns

t

RW C

RAS to WE delay time 67 – 77 – ns 11

t

RW D

CAS to WE delay time 32 – 35 – ns 11

t

CWD

t

Column address to WE delay time 42 – 47 – ns 11

AW D

Unit NotesMin Max Min Max

AS4C4M4F0
AS4C4M4F1

Refresh cycle

-50 -60

Symbol Parameter

CAS setup time (CAS-before-RAS)5–5–ns3

t

CSR

t

CAS hold time (CAS-before-RAS)8–10–ns3

CHR

RAS precharge to CAS hold time 0 – 0 – ns

t

RPC

precharge time

t

CPT

CAS
(CBR counter test)

10 10 – ns

Unit NotesMin Max Min Max

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