Allegro UCN5881EP Datasheet

5881

BiMOS II DUAL
8-BIT LATCHED DRIVER

Data Sheet

26180.16

588 1

BiMOS II DUAL 8-BIT LATCHED

DRIVER WITH READ BACK

With 16 CMOS data latches (two sets of eight), CMOS control
circuitry for each set of latches, and a bipolar saturated driver for each
latch, the UCN5881EP provides low-power interface with maximum
flexibility. The driver includes thermal shutdown circuitry to protect
against damage from high junction temperatures and clamp diodes
for inductive load transient suppression.

The CMOS inputs cause minimal circuit loading and are compat­ible with standard CMOS, PMOS, and NMOS circuits. TTL or DTL
circuits may require the use of appropriate pull up resistors. When
reading back, each data input will sink 8 mA (if its corresponding latch
is low) or source 400 µA (if its corresponding latch is high). The read
back feature is for error checking. It allows the system to verify that
data has been received and latched.

The bipolar outputs are suitable for use with low-power relays,
solenoids, and stepping motors. The very-low output saturation

Dwg. No. A-14,225

voltage makes this device well-suited for driving LED arrays. The
output transistors are capable of sinking 50 mA and will maintain at
least 20 V in the OFF state. Outputs may be paralleled for higher
current capability.

The UCN5881EP dual 8-bit latched sink driver is rated for opera­tion over the temperature range of -20°C to +85°C and is supplied in a
plastic 44-lead chip carrier conforming to the JEDEC MS-007AB
outline.

FEATURES

ABSOLUTE MAXIMUM RATINGS

Output Voltage, V
Output Sustaining Voltage, V
Output Current, I
Input Voltage Range,

V

. . . . . . . . . . . -0.3 V to VDD + 0.3 V

IN

Logic Supply Voltage, V

DISCONTINUED PRODUCT

Package Power Dissipation,

P

. . . . . . . . . . . . . . . . . . . See Graph

D

Operating Temperature Range,

T

. . . . . . . . . . . . . . . . -20°C to +85°C

A

Storage Temperature Range,

T

Caution: CMOS devices have input static
protection, but are susceptible to damage when
exposed to extremely high static electrical
charges.

— FOR REFERENCE ONLY

. . . . . . . . . . . . . . . -55°C to +150°C

S

. . . . . . . . . . . . . . 20 V

OUT

. . . . . . . . . . . . 50 mA

OUT

. . . . . . . . . . 15 V

DD

CE(sus)

.. . 15 V

■ 4.4 MHz Minimum Data-Input Rate

■ Low-Power CMOS Logic

■ 20 V, 50 mA (Max.) Outputs

■ Transient-Protected Outputs

■ Thermal Shutdown Protection

■ Low-Profile Leaded Chip Carrier

Always order by complete part number: UCN5881EP .

5881

BiMOS II DUAL
8-BIT LATCHED DRIVER

FUNCTIONAL BLOCK DIAGRAM

(1 of 16 Channels)

3.0

2.5

2.0

1.5

R = 46°C/W

θJA

1.0

0.5

ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS

0

25

50 75 100 125 150

AMBIENT TEMPERATURE IN °C

Dwg. GP-025-1A

Dwg. No. A-14,227

TRUTH TABLE

Output Latch

Read/ln Strobe Clear Enable Read/Write Contents Output

X X X 1 X X OFF
0100 1 0 OFF
1100 1 1 ON
X 0 0 0 1 n-1 n-1
X X 1 X X 0 OFF
nX0X 0 n n

n = Present Latch Contents
n-1 = Previous Latch Contents
X = Irrelevant

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Worcester, Massachusetts 01615-0036 [phone]

W
Copyright © 1985, 1995, Allegro MicroSystems, Inc.