▪ Two matched Hall effect switches on a single substrate
▪ Sensor Hall element spacing approximately 1 mm
▪ Superior temperature stability
▪ 3.3 to 18 V operation
▪ Integrated ESD diode from OUTPUT and VCC pins
The A3425 is a dual–output-channel, bipolar switch with
each channel comprising a separate complete Hall-effect
sensor circuit with dedicated Hall element and separate digital
output for speed and direction signal processing capability. The
independent Hall elements (E1 integrated with OUTPUTA, and
E2 integrated with OUTPUTB) are photolithographically aligned
to better than 1 μm. Maintaining this accurate mechanical
location between the two active Hall elements eliminates the
major manufacturing hurdle encountered in fine-pitch detection
applications. The A3425 is a highly sensitive, temperature-stable
magnetic sensing device, which is ideal for use in ring magnetbased speed and direction systems used in harsh automotive
and industrial environments.
The A3425 contains two independent Hall effect switches, and
has a monolithic IC that accurately locates the two Hall elements,
E1 and E2, approximately 1 mm apart. The digital outputs are
90º out of phase so that the outputs are in quadrature, with the
proper ring magnet design. This allows for easy processing of
speed and direction signals. Extremely low-drift amplifiers
guarantee symmetry between the switches to maintain signal
Not to scale
V
Supply
Continued on the next page…
T ypical Application
100 Ω
0.1 uF
Using unregulated supply
VOUTPUTB
VOUTPUTA
2
OUTPUTA
A3425
1
VCC
GND
OUTPUTB
4
3
A3425DS-Rev. 7
Ultra-Sensitive Dual-Channel Quadrature
A3425
Description (continued)
quadrature. The patented chopper stabilization technique cancels
offsets in each channel, and provides stable operation over the
operating temperature and voltage ranges. An on-chip regulator
allows the use of this device over a wide operating voltage range.
The A3425 is available in a plastic 8-pin SOIC surface mount
package (L) and a plastic 4-pin SIP (K), both in two operating
temperature ranges. Each package is available in a lead (Pb) free
version with 100% matte tin plated leadframe.
When operating at maximum voltage, never exceed maximum junction temperature, T
2
Device will survive the current level specifi ed, but operation within magnetic specifi cation cannot be guaranteed.
3
Short circuit of the output to VCC is protected for the time duration specifi ed.
4
Maximum specifi cation limit is equivalent to I
5
Magnetic fl ux density, B, is indicated as a negative value for north-polarity magnetic fi elds, and as a positive value for south-polarity
OP(A)
+ B
RP(A), BOP(B)
OP(A)
RP(A)
+ B
– B
– B
RP(B)
OP(B)
RP(B)
B
, B
OP(A)
B
, B
RP(A)
B
, B
HYS(A)
SYMA, SYM
SYM
AB(OP)
SYM
AB(RP)
5
B
, B
OP(A)
B
, B
RP(A)
B
, B
HYS(A)
SYMA, SYM
SYM
AB(OP)
SYM
AB(RP)
CC(max)
OP(B)
RP(B)
HYS(B)
OP(B)
RP(B)
HYS(B)
B
B
+ 3 mA.
–735G
–35–7–G
51640 G
–40–40G
–30–30G
–30–30G
–730G
–30–7–G
51435 G
–35–35G
–25–25G
–25–25G
. Refer to power derating curve charts.
J(max)
magnetic fi elds. This so-called algebraic convention supports arithmetic comparison of north and south polarity values, where the
relative strength of the fi eld is indicated by the absolute value of B, and the sign indicates the polarity of the fi eld (for example, a
–100 G fi eld and a 100 G fi eld have equivalent strength, but opposite polarity).
When using Hall effect technology, a limiting factor
for switchpoint accuracy is the small signal voltage
developed across the Hall element. This voltage is disproportionally small relative to the offset that can be
produced at the output of the Hall device. This makes
it diffi cult to process the signal and maintain an accu-
rate, reliable output over the specifi ed temperature and
voltage range.
Chopper stabilization is a unique approach used to
minimize Hall offset on the chip. The patented Allegro
removes key sources of the output drift induced by
thermal and mechanical stress. This offset reduction
technique is based on a signal modulation-demodulation process. The undesired offset signal is separated
from the magnetically induced signal in the frequency
domain through modulation. The subsequent demodulation acts as a modulation process for the offset,
causing the magnetically-induced signal to recover its
original spectrum at the baseband level, while the dc
offset becomes a high-frequency signal. Then, using a
low-pass fi lter, the signal passes while the modulated
dc offset is suppressed.
The chopper stabilization technique uses a 170 kHz
high-frequency clock. The Hall element chopping
occurs on each clock edge, resulting in a 340 kHz
chop frequency. This high-frequency operation allows
for a greater sampling rate, which produces higher
accuracy and faster signal processing capability. This
approach desensitizes the chip to the effects of thermal and mechanical stress. The disadvantage to this
approach is that jitter, also known as 360° repeatability,
can be induced on the output signal. The sample-and-hold process, used by the demodulator to store and
recover the signal, can slightly degrade the signalto-noise ratio. This is because the process generates
replicas of the noise spectrum at the baseband, causing
a decrease in jitter performance. However, the improvement in switchpoint performance, resulting from the
reduction of the effects of thermal and mechanical
stress, outweighs the degradation in the signal-to-noise
ratio.
This technique produces devices that have an
extremely stable quiescent Hall element output voltage, are immune to thermal stress, and have precise
recoverability after temperature cycling. This technique is made possible through the use of a BiCMOS
process, which allows the use of low-offset and lownoise amplifi ers in combination with high-density
logic integration and sample-and-hold circuits. This
process is illustrated in the following diagram.
Output voltage in relation to sensed magnetic fl ux density.
Output on each channel independently follows the same
pattern of transition through B
through B
RP
.
followed by transition
OP
Channel B
Magne tic Field
at Hall Element E2
Channel A
Output Signal
at OUTPUTA
Channel B
Output Signal
at OUTPUTB
Quadrature output signal confi guration. The outputs of the two
output channels have a phase difference of 90º when used
with a properly designed magnet that has an optimal pole pitch
of twice the Hall element spacing of 1.0 mm.
This device requires minimal protection circuitry
during operation with a low-voltage regulated line.
The on-chip voltage regulator provides immunity
to power supply variations between 3.3 and 18 V.
Because the device has open-drain outputs, pull-up
resistors must be included.
If protection against coupled and injected noise is
required, then a simple low-pass fi lter on the supply
(RC) and a fi ltering capacitor on each of the outputs
may also be needed, as shown in the unregulated
supply diagram.
For applications in which the device receives its power
from unregulated sources, such as a car battery, full
V
Supply
protection is generally required to protect the device
against supply-side transients. Specifi cations for such
transients vary for each application, so the design of
the protection circuit should be optimized for each
application.
For example, the circuit shown in the unregulated
supply diagram includes a Zener diode that offers high
voltage load-dump protection and noise fi ltering by
means of a series resistor and capacitor. In addition, it
includes a series diode that protects against high-volt-
The device must be operated below the maximum junction
temperature of the device, T
. Under certain combinations of
J(max)
peak conditions, reliable operation may require derating supplied power or improving the heat dissipation properties of the
application. This section presents a procedure for correlating
factors affecting operating TJ. (Thermal data is also available on
the Allegro MicroSystems Web site.)
The Package Thermal Resistance, R
, is a fi gure of merit sum-
θJA
marizing the ability of the application and the device to dissipate
heat from the junction (die), through all paths to the ambient air.
Its primary component is the Effective Thermal Conductivity,
K, of the printed circuit board, including adjacent devices and
traces. Radiation from the die through the device case, R
relatively small component of R
. Ambient air temperature,
θJA
θJC
, is
TA, and air motion are signifi cant external factors, damped by
overmolding.
The effect of varying power levels (Power Dissipation, PD), can
be estimated. The following formulas represent the fundamental
relationships used to estimate TJ, at PD.
PD = VIN × I
ΔT = PD × R
IN
θJA
(2)
(1)
TJ = TA + ΔT (3)
Example: Reliability for VCC at TA = 150°C, package L, using
minimum-K PCB
Observe the worst-case ratings for the device, specifi cally:
R
140 °C/W, T
θJA =
I
CC(max) = 6
mA.
Calculate the maximum allowable power level, P
J(max) =
165°C, V
CC(max) = 18
V, and
D(max)
. First,
invert equation 3:
ΔT
max
= T
– TA = 165 °C – 150 °C = 15 °C
J(max)
This provides the allowable increase to TJ resulting from internal
power dissipation. Then, invert equation 2:
P
D(max)
= ΔT
max
÷ R
= 15°C ÷ 140 °C/W = 107 mW
θJA
Finally, invert equation 1 with respect to voltage:
V
CC(est)
= P
D(max)
÷ I
= 107 mW ÷ 6 mA = 18 V
CC(max)
The result indicates that, at TA, the application and device can
dissipate adequate amounts of heat at voltages ≤V
Compare V
able operation between V
R
. If V
θJA
V
is reliable under these conditions.
CC(max)
CC(est)
CC(est)
to V
≥ V
. If V
CC(max)
CC(est)
CC(max)
CC(est)
and V
CC(max)
, then operation between V
≤ V
CC(max)
requires enhanced
.
CC(est)
, then reli-
CC(est)
and
For example, given common conditions such as: TA= 25°C,
V
= 12 V, I
CC
PD = VCC × I
ΔT = P
T
= TA + ΔT = 25°C + 7°C = 32°C
J
A worst-case estimate, P
able power level (V
at a selected R
Dimensions in inches
Millimeters in brackets, forreference only
Case dimensions exclusive ofmold flash orgate burrs
Mold flash .010 [0.25]MAX, gate burr.008 [0.20]MAX, dambar protrusion.004 [0.10]MAX
Exact case and leadconfiguration at supplierdiscretion withinlimits shown
A
Dambar removal protrusion (8X)
B
Ejector mark on oppositeside
C
ActiveArea Depth .0165 [0.42] NOM
Hall elements E1, E2(not to scale)
Preliminary dimensions, for reference only
Dimensions in millimeters
U.S. Customary dimensions (in.) in brackets, for reference only
(reference JEDEC MS-012 AA)
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
A
Terminal #1 mark area
B
Reference pad layout (reference IPC SOIC127P600-8M);
adjust as necessary to meet application process requirements
C
Active Area Depth 0.40 [0.016]
D
Hall elements E1, E2 (not to scale), U.S. Customary
dimensions controlling
The products described herein are manufactured under one
or more of the following U.S. patents: 5,045,920; 5,264,783;
5,442,283; 5,389,889; 5,581,179; 5,517,112; 5,619,137; 5,621,319;
5,650,719; 5,686,894; 5,694,038; 5,729,130; 5,917,320; and other
patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time
to time, such de par tures from the detail spec i fi ca tions as may be
required to permit improvements in the per for mance, reliability,
or manufacturability of its products. Before placing an order, the
user is cautioned to verify that the information being relied upon is
current.
Allegro products are not authorized for use as critical components in life-support devices or sys tems without express written
approval.
The in for ma tion in clud ed herein is believed to be ac cu rate and
reliable. How ev er, Allegro MicroSystems, Inc. assumes no re spon si bil i ty for its use; nor for any in fringe ment of patents or other
rights of third parties which may result from its use.