▪ Two matched Hall effect switches on a single substrate
▪ Sensor Hall element spacing approximately 1 mm
▪ Superior temperature stability
▪ 3.3 to 18 V operation
▪ Integrated ESD diode from OUTPUT and VCC pins
The A3425 is a dual–output-channel, bipolar switch with
each channel comprising a separate complete Hall-effect
sensor circuit with dedicated Hall element and separate digital
output for speed and direction signal processing capability. The
independent Hall elements (E1 integrated with OUTPUTA, and
E2 integrated with OUTPUTB) are photolithographically aligned
to better than 1 μm. Maintaining this accurate mechanical
location between the two active Hall elements eliminates the
major manufacturing hurdle encountered in fine-pitch detection
applications. The A3425 is a highly sensitive, temperature-stable
magnetic sensing device, which is ideal for use in ring magnetbased speed and direction systems used in harsh automotive
and industrial environments.
The A3425 contains two independent Hall effect switches, and
has a monolithic IC that accurately locates the two Hall elements,
E1 and E2, approximately 1 mm apart. The digital outputs are
90º out of phase so that the outputs are in quadrature, with the
proper ring magnet design. This allows for easy processing of
speed and direction signals. Extremely low-drift amplifiers
guarantee symmetry between the switches to maintain signal
Not to scale
V
Supply
Continued on the next page…
T ypical Application
100 Ω
0.1 uF
Using unregulated supply
VOUTPUTB
VOUTPUTA
2
OUTPUTA
A3425
1
VCC
GND
OUTPUTB
4
3
A3425DS-Rev. 7
Ultra-Sensitive Dual-Channel Quadrature
A3425
Description (continued)
quadrature. The patented chopper stabilization technique cancels
offsets in each channel, and provides stable operation over the
operating temperature and voltage ranges. An on-chip regulator
allows the use of this device over a wide operating voltage range.
The A3425 is available in a plastic 8-pin SOIC surface mount
package (L) and a plastic 4-pin SIP (K), both in two operating
temperature ranges. Each package is available in a lead (Pb) free
version with 100% matte tin plated leadframe.
When operating at maximum voltage, never exceed maximum junction temperature, T
2
Device will survive the current level specifi ed, but operation within magnetic specifi cation cannot be guaranteed.
3
Short circuit of the output to VCC is protected for the time duration specifi ed.
4
Maximum specifi cation limit is equivalent to I
5
Magnetic fl ux density, B, is indicated as a negative value for north-polarity magnetic fi elds, and as a positive value for south-polarity
OP(A)
+ B
RP(A), BOP(B)
OP(A)
RP(A)
+ B
– B
– B
RP(B)
OP(B)
RP(B)
B
, B
OP(A)
B
, B
RP(A)
B
, B
HYS(A)
SYMA, SYM
SYM
AB(OP)
SYM
AB(RP)
5
B
, B
OP(A)
B
, B
RP(A)
B
, B
HYS(A)
SYMA, SYM
SYM
AB(OP)
SYM
AB(RP)
CC(max)
OP(B)
RP(B)
HYS(B)
OP(B)
RP(B)
HYS(B)
B
B
+ 3 mA.
–735G
–35–7–G
51640 G
–40–40G
–30–30G
–30–30G
–730G
–30–7–G
51435 G
–35–35G
–25–25G
–25–25G
. Refer to power derating curve charts.
J(max)
magnetic fi elds. This so-called algebraic convention supports arithmetic comparison of north and south polarity values, where the
relative strength of the fi eld is indicated by the absolute value of B, and the sign indicates the polarity of the fi eld (for example, a
–100 G fi eld and a 100 G fi eld have equivalent strength, but opposite polarity).
When using Hall effect technology, a limiting factor
for switchpoint accuracy is the small signal voltage
developed across the Hall element. This voltage is disproportionally small relative to the offset that can be
produced at the output of the Hall device. This makes
it diffi cult to process the signal and maintain an accu-
rate, reliable output over the specifi ed temperature and
voltage range.
Chopper stabilization is a unique approach used to
minimize Hall offset on the chip. The patented Allegro
removes key sources of the output drift induced by
thermal and mechanical stress. This offset reduction
technique is based on a signal modulation-demodulation process. The undesired offset signal is separated
from the magnetically induced signal in the frequency
domain through modulation. The subsequent demodulation acts as a modulation process for the offset,
causing the magnetically-induced signal to recover its
original spectrum at the baseband level, while the dc
offset becomes a high-frequency signal. Then, using a
low-pass fi lter, the signal passes while the modulated
dc offset is suppressed.
The chopper stabilization technique uses a 170 kHz
high-frequency clock. The Hall element chopping
occurs on each clock edge, resulting in a 340 kHz
chop frequency. This high-frequency operation allows
for a greater sampling rate, which produces higher
accuracy and faster signal processing capability. This
approach desensitizes the chip to the effects of thermal and mechanical stress. The disadvantage to this
approach is that jitter, also known as 360° repeatability,
can be induced on the output signal. The sample-and-hold process, used by the demodulator to store and
recover the signal, can slightly degrade the signalto-noise ratio. This is because the process generates
replicas of the noise spectrum at the baseband, causing
a decrease in jitter performance. However, the improvement in switchpoint performance, resulting from the
reduction of the effects of thermal and mechanical
stress, outweighs the degradation in the signal-to-noise
ratio.
This technique produces devices that have an
extremely stable quiescent Hall element output voltage, are immune to thermal stress, and have precise
recoverability after temperature cycling. This technique is made possible through the use of a BiCMOS
process, which allows the use of low-offset and lownoise amplifi ers in combination with high-density
logic integration and sample-and-hold circuits. This
process is illustrated in the following diagram.