Akai LCT2662 Service Manual

SERVICE MANUAL

Model:

LCT2662

Safety Instructions
Features & Specifications
Block Diagram
Wiring Diagram
Disassembly
Schematic & Component Diagrams
Bill of Material
Pin Descriptions
Exploded View Diagram

This manual is the latest at the time of printing, and does not
include the modification which may be made after the printing,
by the constant improvement of product.

I. Safety Instru ctions

CAUTION

RISK OF ELECTRIC SHOCK

DO NO T OPEN

The l ightning fla sh w ith arro whead symb ol,
within an equilateral triangle, is intended to alert
the user to the presence of uninsulated “dangerous
voltage” within the prod uct’s enclosure that may
be of sufficient magnitude to constitute a risk of
electric shock to persons.

CAUTIO N: TO REDUCE THE RISK OF ELECTRIC
SHO CK, DO NOT REMOVE COVER (OR BACK). NO
USER-SERVI CEABLE PART S INSIDE. REFER
SERVICING TO QUALIFI ED SERVICE PERSONNEL
O NLY.

PRECAUTIONS DURING SERVICING

1. In a ddition to safety, other parts and assemblies are
speci fied for conformance with such regulations as
those applyi ng to spurious radiation. These must
also be replaced only with specified replacements.
Exampl es: RF converters, tuner units, antenna
selection switches, RF cables, noise-blocking
capacitors, noise-bl ocking filters, etc.

2. Use sp ecified internal Wiring. Note especially:

1) Wires covered with PVC tubing

2) Do uble insulated wires

3) Hig h voltage leads

3. Use specified i nsulating materials for hazardous
live pa rts. Note especially:

1) In sulating Tape

2) PVC tubing

3) Spa cers (insulating barriers)

4) Insulating sheets for transistors

5) Plastic screws for fixing micro switches

4. When replacing AC primary side compo nents
(tran sformers, power cords, n oise blocking
capacitors, e tc.), wrap ends of wires securely about
the te rminals before soldering.

5. Make sure that w ires do not contact heat generating
parts (he at sinks, oxide metal film resistors, fusible
resistors, etc.)

6. Check if replace d wires do not contact sharply edged
or po inted parts.

7. Make sure that foreign objects (screws, solder
drop lets, etc.) do not remain insi de the set.

MAKE YOUR CONTRIBUTION TO PROTECT THE
ENVIR ONMENT

Used batteries with the ISO symbol
for recycling a s well as small
accumu lators (rechargeable batteries), mini-batteries
(cell s) and starter batteries should not be thrown
into the garbage can.
Please leave them at an appropriate depot.

The excla mation po int wi thin a n equilateral
tri angle is intended to a lert th e user to the
presence of important operating and maintenance
(servici n g) instr u ct i o n s i n th e liter a tu re
accompanying the appliance.

W ARNING:

Before servicing this TV receiver, read the X-RAY
RADIATION PRECAUTION, SAFETY INSTRUCTION
and PRODUCT SAFETY NOTICE.

X-RA Y RADIATION PRECAUTION

1. Excessively high can prod uce potentially hazardous
X-RAY RADIATION. T o avoid such hazards, the high
volta ge must not exceed the specified limit. The
normal va lue of the high voltage of this TV receiver
is 2 7 KV at zero bean current (minimum brightness).
The high voltage must not exceed 30 KV under any
circu mstances. Each time when a re ceiver requires
servici ng, the high voltage should be checked. The
readi ng of the high voltage is re commended to be
reco rded as a part of the service record, It is
important to u se an accurate and reliable high
voltage meter.

2. The only source of X-RAY RADIATION in this TV
receiver is the picture tube. For con tinued X-RAY
RADIATION protectio n, the replacement tube must be
exactly the sa me type as specified in th e parts list.

3. Some parts in this TV receiver have special safety
related characteristics fo r X-RADIATION protection.
For continued safety, the parts replacement should
be under taken only afte r referring the PRODUCT
SAFETY NOTICE.

SAFETY IN STRUCTION

The se rvice should not be attempted by anyone
unfamiliar with the ne cessary instructions on this TV
receiver. The fo llowing are the necessary instructions
to be ob served before servicing.

1. An isolation transformer shoul d be connected in the
power li ne between the receiver and the AC line
when a service is performed on the primary of the
conve rter transformer of the set.

2. Comply wi th all caution and safety related provided
on th e back of the cabinet, inside the cabinet, on the
chassis or p icture tube.

3. T o avoid a shock hazard, always discharge the
pictu re tube's anode to the chassis g round before
removi ng the anode cap.

- 2 -

4. Completely discharge the high potential voltage of the
picture tube before handli ng. The picture tube is a
vacuum and if bro ken, the glass will explode.

5. When rep lacing a MAIN PCB in the cabinet, always
be certai n that all protective are installed properly
such as control knobs, adjustment co vers or shields,
barri ers, isolation resistor networks etc.

6. When se rvicing is required, observe the original lead
dressing. Extra precau tion should be given to assure
correct lead dressing in the high voltage area.

7. Keep wires away from high voltage or high te mpera
ture components.

8. Befo re returning the set to the customer, al ways
perform an AC leaka ge current check on the exposed
meta llic parts of the cabinet, such as anten nas,
termin als, screwheads, metal overlay, control shafts,
etc., to be sure the set is safe to operate without
danger of electrica l shock. Plug the AC line cord
directly to the AC outlet (do not use a line isolation
transformer d uring this check). Use an AC voltmeter
havin g 5K ohms volt sensitivity or more in the
following manner.
Conne ct a 1.5K ohm 10 watt resistor paralleled by a

0.15µF AC type capacito r, between a good earth
ground (water pipe, conductor etc.,) and the exposed
metallic parts, one at a time.
Measure the AC vol tage across the combination of
the 1 .5K ohm resistor and 0.15 uF capacitor. Reverse
the AC p lug at the AC outlet and repeat the AC
volta ge measurements for each exposed metallic
part.
The me asured voltage must not exceed 0.3V RMS.
This correspo nds to 0.5mA AC. Any value exceeding
this limit constitutes a potential shock hazard and
must be corrected immediately.
The resistance measurement should be done
betwe en accessible exposed metal parts and power
cord plug prongs with the power switch "ON". The
resi stance should be more than 6M ohms.

PRODUCT SA FETY NOTICE

Many e lectrical and mechanical parts in this TV
receiver have special safety-related characteristics.
These characteristics are offer passed unnoticed by
visual spection and the protection afforded by them
cannot necessari ly be obtained by using replacement
compon ents rates for a higher voltage, wattage, etc.
The replacemen t parts which have these special
safety characteristics are identified by marks on
the schematic diagram and on the parts list.
Before replacin g any of these components, read the
parts list in thi s manual carefully. The use of
substitute re placement parts which do not have the
same safety characteristics as specified in the parts
list may cre ate shock, fire, X-RAY RADIATION or
other h azards.

Good earth ground
such as the water
pipe, conductor,
etc.

AC Leak age Current Check

AC VOLTMETER

Place this probe
on eac h e x­pos ed metallic
part

- 3 -

V

FEATURES

●POWER SUPPLY:AC 90~264V 50/60Hz

●MULTI TV SYSTEM:NTSC M

●MULTISTANDARD SOUND PROCESSORS:,BTSC+SAP

●MULTI VEDEO SYSTEM:PAL/NTSC/SECAM

●VERSATILE INPUT SOURCES:

TV,AV1,AV2,S-VIDEO,YCbCr,YPbPr,DVI,PC(ANALOG)

●FULL FUNCTION REMOTE CONTROLLER

●EXCELLENT SOUND EFFECT WITH VOLUME,TRABLE, BASS, BALANCE,

AVC ADJUSTABLE, AUDIO MODE, SPACIAL EFFECT, EQUALIZER

●SMART SOUND & PICTURE MODE SET:
PERSONAL,CINEMA, SPEECH, MUSIC; STANDARD,PERSONAL,BRIGHT,

MILD

●ADAPTIVE 2/4 LINE COMB FILTER FOR PAL/NTSC

●VTR FOR WEAK AND DISTORETED SIGNAL FROM VIDEO TAPE

RECORDER

●AUTOMATICALLY TURN OFF THE SET WHEN SIGNAL ABSENT LONGER
THAN 10 MINUTES

●216 CHANNELS

●BLUE SCREEN DISPLAY

●CC / V-CHIP

●FREEZE PICTURE

●PROGRAM LABEL

●SLEEP

●SCREEN SIZE CHANGE

●STANDBY

●CHANNEL SWAP

●VOG PIP (AT PC 1280X768/60Hz, TV WIDE FORMAT)

GENERAL SPECIFICATION:
PART1:TV SET

POWER CONSUMPTION
TV RECEIVE SYSTEM

VIDEO SYSTEM

ISION INTERMEDIATE
FREQUENCY
INTER-CARRIER FREQUENCY

180Watt（ MAX.）

≤ 3Watt(STBY)
NTSC M
MULTI PAL/ SECAM/ NTSC

45.75MHz

CHROMA IF FREQUENCY

CHANNELS RECEIVED

TUNING MODE

AV IN/OUT SPECIFICATION

ANTENNA INPUT IMPEDANCE

OSD LANGUAGE

AUDIO OUTPUT POWER
LED INDICATORS
HAND SET POWER SUPLY

4.5MHz(BTSC)

42.17MHz

USA 216 Channel
(AIR 2-83 Channel)

(CATV(STD IRC HRC) 1-134

Channel)
PLL SYSTEM

1 AV1 IN,1 AV2 IN,1 S-VIDEO IN

YCbCr IN, YPbPr IN AV IN/OUT

1 AV OUT
Y/C IN -Y：1.0±0.2V

C:0.7 V

P-P

75Ω

VIDEO IN----1.0 ±0.2V

P-P

P-P

75Ω

75Ω

AUDIO IN----Approx,500mV
VIDEO OUT----1.0±0.2 V

P-P

75Ω

AUDIO OUT----Approx,400mV
RGB IN : ≤0.7 V

P-P

75 OHM

ENGLISH/SPAINISH/ GERMAN /

FRENCH PORTUGUES/

NOTE: The OSD language has only 5 language.

6Wx2 (1KHz, 0.5Vrms, 10%THD)

Continue shine POWER ON

Flash standby
BATTERY 1.5V （AAA）x2

PART2:PC RESOLUTION

ANALOG RGB IN 0.7 V

RESOLUTION V.Feq.(Hz) h.Feq.(Hz) GRAPHIC MODE

640X480 59.940 31.469 VGA

800X600 60.317 37.879 VGA

1024X768 60.004 48.363 VGA

1280X720 59.870 47.776 VGA

P-P

PART3:PANEL

Brand & Model CHIMEI/V270W1-L03
Resolution 1280X720
Displayable Colour 16.7MHz
Surface Hard Coating + Anti-Radiation
Viewing Angle (H/V) 170° (Hor) / 170° (Ver)
Display Response Time 25ms
Contrast Ratio 1:600
Brightness 550nit
Aspect 16;9
Lamp Life 50,000Hrs
Bad Pixel Quality (Bright/Dark/Total) 2/6/8

7654321

Block Diagram

8

U6

TELETEXT CCD/VCHIP

EEPRAM

D

U4

TUNER

AV IN

S_VIDEO IN

YCrCb

U24

VIDEO

SCART

C

PC

YPrPb

B

SWITCH

U3

SYNC

U10

SWITCH

DVI

VIDEO

DECODER

U11

ADC

U1

DAC

U7U8

UC

U14

BUFFER

U9

SDRAM

DEINTERLACER

U18

UB

BUFFER

U21

SWITCH

I2C

U5

EEPRAM

FLASH MEMERY

U17

CPU/SCALER

UD

RESET

U2

BUFFER

UE

AMP

LVDS

U19

LCD PANEL

D

C

B

A

TV AUDIO

AV AUDIO

SCART AUDIO

HDTV AUDIO

POWER

1 2 3 4 5 6 78

24VDC

11----20VDC
5VDC
5VDC_SB
3VDC_SB

STAND BY

AUDIO

DECODER

POWER

AMP

A

7654321

Wiring Diagram

OVCC CVCC PVCC AVCC

97

18

D

AVCC

R1

96

EXT_RES

510R

DVI1

DATA2/4_SHLD

DDC_DATA

C

B

VCC

DATA1/3_SHLD

H_PLUG_DET

DATA0/5_SHLD

CLK_SHLD

DVI

IC1

VIN3VOUT

LT1117-3.3V

SHELL1

DATA2­DATA2+

DATA4-

DATA+

DDC_CLK
A_VSYNC

DATA1­DATA1+

DATA3­DATA3+

+5V

GND

DATA0­DATA0+

DATA5­DATA5+

CLK+
CLK-

A_RED

A_GREEN

A_BLUE

A_HSYNC

A_GND

SHELL2

1

GND

31

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

25(C1)
26(C2)
27(C3)
28(C4)
29(C5)

32

47uF/16V

GSCLV
DDCDV

DVC1

L2

2

112

22uH

L3

2

C2

C1

0.1

22uH

L4

22uH

L5

22uH

GSCLV
DDCDV

7,9

3,7,9

9

OVCC

PVCC

AVCC

CVCC

OVCC OVCC OVCC OVCC OVCC CVCC CVCC CVCC

C11

C12

C13

0.1

0.1

0.1

DIGSEL

PD

C14

0.1

CVCC

R2

1K

R187
0

C15

C16

0.1

0.1

R10
1K_NS

90

RX0p

91

RX0m

85

RX1p

86

RX1m

80

RX2p

81

RX2m

93

RXCp

94

RXCm

100

OCK_INV

4

PIXS

1

DFO

7

STAG_OUT

3

ST

9

PDO

2

PD

99

RSVD

CVCC

C17

C18

C19

0.1

0.1

0.1

OVCC578OVCC457OVCC343OVCC229OVCC1

OGND119OGND228OGND345OGND458OGND576GND15GND239GND368PGND98AGND179AGND283AGND387AGND489AGND5

82

6

VCC367VCC238VCC1

PVCC

U1

AVCC495AVCC388AVCC284AVCC1

8

SCDT

10

QE0

11

QE1

12

QE2

13

QE3

14

QE4

15

QE5

16

QE6

17

QE7

20

QE8

21

QE9

22

QE10

23

QE11

24

QE12

25

QE13

26

QE14

27

QE15

30

QE16

31

QE17

32

QE18

33

QE19

34

QE20

35

QE21

36

QE22

37

QE23

49

QO0

50

QO1

51

QO2

52

QO3

53

QO4

54

QO5

55

QO6

56

QO7

59

QO8

60

QO9

61

QO10

62

QO11

63

QO12

64

QO13

65

QO14

66

QO15

69

QO16

70

QO17

71

QO18

72

QO19

73

QO20

74

QO21

75

QO22

76

QO23

ODCK

DE
VSYNC
HSYNC

CTL1
CTL2
CTL3

92

SII161

R11

44
46
47
48

40
41
42

RP1

RP3 47

RP2 47

RP4

RP5 47

RP6 47

1

1

GB0

47

GB1
GB2
GB3
GB4
GB5
GB6
GB7
GG0
GG1
GG2
GG3

47

GG4
GG5
GG6
GG7
GR0
GR1
GR2
GR3
GR4

47

R12

T2

1

T1

2

GR5
GR6
GR7

R13 47_NS

T3

GCLK

GFBK

6,7,8

GVS

GRAPHIC

47

DVI-DE

8

D

C

B

A

AVCC AVCC AVCC AVCC AVCC PVCC PVCC

C3

C4

C5

0.1

0.1

1 2 3 4 5 6 78

0.1C80.1C90.1

C7

0.1C60.1

A

7654321

8

D

C

CN14

1
2
3
4
5

TVVIN

GND

BLANKING

GND

TV-AUDIO

TV-VIN

BLANKING

D

C

CON6

B

CN12

CON6

R28 0

AV2_L

6

SD

5

R41 0

AV2_R

4

SL

3

SD

2

SR

1

RCA1

1
2
3

B

A

A

1 2 3 4 5 6 78

7654321

8

CON5 is for LCD control (J24's) supplement,

D

PWCS0#

11

CLK

VCC

PWD0

3

PWD1
PWD2
PWD3
PWD4
PWD5
PWD6
PWD7

MEM_BUS

9,10

2D

7

3D

8

4D

13

5D

14

6D

17

7D

18

8D

74HC374

1D

4

GND

1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
OE

C

U2

VDD

20

2
5
6
9
12
15
16
19
1
10

MUTE

R38

R39

R40

LCDON
BKLON
PD

LVDSON

680R

680R
0

11
11
4,9

12

DIGSEL

LED1

GREEN

LED2

DIODE

MUTE

DIGSEL

CN5

1
2

CON2

BUF-HS

BUF-HS

22R

R36

C25

2.2K

22P

7

R34

U3

1
2
3
4
5
6
7 8

74hc14a

7

HSYNC

R35

BUF-VS

7

BUF-VS

1

22R

C26

R37

22P

2.2K

VFF

14
13
12
11
10
9

VSYNC

7

D

C

RCA1

1,7,9

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

DDCD

2

D1

K

R29
10K

7

DDCC

D2

R30
10K

7,1 7,1 7,1

RED

D3

GREEN

D4

BLUE

D5

BUF-HS

D6

R44
2K

BUF-VS

D7

R14

2

SAGND

1

R45
2K

0

R184 10K

AV2-IN

VIN4

YSOG

AV2-IN

AV2-IN
VIN4

YSOG

1
2
3
4
5
6
7

U21

0Y

2Y

YOUT

3Y

1Y

INH

VEE

VSS8B

VDD

XOUT

CD4052

VCC

VCC

C234

16

0.1

15

2X

14

1X

13
12

0X

11

3X

10

A

9

DEN
DDEN
DVI-DE

A

A

B1

B1

3

B

1

A

BAV99L

BAV99L

BAV99L

BAV99L

BAV99L

BAV99L

BAV99L

R223
10K

R225
10K

B

VIN YSOG

R224
10K

A

A

1 2 3 4 5 6 78

7654321

VAA

VAA

R64

R62

D

C62

R59

100

4.7

RST1#

4.7

1

R204

L42
FB

VAA

100

GND GND

VAA

GND

0

R202

5.6K

R205
22K

C208
100uF/16V

R66

VAA

VOUT

VOUT

VINHS

VINVS

SDA
SCL

RST1#

C246

OUT

GND

2

VOUT

4

C

+12

L41
FB

3

C249
100uF/16V

IC9
7805

IN

B

A

5.6K

R63
22K

GND GND

R203

47

Q2
9014

R206
470

4,6,8,9

C20

C244

0.1

0.1

V33VT

47

Q3
9014

C63

R60
470

R207

R209 1K

0.1

470

VID_BUS

R80

24K

C60
20pF

R61

CVBS0

12.000M

SCL
SDA

X2

VAA

C38 is the bypass cap for Q1

C64

0.1

GND

470

SCL
SDA

VINVS
VINHS

C21

CVBS0

0.1

C61
20pF

Q1

R232
10K

9015

R208

5.6K

RST1#

VAA

CCVIN

VINHS
VINVS

SDA
SCL

R73 10K

GND GND

49

SCL

50

SDA

37

VSYNC

36

HSYNC

23

CVBS0

24

CVBS1

25

FILT

26

IREF

42

XO

41

XI

40

XGND

43

RESET

28

TEST

9

ADC0

10

ADC1

11

ADC2

12

ADC3

R65

0_NS

13
14

15

10

11

31

7

5

4

6

1

VDDA

22

V33VT

GNDA

U7

VIDEO

HS_IN
VS_IN

SDA
SCL

SEN
PREF

SMS
ASEL

VSSA

Z86229

39

U8

VDDC

13

GNDC

44

VDDP

38

SDA_NV
SCL_NV

GNDP

GREEN

CSYNC

GREEN

FRAME

BLUE

VDS
RED

BLUE

PWM

PW7
PW6
PW5
PW4
PW3
PW2
PW1
PW0

P0_7
P0_6
P0_5
P0_4
P0_3
P0_2

P1_5
P1_4
P1_3
P1_2
P1_1
P1_0

COR

VDD
SDO

RED

BOX

VAA

C65

0.1

GND

VAA

GND

12

16

GND

18

2

3

17

C67

8

R75

9

LPF

5264

6.8K

C77

35

34
33
32

1
30

8
7
6
5
4
3
2

21
20
19
18
17
16

R210 10K

52
51
48
47
46
45

29
27

15

DA

14

CL

GND

C78

6.8nF

C54

0.1

R31
10K

R192

R67 470

R193

R68 470

R194

R69 470

D13

IN4148

68nF

V33VT

0.1

470

470

470

R32

10K

V33VT

D14

IN4148

R196

R198

R200

GND

C71

75

R74

R76

75

GND

470

470

470

U6

5

6
7

8

SDA

SCL
TEST

VCC

GND

A2
A1

A0

24C16

33pF

C72

0.22

V-RED

C69
33pF

C73

0.22

C70
33pF

C74

0.22

4

3
2

1

V-RED

V-GRN

V-GRN

V-BLU

V-BLU

V-BOX

V-BOX

C75
33pF

VDD V33VT

L8
FB

U26 bypass cap

C80

100uF/16V

8

D

C

C22

0.1

B

A

1 2 3 4 5 6 78

7654321

8

VOUT

5

VOUT

RST1#

RST1#

5,6,9,10,11

SDA

S-CIN
S-YIN
SAGND
SAGND
SAGND
SAGND
SAGND
SAGND
SAGND

HD-Y1

HD-Y

HD-Pb1
HD-Pb

HD-Pr1

HD-Pr

AV-IN
SAGND

S-VIDEO1

5

X

2

GND

X

2

GND

X

2

GND

CON9

Y

Y

Y

SCL

1
2
3
4
5
6
7
8
9

D

CN3

2
1

CON2

C

B

A

SDA

SCL

SCL

14

15

13

VIN3

SCL

SDA

VIN2

CIN

VIN1

VIN4

Y2/G2

U2/B2

V2/R2

Y1/G1
U1/B1
V1/R1
FBIN1

XTALI

XTALO

CLK560FPDAT58CLK2024ASGND7ASGND64GND11APGND25APVDD26PLGND30YGND35CGND46SPGND51AFGND65ISGND68ISGND77ISGND80I2CSEL

V-BLU

S-B

V-GRN

S-G

V-RED

S-R

RGB/V

V-BOX

V-BOX

R251 6.8K

R245
0_NS

R246
0_NS

R247
0_NS

YY

YCb

YCr

AV-IN

S-CIN

S-YIN

0.1

VDD

2

TV-VIN

VIN4

VIN4

R52 75

GND

R53 75

GND

R54 75

GND

GRN

BLU

YY YCb YCr YCb2 YY2 YCr2

R212

R214

10K

10K

U5

5
6

7
8

SDA

SCL
TEST

VCC

GND

RRED
V-BOX1

A2
A1

A0

R216
10K

4
3

2
1

3.3uH

3.3uH

L11

3.3uH

R71 1.2K

R218
10K

TGND

GND

YSOG

R220
10K

R56 75L9

R57 75L10

R55

C58
20pF

C59
20pF

R49 2K

R50 75

R51 75

R58 75

75

GND

R222
10K

C55
330pF

C56
330pF

C57
330pF

C255 0.22

X1

20.25M

C27

0.68

C28

0.68

C31
1nF

C29

0.68

C30

0.68
C37

0.22

C38

0.22

C39

0.22

C256 0.22

C254

0.22

74

73

71

72

75

5

4

6

2
1
3

79

62

63

2

TV-VIN

G

B

R

1

1

1

SDA

SCL

C53

24C16

1 2 3 4 5 6 78

C32
1nF

VDD

C36

0.22

10

12

VDD

VDDCAP9GNDCAP

RST#

70

VOUT

U4
VPC3230D

C44
47nF

R248 0_NS

R249

0_NS

R250

0_NS

S1A
S2A

S1B
S2B

S1C
S2C

S1D
S2D

IN
EN

VSS

GND

C33
1nF

16

VCC

PI5V330

GND

8 U24

GND

2
3

5
6

11
10

14
13

1

15

VDD +5

29

52

36

45

CVDD

YVDD

PLVDD

SPVDD

4

DA

7

DB

9

DC

12

DD

69

AFVDD

V-BOX1

GND

76

BLU

GRN

RRED

ISVDD

VCC is 5V power supply from the power socket VDD is 3.3V digital power supply, +5 is 5V
analog power supply for U1 VPC3230D; VTT is 5V power supply for U2 FI1256M K 2 (TV Tuner)

GND

D

C52

C

0.1

C35
1nF

B

59

VREF

78

VREF

66

VRT

VSTBY

FFIE

FFWE

FFRST

FFRE
FFOE

Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0

UV7
UV6
UV5
UV4
UV3
UV2
UV1
UV0

LLC2

LLC

AVO

HCLP

HS
VS

INTLC

TEST

VGAV

OE#

67

19
20
21
22
23

31
32
33
34
37
38
39
40

41
42
43
44
47
48
49
50

27
28
54
55
56
57
53

16

17
18

47

47

L38

11R/100MHZ

YCr2
YCr
YCb2
B
YCb

C42
47nF

RP7

RP8

U22

BY
BX
CY
C
CX
INH
VEE
VSS C

CD4053

GNDGND GND GND

L39

11R/100MHZ

VDD

AY
AX

C43

C45

47nF

10uF

VINY7

VINY6

VINY5
VINY4
VINY3
VINY2
VINY1
VINY0

VINCK

VHREF
VINHS

VINVS

VIODD

R

B

G

A

YY2

YY

A
B

R185 10K

公司名称

+5

(VSTBY)

C48

0.1

VDD

C47
10uF

GNDGND

VID_BUS

C49

0.1

+5

C40

0.22

R186 1K

C76

0.1

C46
10uF

VIDEO BUS

+12

Q9

9014

深圳市凯欣达电子有限公司

深圳市车公庙泰然工业区

5,6,8,9

C51

C50

0.1

0.1

C34

C41

1nF

0.22

S/Y

210栋三楼EF座

公司地址

图名

图号

绘制

文件名

当前时间

04-CODER.SCH

4

版本号

校对

30TV

当前日期

2

审核

A.1

2003.06.12

A

7654321

8

8

D

VID_BUS

4,5,8,9

C

1,7,8

GRAPHIC

B

GRAPHIC

VINY7
VINY6
VINY5
VINY4
VINY3
VINY2
VINY1
VINY0

VINCK
VINHS
VINVS

GR7
GR6
GR5
GR4
GR3
GR2
GR1
GR0

GG7
GG6
GG5
GG4
GG3
GG2
GG1
GG0

GB7
GB6
GB5
GB4
GB3
GB2
GB1
GB0

GCLK
GFBK
GVS

UCA
PW1230

23

VG7

22

VG6

21

VG5

20

VG4

18

VG3

17

VG2

16

VG1

15

VG0

38

VR7

37

VR6

36

VR5

35

VR4

33

VR3

32

VR2

31

VR1

30

VR0

25

PVCLK

26

CREF

28

PVHS

27

PVVS

9

VB7

8

VB6

7

VB5

6

VB4

4

VB3

3

VB2

2

VB1

1

VB0

13

SVCLK

11

SVHS

12

SVVS

UCB
PW1230

100

GR7

99

GR6

98

GR5

97

GR4

95

GR3

94

GR2

92

GR1

91

GR0

89

GG7

88

GG6

87

GG5

86

GG4

84

GG3

83

GG2

82

GG1

81

GG0

79

GB7

78

GB6

76

GB5

75

GB4

73

GB3

72

GB2

71

GB1

70

GB0

68

GCLK

66

GHS

67

GVS

UCC
PW1230

UCF
PW1230

142

DR7

141

DR6

139

DR5

138

DR4

136

DR3

135

DR2

133

DR1

132

DR0

130

DG7

129

DG6

128

DG5

127

DG4

125

DG3

124

DG2

122

DG1

121

DG0

119

DB7

118

DB6

117

DB5

116

DB4

114

DB3

113

DB2

111

DB1

110

DB0

102

R86

DCLK

R87 47

104

DHS

103

R88 47

DVS

108

R89

DENR

106

DENG

107

DENB

145

DEN

161

VREFI

162

VREFO

160

COMP

153

Y/GA

150

U/BA

156

V/RA

159

RSET

VXX VDD

123

140

175

205

235

VDD5VDD34VDD93VDD

VDD

VDD

VDD

VDD

PVDD14PVDD29PVDD42PVDD54PVDD64PVDD69PVDD80PVDD90PVDD

VSS19VSS49VSS77VSS

VSS

VSS

VSS

VSS

PVSS10PVSS24PVSS39PVSS46PVSS57PVSS65PVSS74PVSS85PVSS96PVSS

112

134

187

219

251

47

47

BGND

GPR7
GPR6
GPR5
GPR4
GPR3
GPR2
GPR1
GPR0

GPG7
GPG6
GPG5
GPG4
GPG3
GPG2
GPG1
GPG0

GPB7
GPB6
GPB5
GPB4
GPB3
GPB2
GPB1
GPB0

DDHS
DDVS
DEN

PW1230E

C81

0.1

BGND

C110

0.1

R92
316

101

RP9
47

RP10
47

RP11
47

RP12
47

RP13
47

RP14
47

L43 FB

DEN 9

+3.3

109

120

131

PVDD

PVDD

PVDD

PVSS

PVSS

105

115

126

DISPLAY BUS (G-PORT)DE-INTERLACED

UCD
PW1230

NVA13

218

MA13
MA12
MA11
MA10

MA9
MA8
MA7
MA6
MA5
MA4
MA3
MA2
MA1
MA0

MD15
MD14

MCLKFB

VXX

C82

0.1

VZZVYY +2.5 +3.3

197

199

DPAVDD

DPDVDD

MPDVDD58MPAVDD60ADDVDD

DPAVSS

DPDVSS

MPDVSS59MPAVSS61ADDVSS

196

198

MD13
MD12
MD11
MD10

MD9
MD8
MD7
MD6
MD5
MD4
MD3
MD2
MD1
MD0

MRAS#
MCAS#

MWE#
MCLK

149

148

R86

470

DDCK

PW1230E

143

165

180

200

PVDD

PVDD

PVDD

PVDD

PVSS

PVSS

PVSS

PVSS

137

147

171

189

PW1230C

7,8,9

208

216

224

230

237

243

249

256

PVDD

PVDD

PVDD

PVDD

PVDD

PVDD

PVDD

PVDD

PVSS

PVSS

PVSS

PVSS

PVSS

PVSS

PVSS

PVSS

PVSS

193

202

212

222

228

233

240

246

253

C83

0.1

163

166

ADAVDD

ADGVDD

ADAVSS

ADGVSS

164

167

NVA12

221

NVA11

220

NVA10

215

NVA9

217

NVA8

214

NVA7

211

NVA6

209

NVA5

206

NVA4

203

NVA3

204

NVA2

207

NVA1

210

NVA0

213

NVD15

254

NVD14

250

NVD13

247

NVD12

244

NVD11

241

NVD10

238

NVD9

234

NVD8

231

NVD7

232

NVD6

236

NVD5

239

NVD4

242

NVD3

245

NVD2

248

NVD1

252

NVD0

255

NVRAS#

225

NVCAS#

226

NVWE#

227

NVCLK

229

NVCLK

223

C84

C85

0.1

0.1

151

154

157

VYY VZZ

AVD33B

AVD33G

AVD33R

AVS33B

AVS33G

AVS33R

152

155

158

C86

0.1

NVA13
NVA11

R81

NVA12

NVA10
NVA9
NVA8
NVA7
NVA6
NVA5
NVA4
NVA3
NVA2
NVA1
NVA0

NVCLK

NVRAS#
NVCAS#
NVWE#

SDA
SCL

RST1#

C87

C88

0.1

0.1

0

R82
0

SDA
SCL

RST1#

BGND

R90

3.3K
R91

3.3K

21
20

35
22
34
33
32
31
30
29
26
25
24
23

38

18
17
16

39
15

C112

20pF

C89

0.1

PW1230 MEMORY BUS

VDD

BSL1
BSL0

VCC1VCC3VCC9VCC14VCC27VCC43VCC

A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

CLK

RAS#
CAS#
WE#

UDQM
LDQM

VSS6VSS12VSS28VSS41VSS46VSS52VSS

VDD

X3

10MHz

C113
20pF

R191
10K

U9

146

201

R93

144

K4S641632C

40

2.2M

41

47
45

55

44
43

56

53
50
51
48
52

49

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10

CKEN

54

UCE
PW1230

CGMS
MVE

XTALI

XTALO

SDA
SCL

RST#
CSA2

CSA1
TEST

TSTCLK

TRST#
TCK
TDI
TDO
TMS

DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

CS#

53
51
50
48
47
45
44
42
13
11
10
8
7
5
4
2

37
19

NVD15
NVD14
NVD13
NVD12
NVD11
NVD10
NVD9
NVD8
NVD7
NVD6
NVD5
NVD4
NVD3
NVD2
NVD1
NVD0

VDD

MCUA7
MCUA6
MCUA5
MCUA4
MCUA3
MCUA2
MCUA1
MCUA0

MCUD7
MCUD6
MCUD5
MCUD4
MCUD3
MCUD2
MCUD1
MCUD0

MCUCS#

MCUWR#

MCUCMD

MCURDY

G-PORT

7,8,9

D

C

177
176
174
173
172
170
169
168

186
185
184
183
182
181
179
178

190
191
192
188

B

BGND BGND BGND BGND

A

VDD +3.3 VDD

C90

C91

C92

C93

C94

C95

0.1

0.1

0.1

0.1

0.1

1 2 3 4 5 6 78

C96

0.1

0.1

+2.5

C97

C98

C99

C100

C101

C102

0.1

0.1

0.1

0.1

0.1

C103

0.1

0.1

BGND

C104

0.1

C105

0.1

C106

0.1

C107

0.1

C108

0.1

C109

0.1

A

7654321

8

VDD1

VEE

C116

0.1

C122

0.1

C123

0.1

GRAPHIC

C117

0.1

C125

0.1

GND

G-PORT

GRAPHIC

C118

0.1

C126

0.1

G-PORT

GND

VDD

A.1

C119

0.1

C127

0.1

C128

0.1

1,6,8

D

C

6,8,9

B

A

SDA
SCL

HD-Y
HD-Y

D

HD-Pb
HD-Pb

HD-Pr
HD-Pr

C

VGASEL

9
9

GCOAST

PW1230E

6,8,9

6

PW1230C

9

FLASHEN

B

DDCC

3

1,9

GSCL

A

DDCD

1,3,9

SDA
SCL

L12
HfFB

1

X

Y

R94

2

75

GND

GND

GND

GND

GSCL

L13
HfFB

1

X

Y

R95

2

75

GND

L14
HfFB

1

X

Y

R96

2

75

GND

VGA

10

5

15

9

4

14

8

3

13

7

2

12

6

1

11

DB15

DDCD

DDCC

VGASEL

GCOAST

PW1230E

PW1230 CLK & SYNCs

FLASHEN

VDD

DDCC

GSCL

GSDA( )

VDD

1 2 3 4 5 6 78

DDCD

PIN9

PIN9

R107

3.3K

R108

3.3K

R109

3.3K
R110

3.3K

VDD

GND

HD-Y

HD-Pb

HD-Pr

R97
10K

VGABI

VGAGI

VGARI

VGAHS
VGAVS

D8

DIODE

VDD

R104

3.3K

VGAHS

R105

3.3K

VGAVS

L16
HfFB

R98 75

9

GND

L17
HfFB

GND

L15 HfFB

GND

UAB
74LV126

UAD
74LV126

10

UAC
74LV126

8 9

6
5

7

8

R33
10k

D9

R99 75

R100
75

13

U13
24LC21A

4

SCL
SDA

VCLK
VCC

DIODE

56

1112

VGA-B

VGA-G

VGA-R

TXD

RXD

DDCEN

GND

NC

NC
NC

VCC

VSS

Bypass cap for U9

C114

0.1

GND

HD-Pr
VGA-R

HD-Y
VGA-G

HD-Pb

11

VGA-B

10

14
13

15

2 3

VDD

R118

8.2K

R111

Q4

3.3K

VDD

9014

4
3

2

1

C129

0.1

2
3

5
6

1

1

UAA
74LV126

C130

0.1

VSS

16

S1A
S2A

S1B
S2B

S1C
S2C

S1D
S2D

IN
EN

VCC

GND

DA

VCC

DB

DC

PI5V330

DD

GND

8 U10

R119
1K

C131

0.1

R116
200

R117
200

4

7

9

12

BUF-VS

C138

0.1

C139

0.1

RED

GREEN

BLUE

DVC1

VCC

RED

GREEN

BLUE

VDD

VEE VEE

C136

C132

3.9nF
R106

1,3

C133
47nF

1,3

C134
47nF

C137

1,3

1nF

C135
47nF

HSYNC

3

VSYNC

BUF-HS

1,3

GNDGND

1,3

1

3

11
10

12

9

4

5

R3

R4

GSCLV

DDCDV

C120

0.1

U12
MAX232A

C1P

C1M

TIN1
TIN2

ROUT1
ROUT2

C2P

C2M

3.3K

3.3K

D10

DIODE

D16

DIODE

C121

0.1

39nF

3.3K

VCC

GND

TOUT1
TOUT2

RIN1
RIN2

VM

R6 0
R7 10K

VFF

AVD26AVD27AVD39AVD42AVD45AVD46AVD51AVD52AVD59AVD62VDD11VDD22VDD23VDD69VDD78VDD

33

FILT

57

SDA

56

SCL

55

A0

54

RAIN

48

GAIN

49

SOGIN

43

BAIN

30

HSYNC

31

VSYNC

29

COAST

58

REFBYP

37

MIDSCV

38

CLAMP

GND1GND10GND20GND21GND24GND25GND28GND32GND36GND40GND41GND44GND47GND50GND53GND60GND61GND63GND68GND

GND

VCC

16

15

14
7

13
8

C140

0.1

2

VP

6

C141

0.1

R5

U23

0

24LC21A

6

5
7

8

VDD1

U11
AD9883A

PCRXD

PCTXD

4

GND

SCL
SDA

VCLK
VCC

3

NC

2

NC

1

NC

35

79

PVD34PVD

70

RED7

71

RED6

72

RED5

73

RED4

74

RED3

75

RED2

76

RED1

77

RED0

2

GRN7

3

GRN6

4

GRN5

5

GRN4

6

GRN3

7

GRN2

8

GRN1

9

GRN0

12

BLU7

13

BLU6

14

BLU5

15

BLU4

16

BLU3

17

BLU2

18

BLU1

19

BLU0

67

80

RXD
TXD

R112 47
R113 47

66
65

R114 47

64

R115 47

10

UBC
74LV126

13

UBD
74LV126

1

UBA
74LV126

2 3

4

UBB
74LV126

5 6

89

1112

DATCK

HSOUT

SOGOUT

VSOUT

PW1230E

DDCK

DDHS

DDHS GPFBK

DDVS

9
9

CN9

1
2
3

CON3

L44

GPCLK

GPSOG

GPVS

GCLK

GFBK

GHSSOG

GVS

RP15
47

RP16
47

RP17
47

RP18
47

RP19
47

RP20
47

VFF

C115

0.1

Bypass caps for U10 and U11

GR7
GR6
GR5
GR4
GR3
GR2
GR1
GR0

GG7
GG6
GG5
GG4
GG3
GG2
GG1
GG0

GB7
GB6
GB5
GB4
GB3
GB2
GB1
GB0

FB

VDD1

7654321

8

GRAPHIC

GRAPHIC

D

VDD1

C143

C142

0.1

0.1

Bypass caps for U27

GVS
GHSSOG
GFBK
GCLK

GR7
GR6
GR5
GR4

GR3
GR2
GR1
GR0

VDD1

47

1A1

46

1A2

44

1A3

43

1A4

1

1OE

41

2A1

40

2A2

38

2A3

37

2A4

48

2OE

36

3A1

35

3A2

33

3A3

32

3A4

25

3OE

30

4A1

29

4A2

27

4A3

26

4A4

24

4OE

C

42

VCC7VCC18VCC31VCC

U14

LVC16244

GND4GND10GND15GND21GND28GND34GND39GND

45

VDD1

2

1Y1

3

1Y2

5

1Y3

6

1Y4

GPVS

8

2Y1

GPSOG

9

2Y2

GPFBK

11

2Y3

GPCLK

12

2Y4

GPR7

13

3Y1

GPR6

14

3Y2

GPR5

16

3Y3

GPR4

17

3Y4

GPR3

19

4Y1

GPR2

20

4Y2

GPR1

22

4Y3

GPR0

23

4Y4

BUFFERED GRAPHIC BUS

VXX

VYY is 2.5V display PLL power supply of U7,
VZZ is 2.5V memory PLL power supply of U7,

VCC

42

GG7

47

GG6
GG5
GG4

VDD1

C155

C156

0.1

0.1

B

Bypass caps for U28

6,7,9

PW1230E

PW1230E

GG3
GG2
GG1
GG0

GB7
GB6
GB5
GB4

GB3
GB2
GB1
GB0

1A1

46

1A2
1A3
1A4

1OE
2A1

2A2
2A3
2A4

2OE
3A1

3A2
3A3
3A4

3OE
4A1

4A2
4A3
4A4

4OE

VCC7VCC18VCC31VCC

U15

LVC16244

GND4GND10GND15GND21GND28GND34GND39GND

44
43

1

41
40
38
37

48

36
35
33
32

25
30

29
27
26

24

GPG7

2

1Y1

GPG6

3

1Y2

GPG5

5

1Y3

GPG4

6

1Y4

GPG3

8

2Y1

GPG2

9

2Y2

GPG1

11

2Y3

GPG0

12

2Y4

GPB7

13

3Y1

GPB6

14

3Y2

GPB5

16

3Y3

GPB4

17

3Y4

GPB3

19

4Y1

GPB2

20

4Y2

GPB1

22

4Y3

GPB0

23

4Y4

L21
FB

L22
FB

L23
FB

(G-PORT)

IC2
LT1117

VIN3VOUT

G-PORT1,6,7 6,7,9

VYY

VZZ

+2.5

2

ADJ

1

R128
300

VXX is 2.5V core power supply of U7 (PW1230)

VADJ125

BGND

R129
300

C165
47uF/16V

L24
FB

BGND

C166
47uF/16V

VXX

+2.5VZZVYY

BGND

C167
47uF/16V

VXX

C168
100uF

D

C

B

45

A

A

A.1

1 2 3 4 5 6 78

4,5,6,8

6,7,8

D

C

B

A

11

1,7
1,3,7

VID_BUS
G-PORT

PWXI

C186
20pF

Clock generation circuit

VCC1

R131

6.8K
R132

470

IR input circuit

R56 may not be stuffed

GCOAST

7

VDD1 VDD1

R135

3.3K

SCL

I2C pull-up resistors

VLL is 1.8V core power for U15

RST#

RST1#

PWMOUT

GSCL
DDCD
SCL
SDA

R134
1K

IRIN

VIDEO BUS

G-PORT

PWXO

X4

14.318

R130

2.2M

C187
20pF

GCOAST

R136

3.3K

SDA

RST#

RST1#

PWMOUT

GSCL

SCL
SDA

DDCD

R227

3.3K

KEY1

C173

0.1

C174

0.1

C179

0.1

C180

0.1

C185

0.1

SDA
SCL
RST1#

MEM BUS

MEM_BUS
D-PORT

D-VS

8

D-HS

R1420R143

CN10

1
2
3
4

CON4

A.1

3,10
11,12

D

C

0

B

A

7654321

MEMORY BUS

KEY6

KEY7

DISPLAY PORT

VLL

C169

0.1

VLL

C170

0.1

VDD1

C175

0.1

VDD1

C176

0.1

VDD1

C181

0.1

VPP

C182

0.1

C171

0.1

C172

0.1

C177

0.1

C178

0.1

C183

0.1

C184

0.1

AGND

D17

DIODE

D18

DIODE

PWCS0#

198

199

CS1

DCLKn

SW
FLASHEN
VGASEL
PW1230E
A

PWNMI

193

CS0

DRO7
DRO6
DRO5
DRO4
DRO3
DRO2
DRO1
DRO0

DGO7
DGO6
DGO5
DGO4
DGO3
DGO2
DGO1
DGO0

DBO7
DBO6
DBO5
DBO4
DBO3
DBO2
DBO1
DBO0

DRE7
DRE6
DRE5
DRE4
DRE3
DRE2
DRE1
DRE0

DGE7
DGE6
DGE5
DGE4
DGE3
DGE2
DGE1
DGE0

DBE7
DBE6
DBE5
DBE4
DBE3
DBE2
DBE1
DBE0

DCLK

DHS
DVS
DEN

68

SCART

BLANKING

NMI

TXD
RXD

R228
1K

KBD_BUS

6,7,8

129
130
131
132
133
134
135
136

119
120
121
122
125
126
127
128

111
112
113
114
115
116
117
118

96
97
98
99
100
101
102
103

88
89
90
91
92
93
94
95

76
77
78
79
80
81
82
83

107
106
109
108
110

7
7

1
2
7

7

3

PWNMI 10

TXD
RXD

SCART
SW

FLASHEN

VGASEL

PW1230E

A

BLANKING

VDD1

11

DRO7
DRO6
DRO5
DRO4
DRO3
DRO2
DRO1
DRO0

DGO7
DGO6
DGO5
DGO4
DGO3
DGO2
DGO1
DGO0

DBO7
DBO6
DBO5
DBO4
DBO3
DBO2
DBO1
DBO0

DRE7
DRE6
DRE5
DRE4
DRE3
DRE2
DRE1
DRE0

DGE7
DGE6
DGE5
DGE4
DGE3
DGE2
DGE1
DGE0

DBE7
DBE6
DBE5
DBE4
DBE3
DBE2
DBE1
DBE0

GND
DCLK
D-HS
D-VS
D-EN

RP27
47

RP28
47

RP29
47

RP30
47

RP31
47

RP32
47

RP33
47

RP34
47

RP35
47

RP36
47

RP37
47

RP38
47

R133 470
R138 47
R139 47_NS
R140 47_NS
R141 47

CN13
CON2

1

2

VPP

ROMOE#

PWD15

PWD14

PWD13

PWD12

PWD11

PWD10

PWD9

PWD8

PWD7

PWD6

PWD5

PWD4

PWD3

PWA19

PWA18

PWA17

PWA16

PWA15

PWA14

PWA13

PWA12

PWA11

PWA10

PWA9

PWA8

PWA7

PWA6

PWA5

PWA4

PWA3

PWA2

PWA1

104

123

140

171

208

165

167

164

173

174

175

A19

A18

VDDP

VDDP

A17

VDD3

VDD3

VDD3

VDD3

176

A16

A15

177

178

179

A14

A13

A12

182A8183A7184A6187A5188A4189A3190A2191A1192

180

181

A9

A11

A10

148

149

150

D15

D14

154D8155D7156D6157D5158D4159D3160D2161D1162D0163

151

152

153

D13

D12

D11

D10

PWD2

D9

PWD1

PWD0

ROMWE#

194

195

196

197

RD

WR

ROMOE

ROMWE

U17
PW113

VSS3

VSS3

VSS3

VSSP

VSSP

TEST

EXTRST28RESET

XT_IN

XT_OUT

TRST

TCK

TMS

TDI

TDO

PORTA7

PORTA6

PORTA5

PORTA4

PORTA3

PORTA2

PORTA1

PORTA0

PORTB764PORTB663PORTB562PORTB461PORTB360PORTB259PORTB158PORTB057PORTC746PORTC645PORTC544PORTC443PORTC342PORTC241PORTC140PORTC039RXD67TXD

105

124

141

172

166

168

142

139

169

170

147

146

145

144

143

200

201

202

203

204

205

206

207

)GSDA(

AGND

R234

3.3K

RST#

PWXI

PWXO

PWMOUT

SDA

SCL

DDCD

GSCL

IRIN

B1

S/Y

KEY7

KEY6

KEY5

KEY4

KEY3

KEY2

RST1#

KEY1

KEYBOARD BUS

R183
1K

VDD116VDD137VDD165VDD184VDD1

VYUV7
VYUV6
VYUV5
VYUV4
VYUV3
VYUV2
VYUV1
VYUV0

VCLK
VHS
VVS
VPEN
VFIELD

GRE7
GRE6
GRE5
GRE4
GRE3
GRE2
GRE1
GRE0

GGE7
GGE6
GGE5
GGE4
GGE3
GGE2
GGE1
GGE0

GBE7
GBE6
GBE5
GBE4
GBE3
GBE2
GBE1
GBE0

GCLK
GHSSOG
GVS
GPEN
GFBK

GCOAST

VSS117VSS138VSS166VSS185VSS1

137

185

138

186

VDD1

VDD1

VDD329VDD352VDD372VDD386VDD3

VSS1

VSS31VSS330VSS353VSS373VSS387VSS3

VLL

56
55
54
51
50
49
48
47

71
75
74

VHREF

70

VIODD

69

GPR7

27

GPR6

26

GPR5

CN6

1
2
3

CON3

DDEN

Q16

9015

)GSDA(

GPR4
GPR3
GPR2
GPR1
GPR0

GPG7
GPG6
GPG5
GPG4
GPG3
GPG2
GPG1
GPG0

GPB7
GPB6
GPB5
GPB4
GPB3
GPB2
GPB1
GPB0

GPCLK
GPSOG

GPVS
DDEN
GPFBK

GCOAST

VDD1

R226 1K

R137

3.3K

25
24
23
22
21
20

19
18
15
14
13
12
11
10

9
8
7
6
5
4
3
2

31
33
32
34
35

36

1 2 3 4 5 6 78

7654321

8

MEM_BUS

3,9

D

C

B

A

MEMORY BUS

PWA19
PWA18
PWA17
PWA16
PWA15
PWA14
PWA13
PWA12
PWA11
PWA10
PWA9
PWA8
PWA7
PWA6
PWA5
PWA4
PWA3
PWA2
PWA1

ROMOE#
ROMWE#

RST#

FCE#

PWA2
PWA4
PWA6

PWA9
PWA11

PWA12
PWA14

PWA17
PWA19

ROMOE#
PWD15
PWD14

PWD5
PWD4

PWD3
PWD2
PWD9

JP1

VDD1

ICE#

IA20
IA21

IRP#

JMP

4
2

R233 0

U17 bypass cap

U16 bypass cap

JMP1

JMP

1
3

R149

3.3K

R150

3.3K

R151

3.3K

R152

3.3K

VDD1

14

13

37

16

A18

17

A17

48

A16

1

A15

2

A14

3

A13

4

A12

5

A11

6

A10

7

A9

8

A8

18

A7

19

A6

20

A5

21

A4

22

A3

23

A2

24

A1

25

A0

28

OE#

11

WE#

12

RST#

26

CE#

R148

3.3K

VPP

WP#

VCC

U18

29LV800D

PROMJET1
PROMJET

1
3
5
7

9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59

BYTE#

A-DQ15

DQ14
DQ13
DQ12
DQ11
DQ10

DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

A20/NC
A19/NC

RY/BY#

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60

FVPP
FWP#

VDD1

47

PWD15

45

PWD14

43

PWD13

41

PWD12

39

PWD11

36

PWD10

34

PWD9

32

PWD8

30

PWD7

44

PWD6

42

PWD5

40

PWD4

38

PWD3

35

PWD2

33

PWD1

31

PWD0

29

10
9

15

27

VSS

46

VSS

FCE#

VDD1VDD1

PWA1
PWA3
PWA5
PWA7
PWA8
PWA10
IRP#
ICE#
PWA13
PWA15
PWA16
PWA18
IA20
IA21
ROMWE#

PWD7
PWD6
PWD13
PWD12

PWD11
PWD10

PWD1
PWD0PWD8

Short JP1 3-4 when writing flash

3

Short JP1 1-2 for write protect. For AMD single power flash,

1

this jumper is not used .

R144

3.3K
R145

3.3K

VDD1

C189

0.1

VDD1

VDD1

2

Short JP2 when using PROMJET or ICE ROM Emualtor,

4

open it when using flash normally.

VDD1

VDD1

C190

0.1

VDD1

SW3 NMI

C233

C232

D12
DIODE

0.1

47uF

R179

VDD1

SW1
NMI

C188

0.1

RNMI

R146

3.3K

RNMI

UDB
74ACT32

4
5

6

UDA
74ACT32

1

2

HD1

1
3

3

R153
200

2
4

R147

3.3K

PWNMI

RST#

PWNMI

RST#

HD2

0

R178
0_NS

D

9

C

B

A

1 2 3 4 5 6 78

7654321

8

KEY0
KEY2
KEY4
KEY6

KEY7
KEY5
KEY3
KEY1

KBD BUS

+12

C193

0.1

U18 bypass cap

+12 is 12V power supply

CN2

1
2
3

CON3

KBD_BUS

9

D

C

B

VDD1VDD1VDD1VDD1VDD1VDD1VDD1VDD1

D

VDD1

KBD1
KBD

1

2

3

4

5

6

7

8

9

10

R158
10K

R159
10K

R160
10K

R161
10K

R162
10K

R163
10K

R164
10K

R165
10K

+12

84

R169
10K

UEA
LM358

3
2

R168
10K

1

BKLIGHT1

R188
2K

VCC

BKLIGHT

R190
300R

C250

R154

R171
3K

510

Q7
T3904

R48
2K

100uF/16v

R155
0

R46
2K

R47

UDC
74ACT32

9

10

8

MOSFET1
MOSFET P

11223

R170
2K

Q5
9014

2K

R166
10K

C192

0.1

PWMOUT

C

R167
10K

VDD1

C196
47uF/16V

D11
1N4148

B

9
3

3

PWMOUT
BKLON

LCDON

PWMOUT
BKLON

LCDON

3

+12

M5V

LCDVCC

C195

0.1

R172

3.3K

C194

0.1

R173

3.3K

Q6
9014

Q8
J279

C197

1000uF/16v

A

A

1 2 3 4 5 6 78

7654321

8

9,11

D-PORT

D

VDD VOO VNN

C198

C199

C204

0.1

C200

0.1

0.1

C205

0.1

0.1

C

Bypass caps for U20

C203

0.1

Bypass caps for U21

B

VOO is 3.3V LVDS power for U20 and U21,

A

C201

0.1

AGND AGND

VNNVOOVDD

C206

0.1

AGNDAGND

C207

0.1

C202

0.1

DRE1
DRE2
DRE3
DRE4
DRE5
DRE6
DRE7

DGE0
DGE1
DGE2
DGE3
DGE4
DGE5
DGE6
DGE7

DBE0
DBE1
DBE2
DBE3
DBE4
DBE5
DBE6
DBE7

D-HS
D-VS
D-EN

DCLK

DRO0
DRO1
DRO2
DRO3
DRO4
DRO5
DRO6
DRO7

DGO0
DGO1
DGO2
DGO3
DGO4
DGO5
DGO6
DGO7

DBO0
DBO1
DBO2
DBO3
DBO4
DBO5
DBO6
DBO7

D-HS
D-VS
D-EN

DCLK

CON30

DISPLAY PORT

TTL1

DRO1

1 2

DRO3

3 4

DRO5

5 6

DRO7

7 8
9 10

DGO1

11 12

DGO3

13 14

DGO5

15 16

DGO7

17 18
19 20

DBO1

21 22

DBO3

23 24

DBO5

25 26

DBO7

27 28
29 30

D-HS D-EN

31 32

DCLK

33 34
35 36

HEADER 18X2_NS

DRE1
DRE3
DRE5
DRE7

DGE1
DGE3
DGE5
DGE7

DBE1
DBE3
DBE5
DBE7

TTL2

112
334
556
778
9910
111112
131314
151516
171718
191920
212122
232324
252526
272728
292930
313132
333334
353536

HEADER 18X2_NS

DRO0
DRO2
DRO4
DRO6

DGO0
DGO2
DGO4
DGO6

DBO0
DBO2
DBO4
DBO6

D-VS

DRE0

2

DRE2

4

DRE4

6

DRE6

8
10

DGE0

12

DGE2

14

DGE4

16

DGE6

18
20

DBE0

22

DBE2

24

DBE4

26

DBE6

28
30
32
34
36

LCDVCC

D

C

B

A

9,12

LVDSON

VDD

3

LVDSON

32

9

26

51

R0

52

R1

54

R2

55

R3

56

R4

3

R5

50

R6

2

R7

4

G0

6

G1

7

G2

11

G3

12

G4

14

G5

8

G6

10

G7

15

B0

19

B1

20

B2

22

B3

23

B4

24

B5

16

B6

18

B7

27

HSYNC

28

VSYNC

30

ENABLE

25

CNTRL

31

CLOCK

VCC1VCC

U19
DS90C383A

R/F

GND5GND13GND21GND29GND

17

VCC

53

VDD

32

9

26

51

R0

52

R1

54

R2

55

R3

56

R4

3

R5

50

R6

2

R7

4

G0

6

G1

7

G2

11

G3

12

G4

14

G5

8

G6

10

G7

15

B0

19

B1

20

B2

22

B3

23

B4

24

B5

16

B6

18

B7

27

HSYNC

28

VSYNC

30

ENABLE

25

CNTRL

31

CLOCK

VCC1VCC

U20
DS90C383A

R/F

GND5GND13GND21GND29GND

17

VCC

53

PWDN

LVDSON

PWDN

OUT0
OUT0

OUT1
OUT1

OUT2
OUT2

OUT3
OUT3

CLKOUT
CLKOUT

LVDSVC

LVDSGD
LVDSGD
LVDSGD

PLLVCC

PLLGND
PLLGND

OUT0
OUT0

OUT1
OUT1

OUT2
OUT2

OUT3
OUT3

CLKOUT
CLKOUT

LVDSVC

LVDSGD
LVDSGD
LVDSGD

PLLVCC

PLLGND
PLLGND

TXE0PDRE0

47

TXE0M

48

TXE1P

45

TXE1M

46

TXE2P

41

TXE2M

42

TXE3P

37

TXE3M

38

TXECP

39

TXECM

40

VOO

44

36
43
49

AGND

VNN

34

33
35

AGND

TXO0P

47

TXO0M

48

TXO1P

45

TXO1M

46

TXO2P

41

TXO2M

42

TXO3P

37

TXO3M

38

TXOCP

39

TXOCM

40

VOO

44

36
43
49

AGND

VNN

34

33
35

AGND

LVDS BUSDISPLAY PORT

TXE3P
TXE3M

TXECP
TXECM

TXE2P
TXE2M

TXE1P
TXE1M

TXE0P
TXE0M

LCDVCC

TXE3P
TXE3M
TXECP
TXECM
TXE2P
TXE2M

TXE1P
TXE1M

TXE0P

TXE0M

TXO3P

TXO3M

TXOCP

TXOCM

TXO2P
TXO2M

TXO1P

TXO1M

TXO0P

TXO0M

+5V

CON1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

CON2

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

CON30_NS

1 2 3 4 5 6 78

7654321

8

D

C

J28' and J28" are supplementary power sockets

B

VCC

L26
FB

L27
FB

IC4
LT1085CM

VIN3VOUT

GND

1

POWER1

8
7
6
5
4
3
2
1

CON8

VSS

+5

VDD

2

VCC

M5V

+12

L32
FB

1 2

L36
FB

V33VT

VDD

VSS +5

C209
47uF/16V

GND

VCC1

VDD

C220
100uF

C219
470uF

V33VT

VDD

VCC1

C223
470uF

C224
470uF

VCC +12

C210
47uF/16V

GND

VDD1

C225

C226

100uF

100uF

VDD

C217
100uF

C124
470uF

VCC

C221
470uF

VCC1

CN11

VDD1

VNN

L33
FB

VOO

L34
FB

+3.3

L37
FB

C218
100uF

CON3

+12VCC

C222
470uF

1
2
3

GND

C212
47uF/16V

GND

C213
47uF/16V

+3.3VOOVNN

GND

VCC1

C214
47uF/16V

IC5
LT1117

R174
300

IC7
LT1117

VIN3VOUT

IC8
LT1117

VIN3VOUT

VIN3VOUT

ADJ

1

V125ADJ

ADJ

1

ADJ

1

VFF is 3.3V analog power for U10

2

R175
680

VLL is 1.8V core power of U15,

L31
FB

2

VEE is 3.3V PLL power for U10

L35
FB

2

VPPVLL

GND

C215
47uF/16V

C231
100uF/16V

L29
FB

CK3 is the decoupling cap for VLL,

VPPVLL

L30
FB

VEEVEEVCC1

C211
47uF/16V

GND

VFFVFFVCC1

C216
47uF/16V

GND

D

C

B

A

1 2 3 4 5 6 78

A

0.1UF50V

0.1

1000UF10V

0.1

CN5,CN8
HDR1X10

CN6
HDR1X8

HDR1X2
CN4

CN7
HDR1X5

CN3
HDR1X3

6

OUT 24V/5A

GND
GND

+5
+5
+5
+5

+11~16V
+11~16V

+5

G
GND

+11~16V
+11~16V
GND
GND
+5

+5

+3.3

GND

D

C

B

A

C49

3300UF35V

R37
100K

Q11

R48
1K

1000UF10V

R49
1K

Q17

54321

L17
5UH

GND

C51

5UH

L14

C44,C45

2200UF25V

L15

10UH3A

C59,C60

10UH1A

1000UF10V

L16

L11
5UH

1000UF10VU6LM1085IT-3.3

SB

5UH8A

C46

1000UF10V

CN2

2200uF25V

C44

L13

C41

C42

0.1

C60

C50

3300UF35V

C58

C55

0.1

C53

1000UF10V

C56

C45

Q13

R44

1.5K

Q4
2N5551

R61
10K

2N5551

C62 221/1KV

R36

4.7K

R35
1K

R54
10K

L8
5UH

C32,C35

25V/2200uF

C27

0.1

U4

47UF/16V

R63
1K

Q16
2N5551

D10

MBR20200

R56 10K

C24
0R

R28

4.7K

3300UF/35V

U5

TL431ACLP

+5V

C40

25V/2200uF

R39

5.1K

C56

R64
10K

L12
5UH/5A

C61,47

C31

104

Q9
MTP50P03HD

R46

5.1K

R43
2K

2N5551

R65

2K

R34

6.2K

Q14

R38

51K

2N5401

2N5551

D2

MUR480E

L4

400UH2A

D

C5

105/400V

RS606

D1

RT1

8OH5A

L1

C

B

A

20mH3A

C3

20mH3A

2200P

CN1

5A500V

0.22UF275V

C1

2200P

C54

L2

C4 0.68UF/275V

R60

RV1

2.2M 1/4W 5W

1 2

10D471

L3

磁珠500欧

FU1

3.15A/250V

C11

SW1

R1

1K

D5

1N4007

100UF25V

C4

U2

8

7

6

5

MBR1100

C10

0.01

R2

R9

0.51 5W

R8

D7

D6

0.1UF400V

C6

0.22

12K

NCP1203P60

1N5819

D3

MUR860T

Q1

FQP18N50

R14

1M

D4

R15

1N4148

1M

8

MC33260D

1

C8

1000PF

1

2

3

4

10

C9

150pf1kv

R3

10

47

7

U1

2

L4

47k

6

3

磁珠500欧

C12

0.1

5

4

C16

103 1KV

68UF450V

FQP7N80

R12

1K

R11

C13

47K

101

L5

磁珠500欧

C7

R31

0R

15V 1/2W

C64

U3

R17
68K5W

10

R21

D13

100UF25V

104/50V

58

R33

100P

1

2

3
6

5

D11
MBR1100

R10

R18

C18

100uF450v

FR107

R25

C22

100P

.

10

MTP50P03HDL

2K

10UF50V

47UF/25V

100UF/450V

L7

C28

ZD2

磁珠500欧

C28

100uf25v

NCP1377DR2

14

C25

R27

CA1

10K

100P

C20

D8
MUR180E

Q4

C15

150P1KV

R13

0.51/5W

300

10

Q3

100R

T1

C19

D9

C17

R26

47K

1N4148

R19
10

R7

15V 1/2W

D18

11,129,107,8

4
5

R23
10

C23

103/1KV

MUR180E

ZD1

MBR20100

D12

Q2

R16
47K

0.24/5W

5UH

C33，C36

25V/2200uF

PH1

PC817B

PC817B

STW12NK80Z

C26

2200P

R20

68K/5W

R24

L9

C21

150p1kv

25V/2200uF

PH2

T2

1

9101112

R53
1K/1W

C30

PH3

D17

MBR20100

R30

100_NS

1K
R22

1K

R29

C37

2200PF200V

R55

PC817B

Q12
MTP50P03HD

R41

5.1k

R42

1K

+5V

Q15
2N5401

47R2W

TL431ACLP

R62

5.1K

2

3
4

6

.

C29

2200P

C43

333_NS

IN:AC 100V-240V

1 2 3 4 56

VHH

C56

1000uF

VHH

8

C57

1000uF

VHH

C58

1000uF

D

7654321

CN1

1
2
3
4

470uF/16V

CON4

D

VHH

L2

VCC1

FB

CN2

3

C1

C3

0.1

CON3

2
1

IF
AGND
TV_AUDIO

CN6

CON2

2
1

AGND4

CON2

2
1

CN7

AV-IN

TV_VIN
AGND3

CN10

CON6

SL
AGND
SR
SCART_L
AGND
SCART_R

CN3

CON2

2
1

6
5
4
3
2
1

CN5

AGND

4

MUTE
AGND

VCC1 VCC

RST1#

3

SCL

2

SDA

1

CON4

L4
FB

VHH

R9
3K

IC1
LT1117

VIN3VOUT

ADJ

1

V125ADJ

VBB

L3
FB

2

R10
560R

VHH

5

VHH

C43

1000uF

TV_AUDIO

C

B

A

PHO

CON3

C41

VCC

IF

C2
100pF

R1
1K

C14

C13
56pF

C15

SDA
SCL

RST1#

R24
10K

R2 1K

C4

0.33

C5

0.33

HD-AR

0.33

0.33

VBB

AGND1

R3
10K

R25
10K

C8

0.33
C9

0.33
C10

0.33
C11

0.33

C49
100uF/16V

HD-AL

PC-AR
PC-AL

C6
C7

R22

10K

R23

AV-AR

10K

AV-AL

SR

SL

AGND

PL

PR

TV_AUDIO

PR
PL

SCART_R
SCART_L

3
2
1

VCC

56pF

56pF

67

ANA_IN1+

68

ANA_IN-

69

VCC

C28

0.1

ANA_IN2+

60

MONO_IN

0.33

57

SC1_IR

56

SC1_IL

54

SC2_IR

53

SC2_IL

51

SC3_IR

50

SC3_IL

48

SC4_IR

47

SC4_IL

73

TP

74

AUD-CL_OUT

77

D_I/O1

78

D_I/O0

80

STANDBYQ

79

A-SEL

4

12S_CL

5

12S_WS

7

12S_I1

17

12S_I2

6

12S_DO

8

ADR_DA

9

ADR_WS

10

ADR_CL

3

SDA

2

SCL

21

RESET

DVSS14DVSS15DVSS16AVSS61AVSS62AHVSS43AHVSS44VREF135VREF226ASG49ASG52ASG

C55

100uF/16V

C12

R26
10K

Q5
9014

R27
10K

VCC1 VBB

DVSUP11DVSUP12DVSUP13AVSUP65AVSUP

AGND1AGND1

L-R

TV_VIN

66

39

AHVSUP

CAPL_M

CAPL_A

XT_OUT

SC1_OR

SC1_OL

SC2_OR

SC2_OL

DACM_R

DACM_L

DACM_S

DACA_R

DACA_L

VREF-T
AGNDC

AGND1

C59

100uF/16V

XT_IN

TEST

U1

VBB

X1

DACM-R

DACM-L

VCC

R12
220R

C16
10uF

C17
10uF

C22
20pF

C23
20pF

C21
10uF
C34

0.1
C47

4.7
C35

0.1

AGND1

RST1#

Q6

9014

C60

TV_VIN1

100uF/16V

DACM-R

DACM-L

VHH

R32
2K

D1

IN4148

VOL-R

VOL-L

C51

470u/16V

R31

5.1K

R33
1K

C26
1nF

C27
1nF

AGND1

40

38

72

18.432

71

36
37

33
34

27

28

30

24

25

58

45
70

3450

55

R28

1K

R4
10K

VCC

C18
10uF

The bypass caps for U5. DVSUP, AVSUP and AHVSUP pin each has 3 caps.

R18
47K

R19

47K

Q4 9015
R29
10K

Q8
9014

C29

0.1uF/16V

C30

0.1uF/16V

R21

R20

47K

47K

R13

3K

R30

3K

Q7
9014

C31

0.1

AMPIN-L

AMPIN-R

C61
220uF

R34

100R

Q1
9014

C37
470pF

VHH

R7
10K

R8
10K

VCC1 VBB

C52

1.5nF

22uF

C48

Q3
9014

R6

3.3K

12

10
13

11

8

6
9

5

C42
220uF

C19
10uF

U2

IN1+
IN2+

IN3+
IN4+

MODE2

MODE1
CIV

SVR

470uF

C32

0.1

VHH

VCC13VCC2

SGND

7

16

OUT1+

OUT2-

OUT4+

OUT3-

GND2

GND1

C38
470pF

MUTE

C36

0.1

C53

1.5nF

1

4

17

14

15

2

CON6

C40

0.1

C20
10uF

R351KR361KR371KR38

CN8

CN9

1K

A.1

C39

1
2

1
2

AGND1

CON2

CON2

470pF

C54

1.5nF

C

B

A

C33

0.1

1 2 3 4 5 6 78

7654321

8

D

C

CN1
M5
TUNER

L1
10uH

C2

0.1

C1

100u/16V

+5V

AGND

B

C4

100u/16V

VTT

AGND

112233445566778899101011111212131314

C3

0.1

SCL
SDA

TV-VIN

SCL
SDA

VTT +5VGND

TV-VIN

14

TV-AUDIO

IF

+5V
SCL
GND
GND
SDA
IF

GND
TV-VIN
TV-AUDIO

1
6
2
7
3
8
4
9
5

DB9

D

C

B

A

A

1 2 3 4 5 6 78

Disassembly

In case of trouble, etc., Necessitating disassemble, please disassemble in the order shown in the
illustrations.
Reassemble in the reverse order.

1. Removal of the Back Cover

2. Removal of the MAIN PCB
a. Remove the screws.

.

b

Slide out the LCD chassis slightly; pull up the connector of AC cord from PCB; pull up the

PCB from LCD.

LCD

c

. Remove the Anode cap from The picture tube. To avaid a shock hazard, be sure to discharge

.

d

Take out the LCD chassis.

MAIN PCB

AUDIO PCB

POWER PCB

TUNER PCB

TURNER.PCB 1.000 PCB

Bill of Material

413210450RZ00 CAP 2.000 C2,C3

50V-104-Z

414133R10RM00 CAP-EL∮4*7 2.000 C1,C4

CD110-10V-33uF-M

420ET15010920 SOCKET 1.000 CN1

DB9

429EC041010R0 INDOUCTOR 1.000 L1

EC0410-100K 10uH 500mA

4320006000500 WIRE 5mm 2.000 J4,J5

4320006000750 WIRE 7.5mm 1.000 J3

4320006001000 WIRE 10mm 1.000 J1

4320006001250 WIRE 12.5mm 1.000 J2

442JS6B312110 TUNER JS-6B3121/F2 1.000 TUNER

7506T2601001F MTV-2601B POWER PART 1.000

4110PQ323A000 TRANSFORMER 1.000 T1

PQ32/30-40305A

411EC42405250 TRANSFORMER 1.000 T2

KBEC42-40525B

4121010118J40 CARBON RES 1.000 R7

1/8W-100Ω-J

4121010201J40 CARBON RES 1.000 R53

1W-1K-J

4121010214J40 CARBON RES1/4W-1KΩ 1.000 R49

4121010314J40 CARBON RES1/4W-10KΩ 1.000 R54

4121010514J40 CARBON RES1/4W-1MΩ 1.000 R14

4121010R14J40 CARBON RES1/4W-10Ω 2.000 R23 R33

4121020214J40 CARBON RES 2.000 R18 R43

1/4W-2KΩ-J

4121024114J40 CARBON RES 1.000 R42

RT14-1/4W-240Ω-J

4121051214J40 CARBON RES1/4W-5.1KΩ 1.000 R39

4121051314J40 CARBON RES1/4W-51KΩ 1.000 R38

4123068305J20 METAL OXIDE RES 2.000 R17 R20

5W-68K-J

41230R3305J20 METAL OXIDE RES 1.000 R40

RY-5W-0.33Ω-J

41230R5105J20 METAL OXIDE RES 1.000 R13

5W-0.51R-J

4129008R05A00 HEAT VARIABLE RES 5A 8R 1.000 RT1

DIP

412A07D471K00 PIEZORESISTANCE 1.000 RV1

ZOV-07D471K （HEL） DIP

412A0R5105J00 WIREWOUND RES 5W-0.51Ω-J 1.000 R9

4130103102M03 HIGH VOLTAGE CERAMIC CAPACITOR 3.000 C14 C23 C20

1KV-103-M

4130151102M00 HIGH VOLTAGE CERAMIC CAPACITOR 3.000 C9 C21,

1000V-151-M

4136104271M02 X CAP 1.000 C4

AC275V-104-M（K）

4136221401M00 Y CAP221 400V 3.000 C1,C3,C26

4136222251M00 Y CAP 2.000 C29,C37

AC250V-222-M（K）

4136684271M03 X CAP 1.000 C54

AC275V-684-M（K）

4138105401K00 METAL MYLAR CAP 1.000 C5

400V-105-K

4140101451M00 CAP- EL DL:18*35(105°) 2.000 C7 C19

CD11G-450V-100u-M

414110125RM01

414110210RM02

CAP-EL 105°high frequency LOW
IMPEDANCER 4.000 C11 C17 C18 C28
CD11HL 25V-100uF-M

CAP-EL 47uF/10V ∮6

CAP-EL 105°high frequency LOW
IMPEDANCER 7.000 C41 C44 C46 C51 C53 C56 C57

1.000

C64

10V-1000uF-M

CAP-EL 105°high frequency LOW

414110216RM01

414122225RM01

414133235RM00

414147R451M00 CAP-EL 105° 1.000 C16

4151000015070 CHIP ZENER 1206 1.000

IMPEDANCER 1.000 C48
16V-1000uF-M

CAP-EL 105°high frequency LOW
IMPEDANCER 8.000 C33 C36 C43 C52 C59 C32 C35 C39
25V-2200uF-M

CAP-EL 105°high frequency LOW
IMPEDANCER 4.000 C47 C49 C50 C61
35V-3300uF-M Φ16*31

450V-47uF-M

15V 0.5W

415300FR10740 DIODE FR107 1.000 D13（OR 1N4935）

415301N400720 DIODE（D015） 1.000 D5

1N4007

41530UF400740 DIODE 2.000 D6 D11

UF4007

4153MBR20100C DIODE MBR20100CT TO-220 1.000 D17

4153MBR20200C DIODE MBR20200 TO-220 3.000 D10 D10 D18

4153MUR180E00 DIODE MUR180E 2.000 D8 D12

DO-15

4153MUR480E00 DIODE MUR480E 1.000 D2

DO-35

4153MUR860T00 DIODE MUR860T 1.000 D3

TO-220

41540KBU6J000 BRIDGE RECTIFIER (DIP) 800V 1.000 D1

KBU6J（RS606）

416000050P030 MOSFET MTP50P03HDL 3.000 Q3 Q9 Q12

TO-220

416002N540100 TRANSISTOR 2N5401 2.000 Q11 Q4

416002N555100 TRANSISTOR 2N5551 2.000 Q13 Q14

41602SK265100 MOSFET 2SK2651 1.000 Q5

416FQP18N5000 MOSFET FQP18N50 1.000 Q1

TO-220

416STW12NK800 MOSFET STW12NK80Z 1.000 Q2

TO-3P

41700000P6210 IC P621[SFH615A-3][PC817] 3.000 PH1 PH2 PH3

4170000TL4310 IC TL431 DIP TO-92 2.000 U4 U5

41700DF108410 IC(DIP) DF1084-3.3V 1.000 U6

TO-220

4222500315210 FUSE T3.15A 250V VDE/UL 1.000 FU1

4290250100040 INDUCTOR 500Ω 4.000 L3 L5 L6 L7

（100MHz）

42903040117B0 INDUCTOR 1.000 L4

PQ32/30-40117B

4290304021600 INDUCTOR 2.000 L1 L2

EE25-40216

42903100K5210 INDUCTOR 2.000 L16 L15

T37-52-100K3A

429035R0K5200 INDUCTOR 1.000 L13

T37-52-5R0K

42903B60974A0 INDUCTOR 1.000 L12

DQG-B6-0974A

42903B61042A0 INDUCTOR 1.000 L9

DQG-B6-1042A

42903B61043A0 INDUCTOR 3.000 L8 L10 L11

DQG-B6-1043A

42903T1605640 INDUCTOR 1.000 L14

LCL-T16-0564

42907RHM40203 magnetic loop 3.000 D3*2，Q1(S)＊1

RHM-004002003

4320007000800 WIRE 8mm Φ0.7 2.000 J7 J23

4320007001000 WIRE10mm Φ0.7 10.000 J4 J5 J8 J10 J11 J13 J14 J17 J18 R31

4320007001500 WIRE15mm Φ0.7 4.000 J22 J21 J20 J24

4320007001700 WIRE17mm Φ0.7 1.000 J19

4320007002000 WIRE20mm Φ0.7 2.000 J12 J9

4320007003000 WIRE30mm Φ0.7 1.000 J1

437T300100260 LEAD WIRE 70mm 1.000 J2

405T2701050A0 26"POWER300.PCB 1.000

2004.8.11

412700R014J70 CHIP RES 1/4W-0Ω 1206 J 2.000 R57 R58

412700R01AJ60 CHIP RES 1/10W-0Ω 0805 1.000 C27

412701021AJ60 CHIP RES 1/10W-1KΩ 0805 J 5.000 R12 R22 R35 R48 R63

412701031AJ60 CHIP RES 1/10W-10KΩ 0805 J 6.000 R1,R27 R32 R56 R61 R64

412701041AJ60 CHIP RES 1/10W-100KΩ 0805 J 1.000 R37

4127010514J70 CHIP RES 1206 1.000 R15

1/4W-1M-J

CHIP RES 0805 2.000 R3 R24

1/4W-1M-J

4127010R1AJ60 CHIP RES 1/10W-10Ω 0805 J 4.000 R10 R4 R19,R8

4127012314J70 CHIP RES 1206 1.000 R2

1/4W-12K-J

4127015214J70 CHIP RES 1206 1.000 R44

1/4W-1K5-J

412702021AJ60 CHIP RES 1/10W-2KΩ 0805 J 2.000 R29 R65

412703011AJ60 CHIP RES 1/10W-300Ω 0805 J 1.000 R25

412704721AJ60 CHIP RES 1/10W-4.7KΩ 0805 J 1.000 R28

4127047314J70 CHIP RES 1206 1.000 R3

1/4W-47K-J

412704731AJ60 CHIP RES 1/10W-47KΩ 0805 J 2.000 R11 R16

412704731AJ70 CHIP RES 1206 1.000 R26

1/4W-47K-J

412705121AJ60 CHIP RES 1/10W-5.1KΩ 0805 J 4.000 R46,R36,R41 R62

412706221AJ60 CHIP RES 1/10W-6.2KΩ 0805 J 1.000 R34

4127075R1AJ70 CHIP RES 1/8W-75Ω 1206 J 1.000 R21

413510150RJ40 CHIP CAP 50V-100P 0805 J NPO 4.000 C13 B1 A1 25

413510150RJ50 CHIP CAP 1206 1.000 C22

50V-100P-J

413510250RK40 CHIP CAP 0805 1.000 C8

50V-102-K

413510350RK40 CHIP CAP 0805 1.000 C10

50V-10nF-K

413510450RZ40 CHIP CAP 50V-104 0805 Z 10.000 C12 24 31 42 45 55 58 60 62 63

413522450RZ40 CHIP CAP 50V-224 0805 Z 1.000 C6

4151000015070 CHIP ZENER 1206 2.000 ZD1 ZD2

15V 0.5W

415201N414870 CHIP DIODE 1N4148 1206 3.000 D4 D9 D7

41700001377B0 IC NCP1377B 1.000 U3

SO8

4170000332600 IC MC33260D 1.000 U1

SO8

41701203P6010 IC NCP1203D60R2 1.000 U2

SOP 8

TRANSISTOR 2N5551 SOT23

TRANSISTOR 2N5401 SOT23

7516T2601000M LCDTV-2627 KEY PCB PART 1.000

40300T1701000 KEY 7.000 P+,P-,V-,V+,MENU,SOURCE,POWER

6*6*5mm

4041920004010 SOCKET 4PIN/2.0 1.000 CN1

4041920008010 SOCKET 8PIN/2.0 1.000 CN2

TVM2627KEY100.PCB 1.000

2.000

1.000

Q16 Q17

Q18

2004.10.6

4105010300010 LED 3mm GREEN 1.000 LED

4300000000080 IR 1.000 REMOUT

7516T2701002F MTV-2601　TUNER SWITCH PCB 1.000

4041920002010 SOCKET 2PIN/2.0 2.000 CN4,6

4041920003010 SOCKET 3PIN/2.0 3.000 CN1,2,3

4041920005010 SOCKET 5PIN/2.0 1.000 CN5

2627-TURNER300.PCB 1.000

2004.10.18

414147116RM00 CAP-EL ∮8*12 1.000 C1

CD110-16V-470uF-M

420ET15010910 SOCKET 1.000 DB2

DB-9A

420ET15010920 SOCKET 1.000 DB1

DB9

4320005001000 WIRE 10mm 2.000 J1、J2

MTV-2701mainboard 0.000

4041920002010 SOCKET 2PIN/2.0 3.000 CN5,CN3,CN13

4041920003010 SOCKET 3PIN/2.0 3.000 CN9,CN11,CN2

4041920004010 SOCKET 4PIN/2.0 1.000 CN6

4041920005010 SOCKET 5PIN/2.0 1.000 CN14

4041920006010 SOCKET 6PIN/2.0 1.000 CN12

4041920007010 SOCKET 7PIN/2.0 1.000 CN10

4041920008010 SOCKET 8PIN/2.0 1.000 POWER1

4041920010010 SOCKET 10PIN/2.0 1.000 KBD1

414110116RM00 CAP-EL 16V-100uF M φ6*7 13.000 C168,C217, C220,C225,C226,C231,C246,C250,C10,23,C62,

C208,C249

414110210RM00 CAP-EL 2.000 C197,C227

10V-1000uF-M

414110R16RM00 CAP-EL 3.000 C45-C47

16V-10uF-M

41412R216RM00 CAP-EL 1.000 C233

16V-2.2uF-M

414147116RM00 CAP-EL 5.000 C124,C219,C221,C223,224

CD110-16V-470uF-M

414147125RM00 CAP-EL 25V-470uF M≤φ8*15 1.000 C222

414147R16RM00 CAP-EL 16V-47uF Mφ5*7 12.000 C165-167,196 C209-C216

417000078L050 IC 78L05 1.000 IC9

4202T27012010 AV SOCKET 1.000 RCA1

AV3-8.4-20

4202T30011210 RCA SOCKET AV8-8.4-7 1.000 RGA

420AD10006110 S-SOCKET DSW-06P 1.000 S-VIDEO

420DT15011510 SOCKET 1.000 VGA

DB-15

424000006101A OSCILLATOR〈49S〉-10℃---80℃ 1.000 X3

10M(+-20PPM,20PF)

424000256201A OSCILLATOR<49S>-10℃---80℃ 1.000 X1

20.25M(+-20PPM,20PF)

424003186142A OSCILLATOR〈49S〉-10℃---80℃ 1.000 X4

14.31818M(+-15PPM,20PF)

405T2701A5302 2627A-pixwork300 PCB 1.000

MAINBOARD（04.12.17）

4105010300060 LED-CHIP GREEN 0805 1.000 LED1

SA0805G1C-1A-01

412700R014J70 CHIP RES 1/4W-0Ω 1206 J 1.000 L29

412700R01AJ80 CHIP RES 1/10W-0Ω 0603J 22.000 R14,R40,R28,R81,R82,R142,R143,R178,187,R233,R245-250,

R41,R66,C254-C256,R97

412701011AJ80 CHIP RES 1/10W-100Ω 0603 J 1.000 R59

412701021AJ80 CHIP RES 1/10W-1KΩ 0603 J 5.000 R2,R134,R188,R190,R226

412701031AF80 CHIP RES 1/10W-10K 0603 F 2.000 R232,R73

412701031AJ80 CHIP RES 1/10W-10KΩ 0603 J 19.000 R29-30,R118,119 R159-169,179 183,191 R228

412701221AJ80 CHIP RES 1/10W-1.2KΩ 0603 J 1.000 R71

412702011AJ80 CHIP RES 1/10W-200Ω 0603 J 3.000 R116,R117,R153

412702021AJ80 CHIP RES 1/10W-2KΩ 0603 J 7.000 R44-R48,R170,R49

412702221AJ80 CHIP RES 1/10W-2.2KΩ 0603 J 2.000 R36,R37

412702231AJ80 CHIP RES 1/10W-22KΩ 0603 J 1.000 R63

412702251AJ80 CHIP RES 0603 2.000 R93,R130

1/10W-2.2M-J

4127022R1AJ80 CHIP RES 1/10W-22Ω 0603 J 2.000 R34,R35

412703011AJ80 CHIP RES 1/10W-300Ω 0603 J 4.000 R92,R128,R129,R174

412703321AJ80 CHIP RES 1/10W-3.3KΩ 0603 J 26.000 R90,R91,R104-R111,R135-R137,R144-R148,R171-R173,R227

,R234,238,R253,R255

412704711AJ80 CHIP RES 1/10W-470Ω 0603 J 11.000 R132,R133,R60,R61,R67-R69,R192-R194,L43

4127047R1AJ80 CHIP RES 1/10W-47Ω 0603 J 14.000 R13,R87,R88,R89,R112-R115,R138,R141,R64,R101,R102,

R103

412705121AJ80 CHIP RES 1/10W-5.1KΩ 0603 J 1.000 R252

412705621AJ80 CHIP RES 1/10W-5.6KΩ 0603 J 1.000 R62

412706811AJ80 CHIP RES 1/10W-680Ω 0603 J 3.000 R38,R39,R175

412706821AJ80 CHIP RES 1/10W-6.8KΩ 0603 J 3.000 R131,R75,R254

4127075R1AJ80 CHIP RES 1/10W-75Ω 0603 J 18.000 R50-R57,R58,R94-R96,R98-R100,R184,R74,R76

413510250RK60 CHIP CAP 0603 5.000 C31-C34,C137

50V-102-K

413510450RZ60 CHIP CAP 50V-104 0603 Z 110.000 C2,C4-6,C9,C11-19,C48-53,C81-97,C99-110,C114-123,

C138-142,155-156 C169-C179,C181-185,C188-C190,
C126-129,C131,C63,C65,C67,C258
C192-C195,C198-C207,C232,C234

413510R50RJ60 CHIP CAP 50V-10P 0603 J NPO 5.000 C111,C143,C144,C180,C228

413520R50RJ60 CHIP CAP 50V-20P 0603 J NPO 9.000 C58-59,C112,113,186,187,146,147,148

413522416RZ60 CHIP CAP 16V-0.22u 0603 Z 8.000 C36-C40,C72,C73,C74

413522R50RJ60 CHIP CAP 50V-22P 0603 J NPO 2.000 C25,C26

413533150RK60 CHIP CAP 50V-330P 0603 K 4.000 C55-C57,C75

413533R50RJ60 CHIP CAP 50V-33P J 0603 NPO 3.000 C69,C70,C71

413539250RK60 CHIP CAP 50V-392 0603 K 1.000 C132

413539350RZ60 CHIP CAP 0603 1.000 C136

50V-39nF-Z

413547350RZ60 CHIP CAP 0603 6.000 C42-C44,C133-C135

50V-47n-Z

413568250RK60 CHIP CAP 0603 1.000 C77

50V-6.8nF-K

413568350RZ60 CHIP CAP 50V-0.068μ 0603 Z 1.000 C78

413568410RZ60 CHIP CAP 0603 4.000 C27-C30

10V-0.68uF-Z

415200BAV9960 DIODE (SOT-23B) 7.000 D1-D7

BAV99

415201N414870 IODE 1N4148 1206 6.000 D11-13,17,18,D15

4160000901421 CHIP TRANSISTOR(SOT23) 6.000 Q3-7,Q10

9014 NPN

4160000901520 CHIP TRANSISTOR 9015 1.000 Q16

416PCHAN20P03 MOSFET P-CHANNEL T0-252 1.000 Q8

MTD20P03HDLT4 OR 25P03

417000024C320 IC(SO8) 1.000 U5

24C32

4170000AC3200 IC(SO14) 1.000 UD

AC32

4170000LM3580 IC(S0-8) 1.000 UE

LM358
41700074HC140 IC 74HC14[SOP] 1.000 U3
417000HC37400 IC(SSOP20） 1.000 U2

HC374
4170074LV1260 IC(SO14) 2.000 UB UA

SN74LV126
41700AMS11170 IC AMS1117[SOP]3.3V 2.000 IC7,IC8

41700APL11170 IC APL1117ADJ[SOT-223] 2.000 IC2,IC5

41700Z8622910 IC Z86229 SO18 1.000 U7

41704M000161A IC(TSOP54) HY57V641620HG 1.000 U9

4M*16 SDRAM 7ns
4170LV800DT10 IC(TSOP48) 1.000 U18

AM29LV800DT-90EC
4170LVC162440 IC（TSSOP48） 2.000 U14，U15

LVC16244
4170MAX232A00 IC（S016） 1.000 U12

MAX232A
4170MST988310 IC(LQFP80) 1.000 U11

MST9883B-C(/110)
41763LVDM8310 IC THC63LVDM83A 1.000 U19

THINE
417AZ1084S3V3 IC(TO-263) 1.000 IC4

AZ1084S-3.3V
417FSAV330M10 IC(SO16) 1.000 U10

P15V330/FSAV330M
417PW11320Q10 IC PW113-20Q [PQFP208] 1.000 U17

417PW12350010 IC PW1235 [PQFP256] 1.000 UC

417S0HCF40520 IC HCF4052 SOP 1.000 U21

417VPC3230D10 IC VPC3230D PQFP80 1.000 U4

420FT15013010 SOCKET SOP 1.000 CON1

DF14-30S-1.25C
42847R0082010 CHIP RES 0603 20.000 RP7-RP20 RP33-38

47Ω*4
429025R6K0010 CHIP INDUCTOR 1210 5.000 L8 24 27 30 36

DR43-5R6K
429042R2J7010 CHIP INDUCTOR 1210 10.000 21-23 26 31 33-35 37,L41

ALM322522-2R2K
429043R3J5010 CHIP INDUCTOR 1206 1.000 L42

3.3uH-J

429043R3J8011 CHIP INDUCTOR 0603 5.000 L9-L11,L39,L38

3.3uH-J

4290511R08010 CHIP INDUCTOR 0603 7.000 L12-17,44

11 OHM@100MHz
4290512108010 CHIP INDUCTOR 0603 1.000 R11

BK1608HM121-T
4290550108010 CHIP INDUCTOR 500Ω 0603 1.000 R86

7596T2701003F 2601B SOUND PCB 1.000

4041920002010 SOCKET 2PIN/2.0 5.000 CN3,CN6-CN9

4041920003010 SOCKET 3PIN/2.0 1.000 CN2

4041920004010 SOCKET 4PIN/2.0 1.000 CN5

4041920005010 SOCKET 5PIN/2.0 1.000 CN1

4041920006010 SOCKET 6PIN/2.0 1.000 CN10

4121010214J40 CARBON RES 1/4W-1KΩ 4.000 R35-R38

414022125RM00 CAP-EL 25V-220uF M 1.000 C42

41404R716RM00 CAP-EL 16V-4.7uF M 1.000 C47

414110116RM00 CAP-EL 16V-100uF M φ6*7 5.000 C49 C55 C59 C60 C61

414110R16RM00 CAP-EL 6.000 C16-21

16V-10uF-M

414122R16RM00 CAP-EL ∮5*11 1.000 C48

CD110-16V-22uF-M

414147125RM00 CAP-EL 25V-470uF M≤φ8*15 7.000 C1,C41,C43,C56,57,58,C51

415201N414840 DIODE 1N4148 1.000 D1

417TDA8947J10 IC TDA8947J SOT243-1 1.000 U2

4202T30011310 RCA SOCKET 1.000 RCA

AV6-8.4-20

4204T15010310 EAR SOCKET 1.000 PHO

EJ-0357-3P

424004326183A OSCILLATOR49S -10℃---80℃ 1.000 X1

18.432MHz ±15PPM，15P

405T2701059B0 2627SOUND300.PCB 1.000

412700R01AJ80 CHIP RES 1/10W-0Ω 0603J 1.000 R26

412701021AJ80 CHIP RES 1/10W-1KΩ 0603 J 5.000 R1,R2,R24,R27,R33

412701031AJ80 CHIP RES 1/10W-10KΩ 0603 J 6.000 R3,R7,R8,R25,R29,R34

412702021AJ80 CHIP RES 1/10W-2KΩ 0603 J 1.000 R30

412702211AJ80 CHIP RES 1/10W-220Ω 0603 J 1.000 R12

412702231AJ80 CHIP RES 1/10W-22KΩ 0603 J 1.000 R4

412703021AJ80 CHIP RES 1/10W-3KΩ 0603 J 3.000 R6,R9,R13

412704731AJ80 CHIP RES 1/10W-47KΩ 0603 J 4.000 R18-R21

4127047R1AJ80 CHIP RES 1/10W-47Ω 0603 J 1.000 R14

412705121AJ80 CHIP RES 1/10W-5.1KΩ 0603 J 2.000 R31 R32

412705611AJ80 CHIP RES 1/10W-560Ω 0603 J 1.000 R10

412705621AJ80 CHIP RES 1/10W-5.6KΩ 0603 J 1.000 R28

413510150RJ60 CHIP CAP 50V-100P 0603 J NPO 1.000 C2

413510250RK60 CHIP CAP 0603 2.000 C26,C27

50V-102-K

413510425RZ60 CHIP CAP 25V-104 0603 Z 11.000 C3,C28-C36,C40

413515250RK60 CHIP CAP 50V-1500P 0603 K 3.000 C52-C54

413520R50RJ60 CHIP CAP 50V-20P 0603 J NPO 2.000 C22,C23

413533416RZ60 CHIP CAP 0603 9.000 C4-C12

16V-0.33uF-Z

413547150RK60 CHIP CAP 50V-470P 0603 K 3.000 C37-C39

413556R50RJ60 CHIP CAP 50V-56P 0603 J NPO 3.000 C13-C15

4160000901421 CHIP CAP (SOT23) 6.000 Q3,Q5,Q6,Q1,Q7,Q8

9014 NPN

4160000901520 CHIP TRANSISTOR 9015 1.000 Q4

41700APL11170 IC APL1117ADJ[SOT-223] 1.000 IC1

417MSP3450G10 IC MSP3450G-QA-C12-001 1.000 U1

[PQFP80]

429025R6K0010 CHIP INDUCTOR 1210 1.000 L2

DR43-5R6K

429042R2J7010 CHIP INDUCTOR 1210 2.000 L3,L4

ALM322522-2R2K

Pinout Information Pin Descriptions

D7D8D9

D10

D11

D12

D13

D14

D15

TRST_N

TCK

TMS

TDI

TDO

TESTEN

VSSQ

VDDQ3

RESET_N

VSS

VDD1

DGR0

DGR1

DGR2

DGR3

DGR4

DGR5

DGR6

DGR7

DGG0

DGG1

DGG2

DGG3

VSSQ

VDDQ3

DGG4

DGG5

DGG6

DGG7

DGB0

DGB1

DGB2

DGB3

DGB4

DGB5

DGB6

DGB7

DEN

DHS

DVS

DCLKNEG

DCLK

VSSQ

105

106

107

108

109

110

111

112

113

114

116

117

118

119

120

121

122

123

124
D6
D5
D4
D3
D2
D1
D0

A1 9
VDDPA2
VSSPA2
VDDPA1
VSSPA1

XO

VDDQ3

VSSQ

A1 8

A1 7

A1 6

A1 5

A1 4

A1 3

A1 2

A1 1

A1 0

A9
A8
A7

VDD1

VSS

A6
A5
A4
A3
A2
A1

NMI

WR

RD

ROMOE

ROMWE

CS0

CS1
PORTA7
PORTA6
PORTA5
PORTA4
PORTA3
PORTA2
PORTA1
PORTA0

VDDQ3

151

152

153

154

155

156
157
158
159
160
161
162
163

164
165
166
167
168
169

XI

170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051

141

PW113

(Top View)

138

139

140

142

143

144

145

146

147

148

149

150

128

125

126

127

129

130

131

132

133

134

135

136

137

115

52

104
103
102
101
100

99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53

VDDQ3
DR0
DR1
DR2
DR3
DR4
DR5
DR6
DR7
DG0
DG1
DG2
DG3
DG4
DG5
DG6
DG7
VSSQ
VDDQ3
VSS
VDD1
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
VHS
VVS
VSSQ
VDDQ3
VCLK
VPEN
VFIELD
TXD
RXD
VSS
VDD1
PORTB7
PORTB6
PORTB5
PORTB4
PORTB3
PORTB2
PORTB1
PORTB0
VYUV7
VYUV6
VYUV5
VSSQ

GBE0

VSSQ

GBE1

GBE2

GBE3

GBE4

GBE5

GBE6

GBE7

GGE0

GGE1

GGE2

VSS

GRE0

GRE1

GRE2

GRE3

GRE4

GRE5

GRE6

GGE3

GGE4

GGE5

VDD1

GGE6

GGE7

GRE7

EXTRSTEN

VDDQ3

VSSQ

GCLK

GVS

GHSSOG

GPEN

GFB K

GCOAST

VSS

VDD1

PORTC0

PORTC1

PORTC2

PORTC3

PORTC4

PORTC5

PORTC6

PORTC7

VYUV0

VYUV1

VYUV2

VYUV3

VYUV4

VDDQ3

Figure 2-1 Pin Locations

Pin Descriptions Pinout Information

2.3 Pin Descriptions

Ta bl e 2 -1 provides detailed Video Port pin descriptions.

Table 2-1 Video Port Pin Descriptions

Name Pin(s) Type Function

VCLK 71 ID 5

VVS 74 ID 5

VHS 75 ID 5

VPEN 70 ID 5

VFIELD 69 ID 5

VPort Pixel Clock. The VCLK pin is used for video port image capture.
The polarity can be selected by the VCLKPOL bit.

VPort Vertical Sync. Indicates start of next field or frame of input data. This
signal is internally polarity corrected so VVS can be either active-high or
active-low. The current status of the VVS signal is given by VPOL and
VSOK status bits when the video port is selected by the PORTSEL bit.
VVS is not used when a composite digital sync source is used (COMPEN).
VVS is required in ITUR656 input mode.

VPort Horizontal Sync. Indicates start of next line of data input. This signal
is internally polarity corrected and monitored for composite sync content.
The current status of the GHS signal is given by the HPOL, HSOK &
COMP status bits when the video port is selected by the PORTSEL bit.
VHS can supply horizontal sync information or digital composite sync
information depending on the COMPEN bit. VHS is required in ITUR656
input mode.

VPort Pixel Enable. Used when external flow control capture mode is
enabled by the EXTFCE bit. When VPEN is active, the input data is valid.
The polarity can be selected by the PENPOL bit. Use of this pin allows
non-contiguous input data.

VGPort Field Input. Video or Graphics port odd/even field indicator
specifies whether odd or even field of interlaced input is being
captured.This pin is enabled by the FLDSEL bit and the polarity can be
specified by the FLDINV bit. Field information can also be derived from
VVS and VHS, so VFIELD is not required in some applications.

Pinout Information Pin Descriptions

Ta bl e 2 -2 provides detailed Graphics Port pin descriptions.

Table 2-2 Graphics Port Pin Descriptions

Name Pin(s) Type Function

GPort Pixel Clock. The GCLK pin is used for graphics port image

GCLK 31 ID 5

GVS 32 ID 5

GPEN 34 ID 5

GHSSOG 33 ID 5

capture. The polarity can be selected by the GCKPOL bit.The GCLK
input can be disabled by the GCLKOFF bit to reduce power
consumption.

GPort Vertical Sync. Indicates start of next field or frame of data. This
signal is internally polarity corrected so GVS can be either active-high or
active-low. The current status of the GVS signal is given by VPOL and
VSOK status bits when the graphics port is selected by the PORTSEL bit.
GVS is not used when a composite digital sync source is used which can
be specified by the SOGSEL and COMPEN bits.

GPort Pixel Enable. Used when external flow control capture mode is
enabled by the EXTFCE bit. When GPEN is active, the input data is valid.
The polarity can be selected by the GPENPOL bi t. Use of this pin allows
non-contiguous input data.

GPort Horizontal Sync/GPort Sync-on-Green. This pin has two different
functions depending on the SOGSEL bit:

SOGSEL GHSSOG Function

GHS: GPort Horizontal Sync. Indicates the start of the next line of
input data. This signal is internally polarity corrected and monitored
for composite sync content. The current status of the GHS signal is
given by the HPOL, HSOK & COMP status bits when the graphics

0

port is selected by the PORTSEL bit. GHS can supply horizontal
sync information or digital composite sync information depending on
the COMPEN and SOGSEL bits.

SOG: Pin is sync-on-green. Driven by an external sync stripper
circuit, this pin is monitored (SOGACT status bit) and can supply

1

composite sync information (depending on SOGSEL & COMPEN
bits).

GCOAST 36 OS

GFBK 35 ID 5

GPort PLL Coast. Tells the PLL when to coast (ignore GREF) during
vertical blanking. Used to prevent the PLL from reacting to extra or missing
HS pulses during vertical blanking. Coast duration and polarity is
programmable through the PLLCM, PLLCB & PLLCE bits.

GPort PLL Feedback / Line Advance Input.

• When PORTSEL=0, this pin is not used.

• When PORTSEL=1, this pin has two different functions depending on the
EXTFCE bit:

EXTFCE GFBK Function

GFBK: An input that is typically driven by the FBK output of an ADC/
PLL device. In free running capture mode this signal is used to define
the horizontal capture region (along with the CAPL and CAPW

0

registers), and advances the GPort capture controller to the next
input line. The LAVPOL bit is used to select the polarity of GFBK.

GLAV: An input to the graphics port line advance. Used in external
flow control capture mode. When GLAV transitions (depending on

1

LAVPOL and LAVMOD bits), the GPort capture controller advances
to the next input line.

Pin Descriptions Pinout Information

Table 2-2 Graphics Port Pin Descriptions (continued)

Name Pin(s) Type Function

GRE0 20 ID 5

GRE1 21 ID 5

GRE2 22 ID 5

GRE3 23 ID 5

GRE4 24 ID 5

GRE5 25 ID 5

GRE6 26 ID 5

GRE7 27 ID 5

GGE0 10 ID 5

GGE1 11 ID 5

GGE2 12 ID 5

GGE3 13 ID 5

GGE4 14 ID 5

GGE5 15 ID 5

GGE6 18 ID 5

GGE7 19 ID 5

GBE0 2 ID 5

GBE1 3 ID 5

GBE2 4 ID 5

GBE3 5 ID 5

GBE4 6 ID 5

GBE5 7 ID 5

GBE6 8 ID 5

GBE7 9 ID 5

GPort Red Pixel Data. GPort Red Even Pixel Data when in 48-bit input
mode.

GPort Green Pixel Data. GPort Green Even Pixel Data when in 48-bit input
mode.

GPort Blue Pixel Data. GPort Blue Even Pixel Data when in 48-bit input
mode.

Ta bl e 2 -3 provides detailed Display/Graphics Port pin descriptions.

Table 2-3 Display/Graphics Port Pin Descriptions

Name Pin(s) Type Function

DGR0 136 I/O SR5

DGR1 135 I/O SR5

DGR2 134 I/O SR5

DGR3 133 I/O SR5

DGR4 132 I/O SR5

DGR5 131 I/O SR5

DGR6 130 I/O SR5

DGR7 129 I/O SR5

DGPort Red Pixel Data. In dual pixel output mode these pins are the ODD
red outputs. In single pixel output mode these pins are not used.

Pinout Information Pin Descriptions

Table 2-3 Display/Graphics Port Pin Descriptions (continued)

Name Pin(s) Type Function

DGG0 128 I/O SR5

DGG1 127 I/O SR5

DGG2 126 I/O SR5

DGG3 125 I/O SR5

DGG4 122 I/O SR5

DGG5 121 I/O SR5

DGG6 120 I/O SR5

DGG7 119 I/O SR5

DGB0 118 I/O SR5

DGB1 117 I/O SR5

DGB2 116 I/O SR5

DGB3 115 I/O SR5

DGB4 114 I/O SR5

DGB5 113 I/O SR5

DGB6 112 I/O SR5

DGB7 111 I/O SR5

DGPort Green Pixel Data. In dual pixel output mode these pins are the
ODD green outputs. In single pixel output mode these pins are not used.

DGPort Blue Pixel Data. In dual pixel output mode these pins are the ODD
blue outputs. In single pixel output mode these pins are not used.

Ta bl e 2 -4 provides detailed Display Port pin descriptions.

Table 2-4 Display Port Pin Descriptions

Name Pin(s) Type Function

DPort Pixel Clock. Output clock for the display port pixel data. DCLK is
enabled by the DCLKEN bit and can be inverted by the DCPOL bit. DCLK

DCLK 106 OSR

DCLKNEG 107 OSR • DPort Pixel Clock.

DVS 108 OS

DHS 109 OS

can be set to run at ½ pixel rate, for dual pixel output mode, by setting the
DCK2EN bit. The DCLK output can be disabled by the DCLKOFF bit
to reduce power consumption.

DPort Vertical Sync. DVS can be either active-high or active-low
depending on the VSPOL bit. Width and timing is controlled by the VPLSE
and VDLY registers.

DPort Vertical Sync. DHS can be either active-high or active-low
depending on the HSPOL bit. Sync width can be controlled by the HPLSE
register.

Pin Descriptions Pinout Information

Table 2-4 Display Port Pin Descriptions (continued)

Name Pin(s) Type Function

DEN 110 OS

DR0 103 OSR

DR1 102 OSR

DR2 101 OSR

DPort Pixel Enable. This signal is active whenever valid data is present.
The polarity is specified by the DENPOL bit.

DR3 100 OSR

DR4 99 OSR

DR5 98 OSR

DR6 97 OSR

DR7 96 OSR

DG0 95 OSR

DG1 94 OSR

DG2 93 OSR

DG3 92 OSR

DG4 91 OSR

DG5 90 OSR

DG6 89 OSR

DG7 88 OSR

DPort Red Pixel Data. In dual pixel output mode these pins are the EVEN
red outputs.

DPort Green Pixel Data. In dual pixel output mode these pins are the
EVEN green outputs. These pins can also be used in conjunction with the
PORTB pins for higher color depth.

DB0 83 OSR

DB1 82 OSR

DB2 81 OSR

DB3 80 OSR

DB4 79 OSR

DB5 78 OSR

DB6 77 OSR

DB7 76 OSR

DPort Blue Pixel Data. In dual pixel output mode these pins are the EVEN
blue outputs.

Pinout Information Pin Descriptions

Ta bl e 2 -5 provides detailed Microprocessor Interface pin descriptions.

Table 2-5 Microprocessor Interface Pin Descriptions

Name

WR 194 I/O D5 Write Enable. Low indicates a write to external RAM or other devices.

RD 195 I/O D5 Read Enable. Low indicates a read to external RAM or other devices.

ROMOE 196 OS ROM Output Enable. Low output indicates a read from external ROM.

ROMWE 197 OS ROM Write Enable. Low indicates a write to external ROM.

CS0 198 I/O D5 Miscellaneous Chip Select 0. Low selects external devices.

CS1 199 I/O D5

NMI 193 ID 5

A1 192 I/O D5

A2 191 I/O D5

A3 190 I/O D5

A4 189 I/O D5

A5 188 I/O D5

A6 187 I/O D5

A7 184 I/O D5

A8 183 I/O D5

A9 182 I/O D5

A10 181 I/O D5

A11 180 I/O D5

A12 179 I/O D5

A13 178 I/O D5

A14 177 I/O D5

A15 176 I/O D5

A16 175 I/O D5

A17 174 I/O D5

A18 173 I/O D5

A19 164 I/O D5

Pin(s) Type Function

Miscellaneous Chip Select 1. When EXTRAMEN=0, low selects external
devices.

Chip select for external RAM. When EXTRAMEN=1, low selects external
RAM. (RAMCS)

Non-Maskable Interrupt. A high input triggers a non-maskable interrupt to
the on-chip microprocessor.

Microprocessor address bus output bits (19:1).

Pin Descriptions Pinout Information

Table 2-5 Microprocessor Interface Pin Descriptions (continued)

Name

D0 163 I/O D5

D1 162 I/O D5

D2 161 I/O D5

D3 160 I/O D5

D4 159 I/O D5

D5 158 I/O D5

D6 157 I/O D5

D7 156 I/O D5

D8 155 I/O D5

D9 154 I/O D5

D10 153 I/O D5

D11 152 I/O D5

D12 151 I/O D5

D13 150 I/O D5

D14 149 I/O D5

D15 148 I/O D5

Pin(s) Type Function

Microprocessor 16-bit bidirectional data bus.

Ta bl e 2 -6 provides detailed Peripheral Interface pin descriptions.

Table 2-6 Peripheral Interface Pin Descriptions

Name Pin(s) Type Function

General-purpose I/O port bit controlled by PADAT0 and PAEN0. This pin

PORTA0 207 I/O U5

PORTA1 206 I/O U5

PORTA2 205 I/O U5

PORTA3 204 I/O U5

PORTA4 203 I/O U5

has one other possible function when EXTRAMEN=1.

When EXTRAMEN=1 and PAEN0=0, PORTA1 is microprocessor address
bit 0 (A0).

General-purpose I/O port bit controlled by PADAT1 and PAEN1. This pin
has one other possible function when EXTRAMEN=1.

When EXTRAMEN=1 and PAEN1=0, PORTA1 is microprocessor byte­high enable (BHEN)

General-purpose I/O port bit controlled by PADAT2 and PAEN2. This pin
has one other possible function when GREFEN=1.

When GREFEN=1 and PAEN2=0, PORTA2 is GPort PLL reference out, a
delayed version of internal horizontal sync (typically connected to the
external PLLs reference input) (GREF)

General-purpose I/O port bit controlled by PADAT3 and PAEN3. This pin
can also function as an external clock source for DCLK (DCLKEXT) when
the internal PLLs are disabled.

General-purpose I/O port bit controlled by PADAT4 and PAEN4. This pin
has one other possible function when IREN=1.

When IREN=1 and PAEN4=1, this pin can function as an input to the on­chip IR receiver 0. (IRRCVR0)

Pinout Information Pin Descriptions

Table 2-6 Peripheral Interface Pin Descriptions (continued)

Name Pin(s) Type Function

General-purpose I/O port bit controlled by PADAT5 and PAEN5. This pin
has other possible functions depending on the IREN, EIEN registers.

PORTA5 202 I/O U5

PORTA6 201 I/O U5

PORTA7 200 I/O D5

PORTB0 57 I/O D5

PORTB1 58 I/O D5

• When EIEN=1 and PAEN5=1, this pin can function as an external
interrupt to the on-chip CPU.

• When IREN=1 and PAEN5=1, this pin can function as an input to the on­chip IR receiver 1. (IRRCVR1). .

General-purpose I/O port bit controlled by PADAT6 and PAEN6. This pin
can also function as BLKSPL when BLKSMPLEN=1.

• When BLKSMPLEN=1 and PAEN6=0, PORTA6 is GPORT black sample
clamp pulse output (typically used as port of an external DC restoration
circuit) (BLKSPL) This pin has one other possible function when
PREF1EN=1.

• When PREF1EN=1 and PAEN6=0, PORTA6 is a variable duty-cycle
pulse reference generator (PWM) output controlled by PREF1HI and
PREF1LO.

General-purpose I/O port bit controlled by PADAT7 and PAEN7. This pin
has one other possible function when PREF0EN=1.

When PREF0EN=1 and PAEN7=0, PORTA7 is a variable duty-cycle pulse
reference generator (PWM) output controlled by PREF0HI and PREF0LO.

General purpose I/O port bit controlled by PBDAT0 and PBEN0. PORTB0
can also function as GRO0 when in 48 bit graphics input mode; VR0 when
in 24 bit RGB video input mode; Y0 when in 24 bit YUV video input mode.

General purpose I/O port bit controlled by PBDAT1 and PBEN1. PORTB1
can also function as GRO1 when in 48 bit graphics input mode; VR1 when
in 24 bit RGB video input mode; Y1 when in 24 bit YUV video input mode.

General purpose I/O port bit controlled by PBDAT2 and PBEN2. PORTB2
can also function as:

PORTB2 59 I/O D5

PORTB3 60 I/O D5

Function When in

DB1E Dual-pixel 27-bit output mode

DB0 30-bit output mode

GRO2 48-bit graphics input mode

VR2 24-bit RGB video input mode

Y2 24-bit YUV video input mode

Cb0 30-bit YCbCr input mode (CSCD30BIT).

General purpose I/O port bit controlled by PBDAT3 and PBEN3. PORTB3
can also function as:

Function When in

DB1O Dual-pixel 27-bit output mode

DB1 30-bit output mode

GRO3 48-bit graphics input mode

VR3 24-bit RGB video input mode

Y3 24-bit YUV video input mode

Cb1 30-bit YCbCr input mode (CSCD30BIT).

Pin Descriptions Pinout Information

Table 2-6 Peripheral Interface Pin Descriptions (continued)

Name Pin(s) Type Function

General purpose I/O port bit controlled by PBDAT4 and PBEN4. PORTB4
can also function as:

Function When in

DG1E Dual-pixel 27-bit output mode

PORTB4 61 I/O D5

General purpose I/O port bit controlled by PBDAT5 and PBEN5. PORTB5
can also function as:

PORTB5 62 I/O D5

DG0 30-bit output mode

GRO4 48-bit graphics input mode

VR4 24-bit RGB video input mode

Y4 24-bit YUV video input mode

Y0 30-bit YCbCr input mode (CSCD30BIT).

Function When in

DG10 Dual-pixel 27-bit output mode

DG1 30-bit output mode

GRO5 48-bit graphics input mode

VR5 24-bit RGB video input mode

Y5 24-bit YUV video input mode

Y1 30-bit YCbCr input mode (CSCD30BIT).

PORTB6 63 I/O D5

PORTB7 64 I/O D5

General purpose I/O port bit controlled by PBDAT6 and PBEN6. PORTB6
can also function as:

Function When in

DR1E Dual-pixel 27-bit output mode

DR0 30-bit output mode

GRO6 48-bit graphics input mode

VR6 24-bit RGB video input mode

Y6 24-bit YUV video input mode

Cr0 30-bit YCbCr input mode (CSCD30BIT).

General purpose I/O port bit controlled by PBDAT7 and PBEN7. PORTB7
can also function as:

Function When in

DR1O Dual-pixel 27-bit output mode

DR1 30-bit output mode

GRO7 48-bit graphics input mode

VR7 24-bit RGB video input mode

Y7 24-bit YUV video input mode

Cr1 30-bit YCbCr input mode (CSCD30BIT).

Pinout Information Pin Descriptions

Table 2-6 Peripheral Interface Pin Descriptions (continued)

Name Pin(s) Type Function

PORTC0 39 I/O D5 General purpose I/O port controlled by PCDAT(7:0) and PCEN(7:0).

PORTC1 40 I/O D5

PORTC2 41 I/O D5

PORTC3 42 I/O D5

PORTC4 43 I/O D5

PORTC5 44 I/O D5

PORTC6 45 I/O D5

PORTC7 46 I/O D5

RXD 67 I/O U5

TXD 68 I/O U5

PORTC(7:0) can also function as:

Function When

GBO(7:0) 48-bit graphics input mode

VB(7:0) 24-bit RGB video input mode

U(7:0) 24-bit YUV video input mode

UV(7:0) 16-bit YUV video input mode

Serial Receive Data. RXD is the serial receive data for the on-chip serial
port. This pin can also function as the 2-wire master data pin when
2WMEN=16.

Serial Transmit Data. TXD is the serial transmit data for the on-chip serial
port. This pin can also function as the 2-wire master clock output pin when
2WMEN=16.

Ta bl e 2 -7 provides detailed Miscellaneous pin descriptions.

Table 2-7 Miscellaneous Pin Descriptions

Name Pin(s) Type Function

TESTEN 142 ID 5 Test Mode Enable. Connect to ground for normal operation.

Bidirectional reset pin. This pin requires a pull-up resistor to V33 (VDDQ3).
The typical value is 3.3K ohm.

RESET_N 139 BOD

EXTRSTEN 28 ID 5

XI 169 I

XO 170 O Crystal Output. Connect to external crystal.

Ta bl e 2 -8

provides detailed Microprocessor Debug Port pin descriptions.

• When EXTRSTEN=1, RESET_N is an input.

• When EXTRSTEN=0, RESET_N is an output. In either case a low
indicates reset.

External Reset Enable.

• When EXTRSTEN=1, the internal reset is disabled and an external reset
must be supplied on the RESET_N pin.

• When EXTRSTEN=0, the internal reset is enabled and RESET_N
becomes a bidirectional pin that can be used to either drive external logic
in the system or receive an external reset signal.

Crystal Input. Connect to external crystal. XI can also function as the
MCLK input LVTTL-level signal from an external oscillator.

Table 2-8 Microprocessor Debug Port Pin Descriptions

Name Pin(s) Type Function

TRST_N 147 ID 5 Debug port reset (low true). Leave floating if debug port is not being used.

TCK 146 ID 5

TMS 145 ID 5 Debug port mode select. Leave floating or pull to ground to disable.

TDI 144 ID 5 Debug port serial data in. Leave floating if debug port is not being used.

TDO 143 I/O D5 Debug port serial data out. Leave floating if debug port is not being used.

Debug port serial data clock. Leave floating if debug port is not being
used.

Pin Descriptions Pinout Information

Ta bl e 2 -9 provides detailed Power and Ground pin descriptions.

Table 2-9 Power and Ground Pin Descriptions

Name

VDD1

VSS

VDDQ3

VSSQ

VDDPA1 167 P 1.8V analog clock generator power.

VDDPA2 165 P 1.8V analog clock generator power.

VSSPA1 168 P Clock generator analog ground.

VSSPA2 166 P Clock generator analog ground.

Pin(s) Type Function

16,37,65,84,

137,185

17,38,66,85,

138,186

29,52,72,86,

104,123,140,

171,208

1, 30, 53, 73, 87,

105, 124, 141,

172,

P 1.8V digital core power.

P Digital core ground.

P 3.3V digital I/O power.

P Digital I/O ground.

Pinout Information Pin Descriptions

MCUCMD

MCUWR

MCUCS

PVSS

MCURDY

VSS

MCUD7

MCUD6

MCUD5

MCUD4

MCUD3

MCUD2

PVDD

MCUD1

MCUD0

MCUA7

MCUA6

VDD

MCUA5

MCUA4

MCUA3

PVSS

MCUA2

MCUA1

MCUA0

ADGVSS

ADGVDD

PVDD

ADAVSS

ADAVDD

VREFOUT

VREFIN

COMP

RSE T

AVS33R

AVD33R

ADR

AVS33G

AVD33G

ADG

AVS33B

AVD33B

ADB

ADDV DD

ADDVSS

PVSS

CGMS

DEN

TES TCLK

PVDD

DR7

DR6

VDD

DR5

DR4

PVSS

DR3

DR2

VSS

DR1

DR0

PVDD

DG7

DG6

192

191

190

189

188

187

186

185

184

183

182

181

180

179

178

177

176

175

174

173

172

171

170

169

168

167

166

165

164

163

162

161

160

159

158

157

156

155

154

153

152

151

150

149

148

147

146

145

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

PVSS

NC
NC

DPAVSS
DPA VDD
DPDV SS
DPDVDD

PVDD

NC

PVSS

MA 4
MA 3
VDD
MA 5
MA 2

PVDD

MA 6
MA 1
MA 7

PVSS

MA 0
MA 8

MA 10

PVDD

MA 9

MA 13

VSS
MA 11
MA 12
PVSS

MC LK F B

PVDD
MRA S
MCA S

MW E
PVSS

MCL K
PVDD

MD8
MD7

PVSS

MD9
VDD
MD6

PVDD

MD1 0

MD5
PVSS
MD1 1

MD4

PVDD

MD1 2

MD3
PVSS
MD1 3

MD2

PVDD

MD1 4

VSS

MD1
PVSS
MD1 5

MD0

PVDD

193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263

VB0

VB1

VB2

VB3

VB4

VB5

VB6

VB7

VDD

PVSS

VG0

VG1

SVHS

SVVS

VG2

PVDD

SVCLK

PW1235

VSS

VG3

VG4

VG5

VG6

VG7

PVSS

PVCLK

VR0

PVVS

VR1

PVHS

PVDD

CREF

VR2

VR3

VR4

VR5

VR6

VR7

VDD

PVSS

XTALI

XTALO

PVSS

PVDD

2WA1

2WA2

2WCLK

TDI

VSS

TDO

TCK

TMS

TES T

PVSS

PVDD

2WDAT

TRS TN

RES ETn

MPDVDD

MPDVSS

128

DG5

127

DG4

126

PVSS

125

DG3

124

DG2

123

VDD

122

DG1

121

DG0

120

PVDD

119

DB7

118

DB6

117

DB5

116

DB4

115

PVSS

114

DB3

113

DB2

112

VSS

111

DB1

110

DB0

109

PVDD

108

DENR

107

DENB

106

DENG

105

PVSS

104

DHS

103

DVS

102

DCLK

101

PVDD

100

DGR7

99

DGR6

98

DGR5

97

DGR4

96

PVSS

95

DGR3

94

DGR2

93

VDD

92

DGR1

91

DGR0

90

PVDD

89

DGG7

88

DGG6

87

DGG5

86

DGG4

85

PVSS

84

DGG3

83

DGG2

82

DGG1

81

DGG0

80

PVDD

79

DGB7

78

DGB6

77

VSS

76

DGB5

75

DGB4

74

PVSS

73

DGB3

72

DGB2

71

DGB1

70

DGB0

69

PVDD

68

DGCLK

67

DGVS

66

DGHS

65

PVSS

64

NC

NC

PVDD

MPAVSS

MPAVDD

Figure 2-1 Pin Layout

Pin Descriptions Pinout Information

2.2.1 Video Port Pins

Ta bl e 2 -1 provides detailed pin descriptions for the Video Port.

Table 2-1 Video Port Pin Descriptions

Name Pin(s) Typ e Function

Primary Video (PV) Port horizontal sync input. Indicates start of next line of input data.

PVHS 28 I

PVVS 27 I

This signal is internally polarity corrected (PVHS_POL) so PVHS can be either active­high or active-low. [Input, pull-down, 5V-tolerant]

Primary Video (PV) Port vertical sync input. Indicates start of next field or frame of
input data. This signal is internally polarity corrected (PVVS_POL) so PVVS can be
either active-high or active-low. [Input, pull-down, 5V-tolerant]

Video input clock reference. [Input, pull-down, 5V-tolerant]

• cref_mode = 1

PVCLK

CREF

CREF 26 I

PVCLK 25 I

SVVS 12 I

SVHS 11 I

SVCLK 13 I

VR, VG, VB

0

1

samp li n g poi n ts

N-1

N

• cref_mode = 0

PVCLK

CREF

VR, VG, VB

0 1 N-1

sampling points

Primary Video (PV) Port pixel clock input. [Input, pull-down, 5V-tolerant]

Secondary Video (SV) Port (ITU-R BT656 format) vertical sync input. Indicates start of
next field or frame of input data. This signal is internally polarity corrected (svvs_pol)
so SVVS can be either active-high or active-low. [Input, pull-down, 5V-tolerant]

Secondary Video (SV) Port (ITU-R BT656 format) horizontal sync input. This signal is
internally polarity corrected (svhs_pol) so SVHS can be either active-high or active­low. [Input, pull-down, 5V-tolerant]

Secondary Video (SV) Port (ITU-R BT656 format) pixel clock input. [Input, pull-down,
5V-tolerant]

N

Pinout Information Pin Descriptions

Table 2-1 Video Port Pin Descriptions (continued)

Name Pin(s) Typ e Function

VR0 30 I

VR1 31 I

VR2 32 I

VR3 33 I

VR4 35 I

VR5 36 I

VR6 37 I

VR7 38 I

Video port red data input. These pins have different functions depending on the
settings of the PVmode register. [Input, pull-down, 5V-tolerant]

PV_mode VR[7:0] Pin Function

00 Reserved.

01

10

11

Primary Video (PV) Port.
UV[7:4]: ITU-R BT601 YUV 4:1:1 UV pixel data.

Primary Video (PV) Port
UV[7:0]: ITU-R BT601 YUV 4:2:2 UV pixel data.

Primary Video (PV) Port.
R[7:0]: red pixel data or
V[7:0]: ITU-R BT601 YUV 4:4:4 pixel data.

VG0 15 I

VG1 16 I

VG2 17 I

VG3 18 I

VG4 20 I

VG5 21 I

VG6 22 I

VG7 23 I

VB0 1 I

VB1 2 I

VB2 3 I

VB3 4 I

VB4 6 I

VB5 7 I

VB6 8 I

VB7 9 I

Video port green data input. These pins have different functions depending on the
settings of the Primary Video (PV) Port mode registers. [Input, pull-down, 5V-tolerant]

PV_mode VG[7:0] Pin Function

00 Reserved.

01

10

11

Primary Video (PV) Port.
Y[7:0]: ITU-R BT601 YUV 4:1:1 UV pixel data.

Primary Video (PV) Port.
Y[7:0]: ITU-R BT601 YUV 4:2:2 UV pixel data.

Primary Video (PV) Port.
G[7:0]: green pixel data or
Y[7:0]: ITU-R BT601 YUV 4:4:4 pixel data.

Video port blue data input. These pins have different functions depending on the
settings for the Primary Video (PV) Port mode registers. [Input, pull-down, 5V-tolerant]

PV_mode VB[7:0] Pin Function

00 Reserved.

01
10

11

Secondary Video (SV) Port
YUV[7:0]: ITU-R BT656 format pixel data.

Primary Video (PV) Port.
B[7:0]: blue pixel data or
U[7:0]: ITU-R BT601 YUV 4:4:4 pixel data.

2.2.2 Digital/Graphics (DG) Port Pins

Ta bl e 2 -2 provides detailed pin descriptions for the Digital/Graphics (DG) Port.

Table 2-2 Digital/Graphics (DG) Port Pin Descriptions

Name Pin(s) Typ e Function

DGS 67 I

DGHS 66 I

DGCLK 68 I

Digital/Graphics (DG) port vertical sync.

[Tri-state output, 4mA drive, 5V-tolerant]
Digital/Graphics (DG) port horizontal sync.

[Tri-state output, 4mA drive, 5V-tolerant]
Digital/Graphics (DG) port pixel clock.

[Tri-state output, 8mA drive, 5V-tolerant]

Pin Descriptions Pinout Information

Table 2-2 Digital/Graphics (DG) Port Pin Descriptions (continued)

Name Pin(s) Typ e Function

DGR0 91 I

DGR1 92 I

DGR2 94 I

DGR3 95 I

DGR4 97 I

DGR5 98 I

DGR6 99 I

DGR7 100 I

DGG0 81 I

DGG1 82 I

DGG2 83 I

DGG3 84 I

DGG4 86 I

DGG5 87 I

DGG6 88 I

DGG7 89 I

DGB0 70 I

DGB1 71 I

DGB2 72 I

DGB3 73 I

DGB4 75 I

DGB5 76 I

DGB6 78 I

DGB7 79 I

Digital/Graphics (DG) port red data. [Bi-directional, input with pull-down, tri-state 4mA
drive output, 5V-tolerant]

DGR[7:0] Pin Function

Digital/Graphics (DG) Port input (single pixel mode).
R[7:0]: red pixel data or
V[7:0]: YUV 4:4:4 pixel data.

Digital/Graphics (DG) port green data. [Bi-directional, input with pull-down, tri-state
4mA drive output, 5V-tolerant]

DGG[7:0] Pin Function

Digital/Graphics (DG) Port input (single pixel mode).
G[7:0]: green pixel data or
Y[7:0]: YUV 4:4:4 pixel data.

Digital/Graphics (DG) port blue data. [Bi-directional, input with pull-down, tri-state 4mA
drive output, 5V-tolerant]

DGB[7:0] Pin Function

Digital/Graphics (DG) Port input (single pixel mode).
B[7:0]: blue pixel data or
U[7:0]: YUV 4:4:4 pixel data.

2.2.3 System Power Pins

Ta bl e 2 -3 provides detailed pin descriptions for System Power.

Table 2-3 System Power Pin Descriptions

Name Pin(s) Typ e Function

5, 34, 93,

VDD

VSS

123, 140,
175, 205,

235

19, 49,

77, 112,

134, 187,

219, 251

Digital core power (2.5V).

P

Digital core ground.

G

Pinout Information Pin Descriptions

Table 2-3 System Power Pin Descriptions (continued)

Name Pin(s) Typ e Function

14, 29,
42, 54,
64, 69,
80, 90,

101, 109,

PVDD

PVSS

MPAVDD 60 P

MPAV SS 61 G

MPDVDD 58 P

MPDVSS 59 G

DPAV DD 197 P

DPAVSS 196 G

DPDVDD 199 P

DPDVSS 198 G

AVD33R 157 P

AVD33G 154 P

AVD33B 151 P

AVS33R 158 G

AVS33G 155 G

AVS33B 152 G

ADAVDD 163 P

ADAVSS 164 G

ADDVDD 149 P

ADDVSS 148 G

ADGVDD 166 P

ADGVSS 167 G

120, 131,
143, 165,
180, 200,
208, 216,
224, 230,
237, 243,

249, 256

10, 24,
39, 46,
57, 65,
74, 85,

96, 105,
115, 126,
137, 147,
171, 189,
193, 202,
212, 222,
228, 233,
240, 246,

253

Digital I/O power (3.3V).

P

Ground.

G

Memory PLL analog power 2.5V.

Memory PLL analog ground.

Memory PLL guard ring / digital power 2.5V.

Memory PLL guard ring / digital ground.

Display PLL analog power 2.5V.

Display PLL analog ground.

Display PLL digital power 2.5V.

Display PLL digital ground.

Analog power (+3.3V) for R (V/Pr) channel.

Analog power (+3.3V) for G (Y/Y) channel.

Analog power (+3.3V) for B (U/Pb) channel.

Analog ground for R (V/Pr) channel.

Analog ground for G (Y/Y) channel.

Analog ground for B (U/Pb) channel.

Analog power supply (+2.5V) for the analog display port.

Analog ground for the analog display port.

Digital power supply (+2.5V) for the analog display port.

Digital ground for the analog display port.

Guard ring power for the analog display port.

Guard ring ground for the analog display port.

Pin Descriptions Pinout Information

2.2.4 Miscellaneous Pins

Ta bl e 2 -4 provides detailed descriptions for Miscellaneous Pins.

Table 2-4 Miscellaneous Pin Descriptions

Name Pin(s) Typ e Function

XTALI 40 I

XTALO 41 O

RESETn 55 I

CGMS 146 I

TCK 50 I

TDI 51 I

TDO 48 O

TMS 52 I

TRSTn 53 I

TEST 56 I

TESTCLK 144 I

NC 201 -

NC

62, 63,

194,195

Crystal oscillator input. Connect to an external 10MHz crystal.

Crystal oscillator output. Connect to an external 10MHz crystal.

Hardware asynchronous reset. The signal is active low. Must be continuously asserted
for a minimum of 100 µs after power-up to satisfy the SDRAM power-up requirement.

[Input, Schmitt trigger, pull-up, 5V-tolerant]

CGMS Enable

Debug port test data clock. TCK provides the clock input for the Test Bus (also known
as the Test Access Port).

Debug port test data in. TDI transfers serial test data into VISTA. TDI provides the
serial input necessary for JTAG specification support.

Debug port test data out. TDO transfers serial test data out of VISTA. TDO provides
the serial input necessary for JTAG specification support.

Debug port test mode select. TMS is a JTAG specification support signal used by
debug tools.

Debug port test reset. TRSTn resets the Test Access Port (TAP) logic. TRSTn must be
driven low during power on RESETn.

Test mode. Active high. Must be low during normal operation. [Input, pull-down, 5V­tolerant]

Used for testing, can be used to supply display clock. [Input, pull-down, 5V-tolerant]

No connect.

No connect.

-

2.2.5 Host Interface Pins

Ta bl e 2 -5 provides detailed pin descriptions for the Host Interface.

Table 2-5 Host Interface Pin Descriptions

Name Pin(s) Typ e Function

2WCLK 45 I

2WDAT 47 I/O

2WA1 43 I

2WA2 44 I

Clock signal of two-wire serial bus. [Input, pull-up, 5V-tolerant]

Data signal of two-wire serial bus. [Bi-directional, tri-state 4mA drive output, 5V­tolerant]

Programmable two-wire serial bus address bit 1. [Input, pull-down, 5V-tolerant]

Programmable two-wire serial bus address bit 2. [Input, pull-down, 5V-tolerant]

2.2.6 Memory Pins

Ta bl e 2 -6 provides detailed pin descriptions for Memory.

Table 2-6 Memory Pin Descriptions

Name Pin(s) Typ e Function

MCLK 229 O

MCLKFB 223 I

SDRAM clock. This signal is rising edge active. [Tri-state output, 8mA drive,
5V-tolerant]

SDRAM clock feedback. For latching in read data. [Input, 5V-tolerant]

Pinout Information Pin Descriptions

Table 2-6 Memory Pin Descriptions (continued)

Name Pin(s) Typ e Function

MRAS 225 O

MCAS 226 O

MWE 227 O

MA0 213 O

MA1 210 O

MA2 207 O

MA3 204 O

MA4 203 O

MA5 206 O

MA6 209 O

MA7 211 O

MA8 214 O

MA9 217 O

MA10 215 O

MA11 220 O

MA12 221 O

MA13 218 O

MD0 255 I/O

MD1 252 I/O

MD2 248 I/O

MD3 245 I/O

MD4 242 I/O

MD5 239 I/O

MD6 236 I/O

MD7 232 I/O

MD8 231 I/O

MD9 234 I/O

MD10 238 I/O

MD11 241 I/O

MD12 244 I/O

MD13 247 I/O

MD14 250 I/O

MD15 254 I/O

SDRAM row address strobe. This signal is active low. [Tri-state output, 8mA drive,
5V-tolerant]

SDRAM column address strobe. This signal is active low. [Tri-state output, 8mA drive,
5V-tolerant]

SDRAM write enable. This signal is active low. [Tri-state output, 8mA drive,
5V-tolerant]

SDRAM address bus. Multiplexed row and column address and bank select. Row
addresses use MA[11:0] for 8MB SDRAM and MA[10:0] for 2MB SDRAM. Column
addresses use MA[7:0]. [Tri-state output, 8mA drive, 5V-tolerant]

Note: MA10 is a control signal during column address charging and pre-charging.

For 8MB SDRAM the bank select pins ba0 and ba1 should be connected to MA12 and
MA13, respectively. For 2MB SDRAM, connect ba0 to MA12.

SDRAM data bus. [Bi-directional, tri-state 8mA drive output, pull-up, 5V-tolerant]

2.2.7 Digital Display Output Port Pins

Ta bl e 2 -7 provides detailed pin descriptions for the Digital Display Output Port.

Table 2-7 Digital Display Output Port Pin Descriptions

Name Pin(s) Typ e Function

DVS 103 O

DHS 104 O

DCLK 102 O

Digital display output port vertical sync. [Tri-state output, 4mA drive, 5V-tolerant]

Digital display output port horizontal sync. [Tri-state output, 4mA drive, 5V-tolerant]

Digital display output port pixel clock. [Tri-state output, 8mA drive, 5V-tolerant]

Pin Descriptions Pinout Information

Table 2-7 Digital Display Output Port Pin Descriptions (continued)

Name Pin(s) Typ e Function

DENR 108 O

DENG 106 O

DENB 107 O

DEN 145 I

DR0 132 O

DR1 133 O

DR2 135 O

DR3 136 O

DR4 138 O

DR5 139 O

DR6 141 O

DR7 142 O

DG0 121 O

DG1 122 O

DG2 124 O

DG3 125 O

DG4 127 O

DG5 128 O

DG6 129 O

DG7 130 O

DB0 110 O

DB 1 111 O

DB2 113 O

DB3 114 O

DB4 116 O

DB5 117 O

DB6 118 O

DB7 119 O

Display pixel enable red. [Tri-state output, 4mA drive, 5V-tolerant]

Digital display pixel enable green. [Tri-state output, 4mA drive, 5V-tolerant]

Digital display pixel enable blue. [Tri-state output, 4mA drive, 5V-tolerant]

Digital display output port output enable. [Input, pull-up, 5V-tolerant]
Active level controlled by DEN_POL [reg 0x61 bit 2].

Note: DEN only controls the data bus [DR(7:0), DG(7:0), DB(7:0)] and not the control
signals [DVS, DHS, DCLK, DENR, DENG, DENB].

Digital display output port red data. [Tri-state output, 4mA drive, 5V-tolerant]

uv_mode DR[7:0] Pin Function

DPort single pixel output.

000

011 UV[7:0]: ITU-R BT601 YUV 4:2:2 pixel data

R[7:0]: red pixel data or
V[7:0]: YUV 4:4:4 pixel data.

Digital display output port green data. [Tri-state output, 4mA drive, 5V-tolerant]

uv_mode DG[7:0] Pin Function

DPort single pixel output.

000

011 Y[7:0]: ITU-R BT601 YUV 4:2:2 pixel data

G[7:0]: green pixel data or
Y[7:0]: YUV 4:4:4 pixel data

Digital display output port blue data. [Tri-state output, 4mA drive, 5V-tolerant]

uv_mode DB[7:0] Pin Function

xxx

DPort single pixel output.
B[7:0]: blue pixel data or
U[7:0]: YUV 4:4:4 pixel data.

2.2.8 Analog Display Port Pins

Ta bl e 2 -8 provides detailed pin descriptions for the Analog Display Port.

Table 2-8 Analog Display Port Pin Descriptions

Name Pin(s) Typ e Function

ADR 156 O

ADG 153 O

ADB 150 O

VREFIN 161 I

VREFOUT 162 O

Analog display port red (V/Pr) data.

Analog display port green (Y/Y) data.

Analog display port blue (U/Pb) data.

Reference voltage input.

Voltage reference output. This output nominally delivers 1.23v reference voltage from
bandgap reference block. It is normally connected to VREFIN pin.

Pinout Information Pin Descriptions

Table 2-8 Analog Display Port Pin Descriptions (continued)

Name Pin(s) Typ e Function

Full-Scale adjust resistor. A resistor should be connected between this pin and AVS33
to control the magnitude of the full-scale video signal.

RSET 159 I/O

COMP 160 i/O

RSET(ohm)=VREFIN(V)*10.66/IOFS(A),

where IOFS is full-scale output current.
Compensation pin. This pin should be connected through 0.1uF ceramic capacitor to

AVD33 (+3.3v) externally.

PIN CONFIGURATION

GND

AV
GND

VSOUT

SOG

OUT

HSOUT

DCK

GND

V

R[7]

R[6]
R[5]
R[4]
R[3]
R[2]
R[1]
R[0]

V
V

GND

61
62

DD

63
64
65
66
67
68
69

DD

70

MST9883B

71
72
73
74
75
76
77
78

DD

79

DD

Pin 1
IDENTIFIER

80

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

GND
AV

DD

CLAMP

MIDSCV
GND
PV

DD

PV

DD

FILT
GND

VSYNC
HSYNC
COAST
GND
PV

DD

PV

DD

GND
GND

V

DD

V

DD

GND

PIN DESCRIPTIONS

Pin Name Pin Type Function Pin Number(s)

REDIN Analog Input Red analog input 54
GRNIN Analog Input Green analog input 48
BLUIN Analog Input Blue analog input 43
SOGIN Analog Input Sync on Green analog input 49

CLAMP Digital CMOS Input External Clamp Input 38
HSYNC Digital CMOS Input Horizontal SYNC Input 30
VSYNC Digital CMOS Input Vertical SYNC Input 31
COAST Digital CMOS Input Hold PLL Frequency, do not track HSYNC 29

SCL Digital CMOS Input Serial Interface clock 56
SDA Digital CMOS Input/Output Serial Interface data pin 57
A0 Digital CMOS Input Serial interface address pin 55

R [7:0] Digital CMOS 3-state Output Red output data 70-77
G [7:0] Digital CMOS 3-state Output Green output data 2-9
B [7:0] Digital CMOS 3-state Output Blue output data 12-19
DCK Digital CMOS 3-state Output Output data clock 67
HSOUT Digital CMOS 3-state Output HSYNC output 66
VSOUT Digital CMOS 3-state Output VSYNC output 64
SOG

Digital CMOS 3-state Output SYNC on Green Slicer Output 65

OUT

FILT No Connection 33

VREF Reference Internal Reference Bypass 58
MIDSCV Reference Internal Mid-Scale Voltage Bypass 37

AVDD 3.3v Power Analog Power 39,42,45,46,51,52,59,62
PVDD 3.3v Power PLL Power 26,27,34,35
VDD 3.3v Power Digital Output Power 11,22, 23, 69,78,79

1,10,20,21,24,25,28,32,36,4

GND System Ground System Ground

0,41,44,47,50,53,60,61,63,6
8,80

PIN CONFIGURATION

VDD
DQ0

DDQ

V

DQ1
DQ2

SSQ

V

DQ3
DQ4

DDQ

V

DQ5
DQ6

SSQ

V

DQ7

DD

V

LDQM

/WE
/CAS
/RAS

/CS
BA0
BA1

A10/ AP

A0
A1
A2
A3

DD

V

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

54pin TSOP II

400mil x 875mil

0.8mm pin pitch

16
17
18
19
20
21
22
23
24
25
26
27

VSS

54

DQ15

53

SSQ

V

52

DQ14

51

DQ13

50

DDQ

V

49

DQ12

48

DQ11

47

SSQ

V

46

DQ10

45

DQ9

44

DDQ

V

43

DQ8

42

SS

V

41

NC

40

UDQM

39

CLK

38

CKE

37

NC

36

A11

35

A9

34

A8

33

A7

32

A6

31

A5

30

A4

29

SS

V

28

PIN DESCRIPTION

PIN PIN NAME DESCRIPTION

CLK Clock

CKE Clock Enable

CS

BA0,BA1 Bank Address

A0 ~ A11 Address

RAS

, CAS, WE

LDQM, UDQM Data Input/Output Mask Controls output buffers in read mode and masks input data in write mode

DQ0 ~ DQ15 Data Input/Output Multiplexed data input / output pin

DD/VSS Power Supply/Ground Power supply for internal circuits and input buffers

V

V

DDQ/VSSQ Data Output Power/Ground Power supply for output buffers

NC No Connection No connection

Chip Select Enables or disables all inputs except CLK, CKE and DQM

Row Address Strobe,
Column Address Strobe,
Write Enable

The system clock input. All other inputs are registered to the SDRAM on the
rising edge of CLK

Controls internal clock signal and when deactivated, the SDRAM will be one
of the states among power down, suspend or self refresh

Selects bank to be activated during RAS
Selects bank to be read/written during CAS

Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA7
Auto-precharge flag : A10

, CAS and WE define the operation

RAS
Refer function truth table for details

activity

activity

CONNECTION DIAGRAMS

This device is also available in Known Good Die (KGD) form. Refer to publication number 21536 for
more information.

A15
A14

A13
A12
A11
A10

A9

A8
NC
NC

WE#

RESET#

NC
NC

RY/BY#

A18
A17

A7

A6

A5

A4

A3

A2

A1

A16

BYTE#

V

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

V

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

OE#

V

CE#

SS

CC

SS

A0

1
2

3
4
5
6
7
8
9
10
11
12
13
14
15

16
17
18

19

20

21

22

23

24

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

Standard TSOP

Reverse TSOP

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

A16
BYTE#
V

SS

DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4

V

CC

DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#

V

SS

CE#

A0

A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
RESET#
NC
NC
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1

21490G-2

CONNECTION DIAGRAMS

This device is also available in Known Good Die (KGD) form. Refer to publication number 21536 for
more information.

RY/BY#

A18
A17

A7
A6
A5
A4
A3
A2
A1
A0

CE#

V
OE#
DQ0
DQ8
DQ1
DQ9
DQ2

DQ10

DQ3

DQ11

SS

10
11
12
13
14
15
16
17
18
19
20
21
22

1
2
3
4
5
6
7
8
9

SO

44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23

RESET#
WE#
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE#
V

SS

DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V

CC

FBGA

Top View, Balls Facing Down

A6 B6 C6 D6 E6 F6 G6 H6

BYTE#A16A15A14A12A13

DQ15/A-1 V

SS

A5 B5 C5 D5 E5 F5 G5 H5

DQ13 DQ6DQ14DQ7A11A10A8A9

A4 B4 C4 D4 E4 F4 G4 H4

V

CC

DQ4DQ12DQ5NCNCRESET#WE#

A3 B3 C3 D3 E3 F3 G3 H3

DQ11 DQ3DQ10DQ2NCA18NCRY/BY#

A2 B2 C2 D2 E2 F2 G2 H2

DQ9 DQ1DQ8DQ0A5A6A17A7

A1 B1 C1 D1 E1 F1 G1 H1

CE#A0A1A2A4A3

OE# V

SS

Special Handling Instructions for FBGA
Package

Special handling is required for Flash Memory products
in FBGA packages.

Flash memory devices in FBGA packages may be
damaged if exposed to ultrasonic cleaning methods.
The package and/or data integrity may be
compromised if the package bod y is exposed to
temperatures above 150°C for prolonged periods of
time.

PIN CONFIGURATION

A0–A18 = 19 addresses
DQ0–DQ14 = 15 data inputs/outputs
DQ15/A-1 = DQ15 (data input/output, word mode),

A-1 (LSB address input, byte mode)
BYTE# = Selects 8-bit or 16-bit mode
CE# = Chip enable
OE# = Output enable
WE# = Write enable
RESET# = Hardware reset pin, active low
RY/BY# = Ready/Busy# output

= 3.0 volt-only single power supply

V

CC

V

SS

NC = Pin not connected internally

(see Product Selector Guide for speed

options and voltage supply toleranc es)

= Device ground

LOGIC SYMBOL

19

A0–A18

CE#
OE#

WE#
RESET#
BYTE# RY/BY#

16 or 8

DQ0–DQ15

(A-1)

PIN DESCRIPTION

Table 1. Z862 29 Pin Identification*

I2C SEL

GREEN

BLUE

SEN

HIN

SMS

VIDEO

CSYNC

LPF

1

2
3

4

5
6
7
8
9

18-Pin

DIP/SOIC

Figure 2. Z86229 Pin Configuration

18

17
16
15

14
13
12
11
10

RED
BOX
SDO
SCK
SDA

/INTRO

V

IN

V

DD

VSS(A)
RREF

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Note: *DIP and SOIC pin configurations are identical.

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&&

*

+0

*

176



+0



176



&&

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&

<

56)

<

.

Notes:
*Voltages referenced to V
operation should be restricted to the limits specified in the DC and AC Characteristicstables or Pin Description section.

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(A). Values beyond the maximum ratings listed above may cause damage to the device. Functional

SS







PIN DEFINITIONS
Inputs

I2CSEL(Pin1).This pinselects 28h for writing and29h for

reading when this input is Low(0). When the input is
High(1), the device selects 2Ah for writing and 2Bh for
reading.

SEN (Pin 4). This pin enables the signal for the SPI mode

of operation onthe SerialControl Port. Whenthis pinis Low
(0), the SPI port is disabled and the SDO pin is in the high­impedance state. Transitions on the SCK and SDA pins are
ignored. SPI mode operation is enabled when SMS is High
(1).

HIN (Pin 5). For this pin, the Horizontal Sync input signal

at the CMOS level must be supplied. When the device is
used in VIDEO-LOCK mode, the signal pulls the on-chip
VCO within theproper range.The circuituses thefrequency
of this signal, which must be within +
signal can be of either polarity. When used in the H-lock
mode, the VCO phase locks to the rising edge of thissignal.
The HPOLbit of the HPosition registercan be setto operate
with either polarity of input signal. This signal is usually
the H Flyback signal. The timing difference between HIN
rising edge and theleading edge of composite sync (of VID­EO input) is one of the factors which affects the horizontal
position of the display. Any shift resulting from the timing
of this signal can be compensated for with the horizontal
timing value in the H Position Register. H-lock is intended
for use when the part is generating an OSD display when
no video signal is present.

SMS (Pin 6). This pin allows the mode select pin forthe Se-

rial Control Port. When this input is at a CMOS High state
(1), the Serial Control Port operates in the SPI mode. When
the input is Low (0), the Serial Control Port operates in the

2

C slave mode.In SPImode, theSEN pin must be tiedHigh.

I
(See Reset Operation section.)

VIDEO (Pin 7). This pin is a composite NTSC video input,

1.0V p-p (nom), band limited to 600 kHz. The circuit op­erates with signal variation between 0.7–1.4V p-p. The po­larity is sync tips negative. This signal pin should be AC
coupled through a 0.1 µF capacitor, driven by a source im­pedance of 470 ohms or less.

3% Fh, but the overall

Reset Operation. When the SMS and SEN pins are both in

the Low (0) state, the part is in the Reset state; therefore, in

2

the I

C mode, the SEN pin can be used as an NReset input.
When SPI mode is used, if three wire operation is required,
bothSMSandSENcanbetiedtogetherandusedasthe
NReset input. In either mode, NReset must be held Low (0)
for at least 100 ns.

Input/Output

VIN/INTRO (Pin 13). In external (EXT) vertical lock mode

of operation, the internal vertical sync circuits lock to the

input signal applied at this pin. The part locks to the

V

IN

rising or falling edge of the signal in accordance with the
setting of the V Polarity command. The default is rising
edge. The V

pulse must be at least 2 lines wide.

IN

In INTRO Mode, when configured forinternal vertical syn­chronization, this pinis an output pin providing an interrupt
signal to the master control device in accordance with the
settings in the Interrupt Mask Register.

SDA (Pin 14). When the Serial Control Port has been set to

2

I

C mode operation, this pin serves as the bidirectional data
line for sending and receiving serial data. In SPI mode op­eration, the device operates as a serial data input. SPI mode
output data is available on the SDO pin.

Outputs

RED, GREEN, BLUE (Pins 2, 3, 18). These pins are osi-

tive-acting CMOS-level signals.

• Color Mode: Red, Green, and Blue characters are in-

corporated as video outputs for use in a color receiver

• Mono Mode: In this mode, all three outputs carry the

character luminance information

Note: The selection of Color/Mono Mode is user controlled in

bit D

of the Configuration Register (Address=00h). (See

1

Internal Registers section.)

CSync (Pin 8).

tied between this pin and analog ground V
pacitor stores the sync slice level voltage.

Sync slice level. A 0.1 µF capacitor must be

(A). This ca-

SS

SCK (Pin 15). This pin is an input for a serial clock signal

from the master control device. In I
clock rate is expected to be within I

2

C mode operation, the

2

C limits. In SPI mode,

the maximum clock frequency is 10 MHz.

LPF (Pin 9). Loop Filter. A series RC low-pass filter must

be tied between this pin and analog ground VSS(A). There
must also be second capacitor from the pin to V

SS

(A).





RREF (Pin 10 ). Reference settingresistor. Resistormust be

10 kOhms, ±2%.

SDO (Pin 16). This pin provides theserial dataoutput when

SPI mode communications have been selected. This pin is

2

not used in I

BOX (Pin 17). Black box keying output is an active High,

C mode operation.

CMOS-level signal used to key in the black box for cap­tions/text displays. This output is in ahigh-impedance state
when the background attribute has been set to semi-trans­parent.

Power Supply

VSS(Pins 11). These pins are the lowest potential power

pins for the analog and digital circuits. They are normally
tied to system ground.

VDD(Pin 12). The voltage on this pin is nominally 5.0

Volts, and may range between 4.75 to 5.25 Volts with re­spect to the VSSpins.

Note: The recommended printed circuit pattern for implement-

ing the power connection and critical components is ref­erenced in the Recommended Application Information
sectiononpage49.

General Description

The MM74HC374 hi gh speed Octal D-Type Flip-Flops uti­lize advanced silicon-gate CMOS technology. They pos­sess the high noise im munity and low power consumpti on
of standard CMOS integrated circuits, as well as the ability
to drive 15 LS-TTL loads. Due to the large output drive
capability and the 3-STATE feature, these devices are ide­ally suited for interfacing with bus lines in a bus organized
system.

These devices are positive edge triggered flip- flops. Data
at the D inputs, meeting the setup and hold ti me require­ments, are transferred to th e Q outputs on positive going
transitions of the CLOCK (CK) input. When a high logic
level is applied to the OUTPUT CONTROL (OC) input, all
outputs go to a high impedance state, regard less of what

signals are present at the oth er inputs and the state of the
storage elements.

The 74HC logic family i s speed, function, and pinou t com­patible with the standard 74 LS logic family. All inputs are
protected from damage due to static discharge by internal
diode clamps to V

and ground.

CC

Features

■ Typical propagation delay: 20 ns

■ Wide operating voltage range: 2–6V

■ Low input current: 1 µA maximum

■ Low quiescent current: 80 µA maximum

■ Compatible with bus-oriented systems

■ Output drive capability: 15 LS-TTL loads

Ordering Code:

Order Number Package Number Package Description

MM74HC374WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
MM74HC374SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC374MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC374N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to t he ordering code.

Connection Diagram

Pin Assignments for DIP, SOIC, SOP and TSSOP

Top View

Truth Table

Output Clock Data Output

Control

L ↑ HH
L ↑ LL
LLXQ

HXXZ

H = HIGH Level
L = LOW Level
X = Don't Care
↑ = Transition from LOW-to-HIGH
Z = High Impedance Stat e

= The l evel of the out put before steady state input conditions were

Q

0

established

0

Pin Out

RS
TD1
TA5
TA6

GND

TB0
TB1
TD2

VCC

TD3
TB2
TB3

GND

TB4
TB5
TD4

R/F
TD5
TB6
TC0

GND

TC1
TC2
TC3
TD6

VCC

TC4
TC5

THC63LVDM83R THC63LVDM63R

1
2
3
4
5
6
7
8
9

10

11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28

56

TA4

55

TA3

54

TA2

53

GND

52

TA1

51

TA0

50

TD0

49

LVDS GND

48

TA-

47

TA+

46

TB-

45

TB+

44

LVDS VCC

43

LVDS GND

42

TC-

41

TC+

40

TCLK-

39

TCLK+

38

TD-

37

TD+

36

LVDS GND

35

PLL GND

34

PLL VCC

33

PLL GND

32

/PDWN

31

CLK IN

30

TC6

29

GND

1

TA4 TA3

2

RS

3

TA5

4

TA6

5

GND

6

TB0

7

TB1

8

VCC

9

TB2

10

TB3

11

GND

12

TB4

13

TB5

14

R/F

15

TB6

16

TC0

17

GND

18

TC1

19

TC2

20

TC3

21

VCC

22

TC4

23

TC5

24

GND

48
47

TA2

46

GND

45

TA1

44

TA0

43

N/C

42

LVDS GND

41

TA-

40

TA+

39

TB-

38

TB+

37

LVDS VCC

36

LVDS GND

35

TC-

34

TC+

33

TCLK-

32

TCLK+

31

LVDS GND

30

PLL GND

29

PLL VCC

28

PLL GND

27

/PDWN

26

CLK IN

25

TC6

THC63LVDM83R Pin Description

Pin Name Pin # Type Description

TA+, TA- 47, 48 LVDS OUT
TB+, TB- 45 , 46 LVDS OUT
TC+, TC- 41 , 42 LVDS OUT
TD+, TD- 37, 38 LVDS OUT

TCLK+, TCLK- 39, 40 LVDS OUT LVDS Clock Out.

TA0 ~ TA6 51, 52, 54, 55, 56, 3, 4 IN
TB0 ~ TB6 6, 7, 11, 12, 14, 15, 19 IN
TC0 ~ TC6 20, 22, 23, 24, 27, 28, 30 IN
TD0 ~ TD6 50, 2, 8, 10, 16, 18, 25 IN

/PDWN 32 IN

RS 1 IN

R/F 17 IN

VCC 9, 26 Power

CLKIN 31 IN Clock in.

GND

LVDS VCC 44 Power Power Supply Pins for LVDS Outputs.

LVDS GND 36, 43, 49 Ground Grou nd Pins for LVDS Outputs.

PLL VCC 34 Power Power Supply Pin for PLL circuitry.

PLL GND 33, 35 Ground Ground Pins for PLL circuitr y.

5, 13, 21,

29, 53

Ground Grou nd Pins for TTL inputs and dig ita l circuitry.

LVDS Data Out.

Pixel Data Inputs.

H: Normal operation,
L: Power down (all outputs are Hi-Z)

LVDS swing control.

RS LVDS swing

VCC 350mV

::

GND 200mV

Input Clock Triggering Edge Select.
H: Rising edge, L: Falling edge
Power Supply Pins for TTL inputs and digital

circuitry.

THine

THC63LVDM63R Pin Description

Pin Name Pin # Type Description

TA+, TA- 40, 41 LVDS OUT

LVDS Data Out.TB+, TB- 38 , 39 LVDS OUT

TC+, TC- 34 , 35 LVDS OUT

TCLK+, TCLK- 32, 33 LVDS OUT LVDS Clock Out.

TA0 ~ TA6 44, 45, 47, 48, 1, 3, 4 IN

Pixel Data Inputs.TB0 ~ TB6 6, 7, 9, 10, 12, 13, 15 IN

TC0 ~ TC6 16, 18, 19, 20, 22, 23, 25 IN

/PDWN 27 IN

RS 2 IN

H: Normal operation,
L: Power down (all outputs are Hi-Z)

LVDS swing control.

RS LVDS swing

VCC 350mV

::

GND 200mV

Pin Name Pin # Type Description

R/F 14 IN

VCC 8, 21 Power

CLKIN 26 IN Clock in.

GND 5, 11, 17, 24, 46 Ground Ground Pins for TTL inp uts and digital circuitry.

LVDS VCC 37 Power Power Supply Pins for LVDS Outputs.

LVDS GND 36, 42 Ground Ground Pins for LVDS Outputs.

PLL VCC 29 Power Power Supply Pin for PLL circuitry.

PLL GND 28, 30 Ground Ground Pins for PLL circuitr y.

Input Clock Triggering Edge Select.
H: Rising edge, L: Falling edge
Power Supply Pins for TTL inputs and digital

circuitry.

Absolute Maximum Ratings

Supply Voltage (VCC)
CMOS/TTL Input Voltage

CMOS/TTL Output Voltage
LVDS Driver Output Voltage

1

-0.3V ~ +4.0V

-0.3V ~ (V

-0.3V ~ (V

-0.3V ~ (V

+ 0.3V)

CC

+ 0.3V)

CC

+ 0.3V)

CC

Output Current continuous
Junction Temperature

Storage Temperature Range
Lead Temperature (Soldering, 4sec)
Maximum Power Dissipation @+25

°

C

°

C

+150

°

C

-65 ~ +150

°

C

+260

1.4W

°

C

Electrical Characteristics

CMOS/TTL DC Specifications

VCC = 3.0V ~ 3.6V, Ta = -10 ~ +70

Symbol Parameter Conditions Min. Typ. Max. Units

V

I

V

INC

I

PD

I

RS

IH

IL

High Level Input Voltage 2.0
Low Level Input Voltage GND 0.8 V

≤≤

Input Current
Pull Down Current

RS Pull Down Current

0V V

INVCC

R/F pin, VIH=V
RS pin, VIH=V

CC

CC

V

±

CC

10

100
100

°

C

°

C

V

µ

A

µ

A

µ

A

1. “Absolute Maximum Ratings” are those valued beyond which the safety of the device can not be guaranteed. They
are not meant to imply that the device should be operated at these limits. The tables of “Electrical Characteristics”
specify conditions for device operation.