BASIC TAPE MECHANISM : TN-21ZSC-2003
BASIC CD MECHANISM : DA11T3C
S/M Code No. 09-007-347-4N2
DATA
Page 2
SPECIFICATIONS
Design and specifications are subject to change without
•
notice
.
-2-
Page 3
PROTECTION OF EYES FROM LASER BEAM DURING SERVICING
This set employs laser. Therefore, be sure to follow carefully the
instructions below when servicing.
WARNING!
WHEN SERVICING, DO NOT APPROACH THE LASER EXIT
WITH THE EYE TOO CLOSELY. IN CASE IT IS NECESSARY TO
CONFIRM LASER BEAM EMISSION. BE SURE TO OBSERVE
FROM A DISTANCE OF MORE THAN 30cm FROM THE
SURFACE OF THE OBJECTIVE LENS ON THE OPTICAL
PICK-UP BLOCK.
Caution: Invisible laser radiation when
open and interlocks defeated avoid exposure to beam.
Advarsel:Usynling laserståling ved åbning,
når sikkerhedsafbrydere er ude af funktion.
Undgå udsættelse for stråling.
VAROITUS!
Laiteen Käyttäminen muulla kuin tässä käyttöohjeessa mainitulla tavalla saattaa altistaa käyt-täjän turvallisuusluokan 1 ylittävälle näkymättömälle lasersäteilylle.
VARNING!
Om apparaten används på annat sätt än vad som specificeras i
denna bruksanvising, kan användaren utsättas för osynling
laserstrålning, som överskrider gränsen för laserklass 1.
CAUTION
Use of controls or adjustments or performance of procedures
other than those specified herein may result in hazardous
radiation exposure.
ATTENTION
L'utilisation de commandes, réglages ou procédures autres que
ceux spécifiés peut entraîner une dangereuse exposition aux
radiations.
ADVARSEL!
Usynlig laserståling ved åbning, når sikkerhedsafbrydereer ude
af funktion. Undgå udsættelse for stråling.
This Compact Disc player is classified as a CLASS 1 LASER
product.
The CLASS 1 LASER PRODUCT label is located on the rear
exterior.
CLASS 1
KLASSE 1
LUOKAN 1
KLASS 1
LASER PRODUCT
LASER PRODUKT
LASER LAITE
LASER APPARAT
-3-
Page 4
Precaution to replace Optical block
(SF-P101NR)
Body or clothes electrostatic potential could ruin
laser diode in the optical block. Be sure ground
body and workbench, and use care the clothes
do not touch the diode.
1) After the connection, remove solder shown in
the right figure.
C784 87-012-286-080 CAP, U 0.01-25
C785 87-016-279-080 CAP,E 1-50 BP
C786 87-016-279-080 CAP,E 1-50 BP
C789 87-012-275-080 C-CAP,U 1200P-50 B
C790 87-012-275-080 C-CAP,U 1200P-50 B
CN602 87-A60-059-010 CONN,08P V 9604S-08C
CN604 87-A60-060-010 CONN,07P V 9604S-07C
L601 87-003-098-080 COIL,2.2UH
L603 87-003-098-080 COIL,2.2UH
LCD601 8A-CJB-630-010 LCD,AIW4214-30P1N ACJ-11
X601 87-030-376-080 VIB,CER CSA5.76MG200
VCD C.B
C101 87-010-182-080 C-CAP,S 2200P-50 B
C102 87-016-669-080 C-CAP,S 0.1-25 K B
C103 87-016-669-080 C-CAP,S 0.1-25 K B
C104 87-016-669-080 C-CAP,S 0.1-25 K B
C105 87-010-404-040 CAP,E 4.7-50 SME
C106 87-016-369-080 C-CAP,S 0.033-25 B K
C107 87-010-197-080 CAP, CHIP 0.01 DM
C108 87-010-546-080 CAP, ELECT 0.33-50V
C109 87-010-382-040 CAP,E 22-25 SME
C110 87-010-213-080 C-CAP,S 0.015-50 B
C111 87-010-263-040 CAP,E 100-10
C112 87-010-197-080 CAP, CHIP 0.01 DM
C113 87-016-369-080 C-CAP,S 0.033-25 B K
C114 87-016-369-080 C-CAP,S 0.033-25 B K
C115 87-016-369-080 C-CAP,S 0.033-25 B K
C609 87-010-178-080 CHIP CAP 1000P
C610 87-010-178-080 CHIP CAP 1000P
C611 87-010-178-080 CHIP CAP 1000P
C612 87-010-178-080 CHIP CAP 1000P
C613 87-010-403-040 CAP,E 3.3-50 SME
C614 87-010-403-040 CAP,E 3.3-50 SME
C615 87-010-318-080 C-CAP,S 47P-50 CH
C616 87-010-318-080 C-CAP,S 47P-50 CH
CN101 87-A60-424-010 CONN,16P V TOC-B
CN403 87-A60-079-010 CONN,08P H 9604S-08F
CN405 87-A60-060-010 CONN,07P V 9604S-07C
CN406 87-A60-619-010 CONN,2P V 2MM JMT
CNA102 8A-CJB-623-010 CONN ASSY,6P CD MOTOR
J501 87-009-502-010 JACK,PIN 1P Y EARTH
L101 87-005-196-080 COIL,10UH
• Regarding connectors, they are not stocked as they are not the initial order items.
The connectors are available after they are supplied from connector manufacturers upon the order is received.
These pins are connected to the A+C and B+C pins of the optical pickup, receiving by currents
input.
Bias adjustment pin of the focus error amplifier. (Not connected)
F and EIV amplifier inverted input pins.
I
These pins are connected to the F and E of the optical pickup, receiving by current input.
Gain adjustment pin of the I-V amplifier E. (When not in use of BAL automatic adjustment)
GND connection pin.
Output terminal for tacking-error amplifier. Output E-F signal.
I
BAL adjustment comparator input pin. (Input through LPF from TEO)
I
Input terminal for tracking error.
I
Window-comparator input terminal for detecting ATSC.
I
Input terminal for tracking-zero cross comparator.
I
Capacitor connection pin for the time constant used when there is defect.
Output terminal for DC voltage reduced to half of VCC+VEE.
52
FZC
I
Input terminal for focus-zero cross comparator.
-27-
Page 28
IC DESCRIPTION-3/7 (CXD2540Q)-1/3
Pin No.Pin NameI/ODescription
1
FOK
I
Focus OK input. Used for SENS output and the servo auto sequencer.
10
11
12
13
14
15
16
17
2
3
4
5
6
7
8
9
FSW
MON
MDP
MDS
LOCK
NC
VCOO
VCOI
TEST
PDO
VSS
PWMI
V16M
VCTL
VPCO
VCKI
O
Spindle motor output filter switching output. (Not connected)
O
Spindle motor on/off control output. (Not connected)
O
Spindle motor servo control. (Pin 5 is not connected)
O
High, when sampled value of GFS at 460Hz is high.
O
Low, when sampled value of GFS at 460Hz is low by 8 times successively.
—
Not used.
O
Analog EFM PLL oscillation circuit output. (Not connected)
I
Analog EFM PLL oscillation circuit input. fLOCK=8.6436MHz. (Connected to GND)
I
TEST pin. (Connected to GND)
O
Analog EFM PLL charge pump output.
—
GND.
I
Spindle motor external control input.
O
VCO2 oscillation output for the wide-band EFM PLL.
I
VCO2 control voltage input for the wide-band EFM PLL.
O
Wide-band EFM PLL charge pump output.
I
VCO2 oscillation input for the wide-band EFM PLL.
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
FILO
FILI
PCO
AVSS
CLTV
AVDD
RF
BIAS
ASYI
ASYO
ASYE
NC
PSSL
WDCK
LRCK
VDD
O
Multiplier PLL (slave=digital PLL) filter output.
I
Multiplier PLL filter input.
O
Multiplier PLL charge pump output.
—
Analog GND.
I
Multiplier VCO1 control voltage input.
—
Analog power supply. (5V)
I
EFM signal input.
I
Constant current input of the asymmetry circuit.
I
Asymmetry comparator voltage input.
O
EFM full-swing output.
I
Low: asymmetry circuit off; high: asymmetry circuit on.
—
Not connected.
Audio data output mode switching input. Low: serial output; high: parallel output. (Connected to
I
GND)
O
D/A interface for 48-bit slot. Word clock f=2Fs. (Not connected)
O
D/A interface for 48-bit slot. LR clock f=Fs.
—
Power supply. (5V)
34
35
36
37
DATA
BCK
DATA64
BCK64
DA16 (MSB) output when PSSL=1.
O
48-bit slot serial data (two’s complement, MSB first) when PSSL=0.
O
DA15 output when PSSL=1. 48-bit slot bit clock when PSSL=0.
DA14 output when PSSL=1.
O
64-bit slot serial data (two’s complement, LSB first) when PSSL=0. (Not connected)
O
DA13 output when PSSL=1. 64-bit slot bit clock when PSSL=0. (Not connected)
-28-
Page 29
IC DESCRIPTION-3/7 (CXD2540Q)-2/3
Pin No.Pin NameI/ODescription
38
LRCK64
O
DA12 output when PSSL=1. 64-bit slot LR clock when PSSL=0. (Not connected)
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
GTOP
XVCF
XPCLK
GFS
RFCK
C2PO
XRAOF
MNT3
MNT2
MNT1
MNT0
APTR
APTL
VSS
XTAI
XTAO
O
DA11 output when PSSL=1. GTOP output when PSSL=0. (Not connected)
O
DA10 output when PSSL=1. XUGF output when PSSL=0. (Not connected)
O
DA09 output when PSSL=1. XPLCK output when PSSL=0. (Not connected)
O
DA08 output when PSSL=1. GFS output when PSSL=0.
O
DA07 output when PSSL=1. RFCK output when PSSL=0. (Not connected)
O
DA06 output when PSSL=1. C2PO output when PSSL=0.
O
DA05 output when PSSL=1. XRAOF output when PSSL=0. (Not connected)
O
DA04 output when PSSL=1. MNT3 output when PSSL=0. (Not connected)
O
DA03 output when PSSL=1. MNT2 output when PSSL=0. (Not connected)
O
DA02 output when PSSL=1. MNT1 output when PSSL=0. (Not connected)
O
DA01 output when PSSL=1. MNT0 output when PSSL=0. (Not connected)
Aperture compensation control output.
O
This pin outputs a high signal when the right channel is used. (Not connected)
Aperture compensation control output.
O
This pin outputs a high signal when the left channel is used. (Not connected)
2/3 frequency divider output for Pins 53 and 54. (Not connected)
O
1/4 frequency divider output for Pins 53 and 54. (Not connected)
O
16.9344MHz output. (V16M output in CLV-W and CAV-W modes) (Not connected)
I
Digital-out on/off control. High: on; low: off
O
Digital-out output.
Outputs a high signal when the playback disc has emphasis, and a low signal when there is no
O
emphasis.
I
WFCK (write frame clock) output.
O
Outputs a high signal when either subcode sync S0 or S1 is detected.
O
Sub P to W serial output.
I
SBSO readout clock input.
O
Sub Q 80-bit and PCM peak, level metter and internal status outputs.
I
SQSO readout clock input.
I
High: mute; low: release
—
SENS output to CPU.
I
System reset. Reset when low.
71
72
73
74
75
DATA
XLAT
VDD
CLOK
SEIN
O
Serial data input from CPU.
O
Latch input from CPU. Serial data is latched at the falling edge.
Power supply. (5V)
O
Serial data transfer clock input from CPU.
I
SENS input from SSP.
-29-
Page 30
IC DESCRIPTION-3/7 (CXD2540Q)-3/3
Pin No.Pin NameI/ODescription
76
CNIN
Track jump count signal input.
I
77
78
79
80
Notes)
•The 64-bit slot is an LSB first, two’s complement output, and the 48-bit slot is an MSB first, two’s complement output.
•GTOP is used to monitor the frame sync protection status. (High: sync protection window open.)
•XUGF is the negative pulse for the frame sync obtained from the EFM signal. It is the signal before sync protection.
•XPLCK is the inverse of the EFM PLL clock. The PLL is designed so that the falling edge and the EFM signal transition point
coincide.
•GFS goes high when the frame sync and the insertion protection timing match.
•RFCK is derived from the crystal accuracy, and has a cycle of 136µ.
•C2PO represents the data error status.
•XRAOF is generated when the 32K RAM exceeds the ±28F jitter margin.
DATO
XLTO
CLKO
MIRR
Serial data output to SSP.
O
Serial data latch output to SSP. Latched at the falling edge.
O
Serial data transfer clock output to SSP.
O
Mirror signal input. Used when the number of tracks is 128 or more for the 2N-track jump and
I
M track move of the auto sequencer.
-30-
Page 31
IC DESCRIPTION-4/7 (CL680)-1/3
Pin No.Pin NameI/ODescription
1
NC
—
No connection.
2
3
4
5
6
7-9
10-15
16
17
18
19
20
21
22
23-29
30-36
37
38
VSS
CD BCK
CD DATA
CD LRCK
CD C2PO
NC
MD0-MD5
VSS
MD6
VDD3
MD7
VSS
MD8
VDD3
MD9-MD15
NC
________
MCE
__________
MWE
—
—
I/O
—
I/O
—
I/O
—
I/O
—
I/O
—
—
O
GND.
I
Bit clock input from CD DSP.
I
Data input from CD DSP.
I
LRCK input from CD DSP.
I
C2 pointer input from CD DSP.
No connection.
DRAM/ROM interface. (DATA)
Ground.
DRAM/ROM interface. (DATA)
Power supply 3.3V.
DRAM/ROM interface. (DATA)
Ground.
DRAM/ROM interface. (DATA)
Power supply 3.3V.
DRAM/ROM interface. (DATA)
No connection.
ROM chip enable.
DRAM write enable.
39
40
41
42
43
44-46
47
48
49
50-52
53
54
55
56-58
59
60
61
VSS
________
CAS
VDD3
___________
RASO
___________
RASI
MA10-MA8
VSS
MA7
VDD3
MA6-MA4
VSS
MA3
VDD3
MA2-MA0
PGIO7
______________
RESET
VDD MAX IN
—
O
—
O
O
O
—
O
—
O
—
O
—
O
I/O
—
Ground.
DRAM/ROM interface.
Power supply 3.3V.
DRAM/ROM interface. (Pin 43 is no connection)
DRAM/ROM interface. (Address)
Ground.
DRAM/ROM interface. (Address)
Power supply 3.3V.
DRAM/ROM interface. (Address)
Ground.
DRAM/ROM interface. (Address)
Power supply 3.3V.
DRAM/ROM interface. (Address)
Programmable I/O. (No connection)
I
Reset input.
Power supply - VDDMAX. (5.0V)
62-64
65
66
67
68
NC
AGND DAC
A DAC
COMP OUT
AGND DAC
—
No connection.
—
Analog ground.
—
Analog power supply (DAC) : 3.3V.
O
Composite out.
—
Analog ground.
-31-
Page 32
IC DESCRIPTION-4/7 (CL680)-2/3
Pin No.Pin NameI/ODescription
Video signal “Y” OUT. (No connection)
69
70
71
72
73
74
75
76
77-79
80
81
82
83, 84
85
Y OUT
AVDD DAC
AGND DAC
R REF
V REF
AVDD DAC
C OUT
AGND DAC
CLK SEL0-2
VSS
CLK SEL3
VDD3
CLK SEL4, 5
AGND PLL
O
Analog power supply (DAC) 3.3V.
—
Analog ground.
—
Reference resistor input.
I
Voltage reference input.
I
Analog power supply (DAC) : 3.3V.
—
Video signal “C” out. (No connection)
O
Analog ground.
—
Clock selection input.
I
Ground.
—
Clock selection input.
I
Power supply 3.3V.
—
Clock selection input.
I
Analog ground.
—
86
87
88
89, 90
91
92
93
94
95
96
97
98
99
100
101
102
103
DA XCK
AVDD PLL
DA EMP
PGIO5, O6
PGIO0
PGIO8
______________ ______________
VSYNC/CSYNC
AVDD PLL
VID_DAC_CK
PROC_CK
AUD_XCK
AGND PLL
VSS
NC
______________
HSYNC
VDD3
VCK OUT
—
O
I/O
I/O
I/O
O
—
O
O
O
—
—
—
O
—
O
DA XCK (16.933MHz) input.
I
Analog power supply 3.3V.
DAC-emphasis output.
Programmable I/O. (No connection)
______________ ______________
VSYNC/CSYNC output.
Analog power supply (PLL) 3.3V.
Video DAC clock.
Processor clock. (No connection)
Audio XCK. (No connection)
Analog ground.
Ground.
No connection.
______________
HSYNC output.
Power supply 3.3V.
VCK out.
104
105
106
107
108
109
110
111
112
113
VSS
GCK
VCK IN
GCK OUT
DA LRCK
VDD MAX OUT
DA DATA
DA BCK
HD OUT
HRDY
Ground.
—
Global clock signal input. (42.3MHz) (No connection)
External X’tal and capacitor for internal sync generator, or the external clock are
I
connected to this terminal. (2fsc or 4fsc)
O
Either the external clock input mode or the X’tal generator mode is selected by this selector
I
terminal. L: X’tal generator mode, H: External clock input.
Blank signal (character and the green ORed signal) is output from this terminal. (MODE 0:
5
BLANK
composite sync signal is output at H) When reset (RST terminal = L), the X’tal clock signal is
O
________
output. (It is not output when reset by the reset command)
6
7
OSC IN
OSC OUT
I
External coil and capacitor for the character output dot clock generator are connected
to this terminal.
O
The character signal is output from this terminal. (MOD 0: when H, the external sync signal
identification signal is output from this terminal. This output signal tells whether the external
8
CHARA
O
sync signal is present or not. When external sync signal is present, H is output) When reset (RST
________
terminal = L), the dot clock signal (LC oscillator) is output. (It is not output when reset by the
reset command)
______
9
CS
Enable signal for the serial data input is input to this terminal. The serial data input is enabled at
I
L. Pull-up resistor is built-in. (Hysteresis input)
SCLK
Clock of the serial data input is input to this terminal. Pull-up resistor is built-in. (Hysteresis
I
input)
11
12
13
14
15
16
17
18
19
20
21
22
23
SIN
VDD2
CV OUT
NC
CV IN
VDD1
SYN IN
SEP C
SEP OUT
SEP IN
CTRL2
CTRL3
________
RST
Serial data input terminal. Pull-up resistor is built-in. (Hysteresis input)
I
Power supply for the composite video signal level adjustment. (Analog power supply)
—
Composite video signal output terminal.
O
Connected to GND or not connected.
—
Composite video signal input terminal.
I
Power supply. (+5V digital power supply)
—
Video signal for the internal sync separator circuit is input to this terminal. (When the internal
sync separator circuit is not used, the horizontal sync signal or composite sync signal is input to
I
this terminal)
Internal sync separator circuit bias voltage monitoring terminal.
—
The composite sync output signal of the internal sync separator circuit is output from this
terminal. (H: MOD 1. H: during internal sync mode. L: during external sync mode) (When
O
internal sync separator circuit is not used, the SYN IN input signal is output from this terminal)
The output signal of the SEP OUT terminal is integrated so that the vertical sync signal is input
I
to this terminal. An integrator circuit must be connected between the SEP OUT terminal and this
terminal. When this terminal is not used, it must be connected to VDD1.
When selecting any of the NTSC or PAL or PAL-M or PAL-N system, the pin setting has
priority. When L, the NTSC system is selected after resetting. Selection of either NTSC or PAL
I
or PAL-M or PAL-N system by the command becomes effective. H: PAL-M system.
Controls whether or not to input the VSYNC signal to the SEPIN input. L: to input the VSYNC
I
signal. H: not to input the VSYNC signal.
I
System reset input terminal. Pull-up resistor is built-in. (Hysteresis input)
22 8A-CJB-625-010 CONN ASSY,10P DECK
23 8A-CLC-610-010 CONN ASSY,3P POWER
24 8A-CJB-003-010 PANEL,L
25 8A-CJB-626-010 CONN ASSY,2P CD DOOR
26 8A-CGC-609-010 FF-CABLE,7P 1.25 250MM
27 8A-CGC-608-010 FF-CABLE,16P 1.0 150MM
28 8A-CJB-623-010 CONN ASSY,6P CD MOTOR
30 88-CH6-220-010 CUSHION,CD A
31 M8-ZZK-E90-070 DA11T3C
32 8Z-CDB-169-010 PANEL,CD SANYO
REF. NOPART NO.KANRIDESCRIPTION
33 8A-CJB-206-010 HLDR,CHAS CD R
34 87-036-389-010 SW,PUSH LOCK
35 8A-CJB-205-010 HLDR,CHAS CD L
36 8Z-NF6-210-010 DMPR,150 N
37 8A-CLC-206-010 SPR-T,CD
A 87-067-703-010 TAPPING SCREW, BVT2+3-10
B 87-723-095-410 QT2+3-8 BLK
C 87-253-033-110 SCREW,U+2-4
D 8A-CK4-223-010 S-SCREW,CD
E 87-B10-230-010 BVT2+3-10 W/O SLOT SILVER CR
F 87-067-586-010 TAPPING SCREW, BVT2+4-8
G 87-078-150-010 BVT2+3-6 SIL
H 87-571-032-410 VIT+2-3
NOTE: No.14, 29 and 47 are not used.
NO.
-40-
Page 41
COLOR NAME TABLE
Basic color symbolColorBasic color symbolColorBasic color symbolColor
BBlackCCreamDOrange
GGreenHGrayLBlue
LTTransparent BlueNGoldPPink
RRedSSilverSTTitan Silver
TBrownVVioletWWhite
WTTransparent WhiteYYellowYTTransparent Yellow
LMMetallic BlueLLLight BlueGTTransparent Green
LDDark BlueDTTransparent OrangeGMMetallic Green
1 S1-921-030-4A0 HEAD BASE
2 S1-821-030-070 AZIMUTH SPRING
3 S1-921-030-090 PANEL P SPRING
4 S1-921-260-050 GEAR PLATE SPRING
5 S1-921-265-020 GEAR PLATE ASSY
6 S6-201-011-110 HEAD,RP7442ES-0951
7 S1-921-015-010 CHASSIS ASSY
8 S1-921-030-110 HEAD PANEL
9 S1-921-143-160 BASE ASSY
10 S1-921-141-8A0 M CONTROL SPRING
11 S1-921-260-4A0 SENSING LEVER
12 S1-921-043-100 PINCH ROLLER ARM ASSY
13 S1-921-130-020 EJECT SLIDE LEVER
14 S1-921-141-3A0 P CONTROL SPRING
15 S1-921-140-550 PAUSE LEVER(E)
16 S1-921-140-120 PAUSE LEVER SPRING
17 S1-921-140-110 PAUSE STOPPER
18 S1-921-140-150 BUTTON LEVER SPRING(B)
19 S1-821-011-590 E KICK LEVER
20 S1-921-141-070 BUTTON LEVER SPRING(A)
26 S1-921-140-240 REW BUTTON LEVER
27 S1-921-140-250 FF BUTTON LEVER
28 S1-921-140-260 STOP BUTTON LEVER
29 S1-921-140-610 PAUSE BUTTON LEVER
30 S1-821-100-700 FF GEAR
31 S1-921-050-060 SENSER
32 S1-921-053-100 TAKE UP REEL ASSY
33 S1-829-100-010 PACK SPRING
34 S1-921-050-150 S REEL HUB
35 S1-921-050-220 BACK TENSION SPRING
REF. NOPART NO.KANRIDESCRIPTION
NO.
36 S1-921-140-220 REC BUTTON LEVER
37 S1-921-140-170 P.S.LEVER SPRING
38 S1-921-073-040 RF CLUTCH ASSY
39 S1-921-070-030 RF BELT
40 S1-921-260-020 CAM GEAR
41 S1-921-140-160 E ACTUATOR SPRING
42 S1-921-093-210 FLYWHEEL ASSY
43 S1-921-090-380 MAIN BELT
44 S1-921-120-590 MOTOR PULLEY
45 S6-002-030-220 MOTOR EG530AD-2B
46 S6-209-100-100 E HEAD PH-K380-MS1
47 S1-921-030-050 MG ARM
48 S1-921-140-210 REC BUTTON LEVER SPRING
49 S1-821-100-690 RECORD SAFETY LEVER
50 S1-821-128-9A0 MOTOR BRACKET
51 S1-821-010-500 PLAY BUTTON LEVER SPRING
A S9-P04-200-310 C TAPPING SCREW 2-3
B S1-921-120-020 MOTOR COLLER SCREW
C S9-B10-200-510 P TAPPING BIND SCREW M2-5
D S9-C07-204-510 SCREW,TAPPING(CAMERA)M2-4.5
E S9-P01-200-610 SCREW,M2-6
F S9-B01-200-310 (+)BIND SCREW M2-3
G S9-F08-200-710 AZIMUTH SCREW M2-7
H S1-921-120-030 MB SCREW
I S9-W02-300-100 P WASHER CUT 1.2-3.8-0.3
J S9-W02-500-100 P WASHER CUT 1.45-3.8-0.5
K S9-W01-400-100 P WASHER 2-3.5-0.4
L S9-W01-130-200 P WASHER 2.1-4-0.13
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Page 44
CD MECHANISM EXPLODED VIEW-1/1 (DA11T3C)
1
SW1
A
2
3
4
MOTOR C.B
M2
PIN 3
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Page 45
CD MECHANISM PARTS LIST-1/1 (DA11T3C)
REF. NOPART NO.KANRIDESCRIPTION
1 M8-ZZK-E90-070 DA11T3C
2 S2-121-A28-400 COVER GEAR
3 S2-511-A21-000 GEAR MIDDLE
4 S2-511-A21-100 GEAR,DRIVE
A S1-PN2-03R-OSE SCR PAN PCS 2-3