TAPE MECHANISM PARTS LIST 1/1 .................................................................................................. 49
CD MECHANISM EXPLODED VIEW 1/1 ............................................................................................. 50
CD MECHANISM PARTS LIST 1/1 ...................................................................................................... 50
ACCESSORIES/PACKAGE LIST ......................................................................................................... 51
2
Page 3
SPECIFICATIONS
Design and specifications are subject to change
•
without notice
.
3
Page 4
PROTECTION OF EYES FROM LASER BEAM DURING SERVICING
This set employs laser. Therefore, be sure to follow carefully the
instructions below when servicing.
WARNING!
WHEN SERVICING, DO NOT APPROACH THE LASER EXIT
WITH THE EYE TOO CLOSELY. IN CASE IT IS NECESSARY TO
CONFIRM LASER BEAM EMISSION. BE SURE TO OBSERVE
FROM A DISTANCE OF MORE THAN 30cm FROM THE
SURFACE OF THE OBJECTIVE LENS ON THE OPTICAL
PICK-UP BLOCK.
Caution: Invisible laser radiation when
open and interlocks defeated avoid exposure to beam.
Advarsel:Usynling laserståling ved åbning,
når sikkerhedsafbrydere er ude af funktion.
Undgå udsættelse for stråling.
VAROITUS!
Laiteen Käyttäminen muulla kuin tässä käyttöohjeessa mainitulla tavalla saattaa altistaa käyt-täjän turvallisuusluokan 1 ylittävälle näkymättömälle lasersäteilylle.
VARNING!
Om apparaten används på annat sätt än vad som specificeras i
denna bruksanvising, kan användaren utsättas för osynling
laserstrålning, som överskrider gränsen för laserklass 1.
CAUTION
Use of controls or adjustments or performance of procedures
other than those specified herein may result in hazardous
radiation exposure.
ATTENTION
L'utilisation de commandes, réglages ou procédures autres que
ceux spécifiés peut entraîner une dangereuse exposition aux
radiations.
ADVARSEL!
Usynlig laserståling ved åbning, når sikkerhedsafbrydereer ude
af funktion. Undgå udsættelse for stråling.
This Compact Disc player is classified as a CLASS 1 LASER
product.
The CLASS 1 LASER PRODUCT label is located on the rear
exterior.
CLASS 1
KLASSE 1
LUOKAN 1
KLASS 1
LASER PRODUCT
LASER PRODUKT
LASER LAITE
LASER APPARAT
Precaution to replace Optical block
(KSS-213B)
Body or clothes electrostatic potential could ruin
laser diode in the optical block. Be sure ground
body and workbench, and use care the clothes
do not touch the diode.
1) After the connection, remove solder shown in
the right figure.
C102 87-016-669-080 C-CAP,S 0.1-25 K B
C103 87-016-669-080 C-CAP,S 0.1-25 K B
C104 87-016-669-080 C-CAP,S 0.1-25 K B
C105 87-010-404-040 CAP,E 4.7-50 SME
C106 87-016-369-080 C-CAP,S 0.033-50 B K
C107 87-010-197-080 CAP, CHIP 0.01 DM
C108 87-010-401-040 CAP,E 1-50 SME
C109 87-010-382-040 CAP,E 22-25 SME
C110 87-010-213-080 C-CAP,S 0.015-50 B
C111 87-010-263-040 CAP,E 100-10
C112 87-010-197-080 CAP, CHIP 0.01 DM
C113 87-016-369-080 C-CAP,S 0.033-50 B K
C114 87-016-369-080 C-CAP,S 0.033-50 B K
C115 87-016-369-080 C-CAP,S 0.033-50 B K
C121 87-010-992-080 C-CAP,S 0.047-25 B
C123 87-016-669-080 C-CAP,S 0.1-25 K B
C125 87-010-198-080 CAP, CHIP 0.022
C126 87-016-669-080 C-CAP,S 0.1-25 K B
C127 87-010-555-040 CAP,E 100-10 GAS
C130 87-010-555-040 CAP,E 100-10 GAS
C131 87-010-555-040 CAP,E 100-10 GAS
C132 87-010-178-080 CHIP CAP 1000P
C133 87-010-555-040 CAP,E 100-10 GAS
C136 87-010-196-080 CHIP CAPACITOR,0.1-25
C290 87-010-178-080 CHIP CAP 1000P
C291 87-010-178-080 CHIP CAP 1000P
C292 87-010-178-080 CHIP CAP 1000P
C293 87-010-403-040 CAP,E 3.3-50 SME
C294 87-010-403-040 CAP,E 3.3-50 SME
• Regarding connectors, they are not stocked as they are not the initial order items.
The connectors are available after they are supplied from connector manufacturers upon the order is received.
CHIP RESISTOR PART CODE
Chip Resistor Part Coding
88
A
Resistor Code
Chip resistor
WattageTypeTolerance
1/16W10055%CJ
1/16W
1/10W
1/8W
1608
2125
3216
5%
5%
5%
TRANSISTOR ILLUSTRATION
Symbol
Figure
Value of resistor
CJ
CJ
CJ
87
Form
L
W
Dimensions (mm)
LW t
1.00.50.35104
t
1.60.80.45
21.25 0.45
1.6
0.55
3.2
Resistor Code
108
118
128
: A
: A
Page 8
WIRING-1 (MAIN)
SPEAKER
R
L
AUX
L
AM
LOOP
ANTENNA
FM
75‰
7
J401
F401
R429
L402
C511
D501
C510
L501
J501
R
C499
CN701
H
654321
FH1
C404
R7
C512
D2
C501
C432
D420
D404
C429
C506
C502
C509
C402
C401
D401
CN401
C434
D406
C431
D403
C428
R521
C505
L982
MAIN C. B(INSERTED PARTS)
R4R5
C1
D1
C416
C495
C418
VCC8V
F
R520
R519
L771
R718
[C]
C781
G
C417
D3022
H
11
12
C424
C423
R422
R420
D415
R719
C415
R421
D
C777
Q410
D412
D413
C774
16
15
D770
10
11
D402
FH2
D405
C430
C507
C508
C504
IC501
C950
R962
R415
C433
C405
C6
C503
L832
FFE801
Q404
R414
C411
12V
C2
C7
Q403
C427
15
C408 R405 R408
R409
C406 C407
R405
Q401
L_CH
1
C8
20
C771
C769
CF802
R830
C820
CF801
R402
R783
R413
C409
Q402
R403
C9
C5
C4
C795
30
1
SFR772
C496
C3
C403
C794
C414
R_CH
C425
C767
R410
C412
C791
L773
R407
TAPE-R
REC-R
D
IC741
C413
1
C419
R428
Q409
C437
Q408
C439
REC-L
C732
C785C786
A
C779
R775
D771
IC720
L403
C410
C438
Q411
TAPE-L
1
22
C702
C420
C422
C440
D416
P-CONT
TU-L
C775
C421
R440
TU-R
L770
X772
Q406
R419
R418
R425
R424
C778
B
R423
D410
Q405
B
D302
C728
R417
D3021
D409
D301
Q407
C711
D721
C325
D414
8
R340
1
Q711
D411
C318
Q304
R61
D306
C701
C436
C435
R312
CN2
C963
C11
SW301
C10
C320
Q302
C304
R325
R318
R317
C319
C321
R325
R313
Q1
C302
D305
R328
R327
R324
C318
R323
C317
D304
R314
R329
R310
C306
C309
R315
R311
R309
CN601
R427
R303
C305
T301
C307
C312
R306
C315
C314
R322
PH1
D303
Q303
R428
R301
R302
R319
R320
J403
IC2
R307
C310
C313
C322
J403
PHONES
8
C301
C308
R305
1
C323
R321
C324
CON501
TO/FROM FRONT C.B
A
A
B
B
C
C
R308
D
D
E
E
F
F
G
G
1
MAIN C. B(CHIP PARTS)
C398
2
R714
R3
R713
C712
R711
R715
3
R798
C721
C703
C722
R707
R1
R773
R743
C727
C704
R781
R779
C756
R776 R774
R729
R726
R724
R728
R720
R708
R2
R712
C713
R705
456
C426
R404
C498
R518
R945
R821
C812
R523
C497
R525
R820
C829
R529
R401
R524
R15
R14
R540
R541
R822
R782
R780
R727
R722
C714
C776
C715
C798
R792
C723
R706
R797
R787
R761
R12
C797
R765
C790
C763
R772
C789
R791
C793
C766
R790
C725
C762
R771
C768
R793
C764
R788
C795
C780
C722
C799
C784
C756
R795
C757
R824
R806
C823
C738
R764
C770
R766
R832
R507
R594
R505
R763
C758
Q805
R827
R511
R508
R840
R509
R784
C822
C821
R506
R825
R823
R502
R510
R964
C955
R739
R503
C960
Q806
C814
C828
R830
7
PT 1
AC VOLTAGE
220 - 240V 110 - 120V
SW C. B
S451
H
H
AC
C. B
8
7
I
J
6
I
5
4
3
2
1
J
AZIMUTH
ADJ
M
M1
TAPE SPEED
ADJ
MA2
(L CH)
MA1
(R CH)
S1
PLAY
SW
S2
MOTOR
SW
M1
DECK
MOTOR
MOTOR C. B
TO / FROM
VCD C.B CN102
109
Page 9
SCHEMATIC DIAGRAM-1 (MAIN)
S301
REC
PB
T218
SW
1211
Page 10
WIRING-2 (VCD/FRONT)
1
234567
8
9
10
111213
14
A
FRONT C. B
(COMPONENT SIDE)
B
VCD C. B
C
D
R385
R394
R391
Q312
E
F
C369
C368
R386
R390
C386
C382
C367C371
R392
R367
G
H
I
Q311
C381
C384
R393
C387
R359
C349
C348
C350
C351
R360
R380
R396
R397
R384
R383
L318
(COMPONENT SIDE)
R379
C363
C365
R375
R374
C331
C388
T3
T4
T5
T1
C358C359
C372
JR211
JR212
R282
T2
C282
Q211
C284
C339
C287
C286
R284
C281
D211
R350
F–
F+
R139
T–T+
C137
Q212
C288
R287
R285
C285
R281
C289
R286
R288
R201
R202
R223
R226
C213
R200
C152
R138 R137
C136
R171
R140
TA1
D201
FE–0
R141
TA0
C291
C290
C292
Q103
R1
R2
R145
C134
R144
R169
R143
C138
C135
C210
R150
R156
C154
C159
Q201
C142
DSP
R146
R142
Q202
C214
R227
R291
C295
Q213
C296
R292
R168
C162
R170
R159
C160
R164
R165
SL+
SL–
UCON
C141
TST0
C309
TST1
IC303
2
TST3
TST2
R148
C132
C311
1
R136
D101
R135
R134
R133
R132
R131
R130
R129
IC302
2
R301
C307
R536
R535
C514C513
R548
100
R545R546
C54
R550
1
C510
R500
R554
R505
R508
R507
R506
R551
R515
D502
D501
D511
R532
R533
R534
Q502
R560
R570
D570
C508
C512
C516
R549C515
RGND
R542
R100
C112
VC
D301
Q303Q302
SL-0
JR104
C120
Q102
TE0
R107
SSP
R110
FE0
R523
R524
R518
R522
R525
C517
R557
R540
R530
R531
R538
R539
D509
R547
D500
R541
1
T6
IC501
81
R543
80
C503
30
R544
R537
43
31
50
51
1
LCD501
J
1413
Page 11
1
234567
8
9
10
111213
14
A
TO/FROM MAIN C. B CN601
FRONT C. B
(CONDUCTOR SIDE)
B
S101
C306
JR102
C139
C111
R116
R117
R118
C114
R122
(OPEN / CLOSE)
C320
1
R302
IC301
4
C302
R303
C312
L301
C301
R113
R114
R112
C110
R109
26
27
39
C105
C127
CN103
8
5
C303
R304
14
13
1
5240
C130
R125
C109
C108
C104
R104
C102
C125
1
2
C304
C305
IC101
C121
JR103
R126
R111
C143
R108
C117
R149
R106
C107
C106
C116
R105
R103
JR101
C126
C123
L302
R101
C103
R102
C101
J16 J5 J6 J7 J9J10J1J4J15J2J3J8
J11J12J13J14
S509
S503
REPEAT
S513
S511
Q501
S510
S512
VOLUMEPOP
S504
SET
L501
D509
C55
D500
C511
D502
D501
D511
S501
ROCK
S508
S504
JAZZ
Q570
D570
S503
C56
X501
CON501
IC502
X502
C501
L500L502
1
3
CN501
S514
AUXBAND
S507
S515
VCD C. B
(CONDUCTOR SIDE)
C
J301
VIDEO
OUT
C364
C352
S201
NTSC
AUTO
PAL
44
IC314
1
J301
C370
13
IC317
24
C379
C366
L316
L314
1
C360
32
IC315
1
L313
C361
32
33
12
1
L317
23
22
D
E
F
G
C362
R378
R373
R351
R377
R352
R372
IC311
L315
C332
R376
C357
C390
C356
C376
17
16
R294
R296
97128
64
C333
96
65
C374
R387
IC316
C283
R295
R293
R398
R363
R362
R361
R353
R382
C353
C341
1
R283
12
C342
R365
R366
R364
R381
C355
R357
C336
R388R267
C334
C343
C344
24
X201
C293
13
IC211
C294
C338
L312
R358
C354
R266
R368
IC313
C335
R371
114
C340
R370
R152
R151
R153
C157
R154
R155
C155
C153
C211
X302
L201
L151
C151
1
C156
24
R160
80
25
R158
C161
1
IC201
16
17
R221
R222
64
C158
1
R157
R207
65
40
R147
64
41
C308
R215
49
48
33
32
IC151
R205
R204
R210
R205
C131
1
16
C310
IC203
R213
R211
R203
R224
C201
Q101
L101
CN101
R121
R123
R124
C119
C133
C118
Q301
X202
C206
R214
R212
C207
C208
C209
C113
C115
H
IC102
CN102
6
1528
C140
I
TO/FROM
CD MOTOR C.B
J
TO/FROM
PICK UP ASSY
LED C. B
CN502
D553
R561R564R562R565R563R567
D552
D551
D550
D549
D548
D547
D546
D545
1615
Page 12
SCHEMATIC DIAGRAM-2 (VCD 1/2)
SW
SWITCHING REGULATOR
AC/DC CONVERTER
1817
Page 13
SCHEMATIC DIAGRAM-3 (VCD 2/2)
VCK OSC
DELAY
SW
OR GATE
NOISE SHAPER
D/A CONVERTER
MUTE
1/2 DIVIDE
2019
Page 14
SCHEMATIC DIAGRAM-4 (FRONT)
D545-549
SLR,342-MG3F
TO/FROM VCD C.B
2221
Page 15
VOLTAGE CHART
23
Page 16
242526
Page 17
Page 18
IC DESCRIPTION
IC, CXA1992AR
Pin No.Pin NameI/ODescription
1
2
3
FEO
FEI
FDFCT
Output terminal for focus error amplifier. Internally connected to window comparator
O
input for bias condition.
Input terminal for focus error.
I
Capacitor connection terminal for time constant used when there is defect.
I
10
11
12
13
14
15
16
4
5
6
7
8
9
FGD
FLB
FE_O
FEM
SRCH
TGU
TG2
FSET
TA_M
TA_O
SL_P
SL_M
SL_O
This pin is connected to GND via capacitor when high frequency gain of the focus
I
servo is attenuated.
This is a pin where the time constant is externally connected to raise the low frequency
I
gain of the focus servo.
Focus drive output.
O
Focus amplifier inverted input pin.
I
This is a pin where the time constant is externally connected to generate the focus
I
search waveform.
This is a pin where the selection time constant is externally connected to set the
I
tracking servo the high frequency gain.
This is a pin where the selection time constant is externally connected to set the
I
tracking high frequency gain.
Pin for setting peak of the phase compensator of the focus tracking.
I
Tracking amplifier inverted input pin.
I
Tracking drive output.
O
Sled amplifier non-inverted input pin.
I
Sled amplifier inverted input pin.
I
Sled drive output.
O
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
ISET
Vcc
LOCK
CLK
XLT
DATA
XRST
C_OUT
SENS1
SENS2
FOK
CC2
CC1
CB
CP
The current which determines height of the focus search, track jump and sled kick is
I
input with external resistance connected.
Power supply.
Clock input for serial data transfer from CPU. (No pull-up resistance)
I
Latch input from CPU. (No pull-up resistance)
I
Serial data input from CPU. (No pull-up resistance)
I
Reset system at “L” setting. (No pull-up resistance)
I
Signal output for track number counting.
O
FZC, DFCT1, TZC, BALH, TGH, FOH, or ATSC is output depending on the
O
command from CPU.
DFCT2, MIRR, BALL, TGL or FOL is output depending on the command from CPU.
O
Output terminal for focus OK comparator.
O
Input pin where the DEFECT bottom hold output is capacitance coupled.
I
DEFECT bottom-hold output terminal. Internally connected to interruption comparator
O
input.
Connection terminal for DEFECT bottom-hold capacitor.
I
Connection terminal for MIRR hold-capacitor.
I
Anti-reverse input terminal for MIRR comparator.
Page 19
Pin No.Pin NameI/ODescription
32
33
34
RF_I
RF_O
RF_M
I
Input terminal by capacity combination of RF summing amplifier.
O
Output terminal of RF summing amplifier. Checkpoint of Eye pattern.
Anti-reverse input terminal for RF summing amplifier.
The gain of RF amplifier is decided by the connection resistance between RF_M and
I
RFO terminals.
35
36
37
38, 39
40
41, 42
43
44
45
46
47
48
49
50
RFTC
LD
PD
PD1, PD2
FEBIAS
F, E
EI
VEE
TEO
LPFI
TEI
ATSC
TZC
TDFCT
O
I/O
—
—
O
This is a pin where the selection time constant is externally connected to control the
These pins are connected to the A+C and B+C pins of the optical pickup, receiving by
currents input.
Bias adjustment pin of the focus error amplifier.
F and EIV amplifier inverted input pins.
I
These pins are connected to the F and E of the optical pickup, receiving by current
input.
Gain adjustment pin of the I-V amplifier E. (When not in use of BAL automatic
adjustment)
GND connection pin.
Output terminal for tacking-error amplifier. Output E-F signal.
I
BAL adjustment comparator input pin. (Input through LPF from TEO)
I
Input terminal for tracking error.
I
Window-comparator input terminal for detecting ATSC.
I
Input terminal for tracking-zero cross comparator.
I
Capacitor connection pin for the time constant used when there is defect.
51
52
VC
FZC
O
Output terminal for DC voltage reduced to half of VCC+VEE.
I
Input terminal for focus-zero cross comparator.
27
Page 20
IC, CXD2540Q
Pin No.Pin NameI/ODescription
1
2
3
FOK
FSW
MON
I
Focus OK input. Used for SENS output and the servo auto sequencer.
O
Spindle motor output filter switching output.
O
Spindle motor on/off control output.
10
11
12
13
14
15
16
17
18
19
20
21
22
4
5
6
7
8
9
MDP
MDS
LOCK
NC
VCOO
VCOI
TEST
PDO
VSS
PWMI
V16M
VCTL
VPCO
VCKI
FILO
FILI
PCO
AVSS
CLTV
O
Spindle motor servo control.
O
High, when sampled value of GFS at 460Hz is high.
O
Low, when sampled value of GFS at 460Hz is low by 8 times successively.
O
Analog EFM PLL oscillation circuit output.
I
Analog EFM PLL oscillation circuit input. fLOCK=8.6436MHz.
I
TEST pin.
O
Analog EFM PLL charge pump output.
GND.
I
Spindle motor external control input.
O
VCO2 oscillation output for the wide-band EFM PLL.
I
VCO2 control voltage input for the wide-band EFM PLL.
O
Wide-band EFM PLL charge pump output.
I
VCO2 oscillation input for the wide-band EFM PLL.
O
Multiplier PLL (slave=digital PLL) filter output.
I
Multiplier PLL filter input.
O
Multiplier PLL charge pump output.
Analog GND.
I
Multiplier VCO1 control voltage input.
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
AVDD
RF
BIAS
ASYI
ASYO
ASYE
NC
PSSL
WDCK
LRCK
VDD
DA16
DA15
DA14
DA13
DA12
Analog power supply (5V).
I
EFM signal input.
I
Constant current input of the asymmetry circuit.
I
Asymmetry comparator voltage input.
O
EFM full-swing output.
I
Low: asymmetry circuit off; high: asymmetry circuit on.
I
Audio data output mode switching input. Low: serial output; high: parallel output.
O
D/A interface for 48-bit slot. Word clock f=2Fs.
O
D/A interface for 48-bit slot. LR clock f=Fs.
Power supply (5V).
DA16 (MSB) output when PSSL=1.
O
48-bit slot serial data (two’s complement, MSB first) when PSSL=0.
O
DA15 output when PSSL=1. 48-bit slot bit clock when PSSL=0.
DA14 output when PSSL=1.
O
64-bit slot serial data (two’s complement, LSB first) when PSSL=0.
O
DA13 output when PSSL=1. 64-bit slot bit clock when PSSL=0.
O
DA12 output when PSSL=1. 64-bit slot LR clock when PSSL=0.
28
Page 21
Pin No.Pin NameI/ODescription
39
40
41
DA11
DA10
DA09
O
DA11 output when PSSL=1. GTOP output when PSSL=0.
O
DA10 output when PSSL=1. XUGF output when PSSL=0.
O
DA09 output when PSSL=1. XPLCK output when PSSL=0.
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
DA08
DA07
DA06
DA05
DA04
DA03
DA02
DA01
APTR
APTL
VSS
XTAI
XTAO
XTSL
FSTT
FSOF
C16M
MD2
DOUT
O
DA08 output when PSSL=1. GFS output when PSSL=0.
O
DA07 output when PSSL=1. RFCK output when PSSL=0.
O
DA06 output when PSSL=1. C2PO output when PSSL=0.
O
DA05 output when PSSL=1. XRAOF output when PSSL=0.
O
DA04 output when PSSL=1. MNT3 output when PSSL=0.
O
DA03 output when PSSL=1. MNT2 output when PSSL=0.
O
DA02 output when PSSL=1. MNT1 output when PSSL=0.
O
DA01 output when PSSL=1. MNT0 output when PSSL=0.
Aperture compensation control output.
O
This pin outputs a high signal when the right channel is used.
Aperture compensation control output.
O
This pin outputs a high signal when the left channel is used.
GND.
I
Crystal oscillation circuit input.
O
Crystal oscillation circuit output.
I
Crystal selector input.
O
2/3 frequency divider output for Pins 53 and 54.
O
1/4 frequency divider output for Pins 53 and 54.
O
16.9344MHz output. (V16M output in CLV-W and CAV-W modes)
I
Digital-out on/off control. High: on; low: off
O
Digital-out output.
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
EMPH
WFCK
SCOR
SBSO
EXCK
SQSO
SQCK
MUTE
SENS
XRST
DATA
XLAT
VDD
CLOK
SEIN
CNIN
—
Outputs a high signal when the playback disc has emphasis, and a low signal when
O
there is no emphasis.
I
WFCK (write frame clock) output.
O
Outputs a high signal when either subcode sync S0 or S1 is detected.
O
Sub P to W serial output.
I
SBSO readout clock input.
O
Sub Q 80-bit and PCM peak, level metter and internal status outputs.
I
SQSO readout clock input.
I
High: mute; low: release
SENS output to CPU.
I
System reset. Reset when low.
O
Serial data input from CPU.
O
Latch input from CPU. Serial data is latched at the falling edge.
Power supply (5V).
O
Serial data transfer clock input from CPU.
I
SENS input from SSP.
I
Track jump count signal input.
29
Page 22
Pin No.Pin NameI/ODescription
77
78
79
DATO
XLTO
CLKO
Serial data output to SSP.
O
Serial data latch output to SSP. Latched at the falling edge.
O
Serial data transfer clock output to SSP.
O
80
Notes)
•The 64-bit slot is an LSB first, two’s complement output, and the 48-bit slot is an MSB first, two’s complement output.
•GTOP is used to monitor the frame sync protection status. (High: sync protection window open.)
•XUGF is the negative pulse for the frame sync obtained from the EFM signal. It is the signal before sync protection.
•XPLCK is the inverse of the EFM PLL clock. The PLL is designed so that the falling edge and the EFM signal transition point
coincide.
•GFS goes high when the frame sync and the insertion protection timing match.
•RFCK is derived from the crystal accuracy, and has a cycle of 136µ.
•C2PO represents the data error status.
•XRAOF is generated when the 32K RAM exceeds the ±28F jitter margin.
MIRR
Mirror signal input. Used when the number of tracks is 128 or more for the 2N-track
I
jump and M track move of the auto sequencer.
30
Page 23
IC, CL680-D1
Pin No.Pin NameI/ODescription
1
NC
—
No connection.
2
3
4
5
6
7-9
10-15
16
17
18
19
20
21
22
23-29
30-36
37
38
VSS
CD BCK
CD DATA
CD LRCK
CD C2PO
NC
MD0-MD5
VSS
MD6
VDD3
MD7
VSS
MD8
VDD3
MD9-MD15
NC
________
MCE
__________
MWE
—
—
I/O
—
I/O
—
I/O
—
I/O
—
I/O
—
—
O
GND.
I
Bit clock input from CD DSP.
I
Data input from CD DSP.
I
LRCK input from CD DSP.
I
C2 pointer input from CD DSP.
No connection.
DRAM/ROM interface. (DATA)
Ground.
DRAM/ROM interface. (DATA)
Power supply 3.3V.
DRAM/ROM interface. (DATA)
Ground.
DRAM/ROM interface. (DATA)
Power supply 3.3V.
DRAM/ROM interface. (DATA)
No connection.
ROM chip enable.
DRAM write enable.
39
40
41
42
43
44-46
47
48
49
50-52
53
54
55
56-58
59
60
61
VSS
________
CAS
VDD3
___________
RASO
___________
RASI
MA10-MA8
VSS
MA7
VDD3
MA6-MA4
VSS
MA3
VDD3
MA2-MA0
PGIO7
______________
RESET
VDD MAX IN
—
O
—
O
O
O
—
O
—
O
—
O
—
O
I/O
—
Ground.
DRAM/ROM interface.
Power supply 3.3V.
DRAM/ROM interface.
DRAM/ROM interface. (Address)
Ground.
DRAM/ROM interface. (Address)
Power supply 3.3V.
DRAM/ROM interface. (Address)
Ground.
DRAM/ROM interface. (Address)
Power supply 3.3V.
DRAM/ROM interface. (Address)
Programmable I/O.
I
Reset input.
Power supply - VDDMAX. (5.0V)
62-64
65
66
67
68
NC
AGND DAC
A DAC
COMP OUT
AGND DAC
—
—
—
—
No connection.
Analog ground.
Analog power supply (DAC) : 3.3V.
O
Composite out.
Analog ground.
31
Page 24
Pin No.Pin NameI/ODescription
Video signal “Y” OUT.
69
Y OUT
O
70
71
72
73
74
75
76
77-79
80
81
82
83, 84
85
86
87
88
89, 90
AVDD DAC
AGND DAC
R REF
V REF
AVDD DAC
C OUT
AGND DAC
CLK SEL0-2
VSS
CLK SEL3
VDD3
CLK SEL4, 5
AGND PLL
DA XCK
AVDD PLL
DA EMP
PGIO5, O6
—
—
—
O
—
—
—
—
—
O
I/O
Analog power supply (DAC) 3.3V.
Analog ground.
Reference resistor input.
I
Voltage reference input.
I
Analog power supply (DAC) : 3.3V.
Video signal “C” out.
Analog ground.
Clock selection input.
I
Ground.
Clock selection input.
I
Power supply 3.3V.
Clock selection input.
I
Analog ground.
DA XCK (16.933MHz) input.
I
Analog power supply 3.3V.
DAC-emphasis output.
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
PGIO0
PGIO8
______________ ______________
VSYNC/CSYNC
AVDD PLL
VID_DAC_CK
PROC_CK
AUD_XCK
AGND PLL
VSS
NC
______________
HSYNC
VDD3
VCK OUT
VSS
GCK
VCK
GCK OUT
I/O
I/O
O
—
O
O
O
—
—
—
O
—
O
—
O
Programmable I/O.
______________ ______________
VSYNC/CSYNC output.
Analog power supply (PLL) 3.3V.
Video DAC clock.
Processor clock.
Audio XCK.
Analog ground.
Ground.
No connection.
______________
HSYNC output.
Power supply 3.3V.
VCK out.
Ground.
Global clock signal input. (42.3MHz)
I
Video clock signal input. (27.0MHz)
I
Global clock signal output. (27.0MHz)
108
109
110
111
112
113
DA LRCK
VDD MAX OUT
DA DATA
DA BCK
HD OUT
HRDY
O
—
O
O
O
O
DAC-LRCK output.
Power supply (VDD MAX) : 5.0V.
DAC-PCM data output.
DAC-BIT clock output.
Micon interface. (Data out)
Micon interface. (Host ready)
32
Page 25
Pin No.Pin NameI/ODescription
__________
114
HINT
Micon interface. (Host interrupt)
O
115
116
117
118
119
120
121
122
123
124
125
126-128
CDG SCK
VSS
HCK
VDD3
HD IN
VDD3
HSEL
CDG DATA
CDG VFSY
CDG SOSI
DSP-XCK
NC
—
—
—
—
CD-G serial clock input.
I
Ground.
Micon interface. (Host clock)
I
Power supply 3.3V.
Micon interface. (Host data in)
I
Power supply 3.3V.
Micon interface. (Host select in)
I
CD-G data input.
I
CD-G VFSY input.
I
CD-G SOSI input.
I
DSP-XCK output.
O
No connection.
33
Page 26
IC, LC867248A-5H31
Pin No.Pin NameI/ODescription
1
2
3
O-SCONTM
O-SCONTL
O-TUDI
O
M62439SP control. open drain output.
O
O
Tuner control. CMOS output.
4
5
6
7
8
9
10
11
12
13, 14
15
16, 17
18
19
20
21
22
23
24
I-TUDO
O-TUCL
O-COIN
I-SQOUT
___________
O-CQCK
O-RWC
_______________
O-CLKSFT
I-TMBASE
____________
I-RESET
NC
VSS1
CF1, CF2
VDD1
I-KEY0
I-KEY1
I-RDSIG
I-WRQ
I-DRF
I-DOOR
O
O
O
O
O
I/O
—
I/O
—
I
Tuner control.
Tuner control. CMOS output.
CD control. open drain output.
I
CD control.
CD control. open drain output.
Clock shift output. “L” during shift. open drain output.
I
8 Hz time base input.
I
Reset input.
Not used.
GND.
Main clock input/output 5.76 MHz.
+5V.
I
KEY0 A/D input.
I
KEY1 A/D input.
I
RDS signal level input. (A/D input)
I
CD control.
I
I
CD door SW detection SW input. “L” at CLOSE.
25
26
27
28
29
30
31
32
33
34
35
36-38
39-55
56
57
58-79
80
81
82
I-PUIN
I-SWTAPE
________________
I-STEREO
I-RDCL
________
I-REM
___________
I-HOLD
I-RDDT
I-TPREC
I-TPPLAY
O-PL
O-MOTOR
NC
S9-S25
VDD2
VSS2
S26-S47
I-CLKDSP
I-AS
__________
I-STOP
O
O
O
O
—
—
O
I
CD pick-up detection SW input. “L” at ON.
I
Tape detection SW input. (A/D input)
I
Monaural/stereo indication selector input. “L” at stereo.
I
RDS clock input.
I
Remote control input. (fall-down edge interrupt input)
I
Hold mode detection. “L” at hold mode.
I
RDS data input.
I
Tape REC detection input. “H” at REC.
I
Tape PLAY detection input. “H” at PLAY.
Mechanism deck plunger solenoid ON/OFF output. “H” at ON. CMOS output .
Mechanism deck motor ON/OFF output. “H” at ON. CMOS output.
Not used.
LCD SEG terminal Initial setting output. (S10 to S16)
+5V.
GND.
LCD SEG terminal .
REC mute output. “H” during mute. Open drain output.
O
REC/PB select output. “H” during PB. Open drain output.
O
Mute output. “H” during mute. Open drain output.
O
Power control output. “H” at ON. CMOS output.
O
REC bias ON/OFF output. “H” at ON. Open drain output.
O
Not used.
35
Page 28
IC, SM5878AN
Pin No.Pin NameI/ODescription
1
2
3
MUTE
DEEM
CKO
MODE = H: Soft mute ON/OFF terminal. (Mute at H).
I
MODE = L: Attenuator level DOWN/UP terminal. (DOWN at H).
I
De-emphasis ON/OFF terminal. (De-emphasis ON at H).
O
Oscillator clock output. (16.9344 MHz).
10
11
12
13
14
15
16
17
18
19
20
21
22
4
5
6
7
8
9
DVSS
BCKI
DI
DVDD
LRCI
TSTN
TO1
AVDDL
LO
AVSS
RO
AVDDR
MUTEO
XVDD
XTI
XTO
XVSS
DS
RSTN
—
—
O
—
O
—
O
—
O
—
O
—
Digital VSS terminal.
I
Bit clock input terminal.
I
Serial data input terminal.
Digital VDD terminal.
I
Sample rate clock (fs) input terminal. (H = L ch/L = R ch).
I
Test input. (“H” or open during normal operation)
Test output 1. (Normally low level output).
Analog VDD terminal. (For L ch).
Left channel analog output terminal.
Analog VSS terminal.
Right channel analog output terminal.
Analog VDD terminal. (For R ch).
Infinity zero detection output.
X’tal system VDD terminal.
I
X’tal oscillator terminal. (Or external clock input terminal of 16.9344 MHz).
X’tal oscillator terminal.
X’tal system VSS terminal.
I
Double-speed/normal playback selection. (Double-speed at H).
I
Reset terminal. (Reset at L).
23
24
MODE
ATCK
I
Soft mute/Attenuator mode selection. (Soft mute at H).
I
Attenuator level setup clock (Ignored when MODE = H).
External X’tal and capacitor for internal sync generator, or the external clock are
connected to this terminal. (2fsc or 4fsc).
O
10
11
12
4
CTRL1
Either the external clock input mode or the X’tal generator mode is selected by this
I
selector terminal. L: X’tal generator mode, H: External clock input.
Blank signal (character and the green ORed signal) is output from this terminal.
5
BLANK
(MODE 0: composite sync signal is output at H.) When reset (RST terminal = L), the
O
________
X’tal clock signal is output. (It is not output when reset by the reset command).
6
7
OSC IN
OSC OUT
I
External coil and capacitor for the character output dot clock generator are connected
to this terminal.
O
The character signal is output from this terminal. (MOD 0: when H, the external sync
signal identification signal is output from this terminal. This output signal tells whether
8
CHARA
the external sync signal is present or not. When external sync signal is present, H is
O
________
output.) When reset (RST terminal = L), the dot clock signal (LC oscillator) is output.
(It is not output when reset by the reset command).
______
9
CS
Enable signal for the serial data input is input to this terminal. The serial data input is
I
enabled at L. Pull-up resistor is built-in. (Hysteresis input).
SCLK
Clock of the serial data input is input to this terminal. Pull-up resistor is built-in.
I
(Hysteresis input).
SIN
VDD2
—
Serial data input terminal. Pull-up resistor is built-in. (Hysteresis input).
I
Power supply for the composite video signal level adjustment. (Analog power supply).
13
14
15
16
17
18
19
20
21
CV OUT
NC
CV IN
VDD1
SYN IN
SEP C
SEP OUT
SEP IN
CTRL2
—
—
—
Composite video signal output terminal.
O
Connected to GND or not connected.
Composite video signal input terminal.
I
Power supply (+5V digital power supply).
Video signal for the internal sync separator circuit is input to this terminal. (When the
internal sync separator circuit is not used, the horizontal sync signal or composite sync
I
signal is input to this terminal).
Internal sync separator circuit bias voltage monitoring terminal.
The composite sync output signal of the internal sync separator circuit is output from
this terminal. (H: MOD 1. H: during internal sync mode. L: during external sync
O
mode.) (When internal sync separator circuit is not used, the SYN IN input signal is
output from this terminal).
The output signal of the SEP OUT terminal is integrated so that the vertical sync signal
is input to this terminal. An integrator circuit must be connected between the SEP
I
OUT terminal and this terminal. When this terminal is not used, it must be connected
to VDD1.
When selecting any of the NTSC or PAL or PAL-M or PAL-N system, the pin setting
has priority. When L, the NTSC system is selected after resetting. Selection of either
I
NTSC or PAL or PAL-M or PAL-N system by the command becomes effective. H:
PAL-M system.
37
Page 30
Pin No.Pin NameI/ODescription
______________
22
CTRL3
Controls whether or not to input the VSYNC signal to the SEPIN input. L: to input the
I
____________________________
VSYNC signal. H: not to input the VSYNC signal.
23
________
RST
I
System reset input terminal. Pull-up resistor is built-in. (Hysteresis input).
24
VDD1
—
Power supply. (+5V digital power supply).
38
Page 31
IC BLOCK DIAGRAM
IC, BA5915FP
IC, M62439SP
IC, SN74LV74APW
6.65K
6.65K
CH1
MUTE
6.65K
6.65K
IC, LA1837NL
T.S.D: Thermal shut-down
Resistors are in units of Ω.
IC, LC72131
4039
Page 32
ELECTRICAL ADJUSTMENT
4241
Page 33
PRACTICAL SERVICE FIGURE
LCD DISPLAY
< TUNER SECTION >
< FM SECTION >
IHF Sensitivity:Less than 15dB (at 87.5MHz)
(THD 3%)Less than 19dB
(at 98.0/108.0MHz)
Signal to noise ratio:More than 60dB
(Input 54dB)(at 98.0MHz)
Distortion:Less than 2.0%
(Input 54dB)(at 98.0MHz)
Auto stop level:25±10dB (at 98.0MHz)
Stereo separation:More than 30dB (at 98.0MHz)
Intermediate frequency:10.7MHz
< AM SECTION >
Sensitivity:Less than 50dB (at 603kHz)
(S/N 10dB)Less than 49dB (at 999kHz)
Less than 47dB (at 1404kHz)
Signal to noise ratio:More than 33dB
(Input 74dB)(at 999kHz)
Distortion:Less than 2.0%
(Input 74dB)(at 999kHz)
Auto stop level:35-60dB (at 1000kHz)
Intermediate frequency:450kHz
< TAPE SECTION >
Tape speed:3000Hz+3%/–2%
Wow & flutter:Less than 0.35%
(JIS, R.M.S)
Distortion:Less than 3.0% (PB)
Less than 7.0% (REC)
Signal to noise ratio:More than 35dB (PB)
Erasing ratio:More than 55dB
Cross talk:More than 50dB
Separation:More than 35dB