This Service Manual is the “Revision Publishing” and replaces “Simple Manual”
CSD-A110 U(S)/A170 LH(S)(S/M Code No. 09-003-342-2T1).
• BASIC TAPE MECHANISM : ZZM-1 YR2NF
• BASIC CD MECHANISM : DA11T3C
S/M Code No. 09-003-342-2R1
REVISION
DATA
Page 2
SPECIFICATIONS
U MODELLH MODEL
Design and specifications are subject to change
•
without notice
.
Design and specifications are subject to change
•
without notice
.
2
Page 3
PROTECTION OF EYES FROM LASER BEAM DURING SERVICING
This set employs laser. Therefore, be sure to follow carefully the
instructions below when servicing.
WARNING!
WHEN SERVICING, DO NOT APPROACH THE LASER EXIT
WITH THE EYE TOO CLOSELY. IN CASE IT IS NECESSARY TO
CONFIRM LASER BEAM EMISSION. BE SURE TO OBSERVE
FROM A DISTANCE OF MORE THAN 30cm FROM THE
SURFACE OF THE OBJECTIVE LENS ON THE OPTICAL
PICK-UP BLOCK.
Caution: Invisible laser radiation when
open and interlocks defeated avoid exposure to beam.
Advarsel:Usynling laserståling ved åbning,
når sikkerhedsafbrydere er ude af funktion.
Undgå udsættelse for stråling.
VAROITUS!
Laiteen Käyttäminen muulla kuin tässä käyttöohjeessa mainitulla tavalla saattaa altistaa käyt-täjän turvallisuusluokan 1 ylittävälle näkymättömälle lasersäteilylle.
VARNING!
Om apparaten används på annat sätt än vad som specificeras i
denna bruksanvising, kan användaren utsättas för osynling
laserstrålning, som överskrider gränsen för laserklass 1.
CAUTION
Use of controls or adjustments or performance of procedures
other than those specified herein may result in hazardous
radiation exposure.
ATTENTION
L'utilisation de commandes, réglages ou procédures autres que
ceux spécifiés peut entraîner une dangereuse exposition aux
radiations.
ADVARSEL!
Usynlig laserståling ved åbning, når sikkerhedsafbrydereer ude
af funktion. Undgå udsættelse for stråling.
This Compact Disc player is classified as a CLASS 1 LASER
product.
The CLASS 1 LASER PRODUCT label is located on the rear
exterior.
CLASS 1
KLASSE 1
LUOKAN 1
KLASS 1
LASER PRODUCT
LASER PRODUKT
LASER LAITE
LASER APPARAT
Precaution to replace Optical block
(SF-P101NR)
Body or clothes electrostatic potential could ruin
laser diode in the optical block. Be sure ground
body and workbench, and use care the clothes
do not touch the diode.
1) After the connection, remove solder shown in
the right figure.
MAIN C.B
C211 87-A11-603-080 CAP, S 0.15-16<A170 LH<S>>
C212 87-A11-603-080 CAP, S 0.15-16<A170 LH<S>>
C215 87-016-460-080 C-CAP,S 0.22-16 B
C216 87-016-460-080 C-CAP,S 0.22-16 B
C231 87-010-213-080 C-CAP,S 0.015-50 B
C232 87-010-213-080 C-CAP,S 0.015-50 B
C233 87-A10-201-080 C-CAP,S0.33-16 KB
C234 87-A10-201-080 C-CAP,S0.33-16 KB
C235 87-016-669-080 C-CAP,S 0.1-25 K B
C236 87-016-669-080 C-CAP,S 0.1-25 K B
C418 87-010-213-080 C-CAP,S 0.015-50 B
C419 87-A11-608-080 C-CAP,S 0.33-25 K B
C420 87-016-369-080 C-CAP,S 0.033-25 B K
C421 87-A11-177-080 C-CAP,S 0.15-16 K B
C422 87-010-184-080 CHIP CAPACITOR 3300P(K)
C423 87-010-992-080 C-CAP,S 0.047-25 B
C424 87-A11-606-080 C-CAP,S 0.22-25 K B
C425 87-010-176-080 C-CAP,S 680P-50 SL
C426 87-A11-608-080 C-CAP,S 0.33-25 K B
C428 87-010-197-080 CAP, CHIP 0.01 DM
C15 87-016-669-080 C-CAP,S 0.1-25 K B
C16 87-010-178-080 CHIP CAP 1000P
C17 87-016-669-080 C-CAP,S 0.1-25 K B
C18 87-010-198-080 CAP, CHIP 0.022
C19 87-016-669-080 C-CAP,S 0.1-25 K B
C20 87-010-400-080 CAP, ELECT 0.47-50V
C21 87-010-403-080 CAP, ELECT 3.3-50V
C26 87-012-358-080 C-CAP,S 0.47-10 F Z
C27 87-012-358-080 C-CAP,S 0.47-10 F Z
C28 87-010-992-080 C-CAP,S 0.047-25 B
• Regarding connectors, they are not stocked as they are not the initial order items.
The connectors are available after they are supplied from connector manufacturers upon the order is received.
CHIP RESISTOR PART CODE
Chip Resistor Part Coding
88
A
Resistor Code
Chip resistor
WattageTypeTolerance
1/16W10055%CJ
1/16W
1/10W
1/8W
1608
2125
3216
5%
5%
5%
Symbol
Figure
Value of resistor
CJ
CJ
CJ
Form
L
W
Dimensions (mm)
LW t
1.00.50.35104
t
1.60.80.45
21.25 0.45
1.6
0.55
3.2
Resistor Code
108
118
128
mono. SW
: A
: A
Control logic
IC, LA1828IC, BA4560N
87
Page 8
WIRING-1 (MAIN/CD)
1
A
B
C
D
234567
8
9
10
111213
14
E
F
G
H
I
J
K
109
Page 9
SCHEMATIC DIAGRAM-1 (MAIN)
DRY BATTERY
R14X8
DC 12V
1211
J90
Page 10
SCHEMATIC DIAGRAM-2 (CD)
1413
Page 11
WIRING-2 (MOTOR)
1
A
B
H MOTOR C.B
C
234567
M2
TRANSISTOR ILLUSTRATION
ECBECBECB
2SA1296
2SC1815
2SA933
2SC1740
DTC114TS
DTC124XS
2SA1318
D
E
F
G
TO B CD C.B CNA402
_
PIN3
+
M2
(SLED MOTOR)
SW1
(INSIDE LIMIT SW)
(SPINDLE MOTOR)
SW1
_
M3
M3
+
C
B
E
2SC2714
DTC114TK
DTC114YK
DTC124XK
DTC144TK
BCE
2SB1370
H
I
J
K
1615
Page 12
WIRING-3 (FRONT/HP/BATT1/BATT2)
1
A
B
C
D
234567
8
9
10
111213
14
E
F
G
H
I
J
K
1817
Page 13
SCHEMATIC DIAGRAM-3 (FRONT)
CN602
CONN, 8P H 9604S-08F
2019
Page 14
SCHEMATIC DIAGRAM-4 (TUNER)
L005, TC001
FM FREQ. RANGE
ADJ.
2221
Page 15
WIRING-4 (TUNER)
1
A
B
C
D
234567
E
F
G
H
I
J
K
23
Page 16
ELECTRICAL ADJUSTMENT
D
TUNER C.B
5
L003 (MW BAR ANT)
B
CD C.B
TC001
L005
3
2
1
L006
L004
TP1(DET)
16
IC001
1
L007
1
2
IC002
TP2(VT)
+
C039
21
1
5
IC404
SFR430
CN401
A
MAIN C.B
E
H.P. C.B
9
IC801
1
CN201
M1 (TAPE MOTOR)
CN801
L801
8
RPH
67
J251
PHONES
24
6
7
Page 17
PRACTICAL SERVICE FIGURE
< TUNER SECTION >
1. FM VT Adjustment
Settings : • Test point : TP2(VT)
• Adjustment location :L006
Method : Set to FM 108.0MHz and adjust L006 so that the
test point voltage becomes 6.0V ± 0.05V.
2. MW VT Adjustment
Settings : • Test point : TP2(VT)
• Adjustment location :L004
Method : Set to MW 1000kHz (U), and adjust L004 so that
9. FE Balance Adjustment
Settings : • Test point : IC401 PIN58 (VR), IC401 PIN 20
(FE)
• Adjustment location : SFR430
Method : Playback the disc and adjust SFR430 so that the
test point voltage becomes 0V.
25
Page 18
IC DESCRIPTION
IC, LA9241ML
Pin No.Pin NameI/ODescription
Pin to which external pickup photo diode is connected. RF signal is created by adding
1
FIN2
I
with the FIN1 pin signal. FE signal is created by subtracting from the FIN1 pin signal.
10
11
12
13
14
15
2
3
4
5
6
7
8
9
FIN1
E
F
TB
TE-
TE
TESI
SCI
TH
TA
TD-
TD
JP
TO
I
Pin to which external pickup photo diode is connected.
Pin to which external pickup photo diode is connected. TE signal is created by
I
subtracting from the F pin signal.
I
Pin to which external pickup photo diode is connected.
I
DC component of the TE signal is input.
Pin to which external resistor setting the TE signal gain is connected between the TE
I
pin.
O
TE signal output pin.
TES “Track Error Sense” comparator input pin. TE signal is passed through a band-
I
pass filter then input.
I
Shock detection signal input pin.
I
Tracking gain time constant setting pin.
O
TA amplifier output pin.
Pin to which external tracking phase compensation constants are connected between
I
the TD and VR pins.
I
Tracking phase compensation setting pin.
I
Tracking jump signal (kick pulse) amplitude setting pin.
O
Tracking control signal output pin.
16
17
18
19
20
21
22
23
24
25
26
27
28
29
FD
FD-
FA
FA-
FE
FE-
AGND
SP
SPI
SPG
SP-
SPD
SLEQ
SLD
—
O
Focusing control signal output pin.
Pin to which external focusing phase compensation constants are connected between
I
the FD and FA pins.
Pin to which external focusing phase compensation constants are connected between
I
the FD– and FA– pins.
Pin to which external focusing phase compensation constants are connected between
I
the FA and FE pins.
O
FE signal output pin.
I
Pin to which external FE signal gain setting resistor is connected between the FE pin.
Analog signal GND.
O
Signal ended output of the CV+and CV- pin input signal.
I
Spndle amp input.
I
Pin to which external spindle gain setting resistor in 12 cm mode is connected.
Pin to which external spindle phase compensation constants are connected together
I
with SPD pin.
O
Spindle control signal output pin.
I
Pin to which external sled phase compensation constants are connected.
O
Sled control signal output pin.
30, 31
32, 33
34
35
SL-, SL+
JP-, JP+
TGL
TOFF
I
Sled advance signal input pin from microprocessor.
I
Tracking jump signal input pin from DSP.
I
Tracking gain control signal input from DSP. Low gain when TGL = H.
I
Tracking off control signal input pin from DSP. Off when TOFF = H.
26
Page 19
Pin No.Pin NameI/ODescription
36
TES
O
Pin from which TES signal is output to DSP.
37
38
39, 40
41
42
43
44
45
46
47
48
49
50
51
52
HFL
SLOF
CV–, CV+
RFSM
RFS-
SLC
SLI
DGND
FSC
TBC
NC
DEF
CLK
CL
DAT
O
O
O
—
O
—
O
“High Frequency Level” is used to judge whether the main beam position is on top of
bit or on top of mirror.
I
Sled servo off control input pin.
I
CLV error signal input pin from DSP.
RF output pin.
RF gain setting and EFM signal 3T compensation constant setting pin together with
I
RFSM pin.
“Slice Level Control” is the output pin which controls the RF signal data slice level by
DSP.
I
Input pin which control the data slice level by the DSP.
Digital system GND.
Output pin to which external focus search smoothing capacitor is connected.
I
“Tracking Balance Control” EF balance variable range setting pin.
No connection.
Disc defect detector output pin.
I
Reference clock input pin. 4.23 MHz of the DSP is input.
“Focus Search Select” focus search mode (± search/+ search) select pin.
Servo system and digital system Vcc pin.
Pin to which external bypass capacitor for reference voltage is connected.
O
Reference voltage output pin.
I
Disc defect detector time constant setting pin.
I
Pin to which external capacitor for RF signal peak holding is connected.
I
Pin to which external capacitor for RF signal bottom holding is connected.
O
APC circuit output pin.
I
APC circuit input pin.
RF system Vcc pin.
27
Page 20
IC, LC78622ED
Pin No.Pin NameI/ODescription
1
DEFI
I
Defect sense signal (DEF) input pin. (Connect to 0V when not used).
2
3
4
5
6
7
8
9
10
11
12, 13
14
15
16
17
18
TAI
PDO
VVSS
ISET
VVDD
FR
VSS
EFMO
EFMIN
T2
CLV+, CLK-
___
V/P
HFL
TES
TOFF
TGL
—
—
—
I
O
For PLL.
I
Test signal input pin with built-in pull-down resistor. Be sure to connect to 0V.
Phase comparator output pin to control external VCO.
GND pin for built-in VCO. Be sure to connect to 0V.
Pin to which external resistor adjusting the PD0 output current.
Power supply pin for built-in VCO.
I
Pin for VCO frequency range adjustment.
Digital system GND. Be sure to connect to 0V.
O
For slice level control.
I
I
Test signal input pin with built-in pull-down resistor. Be sure to connect to 0V.
O
Disc motor control output. Three level output is possible using command.
Rough servo or phase control automatic selection monitoring output pin. Rough servo
O
EFM signal output pin.
EFM signal input pin.
at H. Phase servo at L.
I
Track detect signal input pin. Schmidt input.
I
Tracking error signal input pin. Schmidt input.
O
Tracking OFF output pin.
O
Tracking gain selection output pin. Gain boost at L.
19, 20
21
22
23
24
25
26
27
28
29
30
31
32, 33
34
35
36
37
JP+, JP-
PCK
FSEQ
VDD
SL+
SL-
—
PUIN
_______
RW
EMPH
C2F
DOUT
T3, T4
N.C.
MUTEL
LVDD
LCHO
—
—
—
—
O
Track jump control signal output pin. Three level output is possible using command.
O
EFM data playback clock monitoring pin 4.3218 MHz when phase is locked in.
Sync signal detection output pin. H when the sync signal which is detected from EFM
O
signal and thesync signal which is internally generated agree.
Digital system power supply pin.
O
Moves the sled to outer circumference.
O
Moves the sled to inner circumference.
Not connected.
I
CD pickup inner switch detection.
O
Read, wright signal.
O
De-emphasis monitor output pin. De-emphasis disc is being played back at H.
O
C2 flag output pin.
O
DIGITAL OUT output pin. (EIAJ format).
I
Test signal input pin with built-in pull-down resistor. Be sure to connect to 0V.
Not used. Set the pin to open.
O
L-channel 1-bit DAC.
O
L-channel mute output pin.
L-channel power supply pin.
L-channel output pin.
38
39
40
41
42
LVSS
RVSS
RCHO
RVDD
MUTER
—
—
—
O
R-channel 1-bit DAC.
O
L-channel GND. Be sure to connect to 0V.
R-channel GND. Be sure to connect to 0V.
R-channel output pin.
R-channel power supply pin.
R-channel mute output pin.
Pin to which external 16.9344 MHz crystal oscillator is connected.
I
Crystal oscillator GND pin. Be sure to connect to 0V.
O
Subcode block sync signal output pin.
O
C1, C2, single and dual correction monitoring pin.
O
Subcode P, Q, R, S, T, U and W output pin.
O
Subcode frame sync signal output pin. Falls down when subcode enters standby.
Subcode read clock input pin. Schmidt input. (Be sure to connected to 0V when not
I
in use.)
Pin outputting the 7.35 kHz sync signal which is generated by dividing frequency of
O
crystal oscillator.
O
Subcode Q output standby output pin.
I
Read/write control input pin. Schmidt input.
O
Subcode Q output pin.
I
Command input pin from microprocessor.
I
Command input read clock or subcode read input clock from SQOUT pin
I
LC78622 reset input pin. Set this pin to L once when the main power is turned on.
O
Test signal output pin. Use this pin as open (normally L output).
60
61
62
63
64
16M
4.2M
T5
______
CS
T1
O
16.9344 MHz output pin.
O
4.2336 MHz output pin.
I
Test signal input pin with built-in pull-down resistor. Be sure to connect to 0V.
Chip select signal input pin with built-in pull-down resistor. Be sure to connect to 0V
I
while it is not controlling.
I
Test signal input pin without built-in pull-down resistor. Be sure to connect to 0V.
29
Page 22
IC, LC865516A-5P16
Pin No.Pin NameI/ODescription
1
2
3
4
5
SEG E
SEG F
SEG G
NC
I-RES
O
SEG E control.
O
SEG F control.
O
SEG G control.
—
Not connected.
I
Micro processor reset input
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
6
7
8
9
XT(IN)
NC
XT2(OUT)
VSS
CF1(IN)
CF2(OUT)
VDD
I-KEY0
I-KEY1
I-MOTOR
I-CD SW
O-SHIFT
NC
O-BASS LED
O-QS LED
O-SFT LED
I-DRF
I-WRQ
NC
I
Connected to an external 32.768 kHz crystal oscillator.
—
Not connected.
O
Connected to an external 32.768 kHz crystal oscillator.
—
GND.
I
Connected to an external 5.76 MHz ceramic filter.
O
Connected to an external 5.76 MHz ceramic filter.
—
Microprocessor power supply (+5V).
I
Key AD input. (AD)
I
Key AD input. (AD)
I
Deck status input. (AD)
I
CD door switch status input.
O
Main clock shift output.
—
Not connected.
O
BASS LED ON/OFF control output. (Not connected)
O
Q sound LED ON/OFF control output. (Not connected)