Agilent Technologies 01664-97005 User Manual

Download

Service Guide

Publication number 01664-97005 Second edition, January 2000

For Safety information, Warranties, and Regulatory information, see the pages at the end of the book.

 Copyright Agilent Technologies 1987–2000

Agilent Technologies 1664A Logic Analyzer

The Agilent Technologies 1664A is a 50-MHz State/500-MHz Timing Logic Analyzer.

Features

Some of the main features of the 1664A Logic Analyzer is as follows:

• 32 data channels and 2 clock/data channels

• 3.5-inch disk drive

• Centronix (parallel) interface (with GPIB and RS-232C interfaces available as

options)

• Variable setup/hold time

• 4 kbytes deep memory on all channels with 8 kbytes in half channel mode

• Marker measurements

• 12 levels of trigger sequencing for state and 10 levels of sequential triggering for

timing

• 100 MHz time and number-of-states tagging

• Full programmability (with optional interface)

Service Strategy

The service strategy for this instrument is the replacement of defective assemblies. This service guide contains information for finding a defective assembly by testing and servicing the 1664A.

This logic analyzer can be returned to Agilent Technologies for all service work, including troubleshooting. Contact your nearest Agilent Technologies Sales Office for more details.

The Agilent Technologies 1664A Logic Analyzer

iii

In This Book

This book is the service guide for the 1664A Logic Analyzers and is divided into eight chapters.

Chapter 1 contains information about the logic analyzer and includes accessories, specifications and characteristics, and equipment required for servicing.

Chapter 2 tells how to prepare the logic analyzer for use.

Chapter 3 gives instructions on how to test the performance of the logic analyzer.

Chapter 4 contains calibration instructions for the logic analyzer.

Chapter 5 contains self-tests and flowcharts for troubleshooting the logic analyzer.

Chapter 6 tells how to replace assemblies of the logic analyzer and how to return them to Agilent Technologies.

Chapter 7 lists replaceable parts, shows an exploded view, and gives ordering information.

Chapter 8 explains how the logic analyzer works and what the self-tests are checking.

1 General Information

Accessories 1–2 Specifications 1–3 Characteristics 1–3 Supplemental Characteristics 1–4 Recommended Test Equipment 1–8

2 Preparing for Use

To inspect the logic analyzer 2–2 Ferrites 2–3 To apply power 2–4 To operate the user interface 2–4 To set the line voltage 2–4 To degauss the display 2–5 To clean the logic analyzer 2–5 To test the logic analyzer 2–5

3 Testing Performance

To perform the self-tests 3–3

To make the test connectors 3–6

To test the threshold accuracy 3–8

Set up the equipment 3–8 Set up the logic analyzer 3–9 Connect the logic analyzer 3–9 Test the TTL threshold 3–10 Test the ECL threshold 3–12 Test the − User threshold 3–13 Test the + User threshold 3–14 Test the 0 V User threshold 3–15 Test the next pod 3–16

To test the glitch capture 3–17

Set up the equipment 3–17 Set up the logic analyzer 3–18 Connect the logic analyzer 3–18 Test the glitch capture on the connected channels 3–20 Test the next channels 3–22

To test the single-clock, single-edge, state acquisition 3–23

Set up the equipment 3–23 Set up the logic analyzer 3–24 Connect the logic analyzer 3–26 Verify the test signal 3–27 Check the setup/hold combination 3–29

Contents

To test the multiple-clock, multiple-edge, state acquisition 1–34

Set up the equipment 1–34 Set up the logic analyzer 1–35 Connect the logic analyzer 1–37 Verify the test signal 1–38 Check the setup/hold with single clock edges, multiple clocks 1–40

To test the single-clock, multiple-edge, state acquisition 1–45

Set up the equipment 1–45 Set up the logic analyzer 1–46 Connect the logic analyzer 1–48 Verify the test signal 1–49 Check the setup/hold combination 1–51

To test the time interval accuracy 1–54

Set up the equipment 1–54 Set up the logic analyzer 1–55 Connect the logic analyzer 1–57 Acquire the data 1–58

Performance Test Record 3–59

4 Calibrating and Adjusting

Logic analyzer calibration 4–2 Set up the equipment 4–2

To adjust the CRT monitor alignment 4–3

To adjust the CRT intensity 4–5

5 Troubleshooting

To use the flowcharts 5–2 To check the power-up tests 5–15 To run the self-tests 5–16 To test the power supply voltages 5–21 To test the CRT monitor signals 5–23 To test the keyboard signals 5–24 To test the disk drive voltages 5–25 To perform the BNC test 5–27 To test the logic analyzer probe cables 5–28 To test the auxiliary power 5–32

6 Replacing Assemblies

To remove and replace the handle 6–5 To remove and replace the feet and tilt stand 6–5 To remove and replace the cover 6–5 To remove and replace the disk drive 6–6 To remove and replace the power supply 6–7

To remove and replace the Main Circuit board 6–7 To remove and replace the switch actuator assembly 6–8 To remove and replace the rear panel assembly 6–9 To remove and replace the front panel and keyboard 6–10 To remove and replace the intensity adjustment 6–10 To remove and replace the monitor 6–11 To remove and replace the handle plate 6–11 To remove and replace the fan 6–12 To remove and replace the line filter 6–12 To remove and replace the optional GPIB and RS-232C cables 6–13 To return assemblies 6–14

7 Replaceable Parts

Replaceable Parts Ordering 7–2 Exploded View 7–3 Replaceable Parts List 7–4 Power Cables and Plug Configurations 7–8

Contents

8 Theory of Operation

Block-Level Theory 8–3

The 1664A Logic Analyzer 8–3 The Logic Acquisition Circuitry 8–6

Self-Tests Description 8–9

Power-up Self-Tests 8–9 System Tests (System PV) 8–10 Analyzer Tests (Analy PV) 8–13

GPIB (Optional) 8–15

RS-232C(Optional) 8–16

Centronix 8–17

vii

Contents

viii

Accessories 1-2 Specifications 1-3 Characteristics 1-3 Supplemental Characteristics 1-4 Recommended Test Equipment 1-8

General Information

This chapter lists the accessories, the specifications and characteristics, and the recommended test equipment.

Accessories

The following accessories are supplied with the 1664A Logic Analyzers.

Accessories Supplied Part Number Qty

Probe tip assemblies 01650-61608 2

Probe cables 16550-61601 1

Grabbers (20 per pack) 5090-4356 2

Probe ground (5 per pack) 5959-9334 2

User’s Reference 01660-90904 1

Accessories Pouch 01660-84501 1

HIL Mouse A2838A 1

Accessories Available

Other accessories available for the 1664A Logic Analyzer are listed in the Accessories for Agilent Logic Analyzers brochure. The table below lists additional documentation that is

available from your nearest Agilent Technologies sales office for use with your logic analyzer.

Accessories Available Part Number

Demo Training Kit E2433-60007

Programming Reference 01660-90933

Service Guide 01664-97005

1–2

General Information

Specifications

The specifications are the performance standards against which the product is tested.

Maximum State Speed 50 MHz

Minimum State Clock Pulse Width

Minimum Master to Master Clock Time

Minimum Glitch Width* 3.5 ns Threshold Accuracy ± (100 mV + 3% of

Setup/Hold Time:

Single Clock, Single Edge 0.0/3.5 ns through 3.5/0.0 ns,

Single Clock, Multiple Edges 0.0/4.0 ns through 4.0/0.0 ns,

Multiple Clocks, Multiple Edges 0.0/4.5 ns through 4.5/0.0 ns,

3.5 ns

20.0 ns

threshold setting)

adjustable in 500-ps increments

* Specified for an input signal VH = -0.9 V, VL = -1.7 V, slew rate = 1 V/ns, and threshold = -1.3 V.

Characteristics

These characteristics are not specifications, but are included as additional information.

Full Channel Half Channel

Maximum State Clock Rate 50 MHz 50 MHz

Maximum Conventional Timing Rate 250 MHz 500 MHz

Maximum Transitional Timing Rate 125 MHz 250 MHz

Maximum Timing with Glitch Rate N/A 125 MHz

Memory Depth 4K 8K

Channel Count: 34 17

* For all modes except glitch.

1–3

General Information

Supplemental Characteristics

Probes

Input Resistance 100 kΩ, ± 2%

Input Capacitance ~ 8 pF

Minimum Voltage Swing 500 mV, peak-to-peak Threshold Range ± 6.0 V, adjustable in 50-mV increments

State Analysis

State/Clock Qualifiers 6

Time Tag Resolution

Maximum Time Count Between States 34 seconds

Maximum State Tag Count

Timing Analysis

Sample Period Accuracy 0.01 % of sample period

Channel-to-Channel Skew 2 ns, typical Time Interval Accuracy ± [sample period + channel-to-channel skew

8 ns or 0.1%, whichever is greater

4.29 x 10

+(0.01%)(time reading)]

Triggering

Sequencer Speed 125 MHz, maximum

State Sequence Levels 12

Timing Sequence Levels 10

Maximum Occurrence Counter Value 1,048,575

Pattern Recognizers 10

Maximum Pattern Width 34 channels

Range Recognizers 2

Range Width 32 bits each

Timers 2

Timer Value Range 400 ns to 500 seconds

Glitch/Edge Recognizers 2 (timing only)

Maximum Glitch/Edge Width 34 channels

*Maximum state clock rate with time or state tags on is 50 MHz. When all pods are assigned to a state or timing

machine, time or state tags halve the memory depth.

1–4

General Information

Supplemental Characteristics

Measurement and Display Functions

Displayed Waveforms 24 lines maximum, with scrolling across 96 waveforms.

Measurement Functions

Run/Stop Functions Run starts acquisition of data in specified trace mode.

Stop In single trace mode or the first run of a repetitive acquisition, Stop halts

acquisition and displays the current acquisition data. For subsequent runs in repetitive mode, Stop halts acquisition of data and does not change the current display.

Trace Mode Single mode acquires data once per trace specification. Repetitive mode repeats single mode acquisitions until Stop is pressed or until the time interval between two specified patterns is less than or greater than a specified value, or within or not within a specified range.

Indicators

Activity Indicators Provided in the Configuration and Format menus for identifying

high, low, or changing states on the inputs.

Markers Two markers (X and O) are shown as vertical dashed lines on the display.

Trigger Displayed as a vertical dashed line in the Timing Waveform display and as line 0

in the State Listing display.

Data Entry/Display

Labels Channels may be grouped together and given a 6-character name. Up to

126 labels in each analyzer may be assigned with up to 32 channels per label.

Display Modes State listing, State Waveforms, Chart, Compare Listing, Compare Difference Listing, Timing Waveforms, and Timing Listings. State Listing and Timing Waveforms can be time-correlated on the same displays.

Timing Waveform Pattern readout of timing waveforms at X or O marker.

Bases Binary, Octal, Decimal, Hexadecimal, ASCII (display only), Two’s Complement,

and User-defined symbols.

Symbols 1,000 maximum. Symbols can be downloaded over RS-232 or GPIB.

1–5

General Information

Supplemental Characteristics

Marker Functions

Time Interval The X and O markers measure the time interval between a point on a

timing waveform and the trigger, two points on the same timing waveform, two points on different waveforms, or two states (time tagging on).

Delta States (state analyzer only) The X and O markers measure the number of tagged states between one state and trigger or between two states.

Patterns The X and O markers can be used to locate the nth occurrence of a specified pattern from trigger, or from the beginning of data. The O marker can also find the nth occurrence of a pattern from the X marker.

Statistics X and O marker statistics are calculated for repetitive acquisitions. Patterns must be specified for both markers, and statistics are kept only when both patterns can be found in an acquisition. Statistics are minimum X to O time, maximum X to O time, average X to O time, and ratio of valid runs to total runs.

Auxiliary Power

Power Through Cables 1/3 amp at 5 V maximum per cable

Operating Environment

Temperature Instrument, 0 °C to 55 °C (+32 °F to 131 °F).

Probe lead sets and cables, 0 °C to 65 °C (+32 °F to 149 °F).

Humidity Instrument, probe lead sets, and cables, up to

95% relative humidity at +40 °C (+122 °F).

Altitude To 4600 m (15,000 ft).

Vibration Operating: Random vibration 5 to 500 Hz,

10 minutes per axis, ≈0.3 g (rms).

Non-operating: Random vibration 5 to 500 Hz, 10 minutes per axis, ≈ 2.41 g (rms); and swept sine resonant search, 5 to 500 Hz,

0.75 g (0-peak), 5 minute resonant dwell at 4 resonances per axis.

Dimensions

1–6

General Information

Supplemental Characteristics

Product Regulations

Safety IEC 348

UL 1244 CSA Standard C22.2 No.231 (Series M-89)

EMC This product meets the requirement of the European

Communities (EC) EMC Directive 89/336/EEC.

Emissions EN55011/CSIPR 11 (ISM, Group1,Class A equipment)

SABS RAA Act No. 24(1990)

Immunity EN50082-1 Code

Notes IEC 801-2 (ESD)4kV CD, 8kV AD 2 IEC 801-3 (Rad.) 3V/m 1

Performance Codes:

IEC 801-4 (EFT) 1kV

1 PASS - Normal operations, no effect. 2 PASS - Temporary degradation, self recoverable. 3 PASS - Temporary degradation, operator intervention required.

4 FAIL - Not recoverable, component damage.

Notes: (None)

1–7

General Information

Recommended Test Equipment

Equipment Required

Equipment Critical Specifications Recommended

Use

Model/Part

Pulse Generator 100 MHz, 3.5 ns pulse width,

Agilent 8131A Option 020 P,T

< 600 ps rise time

Digitizing Oscilloscope Function Generator

≥ 6 GHz bandwidth, < 58 ps rise time

−6

Accuracy ≤ (5)(10

) × frequency,

Agilent 54121T P Agilent 3325B Option 002 P

DC offset voltage ±6.3 V Digital Multimeter 0.1 mV resolution, 0.005% accuracy Agilent 3458A P BNC-Banana Cable Agilent 11001-60001 P BNC Tee BNC (m)(f)(f) Agilent 1250-0781 P Cable BNC (m)(m) 48 inch > 2GHz bandwidth Agilent 8120-1840 P,T SMA Coax Cable (Qty 3) 18 GHz bandwidth Agilent 8120-4948 P Adapter (Qty 4) SMA(m)-BNC(f) Agilent 1250-1200 P, T Adapter SMA(f)-BNC(m) Agilent 1250-2015 P Coupler (Qty 4) BNC (m)(m) Agilent 1250-0216 P, T 20:1 Probes (Qty 2) Agilent 54006A P BNC Test Connector, 17x2

(Qty 1) BNC Test Connector, 6x2

(Qty 4)

P,T

Digitizing Oscilloscope > 100 MHz Bandwidth Agilent 54600A T BNC Shorting Cap Agilent 1250-0074 T BNC-Banana Adapter Agilent 1251-2277 T Light Power Meter United Detector 351 A Alignment Tool 8710-1300 A

*A = Adjustment P = Performance Tests T = Troubleshooting

**Instructions for making these test connectors are in chapter 3, "Testing Performance."

1–8

To inspect the logic analyzer 2-2 Ferrites 2-3 To apply power 2-4 To operate the user interface 2-4

To set the line voltage 2-4 To degauss the display 2-5 To clean the logic analyzer 2-5 To test the logic analyzer 2-5

Preparing for Use

Preparing For Use

This chapter gives you instructions for preparing the logic analyzer for use.

Power Requirements

The logic analyzer requires a power source of either 115 Vac or 230 Vac, –22 % to +10 %, single phase, 48 to 66 Hz, 200 Watts maximum power.

Operating Environment

The operating environment is listed in chapter 1. Note the noncondensing humidity limitation. Condensation within the instrument can cause poor operation or malfunction. Provide protection against internal condensation.

The logic analyzer will operate at all specifications within the temperature and humidity range given in chapter 1. However, reliability is enhanced when operating the logic analyzer within the following ranges:

• Temperature: +20 °C to +35 °C (+68 °F to +95 °F)

• Humidity: 20% to 80% noncondensing

Storage

Store or ship the logic analyzer in environments within the following limits:

• Temperature: -40 °C to + 75 °C

• Humidity: Up to 90% at 65 °C

• Altitude: Up to 15,300 meters (50,000 feet)

Protect the logic analyzer from temperature extremes which cause condensation on the instrument.

To inspect the logic analyzer

1 Inspect the shipping container for damage.

If the shipping container or cushioning material is damaged, keep them until you have checked the contents of the shipment and checked the instrument mechanically and electrically.

Check the supplied accessories.

Accessories supplied with the logic analyzer are listed in "Accessories" in chapter 1.

3 Inspect the product for physical damage.

Check the logic analyzer and the supplied accessories for obvious physical or mechanical defects. If you find any defects, contact your nearest Agilent Technologies Sales Office. Arrangements for repair or replacement are made, at Agilent Technologies’ option, without waiting for a claim settlement.

2–2

Preparing for Use

Ferrites

Ferrites are included in the 1664A accessory pouch for the logic analyzer cable. When properly installed, the ferrites reduce RFI emissions from the logic analyzer.

In order to ensure compliance of the 1664A Logic Analyzer to the CISPR11 Class A radio frequency interference (RFI) limits, you must install the ferrite to absorb radio frequency energy.

Note: Adding or removing the ferrite will not affect the normal operation of the analyzer.

Ferrite Installation Instructions

Use the following steps to install the ferrite on the logic analyzer cable.

Place the ferrite halves and spacer on the logic analyzer cable like a clamshell

around the whole cable. The ferrite should be 10 cm (about 4 in) from the the end of the cable shell as shown.

Ferrites

2 Insert the clamps onto the ends of the ferrites. The locking tab should fit cleanly in

the ferrite grooves.

When properly installed, the ferrite should appear on the logic analyzer cable as shown.

2–3

Preparing for Use

To apply power

CAUTION

Electrostatic discharge can damage electronic components. Use grounded wriststraps and mats when performing any service to the logic analyzer.

Check that the line voltage selector, located on the rear panel, is on the correct setting and the correct fuse is installed.

See also, "To set the line voltage" on this page.

2 Connect the power cord to the instrument and to the power source.

This instrument is equipped with a three-wire power cable. When connected to an appropriate ac power outlet, this cable grounds the instrument cabinet. The type of power cable plug shipped with the instrument depends on the country of destination. Refer to chapter 7, "Replaceable Parts," for option numbers of available power cables and plug configurations.

Turn on the instrument power switch located on the front panel.

To operate the user interface

To select a field on the logic analyzer screen, use the arrow keys to highlight the field, then press the Select key. For more information about the logic analyzer interface, refer to the Agilent Technologies 1660 Series Logic Analyzer User’s Reference.

To set the GPIB address or to configure for RS-232C, refer to the Agilent Technologies 1660 Series Logic Analyzer User’s Reference.

To set the line voltage

When shipped from the factory, the line voltage selector is set and an appropriate fuse is installed for operating the instrument in the country of destination. To operate the instrument from a power source other than the one set, perform the following steps.

2–4

Preparing for Use

To degauss the display

1 Turn the power switch to the Off position, then remove the power cord from the

instrument.

2 Remove the fuse module by carefully prying at the top center of the fuse module

until you can grasp it and pull it out by hand.

3 Reinsert the fuse module with the arrow for the appropriate line voltage aligned

with the arrow on the line filter assembly switch.

4 Reconnect the power cord. Turn on the instrument by setting the power switch to

the On position.

To degauss the display

If the logic analyzer has been subjected to strong magnetic fields, the CRT might become magnetized and display data might become distorted. To correct this condition, degauss the CRT with a conventional external television type degaussing coil.

To clean the logic analyzer

With the instrument turned off and unplugged, use mild soap and water to clean the front and cabinet of the logic analyzer. Harsh soap might damage the water-base paint.

To test the logic analyzer

• If you require a test to verify the specifications, start at the beginning of chapter 3,

"Testing Performance."

• If you require a test to initially accept the operation, perform the self-tests in

chapter 3.

• If the logic analyzer does not operate correctly, go to the beginning of chapter 5,

"Troubleshooting."

2–5

2–6

To perform the self-tests 3-3 To make the test connectors 3-6 To test the threshold accuracy 3-8 To test the glitch capture 3-17 To test the single-clock, single-edge, state acquisition 3-23 To test the multiple-clock, multiple-edge, state acquisition 3-34 To test the single-clock, multiple-edge, state acquisition 3-45 To test the time interval accuracy 3-54 Performance Test Record 3-59

Testing Performance

This chapter tells you how to test the performance of the logic analyzer against the specifications listed in chapter 1. To ensure the logic analyzer is operating as specified, you perform software tests (self-tests) and manual performance tests on the analyzer. The logic analyzer is considered performance-verified if all of the software tests and manual performance tests have passed. The procedures in this chapter indicate what constitutes a "Pass" status for each of the tests.

The Logic Analyzer Interface

Test Strategy

For a complete test, start at the beginning with the software tests and continue through to the end of the chapter. For an individual test, follow the procedure in the test. The examples in this chapter were performed using an 1664A.

The performance verification procedures starting on page 3–8 are each shown from power-up. To exactly duplicate the set-ups in the tests, save the power-up configuration to a file on a disk, then load that file at the start of each test.

If a test fails, check the test equipment set-up, check the connections, and verify adequate grounding. If a test still fails, the most probable cause of failure would be the main circuit board.

Test Interval

Test the performance of the logic analyzer against specifications at two-year intervals or if it is replaced or repaired.

Performance Test Record

A performance test record for recording the results of each procedure is located at the end of this chapter. Use the performance test record to gauge the performance of the logic analyzer over time.

Test Equipment

Each procedure lists the recommended test equipment. You can use equipment that satisfies the specifications given. However, the procedures are based on using the recommended model or part number. Before testing the performance of the logic analyzer, warm-up the instrument and the test equipment for 30 minutes.

3–2

To perform the self-tests

The self-tests verify the correct operation of the logic analyzer. Self-tests can be performed all at once or one at a time. While testing the performance of the logic analyzer, run the self-tests all at once.

1 Disconnect all inputs, insert the boot disk, then turn on the power switch. Wait until

the power-up tests are complete.

2 Press the System key. Select the field next to System, then select Test in the pop-up

menu then press the Select key.

3 Select the box labeled Load Test System then press the Select key. Load the disk

containing the performance verification (self-tests) into the disk drive (normally the same as the boot disk).

4 Select the box labeled Continue and press the Select key. 5 After the test files have been loaded, the Analy PV menu is displayed. Select All

Analyzer Tests.

You can run all tests at one time, except for the Data Input Inspection, by running All Analyzer Tests. To see more details about each test when troubleshooting failures, you can run each test individually. This example shows how to run all tests at once.

When the tests finish, the status for each test shows Passed or Failed, and the status for the All Analyzer Tests changes from Untested to Tested.

6 Select Analy PV, then select Sys PV in the pop-up menu.

3–3

Testing Performance

To perform the self-tests

7 Select the Printer/Controller field next to Sys PV, then select System Test in the

pop-up menu then press the Select key.

8 Install a formatted disk that is not write protected into the disk drive. If the 1664A

has the RS-232C option (020), connect an RS-232C loopback connector onto the RS-232C port.

9 Select All System Tests.

You can run all tests at one time, except for the Front Panel Test and Display Test, by running All System Tests. To see more details about each test when troubleshooting failures, you can run each test individually. This example shows how to run all tests at once.

When the tests finish, the status for each test shows Passed or Failed, and the status for the All System Tests changes from Untested to Tested. Note that the Front Panel Test and Display Test remain Untested, and the RS-232C Test will display FAILED if option 020 is not installed.

Select the Front Panel Test.

A screen duplicating the front panel appears on the screen.

a Press each key on the front panel. The corresponding key on the screen will change

from a light to a dark color. Test the knob by turning it in both directions.

b Note any failures, then press the Done key a second time to exit the Front Panel Test.

The status of the test changes from Untested to Tested.

3–4

Testing Performance

To perform the self-tests

11 Select the Display Test.

A white grid pattern is displayed. These display screens are not normally used, but can be used to adjust the display. Refer to chapter 4, "Calibrating and Adjusting" for display adjustments.

a Select Continue and the screen changes to full bright.

b Select Continue and the screen changes to half bright.

c Select Continue and the test screen shows the Display Test status changed to Tested.

Record the results of the tests on the performance test record at the end of this

chapter.

13 To exit the test system, press the System key, then select Exit Test in the pop-up

menu and press the Select key. Reinstall the disk containing the operating system, then select Exit Test System and press the Select key.

3–5

To make the test connectors

The test connectors connect the logic analyzer to the test equipment.

Materials Required

Description Recommended Part Qty

BNC (f) Connector Agilent 1250-1032 5 100 Ω 1% resistor

Berg Strip, 17-by-2 1 Berg Strip, 6-by-2 4 20:1 Probe Agilent 54006A 2 Jumper wire

1 Build four test connectors using BNC connectors and 6-by-2 sections of Berg strip.

a Solder a jumper wire to all pins on one side of the Berg strip.

b Solder a jumper wire to all pins on the other side of the Berg strip.

c Solder two resistors to the Berg strip, one at each end between the end pins.

d Solder the center of the BNC connector to the center pin of one row on the Berg strip.

e Solder the ground tab of the BNC connector to the center pin of the other row on the

Berg strip.

f On two of the test connectors, solder a 20:1 probe. The probe ground goes to the

same row of pins on the test connector as the BNC ground tab.

Agilent 0698-7212 8

3–6

Testing Performance

To make the test connectors

2 Build one test connector using a BNC connector and a 17-by-2 section of Berg strip.

a Solder a jumper wire to all pins on one side of the Berg strip.

b Solder a jumper wire to all pins on the other side of the Berg strip.

c Solder the center of the BNC connector to the center pin of one row on the Berg strip.

d Solder the ground tab of the BNC connector to the center pin of the other row on the

Berg strip.

3–7

To test the threshold accuracy

Testing the threshold accuracy verifies the performance of the following specification:

• Clock and data channel threshold accuracy.

These instructions include detailed steps for testing the threshold settings of pod 1. After testing pod 1, connect and test pod 2. To test pod 2, follow the detailed steps for pod 1, substituting the pod 2 for pod 1 in the instructions.

Each threshold test tells you to record the voltage reading in the performance test record located at the end of this chapter. To check if each test passed, verify that the voltage reading you record is within the limits listed on the performance test record.

Equipment Required

Equipment Critical Specifications Recommended Model/Part

Digital Multimeter 0.1 mV resolution, 0.005% accuracy Agilent 3458A Function Generator

BNC-Banana Cable Agilent 11001-60001 BNC Tee Agilent 1250-0781 BNC Cable Agilent 8120-1840 BNC Test Connector, 17x2

DC offset voltage ±6.3 V

Agilent 3325B Option 002

Set up the equipment

1 Turn on the equipment required and the logic analyzer. Let them warm up for

30 minutes before beginning the test.

2 Set up the function generator.

a Set up the function generator to provide a DC offset voltage at the Main Signal output.

b Disable any AC voltage to the function generator output, and enable the high voltage

output.

c Monitor the function generator DC output voltage with the multimeter.

3–8

Testing Performance

To test the threshold accuracy

Set up the logic analyzer

1 Press the Config key. Assign all pod fields to Machine 1. To assign the pod fields,

select the pod fields, then select Machine 1 in the pop-up menu.

2 In the Analyzer 1 box, select the Type field. Select Timing in the pop-up menu.

Connect the logic analyzer

1 Using the 17-by-2 test connector, BNC cable, and probe tip assembly, connect the

data and clock channels of pod 1 to one side of the BNC Tee.

2 Using a BNC-banana cable, connect the voltmeter to the other side of the BNC Tee. 3 Connect the BNC Tee to the Main Signal output of the function generator.

3–9

Testing Performance

To test the threshold accuracy

Test the TTL threshold

1 Press the Format key. Select the field to the right of Pod 1, then select TTL in the

pop-up menu.

On the function generator front panel, enter 1.647 V ±1 mV DC offset. Use the multimeter to verify the voltage.

The activity indicators for pod 1 should show all data channels and the J-clock channel at a logic high.

Using the Modify down arrow on the function generator, decrease offset voltage in 1-mV increments until all activity indicators for pod 1 show the channels at a logic low. Record the function generator voltage in the performance test record.

3–10

Testing Performance

To test the threshold accuracy

4 Using the Modify up arrow on the function generator, increase offset voltage in

1-mV increments until all activity indicators for pod 1 show the channels at a logic high. Record the function generator voltage in the performance test record.

3–11

Testing Performance

To test the threshold accuracy

Test the ECL threshold

1 Select the field to the right of Pod 1, then select ECL in the pop-up menu.

On the function generator front panel, enter −1.160 V ±1 mV DC offset. Use the multimeter to verify the voltage.

The activity indicators for pod 1 should show all data channels and the J-clock channel at a logic high.

Using the Modify down arrow on the function generator, decrease offset voltage in

1-mV increments until all activity indicators for pod 1 show the channels are at a logic low. Record the function generator voltage in the performance test record.

4 Using the Modify up arrow on the function generator, increase offset voltage in

1-mV increments until all activity indicators for pod 1 show the channels are at a logic high. Record the function generator voltage in the performance test record.

3–12

Testing Performance

To test the threshold accuracy

Test the − User threshold

1 Move the cursor to the field to the right of Pod 1. Type –6.00, then use the left and

right cursor control keys to highlight V. Press the Select key.

On the function generator front panel, enter −5.718 V ±1 mV DC offset. Use the multimeter to verify the voltage.

The activity indicators for pod 1 should show all data channels and the J-clock channel at a logic high.

Using the Modify down arrow on the function generator, decrease offset voltage in

1-mV increments until all activity indicators for pod 1 show the channels at a logic low. Record the function generator voltage in the performance test record.

4 Using the Modify up arrow on the function generator, increase offset voltage in

1-mV increments until all activity indicators show the channels at a logic high. Record the function generator voltage in the performance test record.

3–13

Testing Performance

To test the threshold accuracy

Test the + User threshold

1 Move the cursor to the field to the right of Pod 1. Type +6.00, then use the left and

right cursor control keys to highlight V. Press the Select key.

On the function generator front panel, enter +6.282 V ±1 mV DC offset. Use the multimeter to verify the voltage.

The activity indicators for pod 1 should show all data channels and the J-clock channel at a logic high.

Using the Modify down arrow on the function generator, decrease offset voltage in

1-mV increments until all activity indicators for pod 1 show the channels at a logic low. Record the function generator voltage in the performance test record.

4 Using the Modify up arrow on the function generator, increase offset voltage in

1-mV increments until all activity indicators for pod 1 show the channels at a logic high. Record the function generator voltage in the performance test record.

3–14

Testing Performance

To test the threshold accuracy

Test the 0 V User threshold

1 Move the cursor to the field to the right of Pod 1. Type 0, then press the Select key.

On the function generator front panel, enter +0.102 V ±1 mV DC offset. Use the multimeter to verify the voltage.

The activity indicators for pod 1 should show all data channels and the J-clock channel at a logic high.

Using the Modify down arrow on the function generator, decrease offset voltage in

1-mV increments until all activity indicators for pod 1 show the channels at a logic low. Record the function generator voltage in the performance test record.

4 Using the Modify up arrow on the function generator, increase offset voltage in

1-mV increments until all activity indicators for pod 1 show the channels at a logic high. Record the function generator voltage in the performance test record.

3–15

Testing Performance

To test the threshold accuracy

Test the next pod

1 Using the 17-by-2 test connector and probe tip assembly, connect the data and clock

channels of pod 2 to the output of the function generator.

Start with "Test the TTL threshold" on page 3−10, substituting pod 2 for pod 1.

3–16

To test the glitch capture

Testing the glitch capture verifies the performance of the following specification:

• Minimum detectable glitch.

This test checks the minimum detectable glitch on sixteen data channels at a time.

Equipment Required

Equipment Critical Specifications Recommended Model/Part

Pulse Generator 100 MHz 3.5 ns pulse width, < 600 ps rise time Agilent 8131A Option 020 Digitizing Oscilloscope

SMA Coax (Qty 3) Adapter (Qty 4) SMA(m)-BNC(f) Agilent 1250-1200 Coupler (Qty 4) BNC (m)(m) Agilent 1250-0216 BNC Test Connector, 6x2 (Qty 4)

≥ 6 GHz bandwidth , < 58 ps rise time 18 GHz bandwidth Agilent 8120-4948

Agilent 54121T

Set up the equipment

1 Turn on the equipment required and the logic analyzer. Let them warm up for

30 minutes before beginning the test if you have not already done so.

2 Set up the pulse generator.

Pulse Generator Setup

Channel 1 Channel 2 Period

Delay: 0 ps Delay : 0 ps 22.0 ns Width: 3.5 ns Width: 3.5 ns

High: −0.9 V High: −0.9 V Low: −1.7 V Low: −1.7 V

3–17

Testing Performance

To test the glitch capture

3 Set up the oscilloscope.

Oscilloscope Setup

Time Base Display Delta V Delta T

Time/Div: 1.00 ns/div mode: avg V markers on T markers on delay: 17.7000 ns # of avg: 16 marker 1 position: Chan 1 start on: Pos Edge 1

screens: dual marker 2 position: Chan 2 stop on: Pos Edge 1

Channel

Channel 1 Channel 2

Display

Probe Atten

Volts/Div

on on

20.00 20.00

400 mV 400 mV

Offset

−1.3000 V −1.3000 V

Set up the logic analyzer

1 Press the Config key. Assign all pod fields to Machine 1. To assign the pod fields,

select the pod fields, then select Machine 1 in the pop-up menu.

2 In the Analyzer 1 box, select the Type field. Select Timing in the pop-up menu.

Connect the logic analyzer

1 Using SMA cables, connect the oscilloscope to the pulse generator channel 1

Output, channel 2 Output, and Trig Output.

2 Using the 6-by-2 test connectors, connect the first combination of logic analyzer

clock and data channels listed in the table to the pulse generator.

You will repeat this test for the remaining combinations.

3–18

Connect the Logic Analyzer to the Pulse Generator

Testing Performance

To test the glitch capture

Testing Combinations

1 Pod 1

2 Pod 2

To Agilent 8131A Channel 1 Output

ch 0, 2, 4, 6, J-clock

ch 0, 2, 4, 6, K-clock

To 8131A Channel 1 Output

Pod 1 ch 1, 3, 5, 7

Pod 2 ch 1, 3, 5, 7

To 8131A Channel 2 Output

Pod 1 ch 8, 10, 12, 14

Pod 2 ch 8, 10, 12, 14

To 8131A Channel 2 Output

Pod 1 ch 9, 11, 13, 15

Pod 2 ch 9, 11, 13, 15

3–19

Testing Performance

To test the glitch capture

Test the glitch capture on the connected channels

1 Set up the Format menu.

a Press the Format key.

b Select the field to the right of the pod, then select ECL in the pop-up menu. Use the

arrow keys to access pods not shown on the screen (select the Pods field and push Select).

c Select Timing Acquisition Mode, then select Glitch Half Channel 125 MHz.

Turn on the channels that correspond to the channels being tested.

The channels being tested are the channels connected to the pulse generator in "Connect the logic analyzer."

a Select the pod field, then select one of the two pods in the pop-up. Move the cursor to

the channel assignment field of the pod and press the Clear entry key until all channels of the pod are assigned (all asterisks). Press the Done key.

b Turn on the clock/data channels that correspond to the clocks being tested. Turn off

the data channels and clock/data channels that are not being tested.

3–20

Testing Performance

To test the glitch capture

3 Set up the Trigger menu.

a Press the Trigger key.

b Select Modify Trigger, then Clear Trigger, then select All in the pop-up menus.

Using the Precision Edge Find in the Delta T menu of the oscilloscope, verify that the pulse widths of the pulse generator channels 1 and 2 are 3.450 ns, +50 ps or −100 ps. If necessary, adjust the pulse widths of the pulse generator channels 1 and 2.

5 Set up the Waveform menu to view all the channels.

a Select one of the Glitch labels, then select Delete All in the pop-up menu.

b Select All, then select continue.

c Press the Select key, then select Insert in the pop-up menu.

d Press the Select key, then select Sequential in the pop-up menu.

3–21

Testing Performance

To test the glitch capture

6 On the logic analyzer, press the Run key. The display should be similar to the figure

below.

7 On the pulse generator, enable Channel 1 and Channel 2 COMP (with the LED on). 8 On the logic analyzer, press the Run key. The display should be similar to the figure

below. Record Pass or Fail in the performance test record.

Test the next channels

• Return to "Connect the logic analyzer" on page 3–18 and connect and test the next

combination of data and clock channels until all pods are tested.

To access pod 2 in the Format menu, select pod 1 field, then select pod 2 in the pop-up menu.

3–22

To test the single-clock, single-edge, state acquisition

Testing the single-clock, single-edge, state acquisition verifies the performance of the following specifications:

• Minimum master to master clock time.

• Maximum state acquisition speed.

• Setup/Hold time for single-clock, single-edge, state acquisition.

• Minimum clock pulse width.

This test checks the data channels using a single-edge clock at three selected setup/hold times.

Equipment Required

Equipment Critical Specifications Recommended Model/Part

Pulse Generator 100 MHz 3.5 ns pulse width, < 600 ps rise time Agilent 8131A option 020 Digitizing Oscilloscope

Adapter SMA(m)-BNC(f) Agilent 1250-1200 SMA Coax Cable (Qty 3) 18 GHz bandwidth Agilent 8120-4948 BNC Cable BNC(m)(m) 48 in. >2 GHz bandwidth Agilent 8120-1840 Coupler BNC(m)(m) Agilent 1250-0216 BNC Test Connector, 6x2 (Qty 4)

≥ 6 GHz bandwidth, < 58 ps rise time

Agilent 54121T

Set up the equipment

1 Turn on the equipment required and the logic analyzer. Let them warm up for

30 minutes before beginning the test if you have not already done so.

2 Set up the pulse generator.

a Set up the pulse generator according to the following table.

Pulse Generator Setup

Channel 1 Channel 2 Period

Delay: 0 ps Doub: 20.0 ns 40 ns Width: 3.5 ns Width: 3.5 ns High: -0.9 V High: -0.9 V Low: -1.7 V Low: -1.7 V

b Disable the pulse generator channel 2 COMP (with the LED off).

3–23

Testing Performance

To test the single-clock, single-edge, state acquisition

3 Set up the oscilloscope.

Oscilloscope Setup

Time Base Display Delta V Delta T

Time/Div: 1.00 ns/div avg V markers on T markers on

# of avg: 16 marker 1 position: Chan 1 start on: Pos Edge 1 screen: dual marker 2 position: Chan 1 stop on: Neg Edge 1

Channel

Channel 1 Channel 2

Display

Probe Atten

on on

20.00 20.00

Offset

Volts/Div

−1.3 V −1.3 V 400 mV 400 mV

Set up the logic analyzer

1 Set up the Configuration menu.

a Press the Config key.

b In the Configuration menu, assign all pods to Machine 1. To assign the pods, select

the pod fields, then select Machine 1 in the pop-up menu.

c Select the Type field in the Analyzer 1 box, then select State.

3–24

Testing Performance

To test the single-clock, single-edge, state acquisition

2 Set up the Format menu.

a Press the Format key. Select State Acquisition Mode, then select Full Channel/4K

Memory/50MHz.

b Select the field to the right of each pod, then select ECL in the pop-up menu.

Set up the Trigger menu.

a Press the Trigger key. Select Modify Trigger, then Clear Trigger, then select All in the

pop-up menus.

b Select Count Off. Press Select again, then select Time in the pop-up menu. Select

Done to exit the menu.

c Select the field labeled 1 under the State Sequence Levels. Select the field labeled

"anystate," then select "no state." Select Done to exit the State Sequence Levels menu.

d Select the field next to "a," under the label Lab1. Type "000A", then press the Select

key.

3–25

Testing Performance

To test the single-clock, single-edge, state acquisition

Connect the logic analyzer

1 Using the 6-by-2 test connectors, connect the logic analyzer clock and data channels

listed in the following table to the pulse generator. Install a BNC cable between the pulse generator channel 2 output and the 6x2 test connector with the logic analyzer clock leads.

2 Using SMA cables, connect the oscilloscope to the pulse generator channel 1

Output, channel 2 Output, and Trig Output.

Connect the 1664A Logic Analyzer to the Pulse Generator

Testing Combination

1 Pod 1, channel 3

Connect to Agilent 8131A Channel 1 Output

Pod 2, channel 3

Connect to Agilent 8131A Channel 1 Output

Pod 1, channel 11 Pod 2, channel 11

Connect to Agilent 8131A Channel 2 Output

J-clock

3 Activate the data channels that are connected according to the previous table.

a Press the Format key.

b Select the field showing the channel assignments for one of the pods being tested,

then press the Clear entry key. Using the arrow keys, move the selector to the data channels to be tested, then press the Select key. An asterisk means that a channel is turned on. When all the correct channels of the pod are turned on, press the Done key. Follow this step for the remaining pods.

3–26

Testing Performance

To test the single-clock, single-edge, state acquisition

c Press the Trigger key. Make sure pattern term a is "A". If not, select the field next to

"a" under the label Lab1. Type "A", then press the Select key.

Verify the test signal

1 Check the clock pulse width. Using the oscilloscope, verify that the clock pulse

width is 3.50 ns, +0 ps or −100 ps.

a Enable the pulse generator channel 1 and channel 2 outputs.

b In the oscilloscope Timebase menu, select Delay. Using the oscilloscope knob,

position the clock waveform so that the waveform is centered on the screen.

c In the oscilloscope Delta V menu, set the Marker 1 Position to Chan 2, then set

Marker 1 at −1.3000 V. Set Marker 2 Position to Chan 2, then set Marker 2 at

−1.3000 V.

d In the oscilloscope Delta T menu, select Start On Pos Edge 1. Select Stop on Neg

Edge 1.

e If the pulse width is outside the limits, adjust the pulse generator channel 2 width and

select the oscilloscope Precision Edge Find until the pulse width is within limits.

Check the clock period. Using the oscilloscope, verify that the clock period is 20 ns,

+0 ps or −250 ps.

a In the oscilloscope Timebase menu, select Sweep Speed 4.00 ns/div.

b Select Delay. Using the oscilloscope knob, position the clock waveform so that a

rising edge appears at the left of the display.

3–27

Testing Performance

To test the single-clock, single-edge, state acquisition

c In the oscilloscope Measure menu, select Measure Chan 2, then select Period. If the

period is more than or equal to 20.000 ns, go to step 4. If the period is less than 20.000 ns but greater than 19.75 ns, go to step 3.

d In the oscilloscope Timebase menu, add 10 ns to the delay.

e In the oscilloscope Measure menu, select Period. If the period is more than or equal to

20.000 ns, decrease the pulse generator Chan 2 Doub in 100-ps increments until one of the two periods measured is less than 20.000 ns but greater than 19.75 ns.

Check the data pulse width. Using the oscilloscope, verify that the data pulse width

is 3.50 ns, +0 ps or −100 ps.

a Enable the pulse generator channel 1 and channel 2 outputs. Leave channel 2 output

disabled.

b In the oscilloscope Timebase menu, select Sweep Speed 1.00 ns/div.

c Select Delay. Using the oscilloscope knob, position the data waveform so that the

waveform is centered on the screen.

d In the oscilloscope Delta V menu, set the Marker 1 Position to Chan 1, then set Marker

1 at −1.3000 V. Set the Marker 2 Position to Chan 1, then set Marker 2 at −1.3000 V.

e In the oscilloscope Delta T menu, select Start On Pos Edge 1. Select Stop on Neg

Edge 1.

f Select Precision Edge Find.

g If the pulse width is outside the limits, adjust the pulse generator channel 1 width and

select the oscilloscope Precision Edge Find until the pulse width is within limits.

3–28

Testing Performance

To test the single-clock, single-edge, state acquisition

Check the setup/hold combination

1 Select the logic analyzer setup/hold time.

a In the logic analyzer Format menu, select Master Clock.

b Select the Setup/Hold field, then select the setup/hold combination to be tested for all

pods. The first time through this test, use the top combination in the following table.

Setup/Hold Combinations

3.5/0.0 ns

0.0/3.5 ns

1.5/2.0 ns

c Select Done to exit the setup/hold combinations.

Disable the pulse generator channel 2 COMP (with the LED off).

3 Using the Delay mode of the pulse generator channel 1, position the pulses

according to the setup time of the setup/hold combination selected, +0.0 ps or −100 ps.

a In the oscilloscope Delta V menu, set the Marker 1 Position to Chan 1, then set

Marker 1 at −1.3000 V. Set the Marker 2 Position to Chan 2, then set Marker 2 at

−1.3000 V.

b In the oscilloscope Delta T menu, select Start on Pos Edge 1. Select Stop on Pos

Edge 1.

3–29

Testing Performance

To test the single-clock, single-edge, state acquisition

c Adjust the pulse generator channel 1 Delay, then select Precision Edge Find in the

oscilloscope Delta T menu. Repeat this step until the pulses are aligned according to the setup time of the setup/hold combination selected, +0.0 ps or −100 ps.

Select the clock to be tested.

a In the Master Clock menu, select the clock field to be tested, then select the clock

edge as indicated in the table. The first time through this test, use the top clock and edge in the following table.

Clocks

J↑ K↑

b Connect the clock to be tested to the pulse generator channel 2 output.

c Select Done to exit the Master Clock menu.

3–30

Testing Performance

To test the single-clock, single-edge, state acquisition

5 Note: This step is only done the first time through the test, to create a Compare file.

For subsequent runs, go to step 6. Use the following to create a Compare file:

a Press Run. The display should show a checkerboard pattern of alternating As and 5s.

Verify the pattern by scrolling through the display.

b Press the List key. In the pop up menu, use the RPG knob to move the cursor to

Compare. Press Select.

c In the Compare menu, move the cursor to Copy Listing to Reference, then select

Execute in the pop-up menu and press the Select key.

d Move the cursor to Specify Stop Measurement and press the Select key. Press Select

again to turn on Compare. At the pop up menu, select Compare. Move the cursor to the Equal field and press the Select key. At the pop up menu, select Not Equal. Press Done.

e Move the cursor to the Reference Listing field and select. The field should toggle to

Difference Listing.

Press the blue shift key, then press the Run key. If 2 - 4 acquisitions are obtained

without the "Stop Condition Satisfied" message appearing, then the test passes. Press Stop to halt the acquisition. Record the Pass or Fail results in the performance test record.

7 Test the next clock.

a Press the Format key, then select Master Clock.

b Turn off and disconnect the clock just tested.

c Repeat steps 4, 6, and 7 for the next clock edge listed in the table in step 4, until all

listed clock edges have been tested.

Enable the pulse generator channel 2 COMP (with the LED on).

8 9 Check the clock pulse width.

a Enable the pulse generator channel 1 and channel 2 outputs.

b In the oscilloscope Timebase menu, select Delay. Using the oscilloscope knob,

position the clock waveform so that the waveform is centered on the screen.

c In the oscilloscope Delta V menu, set the Marker 1 Position to Chan 2, then set

Marker 1 at −1.3000 V. Set the Marker 2 Position to Chan 2, then set Marker 2 at

−1.3000 V.

d In the oscilloscope Delta T menu, select Start On Neg Edge 1. Select Stop on Pos

Edge 1.

e If the pulse width is outside the limits, adjust the pulse generator channel 2 width and

select the oscilloscope Precision Edge Find until the pulse width is within limits.

3–31

Testing Performance

To test the single-clock, single-edge, state acquisition

10 Using the Delay mode of the pulse generator channel 1, position the pulses

according to the setup/hold combination selected, +0.0 ps or −100 ps.

a In the oscilloscope Delta V menu, set the Marker 1 Position to Chan 1, then set

Marker 1 at −1.3000 V. Set the Marker 2 Position to Chan 2, then set Marker 2 at

−1.3000 V.

b In the oscilloscope Delta T menu, select Start on Pos Edge 1. Select Stop on Neg

Edge 1.

c Adjust the pulse generator channel 1 Delay, then select Precision Edge Find in the

oscilloscope Delta T menu. Repeat this step until the pulses are aligned according to the setup time of the setup/hold combination selected.

Select the clock to be tested.

a In the Master Clock menu, select the clock field to be tested, then select the clock

edge as indicated in the table. The first time through this test, use the top clock and edge.

Clocks

J↓ K↓

b Connect the clock to be tested to the pulse generator channel 2 output.

c Select Done to exit the Master Clock menu (see illustration).

3–32

Testing Performance

12 Press the blue shift key, then press the Run key. If 2 - 4 acquisitions are obtained

without the "Stop Condition Satisfied" message appearing, then the test passes. Press Stop to halt the acquisition. Record the Pass or Fail results in the performance test record.

13 Test the next clock.

a Press the Format key, then select Master Clock.

b Turn off and disconnect the clock just tested.

c Repeat steps 11, 12, and 13 for the next clock edge listed in the table in step 10, until

all listed clock edges have been tested.

Test the next setup/hold combination.

a In the logic analyzer Format menu, press Master Clock.

b Turn off and disconnect the clock just tested.

c Repeat steps 1 through 14 for the next setup/hold combination listed in step 1 on

page 3–29, until all listed setup/hold combinations have been tested.

When aligning the data and clock waveforms using the oscilloscope, align the waveforms according to the setup time of the setup/hold combination being tested, +0.0 ps or −100 ps.

3–33

To test the multiple-clock, multiple-edge, state acquisition

Testing the multiple-clock, multiple-edge, state acquisition verifies the performance of the following specifications:

• Minimum master to master clock time.

• Maximum state acquisition speed.

• Setup/Hold time for multiple-clock, multiple-edge, state acquisition.

• Minimum clock pulse width.

This test checks data using multiple clocks at three selected setup/hold times.

Equipment Required

Equipment Critical Specifications Recommended

Model/Part

Pulse Generator 100 MHz 3.5 ns pulse width, < 600 ps rise time Agilent 8131A option 020 Digitizing Oscilloscope

≥ 6 GHz bandwidth, < 58 ps rise time

Agilent 54121T

Set up the equipment

1 Turn on the equipment required and the logic analyzer. Let them warm up for

30 minutes before beginning the test if you have not already done so.

2 Set up the pulse generator.

a Set up the pulse generator according to the following table.

Pulse Generator Setup

Channel 1 Channel 2 Period

Delay: 0 ps Doub: 20.0 ns 40 ns Width: 4.5 ns Width: 3.5 ns

High: −0.9 V High: −0.9 V Low: −1.7 V Low: −1.7 V

b Disable the pulse generator channel 2 COMP (with the LED off).

3–34

To test the multiple-clock, multiple-edge, state acquisition

3 Set up the oscilloscope.

Oscilloscope Setup

Time Base Display Delta V Delta T

Time/Div: 1.00 ns/div avg V markers on T markers on

# of avg: 16 marker 1 position: Chan 1 start on: Pos Edge 1 screen: dual marker 2 position: Chan 1 stop on: Neg Edge 1

Channel

Channel 1 Channel 2

Display

Probe Atten

on on

20.00 20.00

Testing Performance

Offset

Volts/Div

−1.3 V −1.3 V 400 mV 400 mV

Set up the logic analyzer

1 Set up the Configuration menu.

a Press the Config key.

b Assign all pods to Machine 1. To assign pods, select the pod fields, then select

Machine 1.

c In the Analyzer 1 box, select the Type field, then select State.

3–35

Testing Performance

To test the multiple-clock, multiple-edge, state acquisition

2 Set up the Format menu.

a Press the Format key. Select State Acquisition Mode, then select Full Channel/4K

Memory/50MHz.

b Select the field to the right of each Pod field, then select ECL.

Set up the Trigger menu.

a Press the Trigger key. Select Clear Trigger, then select All.

b Select the Count Off field, then select Time in the pop-up menu. Select Done to exit

the menu.

c Select the field labeled 1 under the State Sequence Levels. Select the field labeled

"anystate", then select "no state." Select Done to exit the State Sequence Levels menu.

d Select the field next to the pattern recognizer "a," under the label Lab1. Type "000A" ,

then press Select.

3–36

Testing Performance

To test the multiple-clock, multiple-edge, state acquisition

Connect the logic analyzer

1 Using the 6-by-2 test connectors, connect the logic analyzer clock and data channels

listed in the following table to the pulse generator. Install a BNC cable between the pulse generator channel 2 output and the 6x2 test connector with the logic analyzer clock leads.

2 Using SMA cables, connect channel 1, channel 2, and trigger of the oscilloscope to

the pulse generator.

Connect the 1664A Logic Analyzer to the Pulse Generator

Testing Combination

1 Pod 1, channel 3

Connect to Agilent 8131A Channel 1 Output

Pod 2, channel 3

Connect to Agilent 8131A Channel 1

Pod 1, channel 11 Pod 2, channel 11

Output

Connect to Agilent 8131A Channel 2 Output

J-clock K-clock

3 Activate the data channels that are connected according to the previous table.

a Press the Format key.

b Select the field showing the channel assignments for one of the pods being tested.

Press the Clear entry key. Using the arrow keys, move the selector to the data channels to be tested, then press the Select key. An asterisk means that a channel is turned on. When all the correct channels of the pod are turned on, press the Done key. Follow this step for the remaining pods.

3–37

Testing Performance

To test the multiple-clock, multiple-edge, state acquisition

c Press the Trigger key. Make sure pattern term a is "A". If not, select the field next to

"a" under the label Lab1. Type "A" then press the Select key.

Verify the test signal

1 Check the clock pulse width. Using the oscilloscope, verify that the clock pulse

width is 3.50 ns, +0 ps or −100 ps.

a Enable the pulse generator channel 1 and channel 2 outputs (with the LED off).

b In the oscilloscope Timebase menu, select Delay. Using the oscilloscope knob,

position the clock waveform so that the waveform is centered on the screen.

c In the oscilloscope Delta V menu, set the Marker 1 Position to Chan 2, then set Marker

1 at −1.3000 V. Set the Marker 2 Position to Chan 2, then set Marker 2 at −1.3000 V.

d In the oscilloscope Delta T menu, select Start On Pos Edge 1. Select Stop On Neg

Edge 1.

e If the pulse width is outside of the limits, adjust the pulse generator channel 2 width

and select the oscilloscope Precision Edge Find until the pulse width is within limits.

Check the clock period. Using the oscilloscope verify that the clock period is 20 ns,

+0 ps or −250 ps.

a In the oscilloscope Timebase menu, select Sweep Speed 4.00 ns/div.

b Select Delay. Using the oscilloscope knob, position the clock waveform so that a

rising edge appears at the left of the display.

3–38

Testing Performance

To test the multiple-clock, multiple-edge, state acquisition

c In the oscilloscope Measure menu, select Measure Chan 2, then select Period. If the

period is more than or equal to 20.000 ns, go to step 4. If the period is less than 20.000 ns but greater than 19.75 ns, go to step 3.

d In the oscilloscope Timebase menu, add 10 ns to the Delay.

e In the oscilloscope Measure menu, select Period. If the period is more than or equal to

20.000 ns, decrease the pulse generator Chan 2 DOUB in 100 ps increments until one of the two periods measured is less than 20.000 ns but greater than 19.75 ns.

Check the data pulse width. Using the oscilloscope verify that the data pulse width

is 4.450 ns, +50 ps or −100 ps.

a In the oscilloscope Timebase menu, select Sweep Speed 1.00 ns/div.

b Select Delay. Using the oscilloscope knob, position the data waveform so that the

waveform is centered in the screen.

c In the oscilloscope Delta V menu, set the Marker 1 Position to Chan 1, then set Marker

1 at −1.3000 V. Set the Marker 2 Position to Chan 1, then set Marker 2 at −1.3000 V.

d In the oscilloscope Delta T menu, select Start On Pos Edge 1. Select Stop on Neg

Edge 1.

e If the pulse width is outside of the limits, adjust the pulse generator channel 1 width

and select the oscilloscope Precision Edge Find until the pulse width is within limits.

3–39

Testing Performance

To test the multiple-clock, multiple-edge, state acquisition

Check the setup/hold with single clock edges, multiple clocks

1 Select the logic analyzer setup/hold time.

a In the logic analyzer Format menu, select Master Clock.

b Select and activate any two clock edges.

c Select the Setup/Hold field and select the setup/hold to be tested for all pods. The first

time through this test, use the top combination in the following table.

Setup/Hold Combinations

4.5/0.0 ns

0.0/4.5 ns

2.0/2.5 ns

d Select Done to exit the setup/hold combinations.

Disable the pulse generator channel 2 COMP (with the LED off).

3 Using the Delay mode of the pulse generator channel 1, position the pulses

according to the setup time of the setup/hold combination selected, +0.0 ps or −100 ps.

a In the oscilloscope Delta V menu, set the Marker 1 Position to Chan 1, then set

Marker 1 at −1.3000 V. Set the Marker 2 Position to Chan 2, then set Marker 2 at

−1.3000 V.

b In the oscilloscope Delta T menu, select Start on Pos Edge 1. Select Stop on Pos

Edge 1.

3–40

Testing Performance

To test the multiple-clock, multiple-edge, state acquisition

c Adjust the pulse generator channel 1 Delay, then select Precision Edge Find in the

oscilloscope Delta T menu. Repeat this step until the pulses are aligned according to the setup time of the setup/hold combination selected, +0.0 ps or −100 ps.

Select the clocks to be tested.

Select the clock field to be tested and then select J↑ + K↑ as the clock edges.

b Select Done to exit the Master Clock menu.

3–41

Testing Performance

To test the multiple-clock, multiple-edge, state acquisition

55 If you have not already created a Compare file for the previous test (single-clock,

single-edge state acquisition, page 3-31), use the following steps to create one. For subsequent passes through this test, skip this step and go to step 6.

a Press Run. The display should show a checkerboard pattern of alternating As and 5s.

Verify the pattern by scrolling through the display.

b Press the List key. In the pop up menu, use the RPG knob to move the cursor to

Compare. Press Select.

c In the Compare menu, move the cursor to Copy Listing to Reference, then select

Execute from the pop-up menu and press the Select key.

d Move the cursor to Specify Stop Measurement and press the Select key. Press Select

again to turn on Compare. At the pop up menu, select Compare. Move the cursor to the Equal field and press the Select key. At the pop up menu, select Not Equal. Press Done.

e Move the cursor to the Reference Listing field and select. The field should toggle to

Difference Listing.

Press the blue shift key, then press the Run key. If 2 - 4 acquisitions are obtained

without the "Stop Condition Satisfied" message appearing, then the test passes. Press Stop to halt the acquisition. Record the Pass or Fail results in the performance test record.

7 Enable the pulse generator channel 2 COMP (with the LED on). 8 Check the clock pulse width.

a Enable the pulse generator channel 1 and channel 2 outputs (with the LED off).

bb In the oscilloscope Timebase menu, select Delay. Using the oscilloscope knob,

position the clock waveform so that the waveform is centered on the screen.

c In the oscilloscope Delta V menu, set the Marker 1 Position to Chan 2, then set

Marker 1 at −1.3000 V. Set the Marker 2 Position to Chan 2, then set Marker 2 at

−1.3000 V.

d In the oscilloscope Delta T menu, select Start On Neg Edge 1. Select Stop On Pos

Edge 1.

e If the pulse width is outside of the limits, adjust the pulse generator channel 2 width

and select the oscilloscope Precision Edge Find until the pulse width is within limits.

3–42

Testing Performance

To test the multiple-clock, multiple-edge, state acquisition

9 Using the Delay mode of the pulse generator channel 1, position the pulses

according to the setup time of the setup/hold combination selected, +0.0 ps or −100 ps.

a In the oscilloscope Delta V menu, set the Marker 1 Position to Chan 1, then set

Marker 1 at −1.3000 V. Set the Marker 2 Position to Chan 2, then set Marker 2 at

−1.3000 V.

b In the oscilloscope Delta T menu, select Start On Pos Edge 1. Select Stop on Neg

Edge 1.

c Adjust the pulse generator channel 1 Delay, then select Precision Edge Find in the

oscilloscope Delta T menu. Repeat this step until the pulses are aligned according to the setup time of the setup/hold combination selected, +0.0 ps or −100 ps.

Select the clocks to be tested.

Select the clock field to be tested, then select J↓ + K↓ as the clock edges.

b Select Done to exit the Master Clock menu.

3–43

Testing Performance

To test the multiple-clock, multiple-edge, state acquisition

11 Press the blue shift key, then press the Run key. If 2 - 4 acquisitions are obtained

without the "Stop Condition Satisfied" message appearing, then the test passes. Press Stop to halt the acquisition. Record the Pass or Fail results in the performance test record.

12 Test the next setup/hold combination.

a In the logic analyzer Format menu, select Master Clock.

b Turn off and disconnect the clocks just tested.

c Repeat steps 1 through 12 for the next setup/hold combination listed in step 1 on

page 3-40, until all listed setup/hold combinations have been tested.

When aligning the data and clock waveforms using the oscilloscope, align the waveforms according to the setup time of the setup/hold combination being tested, +0.0 ps or −100 ps.

hen continue through the complete test.

3–44

To test the single-clock, multiple-edge, state acquisition

Testing the single-clock, multiple-edge, state acquisition verifies the performance of the following specifications:

• Minimum master to master clock time.

• Maximum state acquisition speed.

• Setup/Hold time for single-clock, multiple-edge, state acquisition.

This test checks data channels using a multiple-edge single clock at three selected setup/hold times.

Equipment Required

Equipment Critical Specifications Recommended

Model/Part

Pulse Generator 100 MHz 3.5 ns pulse width, < 600 ps rise time Agilent 8131A option 020 Digitizing Oscilloscope

≥ 6 GHz bandwidth, < 58 ps rise time

Agilent 54121T

Set up the equipment

1 Turn on the equipment required and the logic analyzer. Let them warm up for

30 minutes before beginning the test if you have not already done so.

2 Set up the pulse generator according to the following table.

Pulse Generator Setup

Channel 1 Channel 2 Period

Doub: 0 ps Delay: 0 ps 40 ns Width: 4.0 ns Dcyc: 50%

High: −0.9 V High: −0.9 V Low: −1.7 V Low: −1.7 V

COMP: Disabled (LED off)

3–45

Testing Performance

To test the single-clock, multiple-edge, state acquisition

3 Set up the oscilloscope.

Oscilloscope Setup

Time Base Display Delta V Delta T

Time/Div: 1.00 ns/div avg V markers on T markers on

# of avg: 16 marker 1 position: Chan 1 start on: Neg Edge 1 screen: dual marker 2 position: Chan 1 stop on: Neg Edge 2

Channel

Channel 1 Channel 2

Display

Probe Atten

on on

20.00 20.00

Offset

Volts/Div

−1.3 V −1.3 V 400 mV 400 mV

Set up the logic analyzer

1 Set up the Configuration menu.

a Press the Config key.

b Assign all pods to Machine 1. To assign all pods, select the pod fields, then select

Machine 1.

c Select the Type field in the Analyzer 1 box, then select State.

3–46

Testing Performance

To test the single-clock, multiple-edge, state acquisition

2 Set up the Format menu.

a Press the Format key. Select State Acquisition Mode, then select Full Channel/4K

Memory/50MHz.

b Select the field to the right of each pod field, then select ECL.

Set up the Trigger menu.

a Press the Trigger key. Select Clear Trigger, then select All.

b Select the Count Off field, then select Time in the pop-up menu. Select Done to exit

the menu.

c Select the field labeled 1 under the State Sequence Levels. Select the field labeled

"anystate", then select "no state." Select Done to exit the State Sequence Levels menu.

d Select the field next to the pattern recognizer "a," under the label Lab1. Type "000A" ,

then press Select.

3–47

Testing Performance

To test the single-clock, multiple-edge, state acquisition

Connect the logic analyzer

11 Using the 6-by-2 test connectors, connect the logic analyzer clock and data channels

listed in the following table to the pulse generator. Install a BNC cable between the pulse generator channel 2 output and the 6x2 test connector with the logic analyzer clock leads.

2 Using SMA cables, connect channel 1, channel 2, and trigger of the oscilloscope to

the pulse generator.

Connect the 1664A Logic Analyzer to the Pulse Generator

Testing Combination

1 Pod 1, channel 3

Connect to Agilent 8131A Channel 1 Output

Pod 2, channel 3

Connect to Agilent 8131A Channel 1

Pod 1, channel 11 Pod 2, channel 11

Output

Connect to Agilent 8131A Channel 2 Output

J-clock

3 Activate the data channels that are connected according to the previous tables.

a Press the Format key.

b Select the field showing the channel assignments for one of the pods being tested.

3–48

Testing Performance

To test the single-clock, multiple-edge, state acquisition

c Press the Trigger key. Make sure pattern term a is "A". If not, select the field next to

"a" under the label Lab1. Type "A" then press the Select key.

Verify the test signal

1 Check the clock period. Using the oscilloscope, verify that the clock period is 20 ns,

+0 ps or −250 ps.

a In the oscilloscope Timebase menu, select Sweep Speed 4.00 ns/div.

b Select Delay. Using the oscilloscope knob, position the clock waveform (Channel 2)

so that a rising edge appears at the left of the display.

c In the oscilloscope Measure menu, select Measure Chan 2, then select +Width. If the

positive-going pulse width is more than 20.000 ns, go to step d. If the pulse width is less than or equal to 20.000 ns, go to step 2.

d In the oscilloscope Measure menu, select -Width. If the negative-going pulse width is

less than or equal to 20.000 ns but greater than 19.75 ns, go to step 2.

e Decrease the pulse generator Period in 100 ps increments until the oscilloscope

Measure +Width or Measure -Width reads less than or equal to 20.000 ns, but greater than 19.75 ns.

3–49

Testing Performance

To test the single-clock, multiple-edge, state acquisition

2 Check the data pulse width. Using the oscilloscope, verify that the data pulse width

is 4.000 ns, +0 ps or −100 ps.

a In the oscilloscope Timebase menu, select Sweep Speed 1.00 ns/div.

b Select Delay. Using the oscilloscope knob, position the data waveform (Channel 1) so

that the waveform is centered on the screen.

c In the oscilloscope Delta V menu, set the Marker 1 Position to Chan 1, then set Marker

1 at −1.3000 V. Set the Marker 2 Position to Chan 1, then set Marker 2 at −1.3000 V.

d In the oscilloscope Delta T menu, select Start On Pos Edge 1. Select Stop on Neg

Edge 1. Select Precision Edge Find.

e If the pulse width is outside of the limits, adjust the pulse generator channel 1 width

and select the oscilloscope Precision Edge Find until the pulse width is within limits.

3–50

NOTE

Testing Performance

To test the single-clock, multiple-edge, state acquisition

Check the setup/hold combination

1 Select the logic analyzer setup/hold time.

a In the logic analyzer Format menu, select Master Clock.

The first time through this test, assign the clocks according to the first testing combination in step 3 of these procedures.

b In the Master Clock menu, select Setup/Hold.

c In the Setup/Hold menu, select the setup/hold field, then select for all pods the

setup/hold combination to be tested. The first time through this test, use the top combination in the following table.

Setup/Hold Combinations

4.0/0.0 ns

0.0/4.0 ns

2.0/2.0 ns

d Select Done to exit the setup/hold combinations.

Using the Delay mode of the pulse generator Channel 2, position the pulses according to the setup time of the setup/hold combination selected, +0.0 ps or

-100.0 ps.

a In the oscilloscope Delta V menu, set the Marker 1 Position to Chan 1, then set Marker

1 at -1.3000 V. Set the Marker 2 Position to Chan 2, then set Marker 2 at -1.3000 V.

b In the oscilloscope Delta T menu, select Start on Pos Edge 1. Select Stop on Pos

Edge 1. Select Precision Edge Find.

3–51

NOTE

Testing Performance

To test the single-clock, multiple-edge, state acquisition

c Adjust the pulse generator channel 2 Delay, then select Precision Edge Find in the

oscilloscope Delta T menu. Repeat this step until the pulses are aligned according to the setup time of the setup/hold combination selected, +0.0 ps or −100 ps.

If the rising clock edge does not appear on the oscilloscope display, then add 20.0 ns to the oscilloscope Timebase Delay.

Select the clock to be tested.

a In the Master Clock menu, select the clock field to be tested, then select the clock

edge as indicated in the table. The first time through this test, use the top clock and edge in the following table.

Clocks

J↕ K↕

b Select Done to exit the Master Clock menu.

If a Compare file was not created during the single-clock, single-edge test, then the

first time through this test, create a Compare file.

a Press Run. The display should show a checkerboard pattern of alternating A and 5.

Scroll through the display to verify.

b Press the List key. In the pop up menu, use the RPG knob to move the cursor to

Compare. Press Select.

c In the Compare menu, move the cursor to Copy Listing to Reference, then press the

Select key.

d Move the cursor to Specify Stop Measurement and press the Select key. Press Select

again to turn on Compare. At the pop up menu, select Compare. Move the cursor to the Equal field and press the Select key. At the pop up menu, select Not Equal. Press Done.

e Move the cursor to the Reference Listing field and select. The field should toggle to

Difference Listing.

Press the blue shift key, then press the Run key. If 2 - 4 acquisitions are obtained

without the "Stop Condition Satisfied" message appearing, then the test passes. Press Stop to halt the acquisition. Record the Pass or Fail results in the performance test record.

3–52

Testing Performance

To test the single-clock, multiple-edge, state acquisition

6 Test the next clock.

a Press the Format key, then select Master Clock.

b Turn off and disconnect the clock just tested.

c Repeat steps 3 and 5 for the next clock listed in the table in step 3, until all listed clock

edges have been tested.

Test the next setup/hold combination. a Press the Format key, then select Master

Clock and turn off the clock just tested. b Repeat steps 1 through 7 for the next setup/hold combination listed in step 1, until all listed setup/hold combinations have been tested.

When aligning the data and clock waveforms using the oscilloscope, align the waveforms according to the setup time of the setup/hold combination being tested, +0.0 ps or -100.0 ps.

3–53

To test the time interval accuracy

Testing the time interval accuracy does not check a specification, but does check the following:

• 125 MHz oscillator

This test verifies that the 125 MHz timing acquisition synchronizing oscillator is operating within limits.

Equipment Required

Equipment Critical Specifications Recommended

Model/Part

Pulse Generator 100 MHz 3.5 ns pulse width, < 600 ps rise time Agilent 8131A Option 020 Function Generator

SMA Cable Agilent 8120-4948 Adapter BNC(m)-SMA(f) Agilent 1250-2015 BNC Test Connector,

6x2

Accuracy ≤ (5)(10

−6

) × frequency

Agilent 3325B Option 002

Set up the equipment

1 Turn on the equipment required and the logic analyzer. Let them warm up for

30 minutes if you have not already done so.

2 Set up the pulse generator according to the following table.

Pulse Generator Setup

Channel 1 Period Mode EXT TRIG

Delay: 0 ps 5 us TRIG Slope: Positive Width: 2.5 us THRE: 1.0 V

High: −0.9 V Low: −1.7 V

COMP: Disabled (LED off)

3–54

Testing Performance

To test the time interval accuracy

3 Set up the function generator according to the following table.

Function Generator Setup

Freq: 200 000 . 0 Hz Main Function: Square wave Amptd: 3.000 V High Voltage: Disabled (LED Off) Phase: 0.0 deg DC Offset: 0.0 V

Set up the logic analyzer

1 Set up the Configuration menu.

a Press the Config key.

b In the Configuration menu, assign Pod 1 to Machine 1. To assign Pod 1, select the

Pod 1 field, then select Machine 1.

c In the Analyzer 1 box, select the Type field, then select Timing.

3–55

Testing Performance

To test the time interval accuracy

2 Set up the Format menu.

a Press the Format key. Select Timing Acquisition Mode, then select Transitional Full

Channel 125 MHz.

b Select the field to the right of the Pod 1 field, then select ECL.

c Select the field showing the channel assignments for Pod 1. Deactivate all channels by

pressing the Clear entry key. Using the arrow keys, move the selector to Channel 0. Press the Select key to put an asterisk in the channel position, activating the channel, then press the Done key.

Press the Trigger key. Select Modify Trigger, then Clear Trigger and All from the

pop-up menus.

3–56

To test the time interval accuracy

4 Set up the Waveform menu.

a Press the Waveform key.

Move the cursor to the sec/Div field, then use the RPG knob to dial in 2.00 µs.

c Select the Markers Off field, then select Pattern.

d Select the Specify Patterns field. Select X entering 1 and O entering 1.

Testing Performance

e Select Done to exit the Specify Patterns menu.

f Move the cursor to the X-pat field. Type 1, then press Done.

g Move the cursor to the O-pat field. Type 20, then press Done.

h Select the Markers Patterns field, then select Statistics. Select Reset Statistics to

initialize the statistics fields.

Connect the logic analyzer

1 Using a 6-by-2 test connector, connect channel 0 of Pod 1 to the pulse generator

channel 1 output.

2 Using the SMA cable and the BNC adapter, connect the External Input of the pulse

generator to the Main Signal of the function generator.

3–57

Testing Performance

To test the time interval accuracy

Acquire the data

1 Enable the pulse generator channel 1 output (with the LED off). 2 Press the blue key, then press the Run key to select Run-Repetitive. Allow the logic

analyzer to acquire data for at least 100 valid runs as indicated in the pattern statistics field.

3 When the logic analyzer has acquired at least 100 valid runs, touch Stop. The

Min X-O field in the logic analyzer Pattern Statistics menu should read

94.99–95.00 µs. The Max X-O field should read 95.00–95.01 µs. The Avg X-O field should read 94.99–95.01 µs. Record the results in the performance test record.

3–58

Performance Test Record

1664A Logic Analyzer_______

Serial No.______________________ Work Order No.___________________

Recommended Test Interval - 2 Year/4000 hours Date___________________

Recommended next testing___________________ Temperature___________________

Test Settings Results

Self-Tests

Threshold Accuracy

Pod 1

Pod 2

Glitch Capture

± (100 mV + 3% of threshold setting)

TTL, ±145 mV

ECL, ±139 mV

-User, ±280 mV

+User, ±280 mV

0 V, ±100 mV

TTL, ±145 mV

ECL, ±139 mV

-User, ±280 mV

+User, ±280 mV

0 V, ±100 mV Minimum Detectable

Glitch 3.5 ns

Pass/Fail ________

Limits Measured

TTL VL TTL VH ECL VL ECL VH

-User VL

- User VH + User VL + User VH 0 V User VL 0 V User VH

TTL VL TTL VH ECL VL ECL VH

-User VL

- User VH + User VL + User VH 0 V User VL 0 V User VH

Pod 1 ________ Pod 2 ________

+1.355 V +1.645 V

-1.439 V

-1.161 V

-6.280 V

-5.720 V +5.720 V +6.280 V

-100 mV +100 mV

+1.355 V +1.645 V

-1.439 V

-1.161 V

-6.280 V

-5.720 V +5.720 V +6.280 V

-100 mV +100 mV

________ ________ ________ ________ ________ ________ ________ ________ ________ ________

Pass/Fail

3–59

Performance Test Record (continued)

Test Settings Results

Single-Clock, Single-Edge Acquisition

Multiple-Clock, Multiple-Edge Acquisition

Single-Clock, Multiple-Edge Acquisition

Setup/Hold Time 3.5/0.0 ns

Setup/Hold Time 0.0/3.5 ns

Setup/Hold Time 1.5/2.5 ns

Setup/Hold Time 4.5/0.0 ns

Setup/Hold Time 0.0/4.5 ns

Setup/Hold Time 2.0/2.5 ns

J↑ K↑

J↑ + K↑

Pass/Fail Pass/Fail

________ ________

Pass/Fail Pass/Fail ________

________

J↓ K↓

JÅ + K↓

JÅ + K↓ ________

________ ________

________

Time Interval Accuracy

Setup/Hold Time 4.0/0.0 ns

Setup/Hold Time 0.0/4.0 ns

Setup/Hold Time 2.0/2.0 ns

min X-0

max X-0

avg X-0

94.99-95.00 µs

95.00-95.01 µs

94.99-95.01 µs

J↕ K↕

Pass/Fail _______

_______

_______ _______

Measured

_________

3–60

Logic analyzer calibration 4-2 To adjust the CRT monitor alignment 4-3 To adjust the CRT intensity 4-5

Calibrating and Adjusting

This chapter gives you instructions for calibrating and adjusting the logic analyzer.

Adjustments to the logic analyzer include adjusting the CRT monitor assembly.

To periodically verify the performance of the analyzer, refer to "Testing Performance" in chapter 3.

Logic analyzer calibration

The logic analyzer circuitry of the 1664A Logic Analyzer does not require an operational accuracy calibration. To test the logic analyzer circuitry against specifications (full calibration), refer to chapter 3, Testing Performance.

Set up the equipment

Turn on the logic analyzer. Let it warm up for 30 minutes if you have not already done so.

4–2

To adjust the CRT monitor alignment

WARNING

Do not touch the CRT monitor sweep board. High voltages exist on the sweep board that can cause personal injury.

Equipment Required

Equipment Critical Specification Recommended

Model/Part

Alignment Tool 1 8710-1300

11 Turn off the logic analyzer, then disconnect the power cord. Remove the cover.

Refer to chapter 6, "Replacing Assemblies," for instructions to remove the cover.

2 Connect the power cord, insert the operating system disk into the disk drive, then

turn on the logic analyzer.

3 Insert the disk containing the functional performance verification tests (normally

the same disk) into the disk drive, then load the functional performance verification operating system into the logic analyzer (refer to Chapter 3, To Perform Self Tests).

4–3

Calibrating and Adjusting

To adjust the CRT monitor alignment

4 Enter the Sys PV tests, then enter the Display Test.

A grid pattern should appear.

If the display is tilted (rotated), adjust the CRT yoke by rotating it to straighten the display.

Yoke

6 If the grid pattern is not centered horizontally, adjust the H-Hold. 7 If you need to adjust the intensity, go to the next page.

If you are finished with the adjustments, turn off the instrument, then remove the power cord. Install the cover on the instrument.

4–4

To adjust the CRT intensity

WARNING

Do not touch the CRT monitor sweep board. High voltages exist on the sweep board that can cause personal injury.

Equipment Required

Equipment Critical Specification Recommended

Model/Part

Alignment Tool 1 8710-1300 Light Power Meter United Detector 351

1 Turn off the logic analyzer, then disconnect the power cord. Remove the cover.

Refer to chapter 6, "Replacing Assemblies," for instructions to remove the cover.

2 Connect the power cord, insert the operating system disk, then turn on the logic

analyzer.

3 Access the Display Test.

If you just finished adjusting the CRT monitor alignment, go to step 4.

•

To Access the Display Test, perform the following steps.

•

a Insert the disk containing the functional performance verification tests (normally the

same disk) into the disk drive, then load the functional performance verification operating system into the logic analyzer (refer to Chapter 3, To Perform The Self Tests).

b Enter the Sys PV tests and enter the Display Test. A grid pattern should appear.

Press the front panel Select key.

The display should show a full bright test screen.

5 Turn the rear panel intensity adjustment to full bright. 6 Place the light power meter against the display at center screen.

4–5

Calibrating and Adjusting

To adjust the CRT intensity

WARNING

Do not touch the CRT monitor sweep board. High voltages exist on the sweep board that can cause personal injury.

The light power meter should read 137-154 cd/m2. If the measurement is out of this range, use the adjustment tool to adjust the Contrast potentiometer on the monitor driver board.

8 Press the front panel Select key.

The display should show a half bright test screen.

Place the light power meter against the display at center screen. The light power

meter should read 5-27 cd/m

If the reading is not correct, try adjusting the contrast in step 7 closer to the limit.

10 Press the front panel Select key.

The logic analyzer should exit the Display Test.

11 Place the light power meter against the display at center screen. Adjust the rear

panel intensity adjustment until the light power meter reads 45-55 cd/m

12 Exit the functional performance verification tests. 13 Turn off the instrument, then remove the power cord. Install the cover on the

instrument.

4–6

To use the flowcharts 5-2 To check the power-up tests 5-15 To run the self-tests 5-16 To test the power supply voltages 5-21 To test the CRT monitor signals 5-23 To test the keyboard signals 5-24 To test the disk drive voltages 5-25 To perform the BNC test 5-27 To test the logic analyzer probe cables 5-28 To test the auxiliary power 5-32

Troubleshooting

This chapter helps you troubleshoot the logic analyzer to find defective assemblies. The troubleshooting consists of flowcharts, self-test instructions, and tests. This information is not intended for component-level repair.

If you suspect a problem, start at the top of the first flowchart. During the troubleshooting instructions, the flowcharts will direct you to perform other tests.

The service strategy for this instrument is the replacement of defective assemblies. This instrument can be returned to Agilent Technologies for all service work, including troubleshooting. Contact your nearest Agilent Technologies Sales Office for more details.

CAUTION

Electrostatic discharge can damage electronic components. Use grounded wriststraps and mats when you perform any service to this instrument or to the cards in it.

To use the flowcharts

Flowcharts are the primary tool used to isolate defective assemblies. The flowcharts refer to other tests to help isolate the trouble. The circled letters on the charts indicate connections with the other flowcharts. Start your troubleshooting at the top of the first flowchart.

5–2

Troubleshooting

To use the flowcharts

Troubleshooting Flowchart 1

5–3

Troubleshooting

To use the flowcharts

Troubleshooting Flowchart 2

5–4

Troubleshooting

To use the flowcharts

Troubleshooting Flowchart 3

5–5

Troubleshooting

To use the flowcharts

Troubleshooting Flowchart 4

5–6

Troubleshooting

To use the flowcharts

Troubleshooting Flowchart 5

5–7

Troubleshooting

To use the flowcharts

Troubleshooting Flowchart 6

5–8

Troubleshooting

To use the flowcharts

Troubleshooting Flowchart 7

5–9

Troubleshooting

To use the flowcharts

Troubleshooting Flowchart 8

5–10

Troubleshooting

To use the flowcharts

Troubleshooting Flowchart 9

5–11

Troubleshooting

To use the flowcharts

Troubleshooting Flowchart 10

5–12

Agilent Technologies 01664-97005 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Agilent Technologies 1664A Logic Analyzer

In This Book

Table of Contents

General Information

Accessories

Specifications

Characteristics

Supplemental Characteristics

Recommended Test Equipment

Preparing For Use

To inspect the logic analyzer

Ferrites

To apply power

To operate the user interface

To set the line voltage

To degauss the display

To clean the logic analyzer

To test the logic analyzer

Testing Performance

To perform the self-tests

To make the test connectors

To test the threshold accuracy

To test the glitch capture

To test the single-clock, single-edge, state acquisition

To test the multiple-clock, multiple-edge, state acquisition

To test the single-clock, multiple-edge, state acquisition

To test the time interval accuracy

Performance Test Record

Calibrating and Adjusting

Logic analyzer calibration

Set up the equipment

To adjust the CRT monitor alignment

To adjust the CRT intensity

Troubleshooting

To use the flowcharts