Agilent HCPL-3180 User Guide

Functional Diagram

N/C

ANODE

CATHODE

N/C

1

2

3

4

SHIELD

V

8

CC

V

7

O

6

V

O

V

5

EE

Description

This family of devices consists of a GaAsP LED. The LED is optically coupled to an integrated circuit with a power stage. These optocouplers are ideally suited for

Agilent HCPL-3180

2.0 Amp Output Current High Speed Gate Drive Optocoupler

Data Sheet

Features

• 2.0 A minimum peak output current

• 250 kHz maximum switching speed

• High speed response:

• 10 kV/µs minimum Common Mode

• Under Voltage Lock-Out protection

• Wide operating temperature range:

• Wide VCC operating range:

• 20 ns typical pulse width distortion

high frequency driving of power IGBTs and MOSFETs used in Plasma Display Panels, high performance DC/DC converters, and motor control inverter applications.

• Safety approvals:

200 ns maximum propagation delay over temperature range

Rejection (CMR) at V

= 1500 V

CM

(UVLO) with hysteresis

–40°C to 100°C

10 V to 20 V

– UL approval, 3750 V

rms

for 1 minute – CSA approval – IEC/EN/DIN EN 60747-5-2 approval

Applications

• Plasma Display Panel (PDP)

• Distributed Power Architecture (DPA)

• Switch Mode Rectifier (SMR)

• High performance DC/DC converter

• High performance Switching Power Supply (SPS)

• High performance Uninterruptible Power Supply (UPS)

• Isolated IGBT/Power MOSFET gate drive

A 0.1 µF bypass capacitor must be connected between pins VCC and Ground.

CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to

prevent damage and/or degradation, which may be induced by ESD.

Ordering Information

Specify part number followed by option number (if desired).

Example:

HCPL-3180-XXXX

No option = Standard DIP package, 50 per tube.

300 = Gull Wing Surface Mount Option, 50 per tube.

500 = Tape and Reel Packaging Option, 1000 per reel.

Package Outline Drawings HCPL-3180 Standard DIP Package

9.65 ± 0.25

(0.380 ± 0.010)

TYPE NUMBER

A XXXXZ

YYWW

1.19 (0.047) MAX.

060 = IEC/EN/DIN EN 60747-5-2, V

XXXE = Lead Free Option.

7.62 ± 0.25

5678

OPTION CODE* DATE CODE

4321

1.78 (0.070) MAX.

(0.300 ± 0.010)

6.35 ± 0.25

(0.250 ± 0.010)

IORM

= 630 V

PEAK

.

2

3.56 ± 0.13

(0.140 ± 0.005)

1.080 ± 0.320

(0.043 ± 0.013)

4.70 (0.185) MAX.

2.92 (0.115) MIN.

0.65 (0.025) MAX.

2.54 ± 0.25

(0.100 ± 0.010)

0.51 (0.020) MIN.

+ 0.076

5° TYP.

DIMENSIONS IN MILLIMETERS AND (INCHES). * MARKING CODE LETTER FOR OPTION NUMBERS

"V" = OPTION 060 OPTION NUMBERS 300 AND 500 NOT MARKED.

NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.

0.254

(0.010

- 0.051

+ 0.003)

- 0.002)

HCPL-3180 Gull Wing Surface Mount Option 300

9.65 ± 0.25

(0.380 ± 0.010)

6

7

8

5

LAND PATTERN RECOMMENDATION

1.016 (0.040)

1.19

(0.047)

MAX.

1.080 ± 0.320

(0.043 ± 0.013)

6.350 ± 0.25

(0.250 ± 0.010)

1

(0.100)

2.54 BSC

3

2

4

1.780

(0.070)

MAX.

3.56 ± 0.13

(0.140 ± 0.005)

(0.025 ± 0.005)

0.635 ± 0.130

DIMENSIONS IN MILLIMETERS (INCHES). LEAD COPLANARITY = 0.10 mm (0.004 INCHES).

NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.

1.27 (0.050)

9.65 ± 0.25

(0.380 ± 0.010)

7.62 ± 0.25

(0.300 ± 0.010)

0.635 ± 0.25

(0.025 ± 0.010)

10.9 (0.430)

2.0 (0.080)

0.254

(0.010

12° NOM.

+ 0.076

- 0.051

+ 0.003)

- 0.002)

Solder Reflow Temperature Profile

300

PREHEATING RATE 3°C + 1°C/–0.5°C/SEC. REFLOW HEATING RATE 2.5°C ± 0.5°C/SEC.

200

160°C 150°C 140°C

3°C + 1°C/–0.5°C

100

TEMPERATURE (°C)

ROOM

TEMPERATURE

0

50 150100 200 250

2.5°C ± 0.5°C/SEC.

PREHEATING TIME 150°C, 90 + 30 SEC.

TIME (SECONDS)

PEAK

TEMP.

245°C

30

SEC.

30

SOLDERING

TIME

200°C

50 SEC.

PEAK TEMP. 240°C

PEAK

TEMP.

230°C

TIGHT TYPICAL LOOSE

3

Recommended Pb-Free IR Profile

T

p

217 °C

T

L

150 - 200 °C

T

smax

T

smin

TEMPERATURE

25

NOTES: THE TIME FROM 25 °C to PEAK TEMPERATURE = 8 MINUTES MAX. T

= 200 °C, T

smax

smin

260 +0/-5 °C

RAMP-UP

3 °C/SEC. MAX.

t

s

PREHEAT

60 to 180 SEC.

t 25 °C to PEAK

= 150 °C

TIME

TIME WITHIN 5 °C of ACTUAL PEAK TEMPERATURE

t

p

20-40 SEC.

RAMP-DOWN 6 °C/SEC. MAX.

t

L

60 to 150 SEC.

Regulatory Information

The HCPL-3180 has been approved by the following organizations:

IEC/EN/DIN EN 60747-5-2

Approved under: IEC 60747-5-2:1997 + A1:2002 EN 60747-5-2:2001 + A1:2002 DIN EN 60747-5-2 (VDE 0884 Teil 2):2003-01 (Option 060 only)

UL

Approval under UL 1577, component recognition program up to V

= 3750 V

ISO

rms

. File

E55361.

CSA

Approval under CSA Component Acceptance Notice #5, File CA

88324.

IEC/EN/DIN EN 60747-5-2 Insulation Characteristics (HCPL-3180 Option 060)

Description Symbol HCPL-3180 Unit

Installation classification per DIN EN 0110 1997-04 for rated mains voltage ≤ 150 V for rated mains voltage ≤ 300 V for rated mains voltage ≤ 600 V

rms rms rms

Climatic Classification 55/100/21 Pollution Degree (DIN EN 0110 1997-04) 2 Maximum Working Insulation Voltage V

IORM

Input to Output Test Voltage, Method b* V

x 1.875=VPR, 100% Production Test with V

IORM

PR

tm=1 sec, Partial Discharge < 5 pC Input to Output Test Voltage, Method a*

V

x 1.5=VPR, Type and Sample Test, tm=60 sec, V

IORM

PR

Partial Discharge < 5 pC

Highest Allowable Overvoltage V (Transient Overvoltage t

= 10 sec)

ini

IOTM

Safety-limiting values – maximum values allowed in the event of a failure. Case Temperature T Input Current** I Output Power** P

Insulation Resistance at TS, VIO = 500 V R

* Refer to the optocoupler section of the Isolation and Control Components Designer’s Catalog, under Product Safety Regulations section IEC/EN/DIN

EN 60747-5-2 for a detailed description of Method a and Method b partial discharge test profiles.

** Refer to the following figure for dependence of PS and IS on ambient temperature.

S

S,INPUT

S, OUTPUT

S

I - IV I - III

I-II

630 V

1181 V

945 V

6000 V

175 °C 230 mA 600 mW

9

>10

peak

Ω

4

800

S

700 600 500 400

, INPUT CURRENT – I

S

300 200

100

OUTPUT POWER – P

0

25

50 75 100

TS – CASE TEMPERATURE – °C

125

PS (mW) IS (mA)

150 175

200

Insulation and Safety Related Specifications

Parameter Symbol HCPL-3180 Units Conditions

Minimum External Air Gap L(101) 7.1 mm Measured from input terminals to output (Clearance) terminals, shortest distance through air.

Minimum External Tracking L(102) 7.4 mm Measured from input terminals to output (Creepage) terminals, shortest distance path along body.

Minimum Internal Plastic Gap 0.08 mm Through insulation distance conductor to (Internal Clearance) conductor, usually the straight line distance

thickness between the emitter and detector.

Tracking Resistance CTI >175 V DIN IEC 112/VDE 0303 Part 1 (Comparative Tracking Index)

Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1)

Note: Option 300 – surface mount classification is Class A in accordance with CECC 00802.

Absolute Maximum Ratings

Parameter Symbol Min. Max. Units Note

Storage Temperature T Junction Temperature T Average Input Current I Peak Transient Input Current I

S

J F(AVG) F(TRAN)

(<1 µs pulse width, 300 pps) Reverse Input Voltage V “High” Peak Output Current I “Low” Peak Output Current I Supply Voltage VCC-V Output Voltage V Output Power Dissipation P Total Power Dissipation P

R OH(PEAK) OL(PEAK)

EE O(PEAK) O T

Lead Solder Temperature 260°C for 10 sec., 1.6 mm below seating plane Solder Reflow Temperature Profile See Package Outline Drawings section

-55 125 °C

-40 125 °C 25 mA 1

1.0 A

5V

2.5 A 2

-0.5 25 V

0VCCV

250 mW 3 295 mW 4

5

Recommended Operating Conditions

Parameter Symbol Min. Max. Units Note

Power Supply VCC-V Input Current (ON) I Input Voltage (OFF) V Operating Temperature T

F(ON)

F(OFF)

A

EE

10 20 V 10 16 mA

-3.0 0.8 V

-40 100 °C

Electrical Specifications (DC)

Over recommended operating conditions unless otherwise specified.

Test

Parameter Symbol Min. Typ. Max. Units Conditions Fig. Note

High Level Output Current I

OH

0.5 A VO = VCC- 4 2, 3, 17 5

2.0 A VO = VCC-10 2, 3, 17 2

Low Level Output Current I

OL

0.5 A VO = VEE+2.5 5, 6, 18 5

2.0 A VO = VEE+10 5, 6, 18 2 High Level Output Voltage V Low Level Output Voltage V High Level Supply Current I

OH OL

CCH

VCC-4 V IO = -100 mA 1, 3, 19 6, 7

0.5 V IO = 100 mA 4, 6, 20

3.0 6.0 mA Output Open 7, 8 IF = 10 to 16 mA

Low Level Supply Current I

CCL

3.0 6.0 mA Output Open 7, 8 VF = 3.0 to 0.8 mA

Threshold Input Current I

FLH

8.0 mA

Low to High IO = 0 mA, 9, 15, 21 Threshold Input Voltage V

FHL

0.8 V VO > 5 V

High to Low Input Forward Voltage V

F

Temperature Coefficient of DVF/DT

1.2 1.5 1.8 V IF = 10 mA 16

A

–1.6 mV/°CIF = 10 mA

Input Forward Voltage UVLO Threshold V

UVLO+

V

UVLO–

UVLO Hysteresis UVLO Input Reverse Breakdown BV

R

HYST

5VI

7.9 V IF = 10 mA,

7.4 V VO > 5 V 22, 33

0.5 V

= 10 µA

R

Voltage Input Capacitance C

IN

60 pF f = 1 MHz,

VF = 0 V

6

Switching Specifications (AC)

Over recommended operating conditions unless otherwise specified.

Test

Parameter Symbol Min. Typ. Max. Units Conditions Fig. Note

Propagation Delay Time to t

PLH

High Output Level I Propagation Delay Time to t

PHL

50 150 200 ns 10, 11, 14

10 mA, 12, 13,

F =

50 150 200 ns Rg = 10 Ω, 14, 23

Low Output Level f = 250 kHz, Pulse Width Distortion PWD 20 65 ns Duty Cycle = 50%, 10 Propagation Delay PDD -90 90 ns Cg = 10 nF 34, 35 10

Difference Between Any (t

PHL-tPLH

)

Two Parts or Channels Rise Time t Fall Time t UVLO turn On Delay t UVLO turn Off Delay t Output High Level Common

r f UVLO ON UVLO OFF

|CMH| 10 kV/µsTA = 25°C, 24 11, 12

25 ns CL = 1 nF, 23 25 ns Rg = 0 Ω

2.0 µs22

0.3 µs22

Mode Transient Immunity IF = 10 to 16 mA, Output Low Level Common

Mode Transient Immunity V

|CML| 10 kV/µsV

CM CC

= 1.5 kV, 24 11, 13

= 20 V

Package Characteristics

Test

Parameter Symbol Min. Typ. Max. Units Conditions Fig. Note

Input-Output Momentary V

ISO

3750 V

rms

TA = 25°C, 8,9

Withstand Voltage RH < 50% Input-Output Resistance R Input-Output Capacitance C

Notes:

1. Derate linearly above +70°C free air temperature at a rate of 0.3 mA/°C.

2. Maximum pulse width = 10 µs, maximum duty cycle = 0.2%. This value is intended to allow for component tolerances for designs with IO peak minimum = 2.0 A. See Application section for additional details on limiting IOL peak.

3. Derate linearly above +70°C, free air temperature at the rate of 4.8 mW/°C.

4. Derate linearly above +70°C, free air temperature at the rate of 5.4 mW/°C. The maximum LED junction temperature should not exceed +125°C.

5. Maximum pulse width = 50 µs, maximum duty cycle = 0.5%.

6. In this test, VOH is measured with a dc load current. When driving capacitive load VOH will approach VCC as IOH approaches zero amps.

7. Maximum pulse width = 1 ms, maximum duty cycle = 20%.

8. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage > 4500 V current limit I

9. Device considered a two-terminal device: pins on input side shorted together and pins on output side shorted together.

10. PWD is defined as |t

11. Pin 1 and 4 need to be connected to LED common.

12. Common mode transient immunity in the high state is the maximum tolerable dVCM/dt of the common mode pulse VCM to assure that the output will remain in the high state (i.e. VO > 10.0 V).

13. Common mode transient immunity in a low state is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the output will remain in a low state (i.e. VO < 1.0 V).

14. t

propagation delay is measured from the 50% level on the falling edge of the input pulse to the 50% level of the falling edge of the VO signal.

PHL

t

propagation delay is measured from the 50% level on the rising edge of the input pulse to the 50% level of the rising edge of the VO signal.

PLH

15. The difference between t

< 5 µA).

I-O

- t

| for any given device.

PHL

PLH

and t

PHL

I-O I-O

between any two HCPL-3180 parts under same test conditions.

PLH

[11]

10

Ω V

= 500 V 9

I-O

1 pF Freq = 1 MHz

for 1 second (leakage detection

rms

7

-1

-2

-3

-0.5

-1.0

= 10 to 16 mA

I

F

I

= -100 mA

OUT

V

= 10 to 20 V

CC

V

= 0 V

EE

2.5

2.0

1.5

-1.5

-2.0

) – HIGH OUTPUT VOLTAGE DROP – V

-2.5

CC

– V

OH

-3.0

(V

-40

-20002040

60 80

100

TA – TEMPERATURE – °C

1.0 IF = 10 to 16 mA

V

= (VCC - 4 V)

– OUTPUT HIGH CURRENT – A

0.5

OH

I

0

-40

-20

02040

OUT

V

= 10 to 20 V

CC

V

= 0 V

EE

60 80

100

TA – TEMPERATURE – °C

-4

= 10 to 16 mA

I

F

) – OUTPUT HIGH VOLTAGE DROP – V

-5

V

= 10 to 20 V

CC

V

= 0 V

– V (V

EE

OH

-6 0

1

IOH – OUTPUT HIGH CURRENT – A

Figure 1. VOH vs. temperature. Figure 2. IOH vs. temperature. Figure 3. VOH vs. IOH.

100 °C 25 °C

-40 °C

3

2

4

0.30

0.25

0.20

0.15

0.10

– OUTPUT LOW VOLTAGE – V

0.05

OL

V

0

-40

-20

VF (OFF) = -3.0 TO 0.8 V I

= 100 mA

OUT

V

= 10 TO 20 V

CC

V

= 0 V

EE

020

40 60 80

100

TA – TEMPERATURE – °C

3.0

2.5

2.0

1.5

VF (OFF) = -3.0 TO 0.8 V V

= 2.5 V

OUT

V

= 10 TO 20 V

CC

V

= 0 V

EE

100 °C 0 °C 25 °C

3

2

1.0

1

– OUTPUT LOW CURRENT – A

0.5

OL

I

0

-40

-20

020

40 60 80

100

TA – TEMPERATURE – °C

– OUTPUT LOW VOLTAGE – V

OL

V

0

0.541.0 1.5

IOL – OUTPUT LOW CURRENT – A

Figure 4. VOL vs. temperature. Figure 5. IOL vs. temperature. Figure 6. VOL vs. IOL.

– SUPPLY CURRENT – mA

CC

I

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

VCC = 20 V V

= 0 V

EE

I

= 10 mA for I

F

I

= 0 mA for I

F

0

-40

-20

02040

TA – TEMPERATURE – °C

CCL

CCH

I

CCH

I

CCL

60 80

100

– SUPPLY CURRENT – mA

CC

I

3.5 I

CCH

I

CCL

CCH

4

3

2

1

– LOW TO HIGH CURRENT THRESHOLD – mA

0

20

I

FLH

-40

-205020 TA – TEMPERATURE – °C

3.3

3.1

2.9 IF = 10 mA for I

I

= 0 mA for I

2.7

2.5

10

12 14

F

TA = 25 °C V

= 0 V

EE

16 18

VCC – SUPPLY VOLTAGE – V

V

= -3.0 to 0.8 V

F(OFF)

V

= 10 to 20 V

CC

V

= 0 V

EE

VCC = 10 to 20 V V

= 0 V

EE

OUTPUT = OPEN

40 60 80

2.0

2.5

100

Figure 7. ICC vs. temperature. Figure 8. ICC vs. VCC. Figure 9. I

8

vs. temperature.

FLH

250

I T R

200

C DUTY CYCLE = 50% f = 250 kHz

150

= 10 mA

F

= 25°C

A

= 10 Ω

g

= 10 nF

g

250

t

PHL

t

PLH

VCC = 20 V, VEE = 0 V R

= 10 Ω, Cg = 10 nF

g

T

= 25 °C

A

200

f = 250 kHz DUTY CYCLE = 50%

150

250

IF = 10 mA V

CC

R

= 10 Ω, Cg = 10 nF

g

200

f = 250 kHz DUTY CYCLE = 50%

150

= 20 V, VEE = 0 V

100

– PROPAGATION DELAY – ns

p

t

50

10

15

20

25

VCC – SUPPLY VOLTAGE – V

100

– PROPAGATION DELAY – ns

p

t

50

6

10

t

PLH

t

PHL

12

148

16

IF – FORWARD LED CURRENT – mA

100

– PROPAGATION DELAY – ns

p

t

50

-40

-20

02040

t

PHL

t

PLH

60 80

100

TA – TEMPERATURE – °C

Figure 10. Propagation delay vs. VCC. Figure 11. Propagation delay vs. IF. Figure 12. Propagation delay vs. temperature.

250

IF = 10 mA T

= 25°C

A

f = 250 kHz

200

C

= 10 nF

g

DUTY CYCLE = 50%

150

100

– PROPAGATION DELAY – ns

p

t

50

20

10

30

Rg – SERIES LOAD RESISTANCE – Ω

250

IF = 10 mA TA = 25°C Rg = 10 Ω

200

f = 250 kHz

= 10 nF

C

g

DUTY CYCLE = 50%

150

100

– PROPAGATION DELAY – ns

t

PLH

t

PHL

40

50

p

t

50

5

10

15 20

t

PHL

t

PLH

25

Cg – LOAD CAPACITANCE – nF

20

15

10

– OUTPUT VOLTAGE – V

5

O

V

0

1

2

34

5

IF – FORWARD LED CURRENT – mA

Figure 13. Propagation delay vs. Rg. Figure 14. Propagation delay vs. Cg. Figure 15. Transfer characteristics.

1000

– FORWARD CURRENT – mA

F

I

0.001

100

10

I

+

V

F

–

1.0

0.1

0.01

1.20

1.10 VF – FORWARD VOLTAGE – VOLTS

TA = 25°C

F

1.30 1.40 1.50

1.60

Figure 16. Input current vs. forward voltage.

9

8

7

6

5

0.1 µF

1

+

4 V/10

–

I

OH

V

= 10

+

CC

–

to 20 V

2

3

4

IF = 10 to

16 mA

1

2

3

4

Figure 17. IOH test circuit. Figure 18. IOL test circuit.

8

7

6

5

0.1 µF

I

OL

2.5 V/10 V

V

= 10

+

CC

–

to 20 V

+

–

1

2

3

4

IF = 10 to

16 mA

1

2

3

4

8

7

6

5

0.1 µF

V

OH

100 mA

V

= 10

+

CC

–

to 20 V

Figure 19. VOH test circuit. Figure 20. VOL test circuit.

1

2

I

F

3

8

7

6

0.1 µF

VO > 5 V

1

2

V

= 10

+

CC

–

to 20 V

IF = 10 mA

3

8

7

6

5

0.1 µF

8

7

6

V

OL

0.1 µF

100 mA

+

–

VO > 5 V

V

CC

to 20 V

= 10

+

V

CC

–

Figure 21. I

10

4

test circuit. Figure 22. UVLO test circuit.

FLH

5

4

5

250 KHz

50% DUTY

CYCLE

IF = 10 to 16 mA

500 Ω

+

–

1

2

3

4

8

0.1 µF

+

V

7

V

6

5

10 Ω

10 nF

= 20 V

CC

–

O

I

F

t

r

V

OUT

t

PLH

t

f

90% 50%

10%

t

PHL

Figure 23. t

+

5 V

–

, t

, tr and tf test circuit and waveform.

PLH

PHL

I

F

1

A

2

B

3

4

–

+

V

= 1500 V

CM

Figure 24. CMR test circuit and waveform.

Applications Information Eliminating Negative IGBT Gate Drive

To keep the IGBT firmly off, the HCPL-3180 has a very low maximum VOL specification of 0.4 V. The HCPL-3180 realizes the very low VOL by using a DMOS transistor with 1 W (typical) on resistance in its pull down circuit. When the HCPL-3180 is in the low state, the IGBT gate is shorted to the emitter

V

CM

8

0.1 µF

7

6

5

+

V

O

CC

–

0 V

= 20 V

V

O

SWITCH AT A: IF = 10 mA

V

O

SWITCH AT B: IF = 0 mA

by Rg + 1 W. Minimizing Rg and the lead inductance from the HCPL3180 to the IGBT gate and emitter (possibly by mounting HCPL-3180 on a small PC board directly above the IGBT) can eliminate the need for negative IGBT gate drive in many applications as shown in Figure 25. Care should be taken with such a PC board design to avoid routing the IGBT collector or

V

δV

CM

=

∆t

δt

∆t

emitter traces close to the HCPL-3180 input as this can result in unwanted coupling of transient signals into the input of HCPL-3180 and degrade performance.

(If the IGBT drain must be routed near the HCPL-3180 input, then the LED should be reverse biased when in the off state to prevent the transient signals coupled from the IGBT drain from turning on the HCPL-3180.)

V

OH

V

OL

CONTROL

INPUT

COLLECTOR

+5 V

74XXX

OPEN

1

270 Ω

2

3

4

8

0.1 µF

7

6

5

+

–

Figure 25. Recommended LED drive and application circuit for HCPL-3180.

11

= 15 V

V

CC

Rg

Q1

Q2

+ HVDC

3-PHASE

AC

- HVDC

Selecting the Gate Resistor (Rg) for HCPL-3180 Step 1: Calculate Rg minimum from the IOL peak specification. The IGBT

and Rg in Figure 25 can be analyzed as a simple RC circuit with a voltage supplied by the HCPL-3180.

R

≥

g

=

VCC – V

20 – 3

I

OLPEAK

2

OL

= 8.5 Ω

The VOL value of 3 V in the previous equation is the VOL at the peak current of 2 A. (See Figure 6.)

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

– ENERGY PER SWITCHING CYCLE – µJ

0.2

sw

E

0

Rg — GATE RESISTANCE — Ω

20

10

Qg = 100 nC

30 40

50

Step 2: Check the HCPL-3180 power dissipation and increase Rg if

necessary. The HCPL-3180 total power dissipation (PT) is equal to the sum of the emitter power (PE) and the output power (PO).

PT= PE + P

O

PE= IF * VF * Duty Cycle

PO= P

O(BIAS)

+ P

O(SWITCHING)

= ICC * VCC + ESW (Rg;Qg) * f

For the circuit in Figure 25 with IF (worst case) = 16 mA, R Max Duty Cycle = 80%, Qg = 100 nC, f = 200 kHz and T

AMAX

= 10 Ω,

g

= +75°C:

PE= 16 mA * 1.8 V * 0.8 = 23 mW

PO= 4.5 mA

= 260 mW ≥ 226 mW (P

20 V + 0.85 µ

*

200 kHz

*

@ 75°C = 250 mW (5°C * 4.8 mW/°C))

O(MAX)

The value of 4.5 mA for ICC in the previous equation was obtained by derating the ICC max of 6 mA to I is greater than the P

, Rg must be increased to reduce the HCPL-

O(MAX)

max at +75°C. Since P

CC

for this case

O

3180 power dissipation.

P

O(SWITCHING MAX)

= P

O(MAX)

– P

O(BIAS)

Figure 26. Energy dissipated in the HCPL-3180 and for each IGBT.

= 226 mW – 90 mW

= 136 mW

P

O(SWITCHING MAX)

ESW(MAX) =

f

= 136 mW 200 kHz

= 0.68 µW

For Qg = 100 nC, a value of E

12

= 0.68 µW gives a R

sw

= 15 W.

g

Thermal Model (Discussion applies to HCPL-3180)

The steady state thermal model for the HCPL-3180 is shown in Figure 27. The thermal resistance values given in this model can be used to calculate the temperatures at each node for a given operating condition. As shown by the model, all heat generated

TJE = PE * (qLC//qLD + qDC) + qCA) + PD

q

TJD = PE

*

LC * qDC

[

+ q

q

LC + qDC + qLD

flows through qCA which raises the case temperature TC accordingly. The value of qCA depends on the conditions of the board design and is, therefore, determined by the designer. The value

= +83 °C/W was obtained

of q

CA

from thermal measurements using a 2.5 x 2.5 inch PC board, with small traces (no ground plane), a

q

LC * qDC

+ q

q

LC + qDC + qLD

//qLD + qDC) + qCA) + T

CA

] + T

CA

] + P

[

*

D * (qLC

single HCPL- 3180 soldered into the center of the board and still air. The absolute maximum power dissipation derating specifications assume a q

value of +83 °C/W.

CA

From the thermal mode in Figure 27, the LED and detector IC junction temperatures can be expressed as:

A

θLD = 442 °C/W

T

JE

θLC = 467 °C/W θDC = 126 °C/W

Figure 27. Thermal model.

TJE= PE

TJD= PE

(256°C/W + q

*

(57°C/W + q

*

T

C

θ

= 83 °C/W*

CA

T

A

T

JD

For example, given PE = 45 mW, PO = 250 mW, T

TJE= PE

= +70 °C and q

A

339°C/W + P

*

= 45 mW

339°C/W + 250 mW * 140°C/W + 70°C

*

= 120°C

) + PD

CA

) + PD

CA

= +83 °C/W:

CA

140°C/W + T

D

*

T

= LED JUNCTION TEMPERATURE

JE

T

= DETECTOR IC JUNCTION TEMPERATURE

JD

= CASE TEMPERATURE MEASURED AT THE

T

C

CENTER OF THE PACKAGE BOTTOM

= LED-TO-CASE THERMAL RESISTANCE

θ

LC

= LED-TO-DETECTOR THERMAL RESISTANCE

θ

LD

= DETECTOR-TO-CASE THERMAL RESISTANCE

θ

DC

= CASE-TO-AMBIENT THERMAL RESISTANCE

θ

CA

*θ

WILL DEPEND ON THE BOARD DESIGN AND

CA

THE PLACEMENT OF THE PART.

(57°C/W + q

*

(111°C/W + q

*

A

CA

) + T

A

TJD= PE

140°C/W + P

*

= 45 mW

194°C/W + T

D

*

140°C/W + 250 mW * 194°C/W + 70°C

*

A

= 125°C

TJE and T

should be limited to +125 °C based on the board layout

JD

and part placement (qCA) specific to the application.

13

LED Drive Circuit Considerations for Ultra High CMR Performance

Without a detector shield, the dominant cause of optocoupler CMR failure is capacitive coupling from the input side of the optocoupler, through the package, to the detector IC as shown in Figure 28. The HCPL-3180 improves CMR performance by using a detector IC with an optically transparent Faraday shield, which

diverts the capacitively coupled current away from the sensitive IC circuitry. However, this shield does not eliminate the capacitive coupling between the LED and optocoupler pins 5-8 as shown in Figure 29. This capacitive coupling causes perturbations in the LED current during common mode transients and becomes the major source of CMR failures for a shielded optocoupler. The main

design objective of a high CMR LED drive circuit becomes keeping the LED in the proper state (on or off ) during common mode transients. For example, the recommended application circuit (Figure 25), can achieve 10 kV/µs CMR while minimizing component complexity.

Techniques to keep the LED in the proper state are discussed in the next two sections.

1

C

LEDP

2

3

C

LEDN

4

8

7

6

5

Figure 28. Optocoupler input to output capacitance model for unshielded optocouplers.

CMR with the LED On (CMRH)

A high CMR LED drive circuit must keep the LED on during common mode transients. This is achieved by over-driving the LED current beyond the input threshold so that it is not pulled below the threshold during a transient. A minimum LED current of 10 mA provides adequate margin over the maximum I

FLH

of

8 mA to achieve 10 kV/µs CMR.

CMR with the LED Off (CMRL)

A high CMR LED drive circuit must keep the LED off (V

F

≤ V

F(OFF)

) during common mode transients. For example, during a -dVCM/dt transient in Figure 30, the current flowing through C through the R

SAT

LEDP

and V

also flows

of the

SAT

logic gate. As long as the low state voltage developed across the logic gate is less than V

F(OFF)

, the LED will remain off and no common mode failure will occur.

1

2

3

4

C

LEDO1

C

LEDP

C

LEDO2

C

LEDN

SHIELD

8

7

6

5

Figure 29. Optocoupler input to output capacitance model for shielded optocouplers.

The open collector drive circuit, shown in Figure 31, cannot keep the LED off during a +dVCM/dt transient, since all the current flowing through C

must be supplied by the LED,

LEDN

and it is not recommended for applications requiring ultra high CMR

+5 V

+

V

–

SAT

1

C

LEDP

2

I

LEDP

3

C

LEDN

4

SHIELD

* THE ARROWS INDICATE THE DIRECTION OF CURRENT FLOW DURING –dV

+ V

L

CM

–

CM

performance. Figure 32 is an alternative drive circuit, which like the recommended application circuit (Figure 25), does achieve ultra high CMR performance by shunting the LED in the off state.

8

0.1 +

/dt.

7

6

5

µF

= 20 V

V

CC

–

• • •

R

g

• • •

Figure 30. Equivalent circuit for Figure 25 during common mode transient.

14

+5 V

1

3

2

4

8

6

7

5

C

LEDP

C

LEDN

SHIELD

+5 V

1

C

LEDP

2

8

7

3

C

Q1

LEDN

I

LEDN

4

SHIELD

6

5

Figure 31. Not recommended open collector drive circuit.

Under Voltage Lockout Feature

The HCPL-3180 contains an under voltage lockout (UVLO) feature that is designed to protect the IGBT under fault conditions which cause the HCPL-3180 supply voltage (equivalent to the fully charged IGBT gate voltage) to drop below a level necessary to keep the IGBT in a low resistance state. When the HCPL-3180 output is in the high state and the supply voltage drops below the HCPL-3180 V

UVLO-

threshold (typ 7.5 V) the

IPM Dead Time and Propagation Delay Specifications

The HCPL-3180 includes a Propagation Delay Difference (PDD) specification intended to help designers minimize “dead time” in their power inverter designs. Dead time is the time during which the high and low side power transistors are off. Any overlap in Q1 and Q2 conduction will result in large currents flowing through the power devices from the high voltage to the lowvoltage motor rails.

optocoupler output will go into the low state. When the HCPL-3180 output is in the low state and the supply voltage rises above the HCPL-3180 V

threshold (typ

UVLO+

8.5 V) the optocoupler output will go into the high state (assume LED is “ON”).

20 18 16 14 12 10

8 6

– OUTPUT VOLTAGE – V

O

V

4 2 0

5

0

(VCC - VEE) – SUPPLY VOLTAGE – V

10 15

Figure 34. Minimum LED skew for zero dead time.

20

Figure 32. Recommended LED drive circuit for ultra-high CMR.

To minimize dead time in a given design, the turn on of LED2 should be delayed (relative to the turn off of LED1) so that under worst-case conditions, transistor Q1 has just turned off when transistor Q2 turns on, as shown in Figure 34. The amount of delay necessary to achieve this condition is equal to the maximum value of the propagation delay difference specification, PDD

, which is specified to be 90

MAX

ns over the operating temperature range of -40 °C to +100 °C.

I

LED1

V

OUT1

V

OUT2

I

LED2

*PDD = PROPAGATION DELAY DIFFERENCE NOTE: FOR PDD CALCULATIONS, THE PROPAGATION DELAYS

ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS.

Q1 ON

Q2 OFF

t

PHL MAX

PDD* MAX = (t

t

PLH MIN

PHL- tPLH)MAX

Q1 OFF

Q2 ON

= t

PHL MAX - tPLH MIN

Figure 33. Under voltage lock out.

15

Delaying the LED signal by the maximum propagation delay difference ensures that the minimum dead time is zero, but it does not tell a designer what the maximum dead time will be. The maximum dead time is equivalent to the difference between the maximum

I

LED1

V

OUT1

Q1 ON

and minimum propagation delay difference specification as shown in Figure 35. The maximum dead time for the HCPL-3180 is 180 ns (= 90 ns-(- 90 ns)) over the operating temperature range of –40 °C to +100 °C.

Q1 OFF

V

OUT2

I

LED2

*PDD = PROPAGATION DELAY DIFFERENCE NOTE: FOR DEAD TIME AND PDD CALCULATIONS, ALL PROPAGATION DELAYS

ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS.

Q2 OFF

t

PHL MIN

t

PHL MAX

(t

PHL-tPLH) MAX

PDD* MAX

t

PLH

MIN

t

PLH MAX

MAXIMUM DEAD TIME (DUE TO OPTOCOUPLER) = (t

PHL MAX - tPHL MIN

= (t

PHL MAX - tPLH MIN

= PDD* MAX – PDD* MIN

Figure 35. Waveforms for dead time.

Note that the propagation delays used to calculate PDD and dead time are taken at equal temperatures and test conditions since the optocouplers under consideration are typically mounted in close proximity to each other and are switching identical IGBTs.

Q2 ON

) + (t

PLH MAX - tPLH MIN

) – (t

PHL MIN - tPLH MAX

)

16

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Agilent HCPL-3180 User Guide

Specifications and Main Features

Frequently Asked Questions

User Manual