The HP 1660E and 1670E-Series
Benchtop Logic Analyzers
Technical Data
Affordable logic analyzers
designed for your exact needs
HP’s new family of benchtop logic
analyzers includes four new series
of products, enabling design engineers to purchase an affordable
logic analyzer that meets their
exact needs and matches their
budget. The units include a VGA
resolution color flat panel display
to help you find information quickly and the well designed user interface gets you to the answer in less
time. Users can use either a mouse
or the front panel to easily navigate
through the user interface. An
optional PC style keyboard is also
supported. A compact all-in-one
design also helps save space on a
crowded lab bench.
The HP 1660ES-Series models come
with a built-in, 500-MHz, 2-GSa/s
oscilloscope that can be triggered by
the logic analyzer. Some of the
tougher hardware debug problems
can be found only with the digital
triggering capabilities of a logic
analyzer and can only be solved
with the analog resolution of an
oscilloscope.
The pattern generator capability in
the HP 1660EP-Series allows
designers to substitute for missing
sub-systems during development.
The HP 1670E-Series help simplify
the capture and analysis of complex
events with 1M deep memory. Deep
memory is a valuable logic analyzer
feature for debugging embedded
microprocessor systems.
Figure 1. HP’s new family of benchtop logic analyzers with color displays
_______________________________________________________________________________________
Model Number HP 1660E HP 1661E HP 1662E HP 1663E
_______________________________________________________________________________________
Channels 136 102 68 34
_______________________________________________________________________________________
Application General purpose logic analysis
_______________________________________________________________________________________
Model Number HP 1660EP HP 1661EP HP 1662EP HP 1663EP
_______________________________________________________________________________________
Channels 136 102 68 34
_______________________________________________________________________________________
Application Hardware simulation and stimulus-response testing
with integrated 32-channel pattern generator
_______________________________________________________________________________________
Model Number HP 1660ES HP 1661ES HP 1662ES HP 1663ES
_______________________________________________________________________________________
Channels 136 102 68 34
_______________________________________________________________________________________
Application Parametric and mixed-signal testing with integrated
two-channel oscilloscope
_______________________________________________________________________________________
Model Number HP 1670E HP 1671E HP 1672E
_______________________________________________________________________________________
Channels 136 102 68
_______________________________________________________________________________________
Application Complex debugging and troubleshooting with deep memory
_______________________________________________________________________________________
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and describes products or services now available through Agilent. It may also refer to products/services no longer supported by Agilent.
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Discontinued Product—Support Information Only
HP 1670E-Series Logic Analyzer Key
Specifications and Characteristics
_______________________________________________________________________
HP Model Number 1670E 1671E 1672E
________________________________________________________________________________
State and Timing 136 102 68
Channels
________________________________________________________________________________
Timing Analysis Conventional: 125 MHz all channels, 250 MHz half channels
________________________________________________________________________________
State Analysis 100 MHz, all channels
Speed
________________________________________________________________________________
State Clocks/ 4 4 4
Qualifiers
________________________________________________________________________________
Memory Depth 1M per channel, 2M in timing half-channel mode
per Channel
________________________________________________________________________________
HP 1660ES Series Oscilloscope
Key Specifications and
Characteristics
_______________________________________
HP Model Number 1660ES, 1661ES
1662ES, 1663ES
Channels 2
Maximum Sample 2 GSa/s per channel
Rate
Bandwidth dc to 500 MHz
(dc coupled)
Rise Time 700 ps
Vertical Resolution 8 bits
Memory Depth per 32k samples
Channel
HP 1660E/ES/EP Series Logic Analyzer key
Specifications and Characteristics
_______________________________________________________________________
HP Model Number 1660E/ES/EP 1661E/ES/EP 1662E/ES/EP 1663E/ES/EP 1664A
State and Timing 136 102 68 34 34
Channels
Timing Analysis Conventional: 250 MHz all channels, 500 MHz half channels
Transitional: 125 MHz all channels, 250 MHz half channels
Glitch: 125 MHz half channels
State analysis speed 100 MHz, all channels 50 MHz
State Clock/Qualifiers 6 6 4 2 2
Memory Depth 4k per channel, 8k in half-channel modes
per Channel
LAN Port Standard for all E/ES/EP models N/A
HP 1660EP Series Pattern Generator Key
Specifications and Characteristics
_______________________________________________________________________
HP Model Number 1660EP, 1661EP, 1662EP, 1663EP
Maximum Clock Speed 200 MHz 100MHz 50 MHz
Number of Data Channels 16 32 32
Memory Depth, in vectors 258,048 258,048 258,048
“IF” Command No No Yes
17.3 inches
(440 mm)
8.1 in.
(205 mm)
13.0 in.
(330 mm)
14.5 in.
(367 mm)
keyboard
HP-IB
connector
line power
module
external
trigger BNC's
pattern
generator
cables
(optional)
RS-232-C
connector
mouse
parallel
printer
connector
LAN connectors
* your number of pods
may be different
*
***
Figure 2. Diagram of logic analyzer’s front and rear panels
2
Figure 3. Logic analyzer dimensions
and weight
Weight = 28.6 lbs. (13kg)
1660ES
LOGIC ANALYZER
H
display
quick menu keys
data entry keys
disk drive
power on/off
shift key
oscilloscope channels
done key select key
movement keys
MENU
C
Q
A
SDFGJL
ZXCVB
NM
KH
YU
I
OP
WER T
DEF
BA
9
4
0123
567
8
System
Trigger
Done Select
Clear
entry
Run
Cont
Stop
Page
Page
Print
All
Don't
care
±
.
Waveform
Listing
Config
Format
HP 1660E and 1670E-Series
Logic Analyzer Specifications
and Characteristics
_________________________
Human Interface
_________________________
Front Panel A knob and keypad
make up the front-
panel human interface.
Keys include control,
menu, display navigation, and alpha-numeric entry functions.
_________________________
Mouse A DIN mouse is
shipped as standard
equipment. It provides
full instrument control.
Knob functionality is
replicated by holding
down the right button
and moving the mouse
left or right.
[1]
_________________________
Keyboard The logic analyzer can
also be operated using
a DIN keyboard. Order
the HP Logic Analyzer
Keyboard Kit, model
number HP E2427B.
[1]
_________________________
Input/Output, Control,
and Printing
_________________________
I/O Ports All units ship with a
Centronics parallel
printer port, RS-232,
and HP-IB as standard
equipment.
_________________________
LAN Interface An Ethernet LAN inter-
face is standard. The
LAN interface comes
with both Ethertwist
and ThinLan connectors. The LAN supports
FTP and PC/NFS connection protocols. It
also works with X11
windows packages.
[1]
_________________________
Program- Each instrument is fully
mability programmable from a
computer via HP-IB,
RS-232 and LAN connections.
[1]
_________________________
HP Printer Printers which use the
Support HP Printer Control
Language (PCL) and
have a parallel
Centronics, RS-232 or
HP-IB interface are
supported:
HP DeskJet, LaserJet,
QuietJet, PaintJet, and
ThinkJet models
_________________________
_________________________
Alternate The Epson FX80, LX80
Printers and MX80 printers with
Supported an RS-232 or Centronics
interface are supported
in the Epson 8-bit
graphics mode.
_________________________
Hard Copy Screen images can be
Output printed in black and
white or color from all
menus using the
Print
field. State or timing
listings can be also be
printed in full or part
(starting from center
screen) using the
Print All
selection.
_________________________
Mass Storage Files
and Software
_________________________
Updating the The operating system
Operating resides in Flash ROM
System and can be updated
from the flexible disk
drive or from the
internal hard disk
drive.
[1]
_________________________
Mass Storage Supported by an inter-
nal hard disk drive and
by a 1.44 Mbyte, 3.5inch flexible disk drive.
Supports DOS and LIF
formats.
[1]
_________________________
Screen Image An image file of any
Files display screen can be
stored to disk via the
display's
Print
field in
black & white or color
TIFF, color PCX, or
black & white
Encapsulated
PostScript™ (EPS)
formats.
_________________________
ASCII Data State or timing listings
Files can be stored as ASCII
files on a disk via the
display's
Print
field.
These files are equivalent in character width
and line length to hardcopy listings printed via
the
Print All
selection.
_________________________
_________________________
Configuration Logic analyzer and
and Data Files oscilloscope files
that include configura-
tion and data information (if present) are
encoded in a binary
format. They can be
stored to or loaded
from the hard disk drive
or a flexible disk.
_________________________
Recording of Binary format
Acquisition configuration/data files
and Storage are stored with the
Times time of acquisition and
the time of storage.
[1]
_________________________
Acquisition Arming
_________________________
Initiation Arming is started by
Run, Group Run,
or the
Port In BNC.
_________________________
Cross Arming Analyzer machines
and the oscilloscope
or pattern generator
can cross-arm each
other.
_________________________
Output An output signal is
provided at the Port
Out BNC.
_________________________
PORT IN Port In is a standard
Signal and BNC connection.
Connection The input operates at
TTL logic signal levels.
Rising edges are valid
input signals.
_________________________
PORT OUT Port Out is a standard
Signal and BNC connection
Connection with TTL logic
signal levels. A rising
edge is asserted as a
valid output.
_________________________
Skew Correction factors for
Adjustment nominal skew between
displayed timing and
oscilloscope signals
are built into the operating system.
Additional correction
for unit-by-unit variation can be made using
the
Skew
field. An
entered skew value
affects the next (not
the present) acquisition
display.
_________________________
3
1] Please refer to HP 1664A Product Specifications
and Characteristics on page 7.
_________________________
PORT IN 15 ns typical delay
Arms Logic from signal input to a
Analyzer
[2]
don't care
logic
analyzer trigger.
_________________________
PORT IN 40 ns typical delay
Arms from signal input to an
Oscilloscope
immediate
oscilloscope
trigger.
_________________________
Logic 120 ns typical delay
Analyzer from logic analyzer
Arms PORT trigger to signal
OUT
[2]
output.
_________________________
Oscilloscope 60 ns typical delay from
Arms PORT oscilloscope trigger to
OUT signal output.
_________________________
Operating Environment
_________________________
Power 115 Vac or 230 Vac,
–22% to +10%, single
phase, 48-66 Hz, 320 VA
max
_________________________
Temperature Instrument, 0° to 50° C
(+32° to 122° F). Disk
media, 10° to 40° C
(+50° to 104°F). Probes
and cables, 0° to 65° C
(+32° to 149° F)
_________________________
Humidity Instrument, up to 95%,
relative humidity at
+40° C (+140° F). Disk
media and hard drive,
8% to 85% relative
humidity.
_________________________
Altitude To 3,048 m (10,000 ft)
[1]
_________________________
Vibration: Random vibrations
Operating 5–500 Hz,
10 minute per axis,
~ 0.3 g (rms).
_________________________
Vibration: Random vibrations
Non Operating 5–500 Hz,10 minutes per
axis,~ 2.41 g (rms); and
swept sine resonant
search, 5–500 Hz,
0.75 g (0-peak),
5 minute resonant dwell
@ 4 resonances per
axis.
_________________________
_________________________
Physical Factors
_________________________
Safety IEC 348/ HD 401,
UL 1244, and
CSA Standard C22.2
No. 231 (series M-89)
_________________________
EMC
CISPR 11:1990/EN 55011 (1991):
Group 1 Class A
IEC 801-2:1991/EN 50082-1 (1992):
4kV CD, 8 kV AD
IEC 801-3:1984/EN 50082-1 (1992): 3 V/m
IEC 801-4:1988/EN 50082-1 (1992): 1kV
_________________________
_________________________
Logic Analyzer Probes
_________________________
Input 100 kΩ±2%
Resistance
_________________________
Input approx. 8 pF
Capacitance (see figure 4)
_________________________
Figure 4
_________________________
Minimum 500 mV peak-to-peak
Input Voltage
Swing
_________________________
Minimum 250 mV or 30% of input
Input amplitude, whichever is
Overdrive greater
_________________________
Threshold –6.0 V to +6.0 V in 50-mV
Range increments
_________________________
Threshold Threshold levels may be
Setting defined for pods
(17-channel groups) on
an individual basis
_________________________
Threshold ± (100 mV +3% of
Accuracy* threshold setting)
_________________________
Input ± 10 V about the
Dynamic threshold
Range
_________________________
Maximum ± 40 V peak
Input Voltage
_________________________
HP 1660E and 1670E-Series
Logic Analyzer Specifications
and Characteristics (cont.)
4
RT= 250Ω
High Frequency Model for Probe Inputs
RIN= 100kΩCTG= 1 pF Z0=
150Ω
C
COMP
= 7.5 pF
_________________________
+5 V 1/3 amp maximum
Accessory per pod
Current
_________________________
Channel Each group of 34
Assignment channels (a pod pair)
can be assigned to
Machine 1, Machine 2
or remain unassigned.
The HP 1663E/ES/EP
and the HP 1664A do
not have a Machine 2.
______________________________
State Analysis
_________________________
Maximum 100 MHz
[1]
all models
State
Speed*
_________________________
Memory
Depth per
Channel
HP 1660E/ES/ 4k samples std.
EP Series Time tags on:
2k samples
HP 1670E 1M samples standard
Series Time Tags On:
500k samples
Compare Mode On:
250k samples
Compare Mode
and Time Tags On:
120k samples
_________________________
State Clocks Clock edges can be
ORed together and oper-
ate in single phase, twophase demultiplexing, or
two-phase mixed mode.
Clock edge is selectable
as positive, negative, or
both edges for each
clock.
_________________________
State Clock The high or low voltage
Qualifier level of up to 4 of the 6
clocks can be ANDed
or ORed with the clock
specification.
_________________________
Setup/Hold*
[4]
one clock, 3.5/0 ns to 0/3.5 ns
one edge (in 0.5 ns increments)
one clock, 4.0/0 ns to 0/4.0 ns
both edges (in 0.5 ns increments)
multi-clock, 4.5/0 ns to 0/4.5 ns
multi-edge (in 0.5 ns increments)
_________________________
[1] Please refer to HP 1664A Product Specifications
and Characteristics on page 7.
[2] Time may vary depending upon the mode of logic
analyzer operation.
* Warranted specification.
[3] Full channel /half channel modes
HP 1660E and 1670E-Series
Logic Analyzer Specifications
and Characteristics (cont.)
_________________________
Minimum 3.5 ns
State Clock
Pulse Width*
[4]
_________________________
Minimum 10.0 ns
Master to
Master
Clock Time*
[4]
_________________________
Minimum 10.0 ns
Slave to
Slave
Clock Time
[4]
_________________________
Minimum 0.0 ns
Master to
Slave
Clock Time
[4]
_________________________
Minimum 4.0 ns
Slave to Master
Clock Time
[4]
_________________________
Clock 4.0/0 ns (fixed)
Qualifiers
Setup/Hold
[4]
_________________________
State Counts the number of
Tagging
[5]
qualified states
between each stored
state. Measurement
can be shown relative
to the previous state or
relative to trigger. Max.
count is 4.29 ×10
9
.
_________________________
Time Measures the time
Tagging
[5]
between stored states,
relative to either the
previous state or to the
trigger. Max. time
between states is
34.4 sec. Min. time
between states is 8 ns.
Time Tag 8 ns or 0.1% (whichever
Resolution is greater)
_________________________
Timing Analysis
_________________________
Conventional Data stored at selected
Timing sample rate across all
timing channels.
HP 1660 Series
Sample 4 ns/2 ns minimum,
Period
[3]
8.38 ms maximum
HP 1670 Series
Sample 8 ns/4 ns minimum,
Period
[3]
41 ms/10 ms maximum
Time Covered Sample period ×
by Data
[3]
memory depth
_________________________
Transitional (HP 1660E/ES/EP Series
Timing only) Sample is stored
in acquisition memory
only when the data
changes. A time tag
stored with each
sample allows reconstruction of waveform
display. Time covered
by a full memory acquisition varies with the
number of pattern
changes in the data.
Time Covered 16.3 µs minimum,
by Data
[3]
9.7 hrs./6.5 hrs.
maximum
Maximum 34.4 s
Time
Between
Transitions
Number of 1023-2047/682-4094
Captured Depending on input
Transitions
[3]
signals
_________________________
Glitch (HP 1660E/ES/EP Series
Capture only.) Data sample and
Mode glitch information is
stored every sample
period.
Maximum 125 MHz
Timing Speed
Sample 8 ns minimum, 8.38 ms
Period maximum
Minimum 3.5 ns
Glitch Width*
Maximum Sample Period – 1 ns
Glitch Width
Memory 2048 samples
Depth per
Channel
Time Covered Sample Period ×2048:
by Data 16.3 µs minimum,
17.1 sec maximum
_________________________
Time Interval Accuracy
_________________________
Sample ± 0.01%
Period
Accuracy
_________________________
Channel-to- 2 ns typical,
Channel Skew3 ns maximum
_________________________
Time Interval ± (Sample Period
Accuracy Accuracy + channel-
to-channel skew +
0.01% of time interval
reading)
_________________________
Maximum Sample Period 2-8 ns :
Delay 8.389 ms
After Sample Period > 8 ns:
Triggering 1,048,575 ×sample
period
_________________________
Trigger Specifications
_________________________
Trigger Trigger setups can be
Macros selected from a cate-
gorized list of trigger
macros. Each macro is
shown in graphical
form and has a written
description. Macros
can be chained together to create a custom
trigger sequence.
_________________________
Pattern Each recognizer is the
Recognizers AND combination of bit
(0,1, or X) patterns in
each label. Ten pattern
recognizers are available.
_________________________
Minimum >125 MHz timing modes:
Pattern and 13 ns + channel-to-
Range channel skew
Recognizer ≤125 MHz timing modes:
Pulse Width 1.01 x (1 sample period
+1 ns + channel-tochannel skew )
_________________________
5
[3] Full Channel /Half Channel Modes
[4] Specified for an input signal VH= – 0.9V, VL = – 1.7V,
slew rate = 1V/ns, and threshold = –1.3V
[5] Time or-state-tagging (Count Time or Count State)
is available in the full-channel state mode. There is
no speed penalty for tag use. Memory is halved
when time or state tags are used unless a pod pair
(34-channel group) remains unassigned in the
Configuration menu.
* Warranted specification.
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