Agilent 16517A Help Volume

Help Volume

Instrument: Agilent Technologies 16517A 4GHz Timing/1GHz State Logic Analyzer

Agilent Technologies 16517A/18A 4GHz Timing/1GHz State Logic Analyzer

The Agilent Technologies 16517A provides timing analysis at a sample rate of up to 4 GHz. It also offers state analysis that uses your target system’s clock at speeds of up to 1 GHz. The 16517A can be connected to up to 4 Agilent Technologies 16518A expansion cards, giving 80 channels each with a memory depth of 64 Ksamples.

Getting Started

•“Connecting to Your Target System” on page 10

•“Adjusting Skew” on page 16

•“Setting Up a Measurement” on page 17

•“When Something Goes Wrong” on page 35

•“Error Messages” on page 35

Measurement Examples

•“Making a Basic Timing Measurement” on page 22

•“Making a Basic State Measurement” on page 26

• Advanced Measurement Examples (see the Measurement Examples help

volume)

•“Interpreting the Data” on page 30

More Features

Correlating with Other Instruments (see the Agilent Technologies 16700A/B-Series Logic Analysis System help volume)

Using Symbols (see page 85)

Using Markers (see the Markers help volume)

Agilent Technologies 16517A/18A 4GHz Timing/1GHz State Logic Analyzer

“Loading and Saving Logic Analyzer Configurations” on page 34

“Testing the Logic Analyzer Hardware” on page 46

Interface Reference

“The Format Tab” on page 47

“The Trigger Tab” on page 55

The Skew Adjust Tab (see page 16)

“The Symbols Tab” on page 85

“Specifications and Characteristics” on page 80

Main System Help (see the Agilent Technologies 16700A/B-Series Logic Analysis System help volume)

Glossary of Terms (see page 107)

Agilent Technologies 16517A/18A 4GHz Timing/1GHz State Logic Analyzer

1 Agilent Technologies 16517A/18A 4GHz Timing/1GHz State

Logic Analyzer

Connecting to Your Target System 10

Recommended Probe Configurations 10 Probing Accessories 11 Probing System Description 13 Requirements of Target Signals 14

Adjusting Skew 16

Setting Up a Measurement 17

Map the Analyzer to the Target System 17 Set Up the Analyzer 18 Define Trigger Conditions 19 Run the Measurement 20 Examine the Data 20

Making a Basic Timing Measurement 22

Making a Basic State Measurement 26

Interpreting the Data 30

Analysis Using Waveform 30 Analysis Using Listing 32

Loading and Saving Logic Analyzer Configurations 34

Contents

When Something Goes Wrong 35

Nothing Happens 35 Error Messages 35 Suspicious Data 44 Interference with Target System 45

Testing the Logic Analyzer Hardware 46

The Format Tab 47

Setting the Acquisition Mode 47 Defining Labels: Mapping Analyzer Channels to Your System 49 Working with Labels 50 Setting the Pod Threshold 53 Activity Indicators 54

The Trigger Tab 55

Setting Up a Trigger 55 Adding and Deleting Sequence Steps 57 Editing Sequence Steps 58 Setting Up Loops and Jumps in the Trigger Sequence 58 Saving and Recalling Trigger Sequences 59 Clearing Part or All of the Trigger 60 Overview of the Trigger Sequence 61 Predefined Trigger Macros 62 Working with User-Defined Macros 68 Defining Resource Terms 71 Trigger Position Control 76 Sample Period (Timing Only) 77 Oversampling: the Samples/Clock Control 77 Arming Control 78

Contents

Specifications and Characteristics 80

Agilent Technologies 16517A/18A Logic Analyzer Specifications 80 Agilent Technologies 16517A/18A Logic Analyzer Characteristics 81 What is a Specification 83 What is a Characteristic 83 What is a Calibration Procedure 84 What is a Function Test 84

The Symbols Tab 85

Displaying Data in Symbolic Form 86

Setting Up Object File Symbols 87

To Load Object File Symbols 87 Relocating Sections of Code 89 To Delete Object File Symbol Files 90 Symbol File Formats 90 Creating ASCII Symbol Files 91 Creating a readers.ini File 96

User-Defined Symbols 99

To Create User-Defined Symbols 99 To Replace User-Defined Symbols 99 To Delete User-Defined Symbols 100 To Load User-Defined Symbols 100

Using Symbols In The Logic Analyzer 101

Using Symbols As Trigger Terms 101 Using Symbols as Search Patterns in Listing Displays 102 Using Symbols as Trigger Terms in the Source Viewer 102 Using Symbols as Pattern Filter Terms 102 Using Symbols as Ranges in the Software Performance Analyzer 103

Glossary

Contents

Index

Agilent Technologies 16517A/18A 4GHz Timing/1GHz State Logic Analyzer

Chapter 1: Agilent Technologies 16517A/18A 4GHz Timing/1GHz State Logic Analyzer

Connecting to Your Target System

You can connect the logic analyzer to your target system either directly or through an analysis probe. The Agilent Technologies 16517A/18A logic analyzer has two cables ending in pod housings with leads for probing individual lines. Each logic analyzer is shipped with a Probe Accessories Kit, whose components are described below.

You can also connect to the target system through an analysis probe. The Agilent Technologies 16517A/18A logic analyzer requires a clear connection with no termination, so any analysis probe you use must be non-terminated. Additionally, the Agilent Technologies 16517A/18A logic analyzer does not support inverse assembly.

See Also “Recommended Probe Configurations” on page 10

“Probing Accessories” on page 11

“Probing System Description” on page 13

“Requirements of Target Signals” on page 14

Recommended Probe Configurations

Long leads and improper signal connections can result in inconsistent or erroneous data. In an ideal connection, the probe tip connects directly to the target system without any additional lead lengths. Depending on your measurement, the added inductance caused by additional lead length could cause a problem for the signal rise time.

If you must add length to the ground lead, use the following general guidelines:

Target Rise Time Maximum Additional Ground Length

300 ps 1 inch

600 ps 2 inch

Chapter 1: Agilent Technologies 16517A/18A 4GHz Timing/1GHz State Logic Analyzer

Connecting to Your Target System

1 ns 3 inch

Recommended Configurations

Ground Leads

Probing Accessories

The probe accessories described below are part of the probe Accessory Kits supplied with the 16517A master and 16518A expander cards. To order any of these accessories individually, use the part numbers listed below or in the Accessory Kit box.

The probe accessories that plug onto straight pins will fit on 0.63 mm (0.025 in) square pins, or 0.66 mm to 0.84 mm (0.026 in to 0.033 in) diameter round pins.

The following probing components connect the probe to ground.

Right Angle Ground Lead (Agilent Technologies 16517-82106)

This flexible lead is 1.5 inches long with a 90 degree bend off the lead tip. It stacks on 0.1 inch centers.

Chapter 1: Agilent Technologies 16517A/18A 4GHz Timing/1GHz State Logic Analyzer

Connecting to Your Target System

Ground Extender (Agilent Technologies 16517-82105)

If the circuit can tolerate an additional 0.5 to 1 pF capacitance, this socket allows stacking on 0.1 inch centers.

Ground Connector (Agilent Technologies 16515-27601)

This connector creates a 4-to-1 ground connection.

Signal Leads

The following components connect the system to the signal.

Probe Pin (Agilent Technologies 16517-82107)

The probe pin allows touch probing.

SMT Tack-on Signal/Ground Wire (Agilent Technologies 16517-82104)

For surface-mount components, PGAs, or cramped areas, this wire can be tacked onto an IC lead for direct connection.

Grabbers (Agilent Technologies 16517-82108)

These 0.05 pitch grabbers attach to IC pins with lead spacing greater than or equal to 0.5 inch.

Calibration Pod (Agilent Technologies 16517-63201)

BNC to SMB Cable Adapter (Agilent Technologies 16517-

61604)

Chapter 1: Agilent Technologies 16517A/18A 4GHz Timing/1GHz State Logic Analyzer

Connecting to Your Target System

The calibration pod is only included in the accessory kit for the 16517A. You use the calibration pod during the skew adjust procedure. See “Adjusting Skew” on page 16 for information on performing the skew adjust procedure.

On the back of the 16517A card, there are two SMB connectors used for external ECL arm in/out signals. Use this adapter between the BNC cable and the logic analyzer. The adapter cable is only included in the accessory kit for the 16517A.

Probing System Description

The Agilent Technologies 16517A/18A logic analyzer probing system consists of shielded cables ending in a pod housing, with 12-inch coaxial cables for the individual probes. The probing accessories are plugged onto the probes.

The pod housing contains termination networks and comparators. The pod housing also shows the equivalent circuit for 4 GHz operation, so

Chapter 1: Agilent Technologies 16517A/18A 4GHz Timing/1GHz State Logic Analyzer

Connecting to Your Target System

that you can calculate pod loading. It is also shown below.

Each probe has a ground connection, which must be used for acceptable signal quality. The accessory kit contains ground extenders. All probe accessories connect to 0.1-inch centers.

Only Pod 1 of the 16517A card has a clock channel. For state measurements, this probe must be connected to the target system’s clock.

Pressing the Pod ID button on the pod housing causes a message that identifies the pod to appear on the logic analysis system.

See Also “Requirements of Target Signals” on page 14

Logic Analysis System Installation Guide

Agilent Technologies 16517A/18A 4GHz Timing/1GHz State User’s Reference

Requirements of Target Signals

Minimum Signal Amplitude

Any signal line you intend to probe with the logic analyzer probes must supply a minimum voltage swing of 500 mV to the probe tip. If you measure signal lines with a smaller voltage swing, you may not get reliable results. The minimum input overdrive (see page 15) is the

Chapter 1: Agilent Technologies 16517A/18A 4GHz Timing/1GHz State Logic Analyzer

Connecting to Your Target System

greater of 250 mV or 30% of signal amplitude.

Maximum Probe Input Voltage

The maximum probe input voltage of each logic analyzer probe is 40 volts peak.

Overdrive

Overdrive is the amount a signal must exceed the threshold voltage for the logic analyzer to detect a change in logic level. For the Agilent Technologies 16517A/18A logic analyzer, overdrive is 250 mV or 30% of signal peak-to-peak amplitude, whichever is greater.

For example, given a 3.3 volt CMOS signal (low = 0V, high = 3.3 V) the optimal threshold is 1.65 V (50%). If the threshold is set less than 1.0 V or greater than 2.3 V, then a timing acquisition might show excessive channel-to-channel skew. For a state acquisition, the analyzer’s setup and hold requirements might not be met.

The overdrive amount is specified as the greater of 250 mV or 30% of the signal amplitude because it has two purposes. The 250 mV ensures reliable switching or state detection. The 30% of amplitude ensures the threshold is reasonably centered within the waveform in order to minimize channel-to-channel skew (t

PHL

vs t

PLH

Chapter 1: Agilent Technologies 16517A/18A 4GHz Timing/1GHz State Logic Analyzer

Adjusting Skew

Skew adjustment minimizes channel-to-channel skew. This is a necessary step to make sure your Agilent Technologies 16517A/18A logic analyzer meets specifications.

This procedure requires the Agilent Technologies 16517-63201 calibration pod and a BNC coax cable.

1. Connect the BNC cable to the Cal port on the back panel of the 16517A

master card.

2. Connect the other end of the BNC cable to the calibration pod’s Cal input.

3. In the Agilent Technologies 16517A/18A 4GHz Timing/1GHz State window,

select the Skew Adjust tab.

4. Select the Start button.

5. Follow the instructions on screen. Be sure to plug the probes all the way into the module, as shown below.

The Agilent Technologies 16517A/18A does not require an operational accuracy calibration. To test it against the module specifications, refer to "Testing Performance" in the optional Agilent Technologies 16517A/18A Service Guide, available from your Agilent Technologies Sales Office.

Chapter 1: Agilent Technologies 16517A/18A 4GHz Timing/1GHz State Logic Analyzer

Setting Up a Measurement

There are six basic steps for any measurement.

1. “Map the Analyzer to the Target System” on page 17

2. “Set Up the Analyzer” on page 18

3. “Define Trigger Conditions” on page 19

4. “Run the Measurement” on page 20

5. “Examine the Data” on page 20

6. Refine measurement by repeating steps 3 - 5.

If you load a configuration file, it will set up the logic analyzer and trigger sequence. For your particular measurement, you may need to change some settings.

See Also “Making a Basic Timing Measurement” on page 22

“Making a Basic State Measurement” on page 26

Measurement Examples (see the Measurement Examples help volume)

Making Basic Measurements for a self-paced tutorial

Map the Analyzer to the Target System

The first step is to physically connect the logic analyzer to your target system in a way that makes sense.

Connect Pods

The logic analyzer pods detect the signals on your target system. Attach pods in a way that keeps logically related channels together. Be sure to ground each probe.

If you plan on making state measurements, be sure to connect the clock probe on Pod 1 of the 16517A master card to your target

Chapter 1: Agilent Technologies 16517A/18A 4GHz Timing/1GHz State Logic Analyzer

Setting Up a Measurement

system’s clock line.

Step 2: Set Up the Analyzer (see page 18)

See Also “Connecting to Your Target System” on page 10

Set Up the Analyzer

The next step is to set up the logic analyzer. These controls are grouped under the Format tab. If you load a configuration file, this step is taken care of for you.

Set Measurement Type and Clocks

The logic analyzer can perform state or timing measurements. State measurements are also known as synchronous or logic measurements. Timing measurements are also known as asynchronous, internal clock, or periodic measurements. State measurements use the target system’s clock to determine when to sample. Timing measurements sample at a fixed rate which you select.

For state measurements, you must specify a clock edge to match the clocking arrangement used by your target system. If the clock is incorrect, the trace data may indicate a problem where there isn’t one.

Group Bits With Labels

Pod fields correspond to the cables on the logic analyzer module. The bits in the pod fields correspond to the individual signals monitored by the pods. Bits with activity on them show double-headed arrows, like

so . Labels group bits into logical signals; for example, "addr bus". These groupings are then used in the trigger tab and the data displays. A label can have up to 32 channels. Each measurement can define 126 labels.

Step 3: Define Trigger Conditions (see page 19)

Chapter 1: Agilent Technologies 16517A/18A 4GHz Timing/1GHz State Logic Analyzer

See Also “Setting the State Clock” on page 48

“Assigning Bits to a Label” on page 50

“The Format Tab” on page 47

Define Trigger Conditions

The third step is to define the trigger. Controls for this are located under the Tri g ger tab. Configuration files saved from previous measurements automatically define trigger conditions.

Define Terms

If you think of labels as variables, terms are the specific values the variables can assume. A hardware metaphor would be that labels are bits, and terms are the specific values. Terms can match patterns and edges.

Setting Up a Measurement

For example, if you wanted to trigger on a write to a specific address, first you’d group the address bus into a label and then you’d set up a term based on that label with the address.

Set Up a Trigger Sequence

The trigger sequence is like a small program that controls when the logic analyzer stores data. There are trigger macros for the common tasks, or you can set up your own. The logic analyzer starts at the first trigger level until either the main branch or the "else" condition becomes true. When that happens, it goes to the next level and follows the instructions there.

Step 4: Run the Measurement (see page 20)

See Also “Defining Resource Terms” on page 71

“Setting Up a Trigger” on page 55

“The Trigger Tab” on page 55

Chapter 1: Agilent Technologies 16517A/18A 4GHz Timing/1GHz State Logic Analyzer

Setting Up a Measurement

Measurement Examples (see the Measurement Examples help volume)

Run the Measurement

You run the measurement by selecting a button sometimes labeled Run, sometimes Group Run, sometimes Run All. The difference between the three types is that Run starts only the instrument you are using, Group Run starts all instruments attached to group run in the Intermodule window, and Run All starts all instruments currently placed in the workspace.

Runs can be single or repetitive. Single runs gather data until the logic analyzer memory is full, and then stop. Repetitive runs keep repeating the same measurement and are useful for gathering statistics. Repetitive runs on a logic analyzer do not do equivalent time sampling like oscilloscopes do.

If you want to stop a run, select the Stop button.

Step 5: Examine the Data (see page 20)

Examine the Data

Data from your measurement can be viewed in various display windows or offline. Some of the things you can do in the display windows are

• Gather statistics

• Search for patterns

• Display time-correlated data

Automatically gather statistics

In the repetitive mode, set markers on data points you are interested in and then select repetitive run.

Chapter 1: Agilent Technologies 16517A/18A 4GHz Timing/1GHz State Logic Analyzer

Setting Up a Measurement

Search for patterns

Using markers, you can search displays for certain values. There are two global markers which keep their place across all measurement views, even across instruments.

Display correlated data

There are several tools for correlation. The Intermodule window allows you to specify complex triggering configurations using several instruments. It is also useful for starting acquisitions at the same time. Global markers mark the same events in different displays, so you can switch views without having to reorient yourself. The Compare tool lets you compare two different acquisitions to look for changes.

See Also Working with Markers (see the Markers help volume)

Using the Chart Display Tool (see the Chart Display Tool help volume)

Using the Distribution Display Tool (see the Distribution Display Tool help volume)

Using the Listing Display Tool (see the Listing Display Tool help volume)

Using the Digital Waveform Display Tool (see the Waveform Display Tool help volume)

Using the Compare Analysis Tool (see the Compare Tool help volume)

“Interpreting the Data” on page 30

Chapter 1: Agilent Technologies 16517A/18A 4GHz Timing/1GHz State Logic Analyzer

Making a Basic Timing Measurement

This example uses the circuit board that is supplied with the Making Basic Measurements kit as the target system. The kit is supplied with

every logic analysis system, or can be ordered from your Agilent Technologies Sales Office.

There are nine major steps to making a basic measurement. When using the Agilent Technologies 16517A/18A logic analyzer with the training board, you need to connect pod 1 of an Agilent Technologies 16550, 16554, 16555, or 16556 logic analyzer to J1 of the training board in order to supply power.

Map the Logic Analyzer to the Target System

1. Connect probes.

a. Using ground extenders, connect the probes of Pod 1 to J2. You need to

ground each probe.

b. Connect Pod 1 of the other logic analyzer to J1 on the target system to

provide power.

2. On the Agilent Technologies or 16700A/B logic analysis system, open the 16517 logic analyzer setup window.

a. In the main window, select the logic analyzer icon.

b. Choose Setup... from the menu.

3. If the logic analyzer is not already set for Timing, change the sampling mode to Timing.

a. Select the Format tab.

b. Select the sampling mode option button and choose Timing - Full

Channel.

4. Group channels with labels.

a. Optional - Insert a second label.

1. Select Lab1.

Chapter 1: Agilent Technologies 16517A/18A 4GHz Timing/1GHz State Logic Analyzer

Making a Basic Timing Measurement

2. Choose Insert after....

3. In the Enter Label Name box, select OK.

b. Optional - Rename Lab1

1. Select Lab1.

2. Choose Rename....

3. Enter a new name in the name field.

4. Select OK to dismiss the Rename Label box.

c. Select the bit assignment button.

The bit assignment button is to the right of a label name, and under a pod column.

d. Choose ******** from the menu.

If none of the choices match your own system, choose Individual... and select the individual bits to assign them (*) or ignore them (.).

5. Define trigger terms for a bus.

a. Select the Tr igger tab.

b. Optional - Rename pattern term patt1.

1. Select the patt1 field.

2. Enter a new name.

c. Select the appropriate label.

1. Select the label button immediately to the right of the term name.

2. To define the term as a combination of labels, choose Insert... To use a different label to define the term, choose Replace...

3. In the dialog box, select the label name you want to use and then select the OK button.

d. Select the field with XX and enter the value you want to trigger on.

6. Define trigger terms for an edge.

a. Select the Edge tab in the lower part of the window.

b. Optional - Rename edge1.

Chapter 1: Agilent Technologies 16517A/18A 4GHz Timing/1GHz State Logic Analyzer

Making a Basic Timing Measurement

1. Select the edge1 field.

2. Enter a new name.

c. Select the appropriate label.

1. Select the label button immediately to the right of the term name.

2. To define the term as a combination of labels, choose Insert... To use a different label to define the term, choose Replace... Edges within a term are always OR’d together, which means only one of the edges on one of the labels needs to occur for the edge term to become true.

3. In the dialog box, select the label name you want to use and then select the OK button.

d. Select the edge assignment button (........) and enter the edge or

edges you want to trigger on. Remember, if more than one edge is specified, then when the logic analyzer detects any of the edges the term becomes true.

7. Add the edge term to the trigger sequence.

a. Select Modify from the menu bar, then Break down macros.

b. Select the 1 sequence level button and choose Edit...

c. In the dialog box, select the patt1 button and choose Combo...

d. In the Combination box, select Off next to edge1 and choose On.

e. Select the Or option button where the path from patt1 and the path

from edge1 come together, and choose And.

f. Select the OK button.

The analyzer is now set to trigger when it detects edge1 and patt1 is on the bus. The trigger sequence window shows

Find "(patt1*edge)" then TRIGGER

The logic analyzer automatically triggers on the first trigger term. You can set up more complex triggers by editing the sequence levels and defining additional trigger terms.

See Also “The Tri gger Tab” on page 55

Chapter 1: Agilent Technologies 16517A/18A 4GHz Timing/1GHz State Logic Analyzer

1. Select the Run button.

2. Examine the data.

a. Select the Window menu.

b. Select the slot of your high-speed logic analyzer and choose Waveform.

c. To have the waveform display appear automatically when you run the

logic analyzer, select Options -> Popup on Run -> On in the menu bar of the waveform display.

d. To insert additional labels, or expand overlaid signals, select the label

name.

Making a Basic State Measurement

This example uses the circuit board that is supplied with the Making Basic Measurements kit as the target system. The kit is supplied with

every logic analysis system, or can be ordered from your Agilent Technologies Sales Office.

There are ten major steps to making a basic measurement. When using the Agilent Technologies 16517A/18A logic analyzer with the training board, you need to connect pod 1 of an Agilent Technologies 16550, 16554, 16555, or 16556 logic analyzer to J1 of the training board in order to supply power.

Map the Logic Analyzer to the Target System

1. Connect probes.

a. Using ground extenders, connect the probes of Pod 1 to J2. You need to

ground each probe. Be sure to connect the CLK probe to CLK1 of the target system.

b. Connect Pod 1 of the logic analyzer to J1 on the target system.

2. On the Agilent Technologies 16700A/B logic analysis system, open a logic analyzer setup window.

a. In the main window, select the logic analyzer icon.

b. Choose Setup... from the menu.

3. If the logic analyzer is not already set for State, change the sampling mode to State.

a. Select the Format tab.

b. Select the sampling mode option button and choose State - Full

Channel.

4. Check that the logic analyzer is detecting a clock signal.

The Clock Period display shows the measured target system clock. For the training board, the clock is about 40 ns.

If the Clock Period display shows a line, the logic analyzer is not detecting

Chapter 1: Agilent Technologies 16517A/18A 4GHz Timing/1GHz State Logic Analyzer

Making a Basic State Measurement

any clock. Check that the CLK probe of Pod 1 of the master card is connected to CLK1 of J2 on the training board, and that the probe is grounded. If there is still no activity, check that the other logic analyzer is connected to J1 to supply power.

5. Group channels with labels.

a. Optional - Insert a second label.

1. Select the Lab1 button.

2. Choose Insert after....

3. In the Enter Label Name box, select the OK button.

b. Optional - Rename Lab1.

1. Select the Lab1 button.

2. Choose Rename....

3. Enter a new name in the name field.

4. Select OK to dismiss the Rename Label box.

c. Select the bit assignment button.

The bit assignment button is to the right of a label name, and under a pod column.

d. Choose ******** from the menu.

If none of the choices match your own system, choose Individual... and select the individual bits to assign them (*) or ignore them (.).

6. Define trigger terms for patterns on buses.

a. Select the Tr igger tab.

b. Optional - Rename term patt1.

1. Select the patt1 field.

2. Enter a new name.

c. Select the appropriate label.

1. Select the label button immediately to the right of the term name.

2. To define the term as a combination of labels, choose Insert... To use a different label to define the term, choose Replace...

Chapter 1: Agilent Technologies 16517A/18A 4GHz Timing/1GHz State Logic Analyzer

Making a Basic State Measurement

3. In the dialog box, select the label name you want to use and then

select the OK button.

d. Select the field with XX and enter the value you want to trigger on.

e. Optional - Repeat steps a - d for term patt2.

7. Optional - Add additional trigger terms to the trigger sequence.

The logic analyzer automatically triggers on patt1, the first trigger term. You can set up more complex triggers by editing the sequence levels and combining trigger terms.

a. Select the 1 sequence level box and choose Edit...

b. In the dialog box, select the patt1 button and choose Combo...

c. In the Combination box, select Off next to patt2 and choose On.

d. To change the trigger to patt1 and patt2, select the Or button to the

right of the terms and choose And.

e. Select the Combination dialog’s OK button.

f. Select the sequence level dialog’s OK button.

The analyzer is now set to trigger when it detects both the pattern defined by patt1 and the pattern defined by patt2 on the target system’s buses. The trigger sequence windows shows

Find 1 occurrence of "(patt1*patt2)" then TRIGGER

See Also “The Tri gger Tab” on page 55

1. Select the Run button.

2. Examine the data.

a. Select the Window menu.

b. Select the slot of your high-speed logic analyzer and choose Listing.

c. To have the listing display appear automatically when you run the logic

analyzer, select Options -> Popup on Run -> On in the menu bar of the listing display.

d. To insert additional labels, select the label name.

Chapter 1: Agilent Technologies 16517A/18A 4GHz Timing/1GHz State Logic Analyzer

Interpreting the Data

After you’ve acquired a trace with the logic analyzer, you can analyze it in the display tools. The logic analysis system also provides filtering and compare tools for more complex analysis.

The logic analyzer is automatically connected to the Waveform and Listing displays when you set up a measurement. To move to that display,

1. Select the Window menu.

2. Move the cursor over the name of the analyzer whose data you want to view.

3. Choose Waveform or Listing.

•“Analysis Using Waveform” on page 30

•“Analysis Using Listing” on page 32

Analysis Using Waveform

Example: Looking for a Missing Pattern

You can easily use the waveform tool to make timing measurements. For example, if you were triggering when a pattern doesn’t follow an edge within a certain time (see the Measurement Examples help volume), you would probably want to look at your data set to see if the pattern ever did occur. This might be the case when you verifying that the system is responding to an interrupt.

After triggering on an instance where the response did not appear quickly enough, you might take these steps in the Waveform display:

1. Find the edge.

a. Select the Search tab.

b. Select the down arrow after the Label field, and choose the label

containing the edge.

Chapter 1: Agilent Technologies 16517A/18A 4GHz Timing/1GHz State Logic Analyzer

Interpreting the Data

c. Select the value field and enter 1.

d. Select the Next button to locate the edge transition.

2. Place a marker on the edge.

Select Set G1. This sets global marker G1 at the location of the edge you just found.

3. Search for the pattern. Searches start at your current location. Since you just set the global marker G1, it indicates where the search starts from.

a. Select the down arrow after the Label field, and choose the label

containing the pattern.

b. Select the value field and enter the pattern you are searching for.

c. Select the down arrow after the When field and choose Entering.

d. Select the Next button to find the next occurrence of that pattern after

G1.

If the logic analysis system cannot find the pattern, a "Value not found" message pops up.

4. Place a marker on the pattern.

Select Set G2. This will set global marker G2 at the location of the pattern.

5. Find the time between the edge and the pattern.

a. Select the Markers tab.

b. In the G2 row, select the down arrow after from, and choose G1.

The value after the from field changes to the time between G1 and G2. You can toggle between time and samples by selecting the arrow after the Time or Samples field.

See Also Using the Digital Waveform Display Tool (see the Waveform Display Tool

help volume)

Using the Listing Display Tool (see the Listing Display Tool help volume)

Using the Chart Display Tool (see the Chart Display Tool help volume)

Using the Distribution Display Tool (see the Distribution Display Tool help volume)

Chapter 1: Agilent Technologies 16517A/18A 4GHz Timing/1GHz State Logic Analyzer

Interpreting the Data

Using the Compare Analysis Tool (see the Compare Tool help volume)

Using the Pattern Filter Analysis Tool (see the Pattern Filter Tool help volume)

Analysis Using Listing

Listing is more useful than Waveform when your target system is running code because it shows the labels as states rather than transitions. Listing is especially useful when you have defined meaningful symbol names for your states.

Example: Examining a Subroutine

Listing is the preferred display tool for state measurements. for example, if you were trying to see if a subroutine were exiting abnormally, you might want to measure the number of states between entering and exiting the subroutine. After acquiring data with the logic analyzer, you could examine the data set in the Listing display like this:

1. Find the start of the subroutine.

Assume the subroutine starts at the address 0x58FC.

a. Select the Search tab.

b. Select the down arrow after the Label field, and choose ADDR.

c. Select the value field, and enter the starting address, 0x58FC.

d. Select the down arrow after the When field and choose Present.

e. Select the Next or Prev buttons to move the display to the address.

2. Place a marker on the start of the subroutine.

Select the Set G1 button. This sets global marker G1 at the address you just found.

3. Find the end of the subroutine.

Assume the end of the subroutine is at address 0x58FF. Searches always start at the current location. Since you just set the global marker G1, it indicates where the search starts from.

Chapter 1: Agilent Technologies 16517A/18A 4GHz Timing/1GHz State Logic Analyzer

Interpreting the Data

a. Select the value field, and enter 58FF.

b. Select the Next button to find the next occurrence of 0x58FF after the

starting address.

4. Place a marker on the end of the subroutine.

Select the Set G2 button to set global marker G2 at this position. This lets you refer to G2 when you want to know where the subroutine ends.

5. Find the number of states between the start and end of the subroutine.

Since you’ve placed markers at the start and end of the subroutine, all you have to do is find the number of states between those markers.

a. Select the Markers tab.

b. In the G2 row, select the second down arrow and choose Sample.

c. Select the down arrow after from, and choose G1.

The value after the from field changes to the number of states between G1 and G2. You can toggle between time and states by selecting the arrow after the Time or Samples field.

Now you know how long the execution stayed in the subroutine, and can also examine the data set between G1 and G2 to look for unusual data.

See Also Using the Digital Waveform Display Tool (see the Waveform Display Tool

help volume)

Using the Listing Display Tool (see the Listing Display Tool help volume)

Using the Chart Display Tool (see the Chart Display Tool help volume)

Using the Distribution Display Tool (see the Distribution Display Tool help volume)

Using the Compare Analysis Tool (see the Compare Tool help volume)

Using the Pattern Filter Analysis Tool (see the Pattern Filter Tool help volume)

Chapter 1: Agilent Technologies 16517A/18A 4GHz Timing/1GHz State Logic Analyzer

Loading and Saving Logic Analyzer Configurations

The Agilent Technologies 16517A/18A logic analyzer settings and data can be saved to a configuration file. You can also save any tools connected to the logic analyzer. Later, you can restore your data and settings by loading the configuration file into the logic analyzer.

The Agilent Technologies 16517A/18A logic analyzer can only load configuration files that it generated. It cannot load configurations from other logic analyzers.

NOTE: The Agilent Technologies and 16700A/B-series logic analysis systems can

translate configuration files from Agilent Technologies 16500 and 16505 logic analysis systems.

See Also Loading Configuration Files (see the Agilent Technologies 16700A/B-

Series Logic Analysis System help volume)

Saving Configuration Files (see the Agilent Technologies 16700A/BSeries Logic Analysis System help volume)

Chapter 1: Agilent Technologies 16517A/18A 4GHz Timing/1GHz State Logic Analyzer

When Something Goes Wrong

•“Nothing Happens” on page 35

•“Error Messages” on page 35

•“Suspicious Data” on page 44

•“Interference with Target System” on page 45

Nothing Happens

Look for an error message in the message bar at the top of the window. A common message is "Waiting for trigger". Another that appears in the Run Status window is "Cannot Run."

If the Run button briefly grayed-out (while the Stop or Cancel button was briefly active), select the Window menu, select the logic analyzer’s slot, then choose the Waveform or Listing display.

See Also “Waiting for Trigger” on page 36

“Cannot Run. External 16517 Clock Period Should be 1 ns to 50 ns” on

page 39

“Loss of Sync with External 16517 Clock.” on page 40

Error Messages

“Waiting for Trigger” on page 36

“Maximum of 32 Channels Per Label” on page 37

“Using Default 16517/18 Skew Values.” on page 37

“16517/18 Skew Values are from a Different Instrument” on page 38

“16517/18 Memory System Failed -- Replace Card(s)” on page 38

Chapter 1: Agilent Technologies 16517A/18A 4GHz Timing/1GHz State Logic Analyzer

When Something Goes Wrong

“Invalid 16517/16518 Card Configuration.” on page 38

“Cannot Run. External 16517 Clock Period Should be 1 ns to 50 ns” on

page 39

“Measurement Halted in Sequence Level N.” on page 39

“External Clock Out of Spec.” on page 40

“Loss of Sync with External 16517 Clock.” on page 40

“NOTE: Trigger Sequencer Will Not See Oversampled States.” on page 41

“NOTE: 500 MHz Trigger Sequencer Rate Exceeds Sample Rate.” on

page 41

“NOTE: Sample Rate Exceeds 500 MHz Trigger Sequencer Rate.\” on page 41

“Pod XX identified” on page 41

Skew-related Messages

“Data Channels (X....X..) Are Not Connected Properly” on page 42

“The Clock is Not Connected Properly” on page 42

“16517/18 Skew Values Do Not Match Slot Configuration.” on page 43

“16517/18 Skew Values Are From Different Instrument.” on page 43

“Using Default 16517/18 Skew Values.” on page 43

“Invalid 16517/18 Skew Values.” on page 44

Waiting for Trigger

This message indicates that the specified trigger pattern has not occurred. This may be expected, as when you are waiting to trigger on an unusual event.

Possible Causes

• Misaligned boundaries for addresses

When the target is a microprocessor that fetches only from long-word aligned addresses, if the trigger is set to look for an opcode fetch at an

Chapter 1: Agilent Technologies 16517A/18A 4GHz Timing/1GHz State Logic Analyzer

When Something Goes Wrong

address that is not properly aligned, the trigger will never be found.

• Trigger set incorrectly

Some strategies you can use when verifying or debugging trigger sequence levels are:

• Look at the run status message line or open the Run Status window. It will tell you what level of the sequence the logic analyzer is in.

• Stop the measurement and look at the data that was captured.

• Save the trigger setup, then simplify it to see what part of the sequence

does get captured. When you learn what needs to be changed, you can recall the original trigger setup and make changes to it.

See Also “Saving and Recalling Trigger Sequences” on page 59

Maximum of 32 Channels Per Label

The logic analyzer can only assign up to 32 channels for each label. If you need more than 32 channels, assign them to two labels and use the labels in conjunction.

See “Adding and Deleting Labels for Terms” on page 75 for how to use more than one label with trigger terms.

Using Default 16517/18 Skew Values.

Possible Causes

The 16517A 4 GHz Timing/1 GHz State logic analyzer functions best when its channels have been deskewed. This message warns you that the logic analyzer has been moved since it was last deskewed and that measurements might be off.

To deskew the channels, go to the logic analyzer window, select the Skew Adjust tab, and follow the instructions.

See Also Using the Agilent Technologies 16517A Logic Analyzer (see the Agilent

Technologies 16517A 4GHz Timing/1GHz State Logic Analyzer help

volume)

Chapter 1: Agilent Technologies 16517A/18A 4GHz Timing/1GHz State Logic Analyzer

When Something Goes Wrong

16517/18 Skew Values are from a Different Instrument

Possible Causes

• Logic analyzer was last deskewed in a different frame

The 16517A logic analyzer is very sensitive to changes in its environment. If you move the logic analyzer from an Agilent Technologies 16500C frame to an Agilent Technologies 16700A/B-series frame, or between a 16600Aseries and 16700A/B-series frame, you should deskew the channels before making measurements.

To deskew the channels, go to the logic analyzer window, select the Skew Adjust tab, and follow the instructions.

See Also Using the Agilent Technologies 16517A Logic Analyzer (see the Agilent

Technologies 16517A 4GHz Timing/1GHz State Logic Analyzer help

volume)

16517/18 Memory System Failed -- Replace Card(s)

The memory system on the card specified has failed. If your 16517A or 16518A is still under warranty, contact your Agilent Technologies Sales Office for repair.

Invalid 16517/16518 Card Configuration.

This message appears on power-up if the logic analyzer module is not cabled together properly.

Possible Causes • An 16518A is in the frame but not part of a module

The 16518A is strictly an expansion card. It cannot be used on its own without an 16517A.

• The cables connecting the cards of the module are on the wrong side.

• When the expansion card is above the 16517A master card, use the

connector on the left side of the cards.

• When the expansion card is below the 16517A master card, use the connector on the right side of the cards.

• When the 16517A master card is between expansion cards, use the

Chapter 1: Agilent Technologies 16517A/18A 4GHz Timing/1GHz State Logic Analyzer

When Something Goes Wrong

connector on the left for the cards above the master card and the connector on the right for the cards below the master card.

"Left" and "right" are when looking at the back of the mainframe.

• You have more than two expansion cards either above or below the 16517A

master card.

One end of the interconnect cables must be connected to the 16517A master card. Since the longest cable has three plugs, this means you can have no more than two cards on either side of the master card.

• You are trying to use an 16517A master card as an expansion card.

The 16517A master card cannot be used as an expansion card. Each module should contain only one 16517A.

See Also Agilent Technologies 16517A/18A User’s Reference

Cannot Run. External 16517 Clock Period Should be 1 ns to 50 ns

This message only appears in state mode.

Possible Causes • The clock channel is not connected properly.

• The target system clock period is greater than 50 ns. (Slower than 20

MHz.)

If your target system was running near 20 MHz, the capacitive load from the logic analyzer could slow it down further than 20 MHz.

• The target system clock period is less than 1 ns. (Faster than 1 GHz.)

The Agilent Technologies 16517A/18A logic analyzer is only capable of 1 GHz in state mode. For faster speeds, you need to use timing mode.

Measurement Halted in Sequence Level N.

This message occurs when the Agilent Technologies 16517A/18A logic analyzer was stopped before it triggered.

Possible Causes • You pressed Stop.

If the message bar was displaying "Waiting for Trigger" when you pressed

Chapter 1: Agilent Technologies 16517A/18A 4GHz Timing/1GHz State Logic Analyzer

When Something Goes Wrong

Stop, the logic analyzer had not yet found its trigger event. The level is the level in the trigger sequence in which it was waiting.

• A fatal error occurred.

Some error conditions, such as skew values from a different instrument, are serious enough to cause the logic analyzer to halt a run.

See Also “Using Default 16517/18 Skew Values.” on page 37

“16517/18 Skew Values are from a Different Instrument” on page 38

“Cannot Run. External 16517 Clock Period Should be 1 ns to 50 ns” on

page 39

External Clock Out of Spec.

This message only occurs in state mode.

Possible Causes • The target system clock is slightly greater than 50 ns.

• The target system clock is slightly less than 1 ns.

The period of the target system clock is not in the preferred range of 1 ns to 50 ns, but is close enough that the Agilent Technologies 16517A/ 18A logic analyzer can still run. The data may not be valid, however.

See Also “Cannot Run. External 16517 Clock Period Should be 1 ns to 50 ns” on

page 39

Loss of Sync with External 16517 Clock.

This message only occurs in state mode when the logic analyzer loses the clock signal.

Possible Causes • The clock probe has been disconnected.

Check the target system to make sure the clock probe is still firmly connected to the clock channel of your target system.

• The target system is not running.

Look for activity indicators for the data channels. If they had been showing activity and no longer do, the target system may need to be reset.

Chapter 1: Agilent Technologies 16517A/18A 4GHz Timing/1GHz State Logic Analyzer

When Something Goes Wrong

• The voltage threshold level of Pod 1 has been changed.

The clock channel is on Pod 1 of the master card. If the voltage threshold level is changed for the data channels, it will also change the voltage threshold for the clock channel. Check the Format tab to see if it is set properly.

NOTE: Trigger Sequencer Will Not See Oversampled States.

This message appears when you set the Samples/Clock control (available under the Trigger tab in state mode only) to something other than 1.

It is a warning that only states that are synchronous with the clock on the target system will be evaluated in the trigger sequence.

See Also “Oversampling: the Samples/Clock Control” on page 77

NOTE: 500 MHz Trigger Sequencer Rate Exceeds Sample Rate.

In timing mode, you have set the sample period to a value greater than 2 ns (slower than 500 MHz). This message lets you know that you could sample data at a faster rate.

NOTE: Sample Rate Exceeds 500 MHz Trigger Sequencer Rate.\

Trigger May Not Be Included In Acquired Data

In timing mode, you have set the sample period to a value less than 2 ns (faster than 500 MHz).

Because data will be sampled faster than the trigger sequencer can evaluate it, the trigger may not be included in the acquired data.

See Also “Suspicious Data” on page 44

Pod XX identified

This message appears in the logic analyzer window when the Pod ID button on the side of a pod is pressed. The "XX" is replaced with the

Chapter 1: Agilent Technologies 16517A/18A 4GHz Timing/1GHz State Logic Analyzer

When Something Goes Wrong

letter of the slot the card is in, and 1 or 2 to identify the pod.

The message goes away when the logic analysis system detects a mouse movement.

See Also “Probing System Description” on page 13

Data Channels (X....X..) Are Not Connected Properly

This message only appears when you run the Skew Adjust procedure, and one or more data channels of the pod being tested are not connected.

The X in the message refers to the channel that is not connected, with the leftmost position referring to channel 1 of the pod being adjusted.

Make sure that all pod probes are plugged completely into the calibration pod. (The top of the probe should completely fill the slot showing on top of the calibration pod.) Select the Continue button in the Pod Connections dialog. If the warning message still appears and the referenced probe is completely plugged in, the probe hardware is broken.

See Also “Adjusting Skew” on page 16

The Clock is Not Connected Properly

This message appears if you attempt to adjust skew without connecting the clock probe to the calibration pod.

There is only one probe labeled Clk per 16517A/18A module, and it is on pod 1 of the 16517A card. The clock probe must remain plugged into the calibration pod through the entire skew adjust procedure.

If the clock probe is completely plugged into the calibration pod and you still get this message, the clock channel hardware may be bad.

Contact your Agilent Technologies sales office for information on repairing the 16517A card.

See Also “Adjusting Skew” on page 16

Chapter 1: Agilent Technologies 16517A/18A 4GHz Timing/1GHz State Logic Analyzer

16517/18 Skew Values Do Not Match Slot Configuration.

This message appears when the logic analysis system is turned on if the 16517A/18A skew values do not match. The skew values are stored in NV-RAM on the 16517A card.

Possible causes

• The arrangement of 16518A expansion cards changed.

• The module was moved to another slot of the frame.

To correct this situation, run the Skew Adjust procedure.

See Also “Adjusting Skew” on page 16

16517/18 Skew Values Are From Different Instrument.

This message appears when the logic analysis system is turned on if the 16517A/18A skew values are not valid for the current instrument (Agilent Technologies 16700A/B-series frame).

When Something Goes Wrong

Possible causes

• The 16517A/18A module was moved from one frame to another.

The skew values are stored in NV-RAM on the 16517A card and are preserved when the module is moved from one type of analysis frame to another. Because the different frame types have different internal wiring, the skew factors need to be readjusted.

To correct this situation, run the Skew Adjust procedure.

See Also “Adjusting Skew” on page 16

Using Default 16517/18 Skew Values.

This warning message appears when you start a run if the skew values are set to factory defaults. The factory default skew adjustments are good enough to allow the module to run, but may cause inaccuracies in data correlation.

Chapter 1: Agilent Technologies 16517A/18A 4GHz Timing/1GHz State Logic Analyzer

When Something Goes Wrong

Possible Causes

• The skew factors in NV-RAM aren't valid.

You could have invalid skew factors if the module were moved within the frame or if expansion cards were added or removed.

• There were no skew factors in NV-RAM.

Until you perform the skew adjust procedure, no skew factors are stored in NV-RAM.

To correct this situation, run the Skew Adjust procedure.

See Also “Adjusting Skew” on page 16

Invalid 16517/18 Skew Values.

This message appears when the skew values in NV-RAM fail a checksum test.

Possible Causes

• The module was last deskewed in an Agilent Technologies 16500 frame.

• The skew factors have been corrupted.

To correct this situation, run the Skew Adjust procedure.

See Also “Adjusting Skew” on page 16

Suspicious Data

Intermittent Data Errors

Unexpected State at Trigger Point

Check for poor connections, incorrect signal levels on the hardware, incorrect logic levels under the logic analyzer’s Format tab, or marginal timing for signals.

If you are using oversampling in state mode, only the states synchronous with the external clock are evaluated by the trigger sequence. The event you expected may have occurred but not been evaluated. Try setting up the same trigger in timing mode.

Chapter 1: Agilent Technologies 16517A/18A 4GHz Timing/1GHz State Logic Analyzer

When Something Goes Wrong

Unwanted Triggers

If you are using an inverse assembler or a pipeline, triggers can be caused by instructions that were fetched but not executed. To fix, add the prefetch queue or pipeline depth to the trigger address.

The depth of the prefetch queue depends on the processor that you are analyzing, and can be quite deep.

Another solution which is sometimes preferred with very deep prefetch queues is to add writes to dummy variables to your software. Put the instruction just before the area you want to trigger on, then trigger on the actual write to this variable. Although the instruction is prefetched, the analyzer can be set to only trigger when the write is executed.

See Also “Oversampling: the Samples/Clock Control” on page 77

Interference with Target System

Capacitive Loading on the Target System

Excessive capacitive loading can degrade signals, resulting in suspicious data or even system lockup. All analysis probes add capacitive loading, as can custom probes you design for your target. To reduce loading, remove as many pin protectors, extenders, and adapters as possible.

Careful layout of your target system can minimize loading problems and result in better margins for your design.

Chapter 1: Agilent Technologies 16517A/18A 4GHz Timing/1GHz State Logic Analyzer

Testing the Logic Analyzer Hardware

In order to verify that the logic analyzer hardware is operational, run the Self Test utility. The Self Test function of the logic analysis system performs functional tests on both the system and any installed modules.

1. If you have any work in progress, save it to a configuration file. (see the

Agilent Technologies 16700A/B-Series Logic Analysis System help volume)

2. Select the System Admin button.

3. Select the Admini tab, then select the Self Test... button.

The system closes all windows before starting up Self Test.

4. Select Master Frame. If the module is in an expansion frame, select Expansion Frame.

5. Select the 16517A 4GHz Timing/1 GHz State logic analyzer that you want to test.

6. In the Self Test dialog box, select Te s t A l l . You can also run individual tests by selecting them. Tests that require you to do something must be run this way.

If any test fails, contact your local Agilent Technologies Sales Office or Service Center for assistance.

See Also Self Test (see the Agilent Technologies 16700A/B-Series Logic Analysis

System help volume)

Agilent Technologies 16517A/18A 4GHz Timing/1GHz State Service Guide

Chapter 1: Agilent Technologies 16517A/18A 4GHz Timing/1GHz State Logic Analyzer

The Format Tab

Format offers control of the internal resources of the logic analyzer. Format selections tell the logic analyzer:

• Whether it will use the full-channel or half-channel data capture mode.

• What is the maximum rate of the sampling clock during measurements.

• Which logic levels to use to interpret captured data.

• What signals are grouped together.

•“Setting the Acquisition Mode” on page 47

•“Defining Labels: Mapping Analyzer Channels to Your System” on page 49

See Also “Working with Labels” on page 50

The Format Tab

“Setting the Pod Threshold” on page 53

“Activity Indicators” on page 54

“Setting the State Clock” on page 48 (State Only)

“State Clock Sample Offset” on page 49 (State Only)

Setting the Acquisition Mode

The acquisition mode sets whether the analyzer uses an internal or external clock to determine when to get data from the target system. This setting also controls the channel width, memory depth, and maximum sampling rate.

In timing acquisition mode the analyzer stores measurement data at each sampling interval, using its own internal clock. In state acquisition mode, the analyzer stores measurement data at each clock edge of the target system.

Chapter 1: Agilent Technologies 16517A/18A 4GHz Timing/1GHz State Logic Analyzer

The Format Tab

To Set the Acquisition Mode

1. Select the sampling mode option button.

2. Choose the option you want. See the references below for more detail on the choices.

State Mode Full Channel 1 GHz

The synchronous state acquisition mode requires an external clock. Both pods are available on all configured cards. Memory depth is 64 Ksamples per channel.

Timing Mode Full Channel 2 GHz

Both pods are available on all cards. Memory depth is 64 Ksamples per channel. The logic analyzer samples at up to 2 GHz.

Timing Mode Half Channel 4 GHz

Both pods are restricted to bits 0 - 3. Memory depth is doubled to 128 K samples per channel. The logic analyzer samples at 4 GHz, and the speed cannot be adjusted.

When you switch from half-channel to full-channel mode, you are asked if you want to restore bits 4 - 7. A ’Yes’ answer restores these bits in their previous setting.

See Also (State only) “Setting the State Clock” on page 48

“State Clock Sample Offset” on page 49

Setting the State Clock

In the State Acquisition mode, the analyzer is controlled by the state clock channel of Pod 1 on the master card. You can set the logic analyzer to sample the data on either the rising or falling edge of the target system clock.

To Set the State Clock

1. Select the Clock option button.

2. Choose either Rising or Falling.

Chapter 1: Agilent Technologies 16517A/18A 4GHz Timing/1GHz State Logic Analyzer

The Format Tab

State Clock Sample Offset

Sample offset... adjusts the relative position of the clock edge with respect to the time the data is sampled.

To Change Sample Offset

1. Select the Sample offset... button.

2. Choose Coarse - All pods, Fine - All pods, or Fine - Individual pods.

"Coarse" has a 200-ps granularity, and "fine" has a 50-ps granularity.

3. Adjust the offset. The arrow indicates where the data will be sampled relative to the clock edge. If the mode is Fine - Individual pods, there is an arrow for each pod.

4. Select the Close button.

NOTE: Changing the mode to All pods will erase any offset changes you have made to

the individual pods.

NOTE: The Fine modes are limited to ±500 ps from the Coarse setting.

Defining Labels: Mapping Analyzer Channels to Your System

Labels group channels with a name that is relevant to your system under test. Both data channels and clock channels from more than one pod can be included in a single label, but labels with clock channels or channels from more than one pod cannot be included in range terms.

You can define 126 labels per analyzer. Each label can contain up to 32 channels per label.

To Define a Label

1. Select the label name button and choose Rename.

2. Enter a new name and select the OK button.

Chapter 1: Agilent Technologies 16517A/18A 4GHz Timing/1GHz State Logic Analyzer

The Format Tab

3. Assign bits (see page 50) to the label.

4. If necessary, insert more labels (see page 52) in the list.

See Also “Working with Labels” on page 50

Working with Labels

Labels are used to group and identify logic analyzer channels so that you can easily remember what signals the various logic analyzer channels refer to.

•“Assigning Bits to a Label” on page 50

•“Reordering the Bits in a Label” on page 51

•“Inserting and Deleting Labels” on page 52

•“Turning Labels On and Off” on page 52

•“Label Polarity” on page 53

Assigning Bits to a Label

The bits in a label correspond to the physical logic analyzer probe channels. When you run the analyzer, data is gathered on all bits (channels) that are assigned to labels. Unassigned bits are inactive.

( * ) (asterisk) indicates an assigned bit.

( . ) (period) indicates an unassigned bit.

To Assign Bits

1. Select the bit assignment button to the right of the label name you want to define. Each bit assignment button corresponds to the data pod which is listed

Chapter 1: Agilent Technologies 16517A/18A 4GHz Timing/1GHz State Logic Analyzer

above it.

2. Either choose one of the predefined groups, or choose Individual.

3. In Individual, select the bits to toggle them between an asterisk and a

period. You can also hold the left mouse button and move the mouse to assign several bits at once.

NOTE: Labels can have a maximum of 32 channels assigned to them.

Bits assigned to a label are numbered from right to left. The least significant assigned bit on the far right is numbered 0. The next assigned bit to the left is numbered 1, and so on. Labels can contain bits that are not consecutive; however, bits are always numbered consecutively within a label. Above each column of bit assignment fields is a bit reference line that shows you the bit numbers and activity indicators.

The Format Tab

See Also “Activity Indicators” on page 54

Reordering the Bits in a Label

The bit reorder feature allows the channel order, as it appears in the label, to be assigned independently of the physical order. This feature allows the probe tips for each channel to be physically connected where convenient. The Reorder function can then be used to logically rearrange the bits in a label.

To Reorder the Bits in a Label

1. Select the label name button that you want to reorder.

2. Choose Reorder Bits.

3. Set the bit order by using one of the following options:

• To reorder the bits individually, for each channel, enter the number of

the bit you want to map the channel to. You can also use the Spin Buttons to scroll through the list of bits.

• To arrange the bits sequentially, select the button at the top of the

dialog, then choose Default Order.

Chapter 1: Agilent Technologies 16517A/18A 4GHz Timing/1GHz State Logic Analyzer

The Format Tab

• To swap the high and low order bytes or words, select the button at the

top of the dialog, then choose Big-Endian/Little-Endian.

NOTE: Reordered labels can not be used as range terms in triggers.

Inserting and Deleting Labels

To Insert Additional Labels

1. Select the label name button that you want to insert another label next to.

2. Choose Insert before... or Insert after....

To Delete Labels

1. Select the label name button that you want to delete.

2. Choose Delete.

Turning Labels On and Off

You may want to turn off labels that you have created so that the label is not displayed. When a label is turned off, its name and bit assignments are preserved.

To Turn Off a Label

1. Select the button of the label that you want to turn off.

2. Choose Label [ON] to toggle it off.

To Turn On a Label

1. Select the button of the label that you want to turn on.

2. Choose Label [OFF] to toggle it on.

To Display a Label that was Off

1. Turn on the label.

2. At the bottom of the window, select the Apply button. The label's data appears in the display windows.

Chapter 1: Agilent Technologies 16517A/18A 4GHz Timing/1GHz State Logic Analyzer

The Format Tab

Label Polarity

The analyzer uses the label polarity to identify patterns and edges when triggering on and storing data. The default polarity for all labels is positive (+). Setting the polarity to negative (-) inverts the logic for all bits in a label.

To change the label polarity, select the polarity field, which toggles between positive (+) and negative (-).

NOTE: It is rare that negative logic would be used on a circuit. If the negative logic

parameter is applied to a positive logic circuit, unpredictable results will be obtained.

Setting the Pod Threshold

The pod threshold is a voltage level which the data must cross before the analyzer recognizes it as a change in logic levels. You can specify a threshold level for each pod. The level specified for the master pod that includes the clock is also used for the clock threshold.

To Set the Threshold

1. Under the Format tab, select the threshold option button.

The threshold option button is located just below the pod name.

2. Choose one of the threshold options described below.

3. Repeat steps 1 and 2 for the other pods.

NOTE: The clock threshold level is the same as the level assigned in the Pod

Threshold field.

TTL

The threshold level is +1.5 volts.

ECL

The threshold level is -1.3 volts.

Chapter 1: Agilent Technologies 16517A/18A 4GHz Timing/1GHz State Logic Analyzer

The Format Tab

USER

When USER is selected, the threshold level is selectable from -5.0 volts to +5.0 volts.

Activity Indicators

Activity indicators are located above the column of bit assignment fields. When the logic analyzer is properly connected to an active target system, you see dashes and arrows in the Activity Indicator displays for

each channel. An active channel looks like .

A dash at the top of the activity indicator display indicates that the signal connected to that channel is at a logic high. A dash at the bottom indicates that the signal is at a logic low. An arrow indicates that the signal is transitioning.

You can use these indicators to check whether there is proper probe connection: bits that are stuck low may not be properly connected. You can also verify that the signals in your target system are active: bits that are stuck high or low may not be crossing the threshold voltage.

Activity indicators are not displayed during an acquisition.

Chapter 1: Agilent Technologies 16517A/18A 4GHz Timing/1GHz State Logic Analyzer

The Trigger Tab

The Trigge r tab is used to set up a sequence of steps that determine when the analyzer triggers. At the top is a control area where you specify how much data to store before and after the trigger. In the trigger sequence area, you specify the conditions that you want the analyzer to trigger on. In the resource terms area at the bottom of the window, you define variables for use in the trigger sequence specification.

•“Setting Up a Trigger” on page 55

•“Adding and Deleting Sequence Steps” on page 57

•“Editing Sequence Steps” on page 58

•“Setting Up Loops and Jumps in the Trigger Sequence” on page 58

•“Saving and Recalling Trigger Sequences” on page 59

•“Clearing Part or All of the Trigger” on page 60

See Also “Overview of the Trigger Sequence” on page 61

“Predefined Trigger Macros” on page 62

“Working with User-Defined Macros” on page 68

“Defining Resource Terms” on page 71

“Trigger Position Control” on page 76

“Oversampling: the Samples/Clock Control” on page 77

“Sample Period (Timing Only)” on page 77

“Arming Control” on page 78

Setting Up a Trigger

When setting up a trigger sequence, you typically trigger first on a simple pattern or edge. From that point, you execute an iterative

Chapter 1: Agilent Technologies 16517A/18A 4GHz Timing/1GHz State Logic Analyzer

The Trigger Tab

process of adding or fine-tuning sequence steps until the analyzer consistently triggers at the desired point.

To Set Up a Trigger

1. Define resource terms. (see page 71)

2. Select the first sequence level button; choose Edit. (see page 56)

3. Select the Select new macro button, and select the most appropriate macro. (see page 56)

4. Edit the sequence step. (see page 58)

5. If necessary, add/edit additional sequence steps. (see page 57)

See Also “Predefined Trigger Macros” on page 62

“Working with User-Defined Macros” on page 68

“Overview of the Trigger Sequence” on page 61

Selecting the Edit of a Sequence Step

To modify a Trigger Sequence Step, select the number button of the level that needs to be modified, and choose Edit.

Selecting a Macro to Match Trigger Conditions

Review the list of macros and select the one that matches the desired trigger conditions. In most cases one of the predefined macros will satisfy trigger conditions. If none of the predefined macros match choose the User level macro.

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Selecting a Macro from the List

See Also “Predefined Trigger Macros” on page 62

Adding and Deleting Sequence Steps

To Add Sequence Steps

1. Select the number button of the level that you want to insert other levels around.

2. Choose Insert Before or Insert After.

3. Select a macro for the new step.

To Delete Sequence Steps

1. Select the number button of the level that you want to delete.

The Trigger Tab

Trigger Sequence Editing Options

2. Choose Delete.

When you select a sequence level number button, you see a selection menu with choices that allow you to modify the sequence. Choose the option you want from the choices below.

• Edit

Changes the contents of the sequence step. You can change the resource terms or other assignment fields, such as durations and occurrences.

• Copy

Copies the currently selected step. When you copy a level, the new level contains the same macro or user-defined step as the original.

• Replace

Replaces the currently selected level. When you replace a level, you pick a new macro or user-level, and it then replaces the old one.

• Delete

Deletes the level that is currently selected.

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• Insert Before / Insert After

Inserts an additional step before or after the selected step.

Editing Sequence Steps

You can modify the contents of a step in the trigger sequence by editing it.

To Edit a Sequence Step:

1. Select the sequence level number button and choose Edit....

2. To change the macro, select the Select new macro button and choose a

different macro from the list.

3. Select a resource term name to choose a different resource term.

You can also choose negations of terms and combinations of terms.

4. Set the values of the other fields, such as durations and occurrence counts.

5. Select the OK button to close the sequence step editing dialog.

If you are editing a user-defined step, refer to:

“Setting Pattern Durations” on page 69

“Using Occurrence Counters” on page 70

“Setting Up Loops and Jumps in the Trigger Sequence” on page 58

Setting Up Loops and Jumps in the Trigger Sequence

To set up loops and jumps in your trigger sequence, use Branches. Branches are available in most of the Predefined Macros and UserDefined (see page 68) sequence steps. You may need to break down the macros (see page 67) in order to set up branches.

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To Set Up a Branch or Loop

1. Select the Find button and choose the term that you want to branch on. The analyzer will take the branch if this term is found.

2. Select the go to option button and choose the sequence level that you want to branch to.

3. If you want a secondary branch, select the Else on button and choose the term that you want to branch on.

4. Select the go to option button and choose the sequence step that you want to branch to.

The analyzer starts at the first trigger sequence level. It evaluates the data coming from the target system and when the term of either the find or else on branch becomes true, follows that branch to the next specified level (or triggers). If you are using oversampling, remember that oversampled states are not evaluated.

Timers and occurrence counters are reset when a branch is taken, even if it loops back to the same level.

If both branches become true at the same time, the primary (find) branch is taken. Once the analyzer triggers, it stops evaluating data and simply fills its memory. When the acquisition memory is full, the logic analyzer stops and any analysis or display tools connected to it process the data set.

Saving and Recalling Trigger Sequences

You can save a trigger setup independently of configuration files within a session. Recalling the stored trigger sequence specification can change the trigger arming, memory depth, and trigger position as well as the trigger sequence and term definitions. The trigger sequence specification will not change the acquisition mode (full channel vs. half channel).

The Agilent Technologies 16517A/18A logic analyzer can hold up to 10 trigger sequence specifications for State or Timing mode, for a total of 20 specifications. When you exit your Agilent Technologies 16700A/B-

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series session, the trigger sequences are cleared. They can be saved across sessions or be shared among multiple modules as part of a configuration file, however.

To Save a Trigger Sequence

1. Enter a name for the trigger sequence in the Title field just above the trigger sequence area.

2. Select the Save button.

3. Choose a memory location to store the trigger sequence in.

To Recall a Trigger Sequence

1. Select the Recall button.

2. Choose the trigger sequence that you want.

Clearing Part or All of the Trigger

To Clear Part or All of the Trigger:

1. Select Clear from the menu bar.

2. Choose the option you want from the choices described below:

• All

Clears sequence steps, resource terms, and resource term names back to their default values.

• Sequence Levels

Resets the trigger sequence to a default sequence.

• Resource Terms

Resets all resource term assignment fields, including labels and values back to their default values.

• Resource Term Names

Resets all the resource term names to their default values.

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• Store/Recall Memories

Deletes all saved trigger sequence specifications.

Overview of the Trigger Sequence

The trigger sequence is a sequence of steps that control the path that the analyzer takes to find the trigger point. The path taken resembles a flow chart, with each step in the sequence being an opportunity to direct the analyzer’s selection process in the desired direction. You can edit the overall trigger sequence by adding or deleting sequence steps (see page 57).

Each step in the sequence is either a predefined macro (see page 62) or a user-defined step (see page 68). Both the predefined macros and user-defined steps contain variables that you define. The variables, called resource terms (see page 71) represent edges and bit patterns in the data.

When you run the analyzer, it searches for a match between the resource term values and the measurement data. When a match is found, the sequencing continues to the next step, loops back (see page 58) to a previous step, or jumps ahead (see page 58) to another step. Eventually, a path of "true" steps leads to the trigger point.

Each macro uses one or more of the analyzer’s internal sequence levels (see page 61). Each user-defined step uses one internal sequence level.

See Also “Setting Up a Trigger” on page 55

How the Internal Sequence Levels Are Used

The analyzer has four internal sequence levels that it uses to make up the trigger sequence. The levels are used differently, depending on whether you use predefined trigger macros or user-defined steps to construct your trigger sequence.

When you use user-defined steps (see page 68), all of the internal sequence levels are available. Each user-defined sequence level corresponds to one internal level.

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When you use predefined trigger macros (see page 62), more than one of the internal sequence levels may be required for a single macro. The exact number of internal levels required per macro is shown in the macro library list. Even though some trigger macros use multiple sequence levels, macros are easier to use, and they are the most efficient way to construct a trigger sequence.

Predefined Trigger Macros

Trigger macros provide a simple way to set up the analyzer to trigger on common events and conditions. A library of macros is available for both the state and timing acquisition modes.

NOTE: Each macro requires at least one internal sequence level (see page 61), and in

some cases, may require multiple levels. The number of levels used by each macro is described in the macro library.

Timing Trigger Macro Library

State Trigger Macro Library

See Also “Setting Up a Trigger” on page 55

“Timing User Mode” on page 63

“Basic Timing Macros” on page 63

“Pattern/Edge Combinations” on page 64

“Setup and Hold Violations” on page 64

“Time Violations” on page 65

“State User Mode” on page 65

“Basic State Macros” on page 66

“Sequence-Dependent Macros” on page 66

“Time Violations” on page 67

“Defining Resource Terms” on page 71

“Breaking Down and Restoring Macros” on page 67

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Timing User Mode

(user-defined macro)

The User level allows you to create a custom trigger sequence using a trigger term, comparison function, and a jump or loop. This macro uses one internal sequence level.

See Also Working with User-Defined Macros (see page 68) for more information on

the user-defined mode.

Basic Timing Macros

The following basic macros are found in the Macro selection window when the analyzer is in the Timing mode. Each macro uses one internal sequence level.

• Find anystate n times.

This macro becomes true with the nth state it sees. It uses one internal sequence level.

• Find pattern present/absent for > duration.

This macro becomes true when it finds a pattern you have designated that has been present or absent for greater than or equal to the set duration. It uses one internal sequence level.

• Find pattern present/absent for < duration.

This macro becomes true when it finds a pattern you have designated that has been present or absent for less than the set duration. It uses one internal sequence level.

• Find edge.

This macro becomes true when the edge you have designated is seen. It uses one internal sequence level.

• Find Nth occurrence of pattern present/absent for > duration

This macro becomes true when it finds the Nth occurrence of a pattern that has been present or absent for greater than or equal to the set duration. Each valid pattern occurrence is only counted once, even though the same occurrence may be valid for multiple sample clocks. It uses one internal sequence level.

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• Find nth occurrence of an edge.

This macro becomes true when it finds the designated occurrence of an edge you have selected. Note that the 500-MHz trigger sequencer may not count edges that occur closer than 2 ns. This macro uses one internal sequence level.

Pattern/Edge Combinations

The following macros are found in the Macro selection window when the analyzer is in the Timing mode. These predefined macros use a pattern, edge, or a combination of both as the trigger element. These macros use either one or two internal sequence levels.

• Find edge within a valid pattern.

This macro becomes true when a selected edge type is seen within the time window defined by a pattern you have designated. It uses one internal sequence level.

• Find pattern occurring too soon after edge.

This macro becomes true when a pattern you have designated is seen occurring within a set duration after a selected edge type is seen. It uses two internal sequence levels.

• Find pattern occurring too late after edge.

This macro becomes true when one edge type you have selected occurs, and for a designated period after that first edge is seen, a pattern is not seen. It uses two internal sequence levels.

Setup and Hold Violations

• Find setup or hold violation

This macro becomes true when there is a change on a selected group of channels which violates the specified setup or hold time criteria with respect to a selected edge. It uses two internal sequence levels.

• Find setup or hold violation clocked by an edge within a valid pattern

This macro becomes true when either a designated setup or a hold criterion is violated on a selected group of channels which are being clocked by a selected edge which appears within a designated pattern. It

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uses two internal sequence levels.

• Find setup or hold violation clocked by a pattern/pulse

This macro becomes true when there is a change on a selected group of channels which violates the specified setup or hold time criteria with respect to a selected pattern. It uses three internal sequence levels.

Time Violat ion s

The following macros are found in the Macro selection window when the analyzer is in the Timing mode. These predefined macros are specifically tailored to trigger on events occurring out of a predefined time range. These macros use either one or two internal sequence levels.

• Find 2 edges too close together.

This macro becomes true when a second selected edge is seen occurring within a period you have designated after the occurrence of a first selected edge. It uses two internal sequence levels.

• Find 2 edges too far apart.

This macro becomes true when a second selected edge occurs beyond a period you have designated after the first selected edge. It uses two internal sequence levels.

• Find width violations on a pattern/pulse.

This macro becomes true when the width of a pattern violates minimum and maximum width settings you have designated. It uses one internal sequence level.

• Wait t sec.

This macro becomes true after a period you have designated has expired. It uses one internal sequence level.

State User Mode

(User-defined macro)

The User level allows you to create a custom trigger sequence using a trigger term, comparison function, and a jump or loop. This macro

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uses one internal sequence level.

See Also Working with User-Defined Macros (see page 68) for more information on

the user-defined mode.

Basic State Macros

The following basic macros are found in the Macro selection window when the analyzer is in the State mode. Each macro uses one internal sequence level.

• Find anystate n times.

This macro becomes true with the nth state it sees. It uses one internal sequence level.

• Find pattern n times.

This macro becomes true when it sees an event you have designated occurring a designated number of times. The events may occur consecutively, but do not have to. It uses one internal sequence level.

• Find pattern n consecutive times.

This macro becomes true when it sees an event you have designated occurring a designated number of consecutive times. It uses one internal sequence level.

• Find pattern2 immediately after pattern1.

This macro becomes true when the first event you have designated is seen immediately followed by a second designated event. It uses two internal sequence levels.

Sequence-Dependent Macros

The following basic macros are found in the Macro selection window when the analyzer is in the State mode. These macros each trigger on a particular sequence of events.

• Find patt2 n times after patt1, before patt3 occurs.

This macro becomes true when it first finds a designated patt1, followed by a selected number of occurrences of a designated patt2. In addition, if a designated patt3 is seen anytime while the sequence is not yet true, the

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sequence starts over. If patt2’s nth occurrence is coincident with patt3, the sequence starts over. It uses two internal sequence levels.

• Find too few states between pattern1 and pattern2.

This macro becomes true when a designated pattern1 is seen, followed by a designated pattern2, and with fewer than a selected number of states occurring between the two events. It uses two internal sequence levels.

• Find too many states between pattern1 and pattern2.

This macro becomes true when a designated pattern1 is seen, followed by more than a selected number of states, before a designated pattern2. It uses two internal sequence levels.

Time Violations

The following macros are found in the Macro selection window when the analyzer is in the State mode. These predefined macros are specifically tailored to trigger on events occurring out of a predefined time range. These macros use either one or two internal sequence levels.

• Find pattern2 occurring too soon after pattern1.

This macro becomes true when a designated pattern1 is seen, followed by a designated pattern2, and with less than a selected period occurring between the two events. It uses two internal sequence levels.

• Find pattern2 occurring too late after pattern1.

This macro becomes true when a designated pattern1 is seen, followed by at least a selected period, before a designated pattern2 occurs. It uses two internal sequence levels.

• Wait n external clock states.

This macro becomes true after a number of user clock states you have designated have occurred. It uses one internal sequence level.

Breaking Down and Restoring Macros

When you break down a macro, you gain access to all the resource assignment fields and branching options. You can change these fields to change the trigger structure. You might need to do this to create a

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custom trigger sequence or to create loops and jumps.

To Break Down Macros

1. Select Modify in the Trigger window menu bar.

2. Choose Break down macros.

The contents of broken down macros are displayed in the long form used in a user-defined sequence step. If the macro uses two of the analyzer’s internal sequence levels, (see page 61) both levels are separated out and displayed in the trigger sequence area of the Trigger window.

To Restore Macros

1. Select Modify in the Trigger window menu bar.

2. Choose Restore macros.

Use Restore macros to restore all macros to their original structure. Note that when the macros are restored, all changes are lost and any branching that is part of the original structure is restored.

See Also Working with User-Defined Macros (see page 68) for information on

working with macros that are broken down.

Working with User-Defined Macros

NOTE: Before you begin to set up user-defined sequence steps, note that in most

cases one of the predefined trigger macros (see page 62) will work.

You might need to set up a user-defined sequence step to accommodate a condition not covered by the macros, or if you need to set up loops and jumps in the sequence. Each user-defined sequence step has a "fill-in-the-blanks" type statement. You use resource terms to fill in the statement with the appropriate values.

To Set Up a User-Defined Macro

1. Select a sequence level number button; choose Edit.

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2. Select the Select New Macro button; select the User level macro.

3. Select either Occurrence Counter or Tim er.

4. If you selected Occurrence Counter, assign it to the Find or else on

branch. The occurrence counter can only be used in one branch at a time.

5. Select a resource term for the Find branch.

6. Set the occurrence field or timer.

7. Select the goto level button; choose a sequence level or Tr i g g e r.

8. Optional - select a resource term for the else on branch.

9. Select the goto level button; choose a sequence level or Trigger.

10. If you used any pattern terms, set the duration filter.

In the Agilent Technologies 16517A/18A logic analyzer, it is possible to have more than one trigger condition. The logic analyzer does not do any check on the trigger sequence; before running, make sure that the sequence will eventually trigger.

For more information on the functions available in a user-defined step, refer to:

•“Defining Resource Terms” on page 71

•“Setting Pattern Durations” on page 69

•“Using Occurrence Counters” on page 70

•“Using Timer Terms” on page 73

•“Limits on the Number of Simultaneous Terms” on page 74

•“Setting Up Loops and Jumps in the Trigger Sequence” on page 58

Setting Pattern Durations

When a bit pattern is found during a trigger sequence, you can influence when the term actually becomes "true" by assigning a time duration. The Set Pattern Duration statement is available in all sequence levels, but you may have to break down (see page 67) any macros.

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Present/Absent field

This field determines whether the resource term becomes true after being present or absent for the specified time interval.

</> Field

This field allows you to choose whether the pattern duration is longer or shorter than the specified time. When < is selected, the resource is true for one clock cycle after a pattern is present/absent for less than the duration value.

When > is selected, additional control over pattern duration becomes available. This control allows you to pick what happens after the pattern has been present/absent for more than the duration value.

Until exit, Upon exit, Upon entry Field

This part of the Set Pattern Duration statement dictates how long the resource is true after the pattern duration is met. The Until Exit selection keeps the resource true from the time the duration is met, until the end of the pattern. The Upon Entry selection makes the resource true for only one clock cycle after the duration is met. The Upon Exit selection makes the statement true for one clock cycle after the end of the pattern.

Using Occurrence Counters

The occurrence counter is assigned to either the "Find" branch or the "else on" branch. Whatever positive number you assign to the counter, the pattern must be seen that number of times before the term becomes true.

Note that in order to count occurrences of a pattern with a > duration, the Upon Entry or Upon Exit selections should be used. In the Until Exit mode, the occurrence counter is clocked at a 2 ns rate as long as the resource is true, in effect acting like a duration counter.

If the "else on" branch becomes true before all specified occurrences of the primary branch, the secondary "else on" branch is taken.

If you choose to use the occurrence counter in a sequence level, the timer is not available in that level.

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Defining Resource Terms

Resource terms are variables that you can use in defining a trigger sequence. The terms available include bit patterns, edges, counters, and timers.

To Define a Resource Term

1. Select the appropriate tab to bring the group of terms forward.

2. Optional - Select the term name and enter a new name.

3. Optional - Select the label button to the right of the term name and choose

Replace.

4. Select the label that you want to use.

5. Optional - add more labels (see page 75) to the term.

6. Optional - Set the numeric base.

7. Select the term value field to the right of the label name.

8. For pattern terms, enter the term value. For edge terms, assign edges to appropriate bits.

See Also “Using Bit Pattern Terms” on page 71

“Using Edge Terms (Timing Only)” on page 72

“Using Combinations of Terms” on page 73

“Using Timer Terms” on page 73

“Using Occurrence Counters” on page 70

“Adding and Deleting Labels for Terms” on page 75

“Numeric Base” on page 75

“Limits on the Number of Simultaneous Terms” on page 74

Using Bit Pattern Terms

Bit pattern resource terms can be set to match a numeric value or bit pattern on a group of data channels such as a bus. In order for a pattern

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to be found by the analyzer, the input data must match all bits of the pattern that are not defined as Don’t Cares (X). Bit patterns can also be used in a negated form.

To Define a Pattern Term

1. Select the label name to the right of the term name and choose the label

that you want to use.

2. If necessary, add more labels (see page 75) to the term.

3. Select the term value field, to the right of the label name.

4. Enter the pattern for each label. Depending on the base setting, such as hex or octal, some characters will not be accepted. Don’t cares are indicated by an X.

Right-click on any of the bit pattern value fields to quickly assign the pattern term to a preset value. Clear (=X) sets the value to all X (don’t cares). Set (=1) sets the value to all 1s. Reset (=0) sets the value to all 0s.

Using Edge Terms (Timing Only)

Edge terms are only available in the timing acquisition mode. You can set an edge term to match transitions on one or more channels. When you specify an edge on more than one channel, the analyzer logically ORs the edges together. When the analyzer sees a transition that matches any of the ones specified in the edge term, the term becomes true.

The following edge choices are available for each bit:

Rising edge (↑)

Falling edge (

Either rising or falling

↓)

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To Define an Edge Term

1. Select the label name button and choose the label that you want to use.

2. Select the edge value button, to the right of the label name.

3. Set the edge for each channel. Don’t cares are indicated by a (.).

NOTE: After you close the edge term assignment dialog, you may see $ indicators in

the term value field. This symbol indicates that the value can’t be displayed in the selected base. Choose Binary base to see the actual assignments.

Using Timer Terms

Timer options are selected from within sequence levels. The timer term is evaluated as either true or false. A true timer term lets the sequence evaluation continue within the current statement. Because the timer works exclusively for each level it is assigned to, it will not affect any other level or the trigger. However, each sequence level can have its own timer with different values assigned. The timer term options are used in the following ways:

Timer expired

The timer term becomes true when its assigned time expires.

Timer not expired

The timer term is true while the assigned time has not expired. Once expired, the timer term becomes false. This is like negating the timer.

The timer is started as the sequence level is entered. If you return to the same sequence level again, the timer will be restarted. If you choose to use the timer in a sequence level, the occurrence counter is not available in that level.

Using Combinations of Terms

Resource terms can be used in combinations. Combinations use the logical AND and OR functions to combine predefined resource terms.

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To Set Up a Combination

1. Edit the sequence step (see page 58) that you want a combination term to appear in.

2. Select the resource term assignment field that you want to make into a combination.

3. Choose Combo... from the menu of resource terms.

4. In the Combination dialog, select the On/Off/Not option button for each term that you want to use and choose On or Not. Not selects the logical negation of the term.

5. Select the logical operator option buttons and choose a logic operation.

NOTE: The combination of terms is now inserted into the term assignment field. If the

term is too long to fit, the display is truncated.

Limits on the Number of Simultaneous Terms

The analyzer has four internal resources that it uses in trigger sequences. The four resources can be allocated across the four bit patterns and the two edges that are available in timing mode. Since there is a limit of four resources, you can not use all four bit patterns and both edges in a trigger sequence at the same time. It is possible to have all six resource term names assigned to different pattern and edge values; however, you will only be allowed to insert up to four of them in the trigger sequence.

Once you assign the four resources with both a resource term name and a value, the resources can be used either by themselves or in combination with each other.

The actual resource terms available for any particular assignment field varies depending on the acquisition mode, whether the timer or occurrence counter is used, and how many resource terms have already been used in other levels.

Pattern Durations

Pattern duration is assigned per sequence level. This means that you can assign a different duration to the same term name in a different

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sequence level. However, each time you use that same term with different duration values, you use up another resource. In other words, using one resource term four times with different pattern durations is equivalent to using all four resource terms once with the same duration.

Timer/Counters

There is one timer or counter available per sequence level. If you choose to use a timer in one sequence step, the occurrence counter is not available in that same step. On a per-sequence level basis, the timer/counter is either a timer or a counter, but not both.

Adding and Deleting Labels for Terms

Labels are defined in Format, after which they are available throughout the other analyzer areas and attached display tools.

When you use more than one label to define a trigger term, the term conditions must be true on both labels for the term to be true.

To Add a Label to a Resource Term

1. Select the label name button.

2. Choose Insert.

3. Choose the label that you want to add to the resource term.

To Delete a Label from a Resource Term

1. Select the label name button.

2. Choose Delete.

Numeric Base

All labels have a numeric base field next to them. The base choices are Binary, Octal, Decimal, Hex, ASCII, Symbol and Twos Complement.

To Change the Numeric Base

1. Select the base option button.

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2. Choose the base that you want.

NOTE: If the numeric base is changed in one window, the base in other windows may

not change accordingly. For example, the base assigned to symbols is unique, as is the base assigned in the Listing window.

Trigger Position Control

The Trigger Position control determines how much data is stored before and after the trigger occurs for all subsequent acquisitions. The point where the trigger occurred is placed at a specified position relative to the data in memory.

When a Run is started, the analyzer will not look for a trigger until at least the proper percentage of pretrigger data has been stored. After a trigger has been detected, the specified percentage of posttrigger data is stored before the analyzer halts.

The trigger position choices are Start, Center, End, User Defined, or Delay.

• Start

The trigger position is set at the starting point of available memory. This process results in maximum posttrigger data and minimum pretrigger data. Note that there will be a small amount of pretrigger data stored.

• Center

The trigger position is set at the center point of available memory. This results in half pretrigger data and half posttrigger data.

• End

The trigger position is set at the end point of available memory. This results in maximum pretrigger data and minimum posttrigger data. Note that there will be a small amount of posttrigger data stored.

• User Defined

When the trigger position is set to User Defined, a trigger position slider appears. Use this slider to set the trigger position any where between 1%

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and 99%. As the slider is adjusted, the % poststore indicator shows the amount of data that will be stored after the trigger point.

• Delay

This option delays the start of data storage until some time after the trigger. The range of the delay time is affected by the sample period, but the absolute minimum is 0 seconds, and the absolute maximum is 64 seconds.

Sample Period (Timing Only)

Sample Period is used to set the time period between data samples. Every time a new sample is taken, the analyzer will see updated measurement data. The choices available for sample period depend on the acquisition mode, which is set in the Format window.

In full channel mode, the Sample Period is configurable. A list of choices appear when the button is selected. In half channel mode, the analyzer will automatically run at a 250 ps sample period, and is not adjustable.

Oversampling: the Samples/Clock Control

(state only)

The Samples/Clock control sets the number of extra sample points (oversampling) between the edges of the external state clock. All oversampled points are evenly distributed within the period of the external state clock. Oversampling is set in powers of two, up to a maximum of 32, or a sample rate not exceeding 2 GSa/s. The equation below shows how the maximum sample rate is limited:

(external clock rate) x (oversampled setting) = 2 GHz

The external clock rate is checked at each run. If at any time the rate of oversampling exceeds a 2 GHz rate, a lower Samples/Clock setting is automatically chosen. If you notice some of the higher oversampling rate choices are not available, this means those choices would have

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exceeded the 2 GHz sampling rate when multiplied by the external clock rate. The interface will not make those choices available to you until the external clock rate decreases.

Viewing Oversampled Data

Once Samples/Clock is set to a value greater than 1, an additional label called Ext Clk Edge becomes available in the display tools. A 1 (one, or logic high) on label Ext Clk Edge indicates states that were clocked by the external state clock signal. A 0 (zero, or logic low) indicates states that were oversampled.

NOTE: The analyzer WILL NOT TRIGGER ON POINTS OF OVERSAMPLING. The

only points where the analyzer will trigger is on external clock transitions. If triggering is needed on these oversampled points, and the state clock is <500 MHz, convert from state mode to timing mode where all triggering is at 500 MHz.

The figure below shows data at the external clock transitions, data at the points of oversampling, and the data points where the analyzer could trigger.

Arming Control

An instrument must be armed before it can look for its trigger. When you Run an instrument, it is armed immediately. When you are using more than one instrument, you can use one instrument to arm another. The logic analyzer can be armed by the Run button, a Group Run through the Intermodule Bus (IMB), or by an external signal through the SMB Port connector on the back panel.

Chapter 1: Agilent Technologies 16517A/18A 4GHz Timing/1GHz State Logic Analyzer

The Trigger Tab

To Arm the Analyzer Using Run or the SMB Port:

1. Select Arm in the menu bar.

2. Choose the option that you want.

To Arm the Analyzer Using the Intermodule Bus

Refer to Overview - Multiple Instrument Configuration (see the Agilent Technologies 16700A/B-Series Logic Analysis System help volume).

Run/Group Run

Set the Arm control to Run if you are using just a single analyzer to make a measurement. When you select the Run/Stop button, you start the trigger sequence immediately.

SMB Port

Set the Arm control to SMB Port if you want to arm the analyzer with signal from an outside source. An arming signal can come from another module in the frame, such as an oscilloscope TRIG OUT signal. However, the only way the measurement can be time-correlated is if both the sending and receiving modules are configured as a Group Run in the Intermodule window. Generally, the SMB Port is used when you want an external trigger source to arm a module, or group of modules in the frame, or you want to take advantage of the faster arming path.

See Also Overview - Multiple Instrument Configuration (see the Agilent

Technologies 16700A/B-Series Logic Analysis System help volume)

Chapter 1: Agilent Technologies 16517A/18A 4GHz Timing/1GHz State Logic Analyzer

Specifications and Characteristics

NOTE: Definition of Terms

To understand the difference between specifications (see page 83) and characteristics (see page 83), and what gets a calibration procedure (see page 84) and what gets a function test (see page 84), refer to appropriate links within this note.

“Agilent Technologies 16517A/18A Logic Analyzer Specifications” on page 80

“Agilent Technologies 16517A/18A Logic Analyzer Characteristics” on page 81

Agilent Technologies 16517A/18A Logic Analyzer Specifications

The specifications are the performance standards against which the product is tested.

These specifications apply only to the Agilent Technologies 16517A/ 18A 4GHz Timing/1GHz State logic analyzer:

Minimum Input Voltage Swing: 500 mV peak to peak Threshold Accuracy: +/-2% of input signal +/-50 mV Minimum External Clock Period: 1 ns Setup/Hold Time: Per Pod:** 350 ps/350 ps Across Pods: 750 ps/750 ps 350 ps/350 ps, with manual deskew

* Specified for an input signal VH=-0.9 V, VL=-1.7 V, threshold=-1.3 V, slew rate=1 V/ns

** For the frequency range of 62.5 MHz to 20 MHz, a duty cycle of 40% to 60% is required.

Chapter 1: Agilent Technologies 16517A/18A 4GHz Timing/1GHz State Logic Analyzer

Specifications and Characteristics

Agilent Technologies 16517A/18A Logic Analyzer Characteristics

The characteristics are not specifications, but are included as additional information.

General information

- Channel Counts: 16517A 16 with 1 16518A 32 with 2 16518As 48 with 3 16518As 64 with 4 16518As 80

- Memory Depth: Half Channel 131072 samples per channel Full Channel 65536 samples per channel

Probes

- Input DC Resistance: 100 Kohm, +/- 2%

- Input Capacitance: 0.2 pF and then through 500 ohms, 3 pF

- Input Impedance: DC through 400 ns rise time, 100 Kohm, typical

3.5 ns through 350 ps, 500 ohm, typical

Impedance Curve

- Maximum Voltage: +/- 40 V peak CAT I

- Threshold Range: +/- 5.0 V, adjustable in 10-mV increments

- Threshold Setting: Preset TTL, ECL, or User-Defined on a per-pod basis.

- Input Dynamic Range: +/- 5 V about the threshold

- Minimum Input Overdrive: 250 mV or 30% of input, whichever is greater, above the pod threshold.

State Analysis

- Maximum External Clock Speed: 1 GHz, requires a periodic clock

- Minimum State Speed: 20 MSa/s, requires a periodic clock

- State Clocks: One external clock is available on the master card. No clocks are available on the expander card. Clock edge is selectable as rising or falling.

Chapter 1: Agilent Technologies 16517A/18A 4GHz Timing/1GHz State Logic Analyzer

Specifications and Characteristics

- State Clock Duty Cycle Range:

1 GHz through 500 MHz: 45% - 55%, typical 500 MHz through 250 MHz: 30% - 70%, typical 250 MHz through 20 MHz: 20% - 80%, typical

- Channel-to-Channel Skew:

Per Pod: 250 ps, typical Across Pods: 1 ns, typical 250 ps with manual deskew

- Minimum Detectable Pulse Width: 900 ps

- Oversampling: 2x, 4x, 8x, 16x, and 32x, at a rate

up to 2 GSa/s.

- Maximum Delay after Triggering:

(2 to the 20th)x(sample period), or

16.78 ms at or below 16 ns sample

period.

Note: When oversampling, use oversampled period for period above.

Timing Analysis

- Timing Modes: Conventional timing

- Timing Speed:

Full Channel 15.3 KSa/s - 2 GSa/s Half Channel 4 GSa/s

- Sample Period:

Full Channel 500 ps minimum, 65.536 us maximum Half Channel 250 ps

- Sample Period Accuracy: 0.005% of sample period

- Minimum Detectable Pulse Width:

4 GSa/s 800 ps, typical 2 GSa/s or less 1.1 ns, typical

- Time Covered by Data:

Minimum (2 or 4 GSa/s) 32.8 us Maximum (15.3 KSa/s) 4.3 s

- Time Interval Accuracy: +/-( sample period + channel-to-

channel skew + 0.005% of time interval reading )

- Channel-to-Channel Skew: 250 ps, typical

- Maximum Delay after Triggering:

(2 to the 20th)x(sample period), or

16.78 ms at or below 16 ns sample

period.

Triggering

- State Sequence Levels: 4 plus trigger point

- Timing Sequence Levels: 4 plus trigger point

- Maximum Sequencer Speed: 500 MHz

- Maximum Occurrence Count Value: 16,777,216

- Pattern Recognizers: 4. Each pattern recognizer is the

AND combination of bit (0,1,X) patterns.

- Pattern Width: 16/32/48/64/80 channels.

- Minimum Pattern Recognizer

Pulse Width: 2.25 ns

- Edge Recognizers (Timing Only): 2. Recognize rising, falling, or

either edge on any channel. Edges are OR’d across all channels.

- Edge Width: 16/32/48/64/80 channels.

- Edge Counting Frequency: 444 MHz

- Edge Detection: Up to 1 GHz.

- Greater Than Duration: 0 ns - 510 ns. Accuracy is +/- 2.25 ns.

- Less Than Duration: 4 ns - 510 ns. Accuracy is +/- 2.25 ns.

- Resource Terms per Trigger 4. Each edge recognizer and pattern

Specification recognizer of a specified duration count as one resource term.

- Branching: Each sequence level has two branching

qualifiers. When the qualifier is satisfied, the analyzer will branch to the specified sequence level.

- Timer/Counter: 1 timer or counter per sequence level.

Restarted upon each entry to each level.

- Timer/Counter Range:

Chapter 1: Agilent Technologies 16517A/18A 4GHz Timing/1GHz State Logic Analyzer

Specifications and Characteristics

Timing mode 0 s to 33 ms State mode, 500 MHz to 1 GHz (ext. clock period)x(2 to the 23rd) State mode, less than 500 MHz (ext. clock period)x(2 to the 24th)

- Timer Resolution: Timing mode 2 ns State mode, above 500 MHz 2x(ext. clock period) State mode, below 500 MHz ext. clock period

- Timer Accuracy: 0.005% of timer value

Power Requirements All power supplies required for operating the logic analyzer are supplied through the backplane connector in the mainframe.

Operating Environment Characteristics

- Indoor use only.

- Temperature Instrument: 0 to 55 degrees C (+32 to 131 degrees F) Probe lead sets and cables: 0 to 65 degrees C (+32 to 149 degrees F)

- Humidity Instrument, probe lead sets, and cables: up to 95% relative humidity at 40 degrees C (+104 degrees F)

- Altitude To 4600 m (15,000 ft)

- Vibration Operating: Random vibration 5-500 Hz, 10 minutes per axis, approximately 0.3 g rms Non-operating: Random vibration 5 to 500 Hz, 10 minutes per axis, approximately 2.41 g rms; and swept sine resonant search, 5 to 500 Hz, 0.75 g (0-peak), 5-minute resonant dwell at 4 resonances per axis.

What is a Specification

A Specification is a numeric value, or range of values, that bounds the performance of a product parameter. The product warranty covers the performance of parameters described by specifications. Products shipped from the factory meet all specifications. Additionally, the products sent to Agilent Technologies Customer Service Centers for calibration and returned to the customer meet all specifications.

Specifications are verified by Calibration Procedures.

What is a Characteristic

Characteristics describe product performance that is useful in the application of the product, but that is not covered by the product warranty. Characteristics describe performance that is typical of the majority of a given product, but not subject to the same rigor associated with specifications.

Chapter 1: Agilent Technologies 16517A/18A 4GHz Timing/1GHz State Logic Analyzer

Specifications and Characteristics

Characteristics are verified by Function Tests.

What is a Calibration Procedure

Calibration procedures verify that products or systems operate within the specifications. Parameters covered by specifications have a corresponding calibration procedure. Calibration procedures include both performance tests and system verification procedure. Calibration procedures are traceable and must specify adequate calibration standards.

Calibration procedures verify products meet the specifications by comparing measured parameters against a pass-fail limit. The pass-fail limit is the specification less any required guardband.

The term "calibration" refers to the process of measuring parameters and referencing the measurement to a calibration standard rather than the process of adjusting products for optimal performance, which is referred to as an "operational accuracy calibration".

What is a Function Test

Function tests are quick tests designed to verify basic operation of a product. Function tests include operator’s checks and operation verification procedures. An operator’s check is normally a fast test used to verify basic operation of a product. An operation verification procedure verifies some, but not all, specifications, and often at a lower confidence level than a calibration procedure.

Chapter 1: Agilent Technologies 16517A/18A 4GHz Timing/1GHz State Logic Analyzer

The Symbols Tab

The Symbols tab offers control of the symbols capabilities. Symbols represent patterns and ranges of values found on labeled sets of bits. Two kinds of symbols are available:

• Object File Symbols. These are symbols from your source code and symbols generated by your compiler.

• User-Defined Symbols. These are symbols you create.

To load symbols, see:

•“To Load Object File Symbols” on page 87

•“To Load User-Defined Symbols” on page 100

Symbols are available for all state and timing analyzers. Each label listed in the Format menu can have its own group of symbols associated with it.

•“User-Defined Symbols” on page 99

•“Setting Up Object File Symbols” on page 87

•“Using Symbols In The Logic Analyzer” on page 101

•“Displaying Data in Symbolic Form” on page 86

Chapter 1: Agilent Technologies 16517A/18A 4GHz Timing/1GHz State Logic Analyzer

Displaying Data in Symbolic Form

You can display data in symbolic form in some of the display tools, such as the Listing display and the Waveform display.

To View Symbolic Values in a Waveform Display

1. Select the label name where you want to display symbolic values.

2. Choose Properties....

3. In the Properties dialog:

• Set ShowValue to On.

• Set Base to Symbols or Line #s.

• Select the OK button.

The symbolic names for the values now appear in the overlayed bus waveform.

To View Symbolic Values in a Listing Display

1. Select the numeric base of the label where you want to display symbolic values.

2. Set the numeric base to Symbols or Line #s. The symbolic names for the values now appear instead of numeric data.

Chapter 1: Agilent Technologies 16517A/18A 4GHz Timing/1GHz State Logic Analyzer

Setting Up Object File Symbols

Object file symbols can include variable names, procedure or function names, and source file names with line numbers. The linkage between symbol names and address or data values comes from one of two sources:

• Object files that are created by your compiler/linker.

• ASCII symbol files you create with a text editor.

To use object file symbols

1. Generate an object file with symbolic information using your software development tools.

2. If your language tools cannot generate object file formats that are supported by the logic analyzer, create an ASCII symbol file (see page 91).

3. Load the object file (see page 87) or ASCII symbol file into the logic analyzer.

4. If necessary, relocate sections of your code (see page 89).

See Also “Using Symbols In The Logic Analyzer” on page 101

“Symbol File Formats” on page 90

To Load Object File Symbols

1. Select the Symbol tab and then the Object File tab.

2. Select the label name you want to load object file symbols for. In most cases you will select the label representing the address bus of the processor you are analyzing.

3. Specify the directory to contain the symbol database file (.ns ) in the field under, Create Symbol File (.ns) in This Directory. Select the Browse... button if you wish to find an existing directory name.

4. In the Load This Object/Symbol File For Label field, enter the object file

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Setting Up Object File Symbols

name containing the symbols. Select the Browse... button to find the object file and select the Load button in the Browser dialog. If your logic analyzer is NFS mounted to a network, you can select object files from other servers.

To reload object file symbols

1. Select the object file/symbol file to reload from the Object Files with Symbols Loaded For Label field.

2. Select the Reload button.

Value update

The values of the object file symbols being used as terms or as SPA state-interval ranges will be updated automatically each time the object file symbols are reloaded.

Configuration file save

The name of the current object file is saved when a configuration file is saved. The object file will be reloaded when the configuration is loaded.

Multiple files

You can load the same symbol file into several different analyzers, and you can load multiple symbol files into one analyzer. Symbols from all the files you load will appear together in the object file symbol selector that you use to set up resource terms.

Object file versions

During the load process, a symbol database file with a .ns extension will be created by the system. One .ns database file will be created for each symbol file you load. Once the .ns file is created, the Symbol Utility will use this file as its working symbol database. The next time you need to load symbols into the system, you can load the .ns file explicitly, by placing the .ns file name in the Load This Object/Symbol File For Label field.

If you load an object file that has been loaded previously, the system will compare the time stamps on the .ns file and the object file. If the object file is newer, the .ns file will be created. If the object file has not

Chapter 1: Agilent Technologies 16517A/18A 4GHz Timing/1GHz State Logic Analyzer

Setting Up Object File Symbols

been updated since it was last loaded, the existing .ns file will be used.

See Also “Using Symbols In The Logic Analyzer” on page 101

“Symbol File Formats” on page 90

Relocating Sections of Code

Use this option to add offset values to the symbols in an object file. You will need this if some of the sections or segments of your code are relocated in memory at run-time. This can occur if your system dynamically loads parts of your code so that the memory addresses that the code is loaded into are not fixed.

To Relocate a Single Section of Code

1. Select the Symbol tab and then the Object File subtab.

2. Select the Relocate Sections... button.

3. In the Address column, select the address you wish to relocate.

4. In the Edit selected section field, enter the new address.

5. Select Apply Edit.

6. Repeat steps 3 through 5 above for any other sections to be relocated.

7. Select the Close button.

To Relocate All Sections of Code

1. Select the Symbol tab and then the Object File subtab.

2. Select the Relocate Sections... button.

3. Enter the value you wish to use in the Offset all selections by field.

4. Select the Apply Offset button.

5. Select the Close button.

Chapter 1: Agilent Technologies 16517A/18A 4GHz Timing/1GHz State Logic Analyzer

Setting Up Object File Symbols

To Delete Object File Symbol Files

1. Select the Symbol tab, and then the Object File subtab.

2. Select the file name you want to delete in the text box labeled, Object Files with Symbols Loaded For Label.

3. Select the Unload button.

Symbol File Formats

The logic analysis system can read symbol files in the following formats:

• OMF96

• OMFx86

• IEEE-695

• ELF/stabs

• TI COFF

For ELF/stabs, and ELF/stabs/Mdebug files, C++ symbols are demangled so that they can be displayed in the original C++ notation. To improve performance for these ELF symbol files, type information is not associated with variables. Hence, some variables (typically a few local static variables) may not have the proper size associated with them. They may show a size of 1 byte and not the correct size of 4 bytes or even more. All other information function ranges, line numbers, global variables and filenames will be accurate. These behaviors may be changed by creating a readers.ini (see page 96) file.

See Also “Creating ASCII Symbol Files” on page 91Creating ASCII Symbol Files

“Creating a readers.ini File” on page 96Creating a readers.ini File

Chapter 1: Agilent Technologies 16517A/18A 4GHz Timing/1GHz State Logic Analyzer

Setting Up Object File Symbols

Creating ASCII Symbol Files

If your language tool chain does not produce object files in a supported format, you can create an ASCII symbol file to define symbols. You can also use an ASCII symbol file to define symbols that are not included in your object file.

You can create an ASCII symbol file using any text editor that supports ASCII format text. Each entry in the file you create must be a string of ASCII characters consisting of a symbol name followed by an address or address range. The address or address range must be a hexadecimal number. It must appear on the same line of the text file as the symbol name and it must be separated from the symbol name by one or more blank spaces or tabs. Address ranges must be in the following format:

beginning address..ending address

Two formats are available for creating ASCII symbol files:

“Simple Format” on page 91

“Record Header Format” on page 91

NOTE: It is possible to generate ASCII symbol files from the symbol or load map

output of most language tools.

Simple Format

An ASCII symbol file can be a simple list of name/address pairs.

Example

main 00001000..00001009 test 00001010..0000101F var1 00001E22 #this is a variable

This example defines two symbols that correspond to address ranges and one point symbol that corresponds to a single address.

Record Header Format

An ASCII symbol file can be divided into records using key words,

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Setting Up Object File Symbols

called record headers. The different records allow you to specify different kinds of symbols, with differing characteristics. An ASCII symbol file can contain any of the following kinds of records:

“Start Address” on page 93

“Sections” on page 93

“Functions” on page 93

“Variab les” on page 95

“Source Line Numbers” on page 94

“Comments” on page 95

The record headers must be enclosed in square brackets, like this: [HEADER]. If no record header is specified, the lines following are assumed to be symbol definitions in one of the VARIABLES formats:

variable address variable start..end variable start address size

Example

Here is an ASCII symbol file that contains several different kinds of records.

[SECTIONS] prog 00001000..0000101F data 40002000..40009FFF common FFFF0000..FFFF1000

[FUNCTIONS] main 00001000..00001009 test 00001010..0000101F

[VARIABLES] total 40002000 4 value 40008000 4

[SOURCE LINES] File: main.c 10 00001000 11 00001002 14 0000100A 22 0000101E

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Setting Up Object File Symbols

File: test.c 5 00001010 7 00001012 11 0000101A

Start Address . Format

[START ADDRESS] address

address - The address of the program entry point, in hexadecimal.

Example

[START ADDRESS] 00001000

Functions . Use FUNCTIONS to define symbols for program functions, procedures or subroutines.

Format

[FUNCTIONS] func_name start..end

func_name - A symbol representing the function name.

start - The first address of the function, in hexadecimal.

end - The last address of the function, in hexadecimal.

Example

[FUNCTIONS] main 00001000..00001009 test 00001010..0000101F

Sections . Use SECTIONS to define symbols for regions of memory, such as sections, segments, or classes.

Format

[SECTIONS] section_name start..end attribute

section_name - A symbol representing the name of the section.

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Setting Up Object File Symbols

start - The first address of the section, in hexadecimal.

end - The last address of the section, in hexadecimal.

attribute - (optional) Attribute may be one of the following:

NORMAL (default) - The section is a normal, relocatable section, such as code or data.

NONRELOC - The section contains variables or code that cannot be relocated. In other words, this is an absolute segment.

Example

[SECTIONS] prog 00001000..00001FFF data 00002000..00003FFF display_io 00008000..0000801F NONRELOC

NOTE: If Section definitions are used in an ASCII symbol file, any subsequent

Function or Variable definitions must fall within the address ranges of one of the defined Sections. Those Functions and Variables that do not will be ignored by the Symbol Utility.

Source Line Numbers . Use SOURCE LINES to associate addresses with lines in your source files.

Format

[SOURCE LINES] File: file_name line# address

file_name - The name of a file.

line# - The number of a line in the file, in decimal.

address - The address of the source line, in hexadecimal.

Example

[SOURCE LINES] File: main.c 10 00001000 11 00001002

Chapter 1: Agilent Technologies 16517A/18A 4GHz Timing/1GHz State Logic Analyzer

Setting Up Object File Symbols

14 0000100A 22 0000101E

See Also Using the Source Viewer (see the Listing Display Tool help volume)

Variables. You can specify symbols for variables using:

• The address of the variable.

• The address and the size of the variable.

• The range of addresses occupied by the variable.

If you give only the address of a variable, the size is assumed to be 1 byte.

Format

[VARIABLES] var_name start [size] var_name start..end

var_name - A symbol representing the variable name.

start - The first address of the variable, in hexadecimal.

end - The last address of the variable, in hexadecimal.

size - (optional) The size of the variable, in bytes, in decimal.

Example

[VARIABLES] subtotal 40002000 4 total 40002004 4 data_array 40003000..4000302F status_char 40002345

Comments . Any text following a # character is ignored by the Symbol Utility. The # can be used to comment a file. Comments can appear on a line by themselves, or on the same line, following a symbol entry.

Format

#comment text

Chapter 1: Agilent Technologies 16517A/18A 4GHz Timing/1GHz State Logic Analyzer

Setting Up Object File Symbols

Example

#This is a comment

Creating a readers.ini File

You can change how an ELF/Stabs, Ticoff or Coff/Stabs symbol file is processed by creating a reader.ini file.

1. Create the reader.ini file on your workstation or PC.

2. Copy the file to /logic/symbols/readers.ini on the logic analysis system.

Reader options C++Demangle

1= Turn on C++ Demangling (Default) 0= Turn off C++ Demangling

C++DemOptions

803= Standard Demangling 203= GNU Demangling (Default Elf/Stabs) 403= Lucid Demangling 800= Standard Demangling without function parameters 200= GNU Demangling without function parameters 400= Lucid Demangling without function parameters

MaxSymbolWidth

80= Column width max of a function or variable symbol Wider symbols names will be truncated. (Default 80 columns)

OutSectionSymbolValid

0= Symbols whose addresses aren’t within the defined sections are invalid (Default) 1= Symbols whose addresses aren’t within the defined sections are valid

This option must be specified in the Nsr section of the Readers.ini file:

[Nsr] OutSectionSymbolValid=1

ReadElfSection

2= Process all globals from ELF section (Default) Get size information of local variables

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Setting Up Object File Symbols

1= Get size information of global and local variables Symbols for functions will not be read, and only supplemental information for those symbols in the Dwarf or stabs section will be read. 0= Do not read the Elf Section

If a file only has an ELF section this will have no effect and the ELF section will be read completely. This can occur if the file was created without a "generate debugger information" flag (usually -g). Using the g will create a Dwarf or Stabs debug section in addition to the ELF section.

StabsType

StabsType=0 Reader will determine stabs type (Default) StabsType=1 Older style stabs (Older style stabs have individual symbol tables for each file that was linked into the target executable, the indexes of each symbol table restart at 0 for each file.) StabsType=2 Newer style stabs (New style stabs have a single symbol table where all symbols are merged into a large symbol array).

ReadOnlyTicoffPage

ReadOnlyTicoffPage tells the ticoff reader to read only the symbols associated with the specified page (as an example ’ReadOnlyTicoffPage=0’ reads only page 0 symbols). A value of -1 tells the ticoff readers to read symbols associated with all pages.

ReadOnlyTicoffPage=-1 Read all symbols associated will all ticoff pages (Default) ReadOnlyTicoffPage=p Read only symbols associated with page ’p’ (where p is any integer between 0 and n the last page of the object file).

AppendTicoffPage

AppendTicoffPage tells the ticoff reader to append the page number to the symbol value. This assumes that the symbol value is 16-bits wide and that that page number is a low positive number which can be ORed into the upper 16 bits of an address to create a new 32-bit symbol address. For example, if the page is 10 decimal and the symbol address is 0xF100 then the new symbol address will be 0xAF100.

AppendTicoffPage=1 Append the ticoff page to the symbol address AppendTicoffPage=0 Do not append the ticoff page to the symbol address (Default)

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Setting Up Object File Symbols

Examples Example for Elf/Stabs

[ReadersElf] C C MaxSymbolWidth=60 StabsType=2

Example for Coff/Stabs (using Ticoff reader)

[ReadersTicoff] C C MaxSymbolWidth=60 StabsType=2

Example for Ticoff

[ReadersTicoff] C C MaxSymbolWidth=60 ReadOnlyTicoffPage=4 AppendTicoffPage=1

Chapter 1: Agilent Technologies 16517A/18A 4GHz Timing/1GHz State Logic Analyzer

User-Defined Symbols

“To Create User-Defined Symbols” on page 99

“To Replace User-Defined Symbols” on page 99

“To Delete User-Defined Symbols” on page 100

“To Load User-Defined Symbols” on page 100

To Create User-Defined Symbols

1. Under the Symbol tab, select the User Defined tab.

2. Select the label name you want to define symbols for.

3. At the bottom of the User Defined tab, enter a symbol name in the entry

field.

4. Select a numeric base.

5. Select Pattern or Range type for the symbol.

6. Enter values for the pattern or range the symbol will represent.

7. Select the Add button.

8. Repeat steps 3 through 7 for additional symbols.

9. You can edit your list of symbols by using Replace (see page 99) and Delete (see page 100), if desired.

See Also “Using Symbols In The Logic Analyzer” on page 101

To Replace User-Defined Symbols

1. Under the Symbol tab, select the User Defined tab.

2. Select the label you want to replace symbols for.

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User-Defined Symbols

3. Select the symbol to replace.

4. At the bottom of the User Defined tab, modify the symbol name, numberic

base, Pattern/Range type, and value, as desired.

5. Select the Replace button.

6. Repeat steps 3 through 5 to replace other symbols, if desired.

To Delete User-Defined Symbols

1. Under the Symbol tab, select the User Defined tab.

2. Select the label you want to delete symbols from.

3. Select the symbol to delete.

4. Select the Delete button.

5. Repeat steps 3 and 4 to delete other symbols, if desired.

To Load User-Defined Symbols

If you have already saved a configuration file, and the configuration included user-defined symbols, load the file with its symbols, as follows:

1. In the menu bar of your analyzer window, select File and then Load

Configuration....

2. In the Load Configuration dialog, select the directory and filename to be loaded.

3. Select the target of the load operation.

4. Select the Load button. User-defined symbols that were resident in the logic analyzer when the configuration was saved are now loaded and ready to use.

See Also “Using Symbols In The Logic Analyzer” on page 101

100

Agilent 16517A Help Volume

Specifications and Main Features

Frequently Asked Questions

User Manual

Agilent Technologies 16517A/18A 4GHz Timing/1GHz State Logic Analyzer

Contents

Agilent Technologies 16517A/18A 4GHz Timing/1GHz State Logic Analyzer

Connecting to Your Target System

Recommended Probe Configurations

Probing Accessories

Probing System Description

Requirements of Target Signals

Overdrive

Adjusting Skew

Setting Up a Measurement

Map the Analyzer to the Target System

Set Up the Analyzer

Define Trigger Conditions

Run the Measurement

Examine the Data

Making a Basic Timing Measurement

Making a Basic State Measurement

Interpreting the Data

Analysis Using Waveform

Analysis Using Listing

Loading and Saving Logic Analyzer Configurations

When Something Goes Wrong

Nothing Happens

Error Messages

Waiting for Trigger

Maximum of 32 Channels Per Label

Using Default 16517/18 Skew Values.

16517/18 Skew Values are from a Different Instrument

16517/18 Memory System Failed -- Replace Card(s)

Invalid 16517/16518 Card Configuration.

Cannot Run. External 16517 Clock Period Should be 1 ns to 50 ns

Measurement Halted in Sequence Level N.

External Clock Out of Spec.

Loss of Sync with External 16517 Clock.

NOTE: Trigger Sequencer Will Not See Oversampled States.

NOTE: 500 MHz Trigger Sequencer Rate Exceeds Sample Rate.

NOTE: Sample Rate Exceeds 500 MHz Trigger Sequencer Rate.\

Pod XX identified

Data Channels (X....X..) Are Not Connected Properly

The Clock is Not Connected Properly

16517/18 Skew Values Do Not Match Slot Configuration.

16517/18 Skew Values Are From Different Instrument.

Using Default 16517/18 Skew Values.

Invalid 16517/18 Skew Values.

Suspicious Data

Interference with Target System

Testing the Logic Analyzer Hardware

The Format Tab

Setting the Acquisition Mode

Setting the State Clock

State Clock Sample Offset

Defining Labels: Mapping Analyzer Channels to Your System

Working with Labels

Assigning Bits to a Label

Reordering the Bits in a Label

Inserting and Deleting Labels

Turning Labels On and Off

Label Polarity

Setting the Pod Threshold

Activity Indicators

The Trigger Tab

Setting Up a Trigger

Selecting the Edit of a Sequence Step

Selecting a Macro to Match Trigger Conditions

Adding and Deleting Sequence Steps

Editing Sequence Steps

Setting Up Loops and Jumps in the Trigger Sequence

Saving and Recalling Trigger Sequences

Clearing Part or All of the Trigger

Overview of the Trigger Sequence

How the Internal Sequence Levels Are Used

Predefined Trigger Macros

Timing User Mode

Basic Timing Macros

Pattern/Edge Combinations