User’s Reference
Publication number 16517-97006
January 1999
For Safety information, Warranties, and Regulatory
information, see the pages behind the Index
Copyright Hewlett-Packard Company 1987, 1990, 1993, 1996, 1997, 1999
All Rights Reserved
HP 16517A/18A
4-GSa/s Timing and
1-GSa/s Synchronous State
Logic Analyzer
The HP 16517A 4-GSa/S Timing and 1-GSa/S State Logic Analyzer
ii
In This Book
The User’s Reference contains field and
feature definitions. Use this part of the
manual set for information on what the
menu fields do, what they are used for,
and how the features work.
The User’s Reference is divided into
chapters covering general product
information and probing. In addition,
there are separate chapters for each
analyzer menu, a chapter for markers, a
chapter for error messages, and a chapter
for instrument specifications.
You have the choice of using the analyzer
as either a synchronous state analyzer or
a timing analyzer. Some menus in the
analyzer will change depending on the
acquisition mode used. For example,
because a timing analyzer does not use
external clocks, the external clock
assignment fields in the Format menu will
not be available.
If a menu field is only available to a
particular acquisition mode, the field is
designated (Timing only) or (State only)
after the field name. If no designation is
shown, the field is available for both state
and timing.
1
General Information
2
Probing
3
The Format Menu
4
The Trigger Menu
5
The Listing Menu
6
The Waveform Menu
7
The Compare Menu
8
The Chart Menu
Markers and
9
Stop Measurement
10
Skew Adjust
11
Error Messages
Specifications and
12
Characteristics
13
Installation and Service
Index
iii
iv
Contents
1 General Information
User Interface 1–4
Configuration Capabilities 1–5
Accessories Supplied 1–6
Accessories Available 1–6
2 Probing
Probing 2–2
Probing System Description 2–4
Probing Accessories 2–6
Probing Considerations 2–9
Orientation Between Probe Tip and Interface 2–10
3The Format Menu
Synchronous State Acquisition Mode 3–3
Conventional Timing Acquisition Mode 3–4
Select Clock Field (State Only) 3–5
Set Sample Offset Field (State Only) 3–6
Pod Threshold Field 3–8
Label Polarity Fields 3–9
Bit Assignment Fields 3–10
Activity Indicators 3–12
Symbols Field 3–12
4The Trigger Menu
Trigger Sequence Levels 4–4
Modify Trigger Field 4–6
Contents–1
Contents
Pre-defined Trigger Macros 4–9
Using Macros to Create a Trigger Specification 4–11
Timing Trigger Macro Library 4–12
State Trigger Macro Library 4–15
Creating a User Level 4–17
Resource Terms 4–25
Assigning Resource Term Names and Values 4–27
Label and Base fields 4–31
Acquisition Control 4–32
Trigger Position Field 4–33
Sample Period Field (Timing only) 4–34
Samples/Clock Field(State only) 4–34
Armed By Field 4–37
5The Listing Menu
Markers Field 5–3
Data Roll Field 5–3
Label and Base Fields 5–4
Show States All/Ext Clock (State only) 5–5
Sample Offset Field (State only) 5–6
Specify Patterns Field 5–6
Acquisition Control Field 5–6
6The Waveform Menu
Acquisition Control Field 6–3
Accumulate Field 6–4
Seconds Per Division Field 6–5
Delay Field 6–6
Sample Period Display (Timing only) External Clock Period Display (State
only) 6–7
Markers Field 6–8
Contents–2
Waveform Display 6–9
Display Location Reference Line 6–10
External-Clock Indicators (State only) 6–11
Blue Bar Field 6–12
Channel Mode Field 6–14
Module and Label Fields 6–16
Action Insert/Replace Field 6–17
Delete and Delete All Fields 6–18
Waveform Size Field 6–19
Sample Offset Field (State only) 6–20
Reset Statistics Field 6–20
7The Compare Menu
Reference Listing Field 7–4
Difference Listing Field 7–5
Copy Listing to Reference Field 7–7
Find Error Field 7–8
Compare Full / Compare Partial Field 7–9
Mask Field 7–10
Specify Stop Measurement Field 7–11
Data Roll Field 7–14
Bit Editing Field 7–15
Label and Base Fields 7–16
Contents
8The Chart Menu
The Y Markers 8–4
Markers Field 8–5
Rescale 8–6
Axis Control Field 8–8
Accumulate Field 8–11
Contents–3
Contents
9 Markers and Stop Measurements
Markers Field 9–3
Pattern Markers 9–4
Find X-pattern / O-pattern Field (Listing and Chart) 9–5
Occurrence Counter Field (Listing and Chart) 9–5
From Trigger / Start / X Marker Field 9–6
X-pat / O-pat Occurrence Fields (Waveform menu) 9–7
Center Screen Field (Waveform and Chart) 9–7
X to O Display Field (Waveform and Chart) 9–7
Specify Patterns Field 9–8
Stop Measurement Field 9–10
Clear Pattern Field 9–11
Time Markers 9–12
Trig to X / Trig to O Fields 9–13
Marker Label / Base and Display (Waveform menu) 9–13
Statistics Markers 9–14
Reset Statistics Field (Waveform menu) 9–15
Clear Statistics Field (Chart menu) 9–15
10 Skew Adjust
To Calibrate the Data Acquisition Module 10–2
To Adjust the Channel-to-Channel Skew 10–3
Connect the Logic Analyzer 10–3
Set Up the Logic Analyzer 10–4
To Save or Discard the Skew Factors 10–6
Contents–4
11 Error Messages
Error Messages 11–3
Warning Messages 11–4
Advisory Messages 11–7
Skew Adjust and Performance Verification Messages 11–8
12 Specifications and Characteristics
Specifications 12–3
Characteristics 12–4
13 Installation and Service
To Inspect the Module 13–3
To Prepare the Mainframe 13–3
To Configure a One-card Module 13–5
To Configure a Multi-card Module 13–5
To Install the Module 13–7
To Test the Module 13–8
Contents
To Perform the Self-tests 13–9
Access the Self-tests 13–9
Perform the Functional Tests 13–10
Perform the Skew Adjustments and Tests 13–11
Exit the Self-tests 13–12
To Return Assemblies 13–13
To Clean the Logic Analyzer Module 13–13
Index
Contents–5
Contents–6
1
General Information
Logic Analyzer Description
The HP 16517A/18A Synchronous Timing Analyzer module is part of a
family of general-purpose logic analyzers. The HP 16517A/18A is a
multi-card module that is used with the HP 16500 mainframes and the
HP 16501A Expansion Frame.
The HP 16500 mainframe is designed for use by digital and
microprocessor hardware and software designers. The HP 16500
mainframe has HP-IB, RS-232-C, and Ethernet LAN interfaces for
hard copy printouts, postprocessing of measurement data, and control
by a host computer.
The HP 16517A/18A analyzer can be configured in the following ways:
• The HP 16517A master can run as a single-card module or have up
to four HP 16518A expansion cards added for a multi-card module.
• Channel width varies from 16 channels on the HP 16517A master,
up to 80 channels when four HP 16518A expansion cards are added.
• Channel memory depth is 64 Kbytes in both full-channel state and
timing modes or 128 Kbytes in half-channel timing mode.
Timing Modes
The HP 16517A/18A has two timing modes. In full-channel timing
mode, data is sampled at up to 2 GHz. In half-channel timing mode,
data is sampled at 4 GHz.
Synchronous State Mode
In the full-channel state mode, a synchronous external clock running
at speeds up to 1 GHz can be used as the sample clock. In addition,
the sample point can be offset to ensure a sample where you know
data is valid.
1–2
General Information
Not only can you sample at the external clock transitions, but you can
set the analyzer to oversample, in powers of two, up to 32x, or, up to a
maximum of 2 GHz sample rate. Each point of oversampling is
precisely distributed evenly within the external clock period.
Triggering
Defining a trigger specification is as easy as picking a predefined
macro from a trigger macro library. Trigger macros can be used by
themselves or in combination with each other. Resource terms
include four global patterns, two global edges, and one level
dependent timer/counter. By using trigger macros, or defining your
own trigger specification, the user-friendly and flexible triggering
architecture lets you create a large array of trigger sequencing or
qualification needed.
Acquisition Control
Data storage can begin at either the start, center, end, or a
user-defined point within memory. In addition, if the data of interest
occurs a relatively long time after trigger, you can delay storage after a
trigger by a user-defined amount. With all the acquisition control
available, you can fill acquisition memory very efficiently.
Measurement Display
Measurement data is displayed as waveforms or state data listings.
State data can be compared bit by bit to a user-defined reference
image. In the state listing, you can choose to display either sample
clock transitions or both sample clock and oversampling clock
transitions. In the timing waveform display, you can show state values
integrated in the waveform.
1–3
General Information
User Interface
User Interface
The HP 16500 Logic Analysis System has four easy-to-use user interface
devices: the knob, the touchscreen, the optional mouse (standard in the
HP 16500C), and the optional keyboard.
The knob on the front panel is used to move the cursor on certain menus, to
increment or decrement numeric fields, and to roll the display.
The touchscreen fields can be selected by touch or with the optional mouse.
To activate a touchscreen field by touch, simply touch the screen over any
dark blue box on the display with your finger until the field changes color.
Then remove your finger from the screen to activate your selection. The area
under your finger when you remove it from the screen is the area selected.
To activate a field with the mouse, position the cursor (+) of the mouse over
the desired field and press the left button of the mouse.
The keyboard can control all instrument functions by using special function
keys, the arrow keys, and the ENTER key. Alphanumeric entry is simply
typed in.
All user interface devices are discussed in more detail in the HP 16500 User’s
Reference.
1–4
Configuration Capabilities
The logic analyzer can be configured as a single- or multi-card module. The
number of data channels range from 16 channels using just the HP 16517A,
up to 80 channels when four HP 16518A expansion cards are connected. A
half-channel acquisition mode is available which reduces the channel width
by half, but doubles memory depth from 64 Kbits to 128 Kbits per channel.
The configuration guide below illustrates the channel width and memory
depth combinations in all acquisition modes.
Table 1-1
Conventional Timing Modes
General Information
Configuration Capabilities
One-Card
Module
Full Channel
Half Channel
16 channels
64 Kbits Deep
8 channels
128 Kbits Deep
Table 1-2
Synchronous State Mode
One-Card
Module
Full Channel
16 channel
64 Kbits Deep
Two-Card
Module
32 channels
64 Kbits Deep
16 channels
128 Kbits Deep
Two-Card
Module
32 channel
64 Kbits Deep
Three-Card
Module
48 channels
64 Kbits Deep
24 channels
128 Kbits Deep
Three-Card
Module
48 channel
64 Kbits Deep
Four-Card
Module
64 channels
64 Kbits Deep
32 channels
128 Kbits Deep
Four-Card
Module
64 channel
64 Kbits Deep
Five-Card
Module
80 channels
64 Kbits Deep
40 channels
128 Kbits Deep
Five-Card
Module
80 channel
64 Kbits Deep
1–5
General Information
Accessories Supplied
Accessories Supplied
The table below lists the accessories supplied with your logic analyzer. If any
of these accessories are missing, contact your nearest Hewlett-Packard sales
office. If you need additional accessories, refer to
Analyzers
.
Accessories for HP Logic
Table 1-3
Accessories Supplied
Accessory Quantity
Probe Pod 2
Probe Accessory Kit 1
Cable Assembly 1
Operating system disks 1
User’s Reference 1
Accessories Available
There are a number of accessories available that will make your measurement
tasks easier and more accurate. You will find these listed in
HP Logic Analyzers
, available from your HP Sales Office.
Accessories for
1–6
2
Probing
Probing
This chapter describes the probing system used by the
HP 16517A/18A logic analyzer. It also contains information about the
probing accessories, how to connect them to the probing system, and
how to connect the probing system to the target system.
Probing Options
You can connect the logic analyzer to your system under test in one of
the following ways:
• The standard general purpose probing (provided).
• HP E2445A User-Definable Interface (optional).
• Microprocessor and bus specific interfaces (optional).
General-Purpose Probing
General-purpose probing involves connecting the logic analyzer
probes directly to your target system without using any interface.
General purpose probing does not limit you to specific hook up
schemes as, for example, the probe interface does. General-purpose
probing uses grabbers that connect to both through hole and surface
mount components.
General-purpose probing is the standard probing option provided with
the logic analyzer. There is a full description of its components and
use later in this chapter.
2–2
Probing
In addition to the supplied probing system, the logic analyzer can be
connected to a target system using the following probing options:
The E2445A User-Definable Interface
The optional E2445A User-Definable Interface module allows you to
connect the logic analyzer to the microprocessor in your target system
using a breadboard which you custom wire to your system.
The HP 16517-27601 SMA Adapter
The optional SMA adapter allows you to connect the individual probes
to SMA cables.
Microprocessor and Bus Specific Interfaces
The HP 16517A/18A does not support inverse assembly. In addition,
the HP 16517A/18A requires that any preprocessor used be a nonterminated preprocessor. The analyzer requires a clear connection
with no termination.
Microprocessors are supported by universal interfaces or
preprocessor interfaces, or in some cases both. There are a number of
microprocessor and bus specific interfaces available as optional
accessories listed in Accessories for HP Logic Analyzers.
Universal interfaces are aimed at initial hardware turn-on, and will
provide fast, reliable, and convenient connections to the
microprocessor system.
Preprocessor interfaces are aimed at hardware turn-on and
hardware/software integration, and will provide the following:
• All clocking and demultiplexing circuits needed to capture the
system’s operation.
• Additional status lines to further decode the operation of the CPU.
• Bus interfaces to support bus analysis for HP-IB, RS-232-C, RS-449,
SCSI, VME, VXI, ISA, EISA, MCA, FDDI, Futurebus+, JTAG, SBus,
PCI, and PCMCIA.
2–3
Probing
Probing System Description
Probing System Description
The analyzer probing system consists of shielded cables connected to the
analyzer card on one end, and a pod housing on the other. From the pod
housing, connection to the target system is through 12-inch coaxial cables
connected to the assorted probing accessories at the signal end. The pod
housing contains termination networks and comparators that drive open
collector outputs through the main cables. In addition, located on the pod
housing is an equivalent circuit illustration showing pod loading and channel
indicators for the 4 GHz operation. All probe accessories connect to 0.1 inch
centers.
Cable
Lead
Analyzer Probing System
2–4
Probing System Description
All probe cables are installed on the cards at the factory. The only
user-installed components are the probe tip assemblies contained in the
Probe Accessories Kit. The use of these probing accessories is described
later in this chapter. Other probe system specifics are listed as follows:
HP 16517A Master Card
Cables
and 6 standard wires for assorted dc functions.
Shielded, 6-foot long, contain eighteen 50-Ω transmission lines
Probing
Channels
byte), and has 8 data channels and 1 external clock channel. Pod 2, the
MSB (most significant byte), has 8 data channels.
HP 16518A Expansion Card
Cables
and 6 standard wires for assorted dc functions.
Channels
Total of 17 channels. Pod 1 is the LSB (least significant
Shielded, 5-ft long, contains eighteen 50-Ω transmission lines
Total of 16 channels. Each pod contains 8 data channels.
2–5
Probing
Probing Accessories
Probing Accessories
The probe accessories described below are part of the probe Accessory Kits
supplied with the master and expander cards. To order any of these
accessories individually, use the part numbers listed below or in the
Accessory Kit box.
The probe accessories that plug onto straight pins will fit on 0.63 mm
(0.025 in) square pins, or 0.66 mm to 0.84 mm (0.026 to 0.033 in) diameter
round pins.
Ground Leads
The following probing components connect the system to ground.
Ground lead kit
16517-82106
Qty 20
Ground extender kit
16517-82105
Qty 20
Ground connector
16515-27601
Qty 2
Right Angle Ground Lead
This flexible lead is one and a half inches
long with a 90 degree bend off the lead tip. It stacks on 0.1 inch centers.
Ground Extender
If the circuit can tolerate an additional 0.5 to 1 pF
capacitance, this socket allows stacking on 0.1 inch centers.
Ground Connector
This connector creates a 4-to-1 ground connection.
2–6
Probing Accessories
Signal Leads
The following probing components connect the system to the signal.
Probing
Probe pin kit
16517-82107
Qty 4
SMT lead kit
16517-82104
Qty 4 red/4 black
Grabber kit
16517-82108
Qty 20
Probe Pin
SMT Tack-on Signal/Ground Wire
The probe pin allows touch probing.
For surface mount components,
PGAs, or cramped areas, this wire can be tacked onto an IC lead for
direct connection.
Grabbers
These 0.05 pitch grabbers attach to adjacent IC pins with
lead spacing greater than or equal to 0.50 in.
2–7
Calibration pod
16517-63201
BNC to SMB adapter
16517-61604
Probing
Probing Accessories
Calibration Pod
The calibration pod is only included in the Accessory Kit for the master card.
You use the calibration pod during the master and expander card skew
adjust. For complete skew adjust information, refer to the optional
HP 16517A/18A Service Guide, available from your HP Sales Office.
Information on adjusting skew is also available in chapter 10, "Skew Adjust."
BNC to SMB Cable Adapter
On the back of the HP 16517A master card there are two SMB connectors
used for external ECL arm in/out signals. Use this adapter between the BNC
cable and the analyzer. The adapter cable is only included in the Accessory
Kit for the master card.
2–8
Probing
Probing Considerations
Probing Considerations
There are two concerns involved in all probing situations. The first concern
is probe loading of the target system. The HP 16517A/18A probes are
designed to eliminate this problem by providing high impedance from dc to
1 GHz. The second concern is possible inconsistent or erroneous data
capture caused by lead length and improper signal and ground connections.
The ideal connection is when the probe tip connects directly to the target
system without any additional lead length added to the ground. Depending
on your measurement, the added inductance caused by additional lead length
may or may not cause a problem for the signal rise time of the target system.
However, try to use the full performance configurations shown below when
possible. If you must add length to the ground lead, use the following general
guidelines:
Table 2-1
Recommended Probe Configurations
Target Rise time Maximum Additional Ground Length
300 ps 1 inch
600 ps 2 inch
1 ns 3 inch
Full Performance Configurations
2–9
Probing
Orientation Between Probe Tip and Interface
Orientation Between Probe Tip and Interface
If you find that after all the probe connections are made, you want to track or
reference a connection from the target system through the probing system
into the Format menu, use the following points of identification.
1
Use the color coded probe tips to identify the data channel or clock
channel.
2
Press the Pod ID button to display the pod number on screen.
When the Pod ID button is pressed, an advisory is displayed in all menus
identifying the pod number.
2–10
Channel reference line
Orientation Between Probe Tip and Interface
3
After the pod is identified, use the Activity Indicators and the
Channel Reference line in the Format menu to verify activity on the
data or clock channel you are referencing.
Indicators show high, low, or transitional activity while no data acquisition is
in process.
Activity indicatorsActivity indicators
4
Verify that the channel is enabled within the interface by the
assignment of a " * " (asterisk) in the Bit Assignment field.
Probing
Bit assignment
Other Helpful Hints:
Use labels with meaningful names to group data within the Format menu
•
When new pods are added to the module, they are added to the pod list in
•
the Format menu. In addition, if there are more pods configured than can
be displayed onscreen, use the Pods roll field to roll unseen pods back
onscreen.
2–11
2–12
3
The Format Menu
The Format Menu
The Format menu is used to assign which data channels are measured
and to group them under specific labels by function or by other
identification needs. For your convenience in recognizing bit pattern
groupings, you can also specify symbols to represent them.
Within the Format menu you select the acquisition mode, which in
turn sets the clock source (internal or external), memory depth, and
maximum sampling speed. Individual pod clock and data threshold
levels are also set in the Format menu.
If the acquisition mode is set to operate as synchronous state, other
fields appear which set the external clock edge and the sample clock
offset. The sample clock offset allows the offset of the internal sample
clock from the external clock edge to ensure the sampling of valid
data.
Acquisition mode
The Format Menu
3–2
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