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AGERE CSP1027 Datasheet

Data Sheet December 1999
CSP1027 Voice Band Codec for
Cellular Handset and Modem Applications

1 Features

∆-Σ (delta-sigma) A/D and D/A converters with stan-
■
dard 16-bit serial I/O interface.
quency response and signal to distortion plus noise specifications. Suitable for IS-54, GSM, and JDC dig­ital cellular applications.
■ Low-profile package (<1.5 mm) 48-pin thin quad flat
pack (TQFP) available or 44-pin EIAJ quad flat pack (QFP).
■ Operates in systems with a 3.0 V to 5.0 V digital
power supply and a 5.0 V analog supply.
■ Low-power 0.9 µm CMOS technology, fully static
design, typical power of 68 mW when active and
0.05 mW in standby with a 3.3 V digital supply and a
5.0 V analog supply.
■ A low-power inactive (standby) state without stopping
clock or removing power supply.
■ Sampling rates up to 24 kHz.
■ On-chip programmable sampling clock generator
allows input clock to be an integer multiple of 125 times the sampling rate or an integer multiple of the sampling rate.
■ Programmable phase adjust of both codec sampling
clock and baseband codec clock.
■ Two on-chip clock dividers for generating the output
clock for the baseband codec and the output clock for other processors.
■ Regulated microphone power supply.
■ Microphone preamplifier, with programmable input
ranges of 0.16 Vp and 0.5 Vp.
■ Output amplifier, with programmable gain settings,
0 dB to –45 dB in –3 dB steps.
■ High-pass filters selectable via control registers.
■ Power-on reset pulse generator.
■ Standard 16-bit serial I/O interface.
■ Serial I/O multiprocessor mode compatible with the
Lucent Technologies Microelectronics Group’s DSP16A and DSP1610/1616/1617/1618 Digital Sig­nal Processors.

2 Description

The Lucent CSP1027 is a high-precision linear voice­band ∆-Σ (delta-sigma) codec designed for cellular handset and modem applications. The device is fabri­cated in low-power CMOS technology and designed for low-voltage (3.0 V to 5.0 V) digital systems. The CSP1027 is packaged in a 44-pin EIAJ quad flat pack (QFP) or a 48-pin EIAJ thin quad flat pack (TQFP). In the 48-pin TQFP, the CSP1027 occupies a total volume of 0.0784 cm
The CSP1027 has a variety of significant programma­ble features not found in standard voice band codecs. The analog interface includes a microphone preampli­fier with programmable gain settings, an output ampli­fier with gain programmable in 3 dB steps over a 45 dB range, and a regulated microphone power supply. An inactive mode allows a low-power standby state, and a mute function provides suppression of the analog out­put. On-chip antialiasing and anti-imaging filtering includes a selectable high-pass filter. The CSP1027 meets ITU-T G.712 voice band specifications.
The programmable features of the CSP1027 are set by writing four on-chip control registers through the serial I/O interface. The codec’s digital input/output uses a linear 16-bit two’s complement data format that is also transferred through the serial I/O interface. The CSP1027 interfaces easily to the 16-bit serial ports of digital signal processors and other devices. The serial interface supports the Lucent fixed-point DSP family serial multiprocessor mode. This allows up to eight compatible devices, including two CSP1027s, to inter­face to each other on a common 4-wire bus using a time-division-multiplexing scheme.
3
.
CSP1027 Voice Band Codec for Data Sheet Cellular Handset and Modem Applications December 1999

Table of Contents

Contents Page
1 Features........................................................................................................................................... ....... .... 1
2 Description...................................... ....... ...... ....... ...... ....... ............................................ . ...... ...... . ...... ....... .... 1
3 Pin Information ........................................................................................................................................... 3
4 Architectural Information ............................................................................................................................ 5
4.1 Overview............................... ....... ...... ....... ...... ....... ...... ....... ...... ............................................. ....... .... 6
4.2 Description of Signal Paths............................................................................................................... 6
4.3 Programmable Features................................................................................................................. 13
4.4 Power-On Reset............................................................................................................................. 14
4.5 Clock Generation............................................................................................................................ 16
4.6 Serial I/O Configurations................................................................................................................. 20
5 Register Information.................................................................................................................................. 26
5.1 Codec I/O Control 0 (
5.2 Codec I/O Control 1 (
5.3 Codec I/O Control 2 (
5.4 Codec I/O Control 3 (
6 Signal Descriptions ................................................................................................................................... 30
6.1 Clock Interface................................................................................................................................ 30
6.2 Reset Interface ............................................................................................................................... 31
6.3 Serial I/O Interface.......................................................................................................................... 31
6.4 External Gain Control Interface ...................................................................................................... 32
6.5 Digital Power and Ground......................................................... ...... ....... ...... ....... ...... ....... ............... 32
6.6 Analog Interface.............................................................................................................................. 32
6.7 Analog Power and Ground ............................................................................................................. 32
7 Application Information ............................................................................................................................. 33
7.1 Analog Information.......................................................................................................................... 33
7.2 Power Supply Configuration........................................................................................................... 36
7.3 The Need for Fully Synchronous Operation ................................................................................... 36
7.4 Crystal Oscillator............................................................................................................................. 38
7.5 Programmable Clock Generation ................................................................................................... 45
8 Device Characteristics .............................................................................................................................. 47
8.1 Absolute Maximum Ratings............................................................................................................ 47
8.2 Handling Precautions...... ...... ....... ...... ....... ...... ....... ............................................. ...... ....... ............... 47
8.3 Recommended Operating Conditi ons....................................... ...... ....... ...... ....... ...... ....... ...... ....... .. 47
9 Electrical Characteristics and Requirements ............................................................................................ 48
9.1 Power Dissipation........................................................................................................................... 50
10 Analog Characteristics and Requirements................................................................................................ 51
10.1 Analog Input and Microphone Regulator........................................................................................ 51
10.2 Analog-to-Digital Path........................ ....... ............................................. ...... ....... ...... ...................... 52
10.3 Digital-to-Analog Path........................ ....... ............................................. ...... ....... ...... ...................... 53
10.4 Miscellaneous................................................................................................................................. 54
11 Timing Characteristics and Requirements................................................................................................ 55
11.1 Clock Generation............................................................................................................................ 56
11.2 Power-On Reset............................................................................................................................. 57
11.3 Reset .............................................................................................................................................. 58
11.4 Serial I/O Communication .............................................................................................................. 59
11.5 Serial Multiprocessor Communication............................................................................................ 61
12 Outline Diagrams ...................................................................................................................................... 62
12.1 44-Pin EIAJ Quad Flat Pack (QFP)............................. ....... ...... ...... ....... ......................................... 62
12.2 48-Pin EIAJ Thin Quad Flat Pack (TQFP)...................................................................................... 63
cioc0
) Register....... ...... ....... ...... ....... ...... ...... ....... ......................................... 26
cioc1
) Register....... ...... ....... ...... ....... ...... ...... ....... ......................................... 27
cioc2
) Register....... ...... ....... ...... ....... ...... ...... ....... ......................................... 28
cioc3
) Register....... ...... ....... ...... ....... ...... ...... ....... ......................................... 29
2
Lucent Technologies Inc.
Data Sheet CSP1027 Voice Band Codec for December 1999 Cellular Handset and Modem Applications

3 Pin Information

RES RES
RES SMODE1 SMODE0
RES
RES
RES
RES
RES
CKO1
1 2 3 4 5 6 7 8 9 10
11
DDA
V
44
12
CLK
AUXIN
43
13
XLO
REFC
42
14
XHI
SSA
MICIN
V
41
40
CPS1027-J
44-PIN QFP
15
16
CKO2
AOUTP
39
17
SS
V
RES
38
18
SADD
DDAVREGVSSA
AOUTN
V
37
36
19
20
DI
DO
35
21
DD
V
34 33
32 31 30
29 28 27 26 25 24
23 22
SYNC
EIGS SMODE2 PORCAP PORB RSTB RES RES RES RES RES IOCK
XOSCEN
Figure 1. 44-Pin EIAJ Quad Flat Pack (QFP) Pin Diagram
5-7567 (F)
RES RES
RES SMODE1 SMODE0
RES
RES
RES
RES
RES
RES
CKO1 12
DDA
V
AUXIN
4847464544434241403938
1 2 3 4 5 6 7 8 9 10 11
REFC
MICIN
SSA
V
AOUTP
RES
CSP1027-S
48-PIN TQFP
AOUTN
DDAVREGVSSA
V
37 RES
EIGS
36
SMODE2
35
PORCAP
34
PORB
33
RSTB
32
RES
31
RES
30
RES
29
RES
28
RES
27 26
RES
25 IOCK
1314151617181920212223
CLK
XLO
XHI
SS
V
CKO2
SADD
DO
DD
V
RES
SYNC 24
DI
XOSCEN
Figure 2. 48-Pin EIAJ Thin Quad Flat Pack (TQFP) Pin Diagram
5-7568 (F)
Lucent T echnologies Inc.
3
CSP1027 Voice Band Codec for Data Sheet Cellular Handset and Modem Applications December 1999
3 Pin Information
(continued)
Functional descriptions of the pins are found in Section 6 on page 30.
Table 1. Pin Descriptions
QFP Pin TQFP Pin Symbol Type Name/Function
1, 2, 3 1, 2, 3 RES NC* Reserved.
4 4 SMODE1 I Serial Mode Select 1. 5 5 SMODE0 I Serial Mode Select 0.
6, 7, 8,
9, 10
6, 7, 8,
9, 10, 11
RES NC* Reserved.
11 12 CKO1 O Clock Output 1. 12 13 CLK I Clock Input. 13 14 XLO I Crystal Input. 14 15 XHI O Crystal Output. 15 16 XOSCEN I Crystal Oscillator Enable. 16 17 CKO2 O Clock Output 2. 17 18 V
SS
18 19 SADD I/O
P Digital Ground.
†
Serial Address. 19 20 DI I Serial Input Data. 20 21 DO O 21 22 V
DD
†
Serial Output Data.
P Digital Power Supply. — 23 RES NC* Reserved. 22 24 SYNC I/O
23 25 IOCK I
24, 25,
26, 27, 28
26, 27, 28,
29, 30, 31
RES NC* Reserved.
†
Serial Input/Output Load Strobe and Synchronization.
‡
Serial Clock.
29 32 RSTB I Reset. 30 33 PORB O Power-On Reset Output. 31 34 PORCAP I
§
External Capacitor Connection for Power-On Reset. 32 35 SMODE2 I Serial Mode Select 2. 33 36 EIGS I
**
External Input Gain Select. — 37 RES NC* Reserved. 34 38 V 35 39 V 36 40 V
SSA REG DDA
P A nal og Ground. A Regulated Output Voltage for Electrect Condenser Microphone.
P A nal og 5.0 V Power Supply. 37 41 AOUTN A Inverting Analog Output of Output Amplifier. 38 42 RES NC* Reserved. 39 43 AOUTP A Noninverting Analog Output of Output Amplifier. 40 44 V
SSA
P A nal og Ground. 41 45 MICIN A Analog Input for Microphone. 42 46 REFC A External Capacitor Connection for Internal Voltage Regulator. 43 47 AUXIN A Analog Input from Auxiliary. 44 48 V
* Indicates no connection. † Indica tes 3-state output. ‡ Indica tes pull-up device on input.
§ Indicates pull-up resistor on input. ** Indicates pull-down device on input.
DDA
P A nal og 5.0 V Power Supply.
4
Lucent Technologies Inc.
Data Sheet CSP1027 Voice Band Codec for December 1999 Cellular Handset and Modem Applications

4 Architectural Information

AOUTP AOUTN
EIGS
MIC
AUX
ANALOG
OUTPUT
AMP
XOSCEN
LOW-PASS
CLK XLO
XHI CKO1 CKO2
CDIV0 (cioc1), CDIV1 (cioc1), CDIV2 (cioc0), CDIV3 (cioc2), CDIF0 (cioc2), CDIF1 (cioc3), CDIF2 (cioc3)
A/D INPUT
INSEL
cioc0
FILTER
(35 kHz)
CLOCK
GENERATION
BLOCK
TEST
cioc0
A/D
IRSEL
cioc0
M
U
D/A
X
TEST
DITHER
cioc0
cioc3
1 MHz OVERSAMPLING CLOCK
SYNC-CUBIC
M
U
DECIMATION
X
DIGITAL
MODULATOR
AND GAIN
ADJUST
OGSEL
cioc0
DIGITAL
FILTER
7th-ORDER LOW-PASS
FILTER
SAMPLE/HOLD
AND 7th-ORDER
IIR
LOW-PASS
FILTER
V
REG
(3.0 V)
REFC
IIR
M U X
HPFE
cioc3
ON-CHIP
VOLTAGE
REFERENCE
CIRCUITS
3rd-ORDER
IIR
HIGH-PASS
FILTER
3rd-ORDER
IIR
HIGH-PASS
FILTER
PORCAP
PORB
RSTB
1/1251 MHz OVERSAMPLING CLOCK
HPFE
cioc3
M U X
8 kHz
(A/D)
MUTE
cioc0
M U T E
c
c
i
o
o
c
c
3
2
POWER-ON
RESET
SIO
CONTROL
STATUS
C
O
D
S
X
R
C D X
(A/D)
c
c
i
i
i
o
o
c
c
1
0
INTERNAL RESET
M U X
I S R
TSTPOR
cioc3
IOCK SYNC SADD SMODE2 SMODE1 SMODE0
DO
DI
5-7559 (F)
Figure 3. CSP1027 Block Diagram
Lucent T echnologies Inc.
5
CSP1027 Voice Band Codec for Data Sheet
Hz
()
1
25
------
1z
25
–
–
()
1z
1
–
–
()
-------------------------
×
3
=
Cellular Handset and Modem Applications December 1999
4 Architectural Information
(continued)

4.1 Overview

The CSP1027 is a complete analog-to-digital and digi­tal-to-analog acquisition and conversion system (see Figure 3 on page 5) that band limits and encodes ana­log input signals into 16-bit PCM, and takes 16-bit PCM inputs and reconstructs and filters the resultant analog output signal. The selectable A/D input circuits, pro­grammable sample rates, and digital filter options allow the user to optimize the codec configuration for either speech coding or voice band data communications. The on-chip digital filters meet the ITU-T G.712 voice band frequency response and signal to distortion plus noise specifications and are suitable for IS-54, GSM, and JDC digital cellular applications. In addition, the small supply current drain, when powered down, extends battery life in mobile communication applica­tions.
The CSP1027 is intended for both voice band voice and data communication systems. As a result, this codec has a variety of features not found in standard voice band codecs:
■ 3.0 V regulated power supply for a condenser micro-
phone.
■ Microphone preamplifier with programmable input
ranges.
■ Mute control of D/A output.
■ Programmable output gain in 3 dB increments.
■ Output speaker driver.
■ Programmable master clock divider to set A/D and
D/A conversion rate.
■ Testability loopba ck mode.
■ High-quality dither scheme to eliminate idle channel
tones.

4.2.2 Analog-to-Digital Path

The analog-to-digital (A/D) conversion signal path (see Figure 3 on page 5) begins with the analog input driving the input block. The signal from the input block is then encoded by a second-order ∆-Σ modulator A/D. The bulk of the antialiasing filtering is done in the digital domain in two stages following the ∆-Σ modulator to give a 16-bit result. The blocks will next be covered in more detail.

4.2.3 Analog Input Block

The A/D input block operates in two modes: when the external input gain select (EIGS) pin is low or left unconnected, the input goes through a preamplifier and is band limited by a second-order 30 kHz low-pass anti­aliasing filter (see Figure 4 on page 7). When EIGS is high, e xternal r esistor s, Rin and Rfb , are use d to set t he gain of an inverting amplifier (see Figure 5 on page 7). These resistors, in combination with Cin and Cfb, cre­ate a bandpass antialiasing filter. Note that EIGS is a digital pin whose input levels are relative to digital power and ground (V
and VSS).
DD

4.2.4 A/D Modulator and Digital Filters

A second-order ∆-Σ modulator quantizes the analog signal to 1 bit (see Figure 3 on page 5). At the same time, the resulting quantization noise is shaped such that most of this noise lies outside of the baseband. The modulator output is then digitally low-pass filtered to remove the out-of-band quantization noise. After this filtering, the output samples are decimated down to the output sampling frequency. In the CSP1027, the filter­ing and decimation are completed in two stages. The first-stage low-pass filter shapes the modulator output according to the sinc-cubic transfer function:

4.2 Description of Signal Paths

4.2.1 Sampling Frequency

The oversampling ratio of the codec is 125:1; this is the ratio of the frequency of the oversampling clock to the frequency of the sampling clock. Most speech applica­tions specify a sampling frequency of 8 kHz, yielding an oversampling frequency of 8 kHz x 125 = 1.0 MHz. The codec will operate at sampling frequencies up to 24 kHz, with the frequency response of the digital filters being changed proportionally. For this architectural description, the sampling frequency, f be 8 kHz, with an oversampling frequency, f 1 MHz, unless otherwise stated.
6
, is assumed to
S
, of
OS
The output sampling frequency of the sinc-cubic filter is reduced by a factor of 25 from 1 MHz to 40 kHz. The sinc-cubic filter places nulls in the frequency response at multiples of 40 kHz, and removes most of the quanti­zation noise above 20 kHz so that very little energy is aliased as a result of the decimation.
The sinc-cubic filter output is then processed by a seventh-order IIR digital low-pass filter. This filter removes the out-of-band quantization noise between
3.4 kHz and 20 kHz, compensates for the passband droop caused by the sinc-cubic decimator, and deci­mates the sampling frequency by a factor of five from 40 kHz to 8 kHz.
Lucent Technologies Inc.
Data Sheet CSP1027 Voice Band Codec for December 1999 Cellular Handset and Modem Applications
4 Architectural Information
(continued)
Following the low-pass filtering and decimation to 8 kHz, the 16-bit two's complement PCM can go directly to the output register,
cdx(A/D)
, or go to a third-order IIR digital high-pass filter and then to the output register. The –3 dB corner frequency of the high-pass filter is approximately 270 Hz. This filter exceeds the VSELP preprocessing requirements of IS-54 for attenuation of 60 Hz and 120 Hz signals. The high-pass filter is selected by writing the HPFE field in the
cioc3
register (see Table 10 on page 29). The default value upon reset is the high-pass filter
enabled (HPFE = 0).
Vin1
Vin2
EXTERNAL
COMPONENTS
Cin
MICIN
Cin
AUXIN
Rin
Rin
PREAMPLIFIER
AND AA-FILTER
+
AND
FILTERS
–
A/D
5-7592 (F)
Figure 4. CSP1027 A/D Path When in the Preamplifier Mode (EIGS = 0)
AUXIN
INTERNAL
SIGNAL GND
RfbCfb
RinCin
MICIN
EXTERNAL
COMPONENTS
–
+
INTERNAL
SIGNAL GND
+
FILTERS
–
A/D
AND
5-7593 (F)
Figure 5. CSP1027 A/D Path in the External Gain Select Mode (EIGS = 1)

4.2.5 A/D Path Frequency Response

The composite digital filters (decimator, LPF, and HPF) meet the ITU-T G.712 voice band frequency response specifications and are suitable for IS-54, JDC, and GSM digital cellular applications. Figures 6 through 9 show the A/D and D/A frequency response without the optional high-pass filter (HPF). Figures 10 and 11 show the group delay characteristics of the A/D and D/A with­out the high-pass filter. Figures 12 and 13 show the fre­quency response of the high-pass filter. Figures 14 and 15 show the group delay characteristics of the high­pass filter. In all figures, the frequency is normalized to the sampling frequency f
(i.e., frequency/fS). T o get the
S
actual frequency, multiply the normalized frequency by f
. The absolute delay and delay distortion have been
S
normalized to the sampling period 1/f
(i.e., delay x fS).
S
Lucent T echnologies Inc.
To obtain the actual delay, divide the normalized delay by f
. The templates shown in Figures 7 through 9,
S
11 through 13, and 15 correspond to the limits in the ITU-T G.712 specification where f
= 8.0 kHz.
S

4.2.6 PCM Saturation Versus Analog Input Levels

16-bit two's complement saturation is employed to pre­vent wraparound during input overload conditions. The saturation is hard-limiting:
0x7fff = maximum positive level 0x8000 = minimum negative level The analog levels that correspond to the saturation lev-
els for the three input modes are outlined in T ab le 14 on page 51.
7
CSP1027 Voice Band Codec for Data Sheet Cellular Handset and Modem Applications December 1999
4 Architectural Information
–20
–40
–60
–80
LOG MAGNITUDE (dB)
–100 –120
Figure 6. A/D or D/A Path Frequency Response Over 5.0 f
10
–10 –20 –30 –40 –50
LOG MAGNITUDE (dB)
–60 –70
–80
(continued)
20
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 FREQUENCY (fs = 1)
Bandwidth (HPF Disabled)
S
0
0.0 0.5 1.0 1.5 2.0 2.5
5-7594 (F)
FREQUENCY (fs = 1)
5-7595 (F)
Figure 7. A/D or D/A Path Frequency Response Over 2.5 f
8
Bandwidth (HPF Disabled)
S
Lucent Technologies Inc.
Data Sheet CSP1027 Voice Band Codec for
)
December 1999 Cellular Handset and Modem Applications
4 Architectural Information
10
–10 –20 –30 –40 –50
LOG MAGNITUDE (dB)
–60 –70
–80
Figure 8. A/D or D/A Path Frequency Response Over f
1.0
0.8
0.6
0.4
0.2
0.0 –0.2 –0.4
LOG MAGNITUDE (dB)
–0.6 –0.8
–1.0
(continued)
0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 FREQUENCY (fs = 1)
Bandwidth (HPF Disabled)
S
0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
5-7596 (F
Figure 9. A/D or D/A Path Frequency Response Over 0.5 f
Lucent T echnologies Inc.
FREQUENCY (fs = 1)
Bandwidth (HPF Disabled)
S
5-7597 (F)
9
CSP1027 Voice Band Codec for Data Sheet Cellular Handset and Modem Applications December 1999
4 Architectural Information
ABSOLUTE DELAY (# OF SAMPLES)
Figure 10. A/D or D/A Path Absolute Group Delay (HPF Disabled)
(continued)
8 7
6 5 4 3 2 1
0
0.0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 FREQUENCY (fs = 1)
8 7
5-7598 (F)
6 5 4 3 2 1
DELAY DISTORTION (# OF SAMPLES)
0
0.0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 FREQUENCY (fs = 1)
Figure 11. A/D or D/A Path Group Delay Distortion (HPF Disabled)
5-7599 (F)
10
Lucent Technologies Inc.
Data Sheet CSP1027 Voice Band Codec for December 1999 Cellular Handset and Modem Applications
4 Architectural Information
–10 –20 –30 –40 –50
LOG MAGNITUDE (dB)
–60 –70
–80
Figure 12. A/D or D/A Path Frequency Response Over f
1.0
0.8
0.6
0.4
0.2
0.0 –0.2 –0.4
LOG MAGNITUDE (dB)
–0.6 –0.8
–1.0
(continued)
10
0
–4
10
0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
–3
10
FREQUENCY (fs = 1)
10
–2
–1
10
Bandwidth (HPF Enabled)
S
10
0
5-7600 (F)
Figure 13. A/D or D/A Path Frequency Response Over 0.5 f
Lucent T echnologies Inc.
FREQUENCY (fs = 1)
Bandwidth (HPF Enabled)
S
5-7601 (F)
11
CSP1027 Voice Band Codec for Data Sheet Cellular Handset and Modem Applications December 1999
4 Architectural Information
25
20
15
10
ABSOLUTE DELAY (# OF SAMPLES)
Figure 14. A/D or D/A Path Absolute Group Delay (HPF Enabled)
(continued)
5
0
0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 FREQUENCY (fs = 1)
5-7602 (F)
8 7
6 5 4 3 2 1
DELAY DISTORTION (# OF SAMPLES)
0
0.00.050.100.150.200.250.300.350.400.450.50 FREQUENCY (fs = 1)
Figure 15. A/D or D/A Path Group Delay Distortion (HPF Enabled)
5-7603 (F)
12
Lucent Technologies Inc.
Data Sheet CSP1027 Voice Band Codec for December 1999 Cellular Handset and Modem Applications
4 Architectural Information
(continued)

4.2.7 Digital-to-Analog Path

Starting at the bottom right of Figure 3 on page 5, the ∆-Σ D/A conversion process begins with a 16-bit two's complement PCM signal read from the DI serial input. The PCM is interpolated up to 1 MHz in two stages and low-pass filtered at each stage to attenuate 8 kHz images.
The PCM input is latched into the
cdx(D/A)
register at a nominal word rate of 8 kHz. The signal is then option­ally high-pass filtered. This filter has the same transfer function as the A/D high-pass filter.
A digital sample-and-hold increases the word rate by a factor of 5 from 8 kHz to 40 kHz. The seventh-order IIR digital low-pass filter then removes the spectral images between 4 kHz and 20 kHz and predistorts the pass­band to compensate for the filtering done during the interpolation up to the 1 MHz word rate. The transfer function of this low-pass filter is the same as the one employed in the A/D converter.
The output of the low-pass filter feeds a programmable gain adjustment block that serves as a volume control. The gain can be changed in 3 dB increments from 0 dB to –45 dB. The attenuation level is set by writing the OGSEL field in the
cioc0
register (see Table 7 on
page 26). The digital modulator block further increases the word
rate by a factor of 25 from 40 kHz to 1 MHz. Through quantization and noise shaping, the digital ∆-Σ modula­tor creates 1-bit output words at 1 MHz.
The modulator 1-bit output drives a structure combining a 1-bit D/A converter and a second-order switched­capacitor filter having a cutoff frequency of 8 kHz (based on a 1 MHz clock). This is all shown as the D/A block in Figure 3 on page 5.

4.3 Programmable Features

4.3.1 Active/Inactive Modes

The CSP1027 has active and inactive modes of opera­tion which are selected by the ACTIVE field in the
cioc0
register (see Table 7 on page 26). The default value upon reset and powerup is ACTIVE = 0 (i.e., inactive). In the inactive mode, the codec clocks are disabled, data transfers by the codec are disabled, and analog bias currents are shut off. This state is useful in battery-powered applications when prolonged periods of inactivity are expected. It takes approximately 600 ms for the codec to reach full steady-state perfor­mance in going from inactive to active. This is primarily due to the charging of the large external capacitors, C
and C
REF
useful after 100 ms.

4.3.2 Input Select

When the A/D preamplifier is selected (EIGS = 0), the INSEL field of the preamp input between the MICIN and AUXIN inputs. When external gain select is used (EIGS = 1), the INSEL field has no effect.

4.3.3 A/D Input Ranges

When the preamplifier is used (EIGS = 0), the IRSEL field of the selects the 500 mVp range when IRSEL = 0 and the 160 mVp range when IRSEL = 1. IRSEL has no effect when the external gain select mode is used (EIGS = 1).
When EIGS = 1, the inverting amplifier of Figure 5 on page 7 replaces the preamplifier. The input range in this mode is the following:
. However, the codec is functionally
REG
cioc0
(see Table 7 on page 26) switches
cioc0
register (see T able 7 on page 26)
Rin
--------- -
FULL-SCALE
V
=
Rfb
1.578 V p
×
This is followed by a second-order active Chebychev fil­ter having a cutoff frequency of 35 kHz.
The passband ripple of the analog filters is small enough such that they have virtually no effect on the passband response.
The output amplifier buffers the analog filter output. The frequency responses of the A/D and D/A paths are
essentially the same. See Figures 6 through 15 for the magnitude and delay responses versus frequency.
Lucent T echnologies Inc.

4.3.4 Output Mute Function

The D/A converter output can be selectively muted with the MUTE field in the
cioc0
register (see Table 7 on page 26). The default value upon reset is muted (MUTE = 0). The mute function is implemented (Figure 3 on page 5) internally by a MUX following the D/A input. Placing the mute function here causes the signal at the analog output to gradually decay/rise over approximately 1 ms upon muting/unmuting. This effect is due to the impulse response and group delay of the digital filters. This implementation will reduce any potentially undesirable transient effects such as pops, when the D/A is muted.
13
CSP1027 Voice Band Codec for Data Sheet Cellular Handset and Modem Applications December 1999
4 Architectural Information
(continued)

4.3.5 Output Gains

The D/A converter output can be programmed in 3 dB increments with the OGSEL field in the
cioc0
register
(see Table 7 on page 26) to serve as a volume control.

4.3.6 Loopback Mode

The codec has a programmable loopback mode, repre­sented by the TEST field in the
cioc0
register, (see Table 7 on page 26). As shown in Figure 3 on page 5, when TEST = 0, the codec is in its normal mode of operation. When TEST = 1, the loopback mode is acti­vated. In loopback mode, the 1-bit PDM output signal from the analog modulator is received by the analog demodulator. At the same time, the 1-bit signal output from the digital modulator is received by the sinc-cubic filter in the A/D. This results in the analog input being looped back to the analog output through the A/D and D/A, and the digital input being looped back to the digi­tal output through the digital filters. The loopback mode can be useful for evaluating analog performance of the codec in the target system without going through the digital filters. This mode is also useful for evaluating the response of the digital filters or in evaluating the read/ write functions of the
codec
and
cdx
registers without
having to provide an analog input to the A/D.

4.3.7 High-Pass Filter Select

The high-pass filter in the A/D and D/A can be enabled or disabled with the HPFE field in the
cioc3
register
(see Table 10 on page 29).

4.3.8 Dither

A dithering scheme is employed in the CSP1027 which decorrelates the periodic quantization noise of the D/A modulator to make it white noise.
The DITHER field in the
cioc3
register (see Table 10 on page 29) disables this feature. The default value upon reset is DITHER = 0 (i.e., enabled). When the DITHER is disabled, the signal-to-noise ratio will gener­ally be about 2 dB higher. The DITHER should be enabled if the CSP1027 is used in an audio application, i.e., where this device interfaces to an audio trans­ducer. If the CSP1027 is used in an application other than audio, such as data communications, the DITHER can be disabled if so desired.

4.4 Power-On Reset

4.4.1 Internal

The CSP1027 has a power-on reset circuit that is ORed internally with the inversion of the reset pin, RSTB, to form the internal reset (see Figure 16 on page 15). The power-on reset circuit’s inverted output is also an output pin, PORB. The PORB can be used to provide power-on reset to the system.
The power-on reset circuit is composed of two pulse­generating elements, its output being the OR of the two. One element is entirely internal and generates a power-on pulse of 1.5 ms to 7.0 ms. The second ele­ment is composed of an input pin, PORCAP, a resistor connected between PORCAP and V ing input buffer. The user selects the capacitor value to connect between PORCAP and ground that will gener­ate a power-on pulse of desired width. The pin PORCAP allows the user to lengthen the power-on reset pulse to a width greater than the internal power­on element provides. The nominal value of the resistor is 155 kΩ, and the threshold of the inverting input buffer is 0.6 x V
. The formula that relates the power-on
DD
reset pulse delay to the PORCAP capacitor is as fol­lows:
D
T
= –R x C x loge (1 – 0.6)
D
T
= 0.9163 x R x C
, and an invert-
DD
∆-Σ converters are popular due to their high tolerance to component mismatch present in integrated circuit fabrication processes. However, ∆-Σ converters may suffer from periodic noise and spurious tone generation (in-band and out-of-band) due to the coarse quantiza­tion and feedback of the ∆-Σ modulator. Although this periodic noise may exist at very low levels (f or example, at about –90 dBm), it may be very objectionable to the listener while having virtually no impact on the resolu­tion of the converter. The CSP1027 D/A uses a robust dithering scheme which eliminates any potential prob­lems due to this phenomenon.
14
Hence, to generate a 14.2 ms power-on reset pulse, one would use a 0.1 µF capacitor connected between PORCAP and V
SS
.
An internal power-on pulse can be initiated after power­on by writing a one to the TSTPOR field in the
cioc3
register (see T able 10 on page 29). This causes the internal power-on pulse of 1.5 ms to 7.0 ms to be gen­erated. The pulse resets the device and appears on the PORB output pin.
Lucent Technologies Inc.
Data Sheet CSP1027 Voice Band Codec for December 1999 Cellular Handset and Modem Applications
4 Architectural Information
PORCAP
C
EXTERNAL
COMPONENT
XOSCEN
XLO
XHI
CLK
ENABLE
OSCILLATOR
(continued)
DD
V
R
TSTPOR
POWER-ON
PULSE
GENERATOR
RSTB
Figure 16. Power-On Reset Diagram
CDIFS, CDIF0, CDIF1, CDIF2,
CDIV3
ADJMOD,
ADJ
÷
F1
÷
ICLK
CDIV0
÷
CDIV2
1
M U
X
0
ICLK0
CKO2
÷
CDIV1
CKO1
PORB
INTERNAL
RESET
CK
÷
125
OS
CK
5-7604 (F)
S
Lucent T echnologies Inc.
5-7560 (F)
Figure 17. Clock Generation
15
CSP1027 Voice Band Codec for Data Sheet Cellular Handset and Modem Applications December 1999
4 Architectural Information
(continued)

4.5 Clock Generation

Figure 17 on page 15 shows the clock generation and distribution for the CSP1027. The programmable divid­ers can customize the codec sample and master clock rates for a variety of applications in addition to standard 8 kHz sampling, while allowing a range of values for the crystal-controlled input clock. In Figure 17 on page 15, XOSCEN is a chip input to enable the crystal oscil­lator circuit. XLO and XHI are the two leads for the crystal. CLK is the chip clock input if the crystal is not used. CK 8 kHz. CK typically 1 MHz. CKO1 and CKO2 are general-purpose clocks brought out to chip pins. CDIV1 and CDIV2 are programmable dividers with a range fr om 1 to 31. CDIV0 is programmed to be 1 or 2, but extra clock pulses can be added or subtracted at the output for one period of time following a write to the control register
cioc1
ber of clocks is programmed by ADJMOD and ADJ and causes a phase shift in the CKO1 and CK is an integral or a fractional divider controlled by the five programmable coefficients shown connected to it. With the fractional divide, the period of CK but the period of CK
The following discussion begins with the crystal oscilla­tor and is followed by a detailed description of each divisor block. Section 7.5 on page 45 provides some examples of how to program the clocks.

4.5.1 Crystal Oscillator

The CSP1027 has a selectable on-chip clock oscillator. A logic 1 on the XOSCEN pin enables the crystal oscil­lator. A logic 0 disables the oscillator, powers it down, and selects the input buffer connected to the CLK pin.
To use the oscillator, select a 20 MHz to 30 MHz funda­mental-mode crystal with a series resistance less than 60 Ω and a mutual capacitance less than 7.0 pF. Con­nect the crystal between the XLO and XHI pins, and add 10 pF capacitors between XLO and ground, and XHI and ground. The XOSCEN pin enables and dis­ables the crystal oscillator. See the application informa­tion on optimizing the oscillator performance.
is the internal codec sample clock, typically
S
is the internal codec oversampled clock,
OS
. This one-time increase or decrease in the num-
output. F1
S
will vary,
OS
will be constant.
S

4.5.2 Clock Divider 2

ICLK CKO2
÷
CDIV2
5-7589 (F)
Figure 18. Clock Divider 2
The CDIV2 field in
cioc0
(see Table 7 on page 26) sets the clock divider that generates the output clock, CKO2. The clock output is a general-purpose clock that can be used to clock external logic or processors. CDIV2 ranges from 1 to 31, with 0 holding the output low. RSTB going low sets CDIV2 to ÷16. CKO2 is active while RSTB is low and synchronized by RSTB going high.

4.5.3 Clock Divider 0

ADJMOD,
ADJ
ICLK ICLK0
÷
CDIV0
5-7588 (F)
Figure 19. Clock Divider 0
The CDIV0 field in
cioc1
(see Table 8 on page 27) sets the clock divider that generates the internal clock 0 (ICLK0) to either divide by one or divide by two. The ADJMOD and ADJ fields in
cioc1
are used to adjust the phase of ICLK0 by increasing or decreasing the rate of ICLK0 for a burst of pulses, one time only. This event occurs each time control register
cioc1
is written with nonzero values of ADJ. For example, let CDIV0 be set to ÷2, ADJ to seven, and ADJMOD to one (advance). After this word is written to the
cioc1
regis­ter, seven ICLK0 pulses will occur at the same rate as ICLK, not divided by two. These seven clock pulses shift the phase of CK
, CKS, and CKO1 earlier, thus
OS
advancing these clocks. If ADJMOD is set to zero (retard), the ÷2 becomes a ÷3 for seven pulses of ICLK0. The CDIV0 clock divider is temporarily changed internally so that it divides by one greater, to retard the clocks, or one less, to advance the clocks, for the spec­ified number of ICLK0 cycles. Note that the CDIV0 clock divider must be set to divide by two in order to advance and retard the clocks. If CDIV0 clock divider is set to divide by 1, one can only retard the clocks.
16
Lucent Technologies Inc.
Data Sheet CSP1027 Voice Band Codec for
F1 M S
N
125
--------- -
×


+=
fSf
OS
125÷f
ICLK
0
MS
N
125
--------- -
×+


÷
125
÷==
f
ICLK
0
f
S
----------------
125 M
×()
SN
×()+=
1
f
S
---- -
125 N
–()
M
f
ICLK
0
----------------
×
N
MS
+()
f
ICLK
0
--------------------
×+=
December 1999 Cellular Handset and Modem Applications
4 Architectural Information
(continued)
CDIV0 has values of 1 or 2, ADJMOD is 0 or 1, and ADJMOD ranges from 1 to 127, with 0 selecting no clock adjust. RSTB going low sets CDIV0 to ÷2. ICLK0 is active while RSTB is low and synchronized by RSTB going high.

4.5.4 Clock Divider 1

ICLK0 CKO1
÷
CDIV1
5-7587 (F)
Figure 20. Clock Divider 1
The CDIV1 field in
cioc1
(see Table 8 on page 27) sets a clock divider that generates the CKO1 output clock. This general-purpose clock output can be used for clocking another codec in the system, such as the CSP1084. The ability to phase adjust the output clock and the codec sampling clock simultaneously is an important feature. CDIV1 ranges from 1 to 31, with 0 disabling the output. RSTB going low sets CDIV1 to ÷16. CKO1 is active while RSTB is low and synchro­nized by RSTB going high.

4.5.5 Sampling Clocks Generation

CDIFS, CDIF0, DSIF1,
CDIF2, CDIV3
OS
CK
The CSP1027 solves this problem in a unique way, by providing a programmable, fractional divider, F1.
F1 is the programmable ratio between ICLK0 and CK
. The equation for F1 is:
OS
where 3 ≤ M ≤ 64, 0 ≤ N ≤ 62, and S = {1, –1}; or M = 2, 0 ≤ N ≤ 62, and S = 1; or M = 1, N = 0, and S = 1. M is encoded by CDIV3 (see Table 3 on page 18), N is
encoded by CDIF0, CDIF1, and CDIF2 (see Table 5 on page 19), and S is encoded by CDIFS (see Table 4 on page 18).
CK
is generated by dividing CKOS by 125. The fre-
S
quency of CK
can be described by:
S
Note that when N = 0, ICLK0 is simply divided by the integer M to create the oversampling clock, CK
OS
. This is the preferred method for generating the sampling clock. If N ≠ 0, the fractional division results in an over­sampling clock, CK
, whose period varies with time
OS
such that the average period is the desired fraction. This vari ation in the oversampling clock period is mini­mized by the clock generator but can cause distortion in the codec. Because the denominator of the fraction is fixed at 125, the period of the sampling clock, CK
S,
will be an integer multiple of the period of the internal clock, ICLK0, and will not vary. This is more clearly shown by the following equation:
ICLK0
÷
F1
÷
125
CK
S
The expanded equation below explains what is hap­pening in the time domain:
5-7586 (F)
Figure 21. Sampling Clocks Generation
1
During each sampling period, , there are (125 – N)
The oversampling codec clock CK is used in the front sections of the A/D and the back
, typically 1 MHz,
OS
oversampling clock cycles of period and N
sections of the D/A. The lower-frequency codec clock, CK
, typically 8 kHz, is the sample clock at th e output
S
oversampling clock cycles of period . The N
of the A/D and the input to the D/A. The sampling clock frequency, f
, is the oversampling clock frequency, fOS,
S
divided by 125 (the fixed oversampling ratio). The divide by 125 must remain fixed, since it is constrained by the architecture of the codec digital filters. Many sys­tems, however, have fixed high-frequency clocks and fixed sampling clocks, so it is necessary to have a great deal of flexibility in the creation of the codec clock CK
oversampling clock cycles are evenly distributed among the (125 – N) oversampling clock cycles to min­imize the distortion due to oversampling clock cycles of differing period. The values for CDIF[0—2] in Table 5 on page 19 have been selected to achieve the even distribution.
.
S
Lucent T echnologies Inc.
---- -
f
S
M
----------------
f
ICLK
0
MS
()
+
------------------- -
f
ICLK
0
17
CSP1027 Voice Band Codec for Data Sheet Cellular Handset and Modem Applications December 1999
4 Architectural Information
The procedure for selecting M, S, and N is illustrated in Section 7.5 on page 45. The ranges for the programmable dividers are summarized in Table 2.
Table 2. Programmable Divider Summary
Clock Ratio ICLK/ICLK0 ICLK0/CK
Variable Name CDIV0
Range of Values 1, 2 1, 2 to 64.496 125, 250 to 8062 Off, 1 to 31 Off, 1 to 31
Encoding 0, 1 See Tables 3
Table 3. CDIV3 Value for Each M
M CDIV3
1 00 0001 2 00 0010
.
. 62 11 1110 63 11 1111 64 00 0000
. .
(continued)
N
--------- -
M
±
125
through 5.
OS
ICLK0/CKS ICLK/CKO2 ICLK0/CKO1
125M ± N
See Tables 3
through 5.
CDIV2 CDIV1
0 to 31 0 to 31
Table 4. CDIFS Value for Each S
S CDIFS
+1 0 –1 1
18
Lucent Technologies Inc.
Data Sheet CSP1027 Voice Band Codec for December 1999 Cellular Handset and Modem Applications
4 Architectural Information
Table 5. CDIF0, CDIF1, CDIF2 Values for Each N
N CDIF0 CDIF1 CDIF2 N CDIF0 CDIF1 CDIF2
0 00 0000 00 0000 0 0000 32 00 0100 10 1000 0 0010 1 11 1111 00 0000 0 0000 33 00 0100 10 0100 0 0010 2 11 1101 00 0010 0 0000 34 00 0011 00 0010 1 0010 3 10 1001 00 0010 0 0000 35 00 0011 00 0010 1 0100 4 01 1111 00 0000 0 0000 36 00 0011 00 0010 0 0100 5 01 1001 00 0000 0 0000 37 00 0011 00 0011 1 0010 6 01 0101 10 0110 0 0000 38 00 0011 00 0011 0 0010 7 01 0010 10 0100 0 0000 39 00 0011 00 0100 0 0010 8 00 1111 00 0010 0 0000 40 00 0011 00 0111 0 0000
9 00 1110 10 0101 0 0000 41 00 0011 00 1110 0 0000 10 00 1100 00 0010 0 0000 42 00 0011 11 0110 0 0000 11 00 1011 00 0010 0 0010 43 00 0011 10 1001 0 0000 12 00 1010 00 0010 0 0010 44 00 0011 10 0110 0 0000 13 00 1001 00 0010 1 0010 45 00 0011 10 0100 0 0010 14 00 1001 10 0111 0 0010 46 00 0011 10 0011 0 0010 15 00 1000 00 0011 0 0000 47 00 0010 00 0010 1 0010 16 00 1000 10 0100 0 0010 48 00 0010 00 0010 1 0011 17 00 0111 00 0011 0 0000 49 00 0010 00 0010 1 0101 18 00 0111 10 1001 0 0010 50 00 0010 00 0010 0 0000 19 00 0110 00 0010 1 0011 51 00 0010 00 0010 0 0011 20 00 0110 00 0011 0 0010 52 00 0010 00 0010 0 0010 21 00 0110 10 1011 0 0000 53 00 0010 00 0011 1 0011 22 00 0101 00 0010 1 0010 54 00 0010 00 0011 0 0011 23 00 0101 00 0010 0 0010 55 00 0010 00 0011 0 0010 24 00 0101 00 0100 0 0010 56 00 0010 00 0100 0 0010 25 00 0101 00 0000 0 0000 57 00 0010 00 0101 0 0000 26 00 0101 10 0100 0 0010 58 00 0010 00 0110 0 0000 27 00 0100 00 0010 1 0011 59 00 0010 00 0111 0 0010 28 00 0100 00 0010 0 0011 60 00 0010 00 1010 0 0010 29 00 0100 00 0011 0 0000 61 00 0010 00 1111 0 0010 30 00 0100 00 0101 0 0010 62 00 0010 00 0000 0 0000 31 00 0100 00 0000 0 0000
(continued)
Lucent T echnologies Inc.
19
CSP1027 Voice Band Codec for Data Sheet Cellular Handset and Modem Applications December 1999
4 Architectural Information
(continued)

4.6 Serial I/O Configurations

4.6.1 Codec Data Transfer

When the codec is active, ACTIVE = 1 (see Table 7 on page 26), it loads data into the data from the
cdx(D/A)
register (see Figure 3 on page
5) at the sampling frequency, f on a 1 MHz oversampling frequency). The codec data transfers occur independent of the serial input/output data transfers described below. The data is double buffered, allowing the codec to transfer data to or from
cdx
the the shift registers (
while the serial I/O is shifting data into or out of
isr
and to inactive, ACTIVE = 0, there are no codec data trans­fers to the
cdx(A/D)
or from the
The internal STATUS flag is set high when loaded and
cdx(A/D)
cdx(D/A)
is emptied. Loading data from the
into the output shift register ( data from the input shift register ( due to a serial I/O transaction, clears the internal STA­TUS flag. The internal STATUS flag can be observed on the data output (DO) pin in the passive mode and causes data transfers in the active and multiprocessor modes.

4.6.2 Codec Control Writes

The four control registers are written through the serial port. The serial address (SADD) selects between con­trol and data transfers. Bits 15 and 14 of the control word being transferred select which control register,
cioc0, cioc1, cioc2
Bit[15:14] = 00,
cioc1
cioc3
, or
: Bit[15:14] = 01, etc.).

4.6.3 Serial I/O Port Overview

The CSP1027 serial I/O unit is an asynchronous, full­duplex, double-buffered channel operating at up to 20 Mbits/s that easily interfaces with other Lucent fixed­point DSPs (i.e., DSP16A and DSP1610/1616/1617/
1618) in a single or multiple DSP environment. Com­mercially available codecs and time-division multi­plexed (TDM) channels can be interfaced to the CSP1027 device with little, if any, external logic.
cdx(A/D)
(which is 8 kHz based
S
osr
). When the codec is set
cdx(D/A)
and empties
.
cdx(A/D)
osr
) or loading
isr
) into the
, is written (i.e.,
cdx(D/A)
cioc0
is
:
The serial interface is a subset of the standard Lucent DSP serial I/O and is comprised of eight pins:
■ A single passive serial input/output clock (IOCK).
■ A combined input load, output load, and synchroni-
zation (SYNC).
■ Serial data input (DI).
■ Serial data output (DO).
■ Serial address (SADD).
■ Three serial mode select pins (SMODE[2:0]).
The CSP1027's serial I/O is different from the standard Lucent serial I/O in a number of ways:
■ The SMODE[1:0] pins configure the serial I/O port
into one of four possible ways: a passive SIO config­uration, an active SIO configuration, and two multi­processor SIO configurati ons.
■ A fixed most significant bit (MSB) first data format.
■ A fixed 16-bit data mode.
■ The serial address (SADD) is an input during the
passive and active SIO configurations to select between data and control SIO transfers. It is intended to be connected to the DSP’s SADD pin, which is an output during passive and active SIO. Note that the DSP's SADD output is inverted and is composed of two 8-bit fields that are shifted out least significant bit (LSB) first.
■ The multiprocessor mode time slots and serial
addresses are restricted to two sets, one of which is selected based on the state of SMODE0.
■ The SMODE2 pin should always be tied low for the
serial I/O port to operate as described.
■ The frequency of the serial I/O interface clock input
IOCK (F the internal oversampling clock (F
IOCK
) must be greater than the frequency of
IOCK
).
20
Lucent Technologies Inc.
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