Advanced Linear Devices Inc ALD500RAU-20SEI, ALD500RAU-20SE, ALD500RAU-20QEI, ALD500RAU-20QE, ALD500RAU-20PEI Datasheet

ADVANCED
LINEAR
DEVICES, INC.

ALD500RAU/ALD500RA/ALD500R

PRECISION INTEGRATING ANALOG PROCESSOR

WITH PRECISION VOLTAGE REFERENCE

APPLICATIONS

• 4 1/2 digits to 5 1/2 digits plus sign measurements

• Precision analog signal processor

• Precision sensor interface

• High accuracy DC measurement functions

• Portable battery operated instruments

• Computer peripheral

• PCMCIA

FEATURES

• Resolution up to 18 bits plus sign bit and over-range bit

• Accuracy independent of input source impedances

• Accurate on-chip voltage reference

• Tempco as low as 10 ppm/°C guaranteed

• Chip select - power down mode

• High input impedance of 10

12

Ω

• Inherently filters and integrates any external noise spikes

• Differential analog input

• Wide bipolar analog input voltage range ±3.5V

• Automatic zero offset compensation

• Low linearity error - as low as 0.001% typical

• Fast zero-crossing comparator - 1µs

• Low power dissipation - 6mW typical

• Automatic internal polarity detection

• Low input current - 2pA typical

• Optional digital control from a microcontroller, an ASIC, or
a dedicated digital circuit

• Flexible conversion speed vs. resolution trade-off

BENEFITS

• Low cost, simple functionality

• Wide dynamic signal range

• Very high noise immunity

• Automatic compensation and cancellation
of error sources

• Easy to use to acquire bipolar signals

• Up to 19 bit (18 bit + sign bit) single conversion
or 21 bit (20 bit + sign bit) multiple conversion
and noise performance

• Inherently linear and stable with temperature
and component variations

PIN CONFIGURATION

ALD500R

I

1

B

C

2

INT

-

3

V

4

C

AZ

5

B

UF

6

AGND

-

7

C

REF

+

8

C

REF

9

N/C

10

N/C

QE, PE, SE PACKAGE

* N/C pin is connected internally. Connect to V

20

C

S

+

19

V
DGND

18
17

C

OUT

16

B

15

A

+

14

V

IN

-

V

13

IN

+

12

V

REF

-

11

V

REF

-

.

Ordering Information

Resolution Endpoint Voltage Reference Package Type Operating

16 bit 0.015% 0.5% 50ppm/C ALD500R-50PE ALD500R-50SE ALD500R-50QE 0°C to 70°C
17 bit 0.01% 0.3% 20ppm/C ALD500RA-20PE ALD500RA-20SE ALD500RA-20QE 0°C to 70°C
18 bit 0.005% ALD500RAU-20PE ALD500RAU-20SE ALD500RAU-20QE
17 bit 0.01% 0.2% 10ppm/C ALD500RA-10PE ALD500RA-10SE ALD500RA-10QE 0°C to 70°C
18 bit 0.005% ALD500RAU-10PE ALD500RAU-10SE ALD500RAU-10QE
17 bit 0.01% 0.3% 20ppm/C ALD500RA-20PEI ALD500RA-20SEI ALD500RA-20QEI -40°C to +85°C
18 bit 0.005% ALD500RAU-20PEI ALD500RAU-20SEI ALD500RAU-20QEI
18 bit 0.005% 0.3% 20ppm/C ALD500RAU-20DE -55°C to +125°C

Linearity Accuracy/Tempco Temperature

20L PDIP 20L SOIC 20L QSOP 20LCDIP

* Contact factory for customized voltage reference voltage levels, accuracy and tempco specifications.

Rev. 1.01 © 1999 Advanced Linear Devices, Inc., 415 Tasman Drive, Sunnyvale, California 94089-1706 Tel: [phone], Fax: [phone]

http://www.aldinc.com

R

= 100KΩ

REF

CB = 0.1µF

+

V

(14)

AGND

(6)



V

(13)

FIGURE 1. ALD500R Functional Block Diagram

C

N/C

SW

BUF

R

INT

INT

C

AZ

(5)

Integrator

­+

AZ

Bias

C

B

I

B

(1)

C

INT

C

AZ

(2)

(4)

Comp1

Analog
Switch
Control
Signals

C
(20)

+

-

S

-

Comp2

+

Polarity
Detection


Phase
Decoding
Logic


A

B

(16)(15)

Control Logic

Level 
Shift

C

OUT

(17)

DGND

(18)

C

REF

-

R

REF

REF

INT

SWRSW

-

SW

R

+

R

V

REF

(11)

R

+

R

-

SW

R

SW

G

SS

(3) (19) (10) (9)

-

C

REF

(7)

-

Buffer

+

SW

S

REF

Control

N/CVDDV

+

V

REF

(12)

+

C

REF

(8)

SW

IN

IN

SW

SW

Az

SW

SW

IN

-

IN

GENERAL DESCRIPTION

The ALD500RAU/ALD500RA/ALD500R are integrating
dual slope analog processors, designed to operate on ±5V
power supplies for building precision analog-to-digital
converters. The ALD500RAU/ALD500RA/ALD500R
feature specifications suitable for 18 bit/17 bit/16 bit
resolution conversion, respectively. Together with three
capacitors, two resistors, and a digital controller, a precision
Analog to Digital converter with auto zero can be
implemented. The digital controller can be implemented
by an external microcontroller, under either hardware
(fixed logic) or software control. For ultra high resolution
applications, up to 23 bit conversion can be implemented
with an appropriate digital controller and software.

The ALD500R series of analog processors accept
differential inputs and the external digital controller first
counts the number of pulses at a fixed clock rate that a
capacitor requires to integrate against an unknown analog
input voltage, then counts the number of pulses required
to deintegrate the capacitor against a known internal
reference voltage. This unknown analog voltage can then
be converted by the microcontroller to a digital word, which
is translated into a high resolution number, representing
an accurate reading. This reading, when ratioed against
the reference voltage, yields an accurate, absolute voltage
measurement reading.

The ALD500R analog processors consist of on-chip digital
control circuitry to accept control inputs, integrating buffer
amplifiers, analog switches, and voltage comparators and
a highly accurate, ultra-stable voltage reference. It
functions in four operating modes, or phases, namely auto
zero, integrate, deintegrate, and integrator zero phases.
At the end of a conversion, the comparator output goes
from high to low when the integrator crosses zero during
deintegration. ALD500R analog processors also provide
direct logic interface to CMOS logic families.

GENERAL THEORY OF OPERATION
Dual-Slope Conversion Principles of Operation

The basic principle of dual-slope integrating analog to digital
converter is simple and straightforward. A capacitor, C
charged with the integrator from a starting voltage, V

INT

, for a

X

, is

fixed period of time at a rate determined by the value of an
unknown input voltage, which is the subject of measurement.
Then the capacitor is discharged at a fixed rate, based on an
external reference voltage, back to V

where the discharge

X

time, or deintegration time, is measured precisely. Both the
integration time and deintegration time are measured by a
digital counter controlled by a crystal oscillator. It can be
demonstrated that the unknown input voltage is determined
by the ratio of the deintegration time and integration time, and
is directly proportional to the magnitude of the external reference
voltage.

The major advantages of a dual-slope converter are:

a. Accuracy is not dependent on absolute values of

integration time t

and deintegration time t

INT

DINT

, but is
dependent on their relative ratios. Long-term clock frequency
variations will not affect the accuracy. A standard crystal
controlled clock running digital counters is adequate to generate
very high accuracies.

b. Accuracy is not dependent on the absolute values of

R

INT and CINT

, as long as the component values do not vary
through a conversion cycle, which typically lasts less than 1
second.

c. Offset voltage values of the analog components, such

as VX, are cancelled out and do not affect accuracy.

d. Accuracy of the system depends mainly on the accuracy

and the stability of the voltage reference value.

2 Advanced Linear Devices ALD500RAU/ALD500RA/ALD500R

e. Very high resolution, high accuracy measurements

can be achieved simply and at very low cost.
An inherent benefit of the dual slope converter system is noise

immunity. The input noise spikes are integrated (averaged to
near zero) during the integration periods. Integrating ADCs
are immune to the large conversion errors that plague
successive approximation converters and other high resolution
converters and perform very well in high-noise environments.

The slow conversion speed of the integrating converter provides
inherent noise rejection with at least a 20dB/decade attenuation
rate. Interference signals with frequencies at integral multiples
of the integration period are, theoretically, completely removed.
Integrating converters often establish the integration period to
reject 50/60Hz line frequency interference signals.

The relationship of the integrate and deintegrate (charge
and discharge) of the integrating capacitor values are
shown below:

.

V

INT

= VX - (V

IN

t

/ R

. C

INT

INT

INT

)

(integrate cycle) (1)

.

= V

INT

- (V

V

X

REF

t

DINT

/ R

INT

.

C

)

INT

(deintegrate cycle) (2)

Combining equations 1 and 2 results in:

V

/ V

REF

= -t

IN

DINT

/ t

INT

(3)

V

= Reference Voltage

REF

C

= Integrating Capacitor value

INT

R

= Integrating Resistor value

INT

Actual data conversion is accomplished in two phases: Input
Signal Integration Phase and Reference Voltage Deintegration
Phase.

The integrator output is initialized to 0V prior to the start of
Input Signal Integration Phase. During Input Signal Integration

reference voltage is integrated

Phase, internal analog switches connect V

to the buffer

IN

input where it is maintained for a fixed integration time period
(t

). This fixed integration period is generally determined by

INT

a digital counter controlled by a crystal oscillator. The
application of V
a rate determined by V
polarity of V

causes the integrator output to depart 0V at

IN

.

IN

and a direction determined by the

IN

The Reference Voltage Deintegration Phase is initiated
immediately after t

, within 1 clock cycle. During

INT

ReferenceVoltage Deintegration Phase, internal analog
switches connect a reference voltage having a polarity opposite
that of V

to the integrator input. Simultaneously the same

IN

digital counter controlled by the same crystal oscillator used
above is used to start counting clock pulses. The Reference
Voltage Deintegration Phase is maintained until the comparator
output inside the dual slope analog processor changes state,
indicating the integrator has returned to 0V. At that point the
digital counter is stopped. The Deintegration time period

), as measured by the digital counter, is directly

(t

DINT

proportional to the magnitude of the applied input voltage.

where:

V

x

V

INT

V

IN

t

INT

t

DINT

= An offset voltage used as starting voltage
= Voltage change across C

during t

(equal in magnitude)

DINT

during t

INT

INT

and

= Average, or an integrated, value of input voltage

to be measured during t

(Constant VIN)

INT

= Fixed time period over which unknown voltage is

integrated

= Unknown time period over which a known

R

INT

ANALOG

INPUT

(V

)

IN

VOLTAGE

REFERENCE

OUTPUT

INTEGRATOR

t

INT

t

DINT

t

DINT

SWITCHES

S1

REF

V

IN ≈ VFULL SCALE

V

IN ≈ 1/2VFULL SCALE

V

≈

0

x



After the digital counter value has been read, the digital
counter, the integrator, and the auto zero capacitor are all
reset to zero through an Integrator Zero Phase and an Auto
Zero Phase so that the next conversion can begin again. In
practice, this process is usually automated so that analog-to­digital conversion is continuously updated. The digital control
is handled by a microprocessor or a dedicated logic controller.
The output, in the form of a binary serial word, is read by a
microprocessor or a display adapter when desired.

C

INT

INTEGRATOR

-

+

SWITCH DRIVER



POLARITY CONTROL

V

INT

= 4.1V MAX

V

INT

PHASE

CONTROL

COMPARATOR

-

+

POLARITY

DETECTION



CONTROL

LOGIC

AB

MICROCONTROLLER

(CONTROL LOGIC

+ COUNTER)

C

OUT

Figure 2. Basic Dual-Slope Converter

ALD500RAU/ALD500RA/ALD500R Advanced Linear Devices 3

ABSOLUTE MAXIMUM RATINGS

Supply voltage, V
Differential input voltage range -0.3V to V+ +0.3V
Power dissipation 600 mW
Operating temperature range PE, SE package 0°C to +70°C
Operating temperature range QE package -55°C to +125°C
Storage temperature range -65°C to +150°C
Lead temperature, 10 seconds +260°C

+

13.2V

OPERATING ELECTRICAL CHARACTERISTICS
T

= 25°C V

A

+

= +5V V- = -5V (V supply ± 5V) unless otherwise specified; CAZ = C

REF

= 0.47µf

500RAU 500RA 500R

Parameter Symbol Min Typ Max Min Typ Max Min Typ Max Unit Test Conditions

Resolution 15 30 60 µV Notes 1, 7

Zero-Scale Z
Error 0.003 0.005 0.008 %

End Point E
Linearity 0.007 0.015 0.020 0°C to +70°C

Best Case N
Straight Line

SE

NL

L

0.0025 0.003 0.005 % 0°C to 70°C

0.001 0.005 0.003 0.010 0.005 0.015 % Notes 1, 2

0.0025 0.003 0.005 0.003 0.008 % Notes 1, 2

Linearity 0.004 0.008 0.015 0°C to +70°C

Zero-Scale TC
Temperature

ZS

0.3 0.6 0.3 0.7 0.3 0.7 µV/°C0°C to +70°C

Coefficient 0.15 0.3 0.15 0.35 0.15 0.35 ppm/°C Notes 1, 7

Full-Scale S
Symmetry Error

YE

0.005 0.008 0.01 % 0°C to 70°C

(Rollover Error) 0.008 0.010 0.012 %

Full-Scale TC
Temperature Note 7

FS

1.3 1.3 1.3 ppm/°C0°C to +70°C

Coefficient

Input I
Current

IN

222pAV

= 0V

IN

Common-Mode CMVR V
Voltage Range

Integrator V
Output Swing

INT

Analog Input VINV
Signal Range

Voltage V
Reference

REF

+1.5

SS

V

+0.9

SS

+1.5

SS

V

+1

SS

V

-1.5 VSS+1.5

DD

V

-0.9 VSS+0.9

DD

V

-1.5 VSS+1.5

DD

VDD-1 V

+1 V

SS

V

V

-1.5

-0.9

-1.5

+1.5

SS

V

+0.9

SS

V

+1.5

SS

V

-1

+ 1

SS

DD

V

DD

V

DD

DD

V

DD

V

DD

V

DD

V

V

-1.5

V

-0.9

V AGND = 0V

-1.5

V

-1

DD

Range

4 Advanced Linear Devices ALD500RAU/ALD500RA/ALD500R