ADLINK PXIe-9852 User Manual
PXIe-9852
2-CH 14-Bit 200 MS/s Digitizer
User’s Manual
Manual Rev.: 2.00
Revision Date: Dec. 29, 2013
Part No: 50-17047-1000
Advance Technologies; Automate the World.
Revision History
Revision Release Date Description of Change(s)
2.00 12/29/2013 Initial Release
ii
PXIe-9852
Preface
Copyright 2014 ADLINK Technology, Inc.
This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form
without prior written permission of the manufacturer.
Disclaimer
The information in this document is subject to change without prior
notice in order to improve reliability, design, and function and does
not represent a commitment on the part of the manufacturer.
In no event will the manufacturer be liable for direct, indirect,
special, incidental, or consequential damages arising out of the
use or inability to use the product or documentation, even if
advised of the possibility of such damages.
Environmental Responsibility
ADLINK is committed to fulfill its social responsibility to global
environmental preservation through compliance with the European Union's Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE)
directive. Environmental protection is a top priority for ADLINK.
We have enforced measures to ensure that our products, manufacturing processes, components, and raw materials have as little
impact on the environment as possible. When products are at their
end of life, our customers are encouraged to dispose of them in
accordance with the product disposal and/or recovery programs
prescribed by their nation or company.
Conventions
Take note of the following conventions used throughout this
manual to make sure that users perform certain tasks and
instructions properly.
Preface iii
NOTE:
NOTE:
CAUTION:
Additional information, aids, and tips that help users perform
tasks.
Information to prevent minor physical injury, component damage, data loss, and/or program corruption when trying to complete a task.
Information to prevent serious physical injury, component
damage, data loss, and/or program corruption when trying to
complete a specific task.
iv Preface
PXIe-9852
Table of Contents
Preface .................................................................................... iii
List of Figures ....................................................................... vii
List of Tables.......................................................................... ix
1 Introduction ........................................................................ 1
1.1 Features............................................................................... 1
1.2 Applications ......................................................................... 2
1.3 Specifications....................................................................... 2
1.3.1 Analog Input ............................................................... 2
1.3.2 Timebase....................................................................4
1.3.3 Triggers ...................................................................... 5
1.3.4 General Specifications................................................ 6
1.4 Software Support ................................................................. 7
1.4.1 SDK ............................................................................ 7
1.4.2 WD-DASK................................................................... 7
1.5 Device Layout and I/O Array................................................ 8
2 Getting Started ................................................................. 11
2.1 Installation Environment .................................................... 11
2.2 Installing the Module.......................................................... 12
3 Operations ........................................................................ 15
3.1 Functional Block Diagram.................................................. 15
3.2 Analog Input Channel ........................................................ 15
3.2.1 Analog Input Front-End Configuration ...................... 15
3.2.2 Input Range and Data Format .................................. 16
3.2.3 DMA Data Transfer................................................... 16
3.3 Trigger Source and Trigger Modes.................................... 18
3.3.1 Software Trigger ....................................................... 19
Table of Contents v
3.3.2 External Digital Trigger ............................................. 19
3.3.3 PXI STAR Trigger .....................................................19
3.3.4 PXIe_DSTARB Trigger .............................................20
3.3.5 PXI Trigger Bus ........................................................20
3.3.6 Analog Trigger .......................................................... 20
3.3.7 Trigger Export ...........................................................21
3.4 Trigger Modes.................................................................... 21
3.4.1 Post Trigger Mode .................................................... 21
3.4.2 Delayed Trigger Mode .............................................. 21
3.4.3 Pre-Trigger Mode...................................................... 22
3.4.4 Middle Trigger Mode................................................. 23
3.4.5 Acquisition with Re-Triggering ..................................23
3.4.6 Data Average Mode (Post-Trigger and
Delayed-Trigger only) ............................................... 24
3.5 Timebase ........................................................................... 25
3.5.1 Internal Reference Clock .......................................... 25
3.5.2 External Reference Clock .........................................25
3.5.3 External Sampling Clock........................................... 25
3.5.4 PXI_CLK10 Clock.....................................................26
3.5.5 PXI_CLK100 Clock...................................................26
3.6 ADC Timing Control ........................................................... 26
3.6.1 Timebase Architecture.............................................. 26
3.6.2 Basic Acquisition Timing........................................... 26
3.7 Synchronizing Multiple Modules ........................................ 29
A Appendix: Calibration....................................................... 31
A.1 Calibration Constant .......................................................... 31
A.2 Auto-Calibration ................................................................. 31
Important Safety Instructions.............................................. 33
Getting Service ..................................................................... 35
vi Table of Contents
PXIe-9852
List of Figures
Figure 1-1: Analog Input Channel Bandwidth, ±0.2 Vpp............... 3
Figure 1-2: Analog Input Channel Bandwidth, ±2 Vpp.................. 4
Figure 1-3: PXIe-9852 Schematic................................................. 8
Figure 1-4: PXIe-9852 I/O Array ................................................... 9
Figure 3-1: Analog Input Architecture of the PXIe-9852 ............. 15
Figure 3-2: Linked List of PCI Address DMA Descriptors ........... 18
Figure 3-3: Trigger Architecture of the PXIe-9852 ...................... 18
Figure 3-4: External Digital Trigger ............................................. 19
Figure 3-5: Post-Trigger Acquisition ...........................................21
Figure 3-6: Delayed Trigger Mode Acquisition............................ 22
Figure 3-7: Pre-Trigger Mode Acquisition ................................... 22
Figure 3-8: Middle Trigger Mode Acquisition .............................. 23
Figure 3-9: Re-Trigger Mode Acquisition .................................... 24
Figure 3-10: PXIe-9852 Clock Architecture .................................. 25
Figure 3-11: PXIe-9852 Timebase Architecture............................ 26
Figure 3-12: Basic Digitizer Acquisition Timing............................. 27
Figure 3-13: Varying Sampling Rates by Adjusting Scan Interval
Counter28
List of Figures vii
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viii List of Figures
PXIe-9852
List of Tables
Table 1-1: Timebase......................................................................... 5
Table 1-2: Trigger Source & Mode.................................................... 5
Table 1-3: Digital Trigger Input .........................................................5
Table 1-4: Digital Trigger Output....................................................... 6
Table 1-5: PXIe-9852 I/O Array Legend .........................................10
Table 3-1: Input Range and Data Format ....................................... 16
Table 3-2: Input Range FSR and –FSR Values.............................. 16
Table 3-3: Input Range Midscale Values........................................ 16
Table 3-4: Counter Parameters and Description ............................29
List of Tables ix
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x List of Tables
1 Introduction
The PXIe-9852 is a high-speed 2-CH 14-Bit 200 MS/s digitizer,
specifically designed for applications such as LIDAR testing, optical fiber testing and radar signal acquisition. Analog input with 90
MHz bandwidth receives ±10V high speed signals with 50
impedance, and a simplified front-end design and highly stable
onboard reference provide both highly accurate measurement
results and high dynamic performance.
Ideal for environments requiring real-time acquisition and transfer
of data, the PXIe-9852 is based on the PCI Express Gen 2 x4 bus
as interface. When signals are converted from analog to digital,
continual data transfer to host system memory is enabled by PCI
Express high bandwidth capability.
The PXIe-9852 is auto-calibrated with an onboard reference circuit
calibrating offset and acquiring analog input errors. Following
auto-calibration, the calibration constant is stored in EEPROM,
such that these values can be loaded and used as needed by the
board. There is no requirement to calibrate the module manually.
1.1 Features
X PXI Express specification Rev. 1.0 compliant
X Up to 200 MS/s sampling rate
X 2 simultaneous analog inputs
X High resolution 14-Bit ADC
X Up to 90 MHz bandwidth for analog input
X One GB onboard storage memory
X Scatter-Gather DMA data transfer for high-speed data
streaming
X Supports signal averaging
X Support for:
Z one external digital trigger input
Z one digital trigger output to external instrument
Z one external clock input
Z auto-calibration
PXIe-9852
Introduction 1
1.2 Applications
X Distributed Temperature Sensing (DTS)
X Video IC testing
X Physics laboratory and research environments
X Cable fault location and partial discharge monitoring for
power applications
1.3 Specifications
1.3.1 Analog Input
Channel Characteristics Comment
Channels 2 single-ended
Connector type SMA
Input coupling
AC coupling cutoff
frequency
ADC resolution 14-Bit
Input signal range ±0.2V, ±2V or ±10V
Bandwidth (-3dB) 90 MHz
Overvoltage
Input impedance
Offset error ±1 mV
Gain error ±0.65%
SNR
AC or DC, software
selectable
11 Hz
±10V 1M
±10V sinewave / 7Vrms
with |Peaks| < 10V
50 or 1M, software
selectable
56dB 1M, ±0.2V
62dB 1M, ±2V
62dB 1M, ±10V
60dB 50, ±0.2V
62dB 50, ±2V
50
2 Introduction
Channel Characteristics Comment
-73dB 1M, ±0.2V
-69dB 1M, ±2V
THD
-65dB 1M, ±10V
-73dB 50, ±0.2V
-69dB 50, ±2V
72dB 1M, ±0.2V
72dB 1M, ±2V
SFDR
72dB 1M, ±10V
68dB 50, ±0.2V
68dB 50, ±2V
CrossTalk -80dB ±0.2V, ±2V
While ±10V, 50 acquisition is available, overvoltage protection only applies to 7Vrms. Any ±10V sine wave with an offset
CAUTION:
or DC voltage over ±7V input can cause damage.
PXIe-9852
0
−1
−2
−3
−4
−5
Magnitude (dB)
−6
−7
−8
−9
0.1M 0.3M 1M 3M 10M 30M 100M 300M
Bandwidth
Frequency (Hz)
Figure 1-1: Analog Input Channel Bandwidth, ±0.2 Vpp
Introduction 3
0
−1
−2
−3
−4
−5
Magnitude (dB)
−6
−7
−8
−9
0.1M 0.3M 1M 3M 10M 30M 100M 300M
Bandwidth
Frequency (Hz)
Figure 1-2: Analog Input Channel Bandwidth, ±2 Vpp
1.3.2 Timebase
Sample Clock Comment
Internal : on board synthesizer
Timebase options
Sampling clock
frequency
External : CLK IN (front panel),
PXI_CLK10, and PXIe_CLK100
Internal : 200MHz
External : 40MHz ~ 200MHz
(CLK IN)
3.052kS/s to
200MS/s
Timebase accuracy < ± 25ppm
External reference
clock source
Front panel, PXI_CLK10, and
PXIe_CLK100
4 Introduction
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