ADLINK PXIe-9848 User Manual
PXIe-9848
8-CH 14Bit 100 MS/s High-Speed PXI Express
Digitizer
User’s Manual
Manual Rev.: 2.01
Revision Date: Jan. 15, 2013
Part No: 50-17040-1010
Advance Technologies; Automate the World.
Revision History
Revision Release Date Description of Change(s)
2.00 2012/10/26 Initial Release
2.01 2013/01/15 Graphic labeling corrected
ii
PXIe-9848
Preface
Copyright 2013 ADLINK Technology, Inc.
This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form
without prior written permission of the manufacturer.
Disclaimer
The information in this document is subject to change without prior
notice in order to improve reliability, design, and function and does
not represent a commitment on the part of the manufacturer.
In no event will the manufacturer be liable for direct, indirect,
special, incidental, or consequential damages arising out of the
use or inability to use the product or documentation, even if
advised of the possibility of such damages.
Environmental Responsibility
ADLINK is committed to fulfill its social responsibility to global
environmental preservation through compliance with the European Union's Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE)
directive. Environmental protection is a top priority for ADLINK.
We have enforced measures to ensure that our products, manufacturing processes, components, and raw materials have as little
impact on the environment as possible. When products are at their
end of life, our customers are encouraged to dispose of them in
accordance with the product disposal and/or recovery programs
prescribed by their nation or company.
Conventions
Take note of the following conventions used throughout this
manual to make sure that users perform certain tasks and
instructions properly.
Preface iii
NOTE:
NOTE:
CAUTION:
WARNING:
Additional information, aids, and tips that help users perform
tasks.
Information to prevent minor physical injury, component damage, data loss, and/or program corruption when trying to complete a task.
Information to prevent serious physical injury, component
damage, data loss, and/or program corruption when trying to
complete a specific task.
iv Preface
PXIe-9848
Table of Contents
Preface .................................................................................... iii
List of Figures ....................................................................... vii
List of Tables.......................................................................... ix
1 Introduction ........................................................................ 1
1.1 Features............................................................................... 1
1.2 Applications ......................................................................... 2
1.3 Specifications....................................................................... 2
1.3.1 Analog Input ............................................................... 2
1.3.2 Timebase....................................................................3
1.3.3 Triggers ...................................................................... 4
1.3.4 General Specifications................................................ 4
1.4 Software Support ................................................................. 5
1.4.1 SDK ............................................................................ 5
1.4.2 WD-DASK................................................................... 6
1.5 Device Layout and I/O Array................................................ 7
2 ................................................................... Getting Started 9
2.1 Installation Environment ...................................................... 9
2.2 Installing the module.......................................................... 10
3 Operations ........................................................................ 13
3.1 Functional Block Diagram.................................................. 13
3.2 Analog Input Channel ........................................................ 13
3.2.1 Analog Input Front-End Configuration ...................... 13
3.2.2 Input Range and Data Format .................................. 15
3.2.3 FIFO and DMA Transfer For Analog Input ............... 16
3.3 Trigger Source and Trigger Modes.................................... 18
3.3.1 Trigger Sources ........................................................ 18
Table of Contents v
3.4 Trigger Modes.................................................................... 22
3.4.1 Post Trigger Mode .................................................... 23
3.4.2 Pre-trigger Mode....................................................... 23
3.4.3 Middle-trigger Mode.................................................. 24
3.4.4 Delayed Trigger Mode .............................................. 24
3.4.5 Post-Trigger or Delayed-Trigger Acquisition with Re-Trig-
gering........................................................................ 25
3.5 ADC Timing Control ........................................................... 25
3.5.1 Timebase Architecture.............................................. 25
3.5.2 Basic Acquisition Timing........................................... 26
4 Calibration ........................................................................ 29
4.1 Calibration Constant .......................................................... 29
4.2 Auto-Calibration ................................................................. 29
Important Safety Instructions.............................................. 31
Getting Service ..................................................................... 33
vi Table of Contents
PXIe-9848
List of Figures
Figure 1-1: Analog Input Channel Bandwidth, ±2 V Input Range
20MHz3
Figure 1-2: Analog Input Channel Bandwidth, ±2 V Input Range
100MHz3
Figure 1-3: PXIe-9848 Dimensions...............................................7
Figure 1-4: PXIe-9848 I/O Array ................................................... 8
Figure 3-1: Analog Input Architecture of the PXIe-9848 ............. 13
Figure 3-2: Linked List of PCI Address DMA Descriptors ........... 17
Figure 3-3: Trigger Architecture of the PXIe-9848 ...................... 18
Figure 3-4: External Digital Trigger ............................................. 19
Figure 3-5: External Digital Trigger Configuration....................... 20
Figure 3-6: Analog Trigger Conditions ........................................ 21
Figure 3-7: Post-Trigger Acquisition ........................................... 23
Figure 3-8: Pre-trigger Acquisition .............................................. 23
Figure 3-9: Middle-trigger Acquisition ......................................... 24
Figure 3-10: Delayed Trigger Mode Acquisition............................ 24
Figure 3-11: Re-Trigger Mode Acquisition .................................... 25
Figure 3-12: PXIe-9848 Timebase Architecture............................ 25
Figure 3-13: Basic Digitizer Acquisition Timing............................. 27
Figure 3-14: Varying Sampling Rates by Adjusting Scan Interval
Counter27
List of Figures vii
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viii List of Figures
PXIe-9848
List of Tables
Table 1-1: Channel Characteristics................................................... 2
Table 1-2: Analog Input Bandwidth................................................... 2
Table 1-3: Timebase......................................................................... 3
Table 1-4: Trigger Source & Mode.................................................... 4
Table 1-5: Digital Trigger Input .........................................................4
Table 1-6: PXIe-9848 I/O Array ........................................................8
Table 3-1: Input Range and Data Format ....................................... 15
Table 3-2: Input Range FSR and –FSR Values.............................. 15
Table 3-3: Input Range Midscale Values........................................ 15
Table 3-4: Ideal Transfer Characteristics for Analog Triggers ........ 22
Table 3-5: Counter Parameters and Description ............................28
List of Tables ix
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x List of Tables
1 Introduction
The PXIe-9848 high-speed 8CH 14-bit 100 MS/s digitizer is specifically designed for applications such as PSU (power supply unit)
testing, LIDAR testing, and radar signal acquisition. Analog inputs
with 100 MHz bandwidth can receive ±2V high-speed signals with
50 impedance. With a simplified front-end design and highly stable onboard reference, the PXIe-9848 provides not only highly
accurate measurement results but also superior dynamic performance.
For applications requiring real-time data acquisition and transfer,
PXIe-9848 is based on the PXI Express x4 bus interface. When
signals are converted from analog to digital, data is continuously
transferred to host system memory thanks to maximized PCI
Express bandwidth.
PXIe-9848's auto-calibration is performed with onboard reference
circuitry that calibrates the offset and gain errors of analog input.
Once complete, the calibration constant is stored in EEPROM, to
be loaded and used as needed by the board. Because all calibration is executed automatically by software command, no manual
calibration of the module is required.
PXIe-9848
1.1 Features
X PXI Express hardware specification Rev. 1.0 compliant
X Up to 100 MS/s sampling rate
X High resolution 14-Bit ADC
X 100 MHz bandwidth for analog input
X 512 MB onboard storage memory
X Scatter-Gather DMA data transfer for high-speed data
streaming
X One external digital trigger input
X Full auto-calibration
Introduction 1
1.2 Applications
X Radar signal acquisition
X IF signal spectrum monitoring
X Optical fiber testing
X Power supply unit (PSU) testing
X Cable fault location and partial discharge monitoring for
power applications
1.3 Specifications
1.3.1 Analog Input
Channel Characteristics
Channels 8 single-ended channels
Connector type SMB screw type
Input coupling AC or DC, software selectable
ADC resolution 14-Bit
Input signal range ±2.0 V or ±0.2 V
Overvoltage ±5 V
Input impedance 50 or 1 M, software selectable
Offset error ±1 mV
Gain error ±0.5%
Table 1-1: Channel Characteristics
Analog Input Bandwidth (-3 dB)
±2.0 V input 100 MHz or 20 MHz, software selectable
Table 1-2: Analog Input Bandwidth
2 Introduction
PXIe-9848
Figure 1-1: Analog Input Channel Bandwidth, ±2 V Input Range 20MHz
Figure 1-2: Analog Input Channel Bandwidth, ±2 V Input Range 100MHz
1.3.2 Timebase
Sample clock source Internal: onboard clock (oscillator)
Sample clock source Internal: onboard clock (oscillator)
External: PXI_CLK10, PXIe_CLK100
Timebase frequency 100 MHz
Sampling rate 100 MS/s ~ 1025.9 S/s
Internal Timebase Accuracy
Table 1-3: Timebase
Introduction 3
< s25 ppm
1.3.3 Triggers
Trigger Source & Mode
Software command, external digital trigger, analog
Trigger source
Trigger mode
Digital Trigger Input
Sources Front panel SMB connector
Configurable threshold 0.8 mV ~ 3.3 V, default 1.67 V
Adjustable step 0.8 mV, 3.3 V with 12-bit resolution
Maximum input overload -0.5 V ~ +5.5 V
Trigger polarity Rising or falling edge
Pulse width 20 ns minimum
inputs, PXI trigger bus [0..7], and PXIe_DSTARB and
PXI_STAR
Post-trigger, pre-trigger, middle trigger, and delay trigger,
re-trigger for all trigger modes
Table 1-4: Trigger Source & Mode
Table 1-5: Digital Trigger Input
1.3.4 General Specifications
Specifications
Physical dimensions 160 W x 100 H mm (6.3 x 3.94 in.)
Bus
Bus interface PXI Express, PXI hybrid compatible
PCIe signaling PCI Express x 4, Gen 1
Environmental toleance
Operating Temperature: 0°C - 50°C
Relative humidity: 5% - 95%, non-condensing
Storage Temperature: -20°C - +80°C
Relative humidity: 5% - 95%, non-condensing
4 Introduction
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