ADLINK PXIe-9529 User Manual
PXIe-9529
8-CH 24-Bit 192 kS/s
Dynamic Signal Acquisition Module
User’s Manual
Manual Rev.: 2.00
Revision Date: Oct. 31, 2013
Part No: 50-17045-1000
Advance Technologies; Automate the World.
Revision History
Revision Release Date Description of Change(s)
2.00 Oct. 31, 2013 Initial Release
ii
PXIe-9529
Preface
Copyright 2013 ADLINK Technology, Inc.
This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form
without prior written permission of the manufacturer.
Disclaimer
The information in this document is subject to change without prior
notice in order to improve reliability, design, and function and does
not represent a commitment on the part of the manufacturer.
In no event will the manufacturer be liable for direct, indirect,
special, incidental, or consequential damages arising out of the
use or inability to use the product or documentation, even if
advised of the possibility of such damages.
Environmental Responsibility
ADLINK is committed to fulfill its social responsibility to global
environmental preservation through compliance with the European Union's Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE)
directive. Environmental protection is a top priority for ADLINK.
We have enforced measures to ensure that our products, manufacturing processes, components, and raw materials have as little
impact on the environment as possible. When products are at their
end of life, our customers are encouraged to dispose of them in
accordance with the product disposal and/or recovery programs
prescribed by their nation or company.
Conventions
Take note of the following conventions used throughout this
manual to make sure that users perform certain tasks and
instructions properly.
Preface iii
NOTE:
NOTE:
CAUTION:
WARNING:
Additional information, aids, and tips that help users perform
tasks.
Information to prevent minor physical injury, component damage, data loss, and/or program corruption when trying to complete a task.
Information to prevent serious physical injury, component
damage, data loss, and/or program corruption when trying to
complete a specific task.
iv Preface
PXIe-9529
Table of Contents
Preface .................................................................................... iii
List of Figures ....................................................................... vii
List of Tables.......................................................................... ix
1 Introduction ........................................................................ 1
1.1 Features............................................................................... 1
1.2 Applications ......................................................................... 2
1.3 Specifications....................................................................... 2
1.3.1 Analog Input ............................................................... 2
1.3.2 Timebase....................................................................5
1.3.3 Triggers ...................................................................... 6
1.3.4 General Specifications................................................ 6
1.4 Software Support ................................................................. 7
1.4.1 SDK ............................................................................ 7
1.4.2 DSA-DASK ................................................................. 7
1.5 Device Layout and I/O Array................................................ 8
2 Getting Started ................................................................. 11
2.1 Installation Environment .................................................... 11
2.2 Installing the Module.......................................................... 12
3 Operations ........................................................................ 13
3.1 Functional Block Diagram.................................................. 13
3.2 Analog Input Channel ........................................................ 13
3.2.1 Analog Input Front-End Configuration ...................... 13
3.2.2 Input Range and Data Format .................................. 15
3.2.3 ADC and Analog Input Filter.....................................15
3.2.4 DMA Data Transfer................................................... 16
3.3 Trigger Source and Trigger Modes.................................... 18
Table of Contents v
3.4 Trigger Mode...................................................................... 21
3.5 ADC Timing Control ........................................................... 23
3.5.1 Timebase..................................................................23
3.5.2 DDS Timing vs. ADC ................................................ 24
3.5.3 Filter Delay in ADC ................................................... 24
3.6 Synchronizing Multiple Modules ........................................ 24
3.6.1 SSI_TIMEBASE........................................................ 26
3.6.2 SSI_SYNC_START .................................................. 26
3.6.3 SSI_TRIG .................................................................26
A Appendix: Calibration....................................................... 27
A.1 Calibration Constant .......................................................... 27
A.2 Auto-Calibration ................................................................. 27
Important Safety Instructions.............................................. 29
Getting Service ..................................................................... 31
vi Table of Contents
PXIe-9529
List of Figures
Figure 1-1: Analog Input Channel Bandwidth, ±0.2 Vpp...............4
Figure 1-2: Analog Input Channel Bandwidth, ±2 Vpp..................5
Figure 1-3: PXIe-9529 Schematic.................................................8
Figure 1-4: PXIe-9529 I/O Array ................................................... 9
Figure 3-1: Analog Input Architecture ......................................... 13
Figure 3-2: Linked List of PCI Address DMA Descriptors ........... 17
Figure 3-3: Trigger Architecture .................................................. 18
Figure 3-4: External Digital Trigger ............................................. 19
Figure 3-5: Analog Trigger Conditions ........................................ 20
Figure 3-6: Post-Trigger Acquisition ........................................... 22
Figure 3-7: Delay Trigger Mode Acquisition................................ 22
Figure 3-8: Re-Trigger Mode Acquisition .................................... 23
Figure 3-9: Timebase Architecture.............................................. 23
Figure 3-10: SSI Architecture........................................................ 25
List of Figures vii
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viii List of Figures
PXIe-9529
List of Tables
Table 1-1: Channel Characteristics................................................... 3
Table 1-2: Timebase......................................................................... 5
Table 1-3: Trigger Source & Mode.................................................... 6
Table 1-4: Digital Trigger Input .........................................................6
Table 3-1: Input Range and Data Format ....................................... 15
Table 3-2: Input Range Midscale Values........................................ 15
Table 3-3: ADC Sample Rates vs DDS Output Clock..................... 16
Table 3-4: Preferred Characteristics for Analog Triggers ...............21
Table 3-5: Timing Relationship between ADC and PLL Clock........ 24
Table 3-6: ADC Filter Delay ............................................................ 24
Table 3-7: SSI Timing Signal Definitions ........................................25
List of Tables ix
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x List of Tables
1 Introduction
The PXIe-9529 is a high-performance 8-CH 24-Bit 192 kS/s
dynamic signal acquisition module, specifically designed for applications such as structural health monitoring, noise, vibration, and
harshness (NVH) measurement, and phased array data acquisition.
The PXIe-9529 features 24-bit simultaneous sampling at 192 kS/s
over 8 channels, and a 110 dB dynamic range, providing ample
power for high-density, high channel count signal measurement,
and vibration-optimized lower AC cutoff frequency of 0.3 Hz. All
input channels incorporate 4 mA bias current for integrated electronic piezoelectric (IEPE) signal conditioning for accelerometers
and microphones.
The PXIe-9529 is auto-calibrated with an onboard reference circuit
calibrating offset and acquiring analog input errors. Following
auto-calibration, the calibration constant is stored in EEPROM,
such that these values can be loaded and used as needed by the
board. There is no requirement to calibrate the module manually.
1.1 Features
X PXI Express specification Rev. 1.0 compliant
X Up to 200 MS/s sampling rate
X 8 simultaneous analog inputs
X 192 kS/s maximum sampling rate
X AC or DC input coupling, software selectable
X Support for:
Z One external digital trigger input
Z IEPE output on each analog input, software configurable
Z Auto-calibration
PXIe-9529
Introduction 1
1.2 Applications
X Structural health monitoring
X Phase array data acquisition
X Noise, vibration, and harshness (NVH) detection
X Machine status monitoring
1.3 Specifications
1.3.1 Analog Input
Channel Characteristics Comment
Channels 8
Type Differential or Pseudo-Differential
Coupling AC or DC, software selectable
AC coupling cutoff
frequency
ADC resolution 24-Bit
ADC type Delta-sigma
Input signal range ±10V, ±1V
Sampling rate (fs)
Over voltage
protection
Input impedance
Offset error ±1 mV max.
Gain error ±0.1% of FSR
0.5Hz
8 kS/s to 192 kS/s,
768 S/s increments for fs > 108 kS/s,
576 S/s increments for 54 kS/s fs
108 kS/s
Differential: ±42.4V,
Pseudo-differential:
X positive terminal ±42.4 V
X negative terminal unpro-
tected, rated at ±2.5 V
1M, (50 between negative input
and system ground for
pseudo-differential mode)
2 Introduction
PXIe-9529
Channel Characteristics Comment
103 dB fs = 8.0 kS
SNR, @fin = 1kHz
THD < -106 dB
SFDR > 106 dB
crosstalk < -100 dB
-3 dB bandwidth
IEPE
Current
Compliance 24V
104 dB fs = 54.0 kS
99 dB fs = 108 kS
98 dB fs = 192 kS
>0.4863 fs fs < 108 kS
≅ 0.2 fs fs > 108 kS
4 mA, each channel independently
software configurable
Table 1-1: Channel Characteristics
Introduction 3
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