ADLINK PXIe-9529 User Manual

Download

PXIe-9529

8-CH 24-Bit 192 kS/s

Dynamic Signal Acquisition Module

User’s Manual

Manual Rev.: 2.00

Revision Date: Oct. 31, 2013

Part No: 50-17045-1000

Advance Technologies; Automate the World.

Revision History

Revision Release Date Description of Change(s)

2.00 Oct. 31, 2013 Initial Release

PXIe-9529

Preface

This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.

Disclaimer

The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not represent a commitment on the part of the manufacturer.

In no event will the manufacturer be liable for direct, indirect, special, incidental, or consequential damages arising out of the use or inability to use the product or documentation, even if advised of the possibility of such damages.

Environmental Responsibility

ADLINK is committed to fulfill its social responsibility to global environmental preservation through compliance with the European Union's Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE) directive. Environmental protection is a top priority for ADLINK. We have enforced measures to ensure that our products, manufacturing processes, components, and raw materials have as little impact on the environment as possible. When products are at their end of life, our customers are encouraged to dispose of them in accordance with the product disposal and/or recovery programs prescribed by their nation or company.

Conventions

Take note of the following conventions used throughout this manual to make sure that users perform certain tasks and instructions properly.

Preface iii

NOTE:

CAUTION:

WARNING:

Additional information, aids, and tips that help users perform tasks.

Information to prevent minor physical injury, component damage, data loss, and/or program corruption when trying to complete a task.

Information to prevent serious physical injury, component damage, data loss, and/or program corruption when trying to complete a specific task.

iv Preface

PXIe-9529

Preface .................................................................................... iii

List of Figures ....................................................................... vii

List of Tables.......................................................................... ix

1 Introduction ........................................................................ 1

1.1 Features............................................................................... 1

1.2 Applications ......................................................................... 2

1.3 Specifications....................................................................... 2

1.3.1 Analog Input ............................................................... 2

1.3.2 Timebase....................................................................5

1.3.3 Triggers ...................................................................... 6

1.3.4 General Specifications................................................ 6

1.4 Software Support ................................................................. 7

1.4.1 SDK ............................................................................ 7

1.4.2 DSA-DASK ................................................................. 7

1.5 Device Layout and I/O Array................................................ 8

2 Getting Started ................................................................. 11

2.1 Installation Environment .................................................... 11

2.2 Installing the Module.......................................................... 12

3 Operations ........................................................................ 13

3.1 Functional Block Diagram.................................................. 13

3.2 Analog Input Channel ........................................................ 13

3.2.1 Analog Input Front-End Configuration ...................... 13

3.2.2 Input Range and Data Format .................................. 15

3.2.3 ADC and Analog Input Filter.....................................15

3.2.4 DMA Data Transfer................................................... 16

3.3 Trigger Source and Trigger Modes.................................... 18

Table of Contents v

3.4 Trigger Mode...................................................................... 21

3.5 ADC Timing Control ........................................................... 23

3.5.1 Timebase..................................................................23

3.5.2 DDS Timing vs. ADC ................................................ 24

3.5.3 Filter Delay in ADC ................................................... 24

3.6 Synchronizing Multiple Modules ........................................ 24

3.6.1 SSI_TIMEBASE........................................................ 26

3.6.2 SSI_SYNC_START .................................................. 26

3.6.3 SSI_TRIG .................................................................26

A Appendix: Calibration....................................................... 27

A.1 Calibration Constant .......................................................... 27

A.2 Auto-Calibration ................................................................. 27

Important Safety Instructions.............................................. 29

Getting Service ..................................................................... 31

vi Table of Contents

PXIe-9529

List of Figures

Figure 1-1: Analog Input Channel Bandwidth, ±0.2 Vpp...............4

Figure 1-2: Analog Input Channel Bandwidth, ±2 Vpp..................5

Figure 1-3: PXIe-9529 Schematic.................................................8

Figure 1-4: PXIe-9529 I/O Array ................................................... 9

Figure 3-1: Analog Input Architecture ......................................... 13

Figure 3-2: Linked List of PCI Address DMA Descriptors ........... 17

Figure 3-3: Trigger Architecture .................................................. 18

Figure 3-4: External Digital Trigger ............................................. 19

Figure 3-5: Analog Trigger Conditions ........................................ 20

Figure 3-6: Post-Trigger Acquisition ........................................... 22

Figure 3-7: Delay Trigger Mode Acquisition................................ 22

Figure 3-8: Re-Trigger Mode Acquisition .................................... 23

Figure 3-9: Timebase Architecture.............................................. 23

Figure 3-10: SSI Architecture........................................................ 25

List of Figures vii

This page intentionally left blank.

viii List of Figures

PXIe-9529

List of Tables

Table 1-1: Channel Characteristics................................................... 3

Table 1-2: Timebase......................................................................... 5

Table 1-3: Trigger Source & Mode.................................................... 6

Table 1-4: Digital Trigger Input .........................................................6

Table 3-1: Input Range and Data Format ....................................... 15

Table 3-2: Input Range Midscale Values........................................ 15

Table 3-3: ADC Sample Rates vs DDS Output Clock..................... 16

Table 3-4: Preferred Characteristics for Analog Triggers ...............21

Table 3-5: Timing Relationship between ADC and PLL Clock........ 24

Table 3-6: ADC Filter Delay ............................................................ 24

Table 3-7: SSI Timing Signal Definitions ........................................25

List of Tables ix

This page intentionally left blank.

x List of Tables

1 Introduction

The PXIe-9529 is a high-performance 8-CH 24-Bit 192 kS/s dynamic signal acquisition module, specifically designed for applications such as structural health monitoring, noise, vibration, and harshness (NVH) measurement, and phased array data acquisition.

The PXIe-9529 features 24-bit simultaneous sampling at 192 kS/s over 8 channels, and a 110 dB dynamic range, providing ample power for high-density, high channel count signal measurement, and vibration-optimized lower AC cutoff frequency of 0.3 Hz. All input channels incorporate 4 mA bias current for integrated electronic piezoelectric (IEPE) signal conditioning for accelerometers and microphones.

The PXIe-9529 is auto-calibrated with an onboard reference circuit calibrating offset and acquiring analog input errors. Following auto-calibration, the calibration constant is stored in EEPROM, such that these values can be loaded and used as needed by the board. There is no requirement to calibrate the module manually.

1.1 Features

X PXI Express specification Rev. 1.0 compliant

X Up to 200 MS/s sampling rate

X 8 simultaneous analog inputs

X 192 kS/s maximum sampling rate

X AC or DC input coupling, software selectable

X Support for:

Z One external digital trigger input

Z IEPE output on each analog input, software configurable

Z Auto-calibration

PXIe-9529

Introduction 1

1.2 Applications

X Structural health monitoring

X Phase array data acquisition

X Noise, vibration, and harshness (NVH) detection

X Machine status monitoring

1.3 Specifications

1.3.1 Analog Input

Channel Characteristics Comment

Channels 8

Type Differential or Pseudo-Differential

Coupling AC or DC, software selectable

AC coupling cutoff

frequency

ADC resolution 24-Bit

ADC type Delta-sigma

Input signal range ±10V, ±1V

Sampling rate (fs)

Over voltage protection

Input impedance

Offset error ±1 mV max.

Gain error ±0.1% of FSR

0.5Hz

8 kS/s to 192 kS/s, 768 S/s increments for fs > 108 kS/s, 576 S/s increments for 54 kS/s  fs 108 kS/s

Differential: ±42.4V, Pseudo-differential:

X positive terminal ±42.4 V X negative terminal unpro-

tected, rated at ±2.5 V

1M, (50 between negative input and system ground for pseudo-differential mode)

2 Introduction

PXIe-9529

Channel Characteristics Comment

103 dB fs = 8.0 kS

SNR, @fin = 1kHz

THD < -106 dB

SFDR > 106 dB

crosstalk < -100 dB

-3 dB bandwidth

IEPE

Current

Compliance 24V

104 dB fs = 54.0 kS

99 dB fs = 108 kS

98 dB fs = 192 kS

>0.4863 fs fs < 108 kS

≅ 0.2 fs fs > 108 kS

4 mA, each channel independently software configurable

Table 1-1: Channel Characteristics

Introduction 3

−5

−10

−15

Magnitude (dB)

−20

−25

0 1 2 3 4 5 6

Magnitude Response

Frequency (Hz)

Figure 1-1: Analog Input Channel Bandwidth, ±0.2 Vpp

x 10

4 Introduction

PXIe-9529

−2

−4

−6

Magnitude (dB)

−8

−10

−12 0 1 2 3 4 5 6 7 8 9 10

Response when AC coupling enabled

Frequency (Hz)

Figure 1-2: Analog Input Channel Bandwidth, ±2 Vpp

1.3.2 Timebase

Sampling Clock

Timebase options

Internal: onboard synthesizer

External: PXI_CLK10, PXIe_CLK100

Timebase accuracy < ± 25ppm

Table 1-2: Timebase

Introduction 5

1.3.3 Triggers

Trigger Source & Mode

Trigger source

Trigger mode Post trigger and delay trigger

Digital Trigger Input

Sources Front panel SMA connector

Compatibility 3.3 V TTL, 5 V tolerant

Input high threshold 2.0 V

Input low threshold (VIL) 0.8 V

Maximum input overload -0.5 V to +5.5 V

Trigger polarity Rising or falling edge

Pulse width 20 ns minimum

Software, external digital trigger, analog trigger, PXI trigger bus[0..7], PXI_STAR, and PXIe_DSTARB

Table 1-3: Trigger Source & Mode

Table 1-4: Digital Trigger Input

1.3.4 General Specifications

Physical

Physical dimensions 160 W x 100 H mm (6.24 x 3.9 in)

Bus

Bus interface PCI Express Gen 1 x 4

Environmental Tolerance

Operating

Storage

Calibration

Onboard reference +5.000 V

6 Introduction

Temperature: 0°C - 55°C

Relative humidity: 10% - 90%, non-condensing

Temperature: -20°C - +80°C

Relative humidity: 10% - 90%, non-condensing

PXIe-9529

Calibration

Temperature coefficient < 5.0 ppm/°C

Warm-up time 15 minutes

Power Consumption

Power Rail Standby Current (mA) Full Load (mA)

+3.3 V 102 102.2

+12 V 20 20

+5V 1920 2010

1.4 Software Support

ADLINK provides versatile software drivers and packages to suit various user approaches to building a system. Aside from programming libraries, such as DLLs, for most Windows-based systems, ADLINK also provides drivers for other application

environments such as LabVIEW®.

All software options are included in the ADLINK All-in-One CD. Commercial software drivers are protected with licensing codes. Without the code, you may install and run the demo version for trial/demonstration purposes for only up to two hours. Contact your ADLINK dealer to purchase the software license.

1.4.1 SDK

For customers who want to write their own programs, ADLINK provides the following software development kits.

Z DAQPilot for Windows, compatible with various applica-

tion environments, such as VB.NET, VC.NET, VB/VC++, BCB, and Delphi

Z DAQPilot for LabVIEW

Z Toolbox adapter for MATLAB

1.4.2 DSA-DASK

DSA-DASK includes device drivers and DLL for Windows XP/7/8. DLL is binary compatible across Windows XP/7/8. This

Introduction 7

means all applications developed with DSA-DASK are compatible with these Windows operating systems. The development environment may be VB, VB.NET, VC++, BCB, and Delphi, or any Windows programming language that allows calls to a DLL. The DSA-DASK user and function reference manuals are on the ADLINK All-in-One CD.

1.5 Device Layout and I/O Array

All dimensions are in mm

NOTE:

165.04

162.54

100

200.59

Figure 1-3: PXIe-9529 Schematic

8 Introduction

PXIe-9529

The PXIe-9529 I/O array is labeled to indicate connectivity, as shown.

Figure 1-4: PXIe-9529 I/O Array

Introduction 9

This page intentionally left blank.

10 Introduction

2 Getting Started

This chapter describes proper installation environment, installation procedures, package contents and basic information users should be aware of regarding the PXIe-9529.

Diagrams and illustrated equipment are for reference only. Actual system configuration and specifications may vary.

NOTE:

2.1 Installation Environment

When unpacking and preparing to install, please refer to Important Safety Instructions.

Only install equipment in well-lit areas on flat, sturdy surfaces with access to basic tools such as flat- and cross-head screwdrivers, preferably with magnetic heads as screws and standoffs are small and easily misplaced.

Recommended Installation Tools

X Phillips (cross-head) screwdriver

X Flat-head screwdriver

X Anti-static wrist strap

X Antistatic mat

ADLINK PXIe-9529 DSA modules are electrostatically sensitive and can be easily damaged by static electricity. The module must be handled on a grounded anti-static mat. The operator must wear an anti-static wristband, grounded at the same point as the anti-static mat.

PXIe-9529

Getting Started 11

Inspect the carton and packaging for damage. Shipping and handling could cause damage to the equipment inside. Make sure that the equipment and its associated components have no damage

before installation.

The equipment must be protected from static discharge and physical shock. Never remove any of the socketed parts

CAUTION:

except at a static-free workstation. Use the anti-static bag shipped with the product to handle the equipment and wear a grounded wrist strap when servicing.

X Package Contents

X PXIe-9529 dynamic signal acquisition module

X ADLINK All-in-One compact disc

X PXIe-9529 Quick Start Guide

If any of these items are missing or damaged, contact the dealer

Do not install or apply power to equipment that is damaged or missing components. Retain the shipping carton and packing

WARNING:

materials for inspection. Please contact your ADLINK dealer/vendor immediately for assistance and obtain authorization before returning any product.

2.2 Installing the Module

1. Turn off the PXI system/chassis and disconnect the power cable from the power source.

2. Align the module edge with the module guide in the PXI chassis.

3. Slide the module into the chassis until resistance is felt from the PXI connector.

4. Push the ejector upwards and firmly seat the module into the chassis.

5. Once the module is fully seated, a “click” can be heard from the ejector latch.

6. Tighten the screw on the front panel.

7. Connect the power plug to a power source and turn on the PXI system/chassis.

12 Getting Started

3 Operations

This chapter contains information regarding analog input, triggering and timing for the PXIe-9529.

3.1 Functional Block Diagram

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

TRG IN

JFET Buffer

OPAMP

Reference &

Calibration

BUF

Control

PGA

3.2 Analog Input Channel

Quad

24bit ADC

ADC

Quad

24bit ADC

ADC

2-bit /12.288MHz

ADC Ctrl

CLK

Synthesizer

2-bit / 12.288MHz

ADC Ctrl

DC-DC\

LDO

10 MHz

CLK100p/n

PXI CLK10

3.3V 5V

12V

Board to Board Conn x2

PXI CLK10

Geographical Address [0..4]

PCIe Controller

FPGA

ADC Control

Trigger Control

Data Processing

FIFO Interface

DDR2 512MB

Memory

Trigger Bus [0..7]

3.3V 5V

12V

CLK100p/n,

PXIe_DSTARAp/n

ADC BUS

PXIe-9529

SYNC100p/n,

PXIe_DSTARBp/n

PXIe_DSTARCp/n

PCIe Gen1

XJ4

XJ3

PXIe Hybrid Peripheral Slot

3.2.1 Analog Input Front-End Configuration

Signal Switch

CAL+

IEPE+

330nF / 25V

SPST

49.9R

SPST

330nF / 25V

CAL-

IEPE-

Vref

10k

1MR

Cal+

Figure 3-1: Analog Input Architecture

Operations 13

JFET OPAMP

X1 X10 PGA

24-bit ADC

10k

DATA

SCK

ADC Ctrl

CARR

Vref

Differential and Pseudo-Differential Input Configuration

The PXIe-9529 provides both differential and psuedo-differential input configurations, with differential input mode providing voltage to the anode and cathode inputs of the SMB connector according to signal voltage difference therebetween. If the signal source is ground-referenced, differential input mode can be used for common-mode noise rejection.

If the signal source is a floating signal, pseudo-differential input mode can provide a reference ground connected to the cathode input of the SMB through a 50  resistor, preventing the floating source from drifting over the input common-mode range.

Recommended configurations for the signal sources are as follows.

Signal Source Type Card Configuration

Floating Pseudo Differential

Ground-Reference Differential

AC and DC Input Coupling

AC and DC coupling are available. With DC coupling, DC offset present in the input signal is passed to ADC, and is indicated if the signal source has a small level of offset voltage or if DC content of the signal is important. In AC coupling, the DC offset present in the input signal is erased, and is indicated if the DC content of the input signals is to be rejected. AC coupling enables a high pass R-C filter through the input signal path. The corner frequency (-3dB) is about 0.5Hz.

Input for IEPE

For applications that require sensors such as accelerometers or microphones, the PXIe-9529 provides an excitation current source. The common excitation current is usually about 4mA for these IEPE sensors. A DC voltage offset is generated due to the excitation current and sensor impedance. When IEPE current sources are enabled, the PXIe-9529 automatically sets input configuration to AC coupling.

14 Operations

PXIe-9529

3.2.2 Input Range and Data Format

When using an A/D converter, properties of the signal to be measured should be considered prior to selecting channel and signal connection to the module. A/D acquisition is initiated by a trigger source, which must be predetermined.Data acquisition commences once the trigger condition is established. Following completion of A/D conversion, A/D data is buffered in a Data FIFO, and can then be transferred to PC memory for further processing. Transfer characteristics of the two input ranges of the PXIe-9529 are as follows. Data format of the PXIe-9529 is 2’s complement.

Description

Bipolar Analog Input

Digital Code N/A N/A 7FFFFF 800000

Description Midscale +1LSB Midscale Midscale –1LSB

Bipolar Analog Input

Digital Code 000001 000000 -FFFFFF

Full-scale range

±10 V 1.19 V 9.99999881 V -10 V

±1V 0.119 V 0.999999881V -1 V

Table 3-1: Input Range and Data Format

1.19 V 0 V -1.19 V

0.119 V 0 V -0.119 V

Table 3-2: Input Range Midscale Values

Least significant bit

FSR-1LSB -FSR

3.2.3 ADC and Analog Input Filter

ADC (Analog-to-Digital Converter)

The PXIe-9529 provides sigma-delta analog-to-digital converters, suitable for vibration, audio, and acoustic measurement. Analog side of the sigma-delta ADC is 1-bit, and the digital side performs oversampling, noise shaping and digital filtering. For example, if a desired sampling rate is 108kS/s, each ADC samples input signals

Operations 15

at 27.648MS/s, 256 times the sampling rate. The 1-bit 27.648MS/s data streams from 1-bit ADC to its internal digital filter circuit to produce 24-bit data at 108kS/s. The noise shaping removes quantization noise from low frequency to high frequency. At the last stage, the digital filter improves ADC resolution and removes high frequency quantization noise. The relationship between ADC sample rate and DDS output clock is as follows.

Sampling Rate DDS(PLL) CLK

8k to 54kS/s 6.144M~41.472MHz

54K to 108kS/s 13.824 M to 27.648 MHz

108K to 192kS/s 20.736 M to 36.864 MHz

Table 3-3: ADC Sample Rates vs DDS Output Clock

Filter

Each channel has a two-pole lowpass filter. The filters limit bandwidth of the signal path and reject wideband noise.

3.2.4 DMA Data Transfer

The PXIe-9529, as a PCIe Gen1 X 4 device, provides a 192KS/s sampling rate ADC, generating a 3.072 MByte/second rate. To provide efficient data transfer, a PCI bus-mastering DMA is essential for continuous data streaming, as it helps to achieve the full potential PCI Express bus bandwidth. The bus-mastering controller releases the burden on the host CPU since data is directly transferred to the host memory without intervention. Once analog input operation begins, the DMA returns control of the program. During DMA transfer, the hardware temporarily stores acquired data in the onboard AD Data FIFO, and then transfers the data to a user-defined DMA buffer in the computer.

Using a high-level programming library for high speed DMA data acquisition, the sampling period and the number of conversions needs simply to be assigned into specified counters. After the AD trigger condition is met, the data will be transferred to the system memory by the bus-mastering DMA. In a multi-user or multi-task-

16 Operations

PXIe-9529

ing OS, such as Microsoft Windows, Linux, or other, it is difficult to allocate a large continuous memory block. Therefore, the bus controller provides DMA transfer with

scatter-gather function to link non-contiguous memory blocks into a linked list to enable transfer of large amounts of data without memory limitations. In non-scatter-gather mode, the maximum DMA data transfer size is 2 MB double words (8 MB bytes); in scatter-gather mode, there is no limitation on DMA data transfer size except the physical storage capacity of the system. Users can also link descriptor nodes circularly to achieve a multibuffered DMA. A linked list comprising three DMA descriptors. Each descriptor contains a PCI address, PCI dual address, a transfer size, and the pointer to the next descriptor.PCI address and PCI dual address support 64-bit addresses which can be mapped into more than 4 GB of address space, as shown.

First PCI Address PCI Address PCI Address

First Dual Address Dual Address

Transfer Size

Next Descripto

Transfer Size

Next Descripto

Dual Address

Transfer Size

Next Descripto

PCI Bus

Local Memory

(FIFO)

Figure 3-2: Linked List of PCI Address DMA Descriptors

Operations 17

3.3 Trigger Source and Trigger Modes

SMB Connector

Analog CH0 Analog CH1 Analog CH2

Analog CH3 Analog CH4

Analog CH5 Analog CH6

Analog CH7

PXI Interface

TRG IN

Digital Trigger Input

Analog Trigger

Selection

Software Trigger

Analog

Trigger

PXI_STAR

PXIe_DSTARB

PXI Trigger Bus[0:7]

Trigger Source Mux

Trigger

Decision

To Internal FPGA

Circuit

SSI_TRIG1 SSI_TRIG2

SSI_START_OP

PXI Trigger

Bus[0:7]

Trigger Output Mux

Figure 3-3: Trigger Architecture

The PXIe-9529 requires a trigger to implement acquisition of data. Configuration of triggers requires identification of trigger source. The PXIe-9529 supports internal software trigger, external digital trigger, PXI_STAR trigger, PXIe_DSTARB, PXI Trigger Bus [0.7], and SSI bus as well as analog trigger.

Software Trigger

The software trigger, generated by software command, is asserted immediately following execution of specified function calls to begin the operation.

External Digital Trigger

An external digital trigger is generated when a TTL rising edge or a falling edge is detected at the SMB connector on the front panel. As shown, trigger polarity can be selected by software. Note that the signal level of the external digital trigger signal should be TTL compatible, with minimum pulse width 10ns.

PXI Interface

18 Operations

PXIe-9529

Pulse Width > 10ns

Rising

edge trigger event

PXI STAR Trigger

When PXI STAR is selected as the trigger source, the PXIe-9529 accepts a TTL-compatible digital signal as a trigger signal. The trigger occurs when a rising edge or falling edge is detected at PXI STAR, with trigger polarity configurable by software, with minimum pulse width requirement of the digital trigger signal 300 ns.

PXIe_DSTARB Trigger

The PXIe_DSTARB signal, a differential signal transmitted via the PXI Express Chassis backplane, distributes high-speed, high-quality trigger signals. When PXIe_DSTARB is selected as the trigger source, the PXIe-9529 accepts a fast-switching LVDS digital signal as a trigger signal. Triggering occurs when a rising edge or falling edge is detected at PXIe_DSTARB, with trigger polarity configurable by software, with minimum pulse width requirement 300 ns.

PXI Trigger Bus

The PXIe-9529 utilizes PXI Trigger Bus Numbers 0 through 7 to act as a System Synchronization Interface (SSI). With the interconnected bus provided by PXI Trigger Bus, multiple modules are easily synced. When configured as input, the PXIe-9529 serves as a slave module and can accept trigger

Figure 3-4: External Digital Trigger

Pulse Width > 10ns

Falling

edge trigger

event

Operations 19

signals from one of buses 0 through 7. When configured as output, the PXIe-9529 serves as a master module and can output trigger signals to the PXI Trigger Bus Numbers 0 through 7.

Analog Trigger

The PXIe-9529 analog trigger circuitry can be configured to monitor one analog input channel from which data is acquired. Selection of an analog input channel as the analog trigger channel does not influence the input channel acquisition operation. The analog trigger circuit generates an internal digital trigger signal based on the condition between the analog signal and the defined trigger level.

Analog trigger conditions are as follows:

Z Positive-slope trigger: The trigger event occurs when the

analog input signal changes from a voltage lower than the specified trigger level to a voltage exceeding the specified trigger level.

Z Negative-slope trigger: The trigger event occurs when

the analog input signal changes from a voltage exceeding the specified trigger level to a voltage lower than the specified trigger level.

Positive-Slope Trigger Event

Occurs

Negative-Slope Trigger

Event Occurs

Trigger Level

Analog

Signal

Figure 3-5: Analog Trigger Conditions

Trigger signal can be chosen from among CH0, CH1, CH2,CH3, CH4, CH5, CH6 and CH7 during use of an external

20 Operations

PXIe-9529

analog trigger source. The trigger level can be set by software with 24-bit resolution, with characteristics as shown.

Trigger Level Setting (Hex)

7FFFFF 9.99999881 V 0.999999881 V

7FFFFE 9.99999762 V 0.999999762 V

1 1.19 V 0.119 V

00V 0V

FFFFFF -1.19 V -0.119 V

800001 -9.99999881 V -0.999999881 V

800000 -10 V -1 V

Table 3-4: Preferred Characteristics for Analog Triggers

Trigger Voltage (-10V to +10V Range)

Trigger Voltage (-1V to +1V Range)

Trigger Export

The PXIe-9529 can export trigger signals to PXI Trigger Bus Numbers 0 through 7, utilizing them to act as the System Synchronization Interface. When configured as the output, the PXIe-9529 serves as a master module and can output trigger signals to synchronize the slave modules, with the trigger signal routed to any of the seven PXI Trigger Bus Numbers via software.

3.4 Trigger Mode

Two trigger modes applied to trigger sources initiate different data acquisition timings when a trigger event occurs, as applied to analog input and output functions.

Post Trigger Mode

If post trigger mode is configured, activity commences once the following trigger conditions are met:

Z The analog input channel acquires a programmed num-

ber of samples at a specified sampling rate

Z The analog output channel outputs pre-defined voltage

at a specified output rate

Operations 21

Figure 3-6: Post-Trigger Acquisition

Delay Trigger Mode

If delay trigger mode is configured, delay time from when the trigger event asserts to the beginning of the acquisition and waveform generation can be specified, as shown. Delay time is specified by a 32-bit counter value with the counter clocking based on the PCIe clock. Accordingly, maximum delay time is the period of PCIe_CLK X (2^32 - 1) and minimum is the period of PCIe_CLK (8 ns).

Acquisition stop Begin to transfer data to system

Time

Trigger

Data

Operation start

Trigger Event Occurs

Delay Time

Acquisition start

N samples

Figure 3-7: Delay Trigger Mode Acquisition

Post-Trigger or Delay-Trigger Acquisition with Re-Trigger

Post-trigger or delay trigger acquisition with re-trigger function enables collection of data after several trigger events, as shown. When the number of triggers is defined, the PXIe-9529 acquires specific sample data each time a trigger is accepted. All sampled data is stored in onboard memory first, until all trigger events have occurred, such that time between the previous sampled data and the subsequent trigger event can be only

22 Operations

PXIe-9529

one clock period of PCIe CLK. After the initial setup, no additional software intervention is required.

Operation

1st Trigger Event Occurs

start

Trigger

Data

N samples N samples

Figure 3-8: Re-Trigger Mode Acquisition

3.5 ADC Timing Control

3.5.1 Timebase

Onboard

Oscillator

10M

PXIe_CLK100

PXI_CLK10

PXI Interface

PXI Trigger Bus[0:7]

8-to-1 MUX

Timebase Clock Mux

2nd Trigger Event Occurs

SYNC_CLK

ADC0_CLK

ADC1_CLK

1-to-4 Clock

Buffer & PLL

FPGA_MCLK

Time

PXI Trigger Bus[0:7]

1-to-8 MUX

PXI Interface

Figure 3-9: Timebase Architecture

An onboard timebase clock drives the sigma-delta ADC, with frequency exceeding the sample rate and produced by a PLL chip, with output frequency programmable to superior resolution. The PXIe- 9529 accepts the external 10MHz and 100MHz clocks from the PXI Express backplane for improved synchronization between modules.

Operations 23

3.5.2 DDS Timing vs. ADC

Sampling Rate 8k – 54kS/s 54k - 108kS/s 108 k – 192kS/s

6.144

DDS(PLL) CLK

Table 3-5: Timing Relationship between ADC and PLL Clock

M-41.472 MHz

13.824 M-27.648 MHz

20.736 M-36.864 MHz

3.5.3 Filter Delay in ADC

Filter delay indicates time required for data propagation through a converter. Both AI channels experience filter delay due to filter

circuitry and converter architecture, as shown.

Update Rate (kS/s) Filter Delay (samples)

8 K - 54 kS/s 13

54 K - 108 kS/s 13

108 K-192 kS/s 5

Table 3-6: ADC Filter Delay

3.6 Synchronizing Multiple Modules

The SSI (System Synchronization Interface) provides DAQ timing synchronization between multiple cards, with a bidirectional SSI I/O providing flexible connection between cards and allowing a single SSI master to output the signal to other slave modules. SSI signals are designed for card synchronization only, not external devices. In the PXI Express form factor, the PXI trigger bus built on the PXI Express backplane provides the necessary timing signal connections. All SSI signals are routed to the XJ4 connector, with no requirement for additional cabling. The eight interconnected lines on the PXI Express backplane, labeled PXI Trigger Bus[0:7] provide a flexible interface for syncing multiple modules. The PXIe-9529 utilizes the PXI Trigger Bus [0:7] as a System Synchronization Interface (SSI). Flexible routing of timebase clock and trigger signals onto the PXI Trigger Bus enables the PXIe-9529 to simplify synchronization between multiple modules.The bidirectional SSI I/O provides flexible connection between modules,

24 Operations

PXIe-9529

allowing the single SSI master PXIe-9529 to output the SSI signals to other slave modules. SSI timing signals and functions are as shown, as is the SSI architecture.

SSI Timing Signal Functionality

SSI master: issues TIMEBASE

SSI_TIMEBASE

SSI_SYNC_START

SSI_AD_TRIG

Table 3-7: SSI Timing Signal Definitions

SSI slave: accepts SSI_TIMEBASE to replace the internal TIMEBASE signal.

SSI master: issues internal SYNC_START SSI slave: accepts SSI_SYNC_START as the digital trigger signal.

SSI master: issues internal AD_TRIG SSI slave: accepts SSI_AD_TRIG as the digital trigger signal.

PXI Trigger

Bus[0:7]

PXI Interface

One

Trigger Bus

[7..0]

One

Trigger Bus

[7..0]

One

Trigger Bus

[7..0]

SSI_TIMEBASE

SSI_AD_TRG

SSI_SYNC_START

Timing Control

SSI_AD_TRIG

SSI_SYNC_ST ART

Figure 3-10: SSI Architecture

Operations 25

Different signals cannot be routed onto the same trigger bus line.

NOTE:

The three internal timing signals can be routed to the PXI trigger bus through software drivers. Physically, signal routing is accomplished in the FPGA, with cards connected together through the PXI trigger bus achieving synchronization on the three timing signals, as follows.

3.6.1 SSI_TIMEBASE

As output, the SSI_TIMEBASE signal transmits the onboard ADC timebase through the PXI trigger bus. As input, the PXIe-9529 accepts the SSI_TIMEBASE signal as the source of the timebase.

3.6.2 SSI_SYNC_START

Before a SSI master issues SSI_TRIG to other SSI slaves, SSI_SYNC_START is first asserted by the master card, synchronizing all on-chip ADCs in both SSI Master and SSI Slave modules.

3.6.3 SSI_TRIG

As output, the SSI_TRIG signal reflects the trigger event signal in an acquisition sequence. As input, the PXIe-9529 accepts the SSI_TRIG signal as the trigger event source. The signal is configured in the rising edge-detection mode, with minimum pulse width 8ns.

26 Operations

Appendix A Calibration

This chapter introduces the calibration process to minimize analog input measurement errors.

A.1 Calibration Constant

The PXIe-9529 is factory calibrated before shipment, with associated calibration constants written to the onboard EEPROM. At system boot, the PXIe-9529 driver loads these calibration constants, such that analog input path errors are minimized. ADLINK provides a software API for calibrating the PXIe-9529.

The onboard EEPROM provides two banks for calibration constant storage. Bank 0, the default bank, records the factory calibrated constants, providing written protection preventing erroneous auto-calibration. Bank 1 is user-defined space, provided for storage of self-calibration constants. Upon execution of auto-calibration, the calibration constants are recorded to Bank 1.

When PXIe-9529 boots, the driver accesses the calibration constants and is automatically set to hardware. In the absence of user assignment, the driver loads constants stored in bank 0. If constants from Bank 1 are to be loaded, the preferred bank can be designated as boot bank by software. Following re-assignment of the bank, the driver will load the desired constants on system reboot. This setting is recorded to EEPROM and is retained until reconfiguration.

PXIe-9529

A.2 Auto-Calibration

Because errors in measurement and outputs will vary with time and temperature, re-calibration is recommended when the module is installed. Auto-calibration can measure and minimize errors without external signal connections, reference voltages, or measurement devices.

The PXIe-9529 has an on-board calibration reference to ensure the accuracy of auto-calibration. The reference voltage is measured on the production line and recorded in the on-board EEPROM.

Calibration 27

Before initializing auto-calibration, it is recommended to warm up the PXIe-9529 for at least 20 minutes and remove connected cables.

It is not necessary to manually factor delay into applications, as the PXIe-9529 driver automatically adds the compensation

NOTE:

time.

28 Calibration

PXIe-9529

Important Safety Instructions

For user safety, please read and follow all instructions, WARNINGS, CAUTIONS, and NOTES marked in this manual and

on the associated equipment before handling/operating the equipment.

X Read these safety instructions carefully.

X Keep this user’s manual for future reference.

X Read the specifications section of this manual for detailed

information on the operating environment of this equipment.

X When installing/mounting or uninstalling/removing

equipment:

Z Turn off power and unplug any power cords/cables.

X To avoid electrical shock and/or damage to equipment:

Z Keep equipment away from water or liquid sources;

Z Keep equipment away from high heat or high humidity;

Z Keep equipment properly ventilated (do not block or

cover ventilation openings);

Z Make sure to use recommended voltage and power

source settings;

Z Always install and operate equipment near an easily

accessible electrical socket-outlet;

Z Secure the power cord (do not place any object on/over

the power cord);

Z Only install/attach and operate equipment on stable

surfaces and/or recommended mountings; and,

Z If the equipment will not be used for long periods of time,

turn off and unplug the equipment from its power source.

Important Safety Instructions 29

X Never attempt to fix the equipment. Equipment should only

be serviced by qualified personnel.

X A Lithium-type battery may be provided for uninterrupted,

backup or emergency power.

Risk of explosion if battery is replaced with an incorrect type; please dispose of used batteries appropriately.

WARNING:

X Equipment must be serviced by authorized technicians

when:

Z The power cord or plug is damaged;

Z Liquid has penetrated the equipment;

Z It has been exposed to high humidity/moisture;

Z It is not functioning or does not function according to the

user’s manual;

Z It has been dropped and/or damaged; and/or,

Z It has an obvious sign of breakage.

30 Important Safety Instructions

Getting Service

ADLINK Technology, Inc.

Address: 9F, No.166 Jian Yi Road, Zhonghe District New Taipei City 235, Taiwan

ᄅקؑխࡉ೴৬ԫሁ 166 ᇆ 9 ᑔ

Tel: +886-2-8226-5877 Fax: +886-2-8226-5717 Email: service@adlinktech.com

Ampro ADLINK Technology, Inc.

Address: 5215 Hellyer Avenue, #110, San Jose, CA 95138, USA Tel: +1-408-360-0200 Toll Free: +1-800-966-5200 (USA only) Fax: +1-408-360-0222 Email: info@adlinktech.com

ADLINK Technology (China) Co., Ltd.

Address: Ϟ⍋Ꮦ⌺ϰᮄᓴ∳催⾥ᡔು㢇᯹䏃 300 ো(201203) 300 Fang Chun Rd., Zhangjiang Hi-Tech Park,

Pudong New Area, Shanghai, 201203 China Tel: +86-21-5132-8988 Fax: +86-21-5132-3588 Email: market@adlinktech.com

ADLINK Technology Beijing

Address: ࣫ҀᏖ⍋⎔Ϟഄϰ䏃 1 োⲜ߯ࡼ࡯໻ E ᑻ 801 ᅸ(100085)

Rm. 801, Power Creative E, No. 1,

Shang Di East Rd., Beijing, 100085 China Tel: +86-10-5885-8666 Fax: +86-10-5885-8626 Email: market@adlinktech.com

PXIe-9529

ADLINK Technology Shenzhen

Address: ⏅ഇᏖቅ⾥ᡔು催ᮄϗ䘧᭄ᄫᡔᴃು

Tel: +86-755-2643-4858 Fax: +86-755-2664-6353 Email: market@adlinktech.com

LiPPERT ADLINK Technology GmbH

Address: Hans-Thoma-Strasse 11, D-68163, Mannheim, Germany Tel: +49-621-43214-0 Fax: +49-621 43214-30 Email: emea@adlinktech.com

A1 󰶀 2 ὐ C  (518057)

2F, C Block, Bldg. A1, Cyber-Tech Zone, Gao Xin Ave. Sec. 7,

High-Tech Industrial Park S., Shenzhen, 518054 China

Getting Service 31

ADLINK Technology, Inc. (French Liaison Office)

Address: 15 rue Emile Baudot, 91300 Massy CEDEX, France Tel: +33 (0) 1 60 12 35 66 Fax: +33 (0) 1 60 12 35 66 Email: france@adlinktech.com

ADLINK Technology Japan Corporation

Address: ͱ101-0045 ᵅҀ䛑ҷ⬄⼲⬄䤯ފ⬎ 3-7-4

Tel: +81-3-4455-3722 Fax: +81-3-5209-6013 Email: japan@adlinktech.com

ADLINK Technology, Inc. (Korean Liaison Office)

Address: 昢殾柢昢爎割昢爎壟 1675-12 微汾瘶捒娯 8猻

Tel: +82-2-2057-0565 Fax: +82-2-2057-0563 Email: korea@adlinktech.com

ADLINK Technology Singapore Pte. Ltd.

Address: 84 Genting Lane #07-02A, Cityneon Design Centre,

Tel: +65-6844-2261 Fax: +65-6844-2263 Email: singapore@adlinktech.com

ADLINK Technology Singapore Pte. Ltd. (Indian Liaison Office)

Address: 1st Floor, #50-56 (Between 16th/17th Cross) Margosa Plaza,

Tel: +91-80-65605817, +91-80-42246107 Fax: +91-80-23464606 Email: india@adlinktech.com

⼲⬄ 374 ɛɳ 4F KANDA374 Bldg. 4F, 3-7-4 Kanda Kajicho, Chiyoda-ku, Tokyo 101-0045, Japan

8F Mointer B/D,1675-12, Seocho-Dong, Seocho-Gu, Seoul 137-070, Korea

Singapore 349584

Margosa Main Road, Malleswaram, Bangalore-560055, India

ADLINK Technology, Inc. (Israeli Liaison Office)

Address: 6 Hasadna St., Kfar Saba 44424, Israel Tel: +972-9-7446541 Fax: +972-9-7446542 Email: israel@adlinktech.com

32 Getting Service

ADLINK PXIe-9529 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

PXIe-9529

Revision History

Preface

Table of Contents

List of Figures

List of Tables

1 Introduction

1.1 Features

1.2 Applications

1.3 Specifications

1.3.1 Analog Input

1.3.2 Timebase

1.3.3 Triggers

1.3.4 General Specifications

1.4 Software Support

1.4.1 SDK

1.4.2 DSA-DASK

1.5 Device Layout and I/O Array

2 Getting Started

2.1 Installation Environment

2.2 Installing the Module

3 Operations

3.1 Functional Block Diagram

3.2 Analog Input Channel

3.2.1 Analog Input Front-End Configuration

3.2.2 Input Range and Data Format

3.2.3 ADC and Analog Input Filter

ADC (Analog-to-Digital Converter)

Filter

3.2.4 DMA Data Transfer

3.3 Trigger Source and Trigger Modes

3.4 Trigger Mode

3.5 ADC Timing Control

3.5.1 Timebase

3.5.2 DDS Timing vs. ADC

3.5.3 Filter Delay in ADC

3.6 Synchronizing Multiple Modules

3.6.1 SSI_TIMEBASE

3.6.2 SSI_SYNC_START

3.6.3 SSI_TRIG

Appendix A Calibration

A.1 Calibration Constant

A.2 Auto-Calibration

Important Safety Instructions

Getting Service