ADLINK PXI-2208 User Manual

DAQ-/DAQe-/PXI-

2204/2205/2206/2208

64-/96-CH High Performance

Multi-Function Data Acquisition Card

User’s Manual

Manual Rev. 2.01

Revision Date: December 04, 2007

Part No: 50-11220-2010

Advance Technologies; Automate the World.

Copyright 2007 ADLINK TECHNOLOGY INC.

All Rights Reserved.

The information in this document is subject to change without prior
notice in order to improve reliability, design, and function and does
not represent a commitment on the part of the manufacturer.

In no event will the manufacturer be liable for direct, indirect, spe­cial, incidental, or consequential damages arising out of the use or
inability to use the product or documentation, even if advised of
the possibility of such damages.

This document contains proprietary information protected by copy­right. All rights are reserved. No part of this manual may be repro­duced by any mechanical, electronic, or other means in any form
without prior written permission of the manufacturer.

Trademarks

Product names mentioned herein are used for identification pur­poses only and may be trademarks and/or registered trademarks
of their respective companies.

Getting service

Customer satisfaction is our top priority. Contact us should you
require any service or assistance.

ADLINK TECHNOLOGY INC.

Web Site http://www.adlinktech.com
Sales & Service [e-mail]
Telephone No. [phone]
Fax No. [phone]
Mailing Address 9F No. 166 Jian Yi Road, Chungho City,

Taipei Hsien 235, Taiwan, ROC

ADLINK TECHNOLOGY AMERICA, INC.

Sales & Service [e-mail]
Toll-Free +1-866-4-ADLINK (235465)
Fax No. [phone]
Mailing Address 8900 Research Drive, Irvine,

CA 92618, USA

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Sales & Service [e-mail]
Toll-Free [phone]
Fax No. [phone]
Mailing Address Nord Carree 3, 40477 Düsseldorf, Germany

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Sales & Service [e-mail]
Telephone No. [phone]
Fax No. [phone]
Mailing Address 84 Genting Lane #07-02A,

Cityneon Design Center, Singapore 349584

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(INDIA Liaison Office)

Sales & Service [e-mail]
Telephone No. [phone]
Fax No. [phone]
Mailing Address No. 1357, Ground Floor, “Anupama”,

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Sales & Service [e-mail]
Telephone No. [phone]
Fax No. [phone]
Mailing Address 4F, Kostech Building, 262-2,

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Sales & Service [e-mail]
Telephone No. [phone]
Fax No. [phone]
Mailing Address Room 801, Building E, Yingchuangdongli

Plaza, No.1 Shangdidonglu,
Haidian District, Beijing, China

ADLINK TECHNOLOGY (SHANGHAI) CO., LTD.

Sales & Service [e-mail]
Telephone No. [phone]
Fax No. [phone]
Mailing Address Floor 4, Bldg. 39, Caoheting Science and

Technology Park, No.333 Qinjiang Road,
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ADLINK TECHNOLOGY (SHENZEN) CO., LTD.

Sales & Service [e-mail]
Telephone No. [phone]
Fax No. [phone]
Mailing Address C Block, 2nd Floor, Building A1,

Cyber-tech Zone, Gaoxin Ave. 7.S,
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Guangdong Province, China

Using this manual

1.1 Audience and scope

This manual guides you when using ADLINK multi-function DAQ-/
DAQe-/PXI-2204/2205/2206/2208 card. The card’s hardware, sig­nal connections, and calibration information are provided for faster
application building. This manual is intended for computer pro­grammers and hardware engineers with advanced knowledge of
data acquisition and high-level programming.

1.2 How this manual is organized

This manual is organized as follows:

Chapter 1 Introduction: This chapter intoduces the DAQ-/
DAQe-/PXI-2204/2205/2206/2208 card including its features,
specifications and software support information.

Chapter 2 Installation: This chapter presents the card’s lay­out, package contents, and installation.

Chapter 3 Signal Connections: This part describes the DAQ­/DAQe-/PXI-2204/2205/2206/2208 card signal connections.

Chapter 4 Operation Theory: The operation theory of the
DAQ-/DAQe-/PXI-2204/2205/2206/2208 card functions includ­ing A/D conversion, D/A conversion, and programmable func­tion I/O are discussed in this chapter.

Chapter 5 Calibration: The chapter offers information on how
to calibrate the DAQ-/DAQe-/PXI-2204/2205/2206/2208 card
for accurate data acquisition and output.

Warranty Policy: This presents the ADLINK Warranty Policy
terms and coverages.

1.3 Conventions

Take note of the following conventions used throughout the man­ual to make sure that you perform certain tasks and instructions
properly.

NOTE Additional information, aids, and tips that help you per-

form particular tasks.

IMPORTANT Critical information and instructions that you MUST perform to

WARNING Information that prevents physical injury, data loss, mod-

complete a task.

ule damage, program corruption etc. when trying to com­plete a particular task.

Table of Contents

Table of Contents..................................................................... i

List of Tables.......................................................................... iii

List of Figures ........................................................................ iv

1 Introduction ........................................................................ 1

1.1 Features............................................................................... 2

1.2 Applications ......................................................................... 3

1.3 Specifications....................................................................... 3

1.4 Software Support ............................................................... 13

Programming Library .................................................... 13

DAQ-LVIEW PnP: LabVIEW Driver .............................. 14

D2K-OCX: ActiveX Controls ......................................... 14

2 Installation ........................................................................ 15

2.1 Contents of Package ......................................................... 15

2.2 Unpacking.......................................................................... 15

2.3 Card Layout ....................................................................... 17

DAQe-2204/2205/2206/2208 ........................................ 17

DAQ-2204/2205/2206/2208 .......................................... 18

PXI-2204/2205/2206/2208 ............................................ 18

2.4 PCI Configuration .............................................................. 19

Plug and Play ............................................................... 19

Configuration ................................................................ 19

Troubleshooting ............................................................ 19

3 Signal Connections.......................................................... 21

3.1 Connectors Pin Assignment .............................................. 21

CN1 Connector ............................................................. 22

CN2 Connector ............................................................. 24

SSI Connector .............................................................. 28

3.2 Analog Input Signal Connection ........................................ 29

Types of signal sources ................................................ 29

Input Configurations ...................................................... 29

Differential Input Mode .................................................. 31

4 Operation Theory ............................................................. 33

Table of Contents i

4.1 A/D Conversion.................................................................. 33

DAQ-/DAQe-/PXI-2204/2208 AI Data Format .............. 33

DAQ/DAQe/PXI-2005/2006/2016 AI Data Format ........ 36

Software Conversion with Polling Data

Transfer Acquisition Mode (Software Polling) .... 37

Programmable Scan Acquisition Mode ......................... 38

Specifying Channels, Gains, and Input

Configurations in the Channel Gain Queue ........ 40

Trigger Modes ............................................................... 42

Bus-mastering DMA Data Transfer ............................... 52

4.2 D/A Conversion.................................................................. 54

Software Update ........................................................... 55

Timed Waveform Generation ........................................ 56

Trigger Modes ............................................................... 58

4.3 Digital I/O ........................................................................... 64

4.4 General Purpose Timer/Counter Operation ....................... 64

The Basics of Timer/Counter Functions ....................... 65

General Purpose Timer/Counter modes ....................... 65

4.5 Trigger Sources ................................................................. 71

Software-Trigger ........................................................... 71

External Analog Trigger ................................................ 71

4.6 User-controllable Timing Signals ....................................... 77

DAQ timing signals ....................................................... 78

Auxiliary Function Inputs (AFI) ...................................... 80

System Synchronization Interface ................................ 82

5 Calibration ......................................................................... 85

5.1 Loading Calibration Constants........................................... 85

5.2 Auto-calibration .................................................................. 86

5.3 Saving Calibration Constants............................................. 86

Warranty Policy ..................................................................... 87

ii Table of Contents

List of Tables

Table 1-1: Programmabel Input Range ..................................... 4

Table 1-2: Bandwidth ................................................................. 5

Table 1-3: System Noise ........................................................... 6

Table 1-4: CMRR (DC to 60 Hz) ................................................ 6

Table 1-5: Settling Time to Full Scale Step ............................... 7

Table 3-1: CN1 Pin Assignment for

DAQ-/DAQe-/PXI-2204/2205/2206 ......................... 22

Table 3-2: CN1 Pin Assignment for DAQ-/DAQe-/PXI-2208 ... 23
Table 3-3: CN2 Pin Assignment for

DAQ-/DAQe-/PXI-2204/2205/2206 ......................... 24

Table 3-4: CN2 Pin Assignment for DAQ-/DAQe-/PXI-2208 ... 25

Table 3-5: CN1/CN2 Signal Description .................................. 26

Table 3-6: SSI Connector Pin Assignment .............................. 28

Table 3-7: SSI Connector Legend ........................................... 28

Table 4-1: Bipolar Analog Input Range and Output

Digital Code on DAQ/DAQe/PXI-2204/2208 .......... 35

Table 4-2: Unipolar Analog Input Range and Output

Digital Code on DAQ/DAQe/PXI-2204/2208 .......... 35

Table 4-3: Bipolar Analog Input Range and Output

Digital Code for DAQ/DAQe/PXI-2205/2206 .......... 36

Table 4-4: Unipolar Analog Input Range and Output

Digital Code for DAQ/DAQe/PXI-2205/2206 .......... 36

Table 4-5: Bipolar Output Code Table ..................................... 54

Table 4-6: Unipolar Output Code Table ................................... 55

Table 4-7: Analog Trigger SRC1 (EXTATRIG) Ideal

Transfer Characteristic ........................................... 72

Table 4-8: User-controllable Timing Signals and

Functionalities ......................................................... 78

Table 4-9: Auxiliary Function Input Signals and

Functionalities ......................................................... 80

Table 4-10: SSI Timing Signal and Functions ........................... 82

List of Tables iii

List of Figures

Figure 2-1: DAQe-2204/2205/2206/2208 Card Layout .............. 17

Figure 2-2: DAQ-2204/2205/2206/2208 Card Layout ................ 18

Figure 2-3: PXI-2204/2205/2206/2208 Card Layout .................. 18

Figure 3-1: Floating Source and RSE Input Connections .......... 30

Figure 3-2: Ground-referenced Sources and NRSE

nput Connections..................................................... 30

Figure 3-3: Ground-referenced Source and Differential Input.... 31

Figure 3-4: Floating Source and Differential Input ..................... 31

Figure 4-1: Synchronous Digital Inputs Block Diagram.............. 34

Figure 4-2: Synchronous Digital Inputs Timing .......................... 34

Figure 4-3: Scan Timing............................................................. 39

Figure 4-4: Pre-trigger (Trigger occurs after M scans) ............... 43

Figure 4-5: Pre-trigger (Trigger with scan in progress) .............. 44

Figure 4-6: Pre-trigger with M_enable=0 (Trigger occurs

before M scans) ....................................................... 45

Figure 4-7: Pre-trigger with M_enable=1 ................................... 46

Figure 4-8: Middle-Trigger with M_enable = 1 ........................... 47

Figure 4-9: Middle-Trigger (Trigger occurs when a

scan is in progress).................................................. 48

Figure 4-10: Post-trigger .............................................................. 49

Figure 4-11: Delay trigger ............................................................ 50

Figure 4-12: Post trigger with Re-trigger ...................................... 51

Figure 4-13: Scatter/gather DMA for Data Transfer ..................... 53

Figure 4-14: Typical D/A Timing of Waveform Generation .......... 57

Figure 4-15: Post Trigger Waveform Generation ......................... 58

Figure 4-16: Delay Trigger Waveform Generation ....................... 59

Figure 4-17: Re-triggered Waveform Generation with

Post-Trigger (DLY2_Counter=0).............................. 59

Figure 4-18: Finite Iterative Waveform Generation with

Post-trigger (DLY2_Counter = 0) ............................. 60

Figure 4-19: Infinite Iterative Waveform Generation with

Post-trigger (DLY2_Counter = 0) ............................. 61

Figure 4-20: Stop Mode I ............................................................. 62

Figure 4-21: Stop Mode II ............................................................ 63

Figure 4-22: Stop Mode III ........................................................... 63

Figure 4-23: Mode1 Operation ..................................................... 66

Figure 4-24: Mode2 Operation ..................................................... 67

Figure 4-25: Mode3 Operation ..................................................... 67

iv List of Figures

Figure 4-26: Mode4 Operation..................................................... 68

Figure 4-27: Mode5 Operation..................................................... 69

Figure 4-28: Mode6 Operation..................................................... 69

Figure 4-29: Mode7 Operation..................................................... 70

Figure 4-30: Mode8 Operation..................................................... 70

Figure 4-31: Analog Trigger Block Diagram................................. 72

Figure 4-32: Below-Low Analog Trigger Condition ...................... 73

Figure 4-33: Above-High Analog Trigger Condition ..................... 73

Figure 4-34: Inside-Region Analog Trigger Condition.................. 74

Figure 4-35: High-Hysteresis Analog Trigger Condition .............. 75

Figure 4-36: Low-Hysteresis Analog Trigger Condition ............... 75

Figure 4-37: External Digital Trigger ............................................ 76

Figure 4-38: DAQ signals routing................................................. 77

List of Figures v

vi List of Figures

1 Introduction

The DAQ-/DAQe-/PXI-2204/2205/2206/2208 card is an advanced
data acquisition card based on the 32-bit PCI or PCI Express
architecture. High performance designs and state-of-the-art tech­nology make these cards ideal for data logging and signal analysis
applications in medical, process control, etc.

®

Introduction 1

1.1 Features

The DAQ-/DAQe-/PXI-2204/2205/2206/2208 advanced data
acquisition card has the following features:

X 32-bit PCI bus (DAQ/PXI models) or PCI Express (DAQe

model), plug and play

X Up to 96 single-ended inputs or 48 differential inputs sup-

porting combinations of SE and DI analog input signals

X Up to 1024 words analog input Channel Gain Queue config-

uration size

X Analog input resolution and sampling rate:

Z DAQ-/DAQe-/PXI-2204/2208: 12-bit and up to 3 MHz

Z DAQ-/DAQe-/PXI-2205: 16-bit and up to 500 KHz

Z DAQ-/DAQe-/PXI-2206: 16-bit and up to 250 KHz

X Programmable bipolar/unipolar analog input

X Programmable gain:

Z DAQ-/DAQe-/PXI-2204/2208: x1, x2, x4, x5, x8, x10,

x20, x40, x50, x200

Z DAQ-/DAQe-/PXI-2205/2206: x1, x2, x4, x8

X A/D FIFO size: 1024 samples

X Versatile trigger sources: software trigger, external digital

trigger, analog trigger and trigger from System Synchroniza­tion Interface (SSI)

X A/D data transfer: software polling and bus-mastering DMA

with scatter/gather functionality

X Four A/D trigger modes including post-trigger, delay-trigger,

pre-trigger and middle-trigger

X Two-channel D/A outputs with waveform generation capa-

bility (except DAQ-/DAQe-/PXI-2208)

X 1024 word length output data FIFO for D/A channels

X D/A data transfer: Software update and bus-mastering DMA

with scatter/gather functionality

X Support System Synchronization Interface (SSI)

X Full A/D and D/A auto-calibration

X Jumper-free and software-configurable

2Introduction

1.2 Applications

X Automotive Testing

X Cable Testing

X Transient signal measurement

X ATE

X Laboratory Automation

X Biotech measurement

1.3 Specifications

Analog Input (AI)

X Programmable channels:

Z DAQ-/DAQe-/PXI-2204/2205/2206: 64 single-ended

(SE) or 32 differential input (DI)

Z DAQ-/DAQe-/PXI-2208: 96 single-ended (SE) or 48 dif-

ferential input (DI)

Z Mixing of SE and DI analog signal sources (Software

selectable per channel)

X A/D converter:

Z DAQ-/DAQe-/PXI-2204/2008: LT1412 or equivalent

Z DAQ-/DAQe-/PXI-2205: A/D7665 or equivalent

Z DAQ-/DAQe-/PXI-2206: A/D7663 or equivalent

X Max sampling rate:

Z DAQ-/DAQe-/PXI-2204/2008: 3 MS/s (single-channel)

1 MS/s (multi-channel)

Z DAQ-/DAQe-/PXI-2205: 500 kS/s

Z DAQ-/DAQe-/PXI-2206: 250 kS/s

X Resolution:

Z DAQ-/DAQe-/PXI-2204/2208: 12-bit, no missing code

Z DAQ-/DAQe-/PXI-2205/2206: 16-bit, no missing code

X Input coupling: DC

X FIFO buffer size:

Z DAQ-/DAQe-/PXI-2010: 8K samples

Z DAQ-/DAQe-/PXI-2005/2006/2016: 512 samples

Introduction 3

X Programmable input range:

Device Bipolar input range Unipolar input range

±10 V —

±5 V 0 to 10 V

±2.5 V 0 to 5 V

±2 V 0 to 4 V

2204/

2208

±1.25 V 0 to 2.5 V

±1 V 0 to 2 V

±0.5 V 0 to 1 V

±0.25 V 0 to 0.5 V

±0.2 V 0 to 0.4 V

±0.05 V 0 to 0.1 V

±10 V 0 to 10 V

2205/

2206

±5 V 0 to 5 V

±2.5 V 0 to 2.5 V

±1.25 V 0 to 1.25 V

Table 1-1: Programmabel Input Range

X Operational common mode voltage range: ±11V

X Over-voltage protection:

Z Power on: Continuous ±30V

Z Power off: Continuous ±15V

X FIFO buffer size: 1024 samples

X Data transfers:

Z Programmed I/O

Z Bus-mastering DMA with scatter/gather

X Channel Gain Queue configuration size:

Z DAQ-/DAQe-/PXI-2204/2205/2206: 512 words

Z DAQ-/DAQe-/PXI-2208: 1024 words

4Introduction

X Bandwidth (Typical 25ºC):

Device Input range

±10 V —

±5 V 0 V to 10 V

±2.5 V 0 V to 5 V

±1.25 V 0 V to 2.5 V

2204/

2208

±2 V 0 V to 4 V

±0.5 V 0 V to 1 V

±1 V 0 V to 2 V

±0.25 V 0 V to 0.5 V

±0.2 V 0 V to 0.4 V

±0.05 V 0 V to 0.1 V

±10 V 0 V to 0 V 1600 kHz 300 kHz

2205

±5 V 0 V to 5 V 1400 kHz 310 kHz

±2.5 V 0 V to 2.5 V 1000 kHz 310 kHz

±1.25 V 0 V to 1.25 V 600 kHz 330 kHz

±10 V 0 V to 10 V 760 kHz 300 kHz

2206

±5 V 0 V to 5 V 720 kHz 310 kHz

±2.5 V 0 V to 2.5 V 610 kHz 310 kHz

±1.25 V 0 V to 1.25 V 450 kHz 330 kHz

Table 1-2: Bandwidth

Small signal

bandwidth

(-3dB)

Large signal

bandwidth

(1% THD)

2000 kHz —

1450 kHz —

990 kHz —

240 kHz —

Introduction 5

X System Noise (LSBrms, including Quantization, Typical,

25°C)

Device Input Range

System

Noise

Input Range

System

Noise

±10 V 0.95 LSBrms 0 V to 10 V 1.5 LSBrms

2205

±5 V 1.0 LSBrms 0 V to 5 V 1.6 LSBrms

±2.5 V 1.1 LSBrms 0 V to 2.5 V 1.7 LSBrms

±1.25 V 1.3 LSBrms 0 V to 1.25 V 1.9 LSBrms

±10 V 0.8 LSBrms 0 V to 10 V 0.9 LSBrms

2206

±5 V 0.85 LSBrms 0 V to 5 V 1.0 LSBrms

±2.5 V 0.85 LSBrms 0 V to 2.5 V 1.0 LSBrms

±1.25 V 0.9 LSBrms 0 V to 1.25 V 1.2 LSBrms

Table 1-3: System Noise

X Input impedance:

Z Normal power on: 1 GΩ/100 pF

Z Power off: 820 Ω

Z Overload: 820 Ω

X CMRR (DC to 60 Hz, Typical)

Device Input Range CMRR Input Range CMRR

2204/2208 All ranges 90 dB — —

±10 V 83 dB 0 V to 10 V 87 dB

2205/2206

±5 V 87 dB 0 V to 5 V 90 dB

±2.5 V 90 dB 0 V to 2.5 V 92 dB

±1.25 V 92 dB 0 V to 1.25 V 93 dB

Table 1-4: CMRR (DC to 60 Hz)

6Introduction

X Settling time to full-scale step (Typical, 25°C):

Device Input Range Condition Settling time

±10 V • Multiple channels,

±5 V 0 to 10 V

±2.5 V 0 to 5 V

±2 V 0 to 4 V

multiple ranges.

• All samples in unipolar/
bipolar mode.

1 µs to 0.1% error

±1.25 V 0 to 2.5 V

±0.5 V 0 to 1 V

±10 V • Multiple channels,

multiple ranges.

• All samples in unipolar/
bipolar mode.

1.25 µs to 0.1%
error

2204/

2208

±5 V 0 to 10 V

±2.5 V 0 to 5 V

v2 V 0 to 4 V

±1.25 V 0 to 2.5 V

±0.5 V 0 to 1 V

±1 V 0 to 2 V

±0.25 V 0 to 0.5 V

±0.2 V 0 to 0.4 V

±0.05 V 0 to 0.1 V

• Multiple channels,
multiple ranges.

• All samples in unipolar/
bipolar mode.

• Multiple channels,
multiple ranges.

• All samples in unipolar/
bipolar mode.

2 µs to 0.1% error

5 µs to 0.1% error

• Multiple channels,

2205/

2206

All Ranges

All Ranges

multiple ranges.

• All samples in unipolar/
bipolar mode.

• Multiple channels,
multiple ranges.

• All samples in unipolar/

2 µs to 0.1% error,

4 µs to 0.01% error

2 µs to 0.2% error,

4 µs to 0.01% error

bipolar mode.

Table 1-5: Settling Time to Full Scale Step

Introduction 7

X Time-base source:

Z Internal 40 MHz or external clock Input (f

f

: 1 MHz, 50% duty cycle)

min

X Trigger modes: Post-trigger, delay-trigger, pre-trigger and

: 40 MHz,

max

middle-trigger

X Offset error:

Z Before calibration: ±60 mV max

Z After calibration: ±1 mV max

X Gain error (relative to calibration reference):

Z Before calibration: 0.6% of reading

Z After calibration (gain = 1):

0.03% of reading max for DAQ-/DAQe-/PXI-2204/2208

0.01% of reading max for DAQ-/DAQe-/PXI-2205/2206

Z Gain 1 with gain error adjusted to 0 at gain=1:

0.05% of reading max

8Introduction

Analog Output (AO)

NOTE The DAQ-/DAQe-/PXI-2208 card does not support this

function.

X Channels: Two-channel analog voltage output
X DA converter: LTC7545 or equivalent
X Max update rate: 1 MS/s
X Resolution: 12-bit
X FIFO buffer size:

Z 512 samples per channel when both channels are

enabled for timed DA output

Z 1024 samples when only one channel is used for timed

DA output

X Data transfers:

Z Programmed I/O
Z Bus-mastering DMA with scatter/gather

X Output range: ±10 V, 0 V to 10 V, ±AOEXTREF, 0 to AOEX-

TREF

X Settling time: 3 S to 0.5 LSB accuracy
X Slew rate: 20 V/µS
X Output coupling: DC
X Protection: Short-circuit to ground
X Output impedance: 0.01Ω typical
X Output driving current: ±5 mA max
X Stability: Any passive load, up to 1500 pF
X Power-on state: 0V steady-state
X Power-on glitch: ±1.5 V/500 µS
X Relative accuracy: ±0.5 LSB typical, ±1 LSB max
X DNL: ±0.5 LSB typical, ±1.2 LSB max
X Offset error:

Z Before calibration: ±80 mV max
Z After calibration: ±1 mV max

X Gain error:

Z Before calibration: ±0.8% of output max
Z After calibration: ±0.02% of output max

Introduction 9

General Purpose Digital I/O (G.P. DIO, 82C55A)

X Channels: 24 programmable input/output

X Compatibility: TTL

X Input voltage:

Z Logic Low: VIL=0.8 V max; IIL=0.2 mA max

Z High: VIH=2.0 V max; IIH=0.02 mA max

X Output voltage:

Z Low: VOL=0.5 V max; IOL=8 mA max

Z High: VOH=2.7 V min; IOH=400 µA

X Synchronous Digital Inputs (SDI): On DAQ-/DAQe-/PXI-

2204 model only.

Z Channels: 8 digital inputs sampled simultaneously with

the analog signal input

Z Compatibility: TTL/CMOS

Z Input voltage:

Logic Low: VIL=0.8 V max; IIL=0.2mA max

Logic High: VIH=2.7 V min; IIL=0.02mA max

General Purpose Timer/Counter (GPTC)

NOTE The DAQ-/DAQe-/PXI-2208 does not support this func-

tion.

X Channels: 2 independent up/down timer/counters

X Resolution: 16-bit

X Compatibility: TTL

X Clock source: Internal or external

X Max source frequency: 10 MHz

10 Introduction

Analog Trigger (A.Trig)

X Source:

Z All analog input channels

Z External analog trigger (EXTATRIG)

X Level: ±Full-scale, internal; ±10 V external

X Resolution: 8-bit

X Slope: Positive or negative (software-selectable)

X Hysteresis: Programmable

X Bandwidth: 400 kHz

External Analog Trigger Input (EXTATRIG)

X Input Impedance:

Z 40 kΩ for DAQ-/DAQe-/PXI-2204/2208

Z 20 kΩ for DAQ-/DAQe-/PXI-2205/2206

X Coupling: DC

X Protection: Continuous ±35 V maximum

Digital Trigger (D.Trig)

X Compatibility: TTL/CMOS

X Response: Rising or falling edge

X Pulse Width: 10 ns min

System Synchronous Interface (SSI)

X Trigger lines: 7

Stability

X Recommended warm-up time: 15 minutes

X On-board calibration reference:

Z Level: 5.000 V

Z Temperature coefficient: ±2 ppm/°C

Z Long-term stability: 6 ppm/1000 Hr

Introduction 11

Physical

X Dimensions:

Z 175mm by 107mm for DAQ-/DAQe-2204/2205/2206/

2208

Z Standard CompactPCI form factor for PXI-2204/2205/

2206/2208

X I/O connector: 68-pin female VHDCI type (e.g. AMP-

787254-1)

Power Requirement (typical)

X +5 VDC

Z 1.3 A for DAQ-/DAQe-/PXI-2204

Z 1.2 A for DAQ-/DAQe-/PXI-2205/2206

Z 950 mA for DAQ-/DAQe-/PXI-2208

X +12 VDC

Z 358 mA for DAQe-2204

Z 344 mA for DAQe-2205

Z 390 mA for DAQe-2206

Z 258 mA for DAQe-2208

X +3.3 VDC

Z 815 mA for DAQe-2204

Z 735 mA for DAQe-2205

Z 710 mA for DAQe-2206

Z 815 mA for DAQe-2208

Operating Environment

X Ambient temperature: 0°C to 55°C

X Relative humidity: 10% to 90% non-condensing

Storage Environment

X Ambient temperature: -20°C to 80°C

X Relative humidity: 5% to 95% non-condensing

12 Introduction

1.4 Software Support

ADLINK provides versatile software drivers and packages for
users’ different approach to building up a system. ADLINK not only
provides programming libraries such as DLL for most Windows­based systems, but also provide drivers for other software pack­ages such as LabVIEW

All software options are included in the ADLINK CD. Non-free soft­ware drivers are protected with licensing codes. Without the soft­ware code, you can install and run the demo version for two hours
for trial/demonstration purposes. Contact ADLINK dealers to pur­chase the software license.

Programming Library

For customers who are writing their own programs, we provide
function libraries for many different operating systems, including:

X D2K-DASK: Include device drivers and DLL for Windows

98/NT/2000/XP. DLL is binary compatible across Windows
98/NT/2000/XP. This means all applications developed with
D2K-DASK are compatible across Windows 98/NT/2000/
XP. The developing environment can be VB, VC++, Delphi,
BC5, or any Windows programming language that allows
calls to a DLL. The user’s guide and function reference
manual of D2K-DASK are in the CD. (\\Manual\Software
Package\D2K-DASK)

X D2K-DASK/X: Include device drivers and shared library for

Linux. The developing environment can be Gnu C/C++ or
any programming language that allows linking to a shared
library. The user's guide and function reference manual of
D2K-DASK/X are in the CD. (\\Manual\Software Pack­age\D2K-DASK-X.)

®

.

®

Introduction 13

DAQ-LVIEW PnP: LabVIEW Driver

DAQ-LVIEW PnP contains the VIs, which are used to interface
with NI’s LabVIEW software package. The DAQ-LVIEW PnP sup­ports Windows 98/NT/2000/XP. The LabVIEW drivers is shipped
free with the card. You can install and use them without a license.
For detailed information about DAQ-LVIEW PnP, refer to the
user’s guide in the CD. (\\Manual\Software Package\DAQ-LVIEW
PnP)

D2K-OCX: ActiveX Controls

Customers who are familiar with ActiveX controls and VB/VC++
programming are suggested to use D2K-OCX ActiveX control
component libraries for developing applications. D2K-OCX is
designed for Windows 98/NT/2000/XP. For more details on D2K­OCX, refer to the user's guide in the CD. (\\Manual\Software Pack­age\D2K-OCX)

The above software drivers are shipped with the card. Refer to the
Software Installation Guide in the package to install these drivers.

In addition, ADLINK provides the DAQBench ActiveX control soft­ware. DAQBench is a collection of ActiveX controls for measure­ment or automation applications. With DAQBench, you can easily
develop custom user interfaces to display your data, analyze data
you acquired or received from other sources, or integrate with
popular applications or other data sources. For more detailed
information about DAQBench, refer to the user's guide in the CD.
(\\Manual\Software Package\DAQBench Evaluation)

You can also get a free 4-hour evaluation version of DAQBench
from the CD. DAQBench is not free. Contact ADLINK or your
dealer to purchase the software license.

14 Introduction

2 Installation

This chapter describes how to install the DAQ-/DAQe-/PXI-2204/
2205/2206/2208 card. The contents of the package and unpacking
information that you should be aware of are outlined first.

The DAQ-/DAQe-/PXI-2204/2205/2206/2208 card performs an
automatic configuration of the IRQ and port address. You can use
the PCI_SCAN software utility to read the system configuration.

2.1 Contents of Package

In addition to this User's Manual, the package includes the follow­ing items:

X DAQ-/DAQe-/PXI-2016/2010/2006/2005 multi-function data

acquisition card

X ADLINK All-in-one CD

X Software Installation Guide

If any of these items are missing or damaged, contact the dealer
from whom you purchased the product. Save the shipping materi­als and carton in case you want to ship or store the product in the
future.

2.2 Unpacking

Your DAQ-/DAQe-/PXI-2204/2205/2206/2208 card contains elec­tro-static sensitive components that can be easily be damaged by
static electricity.

Therefore, the card should be handled on a grounded anti-static
mat. The operator should be wearing an anti-static wristband,
grounded at the same point as the anti-static mat.

Inspect the card package for obvious damages. Shipping and han­dling may cause damage to the card. Be sure there are no ship­ping and handling damages on the modules carton before
continuing.

After opening the card module carton, extract the system module
and place it only on a grounded anti-static surface with component
side up.

Installation 15

Again, inspect the module for damages. Press down on all the
socketed IC's to make sure that they are properly seated. Do this
only with the module place on a firm flat surface.

You are now ready to install your DAQ-/DAQe-/PXI-2204/2205/
2206/2208 card.

NOTE DO NOT APPLY POWER TO THE CARD IF IT HAS

BEEN DAMAGED.

16 Installation

2.3 Card Layout

DAQe-2204/2205/2206/2208

Figure 2-1: DAQe-2204/2205/2206/2208 Card Layout

Installation 17

DAQ-2204/2205/2206/2208

Figure 2-2: DAQ-2204/2205/2206/2208 Card Layout

PXI-2204/2205/2206/2208

Figure 2-3: PXI-2204/2205/2206/2208 Card Layout

18 Installation

2.4 PCI Configuration

Plug and Play

With support for plug and play, the card requests an interrupt num­ber via its PCI controller. The system BIOS responds with an inter­rupt assignment based on the card information and on known
system parameters. These system parameters are determined by
the installed drivers and the hardware load seen by the system.

Configuration

The board configuration is done on a board-by-board basis for all
PCI boards in the system. Because configuration is controlled by
the system and software, there is no jumper setting required for
base address, DMA, and interrupt IRQ.

The configuration is subject to change with every boot of the sys­tem as new boards are added or removed.

Troubleshooting

If your system doesn’t boot or if you experience erratic operation
with your PCI board in place, it is likely caused by an interrupt con­flict. The BIOS Setup may be incorrectly configured. Consult the
BIOS documentation that comes with your system to solve this
problem.

Installation 19

20 Installation

3 Signal Connections

This chapter describes DAQ-/DAQe-/PXI-2204/2205/2206/2208
card connectors and the signal connection between the DAQ-/
DAQe-/PXI-2204/2205/2206/2208 card and external devices.

3.1 Connectors Pin Assignment

The DAQ-/DAQe-/PXI-2204/2205/2206/2208 card is equipped
with two 68-pin VHDCI-type connector (AMP-787254-1). It is used
for digital input/output, analog input/output, timer/counter signals,
etc. One 20-pin ribbon male connector is used for SSI (System
Synchronous Interface) in DAQ-/DAQe-2204/2205/2206/2208
card. The pin assignments of the connectors are defined in
Table 3-1, Table 3-2, Table 3-3, and Table 3-4.

Signal Connections 21

CN1 Connector

AI0 (AIH0) 135 (AIL0) AI32
AI1 (AIH1) 236 (AIL1) AI33
AI2 (AIH2) 337 (AIL2) AI34
AI3 (AIH3) 438 (AIL3) AI35
AI4 (AIH4) 539 (AIL4) AI36
AI5 (AIH5) 640 (AIL5) AI37
AI6 (AIH6) 741 (AIL6) AI38
AI7 (AIH7) 842 (AIL7) AI39
AI8 (AIH8) 943 (AIL8) AI40
AI9 (AIH9) 10 44 (AIL9) AI41

AI10 (AIH10) 11 45 (AIL10) AI42

AI11 (AIH11) 12 46 (AIL11) AI43
AI12 (AIH12) 13 47 (AIL12) AI44
AI13 (AIH13) 14 48 (AIL13) AI45
AI14 (AIH14) 15 49 (AIL14) AI46
AI15 (AIH15) 16 50 (AIL15) AI47

AISENSE 17 51 AIGND
AI16 (AIH16) 18 52 (AIL16) AI48
AI17 (AIH17) 19 53 (AIL17) AI49
AI18 (AIH18) 20 54 (AIL18) AI50
AI19 (AIH19) 21 55 (AIL19) AI51
AI20 (AIH20) 22 56 (AIL20) AI52
AI21 (AIH21) 23 57 (AIL21) AI53
AI22 (AIH22) 24 58 (AIL22) AI54
AI23 (AIH23) 25 59 (AIL23) AI55
AI24 (AIH24) 26 60 (AIL24) AI56
AI25 (AIH25) 27 61 (AIL25) AI57
AI26 (AIH26) 28 62 (AIL26) AI58
AI27 (AIH27) 29 63 (AIL27) AI59
AI28 (AIH28) 30 64 (AIL28) AI60
AI29 (AIH29) 31 65 (AIL29) AI61
AI30 (AIH30) 32 66 (AIL30) AI62
AI31 (AIH31) 33 67 (AIL31) AI63

EXTATRIG 34 68

Table 3-1: CN1 Pin Assignment for DAQ-/DAQe-/PXI-2204/2205/2206

AIGND

* Symbols in “()” are for differential mode connection.

22 Signal Connections

AI0 (AIH0) 1 35 (AIL0) AI48
AI1 (AIH1) 2 36 (AIL1) AI49
AI2 (AIH2) 3 37 (AIL2) AI50
AI3 (AIH3) 4 38 (AIL3) AI51
AI4 (AIH4) 5 39 (AIL4) AI52
AI5 (AIH5) 6 40 (AIL5) AI53
AI6 (AIH6) 7 41 (AIL6) AI54
AI7 (AIH7) 8 42 (AIL7) AI55

AISENSE 9 43 AIGND
AI8 (AIH8) 10 44 (AIL8) AI56
AI9 (AIH9) 11 45 (AIL9) AI57

AI10 (AIH10) 12 46 (AIL10) AI58

AI11 (AIH11) 13 47 (AIL11) AI59
AI12 (AIH12) 14 48 (AIL12) AI60
AI13 (AIH13) 15 49 (AIL13) AI61
AI14 (AIH14) 16 50 (AIL14) AI62
AI15 (AIH15) 17 51 (AIL15) AI63
AI16 (AIH16) 18 52 (AIL16) AI64
AI17 (AIH17) 19 53 (AIL17) AI65
AI18 (AIH18) 20 54 (AIL18) AI66
AI19 (AIH19) 21 55 (AIL19) AI67
AI20 (AIH20) 22 56 (AIL20) AI68
AI21 (AIH21) 23 57 (AIL21) AI69
AI22 (AIH22) 24 58 (AIL22) AI70
AI23 (AIH23) 25 59 (AIL23) AI71

AIGND 26 60 AIGND
AI24 (AIH24) 27 61 (AIL24) AI72
AI25 (AIH25) 28 62 (AIL25) AI73
AI26 (AIH26) 29 63 (AIL26) AI74
AI27 (AIH27) 30 64 (AIL27) AI75
AI28 (AIH28) 31 65 (AIL28) AI76
AI29 (AIH29) 32 66 (AIL29) AI77
AI30 (AIH30) 33 67 (AIL30) AI78
AI31 (AIH31) 34 68 (AIL31) AI79

Table 3-2: CN1 Pin Assignment for DAQ-/DAQe-/PXI-2208

* Symbols in “()” are for differential mode connection.

Signal Connections 23

CN2 Connector

DA0OUT 1 35 AOGND
DA1OUT 2 36 AOGND

AOEXTREF 3 37 AOGND

NC 4 38 NC

DGND 5 39 DGND

EXTWFTRIG 6 40 DGND

EXTDTRIG 7 41 DGND

SSHOUT 8 42 SDI0 / DGND*

RESERVED 9 43 SDI1 / DGND*
RESERVED 10 44 SDI2 / DGND*

AFI1 11 45 SDI3 / DGND*
AFI0 12 46 DGND

GPTC0_SRC 13 47 DGND

GPTC0_GATE 14 48 DGND

GPTC0_UPDOWN 15 49 DGND

GPTC0_OUT 16 50 DGND
GPTC1_SRC 17 51 DGND

GPTC1_GATE 18 52 DGND

GPTC1_UPDOWN 19 53 DGND

GPTC1_OUT 20 54 DGND

EXTTIMEBASE 21 55 DGND

PB7 22 56 PB6
PB5 23 57 PB4
PB3 24 58 PB2
PB1 25 59 PB0
PC726 60 PC6
PC527 61 PC4

DGND 28 62 DGND

PC329 63 PC2
PC130 64 PC0
PA731 65 PA6
PA532 66 PA4
PA333 67 PA2
PA134 68 PA0

Table 3-3: CN2 Pin Assignment for DAQ-/DAQe-/PXI-2204/2205/2206

*Pin 42~45 are SDI<0.3> for DAQ-/DAQe-/PXI-2204; DGND for DAQ-/DAQe-/PXI-

2205/2206

24 Signal Connections

AI32 (AIH32) 1 35 (AIL32) AI80
AI33 (AIH33) 2 36 (AIL33) AI81
AI34 (AIH34) 3 37 (AIL34) AI82
AI35 (AIH35) 4 38 (AIL35) AI83
AI36 (AIH36) 5 39 (AIL36) AI84
AI37 (AIH37) 6 40 (AIL37) AI85
AI38 (AIH38) 7 41 (AIL38) AI86
AI39 (AIH39) 8 42 (AIL39) AI87

EXTATRIG 9 43 AIGND
AI40 (AIH40) 10 44 (AIL40) AI88
AI41 (AIH41) 11 45 (AIL41) AI89
AI42 (AIH42) 12 46 (AIL42) AI90
AI43 (AIH43) 13 47 (AIL43) AI91
AI44 (AIH44) 14 48 (AIL44) AI92
AI45 (AIH45) 15 49 (AIL45) AI93
AI46 (AIH46) 16 50 (AIL46) AI94
AI47 (AIH47) 17 51 (AIL47) AI95

AIGND 18 52 AIGND

NC 19 53 NC

EXTDTRIG 20 54 AFI0

EXTTIMEBASE 21 55 DGND

PB7 22 56 PB6
PB5 23 57 PB4
PB3 24 58 PB2

PB1 25 59 PB0
PC726 60 PC6
PC527 61 PC4

DGND 28 62 DGND

PC329 63 PC2
PC130 64 PC0

PA731 65 PA6

PA532 66 PA4

PA333 67 PA2

PA134 68 PA0

Table 3-4: CN2 Pin Assignment for DAQ-/DAQe-/PXI-2208

Signal Connections 25

CN1/CN2 Connector Signal Description

Signal Name Reference Direction Description

Analog ground for AI. All three

AIGND — —

AI<0..63/95> AIGND Input

AISENSE AIGND Input

EXTATRIG AIGND Input External AI analog trigger

DA0OUT AOGND Output AO channel 0

DA1OUT AOGND Output AO channel 1

AOEXTREF AOGND Input

AOGND — — Analog ground for AO

EXTWFTRIG DGND Input External AO waveform trigger

EXTDTRIG DGND Input External AI digital trigger

RESERVED — Output Reserved. Please leave it open

Table 3-5: CN1/CN2 Signal Description

ground references (AIGND,
AOGND, and DGND) are
connected together on board.

• For DAQ-/DAQe-/PXI-2204/
2205/2206: Analog Input
Channels 0~63. Each channel
pair, AI<i, i+32> (I=0..31) can
be configured either two single­ended inputs or one differential
input pair(marked as
AIH<0..31> and AIL<0..31>).

• For DAQ-/DAQe-/PXI-2208:
Analog Input Channels 0~95.
Each channel pair, AI<i, i+48>
(I=0..37) can be configured
either two single-ended inputs
or one differential input
pair(marked as AIH<0..47> and
AIL<0..47>).

Analog Input Sense. This pin is
the reference for any channels
AI<0..63> in NRSE input
configuration.

External reference for AO
channels

26 Signal Connections

Signal Name Reference Direction Description

Synchronous digital inputs. These

SDI<0..3>

(for 2204 only)

GPTC<0,1>_SRC DGND Input Source of GPTC<0,1>

GPTC<0,1>_GATE DGND Input Gate of GPTC<0,1>

GPTC<0,1>_OUT DGND Input Output of GPTC<0,1>

GPTC<0,1>_UPDOWN DGND Input Up/Down of GPTC<0,1>

EXTTIMEBASE DGND Input External Timebase

DGND — — Digital ground

PB<7,0> DGND PIO* Programmable DIO of 8255 Port B

PC<7,0> DGND PIO* Programmable DIO of 8255 Port C

PA<7,0> DGND PIO* Programmable DIO of 8255 Port A

AFI0 DGND Input

AFI1 DGND Input

DGND Input

Table 3-5: CN1/CN2 Signal Description

4 digital inputs are sampled
simultaneously with the analog
signal input.

Auxiliary Function Input 0
(ADCONV, AD_START)

Auxiliary Function Input 1 (DAWR,
DA_START)

Signal Connections 27

SSI Connector

SSI_TIMEBASE 1 2 DGND

SSI_ADCONV 3 4 DGND

SSI_DAWR / RESERVED* 5 6 DGND

SSI_SCAN_START 7 8 DGND

RESERVED 9 10 DGND

SSI_AD_TRIG 11 12 DGND

SSI_DA_TRIG / RESERVED* 13 14 DGND

RESERVED 15 16 DGND

RESERVED 17 18 DGND

RESERVED 19 20 DGND

Table 3-6: SSI Connector Pin Assignment

*Pin 5 and 13 are reserved for DAQ/PXI-2208.

SSI Connector Signal Description:

SSI Timing Signal Setting Function

Master Send the TIMEBASE out

SSI_TIMEBASE

SSI_ADCONV

SSI_SCAN_START

SSI_AD_TRIG

SSI_DAWR

SSI_DA_TRIG

Slave

Master Send the ADCONV out

Slave

Master Send the SCAN_START out

Slave

Master Send the internal AD_TRIG out

Slave Accept the SSI_AD_TRIG as the digital trigger signal.

Master Send the DAWR out.

Slave

Master Send the DA_TRIG out.

Slave Accept the SSI_DA_TRIG as the digital trigger signal.

Accept the SSI_TIMEBASE to replace the internal
TIMEBASE signal.

Accept the SSI_ADCONV to replace the internal
ADCONV signal.

Accept the SSI_SCAN_START to replace the internal
SCAN_START signal.

Accept the SSI_DAWR to replace the internal DAWR
signal.

Table 3-7: SSI Connector Legend

28 Signal Connections

3.2 Analog Input Signal Connection

The DAQ-/DAQe-/PXI-2204/2205/2206/2208 card provides up to
64 single-ended or 32 differential analog input channels. You can
fill the Channel Gain Queue to get desired combination of the input
signal types. The analog signal can be converted to digital values
by the A/D converter. To avoid ground loops and get more accu­rate measurements from the A/D conversion, it is important to
understand the signal source type and how to connect the analog
input signals.

Types of signal sources

Floating Signal Sources

A floating signal source means it is not connected in any way to
the buildings ground system. A device with an isolated output is
a floating signal source, such as optical isolator outputs, trans­former outputs, and thermocouples.

Ground-Referenced Signal Sources

A ground-referenced signal means it is connected in some way
to the building system. That is, the signal source is already
connected to a common ground point with respect to the DAQ­/DAQe-/PXI-2204/2205/2206/2208 card, assuming that the
computer is plugged into the same power system. Non-isolated
out-puts of instruments and devices that plug into the buildings
power system are ground-referenced signal sources.

Input Configurations

Single-Ended Connections

A single-ended connection is used when the analog input sig­nal is referenced to a ground that can be shared with other
analog input signals. There are two types of single-ended con­nections: RSE and NRSE. In RSE configuration, the DAQ-/
DAQe-/PXI-2204/2205/2206/2208 card provides the ground­ing point for the external analog input signals and is suitable for
floating signal sources. In the NRSE configuration the board
does not provide the grounding point, the external analog input
signal provides its own reference grounding point and is suit­able for ground-referenced signals.

Signal Connections 29

Referenced Single-ended (RSE) Mode

A

A

A

A

A

A

In referenced single-ended mode, all input signals are con­nected to the ground provided by the DAQ-/DAQe-/PXI-2204/
2205/2206/2208 card. This is suitable for connections with
floating signal sources. Figure 3-1 shows an illustration. Note
that when more than two floating sources are connected, these
sources will be referenced to the same common ground.

CN1

Input Multipexer

In

Instrumentation

mplifier

Floating
Signal
Source

V1

n = 0, ...,63

V2

IGND

-

To A /D
Converter

-

Figure 3-1: Floating Source and RSE Input Connections

Non-Referenced Single-ended (NRSE) Mode

To measure ground-referenced signal sources, which are con­nected to the same ground point, you can connect the signals
in NRSE mode. Figure 3-2 illustrates the connection. The sig­nals local ground reference is connected to the negative input
of the instrumentation Amplifier (AISENSE pin on CN1 connec­tor), and the common-mode ground potential between signal
ground and the ground on board will be rejected by the instru­mentation amplifier.

Input Multipexer

Instrumentation

mplifier

-

To A / D

-

Converter

Ground­Referenced
Signal Source

Common­mode noise &
Ground
potential

V1

V

V2

n = 0, ...,63

cm

In

ISENSE

Figure 3-2: Ground-referenced Sources and NRSE Input Connections

30 Signal Connections

Differential Input Mode

A

A

x

A

A

A

A

x

A

A

The differential input mode provides two inputs that respond to
signal voltage difference between them. If the signal source is
ground-referenced, the differential mode can be used for the com­mon-mode noise rejection. Figure 3-3 shows the connection of
ground-referenced signal sources under differential input mode.

Ground
Referenced
Signal
Source

Common­mode noise &
Ground
potential

V

= 0, ..., 31

cm

IxH

IxL

Input Multipexer

+

-

IGND

Instrumentation

mplifier

To A / D
Converter

-

Figure 3-3: Ground-referenced Source and Differential Input

Ground-referenced Source and Differential Input

Figure 3-4 shows how to connect a floating signal source to the
DAQ-/DAQe-/PXI-2204/2205/2206/2208 card in differential
input mode. For floating signal sources, you need to add a
resistor at each channel to provide a bias return path. The
resistor value should be about 100 times the equivalent source
impedance. If the source impedance is less than 100ohms, you
can simply connect the negative side of the signal to AIGND as
well as the negative input of the Instrumentation Amplifier with­out any resistors. In differential input mode, less noise couples
into the signal connections than in single-ended mode.

IxH

IxL

Input Multipexer

+

-

Instrumentation

mplifier

To A / D
Converter

-

= 0, ..., 31

Ground
Referenced
Signal
Source

IGND

Figure 3-4: Floating Source and Differential Input

Signal Connections 31

32 Signal Connections

4 Operation Theory

The operation theory of the DAQ-/DAQe-/PXI-2204/2205/2206/
2208 card functions are described in this chapter. The functions
include the A/D conversion, D/A conversion, digital I/O, and gen­eral purpose counter/timer. The operation theory can help you
understand how to configure and program the DAQ-/DAQe-/PXI­2204/2205/2206/2208 card.

4.1 A/D Conversion

When using an A/D converter, you must know about the properties
of the signal to be measured. You may decide which channel to
use and how to connect the signals to the card. In addition, users
should define and control the A/D signal configurations, including
channels, gains, and polarities (unipolar/bipolar).

The A/D acquisition is initiated by a trigger source and you must
decide how to trigger the A/D conversion. The data acquisition will
start once a trigger condition is matched.

After the end of an A/D conversion, the A/D data is buffered in a
Data FIFO. The A/D data can now be transferred into the system
memory for further processing.

DAQ-/DAQe-/PXI-2204/2208 AI Data Format

Synchronous Digital Inputs (DAQ-/DAQe-/PXI-2204 only)

When each A/D conversion is completed, the 14-bits converted
digital data accompanied with 2 bits of SDI<1..0>_X per chan­nel from J5 will be latched into the 16-bit register and data
FIFO as shown in Figure 4-1 and Figure 4-2. Therefore, you
can simultaneously sample one analog signal with four digital
signals. The data format of every acquired 16-bit data is as fol­lows:

D11, D10, D9 ....... D1, D0, b3, b2, b1, b0

Where

D11, D10, D9 ....... D1, D0: 2’s complement A/D

12-bit data

b3, b2, b1, b0: Synchronous Digital Inputs

SDI<3..0>

Operation Theory 33

A

SDI<3..0>

A

A

A

from CN2

From
Instrumentation

mplifier

D_conversion

Figure 4-1: Synchronous Digital Inputs Block Diagram

ADC

in

nADCONV

SDI<3..0>

D<11..0>

nADBUSY

16-bit

Register

4

AD

Data

FIFO

12

16

CLK nADBUSY

AD_conversion

nADBUSY

16 bits data(including AD<11..0> and SDI<3..0>
latched into AD Data FIFO

Figure 4-2: Synchronous Digital Inputs Timing

NOTE Since the analog signal is sampled when an A/D conver-

sion starts (falling edge of A/D_conversion signal), while
SDI<3..0> are sampled right after an A/D conversion
completes (rising edge of nADBUSY signal). Precisely
SDI<3..0> are sampled with 280ns lag to the analog sig­nal.

34 Operation Theory

Table 4-1and Table 4-2 illustrate the ideal transfer characteristics
of various input ranges of the DAQ-/DAQe-/PXI-2204/2205/2206/
2208 card.

Description Bipolar Analog Input Range

Digital

code

Full-scale Range ±10V ±5V ±2.5V ±1.25V —

Least significant bit 4.88mV 2.44mV 1.22mV 0.61mV —

FSR-1LSB 9.9951V 4.9976V 2.4988V 1.2494V 7FFX

Midscale +1LSB 4.88mV 2.44mV 1.22mV 0.61mV 001X

Midscale 0V 0V 0V 0V 000X

Midscale –1LSB -4.88mV -2.44mV -1.22mV -0.61mV FFFX

-FSR -10V -5V -2.5V -1.25V 800X

Table 4-1: Bipolar Analog Input Range and Output Digital Code on DAQ/

DAQe/PXI-2204/2208

Note that the last 4 digital codes are SDI<3..0> and is supported only on DAQ-/DAQe-/PXI-

2204)

Description Unipolar Analog Input Range Digital code

Full-scale Range 0V to 10V 0 to +5V 0 to +2.5V —

Least significant bit 2.44mV 1.22mV 0.61mV —

FSR-1LSB 9.9976V 4.9988V 2.9994V 7FFX

Midscale +1LSB 5.00244V 2.50122V 1.25061V 001X

Midscale 5V 2.5V 1.25V 000X

Midscale –1LSB 4.9976V 2.4988V 1.2494V FFFX

-FSR 0V 0V 0V 800X

Table 4-2: Unipolar Analog Input Range and Output Digital Code on DAQ/

DAQe/PXI-2204/2208

Note that the last 4 digital codes are SDI<3..0> and is supported only on DAQ-/DAQe-/PXI-

2204.

Operation Theory 35

DAQ/DAQe/PXI-2005/2006/2016 AI Data Format

The data format of the acquired 16-bit A/D data is 2's Comple­ment coding. Table 4-3 and Table 4-4 illustrate the valid input

ranges and the ideal transfer characteristics.

Description Bipolar Analog Input Range

Full-scale Range ±10V ±5V ±2.5V ±1.25V —

Least significant bit 305.2 µV 152.6 µV 76.3 µV 38.15 µV —

FSR-1LSB 9.999695V 4.999847V 2.499924V 1.249962V 7FFF

Midscale +1LSB 305.2 µV 152.6 µV 76.3 µV 38.15 µV 0001

Midscale 0V 0V 0V 0V 0000

Midscale -1LSB -305.2 µV -152.6 µV -76.3 µV -38.15 µV FFFF

-FSR -10V -5V -2.5V -1.25V 8000

Table 4-3: Bipolar Analog Input Range and Output Digital Code for DAQ/DAQe/

PXI-2205/2206

Description Unipolar Analog Input Range

Full-scale Range 0V to 10V 0 to +5V 0 to +2.5V 0 to +1.25V —

Least significant bit 152.6 µV 76.3 µV 38.15 µV 19.07 µV —

FSR-1LSB 9.999847V 4.999924V 2.499962V 1.249981V 7FFF

Midscale +1LSB 5.000153V 2.500076V 1.250038V 0.625019V 0001

Midscale 5V 2.5V 1.25V 0.625V 0000

Midscale -1LSB 4.999847V 2.499924V 1.249962V 0.624981V FFFF

Table 4-4: Unipolar Analog Input Range and Output Digital Code for DAQ/DAQe/

PXI-2205/2206

Digital

code

Digital

code

36 Operation Theory

Software Conversion with Polling Data Transfer Acquisi­tion Mode (Software Polling)

This is the easiest way to acquire a single A/D data. The A/D con­verter starts one conversion whenever the dedicated software
command is executed. Then the software would poll the conver­sion status and read the A/D data back when it is available.

This method is very suitable for applications that needs to process
A/D data in real time. Under this mode, the timing of the A/D con­version is fully controlled by the software. However, it is difficult to
control the A/D conversion rate.

Specifying Channel, Gain, and Input Configurations in the
Channel Gain Queue

In Software Polling and Programmable Scan Acquisition mode,
the channel, gain, polarity, and input configuration (RSE,
NRSE, or DIFF) can be specified in the Channel Gain Queue.
You can fill the channel number in the Channel Gain Queue in
any order. The channel order of acquisition will be the same as
the order you set in the Channel Gain Queue. Therefore, you
can acquire data with user-defined channel orders and with dif­ferent settings on each channel.

When the specified channels have been sampled from the first
data to the last data in the Channel Gain Queue, the settings in
Channel Gain Queue are maintained. You do not need to re­configure the Channel Gain Queue if you want to keep on sam­pling data in the same order. The maximum number of entries
you can set in the Channel Gain Queue is 512.

Example:

First you can set entries in Channel Gain Queue:

X Ch3 with bipolar ±10V, RSE connection

X Ch1 with bipolar ±2.5V, DIFF connection

X Ch2 with unipolar 5V, NRSE connection

X Ch1 with bipolar ±2.5V, DIFF connection

If you read 10 data by software polling method, then the acqui­sition sequence of channels is 3, 1, 2, 1, 3, 1, 2, 1, 3, 1.

Operation Theory 37

Programmable Scan Acquisition Mode

Scan Timing and Procedure

It is recommended that you use this mode if your applications
need a fixed and precise A/D sampling rate. You can accu­rately program the period between conversions of individual
channels. There are at least four counters which need to be
specified:

X SI_counter (24-bit): Specify the Scan Interval = SI_counter /

Timebase

X SI2_counter (16-bit): Specify the data Sampling Interval =

SI2_counter/Timebase

X PSC_counter (24-bit): Specify Post Scan Counts after a

trigger event

X NumChan_counter (9-bit): Specify the number of samples

per scan

The acquisition timing and the meanings of the 2 counters are
illustrated in Figure 4-3.

TIMEBASE Clock Source

In scan acquisition mode, all the A/D conversions start on the
output of counters, which use TIMEBASE as the clock source.
By software you can specify the TIMEBASE to be either an
internal clock source (onboard 40 MHz clock) or an external
clock input (EXTTIMEBASE) on CN2 connector. The external
TIMEBASE is useful when you want to acquire data at rates
not available with the internal A/D sample clock. The external
clock source should generate TTL-compatible continuous
clocks and with a maximum frequency of 40 MHz while the
minimum should be 1 MHz. Refer to section 4.6 for information
on user-controllable timing signals.

38 Operation Theory

(

)(p

)

3 Scans, 4 Samples per scan
(PSC_Counter=3, NumChan_Counter=4)

Scan_start

AD_conversion

Scan_in_progress

SSHOUT

in8 on CN2

Acquisition_in_progress

( channel sequences are specified in Channel Gain Queue)

Ch2

Ch3

Ch1

Ch0

Ch2

Ch3

Ch1

Ch0

Ch2

Ch3

Ch1

Ch0

Sampling Interval t=
SI2_COUNTER/TimeBase

Scan Interval T=
SI_COUNTER/TimeBase

Figure 4-3: Scan Timing

There are four trigger modes to start the scan acquisition. Refer to
section 4.1 for details. The data transfer mode is discussed in the
following section.

NOTES The maximum A/D sampling rate is 3 MHz for DAQ/

DAQe/PXI-2204/2208, 500 kHz for DAQ/DAQe/PXI­2205, and 250 kHz for DAQ/DAQe/PXI-2206. Therefore,
the minimum setting of SI2_counter is 14 for DAQ/DAQe/
PXI-2204/2208, 80 for DAQ/DAQe/PXI-2205, and 160 for
DAQ/DAQe/PXI-2206 while using the internal TIME­BASE.

The SI_counter is a 24-bit counter and the SI2_counter is
a 16-bit counter. The maximum scan interval using the in­ternal Timebase = 224/40 Ms = 0.419 s, and the maxi­mum sampling interval between two channels using the
internal Timebase = 216/40 Ms = 1.638 ms.

The scan interval may not be smaller than the product of
the data sampling interval and the NumChan_counter
value. The relationship can be represented as:
SI_counter>=SI2_counter * NumChan_counter.

Operation Theory 39

Scan with SSH

You can send the SSHOUT signal on CN2 to external S&H cir­cuits to sample and hold all signals if you want to simulta­neously sample all channels in a scan, as illustrated in
Figure 4-3.

NOTES The DAQ-/DAQe-/PXI-2208 does not support this func-

tion.

The SSHOUT signal is sent to external S&H circuits to
hold the analog signal. You must implement external
S&H circuits on their own to carry out the S&H function.
There are no onboard S&H circuits.

Specifying Channels, Gains, and Input Configurations in the Channel Gain Queue

Like software polling acquisition mode, the channel, gain, and
input configurations can be specified in the Channel Gain Queue
under the scan acquisition mode. Note that in scan acquisition
mode, the number of entries in the Channel Gain Queue is nor­mally equivalent to the value of NumChan_counter (that is, the
number of samples per scan).

Example: Set

X SI2_counter = 160

X SI_counter = 640

X PSC_counter = 3

X NumChan_counter = 4

X Timebase = Internal clock source

X Channel entries in the Channel Gain Queue: ch1, ch2, ch0,

ch2

40 Operation Theory

Then

X Acquisition sequence of channels: 1, 2, 0, 2, 1, 2, 0, 2, 1, 2,

0, 2

X Sampling interval: 160/40 Ms = 4 µs

X Scan interval: 640/40 Ms = 16 µs

X Equivalent sampling rate of ch0, ch1: 62.5 kHz

X Equivalent sampling rate of ch2: 125 kHz

Operation Theory 41

Trigger Modes

The DAQ-/DAQe-/PXI-2204/2205/2206/2208 card provides four
trigger sources (internal software trigger, external analog trigger,
and digital trigger sources, and SSI trigger signals). You must
select one of them as the source of the trigger event. A trigger
event occurs when the specified condition is detected on the
selected trigger source. For example, a rising edge on the external
digital trigger input. Refer to section 4.6 for more information on
SSI signals.

There are four trigger modes (pre-trigger, post-trigger, middle-trig­ger, and delay-trigger) working with the four trigger sources to ini­tiate different scan data acquisition timing when a trigger event
occurs. They are described in the following sections. For informa­tion on trigger sources, refer to section 4.5.

42 Operation Theory

Pre-Trigger Acquisition

Use pre-trigger acquisition in applications where you want to
collect data before a trigger event. The A/D starts to sample
when you execute the specified function calls to begin the pre­trigger operation, and it stops when the trigger event occurs.
Users must program the value M in M_counter (16 bits) to
specify the amount of the stored scans before the trigger event.
If an external trigger occurs, the program only stores the last M
scans of data converted before the trigger event, as illustrated
in Figure 4-4, where M_counter = M =3, PSC_counter = 0. The
post scan count is 0 because there is no sampling after the trig­ger event in pre-trigger acquisition. The total stored amount of
data = Number of enabled channels * M_counter.

AD_conversion

Scan_in_progress
(SSHOUT)(pin8 on CN2)

Acquisition_in_progress

(M_counter = M = 3, NumChan_counter=4, PSC_counter=0)

Trigger

Scan_start

Operation start

Figure 4-4: Pre-trigger (Trigger occurs after M scans)

Aquired data

Acquired & stored data
(M scans)

Operation Theory 43

Note that if a trigger event occurs when a scan is in progress, the
data acquisition won't stop until the scan completes, and the
stored M scans of data includes the last scan. Therefore, the first
stored data will always be the first channel entry of a scan (that is,
the first channel entry in the Channel Gain Queue if the number of
entries in the Channel Gain Queue is equivalent to the value of
NumChan_counter), no matter when a trigger signal occurs, as
illustrated in Figure 16, where M_counter = M =3,
NumChan_counter = 4, PSC_counter = 0.

(M_counter = M = 3, NumChan_counter =4, PSC_counter=0)

Trigger

Scan_start

AD_conversion

Scan_in_progress
(SSHOUT)(pin8 on CN2)

Acquisition_in_progress

Figure 4-5: Pre-trigger (Trigger with scan in progress)

Aquired data

Operation start

Acquired & stored data
(M scans)

Trigger occurs

Data acquisition
won’t stop until a
scan completes

44 Operation Theory

When the trigger signal occurs before the first M scans of data are
converted, the amount of stored data could be fewer than the orig­inally specified amount M_counter, as illustrated in Figure 4-6.
This situation can be avoided by setting M_enable. If M_enable is
set to 1, the trigger signal will be ignored until the first M scans of
data are converted, and it assures the user M scans of data under
pre-trigger mode, as illustrated in Figure 4-7. However, if
M_enable is set to 0, the trigger signal will be accepted any time,
as shown in Figure 4-6. Note that the total amount of stored data
will always be equal to the number in the M_counter because data
acquisition does not stop until a scan is completed.

(M_Counter = M = 3, NumChan_Counter=4, PSC_Counter=0)

Trigger

Scan_start

AD_conversion

Scan_in_progress
(SSHOUT)(pin8 on CN2)

Acquisition_in_progress

Acquired & stored data
(2 scans)

Operation start

Figure 4-6: Pre-trigger with M_enable=0 (Trigger occurs before M scans)

Operation Theory 45

AD_conversion

Scan_in_progress
(SSHOUT)(pin2 on CN2)

Acquisition_in_progress

(M_counter = M = 3, NumChan_counter=4, PSC_counter=0)

Trigger

Scan_start

The first M scans

Trigger signals which occur in the shadow
region(the first M scans) will be ignored

Aquired data

Operation start

Acquired & stored data
(M scans)

Figure 4-7: Pre-trigger with M_enable=1

NOTE The PSC_counter is set to 0 in pre-trigger acquisition

mode.

46 Operation Theory

Middle-Trigger Acquisition

Use middle-trigger acquisition in applications where you want
to collect data before and after a trigger event. The number of
scans (M) stored before the trigger is specified in M_counter,
while the number of scans (N) after the trigger is specified in
PSC_counter.

Like pre-trigger mode, the number of stored data could be less
than the specified amount of data (M+N), if an external trigger
occurs before M scans of data are converted. The M_enable bit
in middle-trigger mode takes the same effect as in pre-trigger
mode. If M_enable is set to 1, the trigger signal will be ignored
until the first M scans of data are converted, and it assures the
user with (M+N) scans of data under middle-trigger mode.
However, if M_enable is set to 0, the trigger signal will be
accepted at any time. Figure 4-8 shows the acquisition timing
with M_enable=1.

Figure 4-8: Middle-Trigger with M_enable = 1

Operation Theory 47

If the trigger event occurs when a scan is in progress, the stored N
scans of data would include this scan, as illustrated in Figure 4-9.

Figure 4-9: Middle-Trigger (Trigger occurs when a scan is in progress)

48 Operation Theory

Post-Trigger Acquisition

Use post-trigger acquisition in applications where you want to
collect data after a trigger event. The number of scans after the
trigger is specified in PSC_counter, as illustrated in Figure 4-

10. The total acquired data length = NumChan_counter *
PSC_counter.

Scan_in_progress
(SSHOUT)(pin8 on CN2

Acquisition_in_progress

(NumChan_Counter=4, PSC_Counter=3)

Trigger

Scan_start

AD_conversion

Operation start

Figure 4-10: Post-trigger

Acquired & stored data
(3 scans)

Operation Theory 49

Delay Trigger Acquisition

Use delay trigger acquisition in applications where you want to
delay the data collection after the occurrence of a specified trig­ger event. The delay time is controlled by the value, which is
pre-loaded in the Delay_counter (16-bit). The counter counts
down on the rising edge of the Delay_counter clock source
after the trigger condition is met. The clock source can be soft­ware-programmed either by the TIMEBASE clock (40 MHz) or
A/D sampling clock (TIMEBASE / SI2_counter). When the
count reaches 0, the counter stops and the card starts to
acquire data. The total acquired data length =
NumChan_counter * PSC_counter.

AD_conversion

Scan_in_progress
(SSHOUT)(pin8 on CN2)

Acquisition_in_progress

(NumChan _Counter=4, PSC_Counter=3)

Trigger

Scan_start

Delay until
Delay_Counter
reaches 0

Operation start

Acquired & stored data
(3 scans)

Figure 4-11: Delay trigger

NOTE When the Delay_counter clock source is set to TIME-

BASE, the maximum delay time is 216/40 Ms or 1.638 ms.
When the source is set to A/D sampling clock, the maxi­mum delay time may be higher than 2

16

* SI2_counter /

40M.

50 Operation Theory

Post-Trigger or Delay-trigger Acquisition with re-trigger

Use post-trigger or delay-trigger acquisition with re-trigger
function in applications where you want to collect data after
several trigger events. The number of scans after each trigger
is specified in PSC_counter, and users could program
Retrig_no to specify the re-trigger numbers. Figure 4-12 illus­trates an example. In this example, two scans of data is
acquired after the first trigger signal, then the card waits for the
re-trigger signal (re-trigger signals which occur before the first
two scans is completed will be ignored). When the re-trigger
signal occurs, two more scans are performed. The process
repeats until specified amount of re-trigger signals are
detected. The total acquired data length = NumChan_counter *
PSC_counter * Re-trig_no.

Scan_in_progress
(SSHOUT)(pin8 on CN2)

Acquisition_in_progress

(NumChan _Counter=4, PSC_Counter=2, retrig_no=3)

Trigg er

Scan_start

AD_conversion

Acquired & stored data
(6 scans)

Operation start

Figure 4-12: Post trigger with Re-trigger

Operation Theory 51

Bus-mastering DMA Data Transfer

PCI bus-mastering DMA is necessary for high speed DAQ in order
to utilize the maximum PCI bandwidth. The bus-mastering control­ler, which is built in the PLX IOP-480 PCI controller, controls the
PCI bus when it becomes the master of the bus. Bus mastering
reduces the size of the on-board memory and reduces the CPU
loading because data is directly transferred to the computer’s
memory without host CPU intervention.

Bus-mastering DMA provides the fastest data transfer rate on PCI­bus. Once the analog input operation starts, control returns to your
program. The hardware temporarily stores the acquired data in the
onboard AD Data FIFO and then transfers the data to a user­defined DMA buffer memory in the computer. Note that even when
the acquired data length is less than the Data FIFO, the AD data is
not kept in the Data FIFO but directly transferred into host memory
by the bus-mastering DMA.

The DMA transfer mode is complicated to program. We recom­mend using a high-level program library to configure this card. If
users would like to know more about software programs that can
handle the DMA bus master data transfer, visit to http://www.plx­tech.com for more information on PCI controllers.

By using a high-level programming library for high speed DMA
data acquisition, you simply need to assign the sampling period
and the number of conversion into your specified counters. After
the AD trigger condition is matched, the data is transferred to the
system memory by the bus-mastering DMA.

The PCI controller also supports the function of scatter/gather bus
mastering DMA, which helps you transfer large amounts of data
by linking all the memory blocks into a continuous linked list.

In a multi-user or multi-tasking OS, like Windows, Linux, etc, it is
difficult to allocate a large continuous memory block to do the
DMA transfer. Therefore, the PLX IOP-480 provides the function
of scatter/gather or chaining mode DMA to link the non-continuous
memory blocks into a linked list so that you can transfer very large
amounts of data without being limited by the fragment of small size
memory. You can configure the linked list for the input DMA chan­nel or the output DMA channel.

52 Operation Theory

Figure 4-13 shows a linked list that is constructed by three DMA
descriptors. Each descriptor contains a PCI address, a local
address, a transfer size, and the pointer to the next descriptor.
You can allocate many small size memory blocks and chain their
associative DMA descriptors altogether by their application pro­grams. The DAQ-/DAQe-/PXI-2204/2205/2206/2208 card soft­ware driver provides simple settings for the scatter/gather
function, including some sample programs in the ADLINK All-in­One CD.

Figure 4-13: Scatter/gather DMA for Data Transfer

In non-chaining mode, the maximum DMA data transfer size is 2
M double words (8M bytes). However, there is no limitation on the
DMA data transfer size when using scatter/gather chaining mode.
You can also link the descriptor nodes circularly to achieve a multi­buffered mode DMA.

Operation Theory 53

4.2 D/A Conversion

NOTE The DAQ-/DAQe-/PXI-2208 card does not support this

function.

There are two 12-bit D/A output channels available in the DAQ-/
DAQe-/PXI-2204/2205/2206 card. When using D/A converters,
you should assign and control the D/A converter reference
sources for the D/A operation mode and D/A channels. You could
also set the output polarity to unipolar or bipolar.

The reference selection control lets you utilize in full the multiply­ing characteristics of the D/A converters. Internal 10V reference
and external reference inputs are available in the DAQ-/DAQe-/
PXI-2204/2205/2206 card. The range of the D/A output is directly
related to the reference. The digital codes that are updated to the
D/A converters will multiply with the reference to generate the ana­log output. While using internal 10V reference, the full range would
be –10V to +9.9951V in the bipolar output mode, and 0V to

9.9976V in the unipolar output mode. While using an external ref­erence, you can reach different output ranges by connecting differ­ent references. For example, if connecting a DC –5V with the
external reference, then you can get a full range from –4.9976V to
+5V in the bipolar output with inverting characteristics due to the
negative reference voltage. You could also have an amplitude
modulated (AM) output by feeding a sinusoidal signal into the ref­erence input. The range of the external reference should be within
±10V. Table 4-5 and Table 4-6 illustrates the relationship between
digital code and output voltages with Vref=10V and if internal ref­erence is selected.

Digital Code Analog Output

111111111111 Vr ef * (2047/2048)

100000000001 Vref * (1/2048)

100000000000 0V

011111111111 -Vr e f * ( 1 / 2 0 48)

000000000000 -Vref

Table 4-5: Bipolar Output Code Table

54 Operation Theory

Digital Code Analog Output

111111111111 Vref * (4095/4096)

100000000000 Vref * (2048/4096)

000000000001 Vref * (1/4096)

000000000000 0V

Table 4-6: Unipolar Output Code Table

The D/A conversion is initiated by a trigger source. You must
decide how to trigger the D/A conversion. The data output will start
when a trigger condition is met. Before the start of D/A conversion,
D/A data is transferred from the computer’s main memory to a
buffering Data FIFO.

Two D/A conversion modes are available: Software Update and
Timed Waveform Generation. These are described below, includ­ing the timing, trigger source control, trigger modes, and data
transfer methods. Either mode may be applied to D/A channels
independently. You can simultaneously software update DA CH0
while generating timed waveforms on CH1.

Software Update

This is the easiest way to generate D/A output. To do this:

1. Specify the D/A output channels.

2. Set output polarity (unipolar or bipolar) and reference
source (internal 10V or external AOEXTREF).

3. Update the digital values into D/A data registers through
a software output command.

Operation Theory 55

Timed Waveform Generation

This mode can provide your applications with a precise D/A output
with a fixed update rate. It can be used to generate an infinite or
finite waveform. You can accurately program the update period of
the D/A converters.

The D/A output timing is provided through a combination of
counters in the FPGA on board. There are a total of five counters
to be specified. These counters include:

X UI_counter (24 bits): specify the DA update interval is equal

to CHUI_counter/TIMEBASE

X UC_counter (24 bits): specify the total update counts in a

single waveform

X IC_counter (24 bits): specify the iteration counts of wave-

form

X DA_DLY1_counter (16 bits): specify the delay from the trig-

ger to the first update start

X DA_DLY2_counter (16 bits): specify the delay between two

consecutive waveform generations

Figure 4-14 shows a typical D/A timing diagram assuming the data
in the data buffer are 2V, 4V, -4V, 0V. D/A updates its output on
each rising edge of DAWR. The meaning of the counters enumer­ated above are discussed in the following sections.

56 Operation Theory

Trigger

DAWR

WFG_in_progress

4 update counts, 3 iterations

(UC _Counter=4, IC_Counter=3)

UC_Counter=4

Output Waveform

Operation start

Delay until
DLY1_Counter
reaches 0

Delay until
DLY2_Counter
reaches 0

DA update_interval t=
UI_Counter/Timebase

-

A single waveform

IC_Counter = 3

Delay until
DLY2_Counter
reaches 0

Figure 4-14: Typical D/A Timing of Waveform Generation

NOTE The maximum D/A update rate is 1 MHz. Therefore, the

minimum setting of the UI_counter is 40 while using an in­ternal TIMEBASE (40 MHz).

Operation Theory 57

Trigger Modes

Post-Trigger Generation

Use post-trigger when you want to perform DA waveform right
after a trigger event occurs. In this trigger mode DLY1_Counter
is ignored and not be specified. Figure 4-15 shows a single
waveform generated right after a trigger signal is detected and
assuming the data in the data buffer are 2V, 4V, 6V, 3V, 0V, ­4V, -2V, and 4V. The trigger signal could come from a software
command, an analog trigger or a digital trigger. Refer to section

4.5 for detailed information.

Trigger

DAWR

WFG_in_progress

Output Waveform

8 update counts, 1 iteration

(UC _Counter=8, IC_Counter=1)

2

-

-

Operation start

Figure 4-15: Post Trigger Waveform Generation

Delay-Trigger Generation

Use delay trigger when you want to delay the waveform gener­ation after a trigger event. In Table 4-16, DA_DLY1_counter
determines the delay time from the trigger signal to the start of
the waveform generation, assuming the data in the data buffer
are 2V, 4V, 6V, 3V, 0V, -4V, -2V, and 4V. DLY1_counter
counts down on the rising edge of its clock source after the trig­ger condition is met. When the count reaches 0, the counter
stops and the DAQ-/DAQe-/PXI-2204/2205/2206/2208 card
starts the waveform generation. This DLY1_Counter is 16-bit
wide and you can set the delay time in units of TIMEBASE
(delay time = DLY1_Counter/TIMEBASE) or in units of update
period (delay time = DLY1_Counter * UI_counter/TIMEBASE),
so the delay time can reach a wider range.

58 Operation Theory

Figure 4-16: Delay Trigger Waveform Generation

Post-Trigger or Delay-Trigger with Re-trigger

Use post-trigger or delay-trigger with re-trigger function when
you want to generate waveform after more than one trigger
events. The re-trigger function can be enabled or disabled by
software setting. In Figure 4-17, each trigger signal will initiate
a waveform generation assuming the data in the data buffer
are 2V, 4V, 2V, and 0V. However, the trigger event would be
ignored while the waveform generation is ongoing.

Figure 4-17: Re-triggered Waveform Generation with Post-Trigger

(DLY2_Counter=0)

Operation Theory 59

Iterative Waveform Generation

Set IC_Counter in order to generate iterative waveforms from
the data of a single waveform. The counter stores the iteration
number and the iterations may be finite (Figure 4-18) or infinite
(Figure 4-19). Take note that in infinite mode the waveform
generation does not stop until software stop function is exe­cuted and IC_Counter is still valid when stop mode III is
selected. Both figures assume that the data in the data buffer
are 2V, 4V, 2V, and 0V.

An onboard data FIFO is used to buffer the digital data for DA
output. If the data size of a single waveform you specified (That
is, Update Counts in UC_counter) is less than the FIFO size,
after initially transferring the data from the host PC memory to
the FIFO on board, the data in the FIFO will be automatically
re-transmitted whenever a single waveform is completed.
Therefore, it does not occupy the PCI bandwidth when repeti­tive waveforms are performed. However, if the size of a single
waveform were larger than that of the FIFO, it needs to be
intermittently loaded from the host PC’s memory via DMA,
when a repetitive waveforms is performed thus PCI bandwidth
would be occupied.

The data FIFO size on the DAQ-/DAQe-/PXI-2204/2205/2206/
2208 card is 1024 (words) when one DA channel is enabled, or
512 (words) when both DA channels are enabled.

Figure 4-18: Finite Iterative Waveform Generation with Post-trigger

(DLY2_Counter = 0)

60 Operation Theory

Figure 4-19: Infinite Iterative Waveform Generation with Post-trigger

(DLY2_Counter = 0)

Delay2 in Iterative Waveform Generation

To stretch out the flexibility of the D/A waveform generation, we
add a DLY2_Counter to separate two consecutive waveforms
in iterative waveform generation. The time between two wave­forms is assigned by setting the value of the DLY2_Counter.
The DLY2_Counter starts to count down after a waveform gen­eration finishes and the next waveform generation starts right
after it counts down to zero, as shown in Figure 4-20. This
DLY2_Counter is 16-bit wide and you may set the delay time in
unit of TIMEBASE (delay time = DLY2_Counter/TIMEBASE) or
in unit of update period (delay time = DLY2_Counter *
UI_Counter/TIMEBASE), so the delay time can reach a wider
range.

Operation Theory 61

Stop Modes of Scan Update

You can call software stop function to stop waveform genera­tion when it is still in progress. Three stop modes are provided
for timed waveform generation meant to stop the waveform
generation. You can apply these three modes to stop wave­form generation no matter infinite or finite waveform generation
mode is selected.

Figure 4-20 illustrates an example for stop mode I, assuming
the data in the data buffer are 2V, 4V, 2V, and 0V. In this
mode, the waveform stops immediately when software com­mand is asserted.

.

Figure 4-20: Stop Mode I

62 Operation Theory

In stop mode II, after a software stop command is given, the
waveform generation does not stop until a complete single
waveform is finished. See Figure 4-21. Since the UC_counter
is set to four, the total DA update counts (number of pulses of
DAWR signal) must be a multiple of four (update counts = 20 in
this example).

Figure 4-21: Stop Mode II

In stop mode III, after a software stop command is given, the
waveform generation does not stop until the performed number
of waveforms is a multiple of the IC_Counter. See Figure 4-22.
Since the IC_Counter is set to three, the total generated wave­forms must be a multiple of three (waveforms = 6 in this exam­ple), and the total DA update counts must be a multiple of 12
(UC_counter * IC_Counter). You can compare these three fig­ures to see the differences.

Figure 4-22: Stop Mode III

Operation Theory 63

4.3 Digital I/O

The DAQ-/DAQe-/PXI-2204/2205/2206/2208 card contains 24
lines of general-purpose digital I/O (GPIO) which is provided
through the 82C55A chip.

The 24-line GPIO are separated into three ports: Port A, Port B
and Port C. Port A and Port B can be programmed to be either
input or output ports. Port C can be separated into high bit (PC4­PC7) and low bit (PC0-PC3), and both high bit and low bit ports
can be programmed for input or output. Upon system startup or
reset, all the GPIO pins are reset to high impedance inputs.

The DAQ/DAQe/PXI-2010 also provides two digital inputs per
channel (SDI from CN2), which are sampled simultaneously with
an analog signal input and is stored with the 12-bit AD data. Refer
to Figure 4.1 for the more details.

4.4 General Purpose Timer/Counter Operation

NOTE The DAQ-/DAQe-/PXI-2208 card does not support this

function.

Two independent 16-bit up/down timer/counter are designed
within FPGA for various applications. They have the following fea­tures:

X Count up/down controlled by hardware or software

X Programmable counter clock source (internal or external

clock up to 10 MHz)

X Programmable gate selection (hardware or software con-

trol)

X Programmable input and output signal polarities (high active

or low active)

X Initial count can be loaded from software

X Current count value can be read-back by software without

affecting circuit operation

64 Operation Theory

The Basics of Timer/Counter Functions

Each timer/counter has three inputs that can be controlled via
hardware or software. These are clock input (GPTC_CLK), gate
input (GPTC_GATE), and up/down control input
(GPTC_UPDOWN). The GPTC_CLK input provides a clock
source input to the timer/counter. Active edges on the GPTC_CLK
input make the counter increment or decrement. The
GPTC_UPDOWN input controls whether the counter counts up or
down. The GPTC_GATE input is a control signal which acts as a
counter enable or a counter trigger signal under different applica­tions.

The output of timer/counter is GPTC_OUT. After power-up,
GPTC_OUT is pulled high by a pulled-up resister about 10K
ohms. Then GPTC_OUT goes low after the DAQ-/DAQe-/PXI­2204/2205/2206/2208 card is initialized.

All the polarities of input/output signals can be programmed by
software. In this chapter, for easy explanation, all GPTC_CLK,
GPTC_GATE, and GPTC_OUT are assumed to be active high or
rising-edge triggered in the figures.

General Purpose Timer/Counter modes

Eight programmable timer/counter modes are provided. All modes
start operating following a software-start signal that is set by the
software. The GPTC software reset initializes the status of the
counter and re-loads the initial value to the counter. The operation
remains halted until the software-start is re-executed. The operat­ing theories under different modes are described in the following
sections.

Operation Theory 65

Mode1: Simple Gated-Event Counting

In this mode, the counter counts the number of pulses on the
GPTC_CLK after the software-start. Initial count can be loaded
from software. Current count value can be read-back by soft­ware any time without affecting the counting. GPTC_GATE is
used to enable/disable counting. When GPTC_GATE is inac­tive, the counter halts the current count value. Figure 4-23 illus­trates the operation with initial count = 5, countdown mode.

Figure 4-23: Mode1 Operation

Mode2: Single Period Measurement

In this mode, the counter counts the period of the signal on
GPTC_GATE in terms of GPTC_CLK. Initial count can be
loaded from software. After the software-start, the counter
counts the number of active edges on GPTC_CLK between
two active edges of GPTC_GATE. After the completion of the
period interval on GPTC_GATE, GPTC_OUT outputs high and
then current count value can be read-back by software.
Figure 4-24 illustrates the operation where initial count = 0,
count-up mode.

66 Operation Theory

Figure 4-24: Mode2 Operation

Mode3: Single Pulse-width Measurement

In this mode, the counter counts the pulse-width of the signal
on GPTC_GATE in terms of GPTC_CLK. Initial count can be
loaded from software. After the software-start, the counter
counts the number of active edges on GPTC_CLK when
GPTC_GATE is in its active state. After the completion of the
pulse-width interval on GPTC_GATE, GPTC_OUT outputs
high, then current count value can be read-back by software.
Figure 4-25 illustrates the operation where initial count = 0,
count-up mode.

Figure 4-25: Mode3 Operation

Operation Theory 67

Mode4: Single Gated Pulse Generation

This mode generates a single pulse with programmable delay
and programmable pulse-width following the software-start.
The two programmable parameters could be specified in terms
of periods of the GPTC_CLK input by software. GPTC_GATE
is used to enable/disable counting. When GPTC_GATE is inac­tive, the counter halts the current count value. Figure 4-26 illus­trates the generation of a single pulse with a pulse delay of two
and a pulse-width of four.

Figure 4-26: Mode4 Operation

Mode5: Single Triggered Pulse Generation

This function generates a single pulse with programmable
delay and pro-grammable pulse-width following an active
GPTC_GATE edge. You could specify these programmable
parameters in terms of periods of the GPTC_CLK input. Once
the first GPTC_GATE edge triggers the single pulse,
GPTC_GATE takes no effect until the software-start is re-exe­cuted. Figure 4-27 illustrates the generation of a single pulse
with a pulse delay of two and a pulse-width of four.

68 Operation Theory

Figure 4-27: Mode5 Operation

Mode6: Re-triggered Single Pulse Generation

This mode is similar to Mode5 except that the counter gener­ates a pulse following every active edge of GPTC_GATE. After
the software-start, every active GPTC_GATE edge triggers a
single pulse with programmable delay and pulse-width. Any
GPTC_GATE triggers that occur when the prior pulse is not
completed would be ignored. Figure 4-28 illustrates the gener­ation of two pulses with a pulse delay of two and a pulse-width
of four.

Figure 4-28: Mode6 Operation

Operation Theory 69

Mode7: Single Triggered Continuous Pulse Generation

This mode is similar to Mode5 except that the counter gener­ates continuous periodic pulses with programmable pulse inter­val and pulse-width following the first active edge of
GPTC_GATE. Once the first GPTC_GATE edge triggers the
counter, GPTC_GATE takes no effect until the software-start is
re-executed. Figure 4-29 illustrates the generation of two
pulses with a pulse delay of four and a pulse-width of three.

Figure 4-29: Mode7 Operation

Mode8: Continuous Gated Pulse Generation

This mode generates periodic pulses with programmable pulse
interval and pulse-width following the software-start.
GPTC_GATE is used to enable/disable counting. When
GPTC_GATE is inactive, the counter halts the current count
value. Figure 4-30 illustrates the generation of two pulses with
a pulse delay of four and a pulse-width of three.

Figure 4-30: Mode8 Operation

70 Operation Theory

4.5 Trigger Sources

ADLINK provides flexible trigger selections in the DAQ-/DAQe-/
PXI-2204/2205/2206/2208 card. In addition to the internal soft­ware trigger, the DAQ-/DAQe-/PXI-2204/2205/2206/2208 card
also supports external analog, digital triggers, and SSI triggers.
You can configure the trigger source by software for A/D and D/A
processes individually. Note that the A/D and the D/A conversion
share the same analog trigger.

Software-Trigger

This trigger mode does not need any external trigger source. The
trigger asserts right after you execute the specified function calls
to begin the operation. A/D and D/A processes can receive an
individual software trigger.

External Analog Trigger

The analog trigger circuitry routing is shown in the Figure 4-31.
The analog multiplexer can select either a direct analog input from
the EXTATRIG pin (SRC1 in Figure 4-31) in the 68-pin connector
or the input signal of ADC (SRC2 in Figure 4-31). That is, one of
the four channel inputs you can select as a trigger source. Both
trigger sources can be used for all trigger modes. The range of
trigger level for SRC1 is ±10V and the resolution is 78mV (refer to
Table 4-6), while the trigger range of SRC2 is the full-scale range
of the selected channel input and the resolution is the desired
range divided by 256. For example, if the channel input selected to
be the trigger source is set bipolar and ±5V range, the trigger volt­age would be 4.96V when the trigger level code is set to 0xFF
while -4.96V when the code is set to 0x01.

Operation Theory 71

Figure 4-31: Analog Trigger Block Diagram

Trigger level digital setting Tri gger vol tage

0xFF 9.92V

0xFE 9.84V

0x81 0.08V

0x80 0

0x7F -0.08V

0x01 -9.92V

Table 4-7: Analog Trigger SRC1 (EXTATRIG) Ideal Transfer Characteristic

The trigger signal is generated when the analog trigger condition
is satisfied. There are five analog trigger conditions in the DAQ-/
DAQe-/PXI-2204/2205/2206/2208 card. The DAQ-/DAQe-/PXI­2204/2205/2206/2208 card uses two threshold voltages,
Low_Threshold and High_Threshold to build the five different trig­ger conditions. You can configure the trigger conditions easily by
software.

72 Operation Theory

Below-Low Analog Trigger Condition

Figure 4-32 shows the below-low analog trigger condition, the
trigger signal is generated when the input analog signal is less
than the Low_Threshold voltage, and the High_Threshold set­ting is not used in this trigger condition.

Figure 4-32: Below-Low Analog Trigger Condition

Above-High Analog Trigger Condition

Figure 4-33 shows the above-high analog trigger condition, the
trigger signal is generated when the input analog signal is
higher than the High_Threshold voltage, and the
Low_Threshold setting is not used in this trigger condition.

Figure 4-33: Above-High Analog Trigger Condition

Operation Theory 73

Inside-Region Analog Trigger Condition

Figure 4-34 shows the inside-region analog trigger condition,
the trigger signal is generated when the input analog signal
level falls in the range between the High_Threshold and the
Low_Threshold voltages.

NOTE The High_Threshold setting should be always higher

than the Low_Threshold voltage setting.

Figure 4-34: Inside-Region Analog Trigger Condition

High-Hysteresis Analog Trigger Condition

Figure 4-35 shows the high-hysteresis analog trigger condition,
the trigger signal is generated when the input analog signal
level is greater than the High_Threshold voltage, and the
Low_Threshold voltage determines the hysteresis duration.
Note the High_Threshold setting should be always higher then
the Low_Threshold voltage setting.

74 Operation Theory

Figure 4-35: High-Hysteresis Analog Trigger Condition

Low-Hysteresis Analog Trigger Condition

Figure 4-36 shows the low-hysteresis analog trigger condition,
the trigger signal is generated when the input analog signal
level is less than the Low_Threshold voltage, and the
High_Threshold voltage determines the hysteresis duration.
Note the High_Threshold setting should be always higher then
the Low_Threshold voltage setting.

Figure 4-36: Low-Hysteresis Analog Trigger Condition

Operation Theory 75

External Digital Trigger

An external digital trigger occurs when a rising edge or a falling
edge is detected on the digital signal connected to the EXT­DTRIG or the EXTWFTRG of the 68-pin connector for external
digital trigger. The EXTDTRIG is dedicated for A/D process,
and the EXTWFTRG is used for D/A process. You can program
the trigger polarity using the software drivers. Note that the sig­nal level of the external digital trigger signals should be TTL­compatible and the minimum pulse is 20 ns.

Figure 4-37: External Digital Trigger

76 Operation Theory

4.6 User-controllable Timing Signals

In order to meet the requirements for user-specific timing and
requirements for synchronizing multiple cards, the DAQ-/DAQe-/
PXI-2204/2205/2206/2208 card provides flexible user-controllable
timing signals to connect to external circuitry or additional cards.

The whole DAQ timing of the DAQ-/DAQe-/PXI-2204/2205/2206/
2208 card is composed of a bunch of counters and trigger signals
in the FPGA. These timing signals are related to the A/D, D/A con­versions, and Timer/Counter applications. These timing signals
can be input to or output from the I/O connectors, SSI connector,
and the PXI bus. Therefore, the internal timing signals can be
used to control external devices or circuitry. Note that in other
models of DAQ-/DAQe-/PXI-2204/2205/2206/2208 card, the user­controllable timing signals may vary. However, the SSI/PXI timing
signals remain the same for every DAQ-/DAQe-/PXI-2204/2205/
2206/2208 card.

We implemented signal multiplexers in the FPGA to individually
choose the desired timing signals for the DAQ operations, as
shown in the Figure 4-38.

Figure 4-38: DAQ signals routing

Operation Theory 77

You can utilize the flexible timing signals through our software
drivers, then simply and correctly connect the signals with the
DAQ-/DAQe-/PXI-2204/2205/2206/2208 card. Here is the sum­mary of the DAQ timing signals and the corresponding functional­ities for DAQ-/DAQe-/PXI-2204/2205/2206/2208 card.

Timing signal category Corresponding functionality

SSI/PXI signals Multiple cards synchronization

AFI signals

Table 4-8: User-controllable Timing Signals and Functionalities

Control DAQ-/DAQe-/PXI-2204/2205/2206/
2208 by external timing signals

DAQ timing signals

NOTES Refer to section 4.1 for the internal timing signal defini-

tion.

The DAQ-/DAQe-/PXI-2208 card supports
SCAN_START, ADCONV and DA_TRIG, DAWR.

The user-controllable DAQ timing-signals contain:

1. TIMEBASE, providing TIMEBASE for all DAQ opera­tions, which could be from internal 40 MHz oscillator,
EXTTIMEBASE from I/O connector or the
SSI_TIMEBASE. Note that the frequency range of the
EXTTIMEBASE is 1 MHz to 40 MHz, and the EXTTIME­BASE must be TTL-compatible.

2. AD_TRIG, the trigger signal for the A/D operation, which
could come from external digital trigger, analog trigger,
internal software trigger, and SSI_AD_TRIG. Refer to
section 4.5 for detailed description.

3. SCAN_START, the signal to start a scan, which would
bring the following ADCONV signals for AD conversion,
and could come from the internal SI_counter, AFI[0] and
SSI_AD_START. This signal is synchronous to the
TIMEBASE. Note that the AFI[0] should be TTL-compat­ible and the minimum pulse width should be the pulse

78 Operation Theory

width of the TIMEBASE to guarantee correct functional­ities.

4. ADCONV, the conversion signal to initiate a single con-

version, which could be derived from internal counter,
AFI[0] or SSI_ADCONV. Note that this signal is edge­sensitive. When using AFI[0] as the external ADCONV
source, each rising edge of AFI[0] would bring an effec­tive conversion signal. Also note that the AFI[0] signal
should be TTL-compatible and the minimum pulse width
is 20 ns.

5. DA_TRIG, the trigger signal for the D/A operation, which

could be derived from external digital trigger, analog trig­ger, internal software trigger, and SSI_AD_TRIG. Refer
to section 4.5 for detailed description.

6. DAWR, the update signal to initiate a single D/A conver-

sion, which could be derived from internal counter,
AFI[1] or SSI_DAWR. Note that this signal is edge-sensi­tive. When using AFI[1] as the external DAWR source,
each rising edge of AFI[1] would bring an effective
update signal. Also note that the AFI[1] signal should be
TTL-compatible and the minimum pulse width is 20 ns.

Operation Theory 79

Auxiliary Function Inputs (AFI)

You can use the AFI in applications that take advantage of exter­nal circuitry to directly control the DAQ-/DAQe-/PXI-2204/2205/
2206/2208 card. The AFI includes two categories of timing signals:
one group is the dedicated input, and the other is the multi-func­tion input. Table 4-9 illustrates this categorization.

Category Timing signal Functionality Constraints

Replace the

EXTTIMEBASE

Dedi­cated

input

Multi-

function

input

Table 4-9: Auxiliary Function Input Signals and Functionalities

EXTDTRIG

EXTWFTRG

AFI[0]

(Dual-functions)

AFI[1]

internal TIME-

BASE

External digital
trigger input for

A/D operation

External digital
trigger input for

D/A operation

Replace the

internal

ADCONV

Replace the

internal

SCAN_START

Replace the

internal DAWR

EXTDTRIG and EXTWFTRIG

•TTL-compatible

• 1 MHz to 40 MHz

• Affects on both A/D and D/A
operations.

•TTL-compatible

• Minimum pulse width = 20ns

• Rising edge or falling edge

•TTL-compatible

• Minimum pulse width = 20ns

• Rising edge or falling edge

•TTL-compatible

• Minimum pulse width = 20ns

• Rising–edge sensitive only

•TTL-compatible

• Minimum Pulse width > 2/
TIMEBASE

•TTL-compatible

• Minimum pulse width = 20ns

• Rising–edge sensitive only

EXTDTRIG and EXTWFTRIG are dedicated digital trigger input
signals for A/D and D/A operations respectively. Refer to sec­tion 4.5 for details.

EXTTIMEBASE

When the applications needs specific sampling frequency or
update rate that the card could not generate from its internal
TIMEBASE — the 40 MHz clock — you could utilize the EXT­TIMEBASE with internal counters to achieve the specific timing

80 Operation Theory

intervals for both A/D and D/A operations. Note that once you
choose the TIMEBASE source, both A/D and D/A operations
will be affected because A/D and D/A operations share the
same TIMEBASE.

AFI[0]

Alternatively, you can also directly apply an external A/D con­version signal to replace the internal ADCONV signal. This is
another way to achieve customized sampling frequencies. The
external ADCONV signal can only be inputted from the AFI[0].
As section 4.1 describes, the SI_counter triggers the genera­tion of the A/D conversion signal, ADCONV, but when using
the AFI[0] to replace the internal ADCONV signal, the
SI_counter and the internally generated SCAN_START is not
effective. By controlling the ADCONV externally, you can sam­ple the data according to external events. In this mode, the
Trigger signal and trigger mode settings are not available.

AFI[0] could also be used as SCAN_START signal for A/D
operations. Refer to section 4.1 and section 4.6 for detailed
descriptions of the SCAN_START signal. When using external
signal (AFI[0]) to replace the internal SCAN_START signal, the
pulse width of the AFI[0] must be greater than two time of the
period of Timebase. This feature is suitable for the DAQ-2200/
DAQe-2200/PXI-2200 Series, which can scan multiple chan­nels data controlled by an external event. Note that the AFI[0]
is a multi-purpose input, and it can only be utilized for one func­tion at any one time.

AFI[1]

Regarding the D/A operations, users could directly input the
external D/A update signal to replace the internal DAWR sig­nal. This is another way to achieve customized D/A update
rates. The external DAWR signal can only be inputted from the
AFI[1]. Note that the AFI[1] is a multi-purpose input, and it can
only be utilized for one function at any one time. AFI[1] cur­rently only has one function. ADLINK reserves it for future
development.

Operation Theory 81

System Synchronization Interface

SSI (System Synchronization Interface) provides the DAQ timing
synchronization between multiple cards. In DAQ-/DAQe-/PXI­2204/2205/2206/2208 card, we designed a bi-directional SSI I/O
to provide flexible connection between cards and allow one SSI
master to output the signal and up to three slaves to receive the
SSI signal. Note that the SSI signals are designed for card syn­chronization only and not for external devices.

SSI Timing Signal Setting Function

Master Send the TIMEBASE out

SSI_TIMEBASE

SSI_ADCONV

SSI_SCAN_START

SSI_AD_TRIG

SSI_DAWR

SSI_DA_TRIG

Slave

Master Send the ADCONV out

Slave

Master Send the SCAN_START out

Slave

Master Send the internal AD_TRIG out

Slave Accept the SSI_AD_TRIG as the digital trigger signal.

Master Send the DAWR out.

Slave

Master Send the DA_TRIG out.

Slave Accept the SSI_DA_TRIG as the digital trigger signal.

Table 4-10: SSI Timing Signal and Functions

In PCI form factor, there is a connector on the top right corner of
the card for the SSI. Refer to section 2.3 for the connector posi­tion. All the SSI signals are routed to the 20-pin connector from the
FPGA. To synchronize multiple cards, users can connect a special
ribbon cable (ACL-SSI) to all the cards in a daisy-chain configura­tion.

Accept the SSI_TIMEBASE to replace the internal
TIMEBASE signal.

Accept the SSI_ADCONV to replace the internal
ADCONV signal.

Accept the SSI_SCAN_START to replace the internal
SCAN_START signal.

Accept the SSI_DAWR to replace the internal DAWR
signal.

82 Operation Theory

In PXI form factor, we utilize the PXI trigger bus built on the PXI
backplane to provide the necessary timing signal connections. All
the SSI signals are routed to the P2 connector. No additional cable
is needed. For detailed information of the PXI specifications, refer
to the PXI Specification Revision 2.0 from PXI System Alliance
(www.pxisa.org).

The six internal timing signals could be routed to the SSI or the
PXI trigger bus through software drivers. Refer to section 4.6 for
detailed information on the six internal timing signals. Physically,
the signal routings are accomplished in the FPGA. Cards that are
connected together through the SSI or the PXI trigger bus, will still
achieve synchronization on the six timing signals.

Operation Theory 83

The SSI/PXI Mechanism

We adopt master-slave configuration for SSI/PXI. In a system,
for each timing signal, there shall be only one master, and
other cards are SSI slaves or with SSI function disabled.

For each timing signal, the SSI master does not have to be in a
single card. For example:

We want to synchronize the A/D operation through the
ADCONV signal for four DAQ-/DAQe-/PXI-2204/2205/2206/
2208 cards. Card 1 is the master, and Card 2, 3, 4 are slaves.
Card 1 receives an external digital trigger to start the post trig­ger mode acquisition. The SSI setting could be:

X Set the SSI_ADCONV signal of Card 1 to be the master.

X Set the SSI_ADCONV signals of Card 2, 3, 4 to be the

slaves.

X Set external digital trigger for Card 1’s A/D operation.

X Set the SI_counter and the post scan counter (PSC) of all

other cards.

X Start DMA operations for all cards, so all the cards are wait-

ing for the trigger event.

When the digital trigger condition of Card 1 occurs, Card 1 will
internally generate the ADCONV signal and output this
ADCONV signal to SSI_ADCONV signal of Card 2, 3 and 4
through the SSI/PXI connectors. Thus we can achieve 16­channel acquisition simultaneously.

You could arbitrarily choose each of the six timing signals as
the SSI master from any one of the cards. The SSI master can
output the internal timing signals to the SSI slaves. With the
SSI, users could achieve better card-to-card synchronization.

Note that when power-up or reset, the DAQ timing signals are
reset to use the internal generated timing signals.

84 Operation Theory

5 Calibration

This chapter introduces the calibration process to minimize AD
measurement errors and DA output errors.

5.1 Loading Calibration Constants

The DAQ-/DAQe-/PXI-2204/2205/2206/2208 card is factory-cali­brated before shipment. The associated calibration constants of
the TrimDACs firmware to the onboard EEPROM. TrimDACs are
devices containing multiple DACs within a single package. Trim­DACs do not have memory capability. That means the calibration
constants do not retain their values after the system power is
turned off. Loading calibration constants is the process of loading
the values of TrimDACs firmware stored in the onboard EEPROM.
ADLINK provides a software utility that automatically reads the
calibration constants automatically, if necessary.

There is a dedicated space for storing calibration constants in the
EEPROM. In addition to the default bank of factory calibration con­stants, there is one user-utilization bank. This bank allows you to
load the TrimDACs firmware values either from the original factory
calibration or from a subsequently-performed calibration.

Because of the fact that measurements and outputs errors may
vary depending on time and temperature, it is recommended that
you calibrate the card when it is integrated in your computing envi­ronment. The auto-calibration function is presented in the follow­ing sections.

Calibration 85

5.2 Auto-calibration

Through the DAQ-/DAQe-/PXI-2204/2205/2206/2208 card auto­calibration feature, the calibration software measures and corrects
almost all calibration errors without any external signal connec­tions, reference voltage, or measurement devices.

The DAQ-/DAQe-/PXI-2204/2205/2206/2208 card comes with an
onboard calibration reference to ensure the accuracy of auto-cali­bration. The reference voltage is measured in the production line
through a digital potentiometer and compensated in the software.
The calibration constant is memorized after this measurement. We
do not recommended adjustment of the onboard calibration refer­ence except when an ultra-precision calibrator is available.

NOTES

• Warm the card up for at least 15 minutes before initiating auto-cal­ibration.

• Remove the cable before auto-calibrating the card since the DA
outputs are changed during the process.

5.3 Saving Calibration Constants

When auto-calibration is completed, you can save the new calibra­tion constants to the user-configurable banks in the EEPROM.
The date and the temperature when you ran auto-calibration is
saved with the calibration constants. You can store three sets of
calibration constants according to three different environments
and re-load the calibration constants later.

86 Calibration

Warranty Policy

Thank you for choosing ADLINK. To understand your rights and
enjoy all the after-sales services we offer, please read the follow­ing carefully.

1. Before using ADLINK’s products please read the user man­ual and follow the instructions exactly. When sending in
damaged products for repair, please attach an RMA appli­cation form which can be downloaded from: http://
rma.adlinktech.com/policy/.

2. All ADLINK products come with a limited two-year war­ranty, one year for products bought in China:

X The warranty period starts on the day the product is

shipped from ADLINK’s factory.

X Peripherals and third-party products not manufactured

by ADLINK will be covered by the original manufactur­ers' warranty.

X For products containing storage devices (hard drives,

flash cards, etc.), please back up your data before send­ing them for repair. ADLINK is not responsible for any
loss of data.

X Please ensure the use of properly licensed software with

our systems. ADLINK does not condone the use of
pirated software and will not service systems using such
software. ADLINK will not be held legally responsible for
products shipped with unlicensed software installed by
the user.

X For general repairs, please do not include peripheral

accessories. If peripherals need to be included, be cer­tain to specify which items you sent on the RMA Request
& Confirmation Form. ADLINK is not responsible for
items not listed on the RMA Request & Confirmation
Form.

Warranty Policy 87

3. Our repair service is not covered by ADLINK's guarantee
in the following situations:

X Damage caused by not following instructions in the

User's Manual.

X Damage caused by carelessness on the user's part dur-

ing product transportation.

X Damage caused by fire, earthquakes, floods, lightening,

pollution, other acts of God, and/or incorrect usage of
voltage transformers.

X Damage caused by unsuitable storage environments

(i.e. high temperatures, high humidity, or volatile chemi­cals).

X Damage caused by leakage of battery fluid during or

after change of batteries by customer/user.

X Damage from improper repair by unauthorized ADLINK

technicians.

X Products with altered and/or damaged serial numbers

are not entitled to our service.

X This warranty is not transferable or extendible.

X Other categories not protected under our warranty.

4. Customers are responsible for shipping costs to transport
damaged products to our company or sales office.

5. To ensure the speed and quality of product repair, please
download an RMA application form from our company web­site: http://rma.adlinktech.com/policy. Damaged products
with attached RMA forms receive priority.

If you have any further questions, please email our FAE staff:
[e-mail].

88 Warranty Policy