ADLINK PXI-2006 User Manual

DAQ/PXI-201x/200x

4-CH, Simultaneous, High Performance

Multi-Function Data Acquisition Card

User’s Manual

Manual Rev. 2.00

Revision Date: April 20, 2006

Part No: 50-11020-1030

Advance Technologies; Automate the World.

Copyright 2006 ADLINK TECHNOLOGY INC.

All Rights Reserved.

The information in this document is subject to change without prior
notice in order to improve reliability, design, and function and does
not represent a commitment on the part of the manufacturer.

In no event will the manufacturer be liable for direct, indirect, spe­cial, incidental, or consequential damages arising out of the use or
inability to use the product or documentation, even if advised of
the possibility of such damages.

This document contains proprietary information protected by copy­right. All rights are reserved. No part of this manual may be repro­duced by any mechanical, electronic, or other means in any form
without prior written permission of the manufacturer.

Trademarks

Product names mentioned herein are used for identification pur­poses only and may be trademarks and/or registered trademarks
of their respective companies.

Getting Service from ADLINK

Customer Satisfaction is top priority for ADLINK Technology Inc.
Please contact us should you require any service or assistance.

ADLINK TECHNOLOGY INC.

Web Site: http://www.adlinktech.com

Sales & Service: [e-mail]

TEL: [phone]

FAX: [phone]

Address: 9F, No. 166, Jian Yi Road, Chungho City,

Taipei, 235 Taiwan

Please email or FAX this completed service form for prompt and
satisfactory service.

Company Information

Company/Organization

Contact Person

E-mail Address

Address

Country

TEL FAX:

Web Site

Product Information

Product Model

OS:

Environment

M/B: CPU:
Chipset: Bios:

Please give a detailed description of the problem(s):

Table of Contents

1 Introduction ........................................................................ 1

1.1 Features............................................................................... 2

1.2 Applications ......................................................................... 3

1.3 Specifications....................................................................... 4

1.4 Software Support ............................................................... 13

Programming Library .................................................... 13

DAQ-LVIEW PnP: LabVIEW® Driver ........................... 13

D2K-OCX: ActiveX Controls ......................................... 14

2 Installation ........................................................................ 15

2.1 Contents of Package ......................................................... 15

2.2 Unpacking.......................................................................... 15

2.3 DAQ/PXI-20XX Layout ...................................................... 17

2.4 PCI Configuration .............................................................. 18

3 Signal Connections.......................................................... 19

3.1 Connectors Pin Assignment .............................................. 19

3.2 Analog Input Signal Connection ........................................ 24

Types of signal sources ................................................ 24

Single-Ended Measurements ....................................... 24

Differential Measurements ............................................ 25

4 Operation Theory ............................................................. 27

4.1 A/D Conversion.................................................................. 27

DAQ/PXI-2010 AI Data Format ..................................... 28

DAQ/PXI-2005/2006/2016 AI Data Format ................... 30

Software conversion with polling data transfer acqui-sition

mode (Software Polling) ..................................... 30

Programmable scan acquisition mode .......................... 31

Trigger Modes ............................................................... 33

4.2 D/A Conversion.................................................................. 42

Software Update ........................................................... 43

Timed Waveform Generation ........................................ 44

Trigger Modes ............................................................... 45

4.3 Digital I/O ........................................................................... 51

4.4 General Purpose Timer/Counter Operation....................... 52

Timer/Counter functions basics .................................... 52

General Purpose Timer/Counter modes ....................... 53

Table of Contents i

4.5 Trigger Sources ................................................................. 57

Software-Trigger ........................................................... 57

External Analog Trigger ................................................ 57

4.6 User-controllable Timing Signals ....................................... 61

DAQ timing signals ....................................................... 63

Auxiliary Function Inputs (AFI) ...................................... 64

System Synchronization Interface ................................ 67

AI_Trig_Out and AO_Trig_Out ..................................... 69

5 Calibration ......................................................................... 71

5.1 Loading Calibration Constants........................................... 71

5.2 Auto-calibration .................................................................. 71

5.3 Saving Calibration Constants............................................. 72

ii Table of Contents

List of Tables

Table 1-1: -3dB small signal bandwidth ..................................... 5

Table 1-2: System Noise ........................................................... 5

Table 1-3: CMRR: (DC to 60Hz) ................................................ 7

Table 3-1: 68-pin VHDCI-type pin assignment ........................ 19

Table 3-2: 68-pin VHDCI-type Connector Legend ................... 20

Table 3-3: SSI connector (JP3) pin assignment for DAQ-20XX 22

Table 3-4: Legend of SSI connector ........................................ 22

Table 4-1: Bipolar analog input range and the output digital code on

DAQ/PXI-2010 (Note that the last 2 digital codes are

SDI<1..0>) .............................................................. 29

Table 4-2: Unipolar analog input range and the output digital code

on DAQ/PXI-2010 (Note that the last 2 digital codes are

SDI<1..0>) .............................................................. 29

Table 4-3: Bipolar analog input range and the output digital code on

the DAQ/PXI-2005/2006/2016 ................................ 30

Table 4-4: Unipolar analog input range and the output digital code

on the DAQ/PXI-2005/2006/2016 ........................... 30

Table 4-5: Bipolar output code table (Vref=10V if internal reference

is selected) ............................................................. 43

Table 4-6: Unipolar output code table (Vref=10V if internal reference

is selected) ............................................................. 43

Table 4-7: Analog trigger SRC1 (EXTATRIG) ideal transfer charac-

teristic ..................................................................... 58

Table 4-8: Summary of user-controllable timing signals and the cor-

responding functionalities ....................................... 62

Table 4-9: Auxiliary function input signals and the corresponding

functionalities .......................................................... 65

Table 4-10: Summary of SSI timing signals and the corresponding

functionalities as the master or slave ..................... 67

List of Tables iii

List of Figures

Figure 2-1: PCB Layout of the DAQ-20XX................................. 17

Figure 2-2: PCB Layout of the PXI-20XX................................... 17

Figure 3-1: Single-Ended connections ....................................... 25

Figure 3-2: Ground-referenced source and differential input ..... 25

Figure 3-3: Floating source and differential input....................... 26

Figure 4-1: Synchronous Digital Inputs Block Diagram.............. 28

Figure 4-2: Synchronous Digital Inputs timing ........................... 28

Figure 4-3: Scan Timing............................................................. 32

Figure 4-4: Pre-trigger (trigger occurs after at least M scans ac-

quired) ..................................................................... 34

Figure 4-5: Pre-trigger scan acquisition (trigger occurs when a con-

version is in progress).............................................. 34

Figure 4-6: Pre-trigger with M_enable = 0 (Trigger occurs before M

scans) ...................................................................... 35

Figure 4-7: Pre-trigger with M_enable = 1 ................................. 35

Figure 4-8: Middle trigger with M_enable = 1............................. 36

Figure 4-9: Middle trigger (trigger occurs when a scan is in progress)

37

Figure 4-10: Post trigger .............................................................. 38

Figure 4-11: Delay trigger ............................................................ 39

Figure 4-12: Post trigger with re-trigger ....................................... 40

Figure 4-13: Scatter/gather DMA for data transfer....................... 42

Figure 4-14: Typical D/A timing of waveform generation (Assuming

the data in the data buffer are 2V, 4V, -4V, 0V)....... 45

Figure 4-15: Post trigger waveform generation (Assuming the data in

the data buffer are 2V, 4V, 6V, 3V, 0V, -4V, -2V, 4V) 46
Figure 4-16: Delay trigger waveform generation (Assuming the data in

the data buffer are 2V, 4V, 6V, 3V, 0V, -4V, -2V, 4V) 47
Figure 4-17: Re-triggered waveform generation (Assuming the data in

the data buffer are 2V, 4V, 2V, 0V).......................... 47

Figure 4-18: Finite iterative waveform generation with Post-trigger and

DLY2_Counter = 0 (Assuming the data in the data buffer

are 2V, 4V, 2V, 0V).................................................. 48

Figure 4-19: Infinite iterative waveform generation with Post-trigger

and DLY2_Counter = 0 (Assuming the data in the data

buffer are 2V, 4V, 2V, 0V)........................................ 49

Figure 4-20: Stop mode I (Assuming the data in the data buffer are 2V,

4V, 2V, 0V) .............................................................. 50

iv List of Figures

Figure 4-21: Stop mode II ............................................................ 51

Figure 4-22: Stop mode III ........................................................... 51

Figure 4-23: Mode 1 Operation.................................................... 53

Figure 4-24: Mode 2 Operation.................................................... 54

Figure 4-25: Mode 3 Operation.................................................... 54

Figure 4-26: Mode 4 Operation.................................................... 55

Figure 4-27: Mode 5 Operation.................................................... 55

Figure 4-28: Mode 6 Operation.................................................... 56

Figure 4-29: Mode 7 Operation.................................................... 56

Figure 4-30: Mode 8 Operation.................................................... 57

Figure 4-31: Analog trigger block diagram................................... 58

Figure 4-32: Below-Low analog trigger condition......................... 59

Figure 4-33: Above-High analog trigger condition ....................... 59

Figure 4-34: Inside-Region analog trigger condition .................... 60

Figure 4-35: High-Hysteresis analog trigger condition................. 60

Figure 4-36: Low-Hysteresis analog trigger condition.................. 61

Figure 4-37: External digital trigger.............................................. 61

Figure 4-38: DAQ signals routing................................................. 62

List of Figures v

1 Introduction

The DAQ/PXI-20XX is an advanced data acquisition card based
on the 32-bit PCI architecture. High performance designs and the
state-of-the-art technology make this card ideal for data logging
and signal analysis ap-plications in medical, process control, etc.

Introduction 1

1.1 Features

The DAQ/PXI-20XX Advanced Data Acquisition Card provides the
fol-lowing advanced features:

X 32-bit PCI-Bus, plug and play

X 4-channel simultaneous differential analog inputs

X DAQ/PXI-2010: 14-bit Analog input resolution with sampling

rate up to 2MS/s

X DAQ/PXI-2005: 16-bit Analog input resolution with sampling

rate up to 500KS/s

X DAQ/PXI-2006: 16-bit Analog input resolution with sampling

rate up to 250KS/s

X DAQ/PXI-2016: 16-bit Analog input resolution with sampling

rate up to 800kS/s

X Programmable bipolar/unipolar analog input

X Programmable gain (x1, x2, x4, x8 for all DQ-20XX)

X DAQ/PXI-2010: Total 8K samples A/D FIFO

X DAQ/PXI-2005/2006/2016: Total 512 samples A/D FIFO

X Versatile trigger sources: software trigger, external digital

trigger, analog trigger and trigger from System Synchroniza­tion Interface (SSI).

X A/D Data transfer: software polling & bus-mastering DMA

with Scatter/Gather functionality

X Four A/D trigger modes: post-trigger, delay-trigger, pre-trig-

ger and middle-trigger

X 2 channel DA outputs with waveform generation capability

X 2K samples output data FIFO for DA channels

X DA Data transfer: software update and bus-mastering DMA

with Scatter/Gather functionality

X System Synchronization Interface (SSI)

X A/D/DA fully auto-calibration

X Completely jumper-less and software configurable

2Introduction

1.2 Applications

X Automotive Testing

X Cable Testing

X Transient signal measurement

X ATE

X Laboratory Automation

X Biotech measurement

Introduction 3

1.3 Specifications

Analog Input (AI)

X Number of channels: 4 differential

X A/D converter:

Z 2010: LTC1414 or equivalent

Z 2005: A/D7665 or equivalent

Z 2006: A/D7663 or equivalent

Z 2016: A/D7671 or equivalent

X Max sampling rate:

Z 2010: 2MS/s

Z 2016: 800kS/s

Z 2005: 500kS/s

Z 2006: 250kS/s

X Resolution:

Z 2010: 14 bits, no missing code

Z 2005/2006/2016:16 bits, no missing code

X FIFO buffer size:

Z 2010:8K samples

Z 2005/2006/2016: 512 samples

X Programmable input range:

Z Bipolar: ±10V, ±5V, ±2.5V, ±1.25V

Z Unipolar: 0~10V, 0~5V, 0~2.5V, 0~1.25V

X Operational common mode voltage range: ±11V

X Overvoltage protection:

Z Power on: continuous ±30V

Z Power off: continuous ±15V

X Input impedance: 1GΩ/100pF

4Introduction

X -3dB small signal bandwidth: (Typical, 25°C)

Device Input Range Bandwidth (-3dB) Input Range Bandwidth (-3dB)

±10V 1170 kHz 0~10V 1090 kHz

2010

±5V 1050 kHz 0~5V 1020 kHz

±2.5V 800 kHz 0~2.5V 790 kHz

±1.25V 530 kHz 0~1.25V 530 kHz

±10V 1160 kHz 0~10V 1210 kHz

2005

±5V 1050 kHz 0~5V 1050 kHz

±2.5V 780 kHz 0~2.5V 770 kHz

±1.25V 520 kHz 0~1.25V 530 kHz

±10V 630 kHz 0~10V 640 kHz

2006

±5V 620 kHz 0~5V 620 kHz

±2.5V 540 kHz 0~2.5V 540 kHz

±1.25V 410 kHz 0~1.25V 420 kHz

±10V 840kHz 0~10V 900kHz

2016

±5V 825kHz 0~5V 800kHz

±2.5V 710kHz 0~2.5V 690kHz

±1.25V 530kHz 0~1.25V 530kHz

Table 1-1: -3dB small signal bandwidth

X Large signal bandwidth (1% THD): 300 kHz

X System Noise: (Typical)

Device Input Range System noise Input Range System noise

±10V 0.6 LSBrms 0~10V 0.8 LSBrms

2010

±5V 0.6 LSBrms 0~5V 0.8 LSBrms

±2.5V 0.6 LSBrms 0~2.5V 0.9 LSBrms

±1.25V 0.6 LSBrms 0~1.25V 0.9 LSBrms

±10V 1.2 LSBrms 0~10V 1.9 LSBrms

2005

±5V 1.2 LSBrms 0~5V 2.0 LSBrms

±2.5V 1.3 LSBrms 0~2.5V 2.1 LSBrms

±1.25V 1.3 LSBrms 0~1.25V 2.2 LSBrms

Table 1-2: System Noise

Introduction 5

Device Input Range System noise Input Range System noise

±10V 1.0 LSBrms 0~10V 1.5 LSBrms

2006

2016

±5V 1.0 LSBrms 0~5V 1.6 LSBrms

±2.5V 1.1 LSBrms 0~2.5V 1.7 LSBrms

±1.25V 1.1 LSBrms 0~1.25V 1.8 LSBrms

±10V 1.6 LSBrms 0~10V 2.9 LSBrms

±5V 1.8 LSBrms 0~5V 3.2 LSBrms

±2.5V 1.8 LSBrms 0~2.5V 3.2 LSBrms

±1.25V 1.9 LSBrms 0~1.25V 3.4 LSBrms

Table 1-2: System Noise

6Introduction

X CMRR: (DC to 60Hz, Typical)

Device Input Range CMRR Input Range CMRR

±10V 90 dB 0~10V 89 dB

2010

±5V 92 dB 0~5V 92 dB

±2.5V 95 dB 0~2.5V 94 dB

±1.25V 97 dB 0~1.25V 97 dB

±10V 86 dB 0~10V 85 dB

2005

±5V 88 dB 0~5V 88 dB

±2.5V 91 dB 0~2.5V 90 dB

±1.25V 93 dB 0~1.25V 93 dB

±10V 87 dB 0~10V 86 dB

2006

±5V 89 dB 0~5V 88 dB

±2.5V 91 dB 0~2.5V 91 dB

±1.25V 93 dB 0~1.25V 93 dB

±10V 85dB 0~10V 86dB

2016

±5V 88dB 0~5V 88dB

±2.5V 91dB 0~2.5V 92dB

±1.25V 95dB 0~1.25V 95dB

Table 1-3: CMRR: (DC to 60Hz)

X Time-base source:

Z Internal 40MHz or External clock Input (fmax: 40MHz,

fmin: 1MHz, 50% duty cycle)

X Trigger modes:

Z Post-trigger, Delay-trigger, Pre-trigger and Middle-trigger

X Data transfers:

Z Programmed I/O, and bus-mastering DMA with scatter/

gather

X Input coupling: DC

X Offset error:

Z Before calibration: ±60mV max

Z After calibration: ±1mV max

X Gain error:

Introduction 7

Z Before calibration: ±0.6% of output max

Z After calibration: ±0.1% of output max for DAQ/PXI-

2010, ±0.03% of output max for DAQ/PXI-2005/2006/
2016

8Introduction

Analog Output (AO)

X Number of channels: 2 channel voltage output

X DA converter: LTC7545 or equivalent

X Max update rate: 1MS/s

X Resolution: 12 bits

X FIFO buffer size:

Z 1k samples per channel when both channels are

enabled for timed DA output, and 2k samples when only

one channel is used for timed DA output

X Data transfers:

Z Programmed I/O, and bus-mastering DMA with scatter/

gather

X Output range:

Z Bipolar: ±10V or ±AOEXTREF

Z Unipolar: 0~10V or 0~AOEXTREF

X Settling time: 3µS to 0.5 LSB accuracy

X Slew rate: 20V/µS

X Output coupling: DC

X Protection: Short-circuit to ground

X Output impedance: 0.3Ω typical

X Output driving current: ±5mA max.

X Stability: Any passive load, up to 1500pF

X Power-on state: 0V steady-state

X Power-on glitch: ±1.5V/500uS

X Relative accuracy:

Z ±0.5 LSB typical, ±1 LSB max

X DNL:

Z ±0.5 LSB typical, ±1.2 LSB max

X Offset error:

Z Before calibration: ±80mV max

Z After calibration: ±1mV max

X Gain error:

Introduction 9

Z Before calibration: ±0.8% of output max

Z After calibration: ±0.02% of output max

X General Purpose Digital I/O (G.P. DIO, 82C55A)

X Number of channels: 24 programmable Input/Output

X Compatibility: TTL/CMOS

X Input voltage:

Z Logic Low: VIL=0.8V max; IIL=0.2mA max.

Z High: VIH=2.0V max; IIH=0.02mA max

X Output voltage:

Z Low: VOL=0.5V max; IOL=8mA max.

Z High: VOH=2.7V min; IOH=400µA

X Synchronous Digital Inputs (SDI, for DAQ/PXI-2010 only)

X Number of channels: 8 digital inputs sampled simulta-

neously with the analog signal input

X Compatibility: TTL/CMOS

X Input voltage:

Z Logic Low: VIL=0.8V max; IIL=0.2mA max.

Z Logic High: VIH=2.7V min; IIL=0.02mA max.

General Purpose Timer/Counter (GPTC)

X Number of channel: 2 Up/Down Timer/Counters

X Resolution: 16 bits

X Compatibility: TTL

X Clock source: Internal or external

X Max source frequency: 10MHz

10 Introduction

Analog Trigger (A.Trig)

X Source:

Z All analog input channels; external analog trigger

(EXTATRIG)

X Level: ±Full-scale, internal; ±10V external

X Resolution: 8 bits

X Slope: Positive or negative (software selectable)

X Hysteresis: Programmable

X Bandwidth: 400khz

External Analog Trigger Input (EXTATRIG)

X Input Impedance:

Z 40kΩ for DAQ/PXI-2010

Z 2kΩ for DAQ/PXI-2005/2006/2016

X Coupling: DC

X Protection: Continuous ±35V maximum

Digital Trigger (D.Trig)

X Compatibility: TTL/CMOS

X Response: Rising or falling edge

X Pulse Width: 10ns min

System Synchronous Interface (SSI)

X Trigger lines: 7

Stability

X Recommended warm-up time: 15 minutes

X On-board calibration reference:

Z Level: 5.000V

Z Temperature coefficient: ±2ppm/°C

Z Long-term stability: 6ppm/1000Hr

Introduction 11

Physical

X Dimensions:

Z 175mm by 107mm for DAQ-20XX

Z Standard CompactPCI form factor for PXI-20XX

X I/O connector: 68-pin female VHDCI type (e.g. AMP-

787254-1)

Power Requirement (typical)

X +5VDC: 1.82 A for DAQ/PXI-2010

Z 2.04 A for DAQ/PXI-2005

Z 1.82 A for DAQ/PXI-2006

Z 2.52 A for DAQ/PXI-2016

Operating Environment

X Ambient temperature: 0 to 55°C

X Relative humidity: 10% to 90% non-condensing

Storage Environment

X Ambient temperature: -20 to 80°C

X Relative humidity: 5% to 95% non-condensing

Interface Connector: 68-pin AMP-787254-1 or equivalent

12 Introduction

1.4 Software Support

ADLINK provides versatile software drivers and packages for
users’ dif-ferent approach to building up a system. ADLINK not
only provides pro-gramming libraries such as DLL for most Win­dows based systems, but also provide drivers for other software
packages such as LabVIEW®.

All software options are included in the ADLINK CD. Non-free soft­ware drivers are protected with licensing codes. Without the soft­ware code, you can install and run the demo version for two hours
for trial/demonstration purposes. Please contact ADLINK dealers
to purchase the formal license.

Programming Library

For customers who are writing their own programs, we provide
function libraries for many different operating systems, including:

X D2K-DASK: Include device drivers and DLL for Windows

98/NT/2000/XP. DLL is binary compatible across Windows
98/NT/2000/XP. This means all applications developed with
D2K-DASK are compatible across Windows 98/NT/2000/
XP. The developing environment can be VB, VC++, Delphi,
BC5, or any Windows programming language that allows
calls to a DLL. The user’s guide and function reference
manual of D2K-DASK are in the CD. (\\Manual\Software
Package\D2K-DASK)

X D2K-DASK/X: Include device drivers and shared library for

Linux. The developing environment can be Gnu C/C++ or
any program-ming language that allows linking to a shared
library. The user's guide and function reference manual of
D2K-DASK/X are in the CD. (\\Manual\Software Pack­age\D2K-DASK-X.)

DAQ-LVIEW PnP: LabVIEW® Driver

DAQ-LVIEW PnP contains the VIs, which are used to interface
with NI’s LabVIEW® software package. The DAQ-LVIEW PnP
supports Windows 98/NT/2000/XP. The LabVIEW® drivers is
shipped free with the card. You can install and use them without a

Introduction 13

license. For detailed information about DAQ-LVIEW PnP, please
refer to the user’s guide in the CD.

(\\Manual\Software Package\DAQ-LVIEW PnP)

D2K-OCX: ActiveX Controls

We suggest customers who are familiar with ActiveX controls and
VB/VC++ programming use D2K-OCX ActiveX control component
libraries for developing applications. D2K-OCX is designed for
Windows 98/NT/2000/XP. For more detailed information about
D2K-OCX, please refer to the user's guide in the CD.

(\\Manual\Software Package\D2K-OCX)

The above software drivers are shipped with the card. Please refer
to the “Software Installation Guide” in the package to install these
drivers.

In addition, ADLINK supplies ActiveX control software DAQBench.
DAQBench is a collection of ActiveX controls for measurement or
auto-mation applications. With DAQBench, you can easily develop
custom user interfaces to display your data, analyze data you
acquired or received from other sources, or integrate with popular
applications or other data sources. For more detailed information
about DAQBench, please refer to the user's guide in the CD.

(\\Manual\Software Package\DAQBench Evaluation)

You can also get a free 4-hour evaluation version of DAQBench
from the CD.

DAQBench is not free. Please contact ADLINK dealer or ADLINK
to pur-chase the software license.

14 Introduction

2 Installation

This chapter describes how to install the DAQ/PXI-20XX. The con­tents of the package and unpacking information that you should be
aware of are outlined first.

The DAQ/PXI-20XX performs an automatic configuration of the
IRQ, and port address. Users can use software utility, PCI_SCAN
to read the system configuration.

2.1 Contents of Package

In addition to this User's Guide, the package should include the
following items:

X DAQ/PXI-20XX Multi-function Data Acquisition Card

X ADLINK All-in-one Compact Disc

X Software Installation Guide

If any of these items are missing or damaged, contact the dealer
from whom you purchased the product. Save the shipping materi­als and carton in case you want to ship or store the product in the
future.

2.2 Unpacking

Your DAQ/PXI-20XX SERIES card contains electro-static sensi­tive com-ponents that can be easily be damaged by static electric­ity.

Therefore, the card should be handled on a grounded anti-static
mat. The operator should be wearing an anti-static wristband,
grounded at the same point as the anti-static mat.

Inspect the card module carton for obvious damages. Shipping
and han-dling may cause damage to your module. Be sure there
are no shipping and handling damages on the modules carton
before continuing.

After opening the card module carton, extract the system module
and place it only on a grounded anti-static surface with component
side up.

Installation 15

Again, inspect the module for damages. Press down on all the
socketed IC's to make sure that they are properly seated. Do this
only with the module place on a firm flat surface.

You are now ready to install your DAQ/PXI-20XX.

Note: DO NOT APPLY POWER TO THE CARD IF IT HAS BEEN

DAMAGED.

16 Installation

2.3 DAQ/PXI-20XX Layout

Figure 2-1: PCB Layout of the DAQ-20XX

Figure 2-2: PCB Layout of the PXI-20XX

Installation 17

2.4 PCI Configuration

1. Plug and Play:

As a plug and play component, the card requests an interrupt
number via its PCI controller. The system BIOS responds with
an interrupt assignment based on the card information and on
known system parameters. These system parameters are
determined by the installed drivers and the hardware load seen
by the system.

2. Configuration:

The board configuration is done on a board-by-board basis for
all PCI boards on your system. Because configuration is con­trolled by the system and software, there is no jumper setting
required for base-address, DMA, and interrupt IRQ.

The configuration is subject to change with every boot of the
sys-tem as new boards are added or removed.

3. Troubleshooting:

If your system doesn’t boot or if you experience erratic opera­tion with your PCI board in place, it’s likely caused by an inter­rupt con-flict (perhaps the BIOS Setup is incorrectly
configured). In general, the solution, once you determine it is
not a simple oversight, is to consult the BIOS documentation
that comes with your system.

18 Installation

3 Signal Connections

This chapter describes the connectors of the DAQ/PXI-20XX, and
the signal connection between the DAQ/PXI-20XX and external
devices.

3.1 Connectors Pin Assignment

The DAQ/PXI-20XX is equipped with one 68-pin VHDCI-type con­nector (AMP-787254-1). It is used for digital input/output, analog
input / output, and timer/counter signals, etc. One 20-pin ribbon
male connector is used for SSI (System Synchronous Interface) in
DAQ-20XX. The pin assign-ments of the connectors are defined in
Table 3-1 and Table 3-2.

CH0+ 1 35 CH0-

CH1+ 2 36 CH1-

CH2+ 3 37 CH2-

CH3+ 4 38 CH3-

EXTATRIG 5 39 AIGND

DA1OUT 6 40 AOGND

DA0OUT 7 41 AOGND

AOEXTREF 8 42 AOGND

SDI3_1 / NC* 9 43 SDI3_0 / NC*

SDI2_1 / NC* 10 44 SDI2_0 / NC*

SDI1_1 / NC* 11 45 SDI1_0 / NC*

SDI0_1 / NC* 12 46 SDI0_0 / NC*

AO_TRIG_OUT 13 47 EXTWFTRG

AI_TRIG_OUT 14 48 EXTDTRIG

GPTC1_SRC 15 49 DGND

GPTC0_SRC 16 50 DGND

GPTC0_GATE 17 51 GPTC1_GATE

GPTC0_OUT 18 52 GPTC1_OUT

GPTC0_UPDOWN 19 53 GPTC1_UPDOWN

EXTTIMEBASE 20 54 DGND

AFI1 21 55 AFI0

Table 3-1: 68-pin VHDCI-type pin assignment

Signal Connections 19

PB7 22 56 PB6

PB5 23 57 PB4

PB3 24 58 PB2

PB1 25 59 PB0

PC7 26 60 PC6

PC5 27 61 PC4

DGND 28 62 DGND

PC3 29 63 PC2

PC1 30 64 PC0

PA7 31 65 PA6

PA5 32 66 PA4

PA3 33 67 PA2

PA1 34 68 PA0

Table 3-1: 68-pin VHDCI-type pin assignment

* SDI for DAQ/PXI-2010 only; NC for DAQ/PXI-2005/2006/2016

Legend:

Pin # Signal Name Reference Direction Description

Differential posi-

1~4 CH<0..3>+ CH0<0..3>- Input

5 EXTATRIG AIGND Input

6 DA0OUT AOGND Output AO channel 0

7 DA1OUT AOGND Output AO channel 1

8 AOEXTREF AOGND Input

9~12

13 AO_TRIG_OUT DGND Output AO trigger signal

14 AI_TRIG_OUT DGND Output AI trigger signal

15,16 GPTC<0,1>_SRC DGND Input

SDI<3..0>_1 (2010)

NC (2005/2006/2016)

Table 3-2: 68-pin VHDCI-type Connector Legend

DGND Input

tive input for AI
channel <0..3>

External AI ana-

log trigger

External refer-

ence for AO

channels

Synchronous dig-

ital inputs

Source of

GPTC<0,1>

20 Signal Connections

Pin # Signal Name Reference Direction Description

17,51 GPTC<0,1>_GATE DGND Input

18,52 GPTC<0,1>_OUT DGND Input

19,53 GPTC<0,1>_UPDOWN DGND Input

20 EXTTIMEBASE DGND Input

21,28,49,50,54,62 DGND -------- -------- Digital ground

22,56,23,57,24,58,25,59 PB<7,0> DGND PIO*

26,60,27,61,29,63,30,64 PC<7,0> DGND PIO*

31,65,32,66,33,67,34,68 PA<7,0> DGND PIO*

35~38 CH<0..3>- -------- Input

39 AIGND -------- --------

40~42 AOGND -------- --------

43~46

47 EXTWFTRIG DGND Input

trigger

48 EXTDTRIG DGND Input

55 AFI0 DGND Input

SDI<3..0>_0 (2010)

NC (2005/2006/2016)

Table 3-2: 68-pin VHDCI-type Connector Legend

DGND Input

Gate of

GPTC<0,1>

Output of

GPTC<0,1>

Up/Down of
GPTC<0,1>

External TIME-

BASE

Programmable

DIO pins of 8255

Port B

Programmable

DIO pins of 8255

Port C

Programmable

DIO pins of 8255

Port A

Differential nega-

tive input for AI
channel <0..3>

Analog ground

for AI

Analog ground

for AO

Synchronous dig-

ital inputs

External AO

waveform

External AI digital

trigger

Auxiliary Func-

tion Input 0

(ADCONV,

AD_START)

Signal Connections 21

Pin # Signal Name Reference Direction Description

Auxiliary Func-

21 AFI1 DGND Input

Table 3-2: 68-pin VHDCI-type Connector Legend

tion Input 1

(DAWR,

DA_START)

*PIO means programmable I/O

SSI_TIMEBASE 1 2 DGND

SSI_ADCONV 3 4 DGND

SSI_DAWR 5 6 DGND

SSI_SCAN_START 7 8 DGND

RESERVED 9 10 DGND

SSI_AD_TRIG 11 12 DGND

SSI_DA_TRIG 13 14 DGND

RESERVED 15 16 DGND

RESERVED 17 18 DGND

RESERVED 19 20 DGND

Table 3-3: SSI connector (JP3) pin assignment for DAQ-20XX

Legend:

SSI timing signal Functionality

SSI master: send the TIMEBASE out

SSI_TIMEBASE

SSI_ADCONV

SSI_SCAN_START

SSI_AD_TRIG

Table 3-4: Legend of SSI connector

SSI slave: accept the SSI_TIMEBASE to

replace the internal TIMEBASE signal.

SSI master: send the ADCONV out

SSI slave: accept the SSI_ADCONV to

replace the internal ADCONV signal.

SSI master: send the SCAN_START out

SSI slave: accept the SSI_SCAN_START to

replace the internal SCAN_START signal.

SSI master: send the internal AD_TRIG out
SSI slave: accept the SSI_AD_TRIG as the

digital trigger signal.

22 Signal Connections

SSI timing signal Functionality

SSI master: send the DAWR out.

SSI_DAWR

SSI_DA_TRIG

Table 3-4: Legend of SSI connector

SSI slave: accept the SSI_DAWR to replace

the internal DAWR signal.

SSI master: send the DA_TRIG out.

SSI slave: accept the SSI_DA_TRIG as the

digital trigger signal.

Signal Connections 23

3.2 Analog Input Signal Connection

The DAQ/PXI-20XX provides 4 differential analog input channels.
The analog signal can be converted to digital values by the A/D
converter. To avoid ground loops and get more accurate measure­ments from the A/D conversion, it is quite important to understand
the signal source type and how to connect the analog input sig­nals.

Types of signal sources

Ground-Referenced Signal Sources

A ground-referenced signal means it is connected in some way
to the building system. That is, the signal source is already
connected to a common ground point with respect to the DAQ/
PXI-20XX, assuming that the computer is plugged into the
same power system. Non- isolated out-puts of instruments and
devices that plug into the buildings power system are ground­referenced signal sources.

Floating Signal Sources

A floating signal source means it is not connected in any way to
the buildings ground system. A device with an isolated output is
a floating signal source, such as optical isolator outputs, trans­former outputs, and thermocouples.

Single-Ended Measurements

For single-ended connection, the analog input signal is referenced
to the common ground of the system. In this case, all the negative
ends of analog input channels should be connected to the AIGND
on the connector in-stead of floating. Please refer to the Figure 3-

1.

24 Signal Connections

Figure 3-1: Single-Ended connections

In single-ended configurations, more electrostatic and magnetic
noise couples into the single connections than in differential con­figurations. Therefore, the single-ended connection is not recom­mended unless minimal wire connections are necessary.

Differential Measurements

Differential Connection for Grounded-Reference Signal
Sources

The differential analog input provides two inputs that respond
to the signal voltage difference between them. If the signal
source is ground-referenced, the differential mode can be used
for the common-mode noise rejection. Figure 3-2 shows the
connection of ground-referenced signal sources under the dif­ferential input mode.

Figure 3-2: Ground-referenced source and differential input

Signal Connections 25

Differential Connection for Floating Signal Sources

Figure 3-3 shows how to connect a floating signal source to
DAQ/PXI-20XX in differential input mode. For floating signal
sources, you need to add a resistor at each channel to provide
a bias return path. The resistor value should be about 100
times the equivalent source impedance. If the source imped­ance is less than 100ohms, you can simply connect the nega­tive side of the signal to AGND as well as the negative input of
the Instru-mentation Amplifier, without any resistors at all. In
differential input mode, less noise couples into the signal con­nections than in single-ended mode.

Figure 3-3: Floating source and differential input

26 Signal Connections

4 Operation Theory

The operation theory of the functions on the DAQ/PXI-20XX is
described in this chapter. The functions include the A/D conver­sion, D/A conversion, Digital I/O and General Purpose Counter/
Timer. The operation theory can help you understand how to con­figure and program the DAQ/PXI-20XX.

The whole DAQ/PXI-2000 series cards, including DAQ/PXI-20XX,
DAQ/PXI-22XX and DAQ/PXI-25XX, are designed based on the
same logic-timing template of DAQ/PXI-22XX. In the DAQ/PXI­22XX cards, all the A/D related timings are for multiplexing A/D
sampling based on scan-ning, so that DAQ/PXI-20XX also adopts
the same concept, except there is only one conversion signal in a
scan which could generate up to 4 samples from the different 4
channels at the same time. In the following description, to conform
to the original timing design, we still use “scan” as the unit of A/D
data acquisition. All the DA and GPTC functions are the same in
DAQ/PXI-20XX and DAQ/PXI-22XX, while DAQ/PXI-25XX pro­vides im-proved DA timing comparing the former 2 series.

4.1 A/D Conversion

When using an A/D converter, users should first know about the
properties of the signal to be measured. Users can decide which
channel to use and where to connect the signals to the card.
Please refer to 3.2 for signal connections. In addition, users
should define and control the A/D signal configurations, including
channels, gains, and A/D signal types.

There are 2 ways to initiate A/D conversion, either by Software
Polling or Programmable Scan Acquisition; these are described
below.

The A/D acquisition is initiated by a trigger source; users must
decide how to trigger the A/D conversion. The data acquisition will
start once a trigger condition is matched.

After the end of A/D conversion, the A/D data is buffered in a Data
FIFO. The A/D data should be transferred into the PC's memory
for further processing.

Operation Theory 27

DAQ/PXI-2010 AI Data Format

Synchronous Digital Inputs (for DAQ/PXI-2010 only)

When each A/D conversion is completed, the 14-bits converted
digital data accompanied with 2 bits of SDI<1..0>_X per chan­nel from J5 will be latched into the 16-bit register and data
FIFO, as shown in Figure 8 and Figure 9. Therefore, users can
simultaneously sample one analog signal with four digital sig­nals. The data format of every acquired 16-bit data is as fol­lows:

D13, D12, D11 ....... D1, D0, b1, b0

Where

D13, D12, D11 ....... D1, D0: 2’s complement A/D

14-bit data

b1, b0: Synchronous Digital Inputs SDI<1..0>

Figure 4-1: Synchronous Digital Inputs Block Diagram

Figure 4-2: Synchronous Digital Inputs timing

Note: Since the analog signal is sampled when an A/D conversion

starts (falling edge of A/D_conversion signal), while
SDI<1..0> are sam-pled right after an A/D conversion com­pletes (rising edge of nADBUSY signal). Precisely SDI<1..0>
are sampled within 220 to 400ns lag to the analog signal,

28 Operation Theory

due to the variation of the conver-sion time of the A/D con-

verters.

Table 4-1 and 4-2 illustrate the ideal transfer characteristics of var­ious input ranges of DAQ\PXI-20XX. The converted digital codes
for DAQ\PXI-2010 are 14-bit and 2’s complement, and here we
present the codes as hexa-decimal numbers. Note that the last 2
bits of the transferred data, which are the synchronous digital input
(SDI), should be ignored when retrieving the analog data.

Description Bipolar Analog Input Range Digital code

Full-scale Range ±10V ±5V ±2.5V ±1.25V

Least significant bit 1.22mV 0.61mV 0.305mV 0.153mV

FSR-1LSB 9.9988V 4.9994V 2.4997V 1.2499V 1FFF

Midscale +1LSB 1.22mV 0.61mV 0.305mV 0.153mV 0001

Midscale 0V 0V 0V 0V 0000

Midscale –1LSB -1.22mV -0.61mV -0.305mV -0.153mV 3FFF

-FSR -10V -5V -2.5V -1.25V 2000

Table 4-1: Bipolar analog input range and the output digital code on DAQ/

PXI-2010 (Note that the last 2 digital codes are SDI<1..0>)

Description Unipolar Analog Input Range Digital code

Full-scale Range 0V to 10V 0 to +5V 0 to +2.5V 0 to +1.25V

Least significant bit 0.61mV 0.305mV 0.153mV 76.3uV

FSR-1LSB 9.9994V 4.9997V 2.9999V 1.2499V 1FFF

Midscale +1LSB 5.00061V 2.50031V 1.25015V 625.08mV 0001

Midscale 5V 2.5V 1.25V 625mV 0000

Midscale –1LSB 4.99939V 2.49970V 1.24985V 624.92mV 3FFF

-FSR 0V 0V 0V 0V 2000

Table 4-2: Unipolar analog input range and the output digital code on DAQ/

PXI-2010 (Note that the last 2 digital codes are SDI<1..0>)

Operation Theory 29

DAQ/PXI-2005/2006/2016 AI Data Format

The data format of the acquired 16-bit A/D data is Binary coding.
Table 7 and 8 illustrate the valid input ranges and the ideal transfer
characteristics. The converted digital codes for DAQ/PXI-2005/
2006/2016 are 16-bit and direct binary, and here we present the
codes as hexadecimal numbers.

Description Bipolar Analog Input Range Digital code

Full-scale Range ±10V ±5V ±2.5V ±1.25V

Least significant bit 305.2uV 152.6uV 76.3uV 38.15uV

FSR-1LSB 9.999695V 4.999847V 2.499924V 1.249962V FFFF

Midscale +1LSB 305.2uV 152.6uV 76.3uV 38.15uV 8001

Midscale 0V 0V 0V 0V 8000

Midscale -1LSB -305.2uV -152.6uV -76.3uV -38.15uV 7FFF

-FSR -10V -5V -2.5V -1.25V 0000

Table 4-3: Bipolar analog input range and the output digital code on the DAQ/

PXI-2005/2006/2016

Description Unipolar Analog Input Range Digital code

Full-scale Range 0V to 10V 0 to +5V 0 to +2.5V 0 to +1.25V

Least signifi-cant bit 152.6uV 76.3uV 38.15uV 19.07uV

FSR-1LSB 9.999847V 4.999924V 2.499962V 1.249981V FFFF

Midscale +1LSB 5.000153V 2.500076V 1.250038V 0.625019V 8001

Midscale 5V 2.5V 1.25V 0.625V 8000

Midscale -1LSB 4.999847V 2.499924V 1.249962V 0.624981V 7FFF

-FSR 0V 0V 0V 0V 0000

Table 4-4: Unipolar analog input range and the output digital code on the DAQ/

PXI-2005/2006/2016

Software conversion with polling data transfer acqui-sition mode (Software Polling)

This is the easiest way to acquire a single A/D data. The A/D con­verter starts one conversion whenever the dedicated software
command is executed. Then the software would poll the conver­sion status and read the A/D data back when it is available.

30 Operation Theory

This method is very suitable for applications that needs to process
A/D data in real time. Under this mode, the timing of the A/D con­version is fully controlled under software. However, it is difficult to
control the A/D con-version rate.

Specifying Channel, Gain, and Polarity

In both the Software Polling and programmable scan acquisi­tion mode, the channel, gain, and polarity for each channel can
be specified and selected. With this configuration, signal
sources must be connected to the right connector as the speci­fied settings.

When the specified channels have been sampled from the first
to the last data, the settings applied to each channel would be
the same until next change.

Example:

Typically you can set the input configuration for different chan­nels:

Ch1 with unipolar ±10V
Ch2 with bipolar ±2.5V
Ch3 with no signal input (disabled)
Ch4 with bipolar ±1.25V

Programmable scan acquisition mode

Scan Timing and Procedure

It's recommended that this mode be used if your applications
need a fixed and precise A/D sampling rate. You can accu­rately program the period between conversions of individual
channels. There are at least 2 counters, which need to be
specified:

SI_counter (24 bit):Specify the Scan Interval =

SI_counter / TIMEBASE

PSC_counter (24 bit):Specify Post Scan Counts,

i.e. the total sample count after a trigger
event,

The acquisition timing and the meanings of the 2 counters are
illustrated in Figure 10. The SCAN_START signal is derived from
the SI_counter, which will lead to the A/D conversion signal gener­ation. Note that the DAQ/PXI-20XX series is a simultaneous sam-

Operation Theory 31

pling A/D card, so the “scan interval” equals to the “sampling
interval”.

Example: (Post-trigger acquisition)

Set

SI_counter = 160

PSC_counter = 30

TIMEBASE = Internal clock source

Then
Scan Interval = 160/40M s = 4 us
Total acquisition time = 30 X 4 us = 120 us

TIMEBASE clock source

In scan acquisition mode, all the A/D conversions start on the
output of counters, which use TIMEBASE as the clock source.
By software you can specify the TIMEBASE to be either an
internal clock source (on-board 40MHz clock) or an external
clock input (EXTTIMEBASE) on J5 connector (68-pin VHDCI).
The external TIMEBASE is useful when you want to ac-quire
data at rates not available with the internal A/D sample clock.
The external clock source should generate TTL-compatible
continuous clocks; with a maximum frequency of 40MHz while
the minimum should be 1MHz. Please refer to 4.6 for informa­tion of user-controllable timing signals.

Figure 4-3: Scan Timing

32 Operation Theory

There are 4 trigger modes to start the scan acquisition, please
refer to section 4.1for more details. The data transfer mode is dis­cussed below.

Note:

1. The maximum A/D sampling rate is 2MHz for DAQ/PXI­2010, 500kHz for DAQ/PXI-2005, 250kHz for DAQ/PXI­2006 and 800kHz for DAQ/PXI-2016. Therefore, the
minimum setting of SI_counter is 20 for DAQ/PXI-2010,
80 for DAQ/PXI-2005, 160 for DAQ/PXI-2006 and 50 for
DAQ/PXI-2016 while using the internal TIMEBASE.

2. The SI_counter is a 24-bit counter. Therefore, the maxi­mum scan in-terval while using an internal TIMEBASE =
224/40M s = 0.419s.

Trigger Modes

DAQ/PXI-20XX provides 4 trigger sources (internal software trig­ger, ex-ternal analog trigger, external digital trigger or SSI trigger
signals). You must select one of them as the source of the trigger
event. A trigger event occurs when the specified condition is
detected on the selected trigger source (For example, a rising
edge on the external digital trigger input). Please refer to section

4.6 for more information about SSI signals.

There are 4 trigger modes (pre-trigger, post-trigger, middle-trigger,
and delay-trigger) working with the 4 trigger sources to initiate dif­ferent scan data acquisition timing when a trigger event occurs.
They are described as follows. For information of trigger sources,
please refer to section 4.5.

Pre-Trigger Acquisition

Use pre-trigger acquisition in applications where you want to
collect data before a trigger event. The A/D starts to sample
when you execute the specified function calls to begin the pre­trigger operation, and it stops when the trigger event occurs.
Users must program the value M in M_counter (16 bits) to
specify the amount of the stored scans before the trigger event.
If an external trigger occurs, the program only stores the last M
scans of data converted before the trigger event, as illustrated
in Figure 4-4, where M_counter = M =3, PSC_counter = 0. The

Operation Theory 33

post scan count is 0 because there is no sampling after the trig­ger event in pre-trigger acquisition. The total stored amount of
data = Number of enabled channels * M_counter.

Figure 4-4: Pre-trigger (trigger occurs after at least M scans acquired)

Note that If the trigger event occurs when a conversion is in
progress, the data acquisition won’t stop until this conversion is
completed, and the stored M scans of data include the last scan,
as illustrated in Figure 4-5, where M_counter = M =3,
PSC_counter = 0.

Figure 4-5: Pre-trigger scan acquisition (trigger occurs when a conversion

is in progress)

When the trigger signal occurs before the first M scans of data are
con-verted, the amount of stored data could be fewer than the
originally speci-fied amount M_counter, as illustrated in Figure 4-6.

34 Operation Theory

This situation can be avoided by setting M_enable. If M_enable is
set to 1, the trigger signal will be ignored until the first M scans of
data are converted, and it assures the user M scans of data under
pre-trigger mode, as illustrated in Figure 4-7. However, if
M_enable is set to 0, the trigger signal will be accepted any time,
as illustrated in Figure 13. Note that the total amount of stored
data will always be equal to the number in the M_counter because
the data acquisition won’t stop until a scan is completed.

Figure 4-6: Pre-trigger with M_enable = 0 (Trigger occurs before M scans)

Figure 4-7: Pre-trigger with M_enable = 1

Operation Theory 35

Note: The PSC_counter is set to 0 in pre-trigger acquisition mode.

Middle-Trigger Acquisition

Use middle-trigger acquisition in applications where you want
to collect data before and after a trigger event. The number of
scans (M) stored before the trigger is specified in M_counter,
while the number of scans (N) after the trigger is specified in
PSC_counter.

Like pre-trigger mode, the number of stored data could be less
than the specified amount of data (M+N), if an external trigger
occurs before M scans of data are converted. The M_enable bit
in middle-trigger mode takes the same effect as in pre-trigger
mode. If M_enable is set to 1, the trigger signal will be ignored
until the first M scans of data are converted, and it assures the
user with (M+N) scans of data under middle-trigger mode.
However, if M_enable is set to 0, the trigger signal will be
accepted at any time. Figure 4-8 shows the acquisition timing
with M_enable=1.

Figure 4-8: Middle trigger with M_enable = 1

36 Operation Theory

If the trigger event occurs when a scan is in progress, the stored N
scans of data would include this scan, as illustrated in Figure 4-9.

Figure 4-9: Middle trigger (trigger occurs when a scan is in progress)

Note:M_counter defined in Middle-Trigger is different from that of
Pre-Trigger. In Middle-trigger, M_Counter ends counting before
the trigger event while in Pre-Trigger, M_Counter ends counting
right at or before trigger event. Please refer to Figure 4-6 and Fig­ure 4-9.

Post-Trigger Acquisition

Use post-trigger acquisition in applications where you want to col­lect data after a trigger event. The number of scans after the trig­ger is specified in PSC_counter, as illustrated in Figure 4-10. The
total acquired data length = number of enable-channel *
PSC_counter.

Operation Theory 37

Figure 4-10: Post trigger

Delay Trigger Acquisition

Use delay trigger acquisition in applications where you want to
delay the data collection after the occurrence of a specified trig­ger event. The delay time is controlled by the value, which is
pre-loaded in the Delay_counter (16bit). The counter counts
down on the rising edge of the Delay_counter clock source
after the trigger condition is met. The clock source can be soft­ware programmed either by the TIMEBASE clock (40MHz) or
A/D sampling clock (TIMEBASE / SI_counter). When the count
reaches 0, the counter stops and the card starts to acquire

38 Operation Theory

data. The total acquired data length = number of enable-chan­nel * PSC_counter.

Figure 4-11: Delay trigger

Note: When the Delay_counter clock source is set to TIMEBASE,

the maximum delay time = 216/40M s = 1.638ms, and when
the source is set to A/D sampling clock, the maximum delay
time can be as higher as (216 * SI_counter / 40M ).

Post-Trigger or Delay-trigger Acquisition with re-trigger

Use post-trigger or delay-trigger acquisition with re-trigger
function in ap-plications where you want to collect data after
several trigger events. The number of scans after each trigger
is specified in PSC_counter, and users could program
Retrig_no to specify the re-trigger numbers. Figure 4-12 il-lus­trates an example. In this example, 2 scans of data is acquired
after the first trigger signal, then the card waits for the re-trigger
signal (re-trigger signals which occur before the first 2 scans is
completed will be ignored). When the re-trigger signal occurs, 2
more scan is performed. The process repeats until specified
amount of re-trigger signals are detected. The total acquired
data length = number of enable-channel * PSC_counter * Re­trig_no.

Operation Theory 39

Figure 4-12: Post trigger with re-trigger

Bus-mastering DMA Data Transfer

PCI bus-mastering DMA is necessary for high speed DAQ in
order to utilize the maximum PCI bandwidth. The bus-master­ing controller, which is built in the PLX IOP-480 PCI controller,
controls the PCI bus when it becomes the master of the bus.
Bus mastering reduces the size of the on-board memory and
reduces the CPU loading because data is directly transferred
to the computer’s memory without host CPU intervention.

Bus-mastering DMA provides the fastest data transfer rate on
PCI-bus. Once the analog input operation starts, control
returns to your program. The hardware temporarily stores the
acquired data in the on-board AD Data FIFO and then transfers
the data to a user-defined DMA buffer memory in the computer.
Please note that even when the acquired data length is less
than the Data FIFO, the AD data will not be kept in the Data
FIFO but directly transferred into host memory by the bus-mas­tering DMA.

The DMA transfer mode is very complex to program. We rec­ommend using a high-level program library to configure this
card. If users would like to know more about programs/soft­ware’s that can handle the DMA bus master data transfer,

40 Operation Theory

please refer to http://www.plxtech.com for more in-formation on
PCI controllers.

By using a high-level programming library for high speed DMA
data ac-quisition, users simply need to assign the sampling
period and the number of conversion into their specified
counters. After the AD trigger condition is matched, the data
will be transferred to the system memory by the bus-mastering
DMA.

The PCI controller also supports the function of scatter/gather
bus mas-tering DMA, which helps the users to transfer large
amounts of data by linking all the memory blocks into a contin­uous linked list.

In a multi-user or multi-tasking OS, like Microsoft Windows,
Linux, and so on, it is difficult to allocate a large continuous
memory block to do the DMA transfer. Therefore, the PLX IOP­480 provides the function of scatter /gather or chaining mode
DMA to link the non-continuous memory blocks into a linked list
so that users can transfer very large amounts of data without
being limited by the fragment of small size memory. Users can
configure the linked list for the input DMA channel or the output
DMA channel. Figure 20 shows a linked list that is constructed
by three DMA descriptors. Each descriptor contains a PCI
address, a local address, a transfer size, and the pointer to the
next descriptor. Users can allocate many small size memory
blocks and chain their associative DMA de-scriptors altogether
by their application programs. DAQ/PXI-20XX software driver
provides simple settings of the scatter/gather function, and
some sample programs are also provided within the ADLINK
all-in-one CD.

Operation Theory 41

Figure 4-13: Scatter/gather DMA for data transfer

In non-chaining mode, the maximum DMA data transfer size is 2M
double words (8M bytes). However, by using chaining mode, scat­ter/gather, there is no limitation on DMA data transfer size. Users
can also link the de-scriptor nodes circularly to achieve a multi­buffered mode DMA.

4.2 D/A Conversion

There are 2 channels of 12-bit D/A output available in the DAQ/
PXI-20XX. When using D/A converters, users should assign and
control the D/A converter reference sources for the D/A operation
mode and D/A channels. Users could also select the output polar­ity: unipolar or bipolar.

The reference selection control lets users fully utilize the multiply­ing characteristics of the D/A converters. Internal 10V reference
and external reference inputs are available in the DAQ/PXI-20XX.
The range of the D/A output is directly related to the reference.
The digital codes that are up-dated to the D/A converters will mul­tiply with the reference to generate the analog output. While using
internal 10V reference, the full range would be –10V ~ +9.9951V
in the bipolar output mode, and 0V ~ 9.9976V in the unipolar out­put mode. While using an external reference, users can reach dif­ferent output ranges by connecting different references. For
example, if connecting a DC –5V with the external reference, then
the users can get a full range from –4.9976V to +5V in the bipolar
output with inverting char-acteristics due to the negative reference
voltage. Users could also have an amplitude modulated (AM) out-

42 Operation Theory

put by feeding a sinusoidal signal into the reference input. The
range of the external reference should be within ±10V. Table 4-5
and 4-6 illustrates the relationship between digital code and output
voltages.

Digital Code Analog Output

111111111111 Vr e f * (2047/2048)

100000000001 Vref * (1/2048)

100000000000 0V

011111111111 -Vr e f * (1/2048)

000000000000 -Vref

Table 4-5: Bipolar output code table (Vref=10V if internal reference is

selected)

Digital Code Analog Output

111111111111 Vr e f * (4095/4096)

100000000000 Vref * (2048/4096)

000000000001 Vref * (1/4096)

000000000000 0V

Table 4-6: Unipolar output code table (Vref=10V if internal reference is

selected)

The D/A conversion is initiated by a trigger source. Users must
decide how to trigger the D/A conversion. The data output will start
when a trigger condition is met. Before the start of D/A conversion,
D/A data is transferred from PC’s main memory to a buffering Data
FIFO.

There are two modes of the D/A conversion: Software Update and
Timed Waveform Generation are described, including timing, trig­ger source con-trol, trigger modes and data transfer methods.
Either mode may be ap-plied to D/A channels independently. You
can software update DA CH0 while generate timed waveforms on
CH1 at the same time.

Software Update

This is the easiest way to generate D/A output. First, users should
specify the D/A output channels, set output polarity: unipolar or

Operation Theory 43

bipolar, and ref-erence source: internal 10V or external AOEX­TREF. Then update the digital values into D/A data registers
through a software output command.

Timed Waveform Generation

This mode can provide your applications with a precise D/A output
with a fixed update rate. It can be used to generate an infinite or
finite waveform. You can accurately program the update period of
the D/A converters.

The D/A output timing is provided through a combination of
counters in the FPGA on board. There are totally 5 counters to be
specified. These counters are:

UI_counter (24 bits): specify the DA Update

Interval = CHUI_counter/TIMEBASE.

UC_counter (24 bits): specify the total Update

Counts in a single waveform

IC_counter (24 bits): specify the Iteration

Counts of waveform.

DA_DLY1_counter (16 bits): specify the Delay from

the trigger to the first update start.

DA_DLY2_counter (16 bits): specify the Delay

between two consecutive waveform
generations.

44 Operation Theory

Figure 21 shows a typical D/A timing diagram. D/A updates its out­put on each rising edge of DAWR. The meaning of the counters
above is dis-cussed more in the following sections.

Figure 4-14: Typical D/A timing of waveform generation (Assuming the data

in the data buffer are 2V, 4V, -4V, 0V)

Note: The maximum D/A update rate is 1MHz. Therefore, the min-

imum setting of the UI_counter is 40 while using an internal
TIMEBASE(40MHz).

Trigger Modes

Post-Trigger Generation

Use post trigger when you want to perform DA waveform right
after a trigger event occurs. In this trigger mode DLY1_Counter is
not used and you don’t need to specify it. Figure 4-15 shows a sin­gle waveform generated right after a trigger signal is detected. The
trigger signal could come from a software command, an analog
trigger or a digital trigger. Please refer to section 4.5 for detailed
information.

Operation Theory 45

Figure 4-15: Post trigger waveform generation (Assuming the data in the

data buffer are 2V, 4V, 6V, 3V, 0V, -4V, -2V, 4V)

Delay-Trigger Generation

Use delay trigger when you want to delay the waveform gener­ation after a trigger event. In Figure 4-16, DA_DLY1_counter
determines the delay time from the trigger signal to the start of
the waveform generation. DLY1_counter counts down on the
rising edge of its clock source after the trigger condition is met.
When the count reaches 0, the counter stops and the DAQ/
PXI-20XX starts the waveform generation. This DLY1_Counter
is 16-bit’s wide and users can set the delay time in units of
TIMEBASE (delay time = DLY1_Counter/TIMEBASE) or in
units of update period (delay time = DLY1_Counter *
UI_counter/TIMEBASE), such that the delay time can reach a
wider range.

46 Operation Theory

Figure 4-16: Delay trigger waveform generation (Assuming the data in the

data buffer are 2V, 4V, 6V, 3V, 0V, -4V, -2V, 4V)

Post-Trigger or Delay-Trigger with Re-trigger

Use post-trigger or delay-trigger with re-trigger function when
you want to generate waveform after more than one trigger
events. The re-trigger function can be enabled or disabled by
software setting. In Figure 4-17, each trigger signal will initiate
a waveform generation. However, the trigger event would be
ignored while the waveform generation is ongoing.

Figure 4-17: Re-triggered waveform generation (Assuming the data in the

data buffer are 2V, 4V, 2V, 0V)

Operation Theory 47

Iterative Waveform Generation

Set IC_Counter in order to generate iterative waveforms from
the data of a single waveform. The counter stores the iteration
number, and the itera-tions can be finite (Figure 4-12) or infinite
(Figure 4-13).

A data FIFO on board is used to buffer the digital data for DA
output. If the data size of a single waveform you specified (That
is, Update Counts in UC_counter) is less than the FIFO size,
after initially transferring the data from the host PC memory to
the FIFO on board, the data in the FIFO will be automatically
re-transmitted whenever a single waveform is completed.
Therefore, it won’t occupy the PCI bandwidth when repetitive
waveforms are performed. However, if the size of a single
waveform were larger than that of the FIFO, it needs to be
intermittently loaded from the host PC’s memory via DMA,
when a repetitive waveforms is performed thus PCI bandwidth
would be occupied.

The data FIFO size on DAQ/PXI-2010 is 2k samples and on
DAQ/PXI-2005/2006/2016 it is 512 samples.

Figure 4-18: Finite iterative waveform generation with Post-trigger and

DLY2_Counter = 0 (Assuming the data in the data buffer are 2V, 4V, 2V, 0V)

48 Operation Theory

Figure 4-19: Infinite iterative waveform generation with Post-trigger and

DLY2_Counter = 0 (Assuming the data in the data buffer are 2V, 4V, 2V, 0V)

Note:

1. When running infinite iterative waveform generation, set­ting IC_Counter is ineffective to the waveform genera­tion. It only makes a difference when setting stop mode
III, please refer to section 4.2.2.3.

2. How to set finite and infinite iterative waveform genera­tion is not in-cluded in this manual. Please refer to soft­ware manual for further in-formation.

Delay2 in Repetitive Waveform Generation

To diversify the D/A waveform generation, we add a DLY2
Counter to separate 2 consecutive waveforms in repetitive
waveform generation. The time between two waveforms is set
by the value of DLY2 Counter. The Delay2 counter starts to
count down after a waveform generation finishes, and the next
waveform generation starts right after it counts down to zero,
just as shown in Figure 21. This DLY2_Counter is 16-bits wide
and users can set the delay time in units of TIMEBASE (delay
time = DLY2_Counter/TIMEBASE) or in units of update period
(delay time = DLY2_Counter * UI_counter/TIMEBASE), such
that the delay time can reach a wider range

Stop Modes of Scan Update

You can call software stop function to stop waveform genera­tion when it is still in progress. Three stop modes are provided

Operation Theory 49

for timed waveform gen-eration, which means when it is to stop
the waveform generation. You can apply these 3 modes to stop
waveform generation no matter infinite or finite waveform gen­eration mode is selected.

Figure 4-20 illustrates an example for stop mode I, in this mode
the waveform stops immediately when software command is
asserted.

In stop mode II, after a software stop command is given, the
waveform generation won’t stop until a complete single wave­form is finished. Take Figure 4-21 for an example, since
UC_counter is set to 4, the total DA update counts (that is,
number of pulses of DAWR signal) must be a multiple of

4.(update counts = 20 in this example)

In stop mode III, after a software stop command is given, the
waveform generation won’t stop until the performed number of
waveforms is a mul-tiple of IC_Counter. Take Figure 4-22 for an
example, since IC_Counter is set to 3, the total generated
waveforms must be a multiple of 3(waveforms = 6 in this exam­ple), and the total DA update counts must be a multiple of
12(UC_counter * IC_Counter). You can compare these three
figures to see their differences.

Figure 4-20: Stop mode I (Assuming the data in the data buffer are 2V, 4V,

2V, 0V)

50 Operation Theory

Figure 4-21: Stop mode II

Figure 4-22: Stop mode III

4.3 Digital I/O

The DAQ/PXI-20XX contains 24-lines of general-purpose digital I/
O (GPIO), which is provided through a 82C55A chip.

The 24-line GPIO are separated into three ports: Port A, Port B
and Port C. High nibble (bit[7…4]), and low nibble (bit[3…0]) of
each port can be indi-vidually programmed to be either inputs or
outputs. Upon system startup or reset, all the GPIO pins are reset
to high impedance inputs.

DAQ/PXI-2010 also provides 2 digital inputs per channel (SDI
from J5), which are sampled simultaneously with an analog signal

Operation Theory 51

input and is stored with the 14-bit AD data. Please refer to section

4.1 for the more details.

4.4 General Purpose Timer/Counter Operation

Two independent 16-bit up/down timer/counter are designed
within FPGA for various applications. They have the following fea­tures:

X Count up/down controlled by hardware or software

X Programmable counter clock source (internal or external

clock up to 10MHz)

X Programmable gate selection (hardware or software con-

trol)

X Programmable input and output signal polarities (high active

or low active)

X Initial Count can be loaded from software

X Current count value can be read-back by software without

affecting circuit operation

Timer/Counter functions basics

Each timer/counter has three inputs that can be controlled via
hardware or software. They are clock input (GPTC_CLK), gate
input (GPTC_GATE), and up/down control input
(GPTC_UPDOWN). The GPTC_CLK input provides a clock
source input to the timer/counter. Active edges on the GPTC_CLK
input make the counter increment or decrement. The
GPTC_UPDOWN input controls whether the counter counts up or
down. The GPTC_GATE input is a control signal which acts as a
counter enable or a counter trigger signal under different applica­tions.

The output of timer/counter is GPTC_OUT. After power-up,
GPTC_OUT is pulled high by a pulled-up resister about 10K
ohms. Then GPTC_OUT goes low after the DAQ/PXI-20XX is ini­tialized.

All the polarities of input/output signals can be programmed by
software. In this chapter, for easy explanation, all GPTC_CLK,

52 Operation Theory

GPTC_GATE, and GPTC_OUT are assumed to be active high or
rising-edge triggered in the figures.

General Purpose Timer/Counter modes

Eight programmable timer/counter modes are provided. All modes
start operating following a software-start signal that is set by the
software. The GPTC software reset initializes the status of the
counter and re-loads the initial value to the counter. The operation
remains halted until the soft-ware-start is re-executed. The operat­ing theories under different modes are described as below.

Mode 1: Simple Gated-Event Counting

In this mode, the counter counts the number of pulses on the
GPTC_CLK after the software-start. Initial count can be loaded
from software. Current count value can be read-back by soft­ware any time without affecting the counting. GPTC_GATE is
used to enable/disable counting. When GPTC_GATE is inac­tive, the counter halts the current count value. Figure 4-23 illus­trates the operation with initial count = 5, count-down mode.

Figure 4-23: Mode 1 Operation

Mode 2: Single Period Measurement

In this mode, the counter counts the period of the signal on
GPTC_GATE in terms of GPTC_CLK. Initial count can be
loaded from software. After the software-start, the counter
counts the number of active edges on GPTC_CLK between
two active edges of GPTC_GATE. After the com-pletion of the
period interval on GPTC_GATE, GPTC_OUT outputs high and
then current count value can be read-back by software. Figure

Operation Theory 53

4-24 il-lustrates the operation where initial count = 0, count-up
mode.

Figure 4-24: Mode 2 Operation

Mode 3: Single Pulse-width Measurement

In this mode the counter counts the pulse-width of the signal on
GPTC_GATE in terms of GPTC_CLK. Initial count can be
loaded from software. After the software-start, the counter
counts the number of active edges on GPTC_CLK when
GPTC_GATE is in its active state. After the completion of the
pulse-width interval on GPTC_GATE, GPTC_OUT out-puts
high and then current count value can be read-back by soft­ware. Figure 4-25 illustrates the operation where initial count =
0, count-up mode.

Figure 4-25: Mode 3 Operation

Mode 4: Single Gated Pulse Generation

This mode generates a single pulse with programmable delay
and pro-grammable pulse-width following the software-start.
The two programma-ble parameters could be specified in
terms of periods of the GPTC_CLK input by software.

54 Operation Theory

GPTC_GATE is used to enable/disable counting. When
GPTC_GATE is inactive, the counter halts the current count
value. Figure 4-26 illustrates the generation of a single pulse
with a pulse delay of two and a pulse-width of four.

Figure 4-26: Mode 4 Operation

Mode 5: Single Triggered Pulse Generation

This function generates a single pulse with programmable
delay and pro-grammable pulse-width following an active
GPTC_GATE edge. You could specify these programmable
parameters in terms of periods of the GPTC_CLK input. Once
the first GPTC_GATE edge triggers the single pulse,
GPTC_GATE takes no effect until the software-start is re-exe­cuted. Figure 4-27 illustrates the generation of a single pulse
with a pulse delay of two and a pulse-width of four.

Figure 4-27: Mode 5 Operation

Operation Theory 55

Mode 6: Re-triggered Single Pulse Generation

This mode is similar to mode5 except that the counter gener­ates a pulse following every active edge of GPTC_GATE. After
the software-start, every active GPTC_GATE edge triggers a
single pulse with programmable delay and pulse-width. Any
GPTC_GATE triggers that occur when the prior pulse is not
completed would be ignored. Figure 4-28 illustrates the gener­ation of two pulses with a pulse delay of two and a pulse-width
of four.

Figure 4-28: Mode 6 Operation

Mode 7: Single Triggered Continuous Pulse Generation

This mode is similar to mode5 except that the counter gener­ates con-tinuous periodic pulses with programmable pulse
interval and pulse-width following the first active edge of
GPTC_GATE. Once the first GPTC_GATE edge triggers the
counter, GPTC_GATE takes no effect until the soft-ware-start is
re-executed. Figure 4-29 illustrates the generation of two
pulses with a pulse delay of four and a pulse-width of three.

Figure 4-29: Mode 7 Operation

56 Operation Theory

Mode 8: Continuous Gated Pulse Generation

This mode generates periodic pulses with programmable pulse
interval and pulse-width following the software-start.
GPTC_GATE is used to enable/disable counting. When
GPTC_GATE is inactive, the counter halts the current count
value. Figure 4-30 illustrates the generation of two pulses with
a pulse delay of four and a pulse-width of three.

Figure 4-30: Mode 8 Operation

4.5 Trigger Sources

We provide flexible trigger selections in the DAQ/PXI-20XXseries
products. In addition to the internal software trigger, DAQ/PXI­20XX also supports external analog, digital triggers and SSI trig­gers. Users can configure the trigger source by software for A/D
and D/A processes individually. Note that the A/D and the D/A
conversion share the same analog trigger.

Software-Trigger

This trigger mode does not need any external trigger source. The
trigger asserts right after you execute the specified function calls
to begin the operation. A/D and D/A processes can receive an
individual software trigger.

External Analog Trigger

The analog trigger circuitry routing is shown in the Figure 4-31.
The analog multiplexer can select either a direct analog input from
the EXTATRIG pin (SRC1 in Figure 4-31) in the 68-pin connector
or the input signal of ADC (SRC2 in Figure 4-31). That is, one of
the 4 channel inputs you can select as a trigger source). Both trig­ger sources can be used for all trigger modes. The range of trigger

Operation Theory 57

level for SRC1 is ±10V and the resolution is 78mV (please refer to
Table 4-6), while the trigger range of SRC2 is the full-scale range
of the selected channel input, and the resolution is the desired
range divided by 256. For example, if the channel input selected to
be the trigger source is set bipolar and ±5V range, the trigger volt­age would be 4.96V when the trigger level code is set to 0xFF
while 0V when the code is set to 0x80.

Figure 4-31: Analog trigger block diagram

Trigger Level digital setting Tri gger vol tage

0xFF 9.92V

0xFE 9.84V

--- ---

0x81 0.08V

0x80 0

0x7F -0.08V

--- ---

0x01 -9.92V

Table 4-7: Analog trigger SRC1 (EXTATRIG) ideal transfer characteristic

The trigger signal is generated when the analog trigger condition
is satis-fied. There are five analog trigger conditions in the DAQ/
PXI-20XX. The DAQ/PXI-20XX uses 2 threshold voltages,
Low_Threshold and High_Threshold to build the 5 different trigger
conditions. Users could configure the trigger conditions easily by
software.

58 Operation Theory

Below-Low analog trigger condition

Figure 4-32 shows the below-low analog trigger condition, the
trigger signal is generated when the input analog signal is less
than the Low_Threshold voltage, and the High_Threshold set­ting is not used in this trigger condi-tion.

Figure 4-32: Below-Low analog trigger condition

Above-High analog trigger condition

Figure 4-33 shows the above-high analog trigger condition, the
trigger signal is generated when the input analog signal is
higher than the High_Threshold voltage, and the
Low_Threshold setting is not used in this trigger condition.

Figure 4-33: Above-High analog trigger condition

Inside-Region analog trigger condition

Figure 4-34 shows the inside-region analog trigger condition,
the trigger signal is generated when the input analog signal
level falls in the range between the High_Threshold and the
Low_Threshold voltages. Note: the High_Threshold setting

Operation Theory 59

should be always higher then the Low_Threshold voltage set­ting.

Figure 4-34: Inside-Region analog trigger condition

High-Hysteresis analog trigger condition

Figure 4-35 shows the high-hysteresis analog trigger condition,
the trigger signal is generated when the input analog signal
level is greater than the High_Threshold voltage, and the
Low_Threshold voltage determines the hysteresis duration.
Note the High_Threshold setting should be always higher then
the Low_Threshold voltage setting.

Figure 4-35: High-Hysteresis analog trigger condition

Low-Hysteresis analog trigger condition

Figure 4-36 shows the low-hysteresis analog trigger condition,
the trigger signal is generated when the input analog signal
level is less than the Low_Threshold voltage, and the

60 Operation Theory

High_Threshold voltage determines the hysteresis duration.
Note the High_Threshold setting should be always higher then
the Low_Threshold voltage setting.

Figure 4-36: Low-Hysteresis analog trigger condition

External Digital Trigger

An external digital trigger occurs when a rising edge or a falling
edge is detected on the digital signal connected to the EXT­DTRIG or the EXTWFTRG of the 68-pin connector for external
digital trigger. The EXTDTRIG is dedicated for A/D process,
and the EXTWFTRG is used for D/A process. Users can pro­gram the trigger polarity through ADLINK’s software drivers
easily. Note that the signal level of the external digital trigger
signals should be TTL-compatible, and the minimum pulse is
20ns.

Figure 4-37: External digital trigger

4.6 User-controllable Timing Signals

In order to meet the requirements for user-specific timing and the
re-quirements for synchronizing multiple cards, the DAQ/PXI-

Operation Theory 61

20XX series provides flexible user-controllable timing signals to
connect to external circuitry or additional cards.

The whole DAQ timing of the DAQ/PXI-20XX series is composed
of a bunch of counters and trigger signals in the FPGA. These tim­ing signals are related to the A/D, D/A conversions and Timer/
Counter applications. These timing signals can be inputs to or out­puts from the I/O connectors, the SSI connector and the PXI bus.
Therefore the internal timing signals can be used to control exter­nal devices or circuitry’s. Note that in different series of DAQ/PXI­20XX, the user-controllable timing signals would be slightly differ­ent. However, the SSI/PXI timing signals remain the same for
every DAQ/PXI-20XX card.

We implemented signal multiplexers in the FPGA to individually
choose the desired timing signals for the DAQ operations, as
shown in the Figure 4-38.

Figure 4-38: DAQ signals routing

Users can utilize the flexible timing signals through our software
drivers, and simply and correctly connect the signals with the
DAQ/PXI-20XX se-ries cards. Here is the summary of the DAQ
timing signals and the corre-sponding functionalities for DAQ/PXI­20XX series.

Timing signal category Corresponding functionality

SSI/PXI signals Multiple cards synchronization

Table 4-8: Summary of user-controllable timing signals and the

corresponding functionalities

62 Operation Theory

Timing signal category Corresponding functionality

AFI signals Control DAQ-2000 by external timing signals

AI_Trig_Out, AO_Trig_Out Control external circuitry or boards

Table 4-8: Summary of user-controllable timing signals and the

corresponding functionalities

DAQ timing signals

The user-controllable internal timing-signals contain: (Please refer
to Section 4.1 for the internal timing signal definition)

1. TIMEBASE, providing TIMEBASE for all DAQ opera­tions, which could be from internal 40MHz oscillator,
EXTTIMEBASE from I/O connector or the
SSI_TIMEBASE. Note that the frequency range of the
EXTTIMEBASE is 1MHz to 40MHz, and the EXTTIME­BASE should be TTL-compatible.

2. AD_TRIG, the trigger signal for the A/D operation, which
could come from external digital trigger, analog trigger,
internal software trigger and SSI_AD_TRIG. Refer to
Section 4.5 for detailed description.

3. SCAN_START, the signal to start a scan, which would
bring the following ADCONV signals for AD conversion,
and could come from the internal SI_counter, AFI[0] and
SSI_AD_START. This signal is synchronous to the
TIMEBASE. Note that the AFI[0] should be TTL-compat­ible and the minimum pulse width should be the pulse
width of the TIMEBASE to guarantee correct functional­ities.

4. ADCONV, the conversion signal to initiate a single con­version, which could be derived from internal counter,
AFI[0] or SSI_ADCONV. Note that this signal is edge­sensitive. When using AFI[0] as the external ADCONV
source, each rising edge of AFI[0] would bring an effec­tive conversion signal. Also note that the AFI[0] signal

Operation Theory 63

should be TTL-compatible and the minimum pulse width
is 20ns.

5. DA_TRIG, the trigger signal for the D/A operation, which
could be derived from external digital trigger, analog trig­ger, internal software trigger and SSI_AD_TRIG. Refer to
Section 4.5 for detailed de-scription.

6. DAWR, the update signal to initiate a single D/A conver­sion, which could be derived from internal counter, AFI[1]
or SSI_DAWR. Note that this signal is edge-sensitive.
When using AFI[1] as the external DAWR source, each
rising edge of AFI[1] would bring an effective update sig­nal. Also note that the AFI[1] signal should be TTL-com­patible and the minimum pulse width is 20ns.

Auxiliary Function Inputs (AFI)

Users could use the AFI in applications that take advantage of
external circuitry to directly control the DAQ/PXI-2000 series
cards. The AFI in-cludes 2 categories of timing signals: one group
is the dedicated input, and the other is the multi-function input.
Table 4-9 illustrates this categorization.

Table 4-9 summarizes the auxiliary function input signals and the
corre-sponding functionalities

64 Operation Theory

Category Timing signal Functionality Constraints

Replace the

EXTTIMEBASE

Dedicated input

Multi-function input

Table 4-9: Auxiliary function input signals and the corresponding functionalities

EXTDTRIG

EXTWFTRG

AFI[0]

(Dual functions)

AFI[1]

internal

TIMEBASE

External digi-

tal trigger

input for A/D

operation

External digi-

tal trigger

input for D/A

operation

Replace the

internal

ADCONV

Replace the

internal

SCAN_STAR

T

Replace the

internal

DAWR

1. TTL-compatible

2. 1MHz to 40MHz

3. Affects on both A/D
and D/A operations

1. TTL-compatible

2. Minimum pulse
width = 20ns

3. Rising edge or fall­ing edge

1. TTL-compatible

2. Minimum pulse
width = 20ns

3. Rising edge or fall­ing edge

1. TTL-compatible

2. Minimum pulse
width = 20ns

3. Rising–edge sensi­tive only

1. TTL-compatible

2. Minimum Pulse

width > 2/TIMEBASE

1. TTL-compatible

2. Minimum pulse
width = 20ns

3.Rising–edge sensi­tive only

EXTDTRIG and EXTWFTRIG

EXTDTRIG and EXTWFTRIG are dedicated digital trigger input
signals for A/D and D/A operations respectively. Please refer to
section 4.5 for detailed descriptions.

Operation Theory 65

EXTTIMEBASE

When the applications needs specific sampling frequency or
update rate that the card could not generate from its internal
TIMEBASE, the 40MHz clock, users could utilize the EXT­TIMEBASE with internal counters to achieve the specific timing
intervals for both A/D and D/A operations. Note that once you
choose the TIMEBASE source, both A/D and D/A operations
will be affected because A/D and D/A operations share the
same TIMEBASE.

AFI[0]

Alternatively, users can also directly apply an external A/D con­version signal to replace the internal ADCONV signal. This is
another way to achieve customized sampling frequencies. The
external ADCONV signal can only be inputted from the AFI[0].
As section 4.1 describes, the SI_counter triggers the genera­tion of the A/D conversion signal, ADCONV, but when using the
AFI[0] to replace the internal ADCONV signal, then the
SI_counter and the internally generated SCAN_START will not
be effective. By controlling the ADCONV externally, users can
sample the data ac-cording to external events. In this mode,
the Trigger signal and trigger mode settings will are not avail­able.

AFI[0] could also be used as SCAN_START signal for A/D
operations. Please refer to sections 4.1 and 4.6.1 for detailed
descriptions of the SCAN_START signal. When using external
signal (AFI[0]) to replace the internal SCAN_START signal, the
pulse width of the AFI[0] must be greater than two time of the
period of Timebase. This feature is suitable for the DAQ-2200/
PXI-2200 series, which can scan multiple channels data con­trolled by an external event. Note that the AFI[0] is a multi-pur­pose input, and it can only be utilized for one function at any
one time.

AFI[1]

Regarding the D/A operations, users could directly input the
external D/A update signal to replace the internal DAWR sig­nal. This is another way to achieve customized D/A update
rates. The external DAWR signal can only be inputted from the

66 Operation Theory

AFI[1]. Note that the AFI[1] is a multi-purpose input, and it can
only be utilized for one function at any one time. AFI[1] cur­rently only has one function. ADLINK reserves it for future
development.

System Synchronization Interface

SSI (System Synchronization Interface) provides the DAQ timing
syn-chronization between multiple cards. In DAQ/PXI-20XX
series, we de-signed a bi-directional SSI I/O to provide flexible
connection between cards and allow one SSI master to output the
signal and up to three slaves to receive the SSI signal. Note that
the SSI signals are designed for card synchronization only, not for
external devices.

SSI timing signal Functionality

SSI master: send the TIMEBASE out

SSI slave: accept the SSI_TIMEBASE to

SSI_TIMEBASE

SSI_AD_TRIG

SSI_ADCONV

SSI_SCAN_START

SSI_DA_TRIG

SSI_DAWR

Table 4-10: Summary of SSI timing signals and the corresponding

functionalities as the master or slave

replace the internal TIMEBASE signal.

Note: Affects on both A/D and D/A opera-

tions

SSI master: send the internal AD_TRIG out

SSI slave: accept the SSI_AD_TRIG as the

digital trigger signal.

SSI master: send the ADCONV out

SSI slave: accept the SSI_ADCONV to

replace the internal ADCONV signal.

SSI master: send the SCAN_START out

SSI slave: accept the SSI_SCAN_START to

replace the internal SCAN_START signal.

SSI master: send the DA_TRIG out.

SSI slave: accept the SSI_DA_TRIG as the

digital trigger signal.

SSI master: send the DAWR out.

SSI slave: accept the SSI_DAWR to replace

the internal DAWR signal.

Operation Theory 67

In PCI form factor, there is a connector on the top right corner of
the card for the SSI. Refer to section 2.3 for the connector posi­tion. All the SSI signals are routed to the 20-pin connector from the
FPGA. To synchronize multiple cards, users can connect a special
ribbon cable (ACL-SSI) to all the cards in a daisy-chain configura­tion

In PXI form factor, we utilize the PXI trigger bus built on the PXI
backplane to provide the necessary timing signal connections. All
the SSI signals are routed to the P2 connector. No additional cable
is needed. For detailed information of the PXI specifications,
please refer to PXI specification Re-vision 2.0 from PXI System
Alliance (www.pxisa.org).

The 6 internal timing signals could be routed to the SSI or the PXI
trigger bus through software drivers. Please refer to section 4.6.1
for detailed in-formation of the 6 internal timing signals. Physically
the signal routings are accomplished in the FPGA. Cards that are
connected together through the SSI or the PXI trigger bus, will still
achieve synchronization on the 6 timing signals.

The mechanism of the SSI/PXI

1. We adopt master-slave configuration for SSI/PXI. In a
system, for each timing signal, there shall be only one
master, and other cards are SSI slaves or with the SSI
function disabled.

2. For each timing signal, the SSI master doesn’t have to
be in a single card.

68 Operation Theory

For example:

We want to synchronize the A/D operation through the ADCONV
signal for 4 DAQ/PXI-20XX cards. Card 1 is the master, and Card
2, 3, 4 are slaves. Card 1 receives an external digital trigger to
start the post trigger mode acquisition. The SSI setting could be:

1. Set the SSI_ADCONV signal of Card 1 to be the master.

2. Set the SSI_ADCONV signals of Card 2, 3, 4 to be the

slaves.

3. Set external digital trigger for Card 1’s A/D operation.

4. Set the SI_counter and the post scan counter (PSC) of

all other cards.

5. Start DMA operations for all cards, thus all the cards are

waiting for the trigger event.

When the digital trigger condition of Card 1 occurs, Card 1 will
internally generate the ADCONV signal and output this ADCONV
signal to SSI_ADCONV signal of Card 2, 3 and 4 through the SSI/
PXI connectors. Thus we can achieve 16-channel acquisition
simultaneously.

You could arbitrarily choose each of the 6 timing signals as the SSI
master from any one of the cards. The SSI master can output the
internal timing signals to the SSI slaves. With the SSI, users could
achieve better card-to-card synchronization.

Note that when power-up or reset, the DAQ timing signals are
reset to use the internal generated timing signals.

AI_Trig_Out and AO_Trig_Out

AI_Trig_Out (or AO_Trig_Out) is the signal output following one of
the four trigger sources (software trigger, analog trigger, digital
trigger and SSI trigger) selected by the user. That is, AI_Trig_Out
follows the A/D trigger source, and AO_Trig_Out follows the D/A
trigger source. These two sig-nals can be used to control external
peripheral circuits or boards, or can be used as synchronization
control signals. The signal level of the AI_Trig_Out and
AO_Trig_Out are TTL-compatible.

Note: AI_Trig_Out and AO_Trig_Out are output pins on J5 (68-pin

Operation Theory 69

VHDCI). Connecting them to any signal source may cause
per-manent damage.

70 Operation Theory

5 Calibration

This chapter introduces the calibration process to minimize AD
meas-urement errors and DA output errors.

5.1 Loading Calibration Constants

The DAQ/PXI-20XX is factory calibrated before shipment by writ­ing the associated calibration constants of TrimDACs to the on­board EEPROM. TrimDACs are devices containing multiple DACs
within a single package. TrimDACs do not have memory capabil­ity. That means the calibration constants do not retain their values
after the system power is turned off. Loading calibration constants
is the process of loading the values of TrimDACs stored in the on­board EEPROM. ADLINK provides software to make it easy to
read the calibration constants automatically when neces-sary.

There is a dedicated space for calibration constants In the
EEPROM. In addition to the default bank of factory calibration con­stants, there are three extra user-modifiable banks. This means
users can load the TrimDACs values either from the original fac­tory calibration or from a calibration that is subsequently per­formed.

Because of the fact that errors in measurements and outputs will
vary with time and temperature, it is recommended re-calibratation
when the card is installed in the users environment. The auto-cali­bration function used to minimize errors will be introduced in the
next sub-section.

5.2 Auto-calibration

By using the auto-calibration feature of the DAQ/PXI-20XX, the
calibration software can measure and correct almost all the cali­bration errors without any external signal connections, reference
voltages, or measurement de-vices.

The DAQ/PXI-20XX has an on-board calibration reference to
ensure the accuracy of auto-calibration. The reference voltage is
measured at the factory and adjusted through a digital potentiome­ter by using an ul-tra-precision calibrator. The impedance of the
digital potentiometer is memorized after this adjustment. It is not

Calibration 71

recommended for users to adjust the on-board calibration refer­ence except when an ultra-precision cali-brator is available.

Note:

1. Before auto-calibration procedure starts, it is recom­mended to warn up the card for at least 15 minutes.

2. Please remove the cable before an auto-calibration pro­cedure is initiated because the DA outputs would be
changed in the process of calibration.

5.3 Saving Calibration Constants

After an auto-calibration is completed, users can save the new cal­ibration constants into one of the three user-modifiable banks in
the EEPROM. The date and the temperature when you ran the
auto-calibration will be saved accompanied with the calibration
constants. This means users can store three sets of calibration
constants according to three different environ-ments and re-load
the calibration constants later.

72 Calibration

Warranty Policy

Thank you for choosing ADLINK. To understand your rights and
enjoy all the after-sales services we offer, please read the follow­ing carefully.

1. Before using ADLINK’s products please read the user man-

ual and follow the instructions exactly. When sending in
damaged products for repair, please attach an RMA appli­cation form which can be downloaded from: http://
rma.adlinktech.com/policy/.

2. All ADLINK products come with a limited two-year war-

ranty, one year for products bought in China:

X The warranty period starts on the day the product is

shipped from ADLINK’s factory.

X Peripherals and third-party products not manufactured

by ADLINK will be covered by the original manufactur­ers' warranty.

X For products containing storage devices (hard drives,

flash cards, etc.), please back up your data before send­ing them for repair. ADLINK is not responsible for any
loss of data.

X Please ensure the use of properly licensed software with

our systems. ADLINK does not condone the use of
pirated software and will not service systems using such
software. ADLINK will not be held legally responsible for
products shipped with unlicensed software installed by
the user.

X For general repairs, please do not include peripheral

accessories. If peripherals need to be included, be cer­tain to specify which items you sent on the RMA Request
& Confirmation Form. ADLINK is not responsible for
items not listed on the RMA Request & Confirmation
Form.

Warranty Policy 73

3. Our repair service is not covered by ADLINK's guarantee
in the following situations:

X Damage caused by not following instructions in the

User's Manual.

X Damage caused by carelessness on the user's part dur-

ing product transportation.

X Damage caused by fire, earthquakes, floods, lightening,

pollution, other acts of God, and/or incorrect usage of
voltage transformers.

X Damage caused by unsuitable storage environments

(i.e. high temperatures, high humidity, or volatile chemi­cals).

X Damage caused by leakage of battery fluid during or

after change of batteries by customer/user.

X Damage from improper repair by unauthorized ADLINK

technicians.

X Products with altered and/or damaged serial numbers

are not entitled to our service.

X This warranty is not transferable or extendible.

X Other categories not protected under our warranty.

4. Customers are responsible for shipping costs to transport
damaged products to our company or sales office.

5. To ensure the speed and quality of product repair, please
download an RMA application form from our company web­site: http://rma.adlinktech.com/policy. Damaged products
with attached RMA forms receive priority.

If you have any further questions, please email our FAE staff:
[e-mail].

74 Warranty Policy