ADLINK PXI-2006 User Manual

DAQ/PXI-201x/200x

4-CH, Simultaneous, High Performance

Multi-Function Data Acquisition Card

User’s Manual

Manual Rev. 2.00

Revision Date: April 20, 2006

Part No: 50-11020-1030

Advance Technologies; Automate the World.

The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not represent a commitment on the part of the manufacturer.

In no event will the manufacturer be liable for direct, indirect, special, incidental, or consequential damages arising out of the use or inability to use the product or documentation, even if advised of the possibility of such damages.

This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.

Trademarks

Product names mentioned herein are used for identification purposes only and may be trademarks and/or registered trademarks of their respective companies.

Getting Service from ADLINK

Customer Satisfaction is top priority for ADLINK Technology Inc. Please contact us should you require any service or assistance.

ADLINK TECHNOLOGY INC.

Web Site: http://www.adlinktech.com

Sales & Service: Service@adlinktech.com

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Please email or FAX this completed service form for prompt and satisfactory service.

List of Tables

Table 1-1: -3dB small signal bandwidth ..................................... 5

Table 1-2: System Noise ........................................................... 5

Table 1-3: CMRR: (DC to 60Hz) ................................................ 7

Table 3-1: 68-pin VHDCI-type pin assignment ........................ 19

Table 3-2: 68-pin VHDCI-type Connector Legend ................... 20

Table 3-3: SSI connector (JP3) pin assignment for DAQ-20XX 22

Table 3-4: Legend of SSI connector ........................................ 22

Table 4-1: Bipolar analog input range and the output digital code on

DAQ/PXI-2010 (Note that the last 2 digital codes are

SDI<1..0>) .............................................................. 29

Table 4-2: Unipolar analog input range and the output digital code

on DAQ/PXI-2010 (Note that the last 2 digital codes are

SDI<1..0>) .............................................................. 29

Table 4-3: Bipolar analog input range and the output digital code on

the DAQ/PXI-2005/2006/2016 ................................ 30

Table 4-4: Unipolar analog input range and the output digital code

on the DAQ/PXI-2005/2006/2016 ........................... 30

Table 4-5: Bipolar output code table (Vref=10V if internal reference

is selected) ............................................................. 43

Table 4-6: Unipolar output code table (Vref=10V if internal reference

is selected) ............................................................. 43

Table 4-7: Analog trigger SRC1 (EXTATRIG) ideal transfer charac-

teristic ..................................................................... 58

Table 4-8: Summary of user-controllable timing signals and the cor-

responding functionalities ....................................... 62

Table 4-9: Auxiliary function input signals and the corresponding

functionalities .......................................................... 65

Table 4-10: Summary of SSI timing signals and the corresponding

functionalities as the master or slave ..................... 67

List of Tables iii

List of Figures

Figure 2-1: PCB Layout of the DAQ-20XX................................. 17

Figure 2-2: PCB Layout of the PXI-20XX................................... 17

Figure 3-1: Single-Ended connections ....................................... 25

Figure 3-2: Ground-referenced source and differential input ..... 25

Figure 3-3: Floating source and differential input....................... 26

Figure 4-1: Synchronous Digital Inputs Block Diagram.............. 28

Figure 4-2: Synchronous Digital Inputs timing ........................... 28

Figure 4-3: Scan Timing............................................................. 32

Figure 4-4: Pre-trigger (trigger occurs after at least M scans ac-

quired) ..................................................................... 34

Figure 4-5: Pre-trigger scan acquisition (trigger occurs when a con-

version is in progress).............................................. 34

Figure 4-6: Pre-trigger with M_enable = 0 (Trigger occurs before M

scans) ...................................................................... 35

Figure 4-7: Pre-trigger with M_enable = 1 ................................. 35

Figure 4-8: Middle trigger with M_enable = 1............................. 36

Figure 4-9: Middle trigger (trigger occurs when a scan is in progress)

Figure 4-10: Post trigger .............................................................. 38

Figure 4-11: Delay trigger ............................................................ 39

Figure 4-12: Post trigger with re-trigger ....................................... 40

Figure 4-13: Scatter/gather DMA for data transfer....................... 42

Figure 4-14: Typical D/A timing of waveform generation (Assuming

the data in the data buffer are 2V, 4V, -4V, 0V)....... 45

Figure 4-15: Post trigger waveform generation (Assuming the data in

the data buffer are 2V, 4V, 6V, 3V, 0V, -4V, -2V, 4V) 46 Figure 4-16: Delay trigger waveform generation (Assuming the data in

the data buffer are 2V, 4V, 6V, 3V, 0V, -4V, -2V, 4V) 47 Figure 4-17: Re-triggered waveform generation (Assuming the data in

the data buffer are 2V, 4V, 2V, 0V).......................... 47

Figure 4-18: Finite iterative waveform generation with Post-trigger and

DLY2_Counter = 0 (Assuming the data in the data buffer

are 2V, 4V, 2V, 0V).................................................. 48

Figure 4-19: Infinite iterative waveform generation with Post-trigger

and DLY2_Counter = 0 (Assuming the data in the data

buffer are 2V, 4V, 2V, 0V)........................................ 49

Figure 4-20: Stop mode I (Assuming the data in the data buffer are 2V,

4V, 2V, 0V) .............................................................. 50

iv List of Figures

Figure 4-21: Stop mode II ............................................................ 51

Figure 4-22: Stop mode III ........................................................... 51

Figure 4-23: Mode 1 Operation.................................................... 53

Figure 4-24: Mode 2 Operation.................................................... 54

Figure 4-25: Mode 3 Operation.................................................... 54

Figure 4-26: Mode 4 Operation.................................................... 55

Figure 4-27: Mode 5 Operation.................................................... 55

Figure 4-28: Mode 6 Operation.................................................... 56

Figure 4-29: Mode 7 Operation.................................................... 56

Figure 4-30: Mode 8 Operation.................................................... 57

Figure 4-31: Analog trigger block diagram................................... 58

Figure 4-32: Below-Low analog trigger condition......................... 59

Figure 4-33: Above-High analog trigger condition ....................... 59

Figure 4-34: Inside-Region analog trigger condition .................... 60

Figure 4-35: High-Hysteresis analog trigger condition................. 60

Figure 4-36: Low-Hysteresis analog trigger condition.................. 61

Figure 4-37: External digital trigger.............................................. 61

Figure 4-38: DAQ signals routing................................................. 62

List of Figures v

1 Introduction

The DAQ/PXI-20XX is an advanced data acquisition card based on the 32-bit PCI architecture. High performance designs and the state-of-the-art technology make this card ideal for data logging and signal analysis ap-plications in medical, process control, etc.

Introduction 1

1.1 Features

The DAQ/PXI-20XX Advanced Data Acquisition Card provides the fol-lowing advanced features:

X 32-bit PCI-Bus, plug and play

X 4-channel simultaneous differential analog inputs

X DAQ/PXI-2010: 14-bit Analog input resolution with sampling

rate up to 2MS/s

X DAQ/PXI-2005: 16-bit Analog input resolution with sampling

rate up to 500KS/s

X DAQ/PXI-2006: 16-bit Analog input resolution with sampling

rate up to 250KS/s

X DAQ/PXI-2016: 16-bit Analog input resolution with sampling

rate up to 800kS/s

X Programmable bipolar/unipolar analog input

X Programmable gain (x1, x2, x4, x8 for all DQ-20XX)

X DAQ/PXI-2010: Total 8K samples A/D FIFO

X DAQ/PXI-2005/2006/2016: Total 512 samples A/D FIFO

X Versatile trigger sources: software trigger, external digital

trigger, analog trigger and trigger from System Synchronization Interface (SSI).

X A/D Data transfer: software polling & bus-mastering DMA

with Scatter/Gather functionality

X Four A/D trigger modes: post-trigger, delay-trigger, pre-trig-

ger and middle-trigger

X 2 channel DA outputs with waveform generation capability

X 2K samples output data FIFO for DA channels

X DA Data transfer: software update and bus-mastering DMA

with Scatter/Gather functionality

X System Synchronization Interface (SSI)

X A/D/DA fully auto-calibration

X Completely jumper-less and software configurable

2Introduction

1.2 Applications

X Automotive Testing

X Cable Testing

X Transient signal measurement

X ATE

X Laboratory Automation

X Biotech measurement

Introduction 3

1.3 Specifications

Analog Input (AI)

X Number of channels: 4 differential

X A/D converter:

Z 2010: LTC1414 or equivalent

Z 2005: A/D7665 or equivalent

Z 2006: A/D7663 or equivalent

Z 2016: A/D7671 or equivalent

X Max sampling rate:

Z 2010: 2MS/s

Z 2016: 800kS/s

Z 2005: 500kS/s

Z 2006: 250kS/s

X Resolution:

Z 2010: 14 bits, no missing code

Z 2005/2006/2016:16 bits, no missing code

X FIFO buffer size:

Z 2010:8K samples

Z 2005/2006/2016: 512 samples

X Programmable input range:

Z Bipolar: ±10V, ±5V, ±2.5V, ±1.25V

Z Unipolar: 0~10V, 0~5V, 0~2.5V, 0~1.25V

X Operational common mode voltage range: ±11V

X Overvoltage protection:

Z Power on: continuous ±30V

Z Power off: continuous ±15V

X Input impedance: 1GΩ/100pF

4Introduction

X -3dB small signal bandwidth: (Typical, 25°C)

Device Input Range Bandwidth (-3dB) Input Range Bandwidth (-3dB)

±10V 1170 kHz 0~10V 1090 kHz

2010

±5V 1050 kHz 0~5V 1020 kHz

±2.5V 800 kHz 0~2.5V 790 kHz

±1.25V 530 kHz 0~1.25V 530 kHz

±10V 1160 kHz 0~10V 1210 kHz

2005

±5V 1050 kHz 0~5V 1050 kHz

±2.5V 780 kHz 0~2.5V 770 kHz

±1.25V 520 kHz 0~1.25V 530 kHz

±10V 630 kHz 0~10V 640 kHz

2006

±5V 620 kHz 0~5V 620 kHz

±2.5V 540 kHz 0~2.5V 540 kHz

±1.25V 410 kHz 0~1.25V 420 kHz

±10V 840kHz 0~10V 900kHz

2016

±5V 825kHz 0~5V 800kHz

±2.5V 710kHz 0~2.5V 690kHz

±1.25V 530kHz 0~1.25V 530kHz

Table 1-1: -3dB small signal bandwidth

X Large signal bandwidth (1% THD): 300 kHz

X System Noise: (Typical)

Device Input Range System noise Input Range System noise

±10V 0.6 LSBrms 0~10V 0.8 LSBrms

2010

±5V 0.6 LSBrms 0~5V 0.8 LSBrms

±2.5V 0.6 LSBrms 0~2.5V 0.9 LSBrms

±1.25V 0.6 LSBrms 0~1.25V 0.9 LSBrms

±10V 1.2 LSBrms 0~10V 1.9 LSBrms

2005

±5V 1.2 LSBrms 0~5V 2.0 LSBrms

±2.5V 1.3 LSBrms 0~2.5V 2.1 LSBrms

±1.25V 1.3 LSBrms 0~1.25V 2.2 LSBrms

Table 1-2: System Noise

Introduction 5

Device Input Range System noise Input Range System noise

±10V 1.0 LSBrms 0~10V 1.5 LSBrms

2006

2016

±5V 1.0 LSBrms 0~5V 1.6 LSBrms

±2.5V 1.1 LSBrms 0~2.5V 1.7 LSBrms

±1.25V 1.1 LSBrms 0~1.25V 1.8 LSBrms

±10V 1.6 LSBrms 0~10V 2.9 LSBrms

±5V 1.8 LSBrms 0~5V 3.2 LSBrms

±2.5V 1.8 LSBrms 0~2.5V 3.2 LSBrms

±1.25V 1.9 LSBrms 0~1.25V 3.4 LSBrms

Table 1-2: System Noise

6Introduction

X CMRR: (DC to 60Hz, Typical)

Device Input Range CMRR Input Range CMRR

±10V 90 dB 0~10V 89 dB

2010

±5V 92 dB 0~5V 92 dB

±2.5V 95 dB 0~2.5V 94 dB

±1.25V 97 dB 0~1.25V 97 dB

±10V 86 dB 0~10V 85 dB

2005

±5V 88 dB 0~5V 88 dB

±2.5V 91 dB 0~2.5V 90 dB

±1.25V 93 dB 0~1.25V 93 dB

±10V 87 dB 0~10V 86 dB

2006

±5V 89 dB 0~5V 88 dB

±2.5V 91 dB 0~2.5V 91 dB

±1.25V 93 dB 0~1.25V 93 dB

±10V 85dB 0~10V 86dB

2016

±5V 88dB 0~5V 88dB

±2.5V 91dB 0~2.5V 92dB

±1.25V 95dB 0~1.25V 95dB

Table 1-3: CMRR: (DC to 60Hz)

X Time-base source:

Z Internal 40MHz or External clock Input (fmax: 40MHz,

fmin: 1MHz, 50% duty cycle)

X Trigger modes:

Z Post-trigger, Delay-trigger, Pre-trigger and Middle-trigger

X Data transfers:

Z Programmed I/O, and bus-mastering DMA with scatter/

gather

X Input coupling: DC

X Offset error:

Z Before calibration: ±60mV max

Z After calibration: ±1mV max

X Gain error:

Introduction 7

Z Before calibration: ±0.6% of output max

Z After calibration: ±0.1% of output max for DAQ/PXI-

2010, ±0.03% of output max for DAQ/PXI-2005/2006/ 2016

8Introduction

Analog Output (AO)

X Number of channels: 2 channel voltage output

X DA converter: LTC7545 or equivalent

X Max update rate: 1MS/s

X Resolution: 12 bits

X FIFO buffer size:

Z 1k samples per channel when both channels are

enabled for timed DA output, and 2k samples when only

one channel is used for timed DA output

X Data transfers:

Z Programmed I/O, and bus-mastering DMA with scatter/

gather

X Output range:

Z Bipolar: ±10V or ±AOEXTREF

Z Unipolar: 0~10V or 0~AOEXTREF

X Settling time: 3µS to 0.5 LSB accuracy

X Slew rate: 20V/µS

X Output coupling: DC

X Protection: Short-circuit to ground

X Output impedance: 0.3Ω typical

X Output driving current: ±5mA max.

X Stability: Any passive load, up to 1500pF

X Power-on state: 0V steady-state

X Power-on glitch: ±1.5V/500uS

X Relative accuracy:

Z ±0.5 LSB typical, ±1 LSB max

X DNL:

Z ±0.5 LSB typical, ±1.2 LSB max

X Offset error:

Z Before calibration: ±80mV max

Z After calibration: ±1mV max

X Gain error:

Introduction 9

Z Before calibration: ±0.8% of output max

Z After calibration: ±0.02% of output max

X General Purpose Digital I/O (G.P. DIO, 82C55A)

X Number of channels: 24 programmable Input/Output

X Compatibility: TTL/CMOS

X Input voltage:

Z Logic Low: VIL=0.8V max; IIL=0.2mA max.

Z High: VIH=2.0V max; IIH=0.02mA max

X Output voltage:

Z Low: VOL=0.5V max; IOL=8mA max.

Z High: VOH=2.7V min; IOH=400µA

X Synchronous Digital Inputs (SDI, for DAQ/PXI-2010 only)

X Number of channels: 8 digital inputs sampled simulta-

neously with the analog signal input

X Compatibility: TTL/CMOS

X Input voltage:

Z Logic Low: VIL=0.8V max; IIL=0.2mA max.

Z Logic High: VIH=2.7V min; IIL=0.02mA max.

General Purpose Timer/Counter (GPTC)

X Number of channel: 2 Up/Down Timer/Counters

X Resolution: 16 bits

X Compatibility: TTL

X Clock source: Internal or external

X Max source frequency: 10MHz

10 Introduction

Analog Trigger (A.Trig)

X Source:

Z All analog input channels; external analog trigger

(EXTATRIG)

X Level: ±Full-scale, internal; ±10V external

X Resolution: 8 bits

X Slope: Positive or negative (software selectable)

X Hysteresis: Programmable

X Bandwidth: 400khz

External Analog Trigger Input (EXTATRIG)

X Input Impedance:

Z 40kΩ for DAQ/PXI-2010

Z 2kΩ for DAQ/PXI-2005/2006/2016

X Coupling: DC

X Protection: Continuous ±35V maximum

Digital Trigger (D.Trig)

X Compatibility: TTL/CMOS

X Response: Rising or falling edge

X Pulse Width: 10ns min

System Synchronous Interface (SSI)

X Trigger lines: 7

Stability

X Recommended warm-up time: 15 minutes

X On-board calibration reference:

Z Level: 5.000V

Z Temperature coefficient: ±2ppm/°C

Z Long-term stability: 6ppm/1000Hr

Introduction 11

Physical

X Dimensions:

Z 175mm by 107mm for DAQ-20XX

Z Standard CompactPCI form factor for PXI-20XX

X I/O connector: 68-pin female VHDCI type (e.g. AMP-

787254-1)

Power Requirement (typical)

X +5VDC: 1.82 A for DAQ/PXI-2010

Z 2.04 A for DAQ/PXI-2005

Z 1.82 A for DAQ/PXI-2006

Z 2.52 A for DAQ/PXI-2016

Operating Environment

X Ambient temperature: 0 to 55°C

X Relative humidity: 10% to 90% non-condensing

Storage Environment

X Ambient temperature: -20 to 80°C

X Relative humidity: 5% to 95% non-condensing

Interface Connector: 68-pin AMP-787254-1 or equivalent

12 Introduction

1.4 Software Support

ADLINK provides versatile software drivers and packages for users’ dif-ferent approach to building up a system. ADLINK not only provides pro-gramming libraries such as DLL for most Windows based systems, but also provide drivers for other software packages such as LabVIEW®.

All software options are included in the ADLINK CD. Non-free software drivers are protected with licensing codes. Without the software code, you can install and run the demo version for two hours for trial/demonstration purposes. Please contact ADLINK dealers to purchase the formal license.

Programming Library

For customers who are writing their own programs, we provide function libraries for many different operating systems, including:

X D2K-DASK: Include device drivers and DLL for Windows

98/NT/2000/XP. DLL is binary compatible across Windows 98/NT/2000/XP. This means all applications developed with D2K-DASK are compatible across Windows 98/NT/2000/ XP. The developing environment can be VB, VC++, Delphi, BC5, or any Windows programming language that allows calls to a DLL. The user’s guide and function reference manual of D2K-DASK are in the CD. (\\Manual\Software Package\D2K-DASK)

X D2K-DASK/X: Include device drivers and shared library for

Linux. The developing environment can be Gnu C/C++ or any program-ming language that allows linking to a shared library. The user's guide and function reference manual of D2K-DASK/X are in the CD. (\\Manual\Software Package\D2K-DASK-X.)

DAQ-LVIEW PnP: LabVIEW® Driver

DAQ-LVIEW PnP contains the VIs, which are used to interface with NI’s LabVIEW® software package. The DAQ-LVIEW PnP supports Windows 98/NT/2000/XP. The LabVIEW® drivers is shipped free with the card. You can install and use them without a

Introduction 13

license. For detailed information about DAQ-LVIEW PnP, please refer to the user’s guide in the CD.

(\\Manual\Software Package\DAQ-LVIEW PnP)

D2K-OCX: ActiveX Controls

We suggest customers who are familiar with ActiveX controls and VB/VC++ programming use D2K-OCX ActiveX control component libraries for developing applications. D2K-OCX is designed for Windows 98/NT/2000/XP. For more detailed information about D2K-OCX, please refer to the user's guide in the CD.

(\\Manual\Software Package\D2K-OCX)

The above software drivers are shipped with the card. Please refer to the “Software Installation Guide” in the package to install these drivers.

In addition, ADLINK supplies ActiveX control software DAQBench. DAQBench is a collection of ActiveX controls for measurement or auto-mation applications. With DAQBench, you can easily develop custom user interfaces to display your data, analyze data you acquired or received from other sources, or integrate with popular applications or other data sources. For more detailed information about DAQBench, please refer to the user's guide in the CD.

(\\Manual\Software Package\DAQBench Evaluation)

You can also get a free 4-hour evaluation version of DAQBench from the CD.

DAQBench is not free. Please contact ADLINK dealer or ADLINK to pur-chase the software license.

14 Introduction

2 Installation

This chapter describes how to install the DAQ/PXI-20XX. The contents of the package and unpacking information that you should be aware of are outlined first.

The DAQ/PXI-20XX performs an automatic configuration of the IRQ, and port address. Users can use software utility, PCI_SCAN to read the system configuration.

2.1 Contents of Package

In addition to this User's Guide, the package should include the following items:

X DAQ/PXI-20XX Multi-function Data Acquisition Card

X ADLINK All-in-one Compact Disc

X Software Installation Guide

If any of these items are missing or damaged, contact the dealer from whom you purchased the product. Save the shipping materials and carton in case you want to ship or store the product in the future.

2.2 Unpacking

Your DAQ/PXI-20XX SERIES card contains electro-static sensitive com-ponents that can be easily be damaged by static electricity.

Therefore, the card should be handled on a grounded anti-static mat. The operator should be wearing an anti-static wristband, grounded at the same point as the anti-static mat.

Inspect the card module carton for obvious damages. Shipping and han-dling may cause damage to your module. Be sure there are no shipping and handling damages on the modules carton before continuing.

After opening the card module carton, extract the system module and place it only on a grounded anti-static surface with component side up.

Installation 15

Again, inspect the module for damages. Press down on all the socketed IC's to make sure that they are properly seated. Do this only with the module place on a firm flat surface.

You are now ready to install your DAQ/PXI-20XX.

Note: DO NOT APPLY POWER TO THE CARD IF IT HAS BEEN

DAMAGED.

16 Installation

+ 58 hidden pages

ADLINK PXI-2006 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Table of Contents

List of Tables

List of Figures

1 Introduction

1.1 Features

1.2 Applications

1.3 Specifications

1.4 Software Support

Programming Library

DAQ-LVIEW PnP: LabVIEW® Driver

D2K-OCX: ActiveX Controls

2 Installation

2.1 Contents of Package

2.2 Unpacking