ADLINK PCIe-9852 User Manual
PCIe-9852
2-CH 14-Bit 200 MS/s digitizer
User’s Manual
Manual Rev.: 2.00
Revision Date: May 20, 2013
Part No: 50-11041-1000
Advance Technologies; Automate the World.
Revision History
Revision Release Date Description of Change(s)
2.00 2013/05/20 Initial Release
ii
PCIe-9852
Preface
Copyright 2013 ADLINK Technology, Inc.
This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form
without prior written permission of the manufacturer.
Disclaimer
The information in this document is subject to change without prior
notice in order to improve reliability, design, and function and does
not represent a commitment on the part of the manufacturer.
In no event will the manufacturer be liable for direct, indirect,
special, incidental, or consequential damages arising out of the
use or inability to use the product or documentation, even if
advised of the possibility of such damages.
Environmental Responsibility
ADLINK is committed to fulfill its social responsibility to global
environmental preservation through compliance with the European Union's Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE)
directive. Environmental protection is a top priority for ADLINK.
We have enforced measures to ensure that our products, manufacturing processes, components, and raw materials have as little
impact on the environment as possible. When products are at their
end of life, our customers are encouraged to dispose of them in
accordance with the product disposal and/or recovery programs
prescribed by their nation or company.
Conventions
Take note of the following conventions used throughout this
manual to make sure that users perform certain tasks and
instructions properly.
Preface iii
NOTE:
NOTE:
CAUTION:
Additional information, aids, and tips that help users perform
tasks.
Information to prevent minor physical injury, component damage, data loss, and/or program corruption when trying to complete a task.
Information to prevent serious physical injury, component
damage, data loss, and/or program corruption when trying to
complete a specific task.
iv Preface
PCIe-9852
Table of Contents
Preface .................................................................................... iii
List of Figures ....................................................................... vii
List of Tables.......................................................................... ix
1 Introduction ........................................................................ 1
1.1 Features............................................................................... 1
1.2 Applications ......................................................................... 2
1.3 Specifications....................................................................... 2
1.3.1 Analog Input ............................................................... 2
1.3.2 Timebase....................................................................4
1.3.3 Triggers ...................................................................... 5
1.3.4 General Specifications................................................ 6
1.4 Software Support ................................................................. 6
1.4.1 SDK ............................................................................ 7
1.4.2 WD-DASK................................................................... 7
1.5 Device Layout and I/O Array................................................ 8
2 Getting Started ................................................................. 11
2.1 Installation Environment .................................................... 11
2.2 Installing the Module.......................................................... 12
3 Operations ........................................................................ 13
3.1 Functional Block Diagram.................................................. 13
3.2 Analog Input Channel ........................................................ 13
3.2.1 Analog Input Front-End Configuration ...................... 13
3.2.2 Input Range and Data Format .................................. 14
3.2.3 DMA Data Transfer................................................... 14
3.3 Trigger Source and Trigger Modes.................................... 16
3.3.1 Software Trigger ....................................................... 17
Table of Contents v
3.3.2 External Digital Trigger ............................................. 17
3.3.3 Analog Trigger .......................................................... 18
3.3.4 Trigger Export ...........................................................18
3.4 Trigger Modes.................................................................... 18
3.4.1 Post Trigger Mode .................................................... 18
3.4.2 Delayed Trigger Mode .............................................. 18
3.4.3 Pre-Trigger Mode...................................................... 19
3.4.4 Middle Trigger Mode................................................. 20
3.4.5 Acquisition with Re-Triggering ..................................20
3.4.6 Data Average Mode
(Post-Trigger and Delayed-Trigger only) .................. 21
3.5 Timebase ........................................................................... 21
3.5.1 Internal Reference Clock .......................................... 21
3.5.2 External Reference Clock .........................................22
3.5.3 External Sampling Clock........................................... 22
3.6 ADC Timing Control ........................................................... 22
3.6.1 Timebase Architecture.............................................. 22
3.6.2 Basic Acquisition Timing........................................... 22
3.7 Synchronizing Multiple Modules ........................................ 25
3.7.2 SSI Timebase ........................................................... 28
3.7.3 SSI_TRIG .................................................................28
3.7.4 SSI__pre_data_rdy................................................... 28
A Appendix: Calibration....................................................... 29
A.1 Calibration Constant .......................................................... 29
A.2 Auto-Calibration ................................................................. 29
Important Safety Instructions.............................................. 31
Getting Service ..................................................................... 33
vi Table of Contents
PCIe-9852
List of Figures
Figure 1-1: Analog Input Channel Bandwidth, ±0.2 Vpp............... 3
Figure 1-2: Analog Input Channel Bandwidth, ±2 Vpp.................. 4
Figure 1-3: PCIe-9852 Schematic................................................. 8
Figure 1-4: PCIe-9852 I/O Array ................................................... 9
Figure 3-1: Analog Input Architecture of the PCIe-9852 ............. 13
Figure 3-2: Linked List of PCI Address DMA Descriptors ........... 16
Figure 3-3: Trigger Architecture of the PCIe-9852...................... 16
Figure 3-4: External Digital Trigger ............................................. 17
Figure 3-5: Post-Trigger Acquisition ...........................................18
Figure 3-6: Delayed Trigger Mode Acquisition............................ 19
Figure 3-7: Pre-Trigger Mode Acquisition ................................... 19
Figure 3-8: Middle Trigger Mode Acquisition .............................. 20
Figure 3-9: Re-Trigger Mode Acquisition .................................... 21
Figure 3-10: PCIe-9852 Clock Architecture .................................. 21
Figure 3-11: PCIe-9852 Timebase Architecture ........................... 22
Figure 3-12: Basic Digitizer Acquisition Timing............................. 23
Figure 3-13: Varying Sampling Rates
by Adjusting Scan Interval Counter .......................... 24
Figure 3-14: Card Number Configuration Switch .......................... 27
List of Figures vii
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viii List of Figures
PCIe-9852
List of Tables
Table 1-1: Channel Characteristics................................................... 3
Table 1-2: Timebase......................................................................... 5
Table 1-3: Trigger Source & Mode.................................................... 5
Table 1-4: Digital Trigger Input .........................................................5
Table 1-5: Digital Trigger Output....................................................... 6
Table 1-6: PCIe-9852 I/O Array Legend ......................................... 10
Table 3-1: Input Range and Data Format ....................................... 14
Table 3-2: Input Range FSR and –FSR Values.............................. 14
Table 3-3: Input Range Midscale Values........................................ 14
Table 3-4: Counter Parameters and Description ............................25
Table 3-5: SSI Signal Location and Pin Definition .......................... 26
Table 3-6: Card Number Configuration Settings............................. 28
List of Tables ix
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x List of Tables
1 Introduction
The PCIe-9852 is a high-speed 2-CH 14-Bit 200 MS/s digitizer,
specifically designed for applications such as LIDAR testing, optical fiber testing and radar signal acquisition. Analog input with 90
MHz bandwidth receives ±10V high speed signals with 50
impedance, and a simplified front-end design and highly stable
onboard reference provide both highly accurate measurement
results and high dynamic performance.
Ideal for environments requiring real-time acquisition and transfer
of data, the PCIe-9852 is based on the PCI Express Gen 2 x4 bus
as interface. When signals are converted from analog to digital,
continual data transfer to host system memory is enabled by PCI
Express high bandwidth capability.
The PCIe-9852 is auto-calibrated with an onboard reference circuit calibrating offset and acquiring analog input errors. Following
auto-calibration, the calibration constant is stored in EEPROM,
such that these values can be loaded and used as needed by the
board. There is no requirement to calibrate the module manually.
1.1 Features
X PCI Express specification Rev. 2.0 compliant
X Up to 200 MS/s sampling rate
X 2 simultaneous analog inputs
X High resolution 14-Bit ADC
X Up to 90 MHz bandwidth for analog input
X One GB onboard storage memory
X Scatter-Gather DMA data transfer for high-speed data
streaming
X Supports signal averaging
X Support for:
Z one external digital trigger input
Z one digital trigger output to external instrument
Z one external clock input
Z auto-calibration
PCIe-9852
Introduction 1
1.2 Applications
X Distributed Temperature Sensing (DTS)
X Video IC testing
X Physics laboratory and research environments
X Cable fault location and partial discharge monitoring for
power applications
1.3 Specifications
1.3.1 Analog Input
Channel Characteristics Comment
Channels 2 single-ended
Connector type SMA
Input coupling AC or DC, software selectable
AC coupling cutoff
frequency
ADC resolution 14-Bit
Inout signal range ±0.2 V, ±2 V, or ±10 V
Bandwidth
(-3dB)
Overvoltage
11Hz
90MHz
±10V 1M
±10V sine wave / 7Vrms for 50
Input impedance 50 or 1M, software selectable
Offset error ±1 mV
Gain error ±0.65%
56dB 1M, ±0.2 V
SNR
2 Introduction
62dB 1M, ±2 V
60dB 50, ±0.2 V
62dB 50, ±2 V
Channel Characteristics Comment
-73dBc 1M, ±0.2 V
PCIe-9852
THD
-69dBc 1M, ±2 V
-73dBc 50, ±0.2 V
-69dBc 50, ±2 V
SFDR -72dBc 1M, ±0.2 V
-72dBc 1M, ±2 V
-68dBc 50, ±0.2 V
-68dBc 50, ±2 V
Crosstalk -80dBc ±0.2 V, ±2 V
Table 1-1: Channel Characteristics
0
−1
−2
−3
−4
Bandwidth
−5
Magnitude (dB)
−6
−7
−8
−9
0.1M 0.3M 1M 3M 10M 30M 100M 300M
Frequency (Hz)
Figure 1-1: Analog Input Channel Bandwidth, ±0.2 Vpp
Introduction 3
0
−1
−2
−3
−4
−5
Magnitude (dB)
−6
−7
−8
−9
0.1M 0.3M 1M 3M 10M 30M 100M 300M
Bandwidth
Frequency (Hz)
Figure 1-2: Analog Input Channel Bandwidth, ±2 Vpp
1.3.2 Timebase
Sample Clock Comment
Internal : on board synthesizer
Timebase options
Sampling clock
frequency
External : CLK IN (front panel),
SSI
Internal : 200MHz
External : 40MHz ~ 200MHz
(CLK IN)
3.052kS/s to
200MS/s
Timebase accuracy < ± 25ppm
External reference
clock source
Front panel, SSI
4 Introduction
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