ADLINK PCIe-9852 User Manual

PCIe-9852

2-CH 14-Bit 200 MS/s digitizer

User’s Manual

Manual Rev.: 2.00

Revision Date: May 20, 2013

Part No: 50-11041-1000

Advance Technologies; Automate the World.

Revision History

Revision Release Date Description of Change(s)

2.00 2013/05/20 Initial Release

ii

PCIe-9852

Preface

Copyright 2013 ADLINK Technology, Inc.

This document contains proprietary information protected by copy­right. All rights are reserved. No part of this manual may be repro­duced by any mechanical, electronic, or other means in any form
without prior written permission of the manufacturer.

Disclaimer

The information in this document is subject to change without prior
notice in order to improve reliability, design, and function and does
not represent a commitment on the part of the manufacturer.

In no event will the manufacturer be liable for direct, indirect,
special, incidental, or consequential damages arising out of the
use or inability to use the product or documentation, even if
advised of the possibility of such damages.

Environmental Responsibility

ADLINK is committed to fulfill its social responsibility to global
environmental preservation through compliance with the Euro­pean Union's Restriction of Hazardous Substances (RoHS) direc­tive and Waste Electrical and Electronic Equipment (WEEE)
directive. Environmental protection is a top priority for ADLINK.
We have enforced measures to ensure that our products, manu­facturing processes, components, and raw materials have as little
impact on the environment as possible. When products are at their
end of life, our customers are encouraged to dispose of them in
accordance with the product disposal and/or recovery programs
prescribed by their nation or company.

Conventions

Take note of the following conventions used throughout this
manual to make sure that users perform certain tasks and
instructions properly.

Preface iii

NOTE:

NOTE:

CAUTION:

Additional information, aids, and tips that help users perform
tasks.

Information to prevent minor physical injury, component dam­age, data loss, and/or program corruption when trying to com­plete a task.

Information to prevent serious physical injury, component
damage, data loss, and/or program corruption when trying to
complete a specific task.

iv Preface

PCIe-9852

Table of Contents

Preface .................................................................................... iii

List of Figures ....................................................................... vii

List of Tables.......................................................................... ix

1 Introduction ........................................................................ 1

1.1 Features............................................................................... 1

1.2 Applications ......................................................................... 2

1.3 Specifications....................................................................... 2

1.3.1 Analog Input ............................................................... 2

1.3.2 Timebase....................................................................4

1.3.3 Triggers ...................................................................... 5

1.3.4 General Specifications................................................ 6

1.4 Software Support ................................................................. 6

1.4.1 SDK ............................................................................ 7

1.4.2 WD-DASK................................................................... 7

1.5 Device Layout and I/O Array................................................ 8

2 Getting Started ................................................................. 11

2.1 Installation Environment .................................................... 11

2.2 Installing the Module.......................................................... 12

3 Operations ........................................................................ 13

3.1 Functional Block Diagram.................................................. 13

3.2 Analog Input Channel ........................................................ 13

3.2.1 Analog Input Front-End Configuration ...................... 13

3.2.2 Input Range and Data Format .................................. 14

3.2.3 DMA Data Transfer................................................... 14

3.3 Trigger Source and Trigger Modes.................................... 16

3.3.1 Software Trigger ....................................................... 17

Table of Contents v

3.3.2 External Digital Trigger ............................................. 17

3.3.3 Analog Trigger .......................................................... 18

3.3.4 Trigger Export ...........................................................18

3.4 Trigger Modes.................................................................... 18

3.4.1 Post Trigger Mode .................................................... 18

3.4.2 Delayed Trigger Mode .............................................. 18

3.4.3 Pre-Trigger Mode...................................................... 19

3.4.4 Middle Trigger Mode................................................. 20

3.4.5 Acquisition with Re-Triggering ..................................20

3.4.6 Data Average Mode

(Post-Trigger and Delayed-Trigger only) .................. 21

3.5 Timebase ........................................................................... 21

3.5.1 Internal Reference Clock .......................................... 21

3.5.2 External Reference Clock .........................................22

3.5.3 External Sampling Clock........................................... 22

3.6 ADC Timing Control ........................................................... 22

3.6.1 Timebase Architecture.............................................. 22

3.6.2 Basic Acquisition Timing........................................... 22

3.7 Synchronizing Multiple Modules ........................................ 25

3.7.2 SSI Timebase ........................................................... 28

3.7.3 SSI_TRIG .................................................................28

3.7.4 SSI__pre_data_rdy................................................... 28

A Appendix: Calibration....................................................... 29

A.1 Calibration Constant .......................................................... 29

A.2 Auto-Calibration ................................................................. 29

Important Safety Instructions.............................................. 31

Getting Service ..................................................................... 33

vi Table of Contents

PCIe-9852

List of Figures

Figure 1-1: Analog Input Channel Bandwidth, ±0.2 Vpp............... 3

Figure 1-2: Analog Input Channel Bandwidth, ±2 Vpp.................. 4

Figure 1-3: PCIe-9852 Schematic................................................. 8

Figure 1-4: PCIe-9852 I/O Array ................................................... 9

Figure 3-1: Analog Input Architecture of the PCIe-9852 ............. 13

Figure 3-2: Linked List of PCI Address DMA Descriptors ........... 16

Figure 3-3: Trigger Architecture of the PCIe-9852...................... 16

Figure 3-4: External Digital Trigger ............................................. 17

Figure 3-5: Post-Trigger Acquisition ...........................................18

Figure 3-6: Delayed Trigger Mode Acquisition............................ 19

Figure 3-7: Pre-Trigger Mode Acquisition ................................... 19

Figure 3-8: Middle Trigger Mode Acquisition .............................. 20

Figure 3-9: Re-Trigger Mode Acquisition .................................... 21

Figure 3-10: PCIe-9852 Clock Architecture .................................. 21

Figure 3-11: PCIe-9852 Timebase Architecture ........................... 22

Figure 3-12: Basic Digitizer Acquisition Timing............................. 23

Figure 3-13: Varying Sampling Rates

by Adjusting Scan Interval Counter .......................... 24

Figure 3-14: Card Number Configuration Switch .......................... 27

List of Figures vii

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viii List of Figures

PCIe-9852

List of Tables

Table 1-1: Channel Characteristics................................................... 3

Table 1-2: Timebase......................................................................... 5

Table 1-3: Trigger Source & Mode.................................................... 5

Table 1-4: Digital Trigger Input .........................................................5

Table 1-5: Digital Trigger Output....................................................... 6

Table 1-6: PCIe-9852 I/O Array Legend ......................................... 10

Table 3-1: Input Range and Data Format ....................................... 14

Table 3-2: Input Range FSR and –FSR Values.............................. 14

Table 3-3: Input Range Midscale Values........................................ 14

Table 3-4: Counter Parameters and Description ............................25

Table 3-5: SSI Signal Location and Pin Definition .......................... 26

Table 3-6: Card Number Configuration Settings............................. 28

List of Tables ix

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x List of Tables

1 Introduction

The PCIe-9852 is a high-speed 2-CH 14-Bit 200 MS/s digitizer,
specifically designed for applications such as LIDAR testing, opti­cal fiber testing and radar signal acquisition. Analog input with 90
MHz bandwidth receives ±10V high speed signals with 50
impedance, and a simplified front-end design and highly stable
onboard reference provide both highly accurate measurement
results and high dynamic performance.

Ideal for environments requiring real-time acquisition and transfer
of data, the PCIe-9852 is based on the PCI Express Gen 2 x4 bus
as interface. When signals are converted from analog to digital,
continual data transfer to host system memory is enabled by PCI
Express high bandwidth capability.

The PCIe-9852 is auto-calibrated with an onboard reference cir­cuit calibrating offset and acquiring analog input errors. Following
auto-calibration, the calibration constant is stored in EEPROM,
such that these values can be loaded and used as needed by the
board. There is no requirement to calibrate the module manually.

1.1 Features

X PCI Express specification Rev. 2.0 compliant

X Up to 200 MS/s sampling rate

X 2 simultaneous analog inputs

X High resolution 14-Bit ADC

X Up to 90 MHz bandwidth for analog input

X One GB onboard storage memory

X Scatter-Gather DMA data transfer for high-speed data

streaming

X Supports signal averaging

X Support for:

Z one external digital trigger input

Z one digital trigger output to external instrument

Z one external clock input

Z auto-calibration

PCIe-9852

Introduction 1

1.2 Applications

X Distributed Temperature Sensing (DTS)

X Video IC testing

X Physics laboratory and research environments

X Cable fault location and partial discharge monitoring for

power applications

1.3 Specifications

1.3.1 Analog Input

Channel Characteristics Comment

Channels 2 single-ended

Connector type SMA

Input coupling AC or DC, software selectable

AC coupling cutoff
frequency

ADC resolution 14-Bit

Inout signal range ±0.2 V, ±2 V, or ±10 V

Bandwidth
(-3dB)

Overvoltage

11Hz

90MHz

±10V 1M

±10V sine wave / 7Vrms for 50

Input impedance 50  or 1M, software selectable

Offset error ±1 mV

Gain error ±0.65%

56dB 1M, ±0.2 V

SNR

2 Introduction

62dB 1M, ±2 V

60dB 50, ±0.2 V

62dB 50, ±2 V

Channel Characteristics Comment

-73dBc 1M, ±0.2 V

PCIe-9852

THD

-69dBc 1M, ±2 V

-73dBc 50, ±0.2 V

-69dBc 50, ±2 V

SFDR -72dBc 1M, ±0.2 V

-72dBc 1M, ±2 V

-68dBc 50, ±0.2 V

-68dBc 50, ±2 V

Crosstalk -80dBc ±0.2 V, ±2 V

Table 1-1: Channel Characteristics

0

−1

−2

−3

−4

Bandwidth

−5

Magnitude (dB)

−6

−7

−8

−9

0.1M 0.3M 1M 3M 10M 30M 100M 300M
Frequency (Hz)

Figure 1-1: Analog Input Channel Bandwidth, ±0.2 Vpp

Introduction 3

0

−1

−2

−3

−4

−5

Magnitude (dB)

−6

−7

−8

−9

0.1M 0.3M 1M 3M 10M 30M 100M 300M

Bandwidth

Frequency (Hz)

Figure 1-2: Analog Input Channel Bandwidth, ±2 Vpp

1.3.2 Timebase

Sample Clock Comment

Internal : on board synthesizer

Timebase options

Sampling clock
frequency

External : CLK IN (front panel),
SSI

Internal : 200MHz

External : 40MHz ~ 200MHz
(CLK IN)

3.052kS/s to
200MS/s

Timebase accuracy < ± 25ppm

External reference
clock source

Front panel, SSI

4 Introduction

Sample Clock Comment

External reference
clock

External reference
clock input range

External sampling
clock input range

10MHz

500mVpp ~ 5Vpp

1Vpp ~ 5Vpp

Table 1-2: Timebase

AC / DC
compliant

AC / DC
compliant

1.3.3 Triggers

Trigger Source & Mode

Trigger source

Trigger mode

Digital Trigger Input

Sources Front panel SMA connector

Compatibility 3.3 V TTL, 5 V tolerant

Input high threshold 2.0 V

Input low threshold (VIL) 0.8 V

Maximum input overload -0.5 V ~ +5.5 V

Trigger polarity Rising or falling edge

Pulse width 20 ns minimum

Software, external digital trigger, analog trigger, and SSI
(system synchronized interface)

Post trigger, delay trigger, pre-trigger, or middle trigger,
re-trigger for post trigger and delay trigger modes

Table 1-3: Trigger Source & Mode

PCIe-9852

Table 1-4: Digital Trigger Input

Digital Trigger Output

Compatibility 5 V TTL

Output high threshold (VOH) 2.4 V

Output low threshold (VOL) 0.2 V

Introduction 5

Digital Trigger Output

Trigger polarity Positive or negative

Pulse width

Trigger output driving capacity Capable of driving 50 load

Table 1-5: Digital Trigger Output

50 ns, 100 ns, 150 ns, 200 ns, 500
ns, 1 s, 2 s, 7.5 s, and 10 s

1.3.4 General Specifications

Specifications

Physical dimensions 167.64 W x 106.68 H mm (6.53 x 4.16 in)

Bus

Bus interface PCI Express Gen 2 x 4

Environmental toleance

Operating

Storage

Calibration

Onboard reference +5 V and +2.5 V

Temperature coefficient 3.0 ppm/°C

Warm-up time 15 minutes

Temperature: 0°C - 50°C

Relative humidity: 5% - 95%, non-condensing

Temperature: -20°C - +80°C

Relative humidity: 5% - 95%, non-condensing

Power Consumption

Power Rail Standby Current (mA) Full Load (mA)

+3.3 V 102 102.2

+12 V 20 20

+5V 1920 2010

1.4 Software Support

ADLINK provides versatile software drivers and packages to suit
various user approaches to building a system. Aside from pro­gramming libraries, such as DLLs, for most Windows-based sys-

6 Introduction

PCIe-9852

tems, ADLINK also provides drivers for other application
environments such as LabVIEW®.

All software options are included in the ADLINK All-in-One CD.
Commercial software drivers are protected with licensing codes.
Without the code, you may install and run the demo version for
trial/demonstration purposes for only up to two hours. Contact
your ADLINK dealer to purchase the software license.

1.4.1 SDK

For customers who want to write their own programs, ADLINK pro­vides the following software development kits.

Z DAQPilot for Windows, compatible with various applica-

tion environments, such as VB.NET, VC.NET, VB/VC++,
BCB, and Delphi

Z DAQPilot for LabVIEW

Z Toolbox adapter for MATLAB

1.4.2 WD-DASK

WD-DASK includes device drivers and DLL for Windows XP/7/8.
DLL is binary compatible across Windows XP/7/8. This
means all applications developed with WD-DASK are compati­ble with these Windows operating systems. The development
environment may be VB, VB.NET, VC++, BCB, and Delphi, or
any Windows programming language that allows calls to a DLL.
The WD-DASK user and function reference manuals are on the
ADLINK All-in-One CD.

Introduction 7

1.5 Device Layout and I/O Array

All dimensions are in mm

NOTE:

NOTE:

174.52

100.36

59.05

176.42

Figure 1-3: PCIe-9852 Schematic

The PCIe-9852 I/O array is labeled to indicate connectivity, as
shown.

111.15

8 Introduction

PCIe-9852

Figure 1-4: PCIe-9852 I/O Array

Name

CH0 N/A Blue

CH1 N/A Blue

Introduction 9

Faceplate
Legend

Type Remark

On indicates CH0 acquisition ongoing
Off indicates CH0 acquisition stopped

On indicates CH1 acquisition ongoing
Off indicates CH1 acquisition stopped

Name

Ext. Clock
Input

Faceplate
Legend

CLK IN

Type Remark

Input for external reference clock or
sample clock to digitizer

Ext. Digital
Trigger
Input

Trigger
Output

Analog
Input

Analog
Input

External digital trigger input, receiving

TRG IN

SMA
Screw

TRG OUT

CH0 Analog input channel

CH1 Analog input channel

Table 1-6: PCIe-9852 I/O Array Legend

trigger signal from external instrument
and initiating acquisition

Trigger output, in which every time
acquisition begins, a pulse
synchronized with Timebase clock
asserts and is output through this
connector, at pulse width
programmable from 50ns to 10s via
software

10 Introduction

2 Getting Started

This chapter describes proper installation environment, installation
procedures, package contents and basic information users should
be aware of regarding the PCIe-9852.

Diagrams and illustrated equipment are for reference only.
Actual system configuration and specifications may vary.

NOTE:

NOTE:

2.1 Installation Environment

When unpacking and preparing to install, please refer to Important
Safety Instructions.

Only install equipment in well-lit areas on flat, sturdy surfaces with
access to basic tools such as flat- and cross-head screwdrivers,
preferably with magnetic heads as screws and standoffs are small
and easily misplaced.

Recommended Installation Tools

X Phillips (cross-head) screwdriver

X Flat-head screwdriver

X Anti-static wrist strap

X Antistatic mat

ADLINK PCIe-9852 DAQ modules are electrostatically sensitive
and can be easily damaged by static electricity. The module must
be handled on a grounded anti-static mat. The operator must wear
an anti-static wristband, grounded at the same point as the anti­static mat.

PCIe-9852

Getting Started 11

Inspect the carton and packaging for damage. Shipping and han­dling could cause damage to the equipment inside. Make sure that
the equipment and its associated components have no damage
before installation.

The equipment must be protected from static discharge and
physical shock. Never remove any of the socketed parts

CAUTION:

except at a static-free workstation. Use the anti-static bag
shipped with the product to handle the equipment and wear a
grounded wrist strap when servicing.

X Package Contents

X PCIe-9852 high-speed digitizer

X ADLINK All-in-one compact disc

X PCIe-9852 Quick Start Guide

If any of these items are missing or damaged, contact the dealer

Do not install or apply power to equipment that is damaged or
missing components. Retain the shipping carton and packing
materials for inspection. Please contact your ADLINK dealer/
vendor immediately for assistance and obtain authorization
before returning any product.

2.2 Installing the Module

1. Turn off the computer.

2. Remove the top cover.

3. Select an available PCI express x4 slot and remove the
bracket-retaining screw and the bracket cover.

4. Line up the PCI express digitizer with the PCI express
slot on the back panel. Slowly push down on the top of
the PCI express digitizer until its card-edge connector is
resting on the slot receptacle.

5. Install the bracket-retaining screw to secure the PCI
express digitizer to the back panel rail.

6. Replace the computer cover.

12 Getting Started

3 Operations

This chapter contains information regarding analog input, trigger­ing and timing for the PCIe-9852.

3.1 Functional Block Diagram

ADC

Interface

Trigger

Interface

AUX DIO Port

FPGA

PCI Express

Controller

FIFO

Local Bus

Interface

CH0

CH1

CLK IN

TRG IN

TRG OUT

Analog Front End

buffer

buffer

Calibration CKT

Synthesizer

14 bit ADC

B to B

High Speed

Interface

Daughter Board Carrier Board

3.2 Analog Input Channel

3.2.1 Analog Input Front-End Configuration

PXIe-9852

PCI Express BUS

Calibration Source

14-bit ADC

0

000

0

14

Protection ckt

AC / DC

Couple

50 / Hi-Z

High Impedance

Buffer

1x / 10x
amplifier

ADC Driver

100MHz

LPF

Figure 3-1: Analog Input Architecture of the PCIe-9852

Input Configuration

The input channel terminates with equivalent 50 or 1 M
input impedance (selected by software). The 14-bit ADC pro­vides not only accurate DC performance but also high signal­to-noise ratio, and high spurious-free dynamic range in AC per­formance. The ADC transfers data to system memory via the
high speed PCI Express Gen2 X 4 interface.

For auto-calibration, internal calibration provides stable and
accurate reference voltage to the AI.

Operations 13

3.2.2 Input Range and Data Format

Data format of the PCIe-9852 is 2’s complement. The ADC data of
PCIe-9852 is on the 14 MSB of the 16-bit A/D data. The 2 LSB of
the 16-bit A/D data should be truncated by software. A/D data
structure is as follows.

D15 D14 D13 D12 …. D3 D2 D1 D0

D15 ~ D2 bits represent the data from ADC (2’s complement)
D1, D0 bits are always 0.

Table 3-1: Input Range and Data Format

Description

Bipolar Analog
Input

Digital Code N/A N/A 7FFC 8000

Table 3-2: Input Range FSR and –FSR Values

Description Midscale +1LSB Midscale Midscale -1LSB

Bipolar Analog
Input

Digital Code 0001 0000 FFFC

Full scale

range

±10V 1.22mV 9.99878V -10.000V

±2V 0.244mV 1.99976V -2V

±0.2V 24.4uV 0.199976V -0.2V

±10V 1.22mV 0V -1.22mV

±2V 0.244mV 0V -0.244mV

±0.2V 24.4V 0V -24.4V

Table 3-3: Input Range Midscale Values

Least

significant bit

FSR-1LSB -FSR

3.2.3 DMA Data Transfer

The PCIe-9852, a PCIe Gen 2 X 4 device, is equipped with a
200MS/s high sampling rate ADC, generating a 800 MByte/
second rate.

14 Operations

PXIe-9852

To provide efficient data transfer, a PCI bus-mastering DMA is
essential for continuous data streaming, as it helps to achieve full
potential PCI Express bus bandwidth. The bus-mastering control­ler releases the burden on the host CPU since data is directly
transferred to the host memory without intervention. Once analog
input operation begins, the DMA returns control of the program.
During DMA transfer, the hardware temporarily stores acquired
data in the onboard AD Data FIFO, and then transfers the data to
a user-defined DMA buffer in the computer.

Using a high-level programming library for high speed DMA data
acquisition, the sampling period and the number of conversions
needs simply to be assigned into specified counters. After the AD
trigger condition is met, the data will be transferred to the system
memory by the bus-mastering DMA.

In a multi-user or multi-tasking OS, such as Microsoft Windows,
Linux, or other, it is difficult to allocate a large continuous memory
block. Therefore, the bus controller provides DMA transfer with
scatter-gather function to link non-contiguous memory blocks into
a linked list so users can transfer large amounts of data without
being limited by memory limitations. In non-scatter-gather mode,
the maximum DMA data transfer size is 2 MB double words (8 MB
bytes); in scatter-gather mode, there is no limitation on DMA data
transfer size except the physical storage capacity of the system.

Users can also link descriptor nodes circularly to achieve a multi­buffered DMA. Figure 3-2 illustrates a linked list comprising three
DMA descriptors. Each descriptor contains a PCI address, PCI
dual address, a transfer size, and the pointer to the next descrip­tor. PCI address and PCI dual address support 64-bit addresses
which can be mapped into more than 4 GB of address space.

Operations 15

First PCI Address

First Dual Address

Transfer Size

Next Descriptor

PCI Address

Dual Address

Transfer Size

Next Descriptor

PCI Express Bus

Local Memory

(FIFO)

Figure 3-2: Linked List of PCI Address DMA Descriptors

3.3 Trigger Source and Trigger Modes

This section details PCIe-9852 triggering operations.

Software trigger

PCI Address

Dual Address

Transfer Size

Next Descriptor

Digital trigger input

Trigger

Decision

To Internal FPGA circuits

MUX

Trigger Output

SSI

Figure 3-3: Trigger Architecture of the PCIe-9852

16 Operations

PXIe-9852

The PCIe-9852 requires a trigger to implement acquisition of data.
Configuration of triggers requires identification of trigger
source. The PCIe-9852 supports internal software trigger,
external digital trigger, and analog trigger.

3.3.1 Software Trigger

The software trigger, generated by software command, is

asserted immediately following execution of specified function
calls to begin the operation.

3.3.2 External Digital Trigger

An external digital trigger is generated when a TTL rising edge

or falling edge is detected at the SMA connector TRG IN on the
front panel. As shown, trigger polarity can be selected by soft­ware. Note that the signal level of the external digital trigger
signal should be TTL compatible, and the minimum pulse width
20 ns.

Pulse Width > 20ns

Pulse Width > 20ns

Rising Edge Trigger Event Falling Edge Trigger Event

Figure 3-4: External Digital Trigger

Operations 17

3.3.3 Analog Trigger

An analog trigger is generated when AI input signal level is
detected at the SMA connector CH0, CH1 (selected by software).
The trigger level is also selected by software.

3.3.4 Trigger Export

When acquisition is initiated, a pulse synchronized with the Time­base clock asserts and is output through trigger output, at a pulse
width programmable from 50ns to 10s via software.

3.4 Trigger Modes

Trigger modes applied to trigger sources initiate different data
acquisition timings when a trigger event occurs. The following trig­ger mode descriptions are applied to analog input function.

3.4.1 Post Trigger Mode

Post-trigger acquisition is applicable when data is to be collected
after the trigger event, as shown. When the operation starts, PCIe­9852 waits for a trigger event. Once the trigger signal is received,
acquisition begins. Data is generated from ADC and transferred to
system memory continuously. The acquisition stops once the total
data amount reaches a predefined value.

Figure 3-5: Post-Trigger Acquisition

3.4.2 Delayed Trigger Mode

Delayed-trigger acquisition is utilized to postpone data collection
after the trigger event, as shown. When PCIe-9852 receives a trig-

18 Operations

PXIe-9852

ger event, a time delay is implemented before commencing acqui­sition. The delay is specified by a 16-bit counter value such that a

maximum thereof is the period of TIMEBASE X (216), and the min­imum is the Timebase period.

Figure 3-6: Delayed Trigger Mode Acquisition

3.4.3 Pre-Trigger Mode

Collects data before the trigger event, starting once specified func­tion calls are executed to begin the pre-trigger operation, and
stopping when the trigger event occurs. If the trigger event occurs
after the specified amount of data has been acquired, the system
stores only data preceding the trigger event by a specified
amount, as follows.

Operation start
Acquisition start

Trigger

Data

Trigger signals occuring before the specified
amount of data has been acquired are ignored

X samples have been acquired
before trigger occurs, where X<N

N samples

Trigger Event Occurs
Acquisition stop
Data transfer to system begins

Time

Figure 3-7: Pre-Trigger Mode Acquisition

Operations 19

3.4.4 Middle Trigger Mode

Collects data before and after the trigger event, with the amount to
be collected set individually (M and N samples), as follows

Operation start
Acquisition start

Trigger

Data

Trigger event occurs

Acquisition stop
Data transfer to system begins

N samplesM samples

Figure 3-8: Middle Trigger Mode Acquisition

3.4.5 Acquisition with Re-Triggering

A digitizer acquires a trace of N samples/channel for a single
acquisition. Re-Trigger mode can also be set to automatically
acquire R traces, containing N*R samples/channel of data, without
additional software intervention.

The Re-Trigger setting can be used for Post-Trigger and Delayed­Trigger modes, with different limitations on the spacing between
trigger events in each mode. Trigger events arriving too close to
the previous instance will be ignored by the digitizer.

X In Post-Trigger mode, the minimum spacing between trigger

events is N+1

X In Delayed-Trigger mode, the minimum spacing between

trigger events is (N+D)+1, where D is the number of the
delayed setting

Time

20 Operations

PXIe-9852

Figure 3-9: Re-Trigger Mode Acquisition

3.4.6 Data Average Mode (Post-Trigger and Delayed-

Trigger only)

In normal post-trigger mode acquisition, N samples/channel data
are generated for a single trigger event. In Re-trigger mode (See
“Acquisition with Re-Triggering” on page 20.), a total of N * R sam­ples/channel data is generated for R trigger events, that is, R
traces (A trace contains N samples/channel). In Data Average
Mode, only N samples/channel data are generated for R trigger
events. The single trace data (N samples/channel) is the average
of the R traces sample by sample.

3.5 Timebase

CLK IN

Clock buffer

10MHz

Xtal

Synthesizer

Figure 3-10: PCIe-9852 Clock Architecture

3.5.1 Internal Reference Clock

The PCIe-9852 internal 10MHz Crystal oscillator acts as reference
clock, generating, after synthesis, precisely 200MHz clock for

ADC.

Operations 21

To ADC

3.5.2 External Reference Clock

The PCIe-9852 can choose an external clock source for use as a
reference clock. When an external clock reference is selected, the
synthesizer input will switch to the clock source at SMA connector
CLK IN, and generate precisely 200MHz clock for ADC. The fre­quency of clock source is restricted to 10MHz.

3.5.3 External Sampling Clock

The PCIe-9852 can further choose an external clock source as
ADC sampling clock. When an external sampling clock is selected,
the ADC sampling frequency switches to the clock source at SMA
Connector CLK IN, and clock source frequency is available from
40MHz to 200MHz.

3.6 ADC Timing Control

3.6.1 Timebase Architecture

Onboard
200 MHz
Oscillator

ADC

ADC Output

200 MHz

X2
Multiplier
PLL

FPGA

400 MHz

200 MHz

For ADC
Data Bus

For ADC
state
machine

Figure 3-11: PCIe-9852 Timebase Architecture

3.6.2 Basic Acquisition Timing

The PCIe-9852 commences acquisition upon receipt of a trigger
event originating with software command, external digital trigger,
or the PXI Trigger Bus. The Timebase is a clock provided to the
ADC and acquisition engine for essential timing. The Timebase is

22 Operations

PXIe-9852

from an onboard synthesizer. To achieve different sampling rates,
a scan interval counter is used.

Using the post-trigger mode as an example, as shown, when a
trigger is accepted by the digitizer, the acquisition engine com­mences acquisition of data from ADC, and stores the sampled
data to the onboard FIFO. When FIFO is not empty, data will be
transferred to system memory immediately through the DMA
engine. The sampled data is generated continuously at the rising
edge of Timebase according to the scan interval counter setting.
When sampled data reaches a specified value, in this example
256, acquisition ends.

Analog

signal

TIMEBASE

Trigger

Acquisition
In Progress

DATA

Trigger mode = post-trigger, DataCnt = 256, ScanIntrv = 1

Acquisition initiates following this clock edge

D1

D3 D4 D255

D2

D253

D254

D256

Figure 3-12: Basic Digitizer Acquisition Timing

To achieve sampling rates other than 200MS/s, a number for scan
interval counter needs only be specified. For example, if the scan
interval counter is set as 2, the equivalent sampling rate is 200MS/
s / 2 = 100MS/s. If as 3, the equivalent sampling rate is 200MS/s /
3 = 66.66MS/s, and vice versa. The scan interval counter is 16 bits

Operations 23

in width, therefore the lowest sampling rate is 3.051KS/s (200MS/s
/ 65535).

Trigger

TIMEBASE

ScanIntrv = 1

D2

D1

D4

D3

D6

D5

D8

D7

D10

D9

DATA

ScanIntrv = 2

ScanIntrv = 3

Acquisition
In Progress

D1

D1

Acquisition is initiated following this clock edge

D2 D3 D4 D5 D6

D2 D3 D4

Figure 3-13: Varying Sampling Rates by Adjusting Scan Interval Counter

Counter
Name

Length Valid Value Description

ScanIntrv 16-bit 1-65535 Timebase divider to achieve

equivalent sampling rate of the
digitizer, where Sampling rate =
Timebase / ScanIntrv

DataCnt 28-bit 1-268435452 Specifies the amount of data to

be acquired:

X 1 - 268435452 for pre-

trig or mid-trig mode
operation

X 1 - 268435452 for Data

Average mode for 1
channel

X 1 - 134217724 for Data

Average mode for 2
channel

trigDelayTicks 16-bit 1 -65535 Indicates time between a trigger

event and commencement of
acquisition. The unit of a delay
count is the period of the
Timebase.

24 Operations

PXIe-9852

Counter
Name

ReTrgCnt 31-bit 1-2147483647 Enables re-trigger to accept

Length Valid Value Description

multiple triggers.

X 1 - 2147483647 for

normal operation

X 1 - 65535 for Data

Average mode

See Acquisition with Re­Triggering

Table 3-4: Counter Parameters and Description

3.7 Synchronizing Multiple Modules

The PCIe-9852 provides a dedicated connector as system syn­chronization interface, enabling multiple module synchroniza­tion. As shown, bi-directional SSI I/Os provides a flexible
connection between modules, allowing one SSI master PCIe-9852
to output SSI signals to other slave modules. The table summa-

rizes SSI timing signals and functionalities.

Different signals cannot be routed onto the same trigger bus
line.

NOTE:

NOTE:

SSI Timing Signal Function

SSI Clock (10MHz) Input/output timebase signal through SSI

SSI Trig Input/output trigger signal through SSI

SSI_pre_data_rdy Input/output trigger signal through SSI

All SSI signals are routed to the 16-pin connector from

FPGA, enabling multi-module synchronization. ACL-eSSI-2/

Operations 25

ACLeSSI-3/ACL-eSSI-4 cables can be used to synchronize 2, 3,
or 4 modules.

Signal Direction Descr. Pin

SSI Clock Input/Output Timebase signal

through SSI

SSI Trig Input/Output Trigger signal through

SSI

SSI_pre_data_rdy Input/Output Trigger signal through

SSI

NC No Connection 7

GND Ground 2, 4, 6,

Reserved Input/Output Reserved for future use 9

Table 3-5: SSI Signal Location and Pin Definition

1

11

3, 5,
13, 15,

8, 10,
12, 14,
16

3.7.1 Card Number Configuration

When multiple cards are used in a single chassis, card number
configuration via switch, as shown.

26 Operations

PXIe-9852

72

1 2 3 4

ON DIP

SW1

Figure 3-14: Card Number Configuration Switch

When all sliders are in ON position, card number is 0, when all are
OFF, card number is 15, as shown.

Slider 1 Slider 2 Slider 3 Slider 4 Card #

ON ON ON ON 0

ON ON ON OFF 1

ON ON OFF ON 2

ON ON OFF OFF 3

ON OFF ON ON 4

ON OFF ON OFF 5

ON OFF OFF ON 6

ON OFF OFF OFF 7

OFF ON ON ON 8

OFF ON ON OFF 9

Operations 27

Slider 1 Slider 2 Slider 3 Slider 4 Card #

OFF ON OFF ON 10

OFF ON OFF OFF 11

OFF OFF ON ON 12

OFF OFF ON OFF 13

OFF OFF OFF ON 14

OFF OFF OFF OFF 15

Table 3-6: Card Number Configuration Settings

Default card number is 0.

3.7.2 SSI Timebase

As an output, the SSI_TIMEBASE signal outputs the onboard
10MHz through ACL-eSSI-2/ACLeSSI-3/ACL-eSSI-4 cables. As
an input, the PCIe-9852 accepts the SSI_TIMEBASE signal to be
the source of timebase.

3.7.3 SSI_TRIG

As an output, the SSI_TRIG signal reflects the trigger event signal
in an acquisition sequence. As an input, the PCIe-9852 accepts
the SSI_TRIG signal to be the trigger event source. The signal is
configured in the rising edge-detection mode.

3.7.4 SSI__pre_data_rdy

If one SSI slave is set to mid-trig or pre-trig mode, the SSI master
should also be in mid-trig or pre-trig mode. SSI slaves in mid-trig
or pre-trig mode should send pre_data_rdy to SSI master through
SSI[0], SSI[1], SSI[5] or SSI[6].

A SSI master sends SSI_trig to other SSI slaves. If set to pre-trig
or mid-trig mode, SI_pre_data_rdy is received from other SSI
slaves. SSI slaves should be set to mid-trig or pre-trig mode to
send SSI_pre_data_rdy signal to the SSI master. Different SSI
slaves should not use the same SSI pins.

28 Operations

Appendix A Calibration

This chapter introduces the calibration process to minimize analog
input measurement errors.

A.1 Calibration Constant

The PCIe-9852 is factory calibrated before shipment, with associ­ated calibration constants written to the onboard EEPROM. At
system boot, the PCIe-9852 driver loads these calibration con­stants, such that analog input path errors are minimized. ADLINK
provides a software API for calibrating the PCIe-9852.

The onboard EEPROM provides two banks for calibration con­stant storage. Bank 0, the default bank, records the factory cali­brated constants, providing written protection preventing
erroneous auto-calibration. Bank 1 is user-defined space, pro­vided for storage of self-calibration constants. Upon execution of
auto-calibration, the calibration constants are recorded to Bank 1.

When PCIe-9852 boots, the driver accesses the calibration con­stants and is automatically set to hardware. In the absence of user
assignment, the driver loads constants stored in bank 0. If con­stants from Bank 1 are to be loaded, the preferred bank can be
designated as boot bank by software. Following re-assignment of
the bank, the driver will load the desired constants on system re­boot. This setting is recorded to EEPROM and is retained until re­configuration.

PCIe-9852

A.2 Auto-Calibration

Because errors in measurement and outputs will vary with time
and temperature, re-calibration is recommended when the module
is installed. Auto-calibration can measure and minimize errors
without external signal connections, reference voltages, or mea­surement devices.

The PCIe-9852 has an on-board calibration reference to ensure
the accuracy of auto-calibration. The reference voltage is mea­sured on the production line and recorded in the on-board
EEPROM.

Calibration 29

Before initializing auto-calibration, it is recommended to warm up
the PCIe-9852 for at least 20 minutes and remove connected

cables.

It is not necessary to manually factor delay into applications, as
the PCIe-9852 driver automatically adds the compensation

NOTE:

NOTE:

time.

30 Calibration

PCIe-9852

Important Safety Instructions

For user safety, please read and follow all instructions,
WARNINGS, CAUTIONS, and NOTES marked in this manual and

on the associated equipment before handling/operating the
equipment.

X Read these safety instructions carefully.

X Keep this user’s manual for future reference.

X Read the specifications section of this manual for detailed

information on the operating environment of this equipment.

X When installing/mounting or uninstalling/removing

equipment:

Z Turn off power and unplug any power cords/cables.

X To avoid electrical shock and/or damage to equipment:

Z Keep equipment away from water or liquid sources;

Z Keep equipment away from high heat or high humidity;

Z Keep equipment properly ventilated (do not block or

cover ventilation openings);

Z Make sure to use recommended voltage and power

source settings;

Z Always install and operate equipment near an easily

accessible electrical socket-outlet;

Z Secure the power cord (do not place any object on/over

the power cord);

Z Only install/attach and operate equipment on stable

surfaces and/or recommended mountings; and,

Z If the equipment will not be used for long periods of time,

turn off and unplug the equipment from its power source.

Important Safety Instructions 31

X Never attempt to fix the equipment. Equipment should only

be serviced by qualified personnel.

X A Lithium-type battery may be provided for uninterrupted,

backup or emergency power.

Risk of explosion if battery is replaced with an incorrect type;
please dispose of used batteries appropriately.

X Equipment must be serviced by authorized technicians

when:

Z The power cord or plug is damaged;

Z Liquid has penetrated the equipment;

Z It has been exposed to high humidity/moisture;

Z It is not functioning or does not function according to the

user’s manual;

Z It has been dropped and/or damaged; and/or,

Z It has an obvious sign of breakage.

32 Important Safety Instructions

Getting Service

Contact us should you require any service or assistance.

ADLINK Technology, Inc.

Address: 9F, No.166 Jian Yi Road, Zhonghe District
New Taipei City 235, Taiwan

ᄅקؑխࡉ೴৬ԫሁ 166 ᇆ 9 ᑔ

Tel: [phone]
Fax: [phone]
Email: [e-mail]

Ampro ADLINK Technology, Inc.

Address: 5215 Hellyer Avenue, #110, San Jose, CA 95138, USA
Tel: [phone]
Toll Free: [phone] (USA only)
Fax: [phone]
Email: [e-mail]

ADLINK Technology (China) Co., Ltd.

Address: Ϟ⍋Ꮦ⌺ϰᮄᓴ∳催⾥ᡔು㢇᯹䏃 300 ো(201203)
300 Fang Chun Rd., Zhangjiang Hi-Tech Park,

Pudong New Area, Shanghai, 201203 China
Tel: [phone]
Fax: [phone]
Email: [e-mail]

ADLINK Technology Beijing

Address: ࣫ҀᏖ⍋⎔Ϟഄϰ䏃 1 োⲜ߯ࡼ࡯໻ E ᑻ 801 ᅸ(100085)

Rm. 801, Power Creative E, No. 1,

Shang Di East Rd., Beijing, 100085 China
Tel: [phone]
Fax: [phone]
Email: [e-mail]

PCIe-9852

ADLINK Technology Shenzhen

Address: ⏅ഇᏖቅ⾥ᡔು催ᮄϗ䘧᭄ᄫᡔᴃು

Tel: [phone]
Fax: [phone]
Email: [e-mail]

LiPPERT ADLINK Technology GmbH

Address: Hans-Thoma-Strasse 11, D-68163, Mannheim, Germany
Tel: [phone]
Fax: [phone]
Email: [e-mail]

A1 󰶀 2 ὐ C  (518057)

2F, C Block, Bldg. A1, Cyber-Tech Zone, Gao Xin Ave. Sec. 7,

High-Tech Industrial Park S., Shenzhen, 518054 China

Getting Service 33

ADLINK Technology, Inc. (French Liaison Office)

Address: 15 rue Emile Baudot, 91300 Massy CEDEX, France
Tel: [phone]
Fax: [phone]
Email: [e-mail]

ADLINK Technology Japan Corporation

Address: ͱ101-0045 ᵅҀ䛑ҷ⬄⼲⬄䤯ފ⬎ 3-7-4

Tel: [phone]
Fax: [phone]
Email: [e-mail]

ADLINK Technology, Inc. (Korean Liaison Office)

Address: 昢殾柢 昢爎割 昢爎壟 1675-12 微汾瘶捒娯 8猻

Tel: [phone]
Fax: [phone]
Email: [e-mail]

ADLINK Technology Singapore Pte. Ltd.

Address: 84 Genting Lane #07-02A, Cityneon Design Centre,

Tel: [phone]
Fax: [phone]
Email: [e-mail]

ADLINK Technology Singapore Pte. Ltd. (Indian Liaison Office)

Address: 1st Floor, #50-56 (Between 16th/17th Cross) Margosa Plaza,

Tel: [phone]
Fax: [phone]
Email: [e-mail]

⼲⬄ 374 ɛɳ 4F
KANDA374 Bldg. 4F, 3-7-4 Kanda Kajicho,
Chiyoda-ku, Tokyo 101-0045, Japan

8F Mointer B/D,1675-12, Seocho-Dong, Seocho-Gu,
Seoul 137-070, Korea

Singapore 349584

Margosa Main Road, Malleswaram, Bangalore-560055, India

ADLINK Technology, Inc. (Israeli Liaison Office)

Address: 6 Hasadna St., Kfar Saba 44424, Israel
Tel: [phone]
Fax: [phone]
Email: [e-mail]

34 Getting Service