ADLINK PCIe-9814 User Manual

PCIe-9814

4-CH 12-Bit 80MS/s Digitizer

PCIe-9814/PCIe-9814P

User’s Manual

Manual Rev.: 2.00

Revision Date: Feb. 13, 2015

Part No: 50-11256-1000

Advance Technologies; Automate the World.

Revision History

Revision Release Date Description of Change(s)

2.00 2015/02/13 Initial Release

ii

PCIe-9814

Preface

Copyright 2015 ADLINK Technology, Inc.

This document contains proprietary information protected by copy­right. All rights are reserved. No part of this manual may be repro­duced by any mechanical, electronic, or other means in any form
without prior written permission of the manufacturer.

Disclaimer

The information in this document is subject to change without prior
notice in order to improve reliability, design, and function and does
not represent a commitment on the part of the manufacturer.

In no event will the manufacturer be liable for direct, indirect,
special, incidental, or consequential damages arising out of the
use or inability to use the product or documentation, even if
advised of the possibility of such damages.

Environmental Responsibility

ADLINK is committed to fulfill its social responsibility to global
environmental preservation through compliance with the Euro­pean Union's Restriction of Hazardous Substances (RoHS) direc­tive and Waste Electrical and Electronic Equipment (WEEE)
directive. Environmental protection is a top priority for ADLINK.
We have enforced measures to ensure that our products, manu­facturing processes, components, and raw materials have as little
impact on the environment as possible. When products are at their
end of life, our customers are encouraged to dispose of them in
accordance with the product disposal and/or recovery programs
prescribed by their nation or company.

Conventions

Take note of the following conventions used throughout this
manual to make sure that users perform certain tasks and
instructions properly.

Preface iii

NOTE:

NOTE:

CAUTION:

Additional information, aids, and tips that help users perform
tasks.

Information to prevent minor physical injury, component dam­age, data loss, and/or program corruption when trying to com­plete a task.

Information to prevent serious physical injury, component
damage, data loss, and/or program corruption when trying to
complete a specific task.

iv Preface

PCIe-9814

Table of Contents

Preface .................................................................................... iii

List of Figures ....................................................................... vii

List of Tables.......................................................................... ix

1 Introduction ........................................................................ 1

1.1 Features............................................................................... 1

1.2 Applications ......................................................................... 2

1.3 Specifications....................................................................... 2

1.3.1 Analog Input ............................................................... 2

1.3.2 Timebase....................................................................4

1.3.3 Triggers ...................................................................... 5

1.3.4 General Specifications................................................ 6

1.4 Software Support ................................................................. 6

1.4.1 WD-DASK................................................................... 7

1.4.2 LabVIEW Support.......................................................7

1.5 Device Layout and I/O Array................................................ 8

2 Getting Started ................................................................. 11

2.1 Installation Environment .................................................... 11

2.2 Installing the Module.......................................................... 12

3 Operations ........................................................................ 13

3.1 Functional Block Diagram.................................................. 13

3.2 Analog Input Channel ........................................................ 13

3.2.1 Analog Input Front-End Configuration ...................... 13

3.2.2 Input Range and Data Format .................................. 14

3.2.3 DMA Data Transfer................................................... 15

3.2.4 Synchronous Digital Input......................................... 16

3.3 Trigger Source and Trigger Modes.................................... 17

Table of Contents v

3.3.1 Software Trigger ....................................................... 18

3.3.2 External Digital Trigger ............................................. 18

3.3.3 Analog Trigger .......................................................... 18

3.4 Trigger Modes.................................................................... 19

3.4.1 Post Trigger Mode .................................................... 19

3.4.2 Delayed Trigger Mode .............................................. 19

3.4.3 Pre-Trigger Mode...................................................... 20

3.4.4 Middle Trigger Mode................................................. 20

3.4.5 Acquisition with Re-Triggering ..................................21

3.5 Timebase ........................................................................... 22

3.5.1 Internal Sampling Clock............................................ 22

3.5.2 External Reference Clock (PCIe-9814P only) ..........22

3.5.3 External Sampling Clock........................................... 22

3.6 ADC Timing Control ........................................................... 23

3.6.1 Timebase Architecture.............................................. 23

3.6.2 Basic Acquisition Timing........................................... 23

3.7 Synchronizing Multiple Modules ........................................ 25

3.7.2 SSI_TRIG .................................................................28

3.8 SDI..................................................................................... 28

3.9 Multi-boot ........................................................................... 29

A Appendix: Calibration....................................................... 31

A.1 Calibration Constant .......................................................... 31

A.2 Auto-Calibration ................................................................. 31

Important Safety Instructions.............................................. 33

Getting Service ..................................................................... 35

vi Table of Contents

PCIe-9814

List of Figures

Figure 1-1: Analog Input Channel Bandwidth, ±0.2 Vpp............... 4

Figure 1-2: PCIe-9814 Schematic................................................. 8

Figure 1-3: PCIe-9814 I/O Array ................................................... 9

Figure 3-1: Analog Input Architecture ......................................... 13

Figure 3-2: Linked List of PCI Address DMA Descriptors ........... 16

Figure 3-3: Synchronous Digital Input Operations ...................... 17

Figure 3-4: Trigger Architecture .................................................. 17

Figure 3-5: External Digital Trigger ............................................. 18

Figure 3-6: Post-Trigger Acquisition ...........................................19

Figure 3-7: Delayed Trigger Mode Acquisition............................ 20

Figure 3-8: Pre-Trigger Mode Acquisition ................................... 20

Figure 3-9: Middle Trigger Mode Acquisition .............................. 21

Figure 3-10: Re-Trigger Mode Acquisition .................................... 21

Figure 3-11: PCIe-9814 Clock Architecture .................................. 22

Figure 3-12: PCIe-9814 Timebase Architecture ........................... 23

Figure 3-13: Basic Digitizer Acquisition Timing............................. 24

Figure 3-14: Varying Sampling Rates by Adjusting

Scan Interval Counter............................................... 24

Figure 3-15: Card Number Configuration Switch .......................... 27

Figure 3-16: Flash Memory Configuration Switch......................... 29

List of Figures vii

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viii List of Figures

PCIe-9814

List of Tables

Table 1-1: Channel Characteristics................................................... 3

Table 1-2: PCIe-9814 I/O Array Legend ......................................... 10

Table 3-1: Input Range and Data Format ....................................... 14

Table 3-2: Input Range FSR and –FSR Values.............................. 14

Table 3-3: Input Range Midscale Values........................................ 15

Table 3-4: Counter Parameters and Description ............................25

Table 3-5: SSI Signal Location and Pin Definition .......................... 26

Table 3-6: Card Number Configuration Settings............................. 28

Table 3-7: SDI Input vs. Data.......................................................... 28

List of Tables ix

This page intentionally left blank.

x List of Tables

1 Introduction

The ADLINK PCIe-9814 is a 4-channel, 12-bit, 80MS/s PCI
Express digitizer providing speedy, high quality data acquisition.
Each of the four input channels supports up to 80MS/s sampling,
with12-bit resolution A/D converter. 40MHz bandwidth analog
input with 50Ω impedance receives ±0.5V, ±1V, ±5V, and ±10V
high speed signals, and a simplified front end and highly stable
onboard reference provide both highly accurate measurement
results and high dynamic performance.

The PCIe-9814, based on x4 lane slot PCI Express technology,
can be used in any standard PCI Express slot, x4, x8, or x16. With
a PCI Express bus interface and extremely large onboard memory
(up to 1GB), the PCIe-9814 easily manages simultaneous 4-CH
data streaming even at the highest sampling rates.

The PCIe-9814 is auto-calibrated with an onboard reference cir­cuit calibrating offset and acquiring analog input errors. Following
auto-calibration, the calibration constant is stored in EEPROM,
such that these values can be loaded and used as needed by the
board. There is no requirement to calibrate the module manually.

PCIe-9814

1.1 Features

X Up to 80MS/s sampling

X 4 simultaneous analog inputs

X High resolution 12-bit ADC

X Up to 40 MHz bandwidth for analog input

X 1GB onboard storage

X Programmable input voltage of ±0.5V, ±1V, ±5V, or ±10V

X Scatter/gather DMA data transfer for high speed streaming

X 10 or 20MHz digital onboard filter (FPGA)

X PLL module provides precise synch (PCIe-9814P only)

X Supports:

Z One external digital trigger input

Z One external clock input

Z Three SDI inputs

X Full auto-calibration

Introduction 1

1.2 Applications

X Testing/monitoring for Energy Management applications,

including:

Z Partial discharge

Z Power line/device monitoring

X Non-destructive testing

X Radar acquisition

X LiDAR

1.3 Specifications

1.3.1 Analog Input

Item Detail Comments

Channels 4 single-ended

Connector type SMB

input coupling DC

ADC resolution 12-Bit

input signal range ±0.5 V, ±1 V, ± 5V, or ± 10V

Bandwidth(-3dB) 40MHz

±10V sine wave / 7 Vrms 50Ω, all ranges

Overvoltage

input impedance

Offset error

Gain error

±10V 1M Ω, ±0.5V or ±1V

±30V 1M Ω, ±5V or ±10V

50 Ω or 1M Ω, software
selectable

±0.5 mV ±0.5V, ±1V

±4 mV ±5V

±10 mV ±10V

50Ω

±1% for all ranges

1MΩ

±0.5% for other ranges

±1% ±10V

2 Introduction

PCIe-9814

Item Detail Comments

150 μV ±0.5V

System Noise
(RMS)

AC Dynamic Performance (10MHz, -1dBFS input signal)

50Ω with filter OFF

SNR 64dB ±0.5V, ±1V, ±5V

THD -74dB ±0.5V, ±1V, ±5V

SFDR 76dB ±0.5V, ±1V, ±5V

1MΩ with filter OFF

SNR 64dB ±0.5V, ±1V, ±5V, ±10V

THD

SFDR

50Ω with filter ON

SNR 65dB ±0.5V, ±1V, ±5V

THD -93dB ±0.5V, ±1V, ±5V

SFDR 78dB ±0.5V, ±1V, ±5V

1MΩ with filter ON

SNR 65dB ±0.5V, ±1V, ±5V, ±10V

THD -93dB

SFDR 78dB

Crosstalk

300 μV ±1.0V

1.5 mV ±5V

2.5 mV ±10V

-71dB ±10V

-73dB ±5V

-75dB ±0.5V, ±1V

72dB ±10V

74dB ±5V

76dB ±0.5V, ±1V

±10V

±5V

±0.5V, ±1V

±10V

±5V

±0.5V, ±1V

-80dB ±0.5V

-90dB ±1V, ±5V, ±10V

Table 1-1: Channel Characteristics

Introduction 3

0

-1

-2

-3

dB

-4

-5

-6

-7

3

10

Figure 1-1: Analog Input Channel Bandwidth, ±0.2 Vpp

1.3.2 Timebase

±5V

±1V

±0.5V

10

&+%DQGZLGWKȍ

4

10

5

Hz

10

6

10

7

10

8

Sample Clock Detail Comment

Timebase options

Internal : onboard crystal
oscillator

External : CLK IN (front panel)

1.22kS/s to
80MS/s

Sampling clock
frequency

Internal : 80MHz

External : 20MHz to 80MHz (CLK
IN)

Timebase accuracy < ± 25ppm

4 Introduction

Sample Clock Detail Comment

External reference
clock source

External reference
clock

External reference
clock input range

External sampling
clock input range

SDI0 (supported by PCI-9814P
only)

10MHz

3.3V to 5V TTL DC compliant

1Vpp to 5Vpp

AC / DC
compliant

1.3.3 Triggers

Trigger Source & Mode

Trigger source

Trigger mode

Digital Trigger Input

Sources Front panel SMB connector

Compatibility 3.3 V TTL, 5 V tolerant

Input high threshold 2.0 V

Input low threshold (VIL) 0.8 V

Maximum input overload -0.5 V to +5.5 V

Trigger polarity Rising or falling edge

Pulse width 20 ns minimum

Software, external digital trigger, analog trigger, and SSI
(system synchronized interface)

Post trigger, delay trigger, pre-trigger, or middle trigger,
re-trigger for post trigger and delay trigger modes

PCIe-9814

Introduction 5

1.3.4 General Specifications

Specifications

Dimensions 167.64 W x 106.68 H mm (6.53 x 4.16 in)

Bus interface PCI Express Gen 1 x 4

Operating

Storage

Calibration

Onboard reference +1.8V, +0.9V, and +0.45V

Temperature coefficient 1.0 ppm/°C

Warm-up time 15 minutes

Power Consumption

Power Rail

3.3V 20 20 20 20

12V 425 505 655 715

Total RMS
Power (W)

Standby
current (mA)

5.116 6.126 7.926 8.646

Temperature: 0°C - 50°C
Relative humidity: 5% - 95%, non-condensing

Temperature: -20°C - +80°C
Relative humidity: 5% - 95%, non-condensing

PCIe-9814 PCIe-9814P

Full load
(mA)

Standby
current (mA)

Full load
(mA)

1.4 Software Support

ADLINK provides versatile software drivers and packages to suit
various user approaches to building a system. Aside from pro­gramming libraries, such as DLLs, for most Windows-based sys­tems, ADLINK also provides drivers for other application
environments such as LabVIEW®.

All software options are included in the ADLINK All-in-One CD.
Commercial software drivers are protected with licensing codes.
Without the code, you may install and run the demo version for

6 Introduction

PCIe-9814

trial/demonstration purposes for only up to two hours. Contact
your ADLINK dealer to purchase the software license.

1.4.1 WD-DASK

WD-DASK includes device drivers and DLL for Windows XP/7/8.
DLL is binary compatible across Windows XP/7/8. This
means all applications developed with WD-DASK are compati­ble with these Windows operating systems. The development
environment may be VB, VB.NET, VC++, BCB, and Delphi, or
any Windows programming language that allows calls to a DLL.
The WD-DASK user and function reference manuals are on the
ADLINK All-in-One CD.

1.4.2 LabVIEW Support

For customers who want to write their own programs in LabVIEW,
a LabVIEW library toolkit, DAQPilot, is provided, with a newly
architected DAQLite package to support PCIe-9814 card use.

Introduction 7

1.5 Device Layout and I/O Array

All dimensions are in mm

NOTE:

NOTE:

100.36

59.05

169.55

Figure 1-2: PCIe-9814 Schematic

The PCIe-9814 I/O array is labeled to indicate connectivity, as
shown.

98.4

8 Introduction

PCIe-9814

Figure 1-3: PCIe-9814 I/O Array

All I/O connectors are SMB Snap-on type.

Introduction 9

Input

Analog CH0

Analog CH1

Analog CH2

Analog CH3

Ext. Clock CLK

Ext. Digital
Trigger

Synced Digital SDI0 3 SDI bits (bit 0:2) and ADC data

Synced Digital SDI1

Synced Digital SDI2

Faceplate
Label

TRG

Remark

Analog Input Channel

Input for external sample clock to
digitizer

External digital trigger input,
receiving trigger signal from
external instrument and initiating
acquisition

are combined into one register and
transferred to host PC by DMA.
Refer to Chapter 3 for detailed data
format.
Optional: For PCIe-9814P (with
PLL module), SDI0 can be used to
receive an external reference 10M
Hz to generate ADC timebase.
Please see Section 3.5.2 External
Reference Clock (PCIe-9814P
only) for more information.

Table 1-2: PCIe-9814 I/O Array Legend

10 Introduction

2 Getting Started

This chapter describes proper installation environment, installation
procedures, package contents and basic information users should
be aware of regarding the PCIe-9814.

Diagrams and illustrated equipment are for reference only.
Actual system configuration and specifications may vary.

NOTE:

NOTE:

2.1 Installation Environment

When unpacking and preparing to install, please refer to Important
Safety Instructions.

Only install equipment in well-lit areas on flat, sturdy surfaces with
access to basic tools such as flat- and cross-head screwdrivers,
preferably with magnetic heads as screws and standoffs are small
and easily misplaced.

Recommended Installation Tools

X Phillips (cross-head) screwdriver

X Flat-head screwdriver

X Anti-static wrist strap

X Antistatic mat

ADLINK PCIe-9814 DAQ modules are electrostatically sensitive
and can be easily damaged by static electricity. The module must
be handled on a grounded anti-static mat. The operator must wear
an anti-static wristband, grounded at the same point as the anti­static mat.

PCIe-9814

Getting Started 11

Inspect the carton and packaging for damage. Shipping and han­dling could cause damage to the equipment inside. Make sure that
the equipment and its associated components have no damage
before installation.

The equipment must be protected from static discharge and
physical shock. Never remove any of the socketed parts

CAUTION:

except at a static-free workstation. Use the anti-static bag
shipped with the product to handle the equipment and wear a
grounded wrist strap when servicing.

X Package Contents

X PCIe-9814 digitizer

X ADLINK All-in-one compact disc

X PCIe-9814 Quick Start Guide

If any of these items are missing or damaged, contact the dealer

Do not install or apply power to equipment that is damaged or
missing components. Retain the shipping carton and packing
materials for inspection. Please contact your ADLINK dealer/
vendor immediately for assistance and obtain authorization
before returning any product.

2.2 Installing the Module

1. Turn off the computer.

2. Remove the top cover.

3. Select an available PCI express x4 slot and remove the
bracket-retaining screw and the bracket cover.

4. Line up the PCI express digitizer with the PCI express
slot on the back panel. Slowly push down on the top of
the PCI express digitizer until its card-edge connector is
resting on the slot receptacle.

5. Install the bracket-retaining screw to secure the PCI
express digitizer to the back panel rail.

6. Replace the computer cover.

12 Getting Started

3 Operations

This chapter contains information regarding analog input, trigger­ing and timing for the PCIe-9814.

3.1 Functional Block Diagram

SSI

CH0

PCIe-9814

CH1

CH2

CH3

CLK IN

TRG IN

SDI0

SDI1

SDI2

Analog

Front-End

Calibration

12 Bit ADC

Clock

Distribution

Buffer

4

3.2 Analog Input Channel

3.2.1 Analog Input Front-End Configuration

Calibration

Source

Anti-aliasing

50Ω /
Hi-Z

Attenuator

High Impe dance

Bue r

ADC D rive r

Filter

FPGA

12-bit A DC

0

0

PCIe Interface

0

0

0

12

Figure 3-1: Analog Input Architecture

Input Configuration

The input channel terminates with equivalent 50Ω or 1MΩ input
impedance (selected by software). The 12-bit ADC provides

Operations 13

not only accurate DC performance but also high signal-to-noise
ratio, and high spurious-free dynamic range in AC perfor­mance. The ADC transfers data to system memory via the high
speed PCI Express Gen 1 X 4 interface.

For auto-calibration, internal calibration provides stable and
accurate reference voltage to the AI.

3.2.2 Input Range and Data Format

Data format of the PCIe-9814 is 2’s complement. The ADC data of
PCIe-9814 is on the 12 MSB of the 16-bit A/D data. D2 to D0 is
SDI2 to SDI0, with D3 disregarded. A/D data structure is as fol­lows.

D15 D14 D13 D12 …. D3 D2 D1 D0

D15 to D4 bits represent the data from ADC (2’s complement)
D2 is SDI2, D1 SDI1, D0 SDI0, and D3 is disregarded

Table 3-1: Input Range and Data Format

Description

Bipolar Analog
Input

Digital Code N/A N/A 7FF0 8000

Comment SDI bit is assumed to be 0

14 Operations

Full scale
range

±10V 4.88mV 9.9512V -10V

±5V 2.44mV 4.99756V -5V

±1V 0.488mV 0.99512V -1V

±0.5V 0.244mV 0.499756V -0.5V

Table 3-2: Input Range FSR and –FSR Values

Least
significant
bit

FSR-1LSB -FSR

PCIe-9814

Description Midscale +1LSB Midscale Midscale -1LSB

4.88mV 0V -4.88mV

Bipolar Analog
Input

Digital Code 0001 0000 FFF0

Comment SDI bit is assumed to be 0

2.44mV 0V -2.44mV

0.488mV 0V -0.488mV

0.244mV 0V -0.244mV

Table 3-3: Input Range Midscale Values

3.2.3 DMA Data Transfer

The PCIe-9814, a PCIe Gen 1 X 4 device, is equipped with a
200MS/s high sampling rate ADC, generating a 640 MByte/
second rate.

To provide efficient data transfer, a PCI bus-mastering DMA is
essential for continuous data streaming, as it helps to achieve full
potential PCI Express bus bandwidth. The bus-mastering control­ler releases the burden on the host CPU since data is directly
transferred to the host memory without intervention. Once analog
input operation begins, the DMA returns control of the program.
During DMA transfer, the hardware temporarily stores acquired
data in the onboard AD Data FIFO, and then transfers the data to
a user-defined DMA buffer in the computer.

Using a high-level programming library for high speed DMA data
acquisition, the sampling period and the number of conversions
needs simply to be assigned into specified counters. After the AD
trigger condition is met, the data will be transferred to the system
memory by the bus-mastering DMA.

In a multi-user or multi-tasking OS, such as Microsoft Windows,
Linux, or other, it is difficult to allocate a large continuous memory
block. Therefore, the bus controller provides DMA transfer with
scatter-gather function to link non-contiguous memory blocks into
a linked list so users can transfer large amounts of data without

Operations 15

being limited by memory limitations. In non-scatter-gather mode,
the maximum DMA data transfer size is 2 MB double words (8 MB
bytes); in scatter-gather mode, there is no limitation on DMA data
transfer size except the physical storage capacity of the system.

Users can also link descriptor nodes circularly to achieve a multi­buffered DMA. Figure 3-2 illustrates a linked list comprising three
DMA descriptors. Each descriptor contains a PCI address, PCI
dual address, a transfer size, and the pointer to the next descrip­tor. PCI address and PCI dual address support 64-bit addresses
which can be mapped into more than 4 GB of address space, but
the subsequent descriptor address must be less than 4GB.

First PCI Address

First Dual Address

Transfer Size

Next Descriptor

Figure 3-2: Linked List of PCI Address DMA Descriptors

PCI Address

Dual Address

Transfer Size

Next Descriptor

PCI Express Bus

Local Memory

(FIFO)

PCI Address

Dual Address

Transfer Size

Next Descriptor

3.2.4 Synchronous Digital Input

The PCIe-9814 has three synchronous digital input channels,
SDI0, SDI1 and SDI1. These three digital input lines can be sam­pled synchronously with the Timebase clock for mixed signal
applications. Thus the data transfer can reach 80 Mbit/s when
using internal 80 MS/s Timebase clock. These three digital input
lines are combined with ADC data and located in 3 LSB when SDI
function is enabled, as shown.

16 Operations

SDI0

SDI1

SDI2

D Flip Flop

D

CLK

D Flip Flop

D

CLK

D Flip Flop

D

CLK

PCIe-9814

Q

Q

Q

Bit 15 Bit 0

Bit 1Bit 2Bit 3

ADC Data

Timebase

CLK

Analog Input

AFE

Data

ADC

Figure 3-3: Synchronous Digital Input Operations

3.3 Trigger Source and Trigger Modes

This section details PCIe-9814 triggering operations.

Software Trigger

Digital Trigger Input

SSI Trigger

Trigger

Decision

X

To Internal FPGA

(Master => Slave)

(Master <= Slave)

SDI0SDI1SDI2

SSI

Figure 3-4: Trigger Architecture

The PCIe-9814 requires a trigger to implement acquisition of data.
Configuration of triggers requires identification of trigger

Operations 17

source. The PCIe-9814 supports internal software trigger,
external digital trigger, and analog trigger.

3.3.1 Software Trigger

The software trigger, generated by software command, is
asserted immediately following execution of specified function
calls to begin the operation.

3.3.2 External Digital Trigger

An external digital trigger is generated when a TTL rising edge

or falling edge is detected at the SMB connector TRG IN on the
front panel. As shown, trigger polarity can be selected by soft­ware. Note that the signal level of the external digital trigger
signal should be TTL compatible, and the minimum pulse width
20 ns.

Pulse Width > 20ns

Pulse Width > 20ns

Rising Edge Trigger Event Falling Edge Trigger Event

Figure 3-5: External Digital Trigger

3.3.3 Analog Trigger

An analog trigger is generated when AI input signal level is
detected at the SMB connectors CH0 to CH3 (selected by soft­ware). The trigger level is also selected by software.

18 Operations

PCIe-9814

3.4 Trigger Modes

Trigger modes applied to trigger sources initiate different data
acquisition timings when a trigger event occurs. The following trig­ger mode descriptions are applied to analog input function.

3.4.1 Post Trigger Mode

Post-trigger acquisition is applicable when data is to be collected
after the trigger event, as shown. When the operation starts, PCIe­9814 waits for a trigger event. Once the trigger signal is received,
acquisition begins. Data is generated from ADC and transferred to
system memory continuously. The acquisition stops once the total
data amount reaches a predefined value.

Figure 3-6: Post-Trigger Acquisition

3.4.2 Delayed Trigger Mode

Delayed-trigger acquisition is utilized to postpone data collection
after the trigger event, as shown. When PCIe-9814 receives a trig­ger event, a time delay is implemented before commencing acqui­sition. The delay is specified by a 16-bit counter value such that a
maximum thereof is the period of TIMEBASE X (216), and the min­imum is the Timebase period.

Operations 19

Figure 3-7: Delayed Trigger Mode Acquisition

3.4.3 Pre-Trigger Mode

Collects data before the trigger event, starting once specified func­tion calls are executed to begin the pre-trigger operation, and
stopping when the trigger event occurs. If the trigger event occurs
after the specified amount of data has been acquired, the system
stores only data preceding the trigger event by a specified
amount, as follows.

Operation start
Acquisition start

Trigger

Data

Trigger signals occuring before the specified
amount of data has been acquired are ignored

X samples have been acquired
before trigger occurs, where X<N

N samples

Trigger Event Occurs
Acquisition stop
Data transfer to system begins

Time

Figure 3-8: Pre-Trigger Mode Acquisition

3.4.4 Middle Trigger Mode

Collects data before and after the trigger event, with the amount to
be collected set individually (M and N samples), as follows

20 Operations

PCIe-9814

Operation start
Acquisition start

Trigger

Data

Trigger event occurs

Acquisition stop
Data transfer to system begins

N samplesM samples

Figure 3-9: Middle Trigger Mode Acquisition

3.4.5 Acquisition with Re-Triggering

A digitizer acquires a trace of N samples/channel for a single
acquisition. Re-Trigger mode can also be set to automatically
acquire R traces, containing N*R samples/channel of data, without
additional software intervention.

The Re-Trigger setting can be used for Post-Trigger and Delayed­Trigger modes, with different limitations on the spacing between
trigger events in each mode. Trigger events arriving too close to
the previous instance will be ignored by the digitizer.

X In Post-Trigger mode, the minimum spacing between trigger

events is N+1

X In Delayed-Trigger mode, the minimum spacing between

trigger events is (N+D)+1, where D is the number of the
delayed setting

Time

Figure 3-10: Re-Trigger Mode Acquisition

Operations 21

3.5 Timebase

CLK IN

To ADC

80M Xtal

Synthesizer

SDI0

Figure 3-11: PCIe-9814 Clock Architecture

3.5.1 Internal Sampling Clock

The PCIe-9814 internal 80MHz crystal oscillator acts as a sam­pling clock for ADC.

3.5.2 External Reference Clock (PCIe-9814P only)

The PCIe-9814P's onboard PLL module allows SDI0 to act as an
external reference clock. Synthesizer input switches to the clock
source at SMB connector SDI0, generating precisely 80MHz clock
for ADC.

Board

3.5.3 External Sampling Clock

The PCIe-9814 can further choose an external clock source as
ADC sampling clock. When an external sampling clock is selected,
the ADC sampling frequency switches to the clock source at SMB
Connector CLK IN, and clock source frequency is available from
20MHz to 80MHz. Be advised that if the frequency of the external
sample clock is changed, the LVDS timebase requires recalibra­tion.

To do so, call WD-DASK function: WD_AI_Config().

22 Operations

PCIe-9814

For more information, refer to the WD-DASK Function Library Ref­erence.

3.6 ADC Timing Control

3.6.1 Timebase Architecture

X6

Onboard

80MHz

Oscillator

ADC

ADC Output

80MHz

Multiplier

480MHz

PLL

80MHz

FPGA

Figure 3-12: PCIe-9814 Timebase Architecture

3.6.2 Basic Acquisition Timing

The PCIe-9814 commences acquisition upon receipt of a trigger
event originating with software command, external digital trigger.
The Timebase is a clock provided to the ADC and acquisition
engine for essential timing. The Timebase is from an onboard syn­thesizer. To achieve different sampling rates, a scan interval coun­ter is used.

Using the post-trigger mode as an example, as shown, when a
trigger is accepted by the digitizer, the acquisition engine com­mences acquisition of data from ADC, and stores the sampled
data to the onboard FIFO. When FIFO is not empty, data will be
transferred to system memory immediately through the DMA
engine. The sampled data is generated continuously at the rising
edge of Timebase according to the scan interval counter setting.
When sampled data reaches a specified value, in this example
256, acquisition ends.

For ADC

Data Bus

For ADC

State machine

Operations 23

Analog

signal

TIMEBASE

Trigger

Acquisition
In Progress

DATA

Trigger mode = post-trigger, DataCnt = 256, ScanIntrv = 1

Acquisition initiates following this clock edge

D3 D4 D255

D2

D1

D253

D254

D256

Figure 3-13: Basic Digitizer Acquisition Timing

To achieve sampling rates other than 80MS/s, a number for scan
interval counter needs only be specified. For example, if the scan
interval counter is set as 2, the equivalent sampling rate is 80MS/s
/ 2 = 40MS/s. If as 3, the equivalent sampling rate is 80MS/s / 3 =

26.66MS/s, and vice versa. The scan interval counter is 16 bits in
width, therefore the lowest sampling rate is 1.221kS/s (80MS/s /

65535).

Trigger

TIMEBASE

DATA

ScanIntrv = 1

ScanIntrv = 2

ScanIntrv = 3

Acquisition
In Progress

D2

D1

D1

D1

Acquisition is initiated following this clock edge

D4

D3

D2 D3 D4 D5 D6

D5

D2 D3 D4

D6

D8

D7

D10

D9

Figure 3-14: Varying Sampling Rates by Adjusting Scan Interval Counter

24 Operations

PCIe-9814

Counter
Name

ScanIntrv 16-bit 1-65535

DataCnt 31-bit 1-2147483647

trigDelayTicks 16-bit 1 -65535

ReTrgCnt 31-bit 1-2147483647

Length Valid Value Description

Timebase divider to achieve
equivalent sampling rate of the
digitizer, where Sampling rate =
Timebase / ScanIntrv

Specifies the amount of data to
be acquired:
1 - 2147483648 for pre-trig or
mid-trig mode operation

Indicates time between a trigger
event and commencement of
acquisition. The unit of a delay
count is the period of the
Timebase.

Enables re-trigger to accept
multiple triggers.
1 - 2147483647 for normal
operation
See Section 3.4.5: Acquisition
with Re-Triggering

Table 3-4: Counter Parameters and Description

3.7 Synchronizing Multiple Modules

The PCIe-9814 provides a dedicated connector as system syn­chronization interface, enabling multiple module synchroniza­tion. As shown, bi-directional SSI I/Os provides a flexible
connection between modules, allowing one SSI master PCIe-9814
to output SSI signals to other slave modules.For more accurate
synchronization between modules, external sampling clock or
external reference clock should be applied.

The table summarizes SSI functionalities.

Different signals cannot be routed onto the same trigger bus
line.

NOTE:

NOTE:

Operations 25

SSI Timing Signal Function

SSI Trig Input/output trigger signal through SSI

All SSI signals are routed to the 16-pin connector from
FPGA, enabling multi-module synchronization. ACL-eSSI-2/
ACLeSSI-3/ACL-eSSI-4 cables can be used to synchronize 2, 3,
or 4 modules.

Signal Direction Descr. Pin

SSI Trig Input/Output

GND Ground

Reserved Input/Output Reserved for future use 3, 5,7

Trigger signal through
SSI

1, 9,
11, 13,
15

2, 4, 6,
8, 10,
12, 14,
16

Table 3-5: SSI Signal Location and Pin Definition

3.7.1 Card Number Configuration

When multiple cards are used in a single chassis, card number
configuration via switch, as shown.

26 Operations

PCIe-9814

34

ON DIP

12

Figure 3-15: Card Number Configuration Switch

When all sliders are in ON position, card number is 15, when all
are OFF, card number is 0, as shown.

Slider 1 Slider 2 Slider 3 Slider 4 Card #

OFF OFF OFF OFF 0

OFF OFF OFF ON 1

OFF OFF ON OFF 2

OFF OFF ON ON 3

OFF ON OFF OFF 4

OFF ON OFF ON 5

OFF ON ON OFF 6

OFF ON ON ON 7

ON OFF OFF OFF 8

Operations 27

Slider 1 Slider 2 Slider 3 Slider 4 Card #

ON OFF OFF ON 9

ON OFF ON OFF 10

ON OFF ON ON 11

ON ON OFF OFF 12

ON ON OFF ON 13

ON ON ON OFF 14

ON ON ON ON 15

Table 3-6: Card Number Configuration Settings

Default card number is 15.

3.7.2 SSI_TRIG

As an output, the SSI_TRIG signal reflects the trigger event signal
in an acquisition sequence. As an input, the PCIe-9814 accepts
the SSI_TRIG signal to be the trigger event source. The signal is
configured in the rising edge-detection mode.

3.8 SDI

In some applications, marks may need to be added to some data.
The PCIe-9814 uses SDI to accomplish this. The lowest 3 LSBs
correspond to the logic level of SDI2 to SDI0.

SDI2 SDI1 SDI0 Data at midscale

Low Low Low 0000

Low Low High 0001

Low High Low 0002

Low High High 0003

High Low Low 0004

High Low High 0005

High High Low 0006

High High High 0007

Table 3-7: SDI Input vs. Data

28 Operations

PCIe-9814

3.9 Multi-boot

The PCIe-9814 supports software-based firmware updates. If firm­ware updates fail, the system may be unable to recognize the
module, in which case the following steps may solve the problem.

1. Config SW2 to "on"

2. Install the module and restart the system

3. If the module is recognized, update firmware again

(ensure the firmware you updated is workable)

4. Turn off the system, config SW2 to "off" and restart the

system.

The default state of SW2 is "off".

If the problem remains, please contact FAE.

Figure 3-16: Flash Memory Configuration Switch

Operations 29

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30 Operations

Appendix A Calibration

This chapter introduces the calibration process to minimize analog
input measurement errors.

A.1 Calibration Constant

The PCIe-9814 is factory calibrated before shipment, with associ­ated calibration constants written to the onboard EEPROM. At
system boot, the PCIe-9814 driver loads these calibration con­stants, such that analog input path errors are minimized. ADLINK
provides a software API for calibrating the PCIe-9814.

The onboard EEPROM provides two banks for calibration con­stant storage. Bank 0, the default bank, records the factory cali­brated constants, providing written protection preventing
erroneous auto-calibration. Bank 1 is user-defined space, pro­vided for storage of self-calibration constants. Upon execution of
auto-calibration, the calibration constants are recorded to Bank 1.

When PCIe-9814 boots, the driver accesses the calibration con­stants and is automatically set to hardware. In the absence of user
assignment, the driver loads constants stored in bank 0. If con­stants from Bank 1 are to be loaded, the preferred bank can be
designated as boot bank by software. Following re-assignment of
the bank, the driver will load the desired constants on system re­boot. This setting is recorded to EEPROM and is retained until re­configuration.

PCIe-9814

A.2 Auto-Calibration

Because errors in measurement and outputs will vary with time
and temperature, re-calibration is recommended when the module
is installed. Auto-calibration can measure and minimize errors
without external signal connections, reference voltages, or mea­surement devices.

The PCIe-9814 has an on-board calibration reference to ensure
the accuracy of auto-calibration. The reference voltage is mea­sured on the production line and recorded in the on-board
EEPROM.

Calibration 31

Before initializing auto-calibration, it is recommended to warm up
the PCIe-9814 for at least 20 minutes and remove connected
cables.

It is not necessary to manually factor delay into applications, as
the PCIe-9814 driver automatically adds the compensation

NOTE:

NOTE:

time.

32 Calibration

PCIe-9814

Important Safety Instructions

For user safety, please read and follow all instructions,
WARNINGS, CAUTIONS, and NOTES marked in this manual and

on the associated equipment before handling/operating the
equipment.

X Read these safety instructions carefully.

X Keep this user’s manual for future reference.

X Read the specifications section of this manual for detailed

information on the operating environment of this equipment.

X When installing/mounting or uninstalling/removing

equipment:

Z Turn off power and unplug any power cords/cables.

X To avoid electrical shock and/or damage to equipment:

Z Keep equipment away from water or liquid sources;

Z Keep equipment away from high heat or high humidity;

Z Keep equipment properly ventilated (do not block or

cover ventilation openings);

Z Make sure to use recommended voltage and power

source settings;

Z Always install and operate equipment near an easily

accessible electrical socket-outlet;

Z Secure the power cord (do not place any object on/over

the power cord);

Z Only install/attach and operate equipment on stable

surfaces and/or recommended mountings; and,

Z If the equipment will not be used for long periods of time,

turn off and unplug the equipment from its power source.

Important Safety Instructions 33

X Never attempt to fix the equipment. Equipment should only

be serviced by qualified personnel.

X A Lithium-type battery may be provided for uninterrupted,

backup or emergency power.

Risk of explosion if battery is replaced with an incorrect type;
please dispose of used batteries appropriately.

X Equipment must be serviced by authorized technicians

when:

Z The power cord or plug is damaged;

Z Liquid has penetrated the equipment;

Z It has been exposed to high humidity/moisture;

Z It is not functioning or does not function according to the

user’s manual;

Z It has been dropped and/or damaged; and/or,

Z It has an obvious sign of breakage.

34 Important Safety Instructions

Getting Service

Contact us should you require any service or assistance.

ADLINK Technology, Inc.

Address: 9F, No.166 Jian Yi Road, Zhonghe District
New Taipei City 235, Taiwan

ᄅקؑխࡉ೴৬ԫሁ 166 ᇆ 9 ᑔ

Tel: [phone]
Fax: [phone]
Email: [e-mail]

Ampro ADLINK Technology, Inc.

Address: 5215 Hellyer Avenue, #110
San Jose, CA 95138, USA
Tel: [phone]
Toll Free: [phone] (USA only)
Fax: [phone]
Email: [e-mail]

ADLINK Technology (China) Co., Ltd.

Address: Ϟ⍋Ꮦ⌺ϰᮄᓴ∳催⾥ᡔು㢇᯹䏃 300 ো(201203)
300 Fang Chun Rd., Zhangjiang Hi-Tech Park

Pudong New Area, Shanghai, 201203 China
Tel: [phone]
Fax: [phone]
Email: [e-mail]

PCIe-9814

ADLINK Technology Beijing

Address: ࣫ҀᏖ⍋⎔Ϟഄϰ䏃 1 োⲜ߯ࡼ࡯໻ E ᑻ 801 ᅸ(100085)

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Fax: [phone]
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Address: ⏅ഇᏖቅ⾥ᡔು催ᮄϗ䘧᭄ᄫᡔᴃು

Tel: [phone]
Fax: [phone]
Email: [e-mail]

LiPPERT ADLINK Technology GmbH

Address: Hans-Thoma-Strasse 11, D-68163
Mannheim, Germany
Tel: [phone]
Fax: [phone]
Email: [e-mail]

Rm. 801, Power Creative E, No. 1 Shang Di East Rd.

A1 󰶀 2 ὐ C  (518057)

2F, C Block, Bldg. A1, Cyber-Tech Zone, Gao Xin Ave. Sec. 7

High-Tech Industrial Park S., Shenzhen, 518054 China

Getting Service 35

ADLINK Technology, Inc. (French Liaison Office)

Address: 6 allée de Londres, Immeuble Ceylan
91940 Les Ulis, France
Tel: [phone]
Fax: [phone]
Email: [e-mail]

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Address: 〒101-0045 東京都千代田区神田鍛冶町 3-7-4

Tel: [phone]
Fax: [phone]
Email: [e-mail]

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Address: 137-881 서울시 서초구 서초대로 326, 802 (서초동, 모인터빌딩)

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Fax: [phone]
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ADLINK Technology Singapore Pte. Ltd.

Address: 84 Genting Lane #07-02A, Cityneon Design Centre

Tel: [phone]
Fax: [phone]
Email: [e-mail]

ADLINK Technology Singapore Pte. Ltd. (Indian Liaison Office)

Address: #50-56, First Floor, Spearhead Towers

Malleswaram, Bangalore - 560 055, India
Tel: [phone]
Fax: [phone]
Email: [e-mail]

神田 374 ビル 4F
KANDA374 Bldg. 4F, 3-7-4 Kanda Kajicho,
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802, Mointer B/D, 326 Seocho-daero, Seocho-Gu,
Seoul 137-881, Korea

Singapore 349584

Margosa Main Road (between 16th/17th Cross)

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Address: 27 Maskit St., Corex Building
PO Box 12777
Herzliya 4673300, Israel
Tel: [phone]
Fax: [phone]
Email: [e-mail]

ADLINK Technology, Inc. (UK Liaison Office)

Tel: [phone]
Email: [e-mail]

ice)

36 Getting Service