ADLINK PCIe-7360 User Manual
PCIe-7360
100 MHz 32-CH High-Speed Digital I/O Card
User’s Manual
Manual Rev.: 2.00
Revision Date: Aug. 2, 2013
Part No: 50-11042-1000
Advance Technologies; Automate the World.
Revision History
Revision Release Date Description of Change(s)
2.00 Aug. 2, 2013 Initial release
ii
PCIe-7360
Preface
Copyright ©2013 ADLINK Technology, Inc.
This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form
without prior written permission of the manufacturer.
Disclaimer
The information in this document is subject to change without prior
notice in order to improve reliability, design, and function and does
not represent a commitment on the part of the manufacturer.
In no event will the manufacturer be liable for direct, indirect, special, incidental, or consequential damages arising out of the use or
inability to use the product or documentation, even if advised of
the possibility of such damages.
Environmental Responsibility
ADLINK is committed to fulfill its social responsibility to global
environmental preservation through compliance with the European Union's Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE)
directive. Environmental protection is a top priority for ADLINK.
We have enforced measures to ensure that our products, manufacturing processes, components, and raw materials have as little
impact on the environment as possible. When products are at their
end of life, our customers are encouraged to dispose of them in
accordance with the product disposal and/or recovery programs
prescribed by their nation or company.
Trademarks
Product names mentioned herein are used for identification purposes only and may be trademarks and/or registered trademarks
of their respective companies.
Preface iii
Conventions
Take note of the following conventions used throughout this
manual to make sure that users perform certain tasks and
instructions properly.
Additional information, aids, and tips that help users perform
tasks.
NOTE:
NOTE:
Information to prevent minor physical injury, component damage, data loss, and/or program corruption when trying to com-
CAUTION:
WARNING:
plete a task.
Information to prevent serious physical injury, component
damage, data loss, and/or program corruption when trying to
complete a specific task.
iv Preface
PCIe-7360
Table of Contents
Revision History...................................................................... ii
Preface .................................................................................... iii
List of Figures ....................................................................... vii
List of Tables.......................................................................... ix
1 Introduction ........................................................................ 1
1.1 Features............................................................................... 1
1.2 Applications ......................................................................... 1
1.3 Specifications....................................................................... 2
1.4 Software Support ............................................................ 11
DAQPilot ....................................................................... 11
PCIS-DASK .................................................................. 11
1.5 Schematics, I/O and Indicators.......................................... 12
1.6 Connectors ........................................................................ 12
1.7 LED indicator ..................................................................... 17
2 Getting Started ................................................................. 19
2.1 Unpacking Checklist .......................................................... 19
2.2 Installing the Card.............................................................. 19
2.3 Selecting Cables and Termination Board .......................... 20
3 Operations ........................................................................ 21
3.1 Block Diagram ................................................................... 21
3.2 Programmable Logic Level ................................................ 22
3.3 Digital I/O Configuration..................................................... 23
DI Raw Data Mapping ................................................... 24
3.4 Sample Clock Phase Shift ................................................. 27
3.5 Bus-mastering DMA Data Transfer.................................... 29
Table of Contents v
3.6 Sample Clock..................................................................... 31
Digital Input (DI) Sample Clock ..................................... 31
Digital Output (DO) Sample Clock ................................ 33
3.7 Operating Modes ............................................................... 35
Polling Mode (Single Read/Write) ................................. 35
DI DMA in Continuous Mode ........................................ 35
DO DMA in Continuous Mode ......................................38
DI DMA in Handshake Mode ........................................ 41
DO DMA in Handshake Mode ......................................44
DI DMA in Burst Handshake Mode ...............................47
DO DMA in Burst Handshake Mode ............................. 50
DO DMA in Burst Handshake Mode 2 .......................... 53
3.8 Trigger Source and Trigger Mode...................................... 54
3.9 Application Function I/O..................................................... 57
I2C Master .................................................................... 62
SPI Master .................................................................... 64
External Digital Trigger ................................................. 67
Trigger Out .................................................................... 68
Event Out ......................................................................69
Handshake .................................................................... 70
Sample Clock In/Out .....................................................71
3.10 Pattern Match..................................................................... 72
3.11 COS (Change of State) Event............................................ 74
3.12 Termination........................................................................ 75
AppendixA ADLINK DIN-68H .......................................... 77
Important Safety Instructions.............................................. 81
Getting Service ..................................................................... 83
vi Table of Contents
PCIe-7360
List of Figures
Figure 1-1: Acquisition Timing Diagram ............................................. 7
Figure 1-2: Generation Timing Diagram............................................. 8
Figure 1-3: PCIe-7360 Schematic Diagram ..................................... 12
Figure 1-4: PCIe-7360 Connectors .................................................. 13
Figure 3-1: PCIe-7360 Block Diagram ............................................. 22
Figure 3-2: DI Raw Data Mapping for 8-Bit Data Width ................... 25
Figure 3-3: DI raw data Mapping for 16-Bit Data Width ................... 26
Figure 3-4: DI raw data Mapping for 24-Bit Data Width ................... 27
Figure 3-5: DI raw data Mapping for 32-Bit Data Width ................... 27
Figure 3-6: Phase Shift of Sample Clock ......................................... 28
Figure 3-7: Maximum Data Throughput ........................................... 29
Figure 3-8: Scatter-Gather DMA for Data Transfer .......................... 31
Figure 3-9: DI/DO Sample Clock Architecture ................................. 34
Figure 3-10: DI Continuous Mode Architecture.................................. 37
Figure 3-11: DI Timing Diagram......................................................... 38
Figure 3-12: DO Continuous Mode Architecture ................................ 40
Figure 3-13: DO Timing Diagram ....................................................... 41
Figure 3-14: DI Handshake Mode Architecture.................................. 43
Figure 3-15: DI Handshake Timing Diagram...................................... 44
Figure 3-16: DO Handshake Mode Architecture ................................ 46
Figure 3-17: DO Handshake Timing Diagram.................................... 47
Figure 3-18: DI Burst Handshake Mode Architecture ........................49
Figure 3-19: DI Burst Handshake Timing Diagram ............................ 50
Figure 3-20: DO Burst Handshake Mode Architecture....................... 52
Figure 3-21: DO Burst Handshake Timing Diagram ..........................53
Figure 3-22: DO Burst Handshake 2 Timing Diagram .......................53
Figure 3-23: DI Post Trigger............................................................... 54
Figure 3-24: DO Post Trigger............................................................. 55
Figure 3-25: DI Post Trigger with Re-trigger ...................................... 55
Figure 3-26: DO Post Trigger with Re-Trigger ................................... 56
Figure 3-27: DI Gated Trigger ............................................................ 56
Figure 3-28: DO Gated Trigger .......................................................... 57
Figure 3-29: I2C Master of PCIe-7360 ............................................... 62
Figure 3-30: Data Transfer on the I2C Bus ........................................ 63
Figure 3-31: I2C Data Format ............................................................ 64
Figure 3-32: SPI Master of PCIe-7360............................................... 65
Figure 3-33: Data Transfer on SPI Bus.............................................. 66
Figure 3-34: Clock Mode of SCK .......................................................66
List of Figures vii
Figure 3-35: External Digital Trigger Input Configuration...................67
Figure 3-36: Configured AFI as Internal Software Trigger Output .....68
Figure 3-37: Pattern Match and COS Event Configuration ................ 69
Figure 3-38: Configured AFI as Handshake Interface........................ 70
Figure 3-39: Configured AFI7 as DI Sampled Clock In/Out ............... 71
Figure 3-40: Configured AFI6 as DO Sampled Clock In/Out .............72
Figure 3-41: Example of Pattern Matching......................................... 74
Figure 3-42: Example of Pattern Match .............................................75
Figure A-1: DIN-68H Layout ............................................................ 77
Figure A-2: Resistor Termination Schematic....................................78
Figure A-3: DIN-68H Layout (Back Side) .........................................79
viii List of Figures
PCIe-7360
List of Tables
Table 1-1: PCIe-7360 SCSI-VHDCI 68-pin Assignment ................. 15
Table 1-2: Signal Descriptions for SCSI-VHDCI
and SMB Connectors..................................................... 16
Table 1-3: SMB Jack Connector Signal Description ....................... 17
Table 1-4: LED indicator ................................................................. 17
Table 3-1: Logic Levels................................................................... 23
Table 3-2: DI/DO Sample Clock Configuration ............................... 35
Table A-1: DIN-68H Pin Assignment ............................................... 77
Table A-2: Pad Position of User-Defined Resistor Termination ......79
List of Tables ix
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x List of Tables
1 Introduction
ADLINK’s PCIe-7360 is a high-speed digital I/O board with
32-channel bi-directional parallel I/O lines. Data rate up to 400
MB/s is available through the x4 PCI Express® interfaces, with
clock rate up to 100 MHz internal clock or 200 MHz external clock,
ideally suited for high-speed and large scale digital data acquisition or exchange applications, such as digital image capture, video
playback, and IC testing.
1.1 Features
X x4 lane PCI Express
X 8/16/24/32-CH @ up to 100MHz for DI or DO and 8/16-CH
@ up to 200MHz for DI in external clock mode
X 400 MB/s maximum throughput
X Software selectable 1.8 V, 2.5 V, or 3.3 V (5 V compatible)
voltage levels
X 80-step phase shift in external clock mode
X Per group (8-bit) input/output direction selectable
X Supports I2C and SPI programmable serial interfaces for
external device communication
X Scatter-gather DMA support
X Flexible handshake and external digital trigger modes
X 8-channel auxiliary programmable I/O support
®
interface
PCIe-7360
1.2 Applications
X High-speed digital data exchange
X Digital pattern generation and acquisition
X IC testing
X Interface to external high-speed A/D and D/A converter
X ATE
Introduction 1
1.3 Specifications
1.3.1 General
Interface x4 PCI Express interface
Connectors
Operating
Temperature
Storage
Temperature
Humidity 5 - 95%, non-condensing
Dimensions 168 mm (L) x 112 mm (H), not including connectors
Power
Consumption
1.3.2 Digital I/O
Channels 32
Direction
(programmable)
Logic level
(programmable)
Min.
Input
voltage
Output
voltage
Driving capacity
(min.)
Max. throughput
V
Max.
V
Min.
V
Max.
V
SMB Jack Connector x2 (CLK IN & OUT)
68-pin SCSI-VHDCI x1 (32-bit Data Lines & 8-CH AFI)
0°C - 55°C
-20°C - 70°C
Typical Maximum
+3.3 VDC 860 mA 950 mA
+12V VDC 270 mA 550 mA
Total Power 6.1 W 9.8 W
Input or output, per group (8 channel) basis
1.8 V 2.5 V
1.2 V 1.6 V 2 V
IH
0.63 V 0.7 V 0.8 V
IL
1.6 V 2.3 V 3.1 V
OH
0.2 V 0.2 V 0.2 V
OL
3.3 V
(5 V compatible)
±8 mA ±16 mA ±32 mA
Digital input: 400M Byte/s
Digital output: 400M Byte/s
2 Introduction
PCIe-7360
Buffer size
Data transfer
Digital input: 8k samples
Digital output: 20k samples
Software polling
Bus-mastering DMA with scatter-gather
Internal clock: up to 100 MHz
External clock: 200 MHz for DI, 100MHz for DO (see
Clock modes
Note)
Handshake
Burst handshake
Software
Trigger source
External digital signal
Pattern match
Trigger modes
Post trigger with re-trigger
Gate trigger
Input impedance 10 k
Input protection
range
Input protection
range
-1 to 6 V
-1 to 6 V
Output impedance 50
Power-up initial
state
Output protection
range
Tri-state/All digital inputs
-0.5 V to 3.8 V
External clock rate, which can be up to 200 MHz, only supports
8 or 16-bit data width
NOTE:
NOTE:
Introduction 3
1.3.3 Application Function I/O (AFI)
Channels 8
Direction
(programmable)
Logic levels
(programmable)
Min.
Input
voltage
V
IH
Max.
V
IL
Min.
Output
voltage
V
OH
Max.
V
OL
Driving capacity
(max.)
Input impedance 10 k
Input protection
range
Output impedance 50
Power-up initial state Tri-state/All digital inputs
Output protection
range
Supported Modes
(programmable)
Input or output, per channel basis
1.8 V 2.5 V
1.2 V 1.6 V 2 V
0.63 V 0.7 V 0.8 V
1.6 V 2.3 V 3.1 V
0.2 V 0.2 V 0.2 V
±8 mA ±16 mA ±32 mA
-1 to 6 V
-0.5V to 3.8V
2
I
C master
SPI master
Handshake
External trigger in/out
DI/DO sample clock in/out
3.3 V (5 V
compatible)
1.3.4 Timing Specifications
Sample Clock
Internal clock: onboard 100MHz with 16-bit
divider
Clock sources
4 Introduction
External clock: AFI6 (for DO)
AFI7 (for DI)
SMB CLK in
PCIe-7360
Internal clock rate
(programmable)
1526 Hz – 100 MHz (100 MHz/ N;
1N65,535)
Phase shift disabled: 0-200 MHz
Ext. frequency range
Phase shift enabled: 20MHz - 100MHz (see
Note)
Phase shift
Internal clock: N/A
External clock: 80 steps; 1 step = 4.5°
Sample Clock Exporting
AFI6 (for DO)
Destination
AFI7 (for DI)
SMB CLK out
Phase shift disabled: 0-100 MHz
Frequency range
Phase shift enabled: 20MHz - 100MHz (see
Note)
Clock jitter Period jitter: 300 ps
Clock duty cycle 50%
Phase shift resolution
1/80 of external sampled clock period (80
steps; 1 step = 4.5°)
When phase shift is enabled, the clock must be continuous and
free-running
NOTE:
NOTE:
Introduction 5
1.3.5 Timing Accuracy
Acquisition Timing
Channel-to-Cannel skew ±1.08 ns
Setup time to sampled clock (t
Hold time to sampled clock (t
Time delay of external sampled clock from AFI7 to
internal (t
AF7D
)
Time delay of external sampled clock from SMB CLK
in to internal (t
SMBID
)
Time delay of DI data from VHDCI connector to
internal (t
DID
)
Generation Timing
Exported clock skew AFI6 -to- SMB CLK out
ECskew
)
(t
Exported clock (AFI6) -to- DO data delay (t
) 2 ns
SU
) 2 ns
H
) 600 ps - 5 ns
AF62D
6.3 ns
9.1 ns
3.26 ns - 4.34 ns
2 ns
6 Introduction
DI Sampled Clock
(AFI7)
PCIe-7360
DI Data
(connector)
DI Sampled Clock
(into FPGA)
DI Data
(into FPGA)
t
= Time delay of external sampled clock from AFI7 to internal
AF7D
t
= Time delay of DI data from VHDCI connector to internal
DID
Figure 1-1: Acquisition Timing Diagram
D0 D1 D2 D3
tSUt
H
Trace & component delay
t
AF7D
D0 D1 D2 D3
t
DID
Introduction 7
DO Sampled Clock
(internal)
Exported DO Sampled Clock
(SMB CLK out/ non-inverted)
Generation Start
Trace & component delay
Exported DO Sampled Clock
(AFI6/ non-inverted)
Exported DO Sampled Clock
(AFI6/ inverted)
Exported DO Sampled Clock
(AFI6/ phase delay)
DO Data
t
= Time delay from sampled clock (internal) to exported sampled clock (AFI6)
SC2AF6
t
= Time delay from exported clock (AFI6) to exported clock (SMB CLK out)
ECskew
= Time delay from exported sampled clock (AFI6) to do data
t
AF62D
Figure 1-2: Generation Timing Diagram
t
SC2AF6
Phase delay (0° ~ 360°)
t
AF62D
D0
D1 D2
Write data to
external device
t
ECskew
8 Introduction
1.3.6 External Clock I/O Specification
CLK IN (SMB Jack Connector)
Destination DI or DO sample clock
Input coupling AC
Input Impedance 50
Minimum detectable pulse
width
External sampled clock
range
CLK OUT (SMB Jack Connector)
Sources DI or DO internal sample clock
Source impedance 50
Logic Levels
(programmable)
Driving Capacity (Max.)
8 ns
Square Wave
Voltage 0.2 Vpp to 5 Vpp
Phase shift disabled:
Frequency
Duty cycle 40% - 60%
Sine Wave
Voltage 0.2 Vpp to 5 Vpp
Frequency
The same logic level of AFI I/O (1.8 V,
2.5 V, or 3.3 V)
±8 mA at 1.8 V
±16 mA at 2.5 V
±32 mA at 3.3 V
0-200 MHz
Phase shift enabled:
20MHz - 100MHz
Phase shift disabled:
0-200 MHz
Phase shift enabled:
20MHz - 100MHz
PCIe-7360
2
1.3.7 I
Signal
Supported clock rate
(programmable)
Introduction 9
C Master Specification
Direction Pin
SCL O AFI0
SDA I/O AFI1
1.9 kHz -244.14 kHz;
488.28125 kHz / (n + 1); 1 n 255
Transfer size of Data 0 - 4 Bytes
Transfer size of Cmd/ Addr 0 - 4 Bytes
Logic families
(programmable)
Input Voltage
Output Voltage
Min. V
Max. V
Min. V
Max. V
1.8 V 2.5 V 3.3 V
1.2 V 1.6 V 2.0 V
IH
0.63 V 0.7 V 0.8 V
IL
1.6 V 2.3 V 3.1 V
OH
0.2 V 0.2 V 0.2 V
OL
1.3.8 SPI Master Specification
SCK O AFI0
Signal
Supported clock rate
(programmable)
SDO O AFI1
SDI I AFI2
CS_0 O AFI3
244.14 kHz -62.5 MHz,
62.5 MHz / (n + 1); 0 n 255
Direction Pin
Clock mode
The first bit be transferred
Mode =1
Mode =0
MSB/ LSB
(Default: MSB)
Transfer size of Data 0 - 32 bits
Transfer size of Cmd/ Addr 0 - 32 bits
Dummy size 0 - 15 bits
SPI Slave selection CS_0
Logic families
(programmable)
Input Voltage
Output Voltage
Min. V
Max. V
Min. V
Max. V
1.8 V 2.5 V 3.3 V
1.2 V 1.6 V 2 V
IH
0.63 V 0.7 V 0.8 V
IL
1.6 V 2.3 V 3.1 V
OH
0.2 V 0.2 V 0.2 V
OL
10 Introduction
PCIe-7360
1.4 Software Support
ADLINK provides versatile software drivers and packages for
users’ different approach to building up a system. ADLINK not only
provides programming libraries such as DLL for most Windows
based systems, but also provide drivers for other software packages such as LabVIEW®.
All software options are included in the ADLINK CD. Non-free software drivers are protected with licensing codes. Without the software code, you can install and run the demo version for two hours
for trial/demonstration purposes. Please contact ADLINK dealers
to purchase the formal license.
DAQPilot
DAQPilot is ADLINK’s proprietary task-oriented software development kit (SDK), supporting ActiveX Controls/.NET Assembly,
Express VI and Polymorphic VI for LabVIEW and DAQ Toolbox for
MATLAB.
You can download and install DAQPilot at:
http://www.adlinktech.com/TM/DAQPilot.html
Please note that only DAQPilot versions 2.6.1.0705 and later support the PCIe-7360.
PCIS-DASK
PCIS-DASK comprises advanced 32/64-bit kernel drivers for customized DAQ application development, enabling detailed operations and superior performance and reliability from the data
acquisition system. DASK kernel drivers now support Windows
8/7/XP OS.
Please note that only PCIS-DASK versions 5.10 and later support
the PCIe-7360 module.
Introduction 11
1.5 Schematics, I/O and Indicators
All dimensions shown are in mm
NOTE:
NOTE:
.
100.36
176.42
Figure 1-3: PCIe-7360 Schematic Diagram
111.15
1.6 Connectors
The PCIe-7360 card is equipped with one 68-pin SCSI-VHDCI
connector for high-speed digital I/O and programmable function
12 Introduction
PCIe-7360
I/O, and two SMB connectors for sample clock input and output,
as labeled on the faceplate.
Figure 1-4: PCIe-7360 Connectors
Introduction 13
ID Pin Pin ID
GND 68 34 GND
(DI CLK) AFI7 67 33 AFI6 (DO CLK)
GND 66 32 GND
D0 65 31 D1
AFI5 64 30 AFI4
D2 63 29 D3
GND 62 28 GND
D4 61 27 D5
AFI3 60 26 AFI2
D6 59 25 D7
GND 58 24 GND
D8 57 23 D9
GND 56 22 GND
D10 55 21 D11
GND 54 20 GND
D12 53 19 D13
AFI1 52 18 GND
D14 51 17 D15
GND 50 16 GND
D16 49 15 D17
GND 48 14 GND
D18 47 13 D19
GND 46 12 GND
D20 45 11 D21
GND 44 10 GND
D22 43 9 D23
GND 42 8 AFI0
D24 41 7 D25
GND 40 6 GND
D26 39 5 D27
GND 38 4 GND
14 Introduction
ID Pin Pin ID
D28 37 3 D29
GND 36 2 GND
D30 35 1 D31
Table 1-1: PCIe-7360 SCSI-VHDCI 68-pin Assignment
PCIe-7360
Pin Signal
25, 27,
29, 31,
59, 61,
D0 – D7 Data I/O
63, 65
17, 19,
21, 23,
51, 53,
D8 – D15 Data I/O
55, 57
9, 11, 13,
15, 43,
45, 47,
D16 – D23 Data I/O
49
1, 3, 5,
7, 35, 37,
D24 – D31 Data I/O
39, 41
8, 26, 30,
52, 60, 64AFI0 – AFI5
Signal
Type
Control
/Data
Direction Description
Port_A bi-directional digital
data lines
Port_B bi-directional digital
data lines
Port_C bi-directional digital
data lines
Port_D bi-directional digital
data lines
Application Function I/O,
can be configured as:
2
X I
C/ SPI
I/O
X Handshake sig-
nal
X External trigger
in/out
X Event out
Introduction 15
Pin Signal
Signal
Type
Direction Description
Application Function I/O,
can be configured as:
X Handshake sig-
nal
33 AFI6
Control
/Data
I/O
X External trigger
in/out
X Event out
X DO sampled
clock in/out
Application Function I/O,
can be configured as:
X Handshake sig-
nal
67 AFI7
Control
/Data
I/O
X External trigger
in/out
X Event out
X DI sampled clock
in/out
2, 4,6,
10, 12,
14, 16,
18,20,
22, 24,
28, 32,
34, 36,
38, 40,
GND Ground N/A
Ground reference for Data
I/O and AFI I/O
42, 44,
46, 48,
50, 54,
56, 58,
62, 66,
68
Table 1-2: Signal Descriptions for SCSI-VHDCI and SMB Connectors
16 Introduction
PCIe-7360
Signal
CLK IN Clock I
CLK OUT Clock O
Signal
Type
Table 1-3: SMB Jack Connector Signal Description
Direction Description
External clock input for DI/DO sampled
clock from external device to the
PCIe-7360
DI/DO sampled clock exporting from the
PCIe-7360 to an external device
1.7 LED indicator
The LED on the faceplate indicates I2C & SPI communication and
digital I/O status of the PCIe-7360.
LED Color Mode
ACC
(Access)
Red DI DMA operation
Green DO DMA operation
Amber DI & DO DMA operation
Table 1-4: LED indicator
Introduction 17
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18 Introduction
2 Getting Started
2.1 Unpacking Checklist
Before unpacking, check the shipping carton for any damage. If
the shipping carton and/or contents are damaged, inform your
dealer immediately. Retain the shipping carton and packing materials for inspection. Obtain authorization from your dealer before
returning any product to ADLINK. Check if the following items are
included in the package.
X PCIe-7360 high-speed DIO card
X ADLINK All-in-One CD
X Quick Start Guide
If any of the items is damaged or missing, contact your dealer
immediately.
The card must be protected from static discharge and physical
shock. Never remove any of the socketed parts except at a
CAUTION:
static-free workstation. Use the anti-static bag shipped with the
product to handle the card. Wear a grounded wrist strap when
servicing.
PCIe-7360
2.2 Installing the Card
Install the card driver before you install the card into your computer system. See “Software Support” on page 11. for driver support information.
To install the card:
1. Turn off the system/chassis and disconnect the power
plug from the power source.
2. Remove the system/chassis cover.
3. Select the PCI Express slot that you intend to use, then
remove the bracket opposite the slot, if any.
4. Align the card connectors (golden fingers) with the slot,
then press the card firmly until the card is completely
seated on the slot.
Getting Started 19
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