ADLINK PCIe-7350 User Manual

PCIe-7350

32-CH High-speed DIO Board

User’s Manual

Manual Rev. 2.00
Revision Date: April 8, 2009
Part No: 50-11039-1000

Advance Technologies; Automate the World.

Copyright 2009 ADLINK TECHNOLOGY INC.

All Rights Reserved.

The information in this document is subject to change without prior
notice in order to improve reliability, design, and function and does
not represent a commitment on the part of the manufacturer.

In no event will the manufacturer be liable for direct, indirect, spe­cial, incidental, or consequential damages arising out of the use or
inability to use the product or documentation, even if advised of
the possibility of such damages.

This document contains proprietary information protected by copy­right. All rights are reserved. No part of this manual may be repro­duced by any mechanical, electronic, or other means in any form
without prior written permission of the manufacturer.

Trademarks

NuDAQ, NuIPC, DAQBench are registered trademarks of ADLINK
TECHNOLOGY INC.

Product names mentioned herein are used for identification pur­poses only and may be trademarks and/or registered trademarks
of their respective companies.

Getting Service from ADLINK

Contact us should you require any service or assistance.

ADLINK Technology Inc.

Address: 9F, No.166 Jian Yi Road, Chungho City,

Taipei County 235, Taiwan
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Tel: [phone]
Fax: [phone]
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Ampro ADLINK Technology Inc.

Address: 5215 Hellyer Avenue, #110, San Jose, CA 95138, USA
Tel: [phone]
Toll Free: [phone] (USA only)
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ADLINK Technology Beijing

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A1 󰶀 2 ὐ C  (518057)

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ADLINK Technology Inc. (German Liaison Office)

Address: Nord Carree 3, 40477 Duesseldorf, Germany
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ADLINK (French Liaison Office)

Address: 15 rue Emile Baudot, 91300 MASSY Cedex, France
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ADLINK Technology Japan Corporation

Address: 151-0072 ᧲ㇺ⼱඙ᐈ䊱⼱㩷

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ADLINK Technology Inc. (Korean Liaison Office)

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Gangnam-gu, Seoul, 135-010, Korea.
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ADLINK Technology Singapore Pte Ltd.

Address: 84 Genting Lane #07-02A, Cityneon Design Centre,

Singapore 349584
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ADLINK Technology Singapore Pte Ltd. (Indian Liaison Office)

Address: No. 1357, "Anupama", Sri Aurobindo Marg, 9th Cross,
JP Nagar Phase I, Bangalore - 560078, India
Tel: [phone]
Fax: [phone]
Email: [e-mail]

Table of Contents

List of Tables.......................................................................... iii

List of Figures........................................................................ iv

1 Introduction ........................................................................ 1

1.1 Features............................................................................... 1

1.2 Applications ......................................................................... 1

1.3 Specifications....................................................................... 2

1.4 Software Support ............................................................... 10

Programming Library .................................................... 10

2 Hardware Information...................................................... 11

2.1 Card Layout ....................................................................... 11

2.2 Connector Pin Assignment ................................................ 12

2.3 LED indicator ..................................................................... 15

2.4 Installing the Card.............................................................. 16

2.5 Unpacking Checklist .......................................................... 17

2.6 Cables and Termination board .......................................... 17

3 Function Block and Operation Theory........................... 19

3.1 Block Diagram ................................................................... 20

3.2 Programmable Logic Level ................................................ 21

3.3 Digital I/O Configuration..................................................... 22

DI Row Data Mapping ................................................... 23

3.4 Phase Shift of Sample Clock ............................................. 27

3.5 Bus-mastering DMA Data Transfer.................................... 29

3.6 Sample Clock..................................................................... 31

Digital Input (DI) Sample Clock ..................................... 31

Digital Output (DO) Sample Clock ................................ 32

3.7 Operation Mode ................................................................. 35

Polling Mode (Single Read/Write) ................................. 35

DI DMA in Continuous Mode ........................................ 35

DO DMA in Continuous Mode ...................................... 38

DI DMA in Handshaking Mode ..................................... 41

DO DMA in Handshaking Mode .................................... 44

DI DMA in Burst Handshaking Mode ............................ 46

DO DMA in Burst Handshaking Mode .......................... 48

3.8 Trigger Source and Trigger Mode...................................... 52

i

3.9 Application Function I/O..................................................... 56

I2C Master .................................................................... 60

SPI Master .................................................................... 62

External Digital Trigger ................................................. 64

Trigger Out .................................................................... 65

Event Out ...................................................................... 66

Handshaking ................................................................. 67

Sample Clock In/Out ..................................................... 68

3.10 Pattern Match..................................................................... 69

3.11 COS (Change of State) Event............................................ 71

3.12 Termination........................................................................ 72

Appendix A ADLINK DIN-68H........................................... 73

ii

List of Tables

Table 2-1: Connector CN1 Pin Assignment ............................. 13

Table 2-2: I/O Signal Descriptions ........................................... 14

Table 2-3: SMB Jack Connector Signal Descriptions .............. 14

Table 2-4: LED indicator .......................................................... 15

Table 3-1: PCIe-7350 Logic Levels ......................................... 21

Table 3-2: PCIe-7350 High-Speed Digital I/O Configuration ... 22

Table 3-3: Phase Shift Configuration of PCIe-7350 ................. 28

Table 3-4: DI/DO Sample Clock Configuration

of the PCIe-7350 .................................................... 34

Table 3-5: PCIe-7350 AFI I/O Configuration ............................ 56

Table 3-6: PCIe-7350 AFI Signal Description .......................... 57

Table 3-7: Logic States of Pattern Match ................................ 69

Table A-1: DIN-68H Pin Assignment ........................................ 73

Table A-2: Pad Position of User-Defined Resistor Termination 75

List of Tables iii

List of Figures

Figure 1-1: Acquisition Timing Diagram ....................................... 6

Figure 1-2: Generation Timing Diagram....................................... 7

Figure 2-1: PCB Layout and Mechanical Drawing

of the PCIe-7350 ..................................................... 11

Figure 3-1: PCIe-7350 Block Diagram ....................................... 20

Figure 3-2: DI Row Data Mapping for 8 Bits Data Width............ 24

Figure 3-3: DI Row Data Mapping for 16 Bits Data Width.......... 25

Figure 3-4: DI Row Data Mapping for 24 bits Data Width .......... 26

Figure 3-5: DI Row Data Mapping for 32 Bits Data Width.......... 26

Figure 3-6: Phase Shift of Sample Clock ................................... 27

Figure 3-7: Maximum Data Throughput of the PCIe-7350......... 29

Figure 3-8: Scatter-Gather DMA for Data Transfer .................... 30

Figure 3-9: DI/DO Sample Clock Architecture ........................... 33

Figure 3-10: DI Continuous Mode Architecture............................ 36

Figure 3-11: DI Timing Diagram................................................... 37

Figure 3-12: DO Continuous Mode Architecture .......................... 39

Figure 3-13: DO Timing Diagram ................................................. 40

Figure 3-14: DI Handshaking Mode Architecture ......................... 42

Figure 3-15: DI Handshaking Timing Diagram............................. 43

Figure 3-16: DO Handshaking Mode Architecture ....................... 45

Figure 3-17: DO Handshaking Timing Diagram ........................... 45

Figure 3-18: DI Burst Handshaking Mode Architecture................ 47

Figure 3-19: DI Burst Handshaking Timing Diagram ................... 48

Figure 3-20: DO Burst Handshaking Mode Architecture.............. 50

Figure 3-21: DO Burst Handshaking Timing Diagram.................. 51

Figure 3-22: DI Post Trigger......................................................... 52

Figure 3-23: DO Post Trigger....................................................... 53

Figure 3-24: DI Post Trigger with Re-trigger ................................ 53

Figure 3-25: DO Post Trigger with Re-Trigger ............................. 54

Figure 3-26: DI Gated Trigger ...................................................... 54

Figure 3-27: DO Gated Trigger .................................................... 55

Figure 3-28: I2C Master of PCIe-7350 ......................................... 60

Figure 3-29: Data Transfer on the I2C Bus .................................. 60

Figure 3-30: I2C Data Format ...................................................... 61

Figure 3-31: SPI Master of PCIe-7350......................................... 62

Figure 3-32: Data Transfer on SPI Bus........................................ 63

Figure 3-33: Clock Mode of SCK ................................................. 63

Figure 3-34: External Digital Trigger Input Configuration............. 64

iv List of Figures

Figure 3-35: Configured AFI as Internal Software

Trigger Output ......................................................... 65

Figure 3-36: Pattern Match and COS Event Configuration.......... 66

Figure 3-37: Configured AFI as Handshaking Interface............... 67

Figure 3-38: Configured AFI7 as DI Sampled Clock In/Out ......... 68

Figure 3-39: Configured AFI6 as DO Sampled Clock In/Out ....... 68

Figure 3-40: Example of Pattern Match ....................................... 70

Figure 3-41: Example of Pattern Match ....................................... 71

Figure A-1: DIN-68H Layout ...................................................... 73

Figure A-2: Resistor Termination Schematic.............................. 74

Figure A-3: DIN-68H Layout (Back Side) ................................... 75

List of Figures v

vi List of Figures

1 Introduction

ADLINK’s PCIe-7350 is a high-speed digital I/O board with 32­channel bi-direction parallel I/O lines. The data rate can achieve
up to 200 MB/s through the x1 PCI Express® interface. The clock
rate can support up to 50 MHz internal clock or 100 MHz external
clock, which is ideal for the applications of high-speed and large­scale digital data acquisition or exchange, such as digital image
capture, video playback and IC testing.

1.1 Features

The PCIe-7350 comes with the following advanced features:

 x1 lane PCI Express® Interface

 Maximum 50 MHz clock rate from internal timer or 100 MHz

from external clock

 200 MB/s maximum throughput

 Software selectable voltage level of 1.8 V, 2.5 V, and 3.3 V

(5 V compatible)

 16-steps phase shift in external clock mode

 Per group (8-bit) input/output direction selectable

 Supports I

external device communication

 Scatter-gather DMA support

 Flexible handshaking and external digital trigger modes

 8-channel auxiliary programmable I/O support

2

C and SPI programmable serial interfaces for

1.2 Applications

 High-speed digital data exchange

 Digital pattern generation and acquisition

 IC testing

 Interface to external high-speed A/D and D/A converter

 ATE

Introduction 1

1.3 Specifications

Digital I/O Specifications

Number of 
Channels

Direction

(programmable)

Logic Level

(programmable)

Min. V

Input 
Voltage

Output 
Voltage

Driving capacity(max.) ±8 mA ±16 mA ±32 mA

Throughput

FIFO Size

Data Transfer

Clocking Modes

Trigger Source

Trigger Modes

Input impedance 10 KΩ
Input protection range -1 to 6 V
Output impedance 50 Ω
Power-up initial state Tri-State / All digital inputs
Output protection range -0.5 V to 3.8 V
Dimensions 168 mm x 112 mm (not including connectors)
Connectors 68-pin VHDCI female x1 SMB x2
Operating Temp. 0 to 55° C
Storage Temp. -20 to 70° C
Relative Humidity 5 to 95%, non-condensing

Max. V
Min. V
Max. V

IH

IL

OH

OL

1.8 V 2.5 V

1.2 V 1.6 V 2 V

0.63 V 0.7 V 0.8 V

1.6 V 2.3 V 3.1 V

0.2 V 0.2 V 0.2 V

Digital Input: 
Maximum: 200 MByte/s (32-bits input @ 50 MHz) (data size≤250k
samples)

Sustained: 192 MByte/s (data size>250k samples) (Note* )
Digital Output: 
Maximum: 200 MByte/s (32-bit output @ 50 MHz) (FIFO load mode,
max. 8k samples)
Sustained: 119.2 MByte/s (Note**)

Digital Input: 8k samples
Digital Output: 8k samples

Software Polling
Bus-mastering DMA with Scatter-Gather

Internal clock: max. 50 MHz
External clock: max. 100 MHz
Handshaking
Burst handshaking

Software
External Digital signal
Pattern match

Post trigger with re-trigger
Gate trigger

per group (8 channel) basis

32

Input or output,

(5 V compatible)

3.3 V

2 Introduction

Note*: DI DMA throughput

DI DMA Bandwidth Test

160

164

168

172

176

180

184

188

192

192.7058

192.7138

0

50

100

150

200

250

40 41 42 43 44 45 46 47 48 49 50

External Clock Rate (MHz)

BW (MB/s)

DI DMA Bandwidth T est

200 200 200 200 200

192.58

192.01

192.64

192.56

191.98

186

188

190

192

194

196

198

200

202

50 100 150 200 250 300 350 400 450 500

Data Count (K samples)

BW (MB/s)

DO DMA Bandwidth Test

100

118

116

112

108

104

119.32

119.28

119. 2

119.34

119.32

95

100

105

110

115

120

125

25 26 27 28 29 30 31 32

Clock Rate (MHz)

BW (MB/s)

Note**: DO DMA throughput

Introduction 3

If you want to have DO throughput to be up to 200M Byte/s, the
data size is limited to less than the 8K FIFO size by the following
steps:

Step1: Read 8K DO data from system memory into DO FIFO

by DMA before writing 8K DO data from DO FIFO to
the external device

Step2: After 8K DO data are all stored into DO FIFO, and

then start writing these 8K DO data to the external
device with 50MHz DO sample clock rate and 32-bit
data width.

External clock rate can be up to 100 MHz, but only support 8 or
16-bit data width because the DI data throughput can’t exceed 200
MB/s

Application Function I/O (AFI)

Number of channels 8
Direction

(programmable)

Logic Levels

(programmable)

Min. V
Max. V
Min. V
Max. V

IH

IL

OH

OL

Input 
Voltage

Output 
Voltage

Driving capacity (max.) ±8 mA ±16 mA ±32 mA
Input impedance 10 KΩ
Input protection range -1 to 6 V
Output impedance 50 Ω
Power-up initial state Tri-State / All digital inputs
Output protection range -0.5V to 3.8V

Supported Mode

(programmable)

1.8 V 2.5 V

1.2 V 1.6 V 2 V

0.63 V 0.7 V 0.8 V

1.6 V 2.3 V 3.1 V

0.2 V 0.2 V 0.2 V

2

I

C master
SPI master
Handshaking
External trigger in/out
DI/DO sample clock in/out

Input or output,

per channel basis

3.3 V

(5 V Compati-

ble)

4 Introduction

Timing Specifications

Sample Clock

Internal clock: on-board 100MHz with 16-bit divider

Clock Sources

Internal Clock Rate

(programmable)

Ext. frequency range

Phase shift
Sample Clock Exporting

Destination

Frequency range
Clock jitter Period jitter: 160 ps

Clock duty cycle 50%
Phase shift resolution

External clock: 1. AFI6 (for DO)

0 - 100 MHz (no phase shift)
2 MHz - 50MHz (phase shift enabled)*

Internal clock: N/A
External clock: 16 steps; 1 step = 22.5°

1. AFI6 (only for DO)

2. AFI7 (only for DI)

3. SMB CLK out

0 ~ 50 MHz (no phase shift)
2 MHz ~ 50MHz (phase shift enabled) (note3)

1/16 of external sampled clock period

2. AFI7 (for DI)

3. SMB CLK in

1526 Hz – 50 MHz

(100 MHz/ N; 2≤N≤65,535)

(16 steps; 1 step = 22.5°)

When you enable phase shift, the clock must be continuous and
free-running

Timing Accuracy

Acquisition Timing
Channel-to-Channel skew ±1.08 ns
Setup time to sampled clock (t

Hold time to sampled clock (t
Time delay of external sampled clock

from AFI7 to internal (t
Time delay of external sampled clock

from SMB CLK in to internal (t
Time delay of DI data from VHDCI

connector to internal (t
Generation Timing

Exported Clock SkewAFI6 -to- SMB
CLK out(t

Exported Clock (AFI6) -to- DO Data
Delay (t

ECskew

AF62D

)

AF7D

DID

)

)

SU

)

H

)

)

SMBID

)

2 ns

2 ns

7.22 ns

8.02 ns

3.26 ns - 4.34 ns

3.24 ns

600 ps - 5 ns

Introduction 5

DI Sampled Clock

(AFI7)

t

AF7D

= Time delay of external sampled clock from AFI7 to internal

t

DID

= Time delay of DI data from VHDCI connector to internal

D0 D1 D2 D3

t

AF7D

Trace & component delay

D0 D1 D2 D3

t

DID

DI Data

(connector)

DI Sampled Clock
(into FPGA)

DI Data

(into FPGA)

tSUt

H

Figure 1-1: Acquisition Timing Diagram

6 Introduction

D0

DO Sampled Clock
(internal)

DO Data

Write data to

external device

t

SC2AF6

= Time delay from sampled clock (internal) to exported sampled clock (AFI6)

t

AF62D

= Time delay from exported sampled clock (AFI6) to do data

Exported DO Sampled Clock
(AFI6/ non-inverted)

t

SC2AF6

Exported DO Sampled Clock

( AFI6/ inverted)

Exported DO Sampled Clock
(AFI6/ phase delay)

Phase delay (0° ~ 360°)

D1 D2

t

AF62D

Gerenation start

t

ECskew

t

ECskew

= Time delay from exported clock (AFI6) to exported clock (SMB CLK out)

Exported DO Sampled Clock
(SMB CLK out/ non-inverted)

Trace & component delay

Introduction 7

Figure 1-2: Generation Timing Diagram

External Clock I/O Specification

CLK IN (SMB Jack Connector)
Destination DI or DO sample clock
Input coupling AC
Input Impedance 50 Ω
Minimum detectable pulse width 8 ns

Square Wave

Voltage 0.2 Vpp to 5 Vpp

Frequency 100 KHz - 50 MHz

External sampled clock range

CLK OUT (SMB Jack Connector)
Sources DI or DO sample clock
Source impedance 50 Ω
Logic Levels

(programmable)

Driving Capacity (Max.)

I2C Master Specification

Signal

Supported clock rate

(programmable)

Transfer size of Data 0 - 4 Bytes
Transfer size of Cmd/ Addr 0 - 4 Bytes
Logic families

(programmable)

Min. V

Input Voltage

Output Voltage

Max. V
Min. V
Max. V

IH

IL

OH

OL

Duty cycle 40% - 60%

Sine Wave

Voltage 0.2 Vpp to 5 Vpp

Frequency 100 KHz – 50 MHz

The same logic level of AFI I/O

(1.8 V, 2.5 V, or 3.3 V)

±8 mA at 1.8 V
±16 mA at 2.5 V
±32 mA at 3.3 V

Direction Pin

SCL O AFI0

SDA I/O AFI1

1.9 kHz -244.14 kHz;

488.28125 kHz / (n + 1); 1 ≤ n ≤ 255

1.8 V 2.5 V 3.3 V

1.2 V 1.6 V 2.0 V

0.63 V 0.7 V 0.8 V

1.6 V 2.3 V 3.1 V

0.2 V 0.2 V 0.2 V

8 Introduction

CS#

SCK

Mode =1
Mode =0

Signal

Supported clock rate

(programmable)

Clock mode

SPI Master Specification

SCK O AFI0

SDO O AFI1

SDI I AFI2

CS_0 O AFI3

CS_1 O AFI4

CS_2 O AFI5

244.14 kHz -62.5 MHz,

62.5 MHz / (n + 1); 0 ≤ n ≤ 255

Direction Pin

The first bit be transferred

MSB/ LSB

(Default: MSB)

Transfer size of Data 0 - 32 bits
Transfer size of Cmd/ Addr 0 - 32 bits
Dummy size 0 - 15 bits

SPI Slave selection
Logic families

(programmable)

Min. V

Input Voltage

Output Voltage

Interface x1 PCI Express interface

Connector

Operation Temperature 0°C - 45°C
Storage Temperature -20°C - 70°C
Humidity 5 - 95%, non-condensing
Dimension 168 mm (L) x 112 mm (H), not including connectors

Power Consumption

IH

Max. V

IL

Min. V

OH

Max. V

OL

General Specification

1. SMB Jack Connector x2 (CLK IN & OUT)

2. 68-pin SCSI-VHDCI x1 (32-bit Data Lines & 8-ch AFI)

+3.3 VDC 450 mA 780 mA

+12V VDC 625 mA 680 mA

Total Power 9 W 10.8 W

Max. 3 slave devices

(selected by CS_0 / CS_1 / CS_2

1.8 V 2.5 V 3.3 V

1.2 V 1.6 V 2 V

0.63 V 0.7 V 0.8 V

1.6 V 2.3 V 3.1 V

0.2 V 0.2 V 0.2 V

Typical Maximum

Introduction 9

1.4 Software Support

ADLINK provides versatile software drivers and packages for
users’ different approach to building up a system. ADLINK not only
provides programming libraries such as DLL for most Windows
based systems, but also provide drivers for other software pack­ages such as LabVIEW®.

All software options are included in the ADLINK CD. Non-free soft­ware drivers are protected with licensing codes. Without the soft­ware code, you can install and run the demo version for two hours
for trial/demonstration purposes. Please contact ADLINK dealers
to purchase the formal license.

1.4.1 Programming Library

For customers who are writing their own programs, we provide
function libraries for many different operating systems, including:

 PCIS-DASK: Include device drivers and DLL for Windows

98/NT/2000/XP/Vista. DLL is binary compatible across

Windows 98/NT/2000/XP/Vista. This means all applications
developed with PCIS-DASK are compatible across Win­dows 98/NT/2000/XP/Vista. The developing environment
can be VB, VC++, Delphi, BC5, or any Windows program­ming language that allows calls to a DLL. The user’s guide
and function reference manual of PCIS-DASK are in the
CD. 
(\\Manual\Software Package\PCIS-DASK)

10 Introduction

2 Hardware Information

167 .65

169 .65

100.36

126.37

(4.5)

111.15

CN1

CN2

CN3

CN4

JP1

U1

CN5

CN6

LED5

LED6

T1

U12

U23

U24

U25

U6

U50

U7

U18

U22

U17

U21

U16

U20

U15

U19

U41 U43 U4 4

U44

U38

U39

U51

U52

U14 U13 U11

U9 U8 U11

LED1

LED2

U46

U36 U33

U35

OSC 1

SW1

U3 U4

U28 U30

C248

U47

U40

U26

U31

U29

U32

L23

C190

Q3

U27

C189

C195

This chapter provides information on the PCIe-7350 layout, con­nectors, and pin assignments.

2.1 Card Layout

Figure 2-1 shows the PCIe-7350 board layout and dimensions.

Figure 2-1: PCB Layout and Mechanical Drawing of the PCIe-7350

Hardware Information 11

2.2 Connector Pin Assignment

The PCIe-7350 card is equipped with one 68-pin SCSI-VHDCI
connector and two SMB connectors. The SCSI-VHDCI connector
is for high-speed digital I/O and programmable function I/O, while
the SMB connectors are for sample clock input or exporting.

12 Hardware Information

Pin # Pin #

GND 68 34 GND

(DI CLK) AFI7 67 33 AFI6 (DO CLK)

GND 66 32 GND

D0 65 31 D1

AFI5 64 30 AFI4

D2 63 29 D3

GND 62 28 GND

D4 61 27 D5

AFI3 60 26 AFI2

D6 59 25 D7

GND 58 24 GND

D8 57 23 D9

GND 56 22 GND

D1055 21D11

GND 54 20 GND

D1253 19D13

AFI1 52 18 GND

D1451 17D15

GND 50 16 GND

D1649 15D17

GND 48 14 GND

D1847 13D19

GND 46 12 GND

D20 45 11 D21

GND 44 10 GND

D22 43 9 D23

GND 42 8 AFI0

D24 41 7 D25

GND 40 6 GND

D26 39 5 D27

GND 38 4 GND

D28 37 3 D29

GND 36 2 GND

D30 35 1 D31

Table 2-1: Connector CN1 Pin Assignment

Hardware Information 13

Signal Descriptions

Below are the signal descriptions for the SCSI-VHDCI and SMB
connectors:

Pin

Number

25, 27, 29, 31, 59,
61, 63, 65

17, 19, 21, 23, 51,
53, 55, 57

9, 11, 13, 15, 43,
45, 47, 49

1, 3, 5, 7, 35, 37,
39, 41

8, 26, 30, 52, 60,
64

33 AFI6

67 AFI7

2, 4,6, 10, 12, 14,
16, 18,20, 22, 24,
28, 32, 34, 36, 38,
40, 42, 44, 46, 48,
50, 54, 56, 58, 62,
66, 68

Signal

Name

D0 – D7 Data I/O Port_A bi-directional digital data lines

D8 – D15 Data I/O Port_B bi-directional digital data lines

D16 – D23 Data I/O Port_C bi-directional digital data lines

D24 – D31 Data I/O Port_D bi-directional digital data lines

AFI0 – AFI5

GND Ground -------- Ground reference for Data I/O and AFI I/O

Signal

Type

Control

/Data

Control

/Data

Control

/Data

Direction Description

Application Function I/O, can be config­ured as the following control signals:

 I

I/O

 Handshaking signal
 External trigger in/out
 Event out

Application Function I/O, can be config­ured as the following control signals:
 Handshaking signal

I/O

 External trigger in/out
 Event out
 DO sampled clock in/out

Application Function I/O, can be config­ured as the following control signals:
 Handshaking signal

I/O

 External trigger in/out
 Event out
 DI sampled clock in/out

Table 2-2: I/O Signal Descriptions

SMB Jack Connector Signal Description

2

C/ SPI

Signal Name Signal Type Direction Description

CLK IN Clock I

CLK OUT Clock O

External clock input for DI/DO sampled clock from
external device to the PCIe-7350

DI/DO sampled clock exporting from the PCIe-7350 to
an external device

Table 2-3: SMB Jack Connector Signal Descriptions

14 Hardware Information

2.3 LED indicator

There are two LEDs on the bracket which display the I2C & SPI
communication and digital I/O status of the PCIe-7350.

LED Color Mode

2

I

C mode enabled

STS 
(Status)

ACC 
(Access)

Table 2-4: LED indicator

Red

Yellow SPI mode enabled

Red DI DMA operation

Yellow DO DMA operation

Amber DI & DO DMA operation

Hardware Information 15

2.4 Installing the Card

IMPORTANT Install the card driver before you install the card into

your computer system. Refer to section 1.5 for driver support infor­mation.

To install the card:

1. Turn off the system/chassis and disconnect the power
plug from the power source.

2. Remove the system/chassis cover.

3. Select the PCI Express slot that you intend to use, then
remove the bracket opposite the slot, if any.

4. Align the card connectors (golden fingers) with the slot,
then press the card firmly until the card is completely
seated on the slot.

5. Secure the card to the chassis with a screw.

6. Replace the system/chassis cover.

7. Connect the power plug to a power source, then turn on
the system.

Configuration

The card configuration is done on a card-by-card basis for all PCI/
PCI Express cards on your system. Because configuration is con­trolled by the system and the software, there is no jumper setting
required for base address, DMA, and interrupt IRQ. The configura­tion is subject to change with every boot of the system as new
PCI/PCI Express® cards are added or removed.

Troubleshooting

If your system fails to boot or if you experience erratic operation
with your PCI/PCI Express card in place, this is likely caused by
an interrupt conflict (such as when the BIOS Setup is incorrectly
configured). Refer to the BIOS documentation that came with the
system for details.

16 Hardware Information