ADLINK PCI-9810 User Manual

NuDAQ PCI-9812/9810

4-CH, 20 MHz Simultaneous

Analog Input Card

User’s Manual

Manual Rev. 3.02
Revision Date: December 2, 2008
Part No: 50-11116-2040

Advance Technologies; Automate the World.

Copyright 2008 ADLINK TECHNOLOGY INC.
All Rights Reserved.

Disclaimer

The information in this document is subject to change without prior
notice in order to improve reliability , design, and function and does
not represent a commitment on the part of the manufacturer.

In no event will the manufacturer be liable for direct, indirect, spe­cial, incidental, or consequential damages arising out of the use or
inability to use the product or documentation, even if advised of
the possibility of such damages.

This document contains proprietary information protected by copy­right. All rights are reserved. No part of this manual may be repro­duced by any mechanical, elec tronic, or other means in a ny form
without prior written permission of the manufacturer.

Trademark Information

NuDAQ, NuIPC, DAQBench are registered trademarks of ADLINK
TECHNOLOGY INC.

Product names mentioned herein are used for identification pur­poses only and may be trademarks and/or registered trademarks
of their respective companies.

Getting service

Customer satisfaction is our top priority. Contact us should you
require any service or assistance.

ADLINK TECHNOLOGY INC.

Web Site http://www.adlinktech.com
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(INDIA Liaison Office)

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Using this manual

Audience and scope

This manual guides you when using ADLINK NuDAQ® multi-func­tion PCI card. The card’s hardware, signal connections, and cali­bration information are provided for faster application building.
This manual is intended for computer programmers and hardware
engineers with advanced knowledge of data acquisition and high­level programming.

How this manual is organized

This manual is organized as follows:

Chapter 1 Introduction: This chapter introduces the PCI­9812/9810 card including its features, specifications, software
support information, and package contents.

Chapter 2 Hardware Information: This chapter presents the
card’s layout and connector pin definition.

Chapter 3 Installation: This part describes the PCI-9812/9810
installation, configuration, and options for signal connections.

Chapter 4 Registers: Descriptions of the register format and
structure of the PCI-9812/9810 are specified in this chapter.

Chapter 5 Operation Theory: The operation theory of the
PCI-9221 functions including A/D conversion, D/A conversion,
and programmable function I/O are discussed in this chapter.

Chapter 6 Function Reference: The chapter includes a soft­ware library necessary for operating the PCI-9812/9810 card in
DOS or Windows 95.

Chapter 7 Calibration: The chapter offers information on how
to calibrate the PCI-9812/9810 for accurate data acquisition
and output.

Chapter 8 Software Utility: The chapter offers information on
how to use the software utility to configure, calibrate, and test
the PCI-9812/9810 card.

War rant y Pol icy : This presents the ADLINK Warranty Policy
terms and coverages.

Conventions

Take note of the following conventions used throughout the man­ual to make sure that you perform certain tasks and instructions
properly.

NOTE Additional information, aids, and tips that help you per-

form particular tasks.

IMPORTANTCritical information and instructions that you MUST perform to

WARNING Information that prevents physical injury, data loss, mod-

complete a task.

ule damage, program corruption etc. when trying to com­plete a particular task.

Table of Contents

List of Tables.......................................................................... iv

List of Figures......................................................................... v

1 Introduction ........................................................................ 1

1.1 Features............................................................................... 1

1.2 Applications ......................................................................... 1

1.3 Specifications....................................................................... 2

1.4 Unpacking Checklist .................. ... ... .... ... ... ... ... .... ... ... ... .... ... 4

1.5 Software Support................................................................. 5

Software Support ............................................................5

Programming Libraries .................. ... ... ... ........................5

Drivers for Third-Party Programming Languages ...........6

2 Hardware Information........................................................ 9

2.1 Layout.................................................................................. 9

2.2 Connectors ........................................................................ 10

JP1 Pin Definition ......................................................... 11

2.3 Input Settings..................................................................... 12

Analog Input ................................................................. 12

External Clock 0 ............................................................14

External Clock 1 ............................................................14

Digital Input ...... .... ... ... .......................................... ... .... .. 14

3 Installation ........................................................................ 15

3.1 Before You Proceed .......................................................... 15

3.2 Installing the Card.............................................................. 15

3.3 Configuring the Card.......................................................... 16

Troubleshooting ................................ ............................ 16

3.4 Installing the Drivers for Windows ..................................... 16

4 Registers........................................................................... 17

4.1 I/O Port Address ................................................................ 17

ADC Channel Enable Register ..................................... 18

ADC Clock Divisor Register . ... ... .... ... ... ... ... .... ... ... ... .... .. 19

Trigger Mode Register .................................................. 20

Trigger Level Register .................................................. 21

Trigger Source Register .................................... ... ... .... .. 22

Table of Contents i

Post Trigger Counter Register ......................................23

FIFO Status Register ....................................................24

FIFO Control Register ...................................................25

Acquisition Enable Register ..........................................26

Clock Source Register ..................................................27

4.2 High Level Programming ................................................... 28

4.3 Low Level Programming.................................................... 28

5 Operation Theory............................................................ .. 29

5.1 Conversion Procedure....................................................... 29

5.2 Signal Source Control........................................................ 31

5.3 Trigger Source Control....................................................... 32

Trigger Sources ............................................................32

Trigger Modes ...............................................................34

5.4 Clock Source Control......................................................... 36

A/D Clock Sources ........................................................36

5.5 Data Transfer..................................................................... 38

Data Transfer ................................................................38

Simultaneous Sampling of Four AD Channels .............38

Total Data Throughput ................................. .................39

Maximum Acquiring Data Length ..................................39

Bus-mastering Data Transfer ........................................40

Host Memory Operation ................................................40

5.6 Data Format....................................................................... 42

6 Function Reference .......................................................... 45

6.1 Installing the Libraries........ ... ... .... ... ... ... .... ... ... ... ................ 45

6.2 Programming Guide........................................................... 46

Naming Convention ............................... ... ... ... .... ... ... ... .46

Data Types ...................................................................47

6.3 Function Reference............................................................ 48

_9812_Initial .................................................................48

_9812_Close ....................................... ................... .......50

_9812_AD_DMA_Start ................................................. 51

_9812_AD_DMA_Status ........................................ .......54

_9812_AD_DMA_Stop .................................................55

_9812_Set_Clk_Src ..................................... .................56

_9812_Set_Clk_Rate .......................................... ..........57

_9812_Set_Trig ............................................................ 58

W_9812_Alloc_DMA_Mem ...........................................60

ii Table of Contents

W_9812_Free_DMA_Mem ........................................... 61

W_9812_Get_Sample .................................................. 62

7 Calibration......................................................................... 63

7.1 Before You Proceed .......................................................... 63

7.2 VR Assignment.................................................................. 63

7.3 A/D Calibration................................................................... 64

A/D Calibration for Channel 0 ........................... ... ... .... .. 64

A/D Calibration for Channels 1/2/3 ............................... 64

8 Software Utility................................................................. 65

8.1 Running the Utility.............................................................. 65

8.2 System Configuration ........................................................ 66

8.3 Calibration.......................................................................... 67

8.4 Functional Testing ............................................................. 69

Table of Contents iii

List of Tables

Table 2-1: JP1 Pin Definition ................................................... 11

Table 2-2: JP1 Pin Definition Connected to

9-pin D-type Connector ........................................... 11

Table 2-3: Analog Input ........................................................... 12

Table 2-4: Switches and Resistors .......................................... 13

Table 4-1: I/O Address ............................................................. 17

Table 4-2: Five Trigger Modes ................................................. 20

Table 6-1: Data Types ....................... ... ... ... .... ... ... ... ... .... ... ... ... 47

Table 7-1: Functions of VRs .................................................... 63

Table 7-2: AD Calibration for Channels 1/2/3 .......................... 64

iv List of Tables

List of Figures

Figure 2-1: Location of Connectors............................................ 10

Figure 5-1: Post-trigger Acquisition............................................ 34

Figure 5-2: Pre-trigger Acquisition ............................................. 34

Figure 5-3: Middle-trigger Acquisition ........................................ 35

Figure 5-4: Delay-trigger Acquisition.......................................... 35

Figure 5-5: Data Transfer Diagram of PCI-9812/9810............... 38

List of Figures v

1 Introduction

The PCI-9812/9810 is an advanced performance data acquisition
card based on the 32-bit PCI bus architecture. With maximum
sampling rate of up to 20 million samples per second, the PCI­9812/9810 delivers continuous and high-speed streaming of A/D
samples to the host memory. The high-performance design and
state-of-the-art technology make these cards ideal for DSP, FFT,
digital filtering, and image processing applications.

1.1 Features

The PCI-9812/9810 advanced DAQ card is designed with the fol­lowing features:

X 32-bit PCI bus with bus mastering DMA data transfer
X 12-bit (PCI-9812)/10-bit (PCI-9810) analog input resolution
X Onboard 32K words (samples) A/D FIFO memory
X Up to 20 MHz A/D sampling rate
X Four single-ended analog input channels
X Bipolar input signals
X Four A/D converters with simultaneously sampling
X Five A/D trigger modes including software trigger, pre-trig-

ger, post-trigger, middle trigger, and delay trigger

1.2 Applications

X IF and BASEBAND digitization
X Ultrasound imaging
X Gamma cameras
X Test instrument
X CCD imaging
X Video digitizing

Introduction 1

1.3 Specifications

Analog Input (AI)

Converters B.B. ADS800 series
Input Channels Four single-ended
Resolution 12-bit (PCI-9812)

10-bit (PCI-9810)

Over Voltage Protection Bipolar ±1 V, or ±5 V by soldering selection

1

Maximum Sampling Rate
Accuracy Gain error ±1.5% at 25°C
Input Impedance (soldering

selectable)

Dynamic Characteristic

Differential Linearity Error ±0.4 LSB (Typ.) ±1.0 LSB (Max.) at 25°C
Integral Linearity Error ±1.9 LSB at 25°C

A/D Clock Sources Internal clock, continuous external digital clock,

Input Impedance of External
Clock Source

Trigger Sources Software, analog threshold comparator using

Trigger Modes Software-trigger, pre-trigger, post-trigger,

AD Data Transfer Method DMA (bus mastering)

Digital Input (DI)

Channels Three TTL compatible inputs with 10 KW pull

Input Voltage

Low Min. 0 V, Max. 0.8 V
High Min. +2.0 V, Max. 5.5 V

Input Load

Low ±1 uA 0 V

High +2.7V min. 20 mA max.

20 MHz samples/second

50 Ω (±1 V and ±5 V)

1.25 KΩ (±5 V only)
5 MΩ (±1 V only)

and continuous external sine wave
50 Ω

internal D/A to set trigger level, and external
digital trigger

middle-trigger, and delay-trigger

down resistor

0.5 mA 5V

2Introduction

General Specifications

Connectors 5 BNC-type, one 10-pin header
Operating Temperature 0°C to 40°C
Storage Temperature -20°C to 80°C
Humidity 5% to 85%, non-condensing
Power Consumption +5 V 2.5 A (maximum)
Dimension 101 mm (H) X 173 mm (L)

1

With a single channel enabled, the maximum sampling rate is 20 MHz. With
two channels enabled, the 20 MHz sampling rate may only be reached when
the number of samples accessed for each channel is smaller than 16K. With
four channels enabled, the 20 MHz sampling rate may only be reached when
the number of samples accessed for each channel is smaller than 8K. Refer
to section 5.5 for more information on sampling rates and data length limita­tions.

Introduction 3

1.4 Unpacking Checklist

Before unpacking, check the shipping carton for any damage. If
the shipping carton and/or contents are damaged, inform your
dealer immediately. Retain the shipping carton and packing mate­rials for inspection. Obtain authorization from your dealer before
returning any product to ADLINK.

Check if the following items are included in the package.

X PCI-9812/9810 multi-function DAQ card
X Five BNC terminators
X ADLINK All-in-One CD
X User’s Manual
X Software Installation Guide

If any of the items is damaged or missing, contact your dealer
immediately.

CAUTION The card must be protected from static discharge and

physical shock. Neve r r emove any of the socketed parts
except at a static-free workstation. Use the anti-static bag
shipped with the product to handle the card. Wear a
grounded wrist strap when servicing.

4Introduction

1.5 Software Support

Software Support

ADLINK provides versatile software drivers and packages to suit
various user approach to building a system. Aside from program­ming libraries, such as DLLs, for most Windows-based systems,
ADLINK also provides drivers for other application environment
such as LabVIEW

™

trol

, and ISaGRAFTMLabVIEW®.

All software options are included in the ADLINK All-in-One CD.
Commercial software drivers are protected with licensing codes.
Without the code, you may install and run the demo version for
trial/demonstration purposes only up to two hours. Contact your
ADLINK dealers if you want to purchase the software license.

Programming Libraries

For customers who want to write their own programs, ADLINK pro­vides the following function libraries which are compatible with var­ious operating systems.

DOS Library

Borland C/C++ and Microsoft C++, the functions descriptions
are included in this user’s guide.

Windows 95 DLL

For VB, VC++, Delphi, and BC5 the functions descriptions are
included in this user’s guide.

®

, HP VEETM, DASYLabTM, InTouch™, InCon-

PCIS-DASK

The PCIS-DASK includes device drivers and DLL for Windows
98/NT/2000. DLL is binary compatible across Windows 98/NT/

2000. This means all applications developed with PCIS-DASK
are compatible with these Windows operating systems. The
developing environment may be VB, VC++, Delphi, BC5, or
any Windows programming language that allows calls to a
DLL. The PCIS-DASK user's and function reference manuals
are in the ADLINK All-in-One CD. (\\Manual_PDF\Software
\PCIS-DASK).

Introduction 5

PCIS-DASK/X

Include device drivers and shared library for Linux. The
developing environment can be Gnu C/C++ or any
programming language that allows linking to a shared library.
The user's guide and function reference manual of PCIS­DASK/X are in the CD. (\Manual_PDF\Software\PCIS-DASK­X).

These software drivers are shipped with the card. Refer to the
Software Installation Guide for details.

Drivers for Third-Party Programming Languages

PCIS-LVIEW: LabVIEW® Driver

The PCIS-LVIEW contains virtual instruments (VIs) which are
used to interface with the LabVIEW software package. PCIS­LVIEW supports Windows 95/98/NT/2000. The LabVIEW
driver is shipped free with the card. These may be installed and
used without a license. For more information on PCIS-LVIEW,
refer to the user’s guide in the All-in-One CD
(\\Manual_PDF\Software\PCIS-LVIEW).

PCIS-VEE: HP-VEE Driver

The PCIS-VEE includes user objects that interface with HP
VEE software package. The PCIS-VEE supports Windows 95/
98/NT. The HP-VEE drivers are shipped free with the card.
These may be installed and used without license. For more
information on PCIS-VEE, refer to the user’s guide in the All-in­One CD (\\Manual_PDF\Software\PCIS-VEE).

DAQBench

For customers who are familiar with ActiveX controls and VB/
VC++ programming, it is recommended to use the DAQBench
ActiveX Control components library for developing applica­tions. DAQBench is designed for Windows NT/98. For more
information on DAQBench, ref er to the user ’s guide in the All­in-One CD (\\Manual_PDF\Software\DAQBench\DAQBench
Manual.PDF).

™

: ActiveX Controls

6Introduction

DASYLab™ PRO

DASYLab is an easy-to-use software package that provides
easy-setup instrument functions such as FFT analysis. Contact
ADLINK for DASYLab PRO support, including DASYLab and
ADLINK hardware drivers.

Introduction 7

8Introduction

2 Hardware Information

This chapter describes the PCI-9812/9810 layout, connectors,
signal connection with external devices, and switch settings for
various applications.

2.1 Layout

Hardware Information 9

2.2 Connectors

The PCI-9812/9810 connects to external devices via five BNC
connectors and one 10-pin dual-in -line header. Figure 2-1 show s
the location of these connectors.

Figure 2-1: Location of Connectors

J1 Input signal of channel 0 A/D converter.
J2 Input signal of channel 1 A/D converter.
J3 Input signal of channel 2 A/D converter.
J4 Input signal of channel 3 A/D converter.
J5 Input signal of external clock 0.

This 10-pin connector is for digital input signal, including a

JP1

digital clock, a digital trigger, and three digital inputs.

10 Hardware Information

JP1 Pin Definition

Below is the default JP1 pin assignment.

Pin Signal

1 External Clock Input 1
2 Ground
3 External Digital Trigger Input
4 Ground
5 Digital Input 0
6 Ground
7 Digital Input 1
8 Ground
9 Digital Input 2

10 Ground

Table 2-1: JP1 Pin Definition

When JP1 is connected to a 9-pin D-type connector using a ribbon
cable, the pin-out of the D-type connector is changed to:

Pin Signal

1 External Clock Input 1
2Ground
3 External Digital Trigger Input
4Ground
5 Digital Input 0
6Ground
7 Digital Input 1
8Ground
9 Digital Input 2

10 N/A

Table 2-2: JP1 Pin Definition Connected to 9-pin D-type Connector

Hardware Information 11

2.3 Input Settings

This section describes the characteristics and settings of the PCI­9812/9810 inputs.

Analog Input

The PCI-9812/9810 has four analog input channels which are
connected through the J1 to J4 connectors. The input impedance
and input amplitude range can be changed through soldering the
gap switches on the board (refer to PCI-9812/9810 layout). A
solder gap switch consists of two copper pads. The switch can be
turned on by soldering the copper pads. As all four channels use
the same method to configure their input characteristics, only
channel 0 is discussed here. There are two solder gap switches
labeled as C0LO (channel 0 low impedance) and C05V (channe l 0
5 V input) to setup the input of channel 0. Refer to Figure 2-1.

C0LO C05V Input Impe da n ce Input Range

Open Open High (~15 MΩ)

Open Close 1.25 KΩ
Close Open Low (50 Ω)
Close Close Low (50 Ω)

Table 2-3: Analog Input

12 Hardware Information

±1 V
±5 V

±1 V (default)

±5 V

CAUTION DO NOT leave the input connector unconnected when it

is configured as high impedance input. The input connec­tor must be connected to a low impedance signal source
to provide a return path for the input bias current. Since
the OPAMP has a maximum input bias current of 35 µA
in the input stage, it will be placed in an abnormal envi­ronment when the input is left unconnected and will lead
to saturation in the output stage. Although a curren t-limit­ing resistor is present to protect the ADC, the large cur­rent brought by the saturation will damage the ADC.

Offset problems will occur if you use high impedance
(~15 MΩ) with signal sources having high output imped­ance. The high output impedance and the input bias cur­rent of up to 35 µA introduces a voltage drop of several
volts. Adjusting the variable resistor does not eliminate
this large offset voltage.

NOTE 75 Ω input impedance can be achieved by: (1) replacing

R95 with a 75-ohm resistor and close C0LO or (2) placing
a T-connector with a 75-ohm terminator on J1 and open
C0LO.

The corresponding switches and resistors of other channels are
listed below:

Channel Switches Resistor

Channel 0 C0LO C05V R95
Channel 1 C1LO C15V R96
Channel 2 C2LO C25V R97
Channel 3 C3LO C35V R98

Table 2-4: Switches and Resistors

Hardware Information 13