ADC MLN7400 User Manual

Cost Effective

Network Processor

for TCP/IP

with ARM7TDMI

™

MLN7400

Evaluation Board Manual

Version 0.20

December 31, 2003

MCS Logic Inc.

EVB7400

Revision History

Version Date Revision Description

V 0.10 December 30, 2003 First Release

User’s Manual V.0.10 2/36

EVB7400

User’s Manual V.0.10 3/36

EVB7400

Table of Contents

CHAPTER 1 INTRODUCTION.................................................................................................................. 6

1.1 SYSTEM REQUIREMENTS............................................................................................................................................ 6

1.2 BOARD COMPONENTS ................................................................................................................................................ 8

CHAPTER 2 BOARD CONFIGURATION.............................................................................................. 11

2.1 ENDIAN SELECTION (SW1)...................................................................................................................................... 11

2.2 BOOT ROM AND ROM BANK0 LENGTH SELECTION (SW2).................................................................................... 11

2.3 NAND FLASH ....................................................................................................................................................... 11

2.4 GPIO SETTING......................................................................................................................................................... 12

CHAPTER 3 SETUP EVB7400 ENVIRONMENTS................................................................................ 13

3.1 ETHERNET 10/100 BASE-T CONNECTOR................................................................................................................ 13

3.2 CONNECTION METHOD FOR UTP CABLE ................................................................................................................. 13

CHAPTER 4 CONNECTION CONFIGURATIONS FOR DEBU G CO NSOLE..................................15

4.1 CONFIGURATION THE HYPER TERMINAL ................................................................................................................. 15

4.2 DOWNLOADING BINARY IMAGE AND FLASH WRITE ................................................................................................ 16

4.2.1 Downloading Binary Image............................................................................................................................ 16

4.2.2 Flash Write...................................................................................................................................................... 19

CHAPTER 5 OPENNICE32 INSTALLATION....................................................................................... 20

5.1 OPENICE32............................................................................................................................................................. 20

5.2 CONNECTING EVB7400 AND PC ............................................................................................................................. 20

5.3 POWERING UP THE BOARD AND OPENICE32 ........................................................................................................... 20

CHAPTER 6 EVB7400 1.0 SCHEMETIC AND BOM ............................................................................ 21

6.1 EVB7400 BOM....................................................................................................................................................... 21

6.2 EVB7400 SCHEMATIC............................................................................................................................................. 24

User’s Manual V.0.10 4/36

EVB7400

List of Figures

[FIGURE 1 ] EVB7400 BLOCK DIAGRAM....................................................................................................................... 6

[FIGURE 2 ] MEMORY MAP.......................................................................................................................................... 7

[FIGURE 3 ] BLOCK DIAGRAM (TOP VIEW).................................................................................................................. 8

[FIGURE 4 ] UTP CABLE CONNECTION...................................................................................................................... 14

[FIGURE 5 ] PROPERTIES SETTING PAGE................................................................................................................. 15

[FIGURE 6 ] CHOOSE SETTING PAGE........................................................................................................................ 16

[FIGURE 7 ] CONNECTING WITH OPENICE32............................................................................................................. 20

User’s Manual V.0.10 5/36

EVB7400

Chapter 1 Introduction

EVB7400 is a MLN7400 evaluation board and MCS-uClinux training kit that is suitable for code development and exploration of MN7400 with MCS-uClinux. It includes much of the hardware and software required completing your application development. It supports various function related with network, communication such as IIC, SPI, UART, 10/100 Ethernet, multimedia module such as sound DAC, storage media such as NAND FLASH memory module. Using the JTAG interface, you can debug the EVB7400 directly.

1.1 System Requirements

-. Host computer : IBM compatible PC

-. EVB7400 (Evaluation Board for MLN7400)

-. DC 5V Power

Ethernet

PHY

(AC101L)

Boot ROM

(ROM Bank0)

User Flash

(ROM Bank1)

SRAM

(ROM Bank2)

JTAG

ARM7TDMI

4KBytes

Cache

10/100

Ethernet

MAC

2ch GDMA

Memory

Contro ller

DMA

M_Bus I/F

M_Bus

Peripheral

Bridge

X-Tal/Osc

PLL

Peripheral Bus

4 Console

UARTs

1 high-

speed

UART

I2C

SPI

GPIOs

4 channel

ADC

4 Timers

UART0~4

IIC Serial EEPROM

&RTC

SPI Serial EEPROM

DAC(CS4340)

MIC IN

KEY

MATRIX

NAND Flash

PCMCIA

Socket

(ROM Bank3)

SDRAM

[Figure 1 ] EVB7400 B

LOCK DIAGRAM

WDT

DAC I/F

Interrupt

Controller

Status

LEDs

Eextenal

Interrupt Key

User’s Manual V.0.10 6/36

EVB7400

ADDRESS MLN7400 MAP EVB7400 0x000_0000 ~ 0x0FF_FFFF ROM/Flash bank 0 (16Mbytes) FLASH(512KB)

0x100_0000 ~ 0x1FF_FFFF ROM/Flash bank 1 (16Mbytes) SRAM(128KB) 0x200_0000 ~ 0x2FF_FFFF ROM/Flash bank 2 (16Mbytes) FLASH(2MB) 0x300_0000 ~ 0x3FF_FFFF ROM/Flash bank 3 (16Mbytes) PCMCIA Card 0x400_0000 ~ 0x5FF_FFFF Cacheable SDRAM area (32Mbytes) SDRAM 64Mbits(8Mbytes) 0x600_0000 ~ 0x600_5FFF

(Cacheable) 0x800_0000 ~ 0xEFF_FFFF (Non-Cacheable) 0xF00_0000 ~ 0xFFF_FFFF SFR Registers

[Figure 2 ]

User’s Manual V.0.10 7/36

MEMORY MAP

EVB7400

1.2 Board Components

The arrangement of major components on the board is shown in Figure 3. The major components include:

[Figure 3 ] B

User’s Manual V.0.10 8/36

LOCK DIAGRAM (TOP VIEW)

EVB7400

A Flash ROM

There is a socket(U9) which accept 512Kbyte size of 8 bit Flash Memory(AT29C010 ~ 40). This is for diaganostic program(includes all pheriperal device driver and TCP/IP protocol stack) and BIOS(MCS-uClinux Boot loader) program.

User Flash memory(Selectable Boot ROM)

A mounted 48 TSOP type flash(AM29LV160BB), U8, is mounted for saving MCS-uClinux image. It has 2Mbytes(1M x 16bits)size. If you want to use this for boot ROM, SW2 should be set to to X16 and U9 should be removed. (The default setting is X8)

SDRAM SDRAM size is 8Mbytes ( 4M x 16bits)

SRAM There is a SRAM at ROM Bank1. SRAM SIZE is 64K x 16 bits.

NAND Flash A mounted NAND Flash ROM is provided for saving user data. To use NAND flash, you should install and uninstall some 0 ohm register at bottom of board. Please refer to chapter 2 and Schemetic.

EEPROM(AT24C256, AT25040)

There are two EEPROM(U3, U4). One is an IIC Serial EEPROM(U3) and the other is a SPI serial EEPROM(U4). The size of EEPROM(U3) is 32Kbytes, and the size of EEPROM(U4) is 4Kbytes.

RTC & Thermometer

There is a DS1629(U5) for RTC and thermometer check. The RTC clock is supplied by the crystal(32.768KHz)

Serial Port

There are 5 9-pin female Serial ports for serial data communiation. One is for console between the host PC and EVB7400 and others for converter(Serial to Ethernet, Serial to wireless and so on). And there is one 9-pin mail Serial ports for High Speed UART.

Ethernet Interface There are RJ45 connector and Ethernet Phy for network.(AC101L, 10/100 BASE-T)

AUDIO IN/OUT

There is a stereo DAC(CS4340) for AUDIO out. And MIC and AMP is connected to ADIN3(ADC channel3) for AUDIO In.

Reset Button

There is a button for system reset.

Power On/Off Switch There is a swithch for power on/off.

LED Indicatorst

Seven LEDs are supplied on the EVB7400. Each LED shows power status, user programmable status, ethernet link and activity.

PCMCIA Socket There is a PCMCIA Socket(J2). To use it, you should set ROM BANK3 as PCMCIA mode.

JTAG Port One 20-pin JTAG port(J3) is supplied to connect with JTAG based Emulator.

Expansion Connectors Seven connectors(JP2~JP8) are supplied for system expansion. They contain board data bus, adddress bus, external memory bank

control, IIC, SPI, and MII signals.

Key Matrix

There are 12 key buttons. They can be used ADC application. Five buttons(SW4, SW7, SW10, SW13, SW15) are connected to ADIN0(ADC channel 0).

User’s Manual V.0.10 9/36

EVB7400

Four buttons(SW5, SW8, SW11, SW14) are connected to ADIN1(ADC channel 1). Three buttons(SW5, SW8, SW11, SW14) are connected to ADIN2(ADC channel 2).

External Interrrupt Key

There are two button to use external interrupts. Each button(S1,S2) is connected to External interrupt0 and 2.

External Timer0 Clock

Timer0 can be supplied by the external clock(ocsillator)

User’s Manual V.0.10 10/36

EVB7400

Chapter 2 Board Configuration

The EVB7400 is set with default configuration. You can use the board with the defualt settings direclty. However, you can also change the settings according to your nedds.

2.1 Endian Selection (SW1)

Status Description BIG

LITTLE BIG

LITTLE

BIG Endian

Little Endian

2.2 Boot ROM and ROM Bank0 length Selection (SW2)

Status Description X8

X16 X8

X16

ROM BANK0 Size is 8 bits. ROM BANK0 : AT29C040 512 X 8bits Flash ROM BANK2 : AM29LV160BB 1M X 16bits Flash

ROM BANK 0 size is 16 bits. ROM BANK0 : AM29LV160BB 1M X 16 bits Flash

*Note : AT29C040(U9) should be removed

2.3 NAND FLASH

You can use NAND Flash through GPIO of MLN7400. To use NAND Flash you shoud install 0 ohm registance. Refer to schementic page4.

Install Register reference Unintall Register Reference R12, R13, R14, R15, R16, R17, R18, R19, R20, R21, R22, R23, R24, R25, R26

*Note: To use NAND Flash, you can’t use SPI Interface, Console UART3 and High Speed UART(UART4)

R39, R40, R41,R42, R43, R44, R54,R55,R56

User’s Manual V.0.10 11/36

EVB7400

2.4 GPIO Setting

<128-TQFP/ 144 -LQFP Common I/O> <144 -LQFP Extended I/O>

Setting

PIN Shared Initial GP00 CUTXD1 N,I UART1 S, O GP27 EXT_TCLK0 N,I Ext Timer0 Clk S, I GP01 CURXD1 N,I UART1 S, O GP28 EXT_TCLK1 N,I LED 2 N, O GP02 CUTXD2 N,I UART2 S, O GP29 EXT_TCLK2 N,I LED 3 N, O GP03 CURXD2 N,I UART2 S, O GP30 HUARTnDCD4 N,I NFIO0 N, I GP04 CUTXD3 N,I UART3/NFWEN S, O GP31 HUARTnCTS4 N,I NFIO1 N, I GP05 CURXD3 N,I UART3/NFWRN S, O GP32(0) HUARTnRTS4 N,I NFIO2 N, I GP06 CUTXD4 N,I UART4/NFALEN S, O GP33(1) HUARTnDSR4 N,I NFIO3 N, I GP07 CURXD4 N,I UART4/NFCLEN S, O GP34(2) HUARTnDTR4 N,I NFIO4 N, I GP08 nBE[0] N,I SRAM(nBE0) S, O GP35(3) EXINT2 N,I Ext Int2 Test S, I GP09 nBE[1] N,I SRAM(nBE1) S, O GP36(4) EXINT3 N,I NFIO5 N, I GP10 TOUT[0] N,I Timer0 TOUT0 S, O GP37(5) TOUT[2] N,I NFIO6 N, I GP11 TOUT[1] N,I SPI SS# N, O GP38(6) TOUT[3] N,I NFIO7 N, I GP12 TX_ERR S,0 LED 0 N, O GP39(7) DLRCK N,I DLRCK S, O GP13 NTRST S,I JTAG(nTRST) S, I GP40(8) DBCK N,I DBCK S, O GP14 ECSN2 S,O SRAM(ECSN2) S, O GP41(9) DMCK N,I DMCK S, O GP15 ECSN3/CE1# S,O PCMCIA(CE1#) S, O GP42(10) DDATA N,I DDATA S, O GP16 SPIMISO N,I SPI MISO/NFCEN S, I GP17 SPIMOSI N,I SPI MOSI/NFRDN S, O GP18 SPICLK N,I SPI Clock/NFRBN S, O S : Special GP19 EXINT0 N,I Ext Int0 Test S, I N : Noraml GP20 EXINT1 N,I PCMCIA IRQ S, I I : Input GP21 EXT_UCLK N,I LED 1 N, O O : Output GP22 REG#/DLRCK N,I PCMCIA REG#/DLRCK S, O GP23 CE2#/DBCK S,O PCMCIA CE2#/DBCK S, O GP24 IORD#/DMCK N,I PCMCIA IORD#DMCK S, O GP25 IOWR#/DDATA N,I PCMCIA IOWR#/DDATA S, O GP26 ENWAIT N,I PCMCIA ENWAIT S, O

Board Setting

Value PIN Shared Initial Board Setting

1) GP22 ~GP25 는 7400P 의 경우 PCMCIA 와 DAC 을 선택적으로 사용

Setting Value

User’s Manual V.0.10 12/36

ADC MLN7400 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Chapter 1 Introduction

Chapter 2 Board Configuration

2.2 Boot ROM and ROM Bank0 length Selection (SW2)