ADC ADC080XLCD Service Manual

INTEGRATED CIRCUITS

ADC0803/0804

CMOS 8-bit A/D converters

Product data
Supersedes data of 2001 Aug 03

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2002 Oct 17

Philips Semiconductors Product data

ADC0803/0804CMOS 8-bit A/D converters

DESCRIPTION

The ADC0803 family is a series of three CMOS 8-bit successive
approximation A/D converters using a resistive ladder and
capacitive array together with an auto-zero comparator. These
converters are designed to operate with microprocessor-controlled
buses using a minimum of external circuitry. The 3-State output data
lines can be connected directly to the data bus.

The differential analog voltage input allows for increased
common-mode rejection and provides a means to adjust the
zero-scale offset. Additionally, the voltage reference input provides a
means of encoding small analog voltages to the full 8 bits of
resolution.

FEATURES

•Compatible with most microprocessors

•Differential inputs

•3-State outputs

•Logic levels TTL and MOS compatible

•Can be used with internal or external clock

•Analog input range 0 V to V

CC

•Single 5 V supply

•Guaranteed specification with 1 MHz clock

PIN CONFIGURATION

D

N PACKAGES

,

CLK IN

INTR

VIN(+)
V

IN

A GND

V

REF

D GND

CS
RD

WR

1
2
3
4
5
6
7

(–)

8
9

/2

10

TOP VIEW

20

V

19

CLK R
D0

18
17

D1
D2

16

D3

15

D4

14

D5

13

D6

12

D7

11

SL00016

CC

Figure 1. Pin configuration

APPLICATIONS

•Transducer-to-microprocessor interface

•Digital thermometer

•Digitally-controlled thermostat

•Microprocessor-based monitoring and control systems

ORDERING INFORMATION

DESCRIPTION

20-pin plastic small outline (SO) package 0 to 70 °C ADC0803CD, ADC0804CD ADC0803-1CD, ADC0804-1CD SOT163-1
20-pin plastic small outline (SO) package –40 to 85 °C ADC0803LCD, ADC0804LCD ADC0803-1LCD, ADC0804-1LCD SOT163-1
20-pin plastic dual in-line package (DIP) 0 to 70 °C ADC0803CN, ADC0804CN ADC0803-1CN, ADC0804-1CN SOT146-1
20-pin plastic dual in-line package (DIP) –40 to +85 °C ADC0803LCN, ADC0804LCN ADC0803-1LCN, ADC0804-1LCN SOT146-1

TEMPERATURE

RANGE

ORDER CODE TOPSIDE MARKING DWG #

ABSOLUTE MAXIMUM RATINGS

SYMBOL PARAMETER CONDITIONS RATING UNIT

V

CC

T

amb

T

stg

T

sld

P

D

NOTE:

1. Derate above 25 °C, at the following rates: N package at 13.5 mW/°C; D package at 11.1 mW/ °C.

Supply voltage 6.5 V
Logic control input voltages –0.3 to +16 V
All other input voltages –0.3 to (VCC +0.3) V
Operating temperature range

ADC0803LCD/ADC0804LCD –40 to +85 °C
ADC0803LCN/ADC0804LCN –40 to +85 °C
ADC0803CD/ADC0804CD 0 to +70 °C

ADC0803CN/ADC0804CN 0 to +70 °C
Storage temperature –65 to +150 °C
Lead soldering temperature (10 seconds) 230 °C
Maximum power dissipation

1

T

= 25 °C (still air)

amb

N package 1690 mW

D package 1390 mW

2002 Oct 17

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Philips Semiconductors Product data

ADC0803/0804CMOS 8-bit A/D converters

BLOCK DIAGRAM

V

REF

A GND

V

D GND

WR

CC

VIN (+) VIN (–)

+

–

M

9

/2

8

LADDER AND

DECODER

20

SAR

10

3

8–BIT

SHIFT REGISTER

CLOCK

76

+

AUTO ZERO
COMPARATOR

–

OUTPUT

LATCHES

LE OE

D7 (MSB) (11)
D6 (12)

D5 (13)
D4 (14)

D3 (15)
D2 (16)
D1 (17)
D0 (LSB) (18)

CS

RD

1

S

INTR

FF

2

RQ

INTR

5419

CLK IN

CLK R

SL00017

Figure 2. Block diagram

2002 Oct 17

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Philips Semiconductors Product data

SYMBOL

PARAMETER

TEST CONDITIONS

UNIT

VOHLogical “1” output voltage

V

ADC0803/0804CMOS 8-bit A/D converters

DC ELECTRICAL CHARACTERISTICS

V

= 5.0 V, f

CC

R

IN

Control inputs

V

IH

V

IL

I

IH

I

IL

Clock in and clock R

VT+ Clock in positive-going threshold voltage 2.7 3.1 3.5 V
VT– Clock in negative-going threshold voltage 1.5 1.8 2.1 V
V

H

V

OL

V

OH

Data output and INTR

V

OL

I

OZL

I

OZH

I

SC

I

SC

I

CC

NOTES:

1. Analog inputs must remain within the range: –0.05 ≤ V

2. See typical performance characteristics for input resistance at V

3. V

/2 and VIN must be applied after the VCC has been turned on to prevent the possibility of latching.

REF

= 1 MHz, T

CLK

min

≤ T

amb

≤ T

, unless otherwise specified.

max

LIMITS

Min Typ Max

ADC0803 relative accuracy error (adjusted) Full-Scale adjusted 0.50 LSB
ADC0804 relative accuracy error (unadjusted) V
V

/2 input resistance

REF

Analog input voltage range

3

3

/2 = 2.500 V

REF

VCC = 0 V

DC

2

400 680 Ω

1 LSB

–0.05 VCC+0.05 V

DC common-mode error Over analog input voltage range 1/16 1/8 LSB

DC
DC

DC
DC

1

2.0 15 V

1/16 LSB

DC

0.8 V

DC

0.005 1 µA

–1 –0.005 µA

DC
DC
DC

DC

DC

2.4 V

0.4 V

DC
DC

Power supply sensitivity VCC = 5V ±10%

Logical “1” input voltage VCC = 5.25 V
Logical “0” input voltage VCC = 4.75 V
Logical “1” input current VIN = 5 V
Logical “0” input current VIN = 0 V

Clock in hysteresis (VT+)–(VT–) 0.6 1.3 2.0 V
Logical “0” clock R output voltage IOL = 360 µA, VCC = 4.75 V
Logical “1” clock R output voltage IOH = –360 µA, VCC = 4.75 V

Logical “0” output voltage
Data outputs IOL = 1.6 mA, VCC = 4.75 V
INTR outputs IOL = 1.0 mA, VCC = 4.75 V

“

”

p

3-State output leakage V
3-State output leakage V
+Output short-circuit current V
–Output short-circuit current V

Power supply current

IOH = –360 µA, VCC = 4.75 V

IOH = –10 µA, VCC = 4.75 V

= 0 VDC, CS = logical “1” –3 µA

OUT

= 5 VDC, CS = logical “1” 3 µA

OUT

= 0 V, T

OUT

= VCC, T

OUT

f

= 1 MHz, V

CLK

CS

= Logical “1”, T

≤ VCC + 0.05 V.

IN

CC

= 5 V.

= 25 °C 4.5 12 mA

amb

= 25 °C 9.0 30 mA

amb

/2 = OPEN,

REF

= 25 °C

amb

DC
DC

DC

DC

2.4

4.5

3.0 3.5 mA

0.4 V

0.4 V

DC
DC

DC

DC
DC

DC
DC

DC
DC

2002 Oct 17

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Philips Semiconductors Product data

SYMBOL

PARAMETER

TO

FROM

TEST CONDITIONS

UNIT

ADC0803/0804CMOS 8-bit A/D converters

AC ELECTRICAL CHARACTERISTICS

LIMITS

Min Typ Max

CLK

1

= 1 MHz

66 73 µs

0.1 1.0 3.0 MHz
40 60 %

13690 conv/s

70 100 ns

100 150 ns

Conversion time f

f

CLK

Clock frequency
Clock duty cycle

1
1

CR Free-running conversion rate

CLK

CS = 0, f

INTR

= 1 MHz

tied to WR
tW(WR)L Start pulse width CS = 0 30 ns
t

ACC

t1H, t

tW1, t
C

IN

C

OUT

0H

Access time Output RD CS = 0, CL = 100 pF 75 100 ns
3-State control Output RD

INTR delay INTR

R1

WD

or RD

CL = 10 pF, RL = 10 kΩ

See 3-State test circuit

Logic input=capacitance 5 7.5 pF
3-State output capacitance 5 7.5 pF

NOTE:

1. Accuracy is guaranteed at f

= 1 MHz. Accuracy may degrade at higher clock frequencies.

CLK

FUNCTIONAL DESCRIPTION

These devices operate on the Successive Approximation principle.
Analog switches are closed sequentially by successive
approximation logic until the input to the auto-zero comparator
[V

(+)–VIN(–) ] matches the voltage from the decoder . After all bits

IN

are tested and determined, the 8-bit binary code corresponding to
the input voltage is transferred to an output latch. Conversion begins
with the arrival of a pulse at the WR

input if the CS input is low. On
the High-to-Low transition of the signal at the WR or the CS input,
the SAR is initialized, the shift register is reset, and the INTR

output
is set high. The A/D will remain in the reset state as long as the CS
and WR inputs remain low. Conversion will start from one to eight
clock periods after one or both of these inputs makes a Low-to-High
transition. After the conversion is complete, the INTR

pin will make a
High-to-Low transition. This can be used to interrupt a processor, or
otherwise signal the availability of a new conversion result. A read
(RD

) operation (with CS low) will clear the INTR line and enable the
output latches. The device may be run in the free-running mode as
described later. A conversion in progress can be interrupted by
issuing another start command.

Digital Control Inputs

The digital control inputs (CS, WR, RD) are compatible with
standard TTL logic voltage levels. The required signals at these
inputs correspond to Chip Select, STAR T Conversion, and Output
Enable control signals, respectively. They are active-Low for easy
interface to microprocessor and microcontroller control buses. For
applications not using microprocessors, the CS
grounded and the A/D STAR T function is achieved by a
negative-going pulse to the WR

input (Pin 3). The Output Enable
function is achieved by a logic low signal at the RD
which may be grounded to constantly have the latest conversion
present at the output.

input (Pin 1) can be

input (Pin 2),

ANALOG OPERATION
Analog Input Current

The analog comparisons are performed by a capacitive charge
summing circuit. The input capacitor is switched between V
and V

, while reference capacitors are switched between taps on

IN(–)

IN(+)

4

the reference voltage divider string. The net charge corresponds to
the weighted difference between the input and the most recent total
value set by the successive approximation register.

The internal switching action causes displacement currents to flow
at the analog inputs. The voltage on the on-chip capacitance is
switched through the analog differential input voltage, resulting in
proportional currents entering the V

input and leaving the V

IN(+)

IN(–)

input. These transient currents occur at the leading edge of the
internal clock pulses. They decay rapidly so do not inherently cause
errors as the on-chip comparator is strobed at the end of the clock
period.

Input Bypass Capacitors and Source Resistance

Bypass capacitors at the input will average the charges mentioned
above, causing a DC and an AC current to flow through the output
resistance of the analog signal sources. This charge pumping action
is worse for continuous conversions with the V
scale. This current can be a few microamps, so bypass capacitors
should NOT be used at the analog inputs of the V
high resistance sources (> 1 kΩ). If input bypass capacitors are
desired for noise filtering and a high source resistance is desired to
minimize capacitor size, detrimental effects of the voltage drop
across the input resistance can be eliminated by adjusting the full
scale with both the input resistance and the input bypass capacitor
in place. This is possible because the magnitude of the input current
is a precise linear function of the differential voltage.

input at full

IN(+)

REF

/2 input for

2002 Oct 17

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Philips Semiconductors Product data

ADC0803/0804CMOS 8-bit A/D converters

Large values of source resistance where an input bypass capacitor
is not used will not cause errors as the input currents settle out prior
to the comparison time. If a low pass filter is required in the system,
use a low valued series resistor (< 1 kΩ) for a passive RC section or
add an op amp active filter (low pass). For applications with source

resistances at or below 1 kΩ, a 0.1 µF bypass capacitor at the inputs

will prevent pickup due to series lead inductance or a long wire. A
100 Ω series resistor can be used to isolate this capacitor (both the
resistor and capacitor should be placed out of the feedback loop)
from the output of the op amp, if used.

Analog Differential Voltage Inputs and
Common-Mode Rejection

These A/D converters have additional flexibility due to the analog
differential voltage input. The V

input (Pin 7) can be used to

IN(–)

subtract a fixed voltage from the input reading (tare correction). This
is also useful in a 4/20 mA current loop conversion. Common-mode
noise can also be reduced by the use of the differential input.

The time interval between sampling V

IN(+)

and V

is 4.5 clock

IN(–)

periods. The maximum error due to this time difference is given by:

V(max) = (V

) (2fCM) (4.5/f

P

CLK

),

where:

V = error voltage due to sampling delay
V

= peak value of common-mode voltage

P

f

= common mode frequency

CM

For example, with a 60 Hz common-mode frequency, f
1 MHz A/D clock, f
would allow a common-mode voltage, V

[V(max) (f

+

V

P

(2f

, keeping this error to 1/4 LSB (about 5 mV)

CM

CLK

)(4.5)

CLK

)

, which is given by:

P

cm

, and a

or

*3

V

+

P

(5 x 10

(6.28) (60) (4.5)

)(104)

+ 2.95V

The allowed range of analog input voltages usually places more
severe restrictions on input common-mode voltage levels than this,
however.

An analog input span less than the full 5 V capability of the device,
together with a relatively large zero offset, can be easily handled by
use of the differential input. (See Reference Voltage Span Adjust).

Noise and Stray Pickup

The leads of the analog inputs (Pins 6 and 7) should be kept as
short as possible to minimize input noise coupling and stray signal
pick-up. Both EMI and undesired digital signal coupling to these
inputs can cause system errors. The source resistance for these
inputs should generally be below 5 kΩ to help avoid undesired noise
pickup. Input bypass capacitors at the analog inputs can create
errors as described previously. Full scale adjustment with any input
bypass capacitors in place will eliminate these errors.

Reference Voltage

For application flexibility , these A/D converters have been designed
to accommodate fixed reference voltages of 5V to Pin 20 or 2.5 V to
Pin 9, or an adjusted reference voltage at Pin 9. The reference can
be set by forcing it at V
supply voltage (Pin 20). Figure 6 indicates how this is accomplished.

/2 input, or can be determined by the

REF

Reference Voltage Span Adjust

Note that the Pin 9 (V
to the V
forced at the V

supply pin, or is equal to the voltage which is externally

CC

REF

references and full span voltages, this also allows for a ratiometric
voltage reference. The internal gain of the V
the full-scale differential input voltage twice the voltage at Pin 9.

For example, a dynamic voltage range of the analog input voltage
that extends from 0 to 4 V gives a span of 4 V (4–0), so the V
voltage can be made equal to 2 V (half of the 4 V span) and full
scale output would correspond to 4 V at the input.

On the other hand, if the dynamic input voltage had a range of

0.5 to 3.5 V , the span or dynamic input range is 3 V (3.5–0.5). To
encode this 3 V span with 0.5 V yielding a code of zero, the
minimum expected input (0.5 V, in this case) is applied to the V
pin to account for the offset, and the V
span, or 1.5 V. The A/D converter will now encode the V
between 0.5 and 3.5 V with 0.5 V at the input corresponding to a
code of zero and 3.5 V at the input producing a full scale output
code. The full 8 bits of resolution are thus applied over this reduced
input voltage range. The required connections are shown in
Figure 7.

/2) voltage is either 1/2 the voltage applied

REF

/2 pin. In addition to allowing for flexible

/2 input is 2, making

REF

/2 pin is set to 1/2 the 3 V

REF

REF

(+) signal

IN

/2

(–)

IN

Operating Mode

These converters can be operated in two modes:

1) absolute mode

2) ratiometric mode

In absolute mode applications, both the initial accuracy and the
temperature stability of the reference voltage are important factors in
the accuracy of the conversion. For V

/2 voltages of 2.5 V , initial

REF

errors of ±10 mV will cause conversion errors of ±1 LSB due to the
gain of 2 at the V
value and stability of the V
important as the same error is a larger percentage of the V

/2 input. In reduced span applications, the initial

REF

/2 input voltage become even more

REF

REF

/2

nominal value. See Figure 8.
In ratiometric converter applications, the magnitude of the reference

voltage is a factor in both the output of the source transducer and
the output of the A/D converter, and, therefore, cancels out in the
final digital code. See Figure 9.

Generally , the reference voltage will require an initial adjustment.
Errors due to an improper reference voltage value appear as
full-scale errors in the A/D transfer function.

ERRORS AND INPUT SPAN ADJUSTMENTS

There are many sources of error in any data converter, some of
which can be adjusted out. Inherent errors, such as relative
accuracy, cannot be eliminated, but such errors as full-scale and
zero scale offset errors can be eliminated quite easily . See Figure 7.

Zero Scale Error

Zero scale error of an A/D is the difference of potential between the
ideal 1/2 LSB value (9.8 mV for V
voltage which just causes an output transition from code 0000 0000
to a code of 0000 0001.

If the minimum input value is not ground potential, a zero offset can
be made. The converter can be made to output a digital code of
0000 0000 for the minimum expected input voltage by biasing the

(–) input to that minimum value expected at the VIN(–) input to

V

IN

that minimum value expected at the V
differential mode of the converter . Any offset adjustment should be
done prior to full scale adjustment.

/2=2.500 V) and that input

REF

(+) input. This uses the

IN

2002 Oct 17

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