ACTEL eX64, eX128, eX256 User Manual

查询EX128-FTQ100供应商

eX Family FPGAs

Leading Edge Performance

•240 MHz System Performance

• 3.9ns Clock-to-Out (Pad-to-Pad)

• 350 MHz Internal Performance

Specifications

• 3,000 to 12,000 Available System Gates

• As Many as 512 Maximum Flip-Flops (Using CC Macros)

µ CMOS Process Technology

•0.22

• Up to 132 User-Programmable I/O Pins

Features

• High-Performance, Low-Power Antifuse FPGA

• LP/Sleep Mode for Additional Power Savings

• Advanced Small-footprint Packages

• Hot-Swap Compliant I/Os

• Single-Chip Solution

• Nonvolatile

•Live on power up

• Power-Up/Down Friendly (No Sequencing Required for Supply Voltages)

• Configurable Weak-Resistor Pull-Up or Pull-Down for Tristated Outputs during Power Up

v3.0

• Individual Output Slew Rate Control

• 2.5V, 3.3V, and 5.0V Mixed Voltage Operation with 5.0V Input Tolerance and 5.0V Drive Strength

• Software Design Support with Actel Designer Series and Libero Tools

• Up to 100% Resource Utilization with 100% Pin Locking

• Deterministic Timing

• Unique In-System Diagnostic and Verification Capability with Silicon Explorer II

• Boundary Scan Testing in Compliance with IEEE Standard

1149.1 (JTAG)

• Secure Programming Technology Prevents Reverse Engineering and Design Theft

General Description

The eX family of FPGAs is a low-cost solution for low-power, high-performance designs. The inherent low power attributes of the antifuse technology, coupled with an additional low static power mode, make these devices ideal for power-sensitive applications. Fabricated with an advanced 0.22 achieve high performance with no power penalty

µ CMOS antifuse technology, these devices

eX Product Profile

Device eX64 eX128 eX256 Capacity

System Gates Typical Gates

Register Cells (Dedicated Flip-Flops) 64 128 256 Combinatorial Cells 128 256 512 Maximum User I/Os 84 100 132 Speed Grades –F, Std, –P –F, Std, –P –F, Std, –P Temperature Grades C, I C, I C, I Package (by pin count)

TQFP CSP

December 2001 1

3,000 2,000

64, 100 49, 128

6,000 4,000

64, 100 49, 128

12,000

8,000

100

128, 180

Ordering Information

eX Family FPGAs

eX128 TQ 100

–P

Application (Temperature Range)

Blank = Commercial (0 to +70°C)

I = I ndustrial (–40 to +85°C)

PP = Pre-production

Package Lead Count

Package Type

TQ = Thin (1.4mm) Quad Flat Pack CS = Chip-Scale Package (0.8mm pitch)

Speed Grade

Blank = Standard Speed

–P = Approximately 30% Faster than Standard –F = Approximately 40% Slower than Standard

Part Number

eX64 = 64 Dedicated Flip-Flops (3,000 System Gates) eX128 = 128 Dedicated Flip-Flops (6,000 System Gates) eX256 = 256 Dedicated Flip-Flops (12,000 System Gates)

Product Plan

Speed Grade Application

–FStd–PCI

eX64 Device

64-Pin Thin Quad Flat Pack (TQFP) ✔✔✔ ✔✔ 100-Pin Thin Quad Flat Pack (TQFP) ✔✔✔ ✔✔ 49-Pin Chip Scale Package (CSP) ✔✔✔ ✔✔ 128-Pin Chip Scale Package (CSP) ✔✔✔ ✔✔

eX128 Device

eX256 Device

100-Pin Thin Quad Flat Pack (TQFP) ✔✔✔ ✔✔ 128-Pin Chip Scale Package (CSP) ✔✔✔ ✔✔ 180-Pin Chip Scale Package (CSP) ✔✔✔ ✔✔

Contact your Actel sales representative for product availability. Speed Grade: –P = Approx. 30% faster than Standard Availability: ✔ = Available Applications: C = Commercial

–F = Approx. 40% slower than Standard I = Industrial

† Only Std Speed Grade

†

Plastic Device Resources

User I/Os (including clock buffers)

Device TQFP 64-Pin TQFP 100-Pin CSP 49-Pin CSP 128-Pin CSP 180-Pin

eX64 41 56 36 84 — eX128 46 70 36 100 — eX256 — 81 — 100 132

Package Definitions: TQFP = Thin Quad Flat Pack, CSP = Chip Scale Package

2v3.0

eX Family FPGAs

eX Family Architecture

The eX family architecture uses a “sea-of-modules” structure where the entire floor of the device is covered with a grid of logic modules with virtually no chip area lost to interconnect elements or routing. Interconnection among these logic modules is achieved using Actel’s patented metal-to-metal programmable antifuse interconnect elements. Actel’s eX family provides two types of logic modules, the register cell (R-cell) and the combinatorial cell (C-cell).

The R-cell contains a flip-flop featuring asynchronous clear, asynchronous preset, and clock enable (using the S0 and S1 lines) control signals (Figure 1). The R-cell registers feature programmable clock polarity selectable on a register-by-register basis. This provides additional flexibility while allowing mapping of synthesized functions into the eX FPGA. The clock source for the R-cell can be chosen from either the hard-wired clock or the routed clock.

Routed

Data Input

The C-cell implements a range of combinatorial functions up to 5 inputs (Figure 2). Inclusion of the DB input and its associated inverter function dramatically increases the number of combinatorial functions that can be implemented in a single module from 800 options in previous architectures to more than 4,000 in the eX architecture.

Module Organization

Actel has arranged all C-cell and R-cell logic modules into horizontal banks called Clusters. The eX devices contain one type of Cluster, which contains two C-cells and one R-cell.

To increase design efficiency and device performance, Actel has further organized these modules into SuperClusters (Figure 3 on page 4). The eX devices contain one type of SuperClusters, which are two-wide groupings of one type of clusters.

Figure 1 • R-Cell

DirectConnect

Input

HCLK

CLKA, CLKB,

Internal Logic

CKS

CKP

PSET

CLR

Figure 2 • C-Cell

A0 B0

v3.0 3

eX Family FPGAs

Routing Resources

Clusters and SuperClusters can be connected through the use of two innovative local routing resources called FastConnect and DirectConnect, which enable extremely fast and predictable interconnection of modules within Clusters and SuperClusters (Figure 4). This routing architecture also dramatically reduces the number of antifuses required to complete a circuit, ensuring the highest possible performance.

DirectConnect is a horizontal routing resource that provides connections from a C-cell to its neighboring R-cell in a given SuperCluster. DirectConnect uses a hard-wired signal path requiring no programmable interconnection to achieve its fast signal propagation time of less than 0.1 ns (–P speed grade).

R-Cell C-Cell

Routed

Data Input

PSET

DirectConnect

Input

FastConnect enables horizontal routing between any two logic modules within a given SuperCluster and vertical routing with the SuperCluster immediately below it. Only one programmable connection is used in a FastConnect path, delivering maximum pin-to-pin propagation of 0.3 ns (–P speed grade).

In addition to DirectConnect and FastConnect, the architecture makes use of two globally oriented routing resources known as segmented routing and high-drive routing. Actel’s segmented routing structure provides a variety of track lengths for extremely fast routing between SuperClusters. The exact combination of track lengths and antifuses within each path is chosen by the 100 percent automatic place-and-route software to minimize signal propagation delays.

YDQ

Sa Sb

HCLK

CLKA, CLKB,

Internal Logic

CKS CKP

Figure 3 • Cluster Organization

Type 1 SuperClusters

CLR

Cluster 1 Cluster 1

Type 1 SuperCluster

A0 B0 A1 B1

DirectConnect

• No antifuses

• 0.1 ns routing delay

FastConnect

• One antifuse

• 0.3 ns routing delay

Routing Segments

• Typically 2 antifuses

• Max. 5 antifuses

Figure 4 • DirectConnect and FastConnect for Type 1 SuperClusters

4v3.0

eX Family FPGAs

Clock Resources

Actel’s high-drive routing structure provides three clock networks. The first clock, called HCLK, is hardwired from the HCLK buffer to the clock select MUX in each R-Cell. HCLK cannot be connected to combinational logic. This provides a fast propagation path for the clock signal, enabling the 3.9ns clock-to-out (pad-to-pad) performance of the eX devices. The hard-wired clock is tuned to provide a clock skew of less than 0.1ns worst case.

The remaining two clocks (CLKA, CLKB) are global clocks that can be sourced from external pins or from internal logic signals within the eX device. CLKA and CLKB may be connected to sequential cells or to combinational logic. If CLKA or CLKB is sourced from internal logic signals then the external clock pin cannot be used for any other input and must be tied low or high. Figure 5 describes the clock circuit used for the constant load HCLK. Figure 6 describes the CLKA and CLKB circuit used in eX devices.

Constant Load Clock Network

HCLKBUF

Figure 5 • eX HCLK Clock Pad

Clock Network

From Internal Logic

CLKBUF CLKBUFI CLKINT CLKINTI

Figure 6 • eX Routed Clock Buffer

Other Architectural Features

Technology

Actel’s eX family is implemented on a high-voltage twin-well CMOS process using 0.22

µ design rules. The metal-to-metal

antifuse is made up of a combination of amorphous silicon and dielectric material with barrier metals and has an “on” state resistance of 25

Ω with a capacitance of 1.0 fF for low

signal impedance.

Performance

The combination of architectural features described above enables eX devices to operate with internal clock frequencies exceeding 350 MHz for very fast execution of complex logic functions. Thus, the eX family is an optimal

platform upon which to integrate the functionality previously contained in CPLDs. In addition, designs that previously would have required a gate array to meet performance goals can now be integrated into an eX device with dramatic improvements in cost and time to market. Using timing-driven place-and-route tools, designers can achieve highly deterministic device performance.

I/O Modules

Each I/O on an eX device can be configured as an input, an output, a tristate output, or a bidirectional pin. Even without the inclusion of dedicated I/O registers, these I/Os, in combination with array registers, can achieve clock-to-out (pad-to-pad) timing as fast as 3.9ns. I/O cells that have embedded latches and flip-flops require instantiation in HDL code; this is a design complication not encountered in eX FPGAs. Fast pin-to-pin timing ensures that the device will have little trouble interfacing with any other device in the system, which in turn enables parallel design of system components and reduces overall design time. See Table 1 for more information.

Table 1 • I/O Features

Function Description

Input Buffer Threshold Selection

Flexible Output Driver

Output Buffer

Power Up Individually selectable pull ups and pull

Hot Swapping

• TTL/3.3V LVTTL

• 2.5V LVCMOS 2

• 3.3V LVTTL

• 5.0V TTL/CMOS “Hot-Swap” Capability

• I/O on an unpowered device does not

sink current

• Can be used for “cold sparing” Selectable on an individual I/O basis Individually selectable low-slew option

downs during power up (default is to power up in tristate)

Enables deterministic power up of device V

CCA

and V

can be powered in any order

CCI

eX I/Os are configured to be hot swappable. During power up/down (or partial up/down), all I/Os are tristated. V and V

do not have to be stable during power up/down,

CCI

CCA

and they do not require a specific power-up or power-down sequence in order to avoid damage to the eX devices. After the eX device is plugged into an electrically active system, the device will not degrade the reliability of or cause damage to the host system. The device’s output pins are driven to a high impedance state until normal chip

v3.0 5

eX Family FPGAs

operating conditions are reached. Please see the Actel SX-A and RT54SX-S Devices in Hot-Swap and Cold-Sparing Applications application note for more information on hot

swapping.

Power Requirements

The eX family supports mixed voltage operation and is designed to tolerate 5.0V inputs in each case (Table 2). Power consumption is extremely low due to the very short distances signals, which are required to travel to complete a circuit. Power requirements are further reduced because of the small number of low-resistance antifuses in the path. The antifuse architecture does not require active circuitry to hold a charge (as do SRAM or EPROM), making it the lowest-power architecture FPGA available today. Also, when the device is in low power mode, the clock pins must not float. They must be driven either HIGH or LOW. We recommend that signals driving the clock pins be fixed at HIGH or LOW rather than toggle to achieve maximum power efficiency.

Table 2 • Supply Voltages

CCA

eX64 eX128 eX256

Low Power Mode

2.5V 2.5V 5.0V 2.5V

2.5V 3.3V 5.0V 3.3V

2.5V 5.0V 5.0V 5.0V

Maximum

CCI

Input

Tolerance

Maximum

Output

Drive

The new Actel eX family has been designed with a Low Power Mode. This feature, activated with a special LP pin, is particularly useful for battery-operated systems where battery life is a primary concern. In this mode, the core of the device is turned off and the device consumes minimal power with low standby current. In addition, all input buffers are turned off, and all outputs and bidirectional buffers are tristated when the device enters this mode. Since the core of the device is turned off, the states of the registers are lost. The device must be re-initialized when normal operating mode is achieved.

2.5V LP/Sleep Mode Specifications Typical Conditions, V

Product Low Power Standby Current Units

eX64 100 µA eX128 111 µA eX256 134 µA

Boundary Scan Testing (BST)

CCA

, V

= 2.5V, TJ = 25° C

CCI

All eX devices are IEEE 1149.1 compliant. eX devices offer superior diagnostic and testing capabilities by providing Boundary Scan Testing (BST) and probing capabilities. These functions are controlled through the special test pins

in conjunction with the program fuse. The functionality of each pin is described in Table 3. In the dedicated test mode, TCK, TDI, and TDO are dedicated pins and cannot be used as regular I/Os. In flexible mode, TMS should be set HIGH through a pull-up resistor of 10k

Ω. TMS can be pulled LOW

to initiate the test sequence.

Table 3 • Boundary Scan Pin Functionality

Program Fuse Blown (Dedicated Test Mode)

TCK, TDI, TDO are dedicated BST pins

No need for pull-up resistor for TMS

Configuring Diagnostic Pins

Program Fuse Not Blown (Flexible Mode)

TCK, TDI, TDO are flexible and may be used as I/Os

Use a pull-up resistor of 10k

Ω on TMS

The JTAG and Probe pins (TDI, TCK, TMS, TDO, PRA, and PRB) are placed in the desired mode by selecting the appropriate check boxes in the “Variation” dialog window. This dialog window is accessible through the Design Setup Wizard under the Tools menu in Actel's Designer software.

TRST Pin

When the “Reserve JTAG Reset” box is checked, the TRST pin will become a Boundary Scan Reset pin. In this mode, the TRST pin will function as an asynchronous, active-low input to initialize or reset the BST circuit. An internal pull-up resistor will be automatically enabled on the TRST pin.

The TRST pin will function as a user I/O when the “Reserve JTAG Reset” box is not checked. The internal pull-up resistor will be disabled in this mode.

Dedicated Test Mode

When the “Reserve JTAG” box is checked, the eX device is placed in Dedicated Test mode, which configures the TDI, TCK, and TDO pins for BST or in-circuit verification with Silicon Explorer II. An internal pull-up resistor is automatically enabled on both the TMS and TDI pins. In Dedicated Test Mode, TCK, TDI, and TDO are dedicated test pins and become unavailable for pin assignment in the Pin Editor. The TMS pin will function as specified in the IEEE

1149.1 (JTAG) Specification.

Flexible Mode

When the “Reserve JTAG” box is not selected (default setting in Designer software), eX is placed in Flexible mode, which allows the TDI, TCK, and TDO pins to function as user I/Os or BST pins. In this mode the internal pull-up resistors on the TMS and TDI pins are disabled. An external 10k pull-up resistor to V

is required on the TMS pin.

CCI

Ω

The TDI, TCK, and TDO pins are transformed from user I/Os into BST pins when a rising edge on TCK is detected while TMS is at logical low. Once the BST pins are in test mode they will remain in BST mode until the internal BST state

6v3.0

eX Family FPGAs

machine reaches the “logic reset” state. At this point the BST pins will be released and will function as regular I/O pins. The “logic reset” state is reached five TCK cycles after the TMS pin is set to logical HIGH.

The Program fuse determines whether the device is in Dedicated Test or Flexible mode. The default (fuse not programmed) is Flexible mode.

Development Tool Support

The eX devices are fully supported by Actel’s line of FPGA development tools, including the Actel Designer Series suite and Libero, the FPGA design tool suite. Designer Series, Actel’s suite of FPGA development tools for PCs and Workstations, includes the ACTgen Macro Builder, timing driven place-and-route, timing analysis tools, and fuse file generation. Libero is a design management environment that integrates the needed design tools, streamlines the design flow, manages all design and log files, and passes necessary design data between tools. Libero includes Synplify, ViewDraw, Actel’s Designer Series, ModelSim HDL Simulator, WaveFormer Lite, and Actel Silicon Explorer.

In addition, the eX devices contain internal probe circuitry that provides built-in access to the output of every C-cell, R-cell, and routed clock in the design, enabling 100-percent real-time observation and analysis of a device's internal logic nodes without design iteration. The probe circuitry is accessed by Silicon Explorer II, an easy-to-use integrated

verification and logic analysis tool that can sample data at 100 MHz (asynchronous) or 66 MHz (synchronous). Silicon Explorer II attaches to a PC’s standard COM port, turning the PC into a fully functional 18-channel logic analyzer. Silicon Explorer II allows designers to complete the design verification process at their desks and reduces verification time from several hours per cycle to only a few seconds.

eX Probe Circuit Control Pins

The Silicon Explorer II tool uses the boundary scan ports (TDI, TCK, TMS and TDO) to select the desired nets for verification. The selected internal nets are assigned to the PRA/PRB pins for observation. Figure 7 illustrates the interconnection between Silicon Explorer II and the FPGA to perform in-circuit verification. The TRST pin is equipped with an internal pull-up resistor. To remove the boundary scan state machine from the reset state during probing, it is recommended that the TRST pin be left floating.

Design Considerations

For prototyping, the TDI, TCK, TDO, PRA, and PRB pins should not be used as input or bidirectional ports. Because these pins are active during probing, critical signals input through these pins are not available while probing. In addition, the Security Fuse should not be programmed because doing so disables the probe circuitry.

Figure 7 • Probe Setup

Serial Connection

Channels

eX FPGA

TDI TCK TMS

Silicon Explorer II

TDO

PRA

PRB

v3.0 7

eX Family FPGAs

2.5V/3.3V/5.0V Operating Conditions

Absolute Maximum Ratings

Symbol Parameter Limits Units

V V V V T

CCI CCA I O STG

DC Supply Voltage –0.3 to +6.0 V DC Supply Voltage –0.3 to +3.0 V Input Voltage –0.5 to +5.5 V Output Voltage –0.5 to +V Storage Temperature –65 to +150 °C

Note:

1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure

+ 0.5 V

CCI

Recommended Operating Conditions

Parameter Commercial Industrial Units

Temperature

Range

2.5V Power Supply Range (V

CCA, VCCI

3.3V Power Supply Range (V

CCI

)

5.0V Power Supply Range (V

CCI

)

0 to +70 –40 to +85 °C

2.3-2.7 2.3-2.7 V

)

3.0-3.6 3.0-3.6 V

4.75-5.25 4.5-5.5 V

Note:

1. Ambient temperature (TA). to absolute maximum rated conditions for extended periods may affect device reliability. Devices should not be operated

outside the Recommended Operating Conditions.

Typical eX Standby Current at 25°C

Product

CCA CCI

= 2.5V

CCA =

CCI

= 3.3V

eX64 397µA 497µA eX128 696µA 795µA eX256 698µA 796µA

2.5V

2.5V Electrical Specifications

Commercial Industrial

Symbol

1,2

tR, t

3,4

Parameter Min. Max. Min. Max. Units

= MIN, VI = V

= MIN,VI = V

Input Low Voltage, V Input High Voltage, V 3-St ate Ou tput Le akage C ur rent, V Input Transition Time tR, t

IH IH IH IH IH

or V or V or V or V or V

or V

OUT

IL IL IL IL IL

≤ V

VOL(max)

≥ V

VOH(min)

OUT

= -100 µA) 2.1 2.1 V

= -1 mA) 2.0 2.0 V

= -2 mA) 1.7 1.7 V

(IOL= 100µA) 0.2 0.2 V (IOL= 1mA) 0.4 0.4 V (IOL= 2 mA) 0.7 0.7 V

-0.3 0.7 -0.3 0.7 V

1.7 V

= V

or GND –10 10 –10 10 µA

CCI

I/O Capacitance 10 10 pF Standby Current 1.0 3.0 mA

IV Curve5Can be derived from the IBIS model at www.actel.com/custsup/models/ibis.html.

Notes:

1. tR is the transition time from 0.7 V to 1.7V.

2. tF is the transition time from 1.7V to 0.7V.

3. ICC max Commercial –F = 5.0mA

4. ICC=I

CCI

+ I

CCA

+ 0.3 1.7 V

+ 0.3 V

10 10 ns

8v3.0

eX Family FPGAs

3.3V Electrical Specifications

Commercial Industrial

Symbol Parameter

= MIN, VI = V

IIL/ I I

tR, t C

3,4

= MIN, VI = V

Input Low Voltage 0.8 0.8 V Input High Voltage 2.0 2.0 V Input Leakage Current, VIN = V 3-State Output Leakage Current, V

1,2

Input Transition Time tR, t I/O Capacitance 10 10 pF Standby Current 1.5 10 mA

IH IH IH IH

or V or V or V or V

IL IL IL IL

or GND –10 10 –10 10 µA

CCI

= V

OUT

or GND –10 10 –10 10 µA

CCI

= -1mA) 0. 9 V

= -8mA) 2.4 2.4 V

(IOL= 1mA) 0.1 V (IOL= 12mA) 0.4 0.4 V

Min. Max. Min. Max. Units

CCI

IV Curve5Can be derived from the IBIS model at www.actel.com/custsup/models/ibis.html.

Notes:

1. tR is the transition time from 0.8 V to 2.0V.

2. tF is the transition time from 2.0V to 0.8V.

3. ICC max Commercial –F=5.0mA

4. ICC=I

CCI

+ I

CCA

5.0V Electrical Specifications

Commercial Industrial

0.9 V

CCI

0.1 V

CCI

10 10 ns

Symbol Parameter

= MIN, VI = V

IIL/ I I

tR, t C

3,4

= MIN, VI = V

Input Low Voltage 0.8 0.8 V Input High Voltage 2.0 2.0 V Input Leakage Current, VIN = V 3-State Output Leakage Current, V

1,2

Input Transition Time tR, t I/O Capacitance 10 10 pF Standby Current 15 20 mA

IH IH IH IH

or V or V or V or V

IL IL IL IL

or GND –10 10 –10 10 µA

CCI

= V

OUT

or GND –10 10 –10 10 µA

CCI

= -1mA) 0. 9 V

= -8mA) 2.4 2.4 V

(IOL= 1mA) 0.1 V (IOL= 12mA) 0.4 0.4 V

Min. Max. Min. Max. Units

CCI

IV Curve5Can be derived from the IBIS model at www.actel.com/custsup/models/ibis.html

Notes:

1. tR is the transition time from 0.8 V to 2.0V.

2. tF is the transition time from 2.0V to 0.8V.

3. ICC max Commercial –F=20mA

4. ICC=I

CCI

+ I

CCA

0.9 V

CCI

0.1 V

CCI

10 10 ns

v3.0 9

eX Dynamic Power Consumption – High Frequency

300 250 200 150 100

Power (mW)

50 100 150 200

Frequency (MHz)

Notes:

1. Device filled with 16-bit counters.

2. V

CCA

, V

= 2.7V, device tested at room temperature.

CCI

eX Dynamic Power Consumption – Low Frequency

eX Family FPGAs

eX 64 eX 128 eX 256

Notes:

1. Device filled with 16-bit counters.

2. V

CCA

, V

= 2.7V, device tested at room temperature.

CCI

80 70 60 50 40 30

Power (mW)

20 10

0 1020304050

Frequency (MH z)

eX64 eX128 eX256

10 v3.0

eX Family FPGAs

Total Dynamic Power (mW)

180

160

140

120

100

Total Dynamic Power (mW)

0 25 50 75 100 125 150 175 200

Freque nc y (MHz)

System Power at 5%, 10%, and 15% Duty Cycle

12,000

10,000

32-bit Dec ode r 8 x 8-bi t Count e rs SDRAM Controller

8,000

6,000

4,000

System Power (uW)

2,000

5% DC 10% DC 15% DC

0 102030405060

Freque ncy ( M Hz)

v3.0 11

Junction Temperature (TJ)

The temperature variable in the Designer Series software refers to the junction temperature, not the ambient temperature. This is an important distinction because the heat generated from dynamic power consumption is usually hotter than the ambient temperature. Equation 1, shown below, can be used to calculate junction temperature.

Junction Temperature =

∆T + T

(1)

Where:

= Ambient Temperature

∆T = Temperature gradient between junction (silicon) and

ambient

∆T = θ

* P

P = Power

eX Family FPGAs

= Junction to ambient of package. θja numbers are

located in the Package Thermal Characteristics section below.

Package Thermal Characteristics

The device junction to case thermal characteristic is θjc,

and the junction to ambient air characteristic is thermal characteristics for

are shown with two different

. The

air flow rates.

The maximum junction temperature is 150

°C.

A sample calculation of the absolute maximum power dissipation allowed for a TQFP 100-pin package at commercial temperature and still air is as follows:

Max. junction temp. (°C) Max. ambient temp. (°C)–

Maximum Power Allowed

Package Type Pin Count θ

Thin Quad Flat Pack (TQFP) 64 14 51.2 35 °C/W Thin Quad Flat Pack (TQFP) 100 12 37.5 30 °C/W Chip Scale Package (CSP) 49 3 71.3 56.0 °C/W Chip Scale Package (CSP) 128 3 54.1 47.8 °C/W Chip Scale Package (CSP) 180 3 57.8 51 °C/W

---------------------------------------------------------------------------------------------------------------------------------

(° C/W)

150° C70°C–

-----------------------------------

37.5°C/W

Still Air

2.1W===

300 ft/min Units

12 v3.0

+ 25 hidden pages

ACTEL eX64, eX128, eX256 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual