ACTEL 40MX, 42MX User Manual

v6.0

40MX and 42MX FPGA Families

Features

High Capacity

•Single-Chip ASIC Alternative

•3,000 to 54,000 System Gates

•Up to 2.5 kbits Configurable Dual-Port SRAM

•Fast Wide-Decode Circuitry

•Up to 202 User-Programmable I/O Pins

High Performance

•5.6 ns Clock-to-Out

•250 MHz Performance

•5 ns Dual-Port SRAM Access

•100 MHz FIFOs

•7.5 ns 35-Bit Address Decode

HiRel Features

•Commercial, Industrial, Automotive, and Military Temperature Plastic Packages

•Commercial, Military Temperature, and MIL-STD-883 Ceramic Packages

•QML Certification

•Ceramic Devices Available to DSCC SMD

Ease of Integration

•Mixed-Voltage Operation (5.0V or 3.3V for core and I/Os), with PCI-Compliant I/Os

•Up to 100% Resource Utilization and 100% Pin Locking

•Deterministic, User-Controllable Timing

•Unique In-System Diagnostic and Verification Capability with Silicon Explorer II

•Low Power Consumption

•IEEE Standard 1149.1 (JTAG) Boundary Scan Testing

Product Profile

Device	A40MX02	A40MX04	A42MX09	A42MX16	A42MX24	A42MX36
Capacity
System Gates	3,000	6,000	14,000	24,000	36,000	54,000
SRAM Bits	–	–	–	–	–	2,560
Logic Modules
Sequential	–	–	348	624	954	1,230
Combinatorial	295	547	336	608	912	1,184
Decode	–	–	–	–	24	24
Clock-to-Out	9.5 ns	9.5 ns	5.6 ns	6.1 ns	6.1 ns	6.3 ns
SRAM Modules
(64x4 or 32x8)	–	–	–	–	–	10
Dedicated Flip-Flops	–	–	348	624	954	1,230
Maximum Flip-Flops	147	273	516	928	1,410	1,822
Clocks	1	1	2	2	2	6
User I/O (maximum)	57	69	104	140	176	202
PCI	–	–	–	–	Yes	Yes
Boundary Scan Test (BST)	–	–	–	–	Yes	Yes
Packages (by pin count)
PLCC	44, 68	44, 68, 84	84	84	84	–
PQFP	100	100	100, 160	100, 160, 208	160, 208	208, 240
VQFP	80	80	100	100	–	–
TQFP	–	–	176	176	176	–
CQFP	–	–	–	–	–	208, 256
PBGA	–	–	–	–	–	272

January 2004	i
© 2004 Actel Corporation	See the Actel website (www.actel.com) for the latest version of this datasheet.

40MX and 42MX FPGA Families

Ordering Information

A42MX16 _ 1

PQ

100

ES

Application (Temperature Range)

Blank =

Commercial (0 to +70˚C)

I

=

Industrial (–40 to +85˚C)

M

=

Military (–55 to +125˚C)

B

=

MIL-STD-883

A

=

Automotive (–40 to +125˚C)

Package Lead Count

Package Type

PL

=

Plastic Leaded Chip Carrier

PQ

=

Plastic Quad Flat Pack

TQ

=

Thin (1.4 mm) Quad Flat Pack

VQ

=

Very Thin (1.0 mm) Quad Flat Pack

BG

=

Plastic Ball Grid Array

CQ

=

Ceramic Quad Flat Pack

Speed Grade

Blank =

Standard Speed

–1

=

Approximately 15% Faster than Standard

–2

=

Approximately 25% Faster than Standard

–3

=

Approximately 35% Faster than Standard

–F

=

Approximately 40% Slower than Standard

Part Number

A40MX02

=

3,000 System Gates

A40MX04

=

6,000 System Gates

A42MX09

=

14,000 System Gates

A42MX16

=

24,000 System Gates

A42MX24

=

36,000 System Gates

A42MX36

=

54,000 System Gates

Plastic Device Resources

						User I/Os
	PLCC	PLCC	PLCC	PQFP	PQFP	PQFP	PQFP	VQFP	VQFP	TQFP	PBGA
Device	44-Pin	68-Pin	84-Pin	100-Pin	160-Pin	208-Pin	240-Pin	80-Pin	100-Pin	176-Pin	272-Pin
A40MX02	34	57	–	57	–	–	–	57	–	–	–
A40MX04	34	57	69	69	–	–	–	69	–	–	–
A42MX09	–	–	72	83	101	–	–	–	83	104	–
A42MX16	–	–	72	83	125	140	–	–	83	140	–
A42MX24	–	–	72	–	125	176	–	–	–	150	–
A42MX36	–	–	–	–	–	176	202	–	–	–	202

Note: Package Definitions

PLCC = Plastic Leaded Chip Carrier, PQFP = Plastic Quad Flat Pack, TQFP = Thin Quad Flat Pack, VQFP = Very Thin Quad Flat Pack, PBGA = Plastic Ball Grid Array

ii

v6.0

40MX and 42MX FPGA Families

Ceramic Device Resources

	User I/Os
Device	CQFP 208-Pin	CQFP 256-Pin
A42MX36	176	202

Note: Package Definitions CQFP = Ceramic Quad Flat Pack

Temperature Grade Offerings

Package	A40MX02	A40MX04	A42MX09	A42MX16	A42MX24	A42MX36
PLCC 44	C, I, M	C, I, M
PLCC 68	C, I, A, M	C, I, M
PLCC 84		C, I, A, M	C, I, A, M	C, I, M	C, I, M
PQFP 100	C, I, A, M	C, I, A, M	C, I, A, M	C, I, M
PQFP 160			C, I, A, M	C, I, M	C, I, A, M
PQFP 208				C, I, A, M	C, I, A, M	C, I, A, M
PQFP 240						C, I, A, M
VQFP 80	C, I, A, M	C, I, A, M
VQFP 100			C, I, A, M	C, I, A, M
TQFP 176			C, I, A, M	C, I, A, M	C, I, A, M
PBGA 272						C, I, M
CQFP 208						C, M, B
CQFP 256						C, M, B
Note:

C = Commercial

I = Industrial

A = Automotive

M = Military

B = MIL-STD-883 Class B

Speed Grade Offerings

	– F	Std	–1	–2	–3
C
I
A
M
B

Note: Refer to the 40MX and 42MX Automotive Family FPGAs datasheet for details on automotive-grade MX offerings.

Contact your local Actel representative for device availability.

v6.0

iii

40MX and 42MX FPGA Families

Table of Contents

40MX and 42MX FPGA Families

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 MX Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Other Architectural Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 Development Tool Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13 Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13 5.0V Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14 5V TTL Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15 3.3V Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16 3.3V LVTTL Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17 Mixed 5.0V/3.3V Operating Conditions (for 42MX Devices Only) . . . . . . . . . . . . . 1-18 Mixed 5.0V/3.3V Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18 Output Drive Characteristics for 5.0V PCI Signaling . . . . . . . . . . . . . . . . . . . . . . . . 1-19 Output Drive Characteristics for 3.3V PCI Signaling . . . . . . . . . . . . . . . . . . . . . . . . 1-20 Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22 Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22 Timing Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-23 Parameter Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-25 Sequential Module Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-26 Sequential Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-27 Decode Module Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-28 SRAM Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-28 Dual-Port SRAM Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-28 Predictable Performance: Tight Delay Distributions . . . . . . . . . . . . . . . . . . . . . . . 1-30 Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-30 Temperature and Voltage Derating Factors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-31 PCI System Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-35 PCI Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-35 Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-36 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-77

Package Pin Assignments

44-Pin PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

68-Pin PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

84-Pin PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

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v

40MX and 42MX FPGA Families

Table of Contents

100-Pin PQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

160-Pin PQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

208-Pin PQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13

240-Pin PQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17

80-Pin VQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20

100-Pin VQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22

176-Pin TQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24

208-Pin CQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28

256-Pin CQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31

272-Pin BGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-34

Datasheet Information

List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2

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v6.0

40MX and 42MX FPGA Families

40MX and 42MX FPGA Families

General Description

Actel's 40MX and 42MX families offer a cost-effective design solution at 5V. The MX devices are single-chip solutions and provide high performance while shortening the system design and development cycle. MX devices can integrate and consolidate logic implemented in multiple PALs, CPLDs, and FPGAs. Example applications include high-speed controllers and address decoding, peripheral bus interfaces, DSP, and coprocessor functions.

The MX device architecture is based on Actel’s patented antifuse technology implemented in a 0.45µm triplemetal CMOS process. With capacities ranging from 3,000 to 54,000 system gates, the MX devices provide performance up to 250 MHz, are live on power-up and have one-fifth the standby power consumption of comparable FPGAs. Actel’s MX FPGAs provide up to 202 user I/Os and are available in a wide variety of packages and speed grades.

Actel’s A42MX24 and A42MX36 devices also feature MultiPlex I/Os, which support mixed-voltage systems, enable programmable PCI, deliver high-performance operation at both 5.0V and 3.3V, and provide a lowpower mode. The devices are fully compliant with the PCI Local Bus Specification (version 2.1). They deliver 200 MHz on-chip operation and 6.1 ns clock-to-output performance.

The 42MX24 and 42MX36 devices include system-level features such as IEEE Standard 1149.1 (JTAG) Boundary Scan Testing and fast wide-decode modules. In addition, the A42MX36 device offers dual-port SRAM for implementing fast FIFOs, LIFOs, and temporary data storage. The storage elements can efficiently address applications requiring wide datapath manipulation and can perform transformation functions such as those required for telecommunications, networking, and DSP.

All MX devices are fully tested over automotive and military temperature ranges. In addition, the largest member of the family, the A42MX36, is available in both CQ208 and CQ256 ceramic packages screened to MIL- STD-883 levels. For easy prototyping and conversion from plastic to ceramic, the CQ208 and PQ208 devices are pincompatible.

MX Architectural Overview

The MX devices are composed of fine-grained building blocks that enable fast, efficient logic designs. All devices within these families are composed of logic modules, I/O modules, routing resources and clock networks, which are the building blocks for fast logic designs. In addition, the A42MX36 device contains embedded dual-port SRAM modules, which are optimized for high-speed datapath functions such as FIFOs, LIFOs and scratchpad memory. A42MX24 and A42MX36 also contain widedecode modules.

Logic Modules

The 40MX logic module is an eight-input, one-output logic circuit designed to implement a wide range of logic functions with efficient use of interconnect routing resources (Figure 1-1).

The logic module can implement the four basic logic functions (NAND, AND, OR and NOR) in gates of two, three, or four inputs. The logic module can also implement a variety of D-latches, exclusivity functions, AND-ORs and OR-ANDs. No dedicated hard-wired latches or flip-flops are required in the array; latches and flipflops can be constructed from logic modules whenever required in the application.

Figure 1-1 • 40MX Logic Module

v6.0

1-1

40MX and 42MX FPGA Families

The 42MX devices contain three types of logic modules: combinatorial (C-modules), sequential (S-modules) and decode (D-modules). Figure 1-2 illustrates the combinatorial logic module. The S-module, shown in Figure 1-3, implements the same combinatorial logic function as the C-module while adding a sequential element. The sequential element can be configured as either a D-flip-flop or a transparent latch. The S-module register can be bypassed so that it implements purely combinatorial logic.

A0

B0

S0

D00

D01 Y

D10

D11

S1

A1

B1

Figure 1-2 • 42MX C-Module Implementation

D00

D00

D01

D01

D10

Y

D

Q

OUT

D10

Y

D

Q

OUT

S0

S0

D11

CLR

D11

GATE

S1

S1

Up to 7-Input Function Plus D-Type Flip-Flop with Clear

Up to 7-Input Function Plus Latch

D0

D00

D01

Y

OUT

Y

D

Q

OUT

D10

S0

D1

GATE

D11

S

CLR

S1

Up to 4-Input Function Plus Latch with Clear	Up to 8-Input Function (Same as C-Module)

Figure 1-3 • 42MX S-Module Implementation

1-2

v6.0

40MX and 42MX FPGA Families

A42MX24 and A42MX36 devices contain D-modules, which are arranged around the periphery of the device. D-modules contain wide-decode circuitry, providing a fast, wide-input AND function similar to that found in CPLD architectures (Figure 1-4). The D-module allows A42MX24 and A42MX36 devices to perform widedecode functions at speeds comparable to CPLDs and PALs. The output of the D-module has a programmable inverter for active HIGH or LOW assertion. The D-module output is hardwired to an output pin, and can also be fed back into the array to be incorporated into other logic.

Dual-Port SRAM Modules

The A42MX36 device contains dual-port SRAM modules that have been optimized for synchronous or asynchronous applications. The SRAM modules are arranged in 256-bit blocks that can be configured as 32x8 or 64x4. SRAM modules can be cascaded together to form memory spaces of user-definable width and depth. A block diagram of the A42MX36 dual-port SRAM block is shown in Figure 1-5.

The A42MX36 SRAM modules are true dual-port structures containing independent read and write ports. Each SRAM module contains six bits of read and write addressing (RDAD[5:0] and WRAD[5:0], respectively) for 64x4-bit blocks. When configured in byte mode, the

highest order address bits (RDAD5 and WRAD5) are not used. The read and write ports of the SRAM block contain independent clocks (RCLK and WCLK) with programmable polarities offering active HIGH or LOW implementation. The SRAM block contains eight data inputs (WD[7:0]), and eight outputs (RD[7:0]), which are connected to segmented vertical routing tracks.

The A42MX36 dual-port SRAM blocks provide an optimal solution for high-speed buffered applications requiring FIFO and LIFO queues. The ACTgen Macro Builder within Actel's Designer software provides capability to quickly design memory functions with the SRAM blocks. Unused SRAM blocks can be used to implement registers for other user logic within the design.

7 Inputs

Hard-Wire to I/O

Programmable

Inverter

Feedback to Array

Figure 1-4 • A42MX24 and A42MX36 D-Module

Implementation

WD[7:0] Latches

[7:0]

		Write	SRAM Module	[5:0]	Latches	RDAD[5:0]
				Read
		Port	32 x 8 or 64 x 4	Port
WRAD[5:0]	[5:0]	Logic	(256 Bits)	Logic
					Read
	Latches
						REN
					Logic
MODE	Write		RD[7:0]			RCLK
BLKEN
WEN	Logic
WCLK			Routing Tracks

Figure 1-5 • A42MX36 Dual-Port SRAM Block

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1-3

40MX and 42MX FPGA Families

Routing Structure

The MX architecture uses vertical and horizontal routing tracks to interconnect the various logic and I/O modules. These routing tracks are metal interconnects that may be continuous or split into segments. Varying segment lengths allow the interconnect of over 90% of design tracks to occur with only two antifuse connections. Segments can be joined together at the ends using antifuses to increase their lengths up to the full length of the track. All interconnects can be accomplished with a maximum of four antifuses.

Horizontal Routing

Horizontal routing tracks span the whole row length or are divided into multiple segments and are located in between the rows of modules. Any segment that spans more than one-third of the row length is considered a long horizontal segment. A typical channel is shown in Figure 1-6. Within horizontal routing, dedicated routing tracks are used for global clock networks and for power and ground tie-off tracks. Non-dedicated tracks are used for signal nets.

Vertical Routing

Another set of routing tracks run vertically through the module. There are three types of vertical tracks: input, output, and long. Long tracks span the column length of the module, and can be divided into multiple segments. Each segment in an input track is dedicated to the input of a particular module; each segment in an output track is dedicated to the output of a particular module. Long segments are uncommitted and can be assigned during routing. Each output segment spans four channels (two above and two below), except near the top and bottom of the array, where edge effects occur. Long vertical tracks contain either one or two segments. An example of vertical routing tracks and segments is shown in Figure 1-6.

Antifuse Structures

An antifuse is a "normally open" structure. The use of antifuses to implement a programmable logic device results in highly testable structures as well as efficient programming algorithms. There are no pre-existing connections; temporary connections can be made using pass transistors. These temporary connections can isolate individual antifuses to be programmed and individual circuit structures to be tested, which can be done before and after programming. For instance, all metal tracks can be tested for continuity and shorts between adjacent tracks, and the functionality of all logic modules can be verified.

	Segmented
	Horizontal	Logic
	Routing
		Modules
		Antifuses

Vertical Routing Tracks

Figure 1-6 • MX Routing Structure

Clock Networks

The 40MX devices have one global clock distribution network (CLK). A signal can be put on the CLK network by being routed through the CLKBUF buffer.

In 42MX devices, there are two low-skew, high-fanout clock distribution networks, referred to as CLKA and CLKB. Each network has a clock module (CLKMOD) that can select the source of the clock signal from any of the following (Figure 1-7 on page 1-5):

•Externally from the CLKA pad, using CLKBUF buffer

•Externally from the CLKB pad, using CLKBUF buffer

•Internally from the CLKINTA input, using CLKINT buffer

•Internally from the CLKINTB input, using CLKINT buffer

The clock modules are located in the top row of I/O modules. Clock drivers and a dedicated horizontal clock track are located in each horizontal routing channel.

Clock input pads in both 40MX and 42MX devices can also be used as normal I/Os, bypassing the clock networks.

The A42MX36 device has four additional register control resources, called quadrant clock networks (Figure 1-8 on page 1-5). Each quadrant clock provides a local, highfanout resource to the contiguous logic modules within its quadrant of the device. Quadrant clock signals can originate from specific I/O pins or from the internal array and can be used as a secondary register clock, register clear, or output enable.

1-4

v6.0

40MX and 42MX FPGA Families

CLKB

CLKINB

CLKA

CLKINA

From

S0

Pads

CLKMOD

Internal

S1

Signal

CLKO(17)

Clock

CLKO(16)

Drivers

CLKO(15)

CLKO(2)

CLKO(1)

Clock Tracks

Figure 1-7 • Clock Networks of 42MX Devices

QCLKA

QCLKC

Quad

Quad

QCLKB

Clock

QCLK1

QCLK3

Clock

QCLKD

*QCLK1IN

Modul

Modul

*QCLK3IN

S0

S1

S1

S0

Quad

Quad

Clock

QCLK2

QCLK4

Clock

*QCLK2IN

Modul

Modul

*QCLK4IN

S0

S1

S1

S0

Note: *QCLK1IN, QCLK2IN, QCLK3IN, and QCLK4IN are internally-generated signals.

Figure 1-8 • Quadrant Clock Network of A42MX36 Devices

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1-5

40MX and 42MX FPGA Families

MultiPlex I/O Modules

42MX devices feature Multiplex I/Os and support 5.0V, 3.3V, and mixed 3.3V/5.0V operations.

The MultiPlex I/O modules provide the interface between the device pins and the logic array. Figure 1-9 is a block diagram of the 42MX I/O module. A variety of user functions, determined by a library macro selection, can be implemented in the module. (Refer to the Antifuse Macro Library Guide for more information.) All 42MX I/O modules contain tristate buffers, with input and output latches that can be configured for input, output, or bidirectional operation.

All 42MX devices contain flexible I/O structures, where each output pin has a dedicated output-enable control (Figure 1-9). The I/O module can be used to latch input or output data, or both, providing fast set-up time. In addition, the Actel Designer software tools can build a D- type flip-flop using a C-module combined with an I/O module to register input and output signals. Refer to the

Antifuse Macro Library Guide for more details.

A42MX24 and A42MX36 devices also offer selectable PCI output drives, enabling 100% compliance with version 2.1 of the PCI specification. For low-power systems, all inputs and outputs are turned off to reduce current consumption to below 500µA.

To achieve 5.0V or 3.3V PCI-compliant output drives on A42MX24 and A42MX36 devices, a chip-wide PCI fuse is programmed via the Device Selection Wizard in the Designer software (Figure 1-10). When the PCI fuse is not programmed, the output drive is standard.

Actel's Designer software development tools provide a design library of I/O macro functions that can implement all I/O configurations supported by the MX FPGAs.

		EN
	Q	D
From Array		PAD
	G/CLK*
To Array	Q	D
	G/CLK*

Note: *Can be configured as a Latch or D Flip-Flop (Using C-Module)

Figure 1-9 • 42MX I/O Module

STD

Signal

Output

PCI

Drive

PCI Enable

Fuse

Figure 1-10 • PCI Output Structure of A42MX24 and

A42MX36 Devices

Other Architectural Features

Performance

MX devices can operate with internal clock frequencies of 250 MHz, enabling fast execution of complex logic functions. MX devices are live on power-up and do not require auxiliary configuration devices and thus are an optimal platform to integrate the functionality contained in multiple programmable logic devices. In addition, designs that previously would have required a gate array to meet performance can be integrated into an MX device with improvements in cost and time-to- market. Using timing-driven place-and-route (TDPR) tools, designers can achieve highly deterministic device performance.

User Security

The Actel FuseLock provides robust security against design theft. Special security fuses are hidden in the fabric of the device and prevent unauthorized users from accessing the programming and/or probe interfaces. It is virtually impossible to identify or bypass these fuses without damaging the device, making Actel antifuse FPGAs immune to both invasive and noninvasive attacks.

Special security fuses in 40MX devices include the Probe Fuse and Program Fuse. The former disables the probing circuitry while the latter prohibits further programming of all fuses, including the Probe Fuse. In 42MX devices, there is the Security Fuse which, when programmed, both disables the probing circuitry and prohibits further programming of the device.

Look for this symbol to ensure your valuable IP is secure.

For more information, refer to Actel's Implementation of Security in Actel Antifuse FPGAs application note.

1-6

v6.0

40MX and 42MX FPGA Families

nonprogrammed), Silicon Sculptor II also allows self-test ™ to verify its own hardware extensively.

The procedure for programming an MX device using Silicon Sculptor II is as follows:

ue

Figure 1-11 • Fuselock

Programming

Device programming is supported through the Silicon Sculptor series of programmers. Silicon Sculptor II is a compact, robust, single-site and multi-site device programmer for the PC. With standalone software, Silicon Sculptor II is designed to allow concurrent programming of multiple units from the same PC.

Silicon Sculptor II programs devices independently to achieve the fastest programming times possible. After being programmed, each fuse is verified to insure that it has been programmed correctly. Furthermore, at the end of programming, there are integrity tests that are run to ensure no extra fuses have been programmed. Not only

does it	test fuses (both programmed and
Table 1 •	Voltage Support of MX Devices

1.Load the .AFM file

2.Select the device to be programmed

3.Begin programming

When the design is ready to go to production, Actel offers device volume-programming services either through distribution partners or via In-House Programming from the factory.

For more details on programming MX devices, please refer to the Programming Antifuse Devices and the Silicon Sculptor II user's guides.

Power Supply

MX devices are designed to operate in both 5.0V and 3.3V environments. In particular, 42MX devices can operate in mixed 5.0V/3.3V systems. Table 1 describes the voltage support of MX devices.

Device	VCC	VCCA	VCCI	Maximum Input Tolerance	Nominal Output Voltage
40MX	5.0V	–	–	5.5V	5.0V
	3.3V	–	–	3.6V	3.3V
42MX	–	5.0V	5.0V	5.5V	5.0V
	–	3.3V	3.3V	3.6V	3.3V
	–	5.0V	3.3V	5.5V	3.3V

Power-Up/Down in Mixed-Voltage Mode

When powering up 42MX in mixed voltage mode

(VCCA = 5.0V and VCCI = 3.3V), VCCA must be greater than or equal to VCCI throughout the power-up sequence. If

VCCI exceeds VCCA during power up, either the I/Os' input protection junction on the I/Os will be forward-biased or the I/Os will be at logical HIGH, and ICC rises to high levels. For power-down, any sequence with VCCA and VCCI can be implemented.

Low Power Mode

42MX devices have been designed with a Low Power Mode. This feature, activated with setting the special LP pin to HIGH for a period longer than 800 ns, is particularly useful for battery-operated systems where battery life is a primary concern. In this mode, the core of the device is turned off and the device consumes minimal power with low standby current. In addition, all input buffers are turned off, and all outputs and bidirectional buffers are tristated. Since the core of the device is turned off, the states of the registers are lost. The device must be re-initialized when exiting Low Power Mode. I/ Os can be driven during LP mode, and clock pins should be driven HIGH or LOW and should not float to avoid drawing current. To exit LP mode, the LP pin must be pulled LOW for over 200 µs to allow for charge pumps to power up, and device initialization will begin.

v6.0

1-7

40MX and 42MX FPGA Families

Power Dissipation

The general power consumption of MX devices is made up of static and dynamic power and can be expressed with the following equation:

General Power Equation

P = [ICCstandby + ICCactive] * VCCI + IOL* VOL* N

+ IOH * (VCCI – VOH) * M

where:

ICCstandby is the current flowing when no inputs or outputs are changing.

ICCactive is the current flowing due to CMOS switching.

IOL, IOH are TTL sink/source currents. VOL, VOH are TTL level output voltages.

N equals the number of outputs driving TTL loads to VOL.

M equals the number of outputs driving TTL loads to VOH.

Accurate values for N and M are difficult to determine because they depend on the family type, on design details, and on the system I/O. The power can be divided into two components: static and active.

Static Power Component

The static power due to standby current is typically a small component of the overall power consumption. Standby power is calculated for commercial, worst-case conditions. The static power dissipation by TTL loads depends on the number of outputs driving, and on the DC load current. For instance, a 32-bit bus sinking 4mA at 0.33V will generate 42mW with all outputs driving LOW, and 140mW with all outputs driving HIGH. The actual dissipation will average somewhere in between, as I/Os switch states with time.

Active Power Component

Power dissipation in CMOS devices is usually dominated by the dynamic power dissipation. Dynamic power consumption is frequency-dependent and is a function of the logic and the external I/O. Active power dissipation results from charging internal chip capacitances of the interconnect, unprogrammed antifuses, module inputs, and module outputs, plus external capacitances due to PC board traces and load device inputs. An additional component of the active power dissipation is the totem pole current in the CMOS transistor pairs. The net effect can be associated with an equivalent capacitance that can be combined with frequency and voltage to represent active power dissipation.

The power dissipated by a CMOS circuit can be expressed by the equation:

Power (µW) = CEQ * VCCA2 * F(1)

where:

CEQ =Equivalent capacitance expressed in picofarads (pF) VCCA =Power supply in volts (V)

F =Switching frequency in megahertz (MHz)

Equivalent Capacitance

Equivalent capacitance is calculated by measuring ICCactive at a specified frequency and voltage for each circuit component of interest. Measurements have been made over a range of frequencies at a fixed value of VCC. Equivalent capacitance is frequency-independent, so the results can be used over a wide range of operating conditions. Equivalent capacitance values are shown below.

CEQ Values for Actel MX FPGAs

Modules (CEQM)3.5 Input Buffers (CEQI)6.9

Output Buffers (CEQO)18.2

Routed Array Clock Buffer Loads (CEQCR)1.4

To calculate the active power dissipated from the complete design, the switching frequency of each part of the logic must be known. The equation below shows a piece-wise linear summation over all components.

Power = VCCA2 * [(m x CEQM * fm)Modules + (n * CEQI * fn)Inputs + (p * (CEQO + CL) *

fp)outputs +

0.5 * (q1 * CEQCR * fq1)routed_Clk1 + (r1 *

fq1)routed_Clk1 +

0.5 * (q2 * CEQCR * fq2)routed_Clk2 + (r2 * fq2)routed_Clk2 (2)

where:

m= Number of logic modules switching at frequency fm

n= Number of input buffers switching at frequency fn

p= Number of output buffers switching at frequency fp

q1	= Number of clock loads on the first routed array
		clock
q2	=	Number of clock loads on the second routed
		array clock
r1	=	Fixed capacitance due to first routed array
		clock
r2	=	Fixed capacitance due to second routed array
		clock

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v6.0

CEQM =		Equivalent capacitance of logic modules in pF
CEQI	=	Equivalent capacitance of input buffers in pF
CEQO =		Equivalent capacitance of output buffers in pF
CEQCR =		Equivalent capacitance of routed array clock in
		pF
CL	=	Output load capacitance in pF
fm	=	Average logic module switching rate in MHz
fn	=	Average input buffer switching rate in MHz
fp	=	Average output buffer switching rate in MHz
fq1	=	Average first routed array clock rate in MHz
fq2	=	Average second routed array clock rate in MHz
Fixed Capacitance Values for MX FPGAs (pF)
			r1	r2
Device Type			routed_Clk1	routed_Clk2
A40MX02			41.4	N/A
A40MX04			68.6	N/A
A42MX09			118	118
A42MX16			165	165
A42MX24			185	185
A42MX36			220	220

Test Circuitry and Silicon Explorer II Probe

MX devices contain probing circuitry that provides builtin access to every node in a design, via the use of Silicon Explorer II. Silicon Explorer II is an integrated hardware and software solution that, in conjunction with the Designer software, allow users to examine any of the internal nets of the device while it is operating in a prototyping or a production system. The user can probe into an MX device without changing the placement and routing of the design and without using any additional

40MX and 42MX FPGA Families

resources. Silicon Explorer II's noninvasive method does not alter timing or loading effects, thus shortening the debug cycle and providing a true representation of the device under actual functional situations.

Silicon Explorer II samples data at 100 MHz (asynchronous) or 66 MHz (synchronous). Silicon Explorer II attaches to a PC's standard COM port, turning the PC into a fully functional 18-channel logic analyzer. Silicon Explorer II allows designers to complete the design verification process at their desks and reduces verification time from several hours per cycle to a few seconds.

Silicon Explorer II is used to control the MODE, DCLK, SDI and SDO pins in MX devices to select the desired nets for debugging. The user simply assigns the selected internal nets in the Silicon Explorer II software to the PRA/PRB output pins for observation. Probing functionality is activated when the MODE pin is held HIGH.

Figure 1-12 illustrates the interconnection between Silicon Explorer II and 40MX devices, while Figure 1-13 on page 1-10 illustrates the interconnection between Silicon Explorer II and 42MX devices

To allow for probing capabilities, the security fuses must not be programmed. (Refer to <zBlue>“User Security” section on page 6 for the security fuses of 40MX and 42MX devices). Table 2 on page 1-10 summarizes the possible device configurations for probing.

PRA and PRB pins are dual-purpose pins. When the "Reserve Probe Pin" is checked in the Designer software, PRA and PRB pins are reserved as dedicated outputs for probing. If PRA and PRB pins are required as user I/Os to achieve successful layout and "Reserve Probe Pin" is checked, the layout tool will override the option and place user I/Os on PRA and PRB pins.

16 Logic Analyzer Channels

Serial Connection

MODE

40MX

to Windows PC

Silicon

SDI

Explorer II

DCLK

SDO

PRA

PRB

Figure 1-12 • Silicon Explorer II Setup with 40MX

v6.0

1-9

40MX and 42MX FPGA Families

	16 Logic Analyzer Channels
	Serial Connection	42MX
		MODE
	to Windows PC
	Silicon	SDI
	Explorer II	DCLK
		SDO

PRA

PRB

Figure 1-13 • Silicon Explorer II Setup with 42MX

Table 2 •	Device Configuration Options for Probe Capability
Security Fuse(s)				PRA, PRB1	SDI, SDO, DCLK1
Programmed		MODE
No		LOW		User I/Os2	User I/Os2
No		HIGH		Probe Circuit Outputs	Probe Circuit Inputs
Yes		–		Probe Circuit Secured	Probe Circuit Secured
Notes:

1.Avoid using SDI, SDO, DCLK, PRA and PRB pins as input or bidirectional ports. Since these pins are active during probing, input signals will not pass through these pins and may cause contention.

2.If no user signal is assigned to these pins, they will behave as unused I/Os in this mode. See the <zBlue>“Pin Descriptions” section on page 77 for information on unused I/O pins.

Design Consideration

It is recommended to use a series 70Ω termination resistor on every probe connector (SDI, SDO, MODE, DCLK, PRA and PRB). The 70Ω series termination is used to prevent data transmission corruption during probing and reading back the checksum.

IEEE Standard 1149.1 Boundary Scan Test

(BST) Circuitry

42MX24 and 42MX36 devices are compatible with IEEE Standard 1149.1 (informally known as Joint Testing Action Group Standard or JTAG), which defines a set of hardware architecture and mechanisms for cost-effective board-level testing. The basic MX boundary-scan logic circuit is composed of the TAP (test access port), TAP controller, test data registers and instruction register (Figure 1-14 on page 1-11). This circuit supports all mandatory IEEE 1149.1 instructions (EXTEST, SAMPLE/ PRELOAD and BYPASS) and some optional instructions. Table 3 on page 1-11 describes the ports that control JTAG testing, while Table 4 on page 1-11 describes the test instructions supported by these MX devices.

Each test section is accessed through the TAP, which has four associated pins: TCK (test clock input), TDI and TDO (test data input and output), and TMS (test mode selector).

The TAP controller is a four-bit state machine. The '1's and '0's represent the values that must be present at TMS at a rising edge of TCK for the given state transition to occur. IR and DR indicate that the instruction register or the data register is operating in that state.

The TAP controller receives two control inputs (TMS and TCK) and generates control and clock signals for the rest of the test logic architecture. On power-up, the TAP controller enters the Test-Logic-Reset state. To guarantee a reset of the controller from any of the possible states, TMS must remain high for five TCK cycles.

42MX24 and 42MX36 devices support three types of test data registers: bypass, device identification, and boundary scan. The bypass register is selected when no other register needs to be accessed in a device. This speeds up test data transfer to other devices in a test data path. The 32-bit device identification register is a shift register with four fields (lowest significant byte (LSB), ID number, part number and version). The boundary-scan register observes and controls the state of each I/O pin.

1-10

v6.0

Each I/O cell has three boundary-scan register cells, each with a serial-in, serial-out, parallel-in, and parallel-out pin. The serial pins are used to serially connect all the boundary-scan register cells in a device into a boundaryscan register chain, which starts at the TDI pin and ends

40MX and 42MX FPGA Families

at the TDO pin. The parallel ports are connected to the internal core logic tile and the input, output and control ports of an I/O buffer to capture and load data into the register to control or observe the logic state of each I/O.

Boundary Scan Register

Output

TDO

MUX

Bypass

JTAG

Control Logic

Register

TMS

TAP Controller

Instruction

TCK

Decode

JTAG

Instruction

TDI

Register

Figure 1-14 • 42MX IEEE 1149.1 Boundary Scan Circuitry

Table 3 •

Test Access Port Descriptions

Port

Description

TMS

(Test

Mode

Serial input for the test logic control bits. Data is captured on the rising edge of the test logic clock (TCK).

Select)

TCK (Test Clock Input)

Dedicated test logic clock used serially to shift test instruction, test data, and control inputs on the rising edge

of the clock, and serially to shift the output data on the falling edge of the clock. The maximum clock frequency

for TCK is 20 MHz.

TDI (Test Data Input)

Serial input for instruction and test data. Data is captured on the rising edge of the test logic clock.

TDO

(Test

Data

Serial output for test instruction and data from the test logic. TDO is set to an Inactive Drive state (high

Output)

impedance) when data scanning is not in progress.

Table 4 •

Supported BST Public Instructions

Instruction

IR Code (IR2.IR0)

Instruction Type

Description

EXTEST

000

Mandatory

Allows the external circuitry and board-level interconnections to

be tested by forcing a test pattern at the output pins and

capturing test results at the input pins.

SAMPLE/PRELOAD

001

Mandatory

Allows a snapshot of the signals at the device pins to be

captured and examined during operation

HIGH Z

101

Optional

Tristates all I/Os to allow external signals to drive pins. Please

refer to the IEEE Standard 1149.1 specification.

CLAMP

110

Optional

Allows state of signals driven from component pins to be

determined from the Boundary-Scan Register. Please refer to

the IEEE Standard 1149.1 specification for details.

BYPASS

111

Mandatory

Enables the bypass register between the TDI and TDO pins. The

test data passes through the selected device to adjacent devices

in the test chain.

v6.0

1-11

40MX and 42MX FPGA Families

JTAG Mode Activation

The JTAG test logic circuit is activated in the Designer software by selecting Tools -> Device Selection. This brings up the Device Selection dialog box as shown in Figure 1-15. The JTAG test logic circuit can be enabled by clicking the "Reserve JTAG Pins" check box. Table 5 explains the pins' behavior in either mode.

		Figure 1-15 • Device Selection Wizard
Table 5 •	Boundary Scan Pin Configuration and Functionality
Reserve JTAG		Checked		Unchecked
TCK		BST input; must be terminated to logical HIGH or LOW to avoid floating		User I/O
TDI, TMS		BST input; may float or be tied to HIGH		User I/O
TDO		BST output; may float or be connected to TDI of another device		User I/O

TRST Pin and TAP Controller Reset

An active reset (TRST) pin is not supported; however, MX devices contain power-on circuitry that resets the boundary scan circuitry upon power-up. Also, the TMS pin is equipped with an internal pull-up resistor. This allows the TAP controller to remain in or return to the Test-Logic-Reset state when there is no input or when a logical 1 is on the TMS pin. To reset the controller, TMS must be HIGH for at least five TCK cycles.

Boundary Scan Description Language

(BSDL) File

Conforming to the IEEE Standard 1149.1 requires that the operation of the various JTAG components be documented. The BSDL file provides the standard format to describe the JTAG components that can be used by automatic test equipment software. The file includes the instructions that are supported, instruction bit pattern, and the boundary-scan chain order. For an in-depth discussion on BSDL files, please refer to Actel BSDL Files Format Description application note.

Actel BSDL files are grouped into two categories - generic and device-specific. The generic files assign all user I/Os as inouts. Device-specific files assign user I/Os as inputs, outputs or inouts.

Generic files for MX devices are available on Actel's website at http://www.actel.com/techdocs/models/bsdl.html.

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v6.0

Development Tool Support

The MX family of FPGAs is fully supported by both Actel's Libero™ Integrated Design Environment and Designer FPGA Development software. Actel Libero IDE is a design management environment that streamlines the design flow. Libero IDE provides an integrated design manager that seamlessly integrates design tools while guiding the user through the design flow, managing all design and log files, and passing necessary design data among tools. Additionally, Libero IDE allows users to integrate both schematic and HDL synthesis into a single flow and verify the entire design in a single environment. Libero IDE includes Synplify® for Actel from Synplicity®, ViewDraw for Actel from Mentor Graphics, ModelSim™ HDL Simulator from Mentor Graphics®, WaveFormer Lite™ from SynaptiCAD™, and Designer software from Actel. Refer to the Libero IDE flow (located on Actel’s website) diagram for more information.

Actel's Designer software is a place-and-route tool and provides a comprehensive suite of backend support tools for FPGA development. The Designer software includes timing-driven place-and-route, and a world-class integrated static timing analyzer and constraints editor. With the Designer software, a user can lock his/her design pins before layout while minimally impacting the results of place-and-route. Additionally, the backannotation flow is compatible with all the major simulators and the simulation results can be cross-probed with Silicon Explorer II, Actel’s integrated verification and logic analysis tool. Another tool included in the Designer software is the ACTgen macro builder, which easily creates popular and commonly used logic functions for implementation into your schematic or HDL design. Actel's Designer software is compatible with the most popular FPGA design entry and verification tools from companies such as Mentor Graphics, Synplicity, Synopsys, and Cadence Design Systems. The Designer software is available for both the Windows and UNIX operating systems.

Actel's Designer software is compatible with the most popular FPGA design entry and verification tools from companies such as Mentor Graphics, Synplicity, Synopsys, and Cadence Design Systems. The Designer software is available for both the Windows and UNIX operating systems.

40MX and 42MX FPGA Families

Related Documents

Application Notes

Actel BSDL Files Format Description

www.actel.com/documents/BSDLformat_AN.pdf

Programming Antifuse Devices

http://www.actel.com/documents/

AntifuseProgram_AN.pdf

Actel's Implementation of Security in Actel Antifuse

FPGAs

www.actel.com/documents/Antifuse_Security_AN.pdf

User’s Guides and Manuals

Antifuse Macro Library Guide

www.actel.com/documents/libguide_UG.pdf

Silicon Sculptor II

www.actel.com/techdocs/manuals/default.asp#programmers

Miscellaneous

Libero IDE Flow Diagram

www.actel.com/products/tools/libero/flow.html

v6.0

1-13

40MX and 42MX FPGA Families

5.0V Operating Conditions

Table 6 •	Absolute Maximum Ratings for 40MX Devices*
Symbol		Parameter	Limits	Units
VCC		DC Supply Voltage	–0.5 to +7.0	V
VI		Input Voltage	–0.5 to VCC+0.5	V
VO		Output Voltage	–0.5 to VCC+0.5	V
tSTG		Storage Temperature	–65 to +150	°C

Note: *Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Devices should not be operated outside the Recommended Operating Conditions.

Table 7 •	Absolute Maximum Ratings for 42MX Devices*
Symbol		Parameter	Limits	Units
VCCI		DC Supply Voltage for I/Os	–0.5 to +7.0	V
VCCA		DC Supply Voltage for Array	–0.5 to +7.0	V
VI		Input Voltage	–0.5 to VCCI+0.5	V
VO		Output Voltage	–0.5 to VCCI+0.5	V
tSTG		Storage Temperature	–65 to +150	°C

Note: *Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Devices should not be operated outside the Recommended Operating Conditions.

Table 8 •	Recommended Operating Conditions
Parameter		Commercial		Industrial	Military	Units
Temperature Range*		0 to +70		-40 to +85	–55 to +125	°C
VCC (40MX)		4.75 to 5.25		4.5 to 5.5	4.5 to 5.5	V
VCCA (42MX)		4.75 to 5.25		4.5 to 5.5	4.5 to 5.5	V
VCCI (42MX)		4.75 to 5.25		4.5 to 5.5	4.5 to 5.5	V

Note: *Ambient temperature (TA) is used for commercial and industrial grades; case temperature (TC) is used for military grades.

1-14

v6.0

40MX and 42MX FPGA Families

5V TTL Electrical Specifications

Table 9 •	5V TTL Electrical Specifications
					Commercial		Commercial -F		Industrial		Military
Symbol		Parameter			Min.	Max.	Min.	Max.	Min.	Max.	Min.	Max.	Units
1		IOH = -10mA			2.4		2.4						V
VOH
		IOH = -4mA							3.7		3.7		V
V 1		I	OL	= 10mA		0.5		0.5					V
OL
			IOL = 6mA							0.4		0.4	V
VIL					-0.3	0.8	-0.3	0.8	-0.3	0.8	-0.3	0.8	V
VIH (40MX)					2.0	VCC+0.3	2.0	VCC+0.3	2.0	VCC+0.3	2.0	VCC+0.3	V
VIH (42MX)					2.0	VCCI+0.3	2.0	VCCI+0.3	2.0	VCCI+0.3	2.0	VCCI+0.3	V
IIL			VIN = 0.5V			-10		-10		-10		-10	µA
IIH			VIN = 2.7V			-10		-10		-10		-10	µA
Input	Transition					500		500		500		500	ns
Time, TR and TF
CIO I/O Capacitance						10		10		10		10	pF
Standby	Current,	A40MX02,				3		25		10		25	mA
2			A40MX04
ICC
			A42MX09			5		25		25		25	mA
			A42MX16			6		25		25		25	mA
		A42MX24,				20		25		25		25	mA
			A42MX36
Low-Power	Mode	42MX devices				0.5		ICC - 5.0		ICC - 5.0		ICC - 5.0	mA
Standby Current				only

IIO, I/O source sink Can be derived from the IBIS model (http://www.actel.com/techdocs/models/ibis.html) current

Notes:

1.Only one output tested at a time. VCC/VCCI = min.

2.All outputs unloaded. All inputs = VCC/VCCI or GND.

v6.0

1-15

40MX and 42MX FPGA Families

3.3V Operating Conditions

Table 10 •	Absolute Maximum Ratings for 40MX Devices*
Symbol		Parameter	Limits	Units
VCC		DC Supply Voltage	–0.5 to +7.0	V
VI		Input Voltage	–0.5 to VCC+0.5	V
VO		Output Voltage	–0.5 to VCC+0.5	V
tSTG		Storage Temperature	–65 to +150	°C

Note: *Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Devices should not be operated outside the Recommended Operating Conditions.

Table 11 •	Absolute Maximum Ratings for 42MX Devices*
Symbol		Parameter	Limits	Units
VCCI		DC Supply Voltage for I/Os	–0.5 to +7.0	V
VCCA		DC Supply Voltage for Array	–0.5 to +7.0	V
VI		Input Voltage	–0.5 to VCCI+0.5	V
VO		Output Voltage	–0.5 to VCCI+0.5	V
tSTG		Storage Temperature	–65 to +150	°C

Note: *Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Devices should not be operated outside the Recommended Operating Conditions.

Table 12 • Recommended Operating Conditions

Parameter	Commercial	Industrial	Military	Units
Temperature Range*	0 to +70	–40 to +85	–55 to +125	°C
VCC (40MX)	3.0 to 3.6	3.0 to 3.6	3.0 to 3.6	V
VCCA (42MX)	3.0 to 3.6	3.0 to 3.6	3.0 to 3.6	V
VCCI (42MX)	3.0 to 3.6	3.0 to 3.6	3.0 to 3.6	V

Note: *Ambient temperature (TA) is used for commercial and industrial grades; case temperature (TC) is used for military grades.

1-16

v6.0

40MX and 42MX FPGA Families

3.3V LVTTL Electrical Specifications

Table 13 • 3.3V LVTTL Electrical Specifications

			Commercial		Commercial -F		Industrial		Military
Symbol		Parameter	Min.	Max.	Min.	Max.	Min.	Max.	Min.	Max.	Units
1		IOH = –4mA	2.15		2.15		2.4		2.4		V
VOH
V 1		I = 6mA		0.4		0.4		0.48		0.48	V
OL		OL
VIL			–0.3	0.8	–0.3	0.8	–0.3	0.8	–0.3	0.8	V
VIH (40MX)			2.0	VCC+0.3	2.0	VCC+0.3	2.0	VCC+0.3	2.0	VCC+0.3	V
VIH (42MX)			2.0	VCCI+0.3	2.0	VCCI+0.3	2.0	VCCI+0.3	2.0	VCCI+0.3	V
IIL				–10		–10		–10		–10	µA
IIH				–10		–10		–10		–10	µA
Input Transition	Time,			500		500		500		500	ns
TR and TF
CIO I/O Capacitance				10		10		10		10	pF
	2	A40MX02,		3		25		10		25	mA
Standby Current, ICC
		A40MX04
		A42MX09		5		25		25		25	mA
		A42MX16		6		25		25		25	mA
		A42MX24,		15		25		25		25	mA
		A42MX36
Low-Power	Mode	42MX		0.5		ICC - 5.0		ICC - 5.0		ICC - 5.0	mA
Standby Current		devices only
IIO, I/O source sink		Can be derived from the IBIS model (http://www.actel.com/techdocs/models/ibis.html)
current
Notes:

1.Only one output tested at a time. VCC/VCCI = min.

2.All outputs unloaded. All inputs = VCC/VCCI or GND.

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40MX and 42MX FPGA Families

Mixed 5.0V/3.3V Operating Conditions (for 42MX Devices Only)

Table 14 •	Absolute Maximum Ratings*
Symbol		Parameter	Limits	Units
VCCI		DC Supply Voltage for I/Os	–0.5 to +7.0	V
VCCA		DC Supply Voltage for Array	–0.5 to +7.0	V
VI		Input Voltage	–0.5 to VCCI+0.5	V
VO		Output Voltage	–0.5 to VCCI+0.5	V
tSTG		Storage Temperature	–65 to +150	°C

Note: *Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Devices should not be operated outside the Recommended Operating Conditions.

Table 15 • Recommended Operating Conditions

Parameter	Commercial	Industrial	Military	Units
Temperature Range*	0 to +70	-40 to +85	–55 to +125	°C
VCCA	4.75 to 5.25	4.5 to 5.5	4.5 to 5.5	V
VCCI	3.14 to 3.47	3.0 to 3.6	3.0 to 3.6	V

Note: *Ambient temperature (TA) is used for commercial and industrial grades; case temperature (TC) is used for military grades.

Mixed 5.0V/3.3V Electrical Specifications

Table 16 • Mixed 5.0V/3.3V Electrical Specifications

		Commercial		Commercial '-F		'Industrial		Military
Symbol	Parameter	Min.	Max.	Min.	Max.	Min.	Max.	Min.	Max.	Units
1	IOH = –10mA	2.4		2.4						V
VOH
	IOH = –4mA					3.7		3.7		V
V 1	I = 10mA		0.5		0.5					V
OL	OL
	IOL = 6mA						0.4		0.4	V
VIL		–0.3	0.8	–0.3	0.8	–0.3	0.8	–0.3	0.8	V
VIH		2.0	VCCI+0.3	2.0	VCCI+0.3	2.0	VCCI+0.3	2.0	VCCI+0.3	V
IL	VIN = 0.5V		–10		–10		–10		–10	µA
IH	VIN = 2.7V		–10		–10		–10		–10	µA
Input Transition Time, TR and TF			500		500		500		500	ns
CIO I/O Capacitance			10		10		10		10	pF
2	A42MX09		5		25		25		25	mA
Standby Current, ICC
	A42MX16		6		25		25		25	mA
	A42MX24, A42MX36		20		25		25		25	mA
Low-Power Mode Standby Current			0.5		ICC - 5.0		ICC - 5.0		ICC - 5.0	mA
IIO I/O source sink current	Can be derived from the IBIS model (http://www.actel.com/techdocs/models/ibis.html)
Notes:

1.Only one output tested at a time. VCCI = min.

2.All outputs unloaded. All inputs = VCCI or GND.

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40MX and 42MX FPGA Families

Output Drive Characteristics for 5.0V PCI Signaling

MX PCI device I/O drivers were designed specifically for high-performance PCI systems. Figure 1-16 on page 1-21 shows the typical output drive characteristics of the MX devices. MX output drivers are compliant with the PCI Local Bus Specification.

Table 17 •	DC Specification (5.0V PCI Signaling)1
			PCI				MX
Symbol	Parameter	Condition	Min.		Max.	Min.		Max.	Units
V	Supply Voltage for I/Os		4.75		5.25	4.75		5.252	V
CCI
VIH	Input High Voltage		2.0		VCC + 0.5	2.0		VCCI + 0.3	V
VIL	Input Low Voltage		–0.5		0.8	–0.3		0.8	V
IIH	Input High Leakage Current	VIN = 2.7V			70	—		10	µA
IIL	Input Low Leakage Current	VIN=0.5V			–70	—		–10	µA
VOH	Output High Voltage	IOUT = –2 mA	2.4						V
		IOUT = –6 mA				3.84
VOL	Output Low Voltage	IOUT = 3 mA,			0.55	—		0.33	V
		6 mA
CIN	Input Pin Capacitance				10	—		10	pF
CCLK	CLK Pin Capacitance		5		12	—		10	pF
LPIN	Pin Inductance				20	—		< 8 nH3	nH

Notes:

1.PCI Local Bus Specification, Version 2.1, Section 4.2.1.1.

2.Maximum rating for VCCI –0.5V to 7.0V.

3.Dependent upon the chosen package. PCI recommends QFP and BGA packaging to reduce pin inductance and capacitance.

Table 18 •	AC Specifications (5.0V PCI Signaling)*
				PCI			MX
Symbol	Parameter	Condition		Min.	Max.	Min.		Max.	Units
ICL	Low Clamp Current	–5 < VIN ≤ –1		–25 + (VIN +1)		–60		–10	mA
				/0.015
Slew (r)	Output Rise Slew Rate	0.4V to 2.4V load		1	5	1.8		2.8	V/ns
Slew (f)	Output Fall Slew Rate	2.4V to 0.4V load		1	5	2.8		4.3	V/ns
Note: *PCI Local Bus Specification, Version 2.1, Section 4.2.1.2.

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40MX and 42MX FPGA Families

Output Drive Characteristics for 3.3V PCI Signaling

Table 19 •	DC Specification (3.3V PCI Signaling)1
			PCI				MX
Symbol	Parameter	Condition	Min.		Max.	Min.		Max.	Units
VCCI	Supply Voltage for I/Os		3.0		3.6	3.0		3.6	V
VIH	Input High Voltage		0.5		VCC + 0.5	0.5		VCCI + 0.3	V
VIL	Input Low Voltage		–0.5		0.8	–0.3		0.8	V
IIH	Input High Leakage Current	VIN = 2.7V			70			10	µA
IIL	Input Leakage Current				–70			–10	µA
VOH	Output High Voltage	IOUT = –2 mA	0.9			3.3			V
VOL	Output Low Voltage	IOUT = 3 mA,			0.1			0.1 VCCI	V
		6 mA
CIN	Input Pin Capacitance				10			10	pF
CCLK	CLK Pin Capacitance		5		12			10	pF
LPIN	Pin Inductance				20			< 8 nH3	nH

Notes:

1.PCI Local Bus Specification, Version 2.1, Section 4.2.2.1.

2.Maximum rating for VCCI –0.5V to 7.0V.

3.Dependent upon the chosen package. PCI recommends QFP and BGA packaging to reduce pin inductance and capacitance.

Table 20 •	AC Specifications for (3.3V PCI Signaling)*
				PCI			MX
Symbol	Parameter	Condition		Min.	Max.	Min.		Max.	Units
ICL	Low Clamp Current	–5 < VIN ≤ –1		–25 + (VIN +1)		–60		–10	mA
				/0.015
Slew (r)	Output Rise Slew Rate	0.2V to 0.6V load		1	4	1.8		2.8	V/ns
Slew (f)	Output Fall Slew Rate	0.6V to 0.2V load		1	4	2.8		4.0	V/ns
Note: *PCI Local Bus Specification, Version 2.1, Section 4.2.2.2.

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40MX and 42MX FPGA Families

	0.50
	0.45
	0.40		PCI I OL Maximum
	0.35
	0.30
	0.25
	0.20		MX PCI IOL
(A)	0.15
Current	0.10				PCI I OL Minimum
	0.05
	0.00
	0	1	2	3	4	5	6
	–0.05	PCI I OH Maximum
						MX PCI IOH
	–0.10
	–0.15				PCI I OH	Minimum
	–0.20

Voltage Out (V)

Figure 1-16 • Typical Output Drive Characteristics (Based Upon Measured Data)

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1-21

40MX and 42MX FPGA Families

Junction Temperature (TJ)

The temperature variable in the Designer software refers to the junction temperature, not the ambient temperature. This is an important distinction because the heat generated from dynamic power consumption is usually hotter than the ambient temperature. EQ 1-1, shown below, can be used to calculate junction temperature.

EQ 1-1

Junction Temperature = ∆T + Ta(1)

Where:

Ta = Ambient Temperature

∆T = Temperature gradient between junction (silicon) and ambient

∆T = θja * P(2)

P = Power

θja = Junction to ambient of package. θja numbers are located in the Package Thermal Characteristics table below.

Package Thermal Characteristics

The device junction-to-case thermal characteristic is θjc, and the junction-to-ambient air characteristic is θja. The thermal characteristics for θja are shown with two different air flow rates.

The maximum junction temperature is 150°C.

Maximum power dissipation for commercialand industrial-grade devices is a function of θja.

A sample calculation of the absolute maximum power dissipation allowed for a TQFP 176-pin package at commercial temperature and still air is as follow:

Maximum Power Allowed =	Max.---------------------------------------------------------------------------------------------------------------------------------junction temp. (°C) – Max. ambient temp. (°C)	=	150----------------------------------°C – 70°C	= 2.86W
	θja(°C/W)		28°C/W

The maximum power dissipation for military-grade devices is a function of θjc. A sample calculation of the absolute maximum power dissipation allowed for CQFP 208-pin package at military temperature and still air is as follows:

Maximum Power Allowed =	Max.---------------------------------------------------------------------------------------------------------------------------------junction temp. (°C) – Max. ambient temp. (°C)	=	150-------------------------------------°C – 125°C	= 3.97W
	θjc(°C/W)		6.3°C/W

Table 21 • Package Thermal Characteristics

				θja
		θjc		1.0 m/s	2.5 m/s
Plastic Packages	Pin Count		Still Air	200 ft/min.	500 ft/min.	Units
Plastic Quad Flat Pack	100	12.0	27.8	23.4	21.2	°C/W
Plastic Quad Flat Pack	160	10.0	26.2	22.8	21.1	°C/W
Plastic Quad Flat Pack	208	8.0	26.1	22.5	20.8	°C/W
Plastic Quad Flat Pack	240	8.5	25.6	22.3	20.8	°C/W
Plastic Leaded Chip Carrier	44	16.0	20.0	24.5	22.0	°C/W
Plastic Leaded Chip Carrier	68	13.0	25.0	21.0	19.4	°C/W
Plastic Leaded Chip Carrier	84	12.0	22.5	18.9	17.6	°C/W
Thin Plastic Quad Flat Pack	176	11.0	24.7	19.9	18.0	°C/W
Very Thin Plastic Quad Flat Pack	80	12.0	38.2	31.9	29.4	°C/W
Very Thin Plastic Quad Flat Pack	100	10.0	35.3	29.4	27.1	°C/W
Plastic Ball Grid Array	272	3.0	18.3	14.9	13.9	°C/W
Ceramic Packages
Ceramic Quad Flat Pack	208	2.0	22.0	19.8	18.0	°C/W
Ceramic Quad Flat Pack	256	2.0	20.0	16.5	15.0	°C/W

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40MX and 42MX FPGA Families

Timing Models

Predicted

Input Delay Internal Delays Routing Output Delay

Delays

I/O Module

I/O Module

tINYL=0.62 ns tIRD2=2.59 ns

Logic Module

tDLH=3.32 ns

tIRD1=2.09 ns

tRD1=1.28 ns

tIRD4=3.64 ns

t

tRD2=1.80 ns

tENHZ=7.92 ns

tIRD8=5.73 ns

tPD=1.24 ns

tRD4=2.33 ns

CO=1.24 ns

tRD8=4.93 ns

Array

Clock

tCKH=4.55 ns

FO=128

FMAX=180 MHz

Note: * Values are shown for 40MX ‘–3’ speed devices at 5.0V worst-case commercial conditions.

Figure 1-17 • 40MX Timing Model*
Input Delays		Internal Delays		Predicted		Output Delays
					Routing
I/O Module		tIRD1=2.0 ns†			Delays	I/O Module
tINYL=0.8 ns
		Combinatorial
		Logic Module		t			tDLH=2.5 ns
					RD1=0.7 ns
D	Q	tPD=1.2 ns		tRD2=1.9 ns
				tRD4=1.4 ns
				tRD8=2.3 ns
G						I/O Module
tINH=0.0 ns		Sequential					tDLH=2.5 ns
		Logic Module
tINSU=0.3 ns
tINGL=1.3 ns		Combin
			D	Q		D	Q
		-atorial			tRD1=0.70 ns		tENHZ=4.9 ns
		Logic
						G
		include
						tOUTH=0.00 ns
Array		tSUD=0.3 ns	tCO=1.3 ns			t
						tOUTSU=0.3 ns
Clocks		tHD=0.00 ns				GLH=2.6 ns
	FO = 32
tCKH=2.70 ns
FMAX=296 MHz		tLCO=5.2 ns (light loads, pad-to-pad)

Notes: *Values are shown for A42MX09 ‘–3’ at 5.0V worst-case commercial conditions.

† Input module predicted routing delay.

Figure 1-18 • 42MX Timing Model*

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40MX and 42MX FPGA Families

Input Delays		Internal Delays		Predicted	Output Delays
				Routing
I/O Module		tIRD1=2.0 ns†		Delays	I/O Module
tINYL=0.8 ns
		Combinatorial
		Logic Module		tRD1=0.7 ns		tDLH=2.5 ns
D	Q	tPD=1.2 ns		tRD2=1.9 ns
				tRD4=1.4 ns
				tRD8=2.3 ns
G					I/O Module
tINH=0.0 ns		Sequential				tDLH=2.5 ns
		Logic Module
tINSU=0.3 ns
tINGL=1.3 ns		Combin
			D	Q	D	Q
		-atorial		tRD1=0.70 ns		tENHZ=4.9 ns
		Logic
					G
		include
					tOUTH=0.00 ns
Array		tSUD=0.3 ns	tCO=1.3 ns		t
					tOUTSU=0.3 ns
Clocks		tHD=0.00 ns			GLH=2.6 ns
	FO = 32
tCKH=2.70 ns
FMAX=296 MHz		tLCO=5.2 ns (light loads, pad-to-pad)

Notes: * Values are shown for A42MX36 ‘–3’ at 5.0V worst-case commercial conditions. ** Load-dependent

Figure 1-19 • 42MX Timing Model (Logic Functions Using Quadrant Clocks)

Input Delays

I/O Module

tINPY=1.0ns		t
		IRD1=2.0ns
D	Q
G			Predicted	I/O Module
			Routing
tINSU=0.5ns				tDLH=2.6ns
			Delays
tINH=0.0ns		WD [7:0]	RD [7:0]
tINGO=1.4ns		WRAD [5:0]	tRD1=0.9ns
			RDAD [5:0]
		BLKEN	REN	D	Q

				WEN						G
				WCLK	RCLK
			tADSU=1.6ns		tADSU=1.6ns				t	GHL=2.9ns
Array			tADH=0.0ns		tADH=0.0ns				t	LSU=0.5ns
			t		t
Clocks			WENSU=2.7ns		RENSU=0.6ns				tLH=0.0ns
			tBENS=2.8ns		tRCO=3.4ns

FMAX =167 MHz

Note: *Values are shown for A42MX36 ‘–3 at 5.0V worst-case commercial conditions.

Figure 1-20 • 42MX Timing Model (SRAM Functions)

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v6.0