ACTEL A500K050, A500K130, A500K180, A500K270, A500K350 User Manual

1

查询A500K050-BG272供应商

Advanced v.3

ProASIC

Features and Benefits

High Capacity

• 98,000 to 1.1 Million System Gates

• 14k to 138k Bits of Two-Port SRAM

• 210 to 623 User I/Os

Performance

• 33 MHz PCI 32-Bit

• Internal System Performance up to 250 MHz

• External System Performance up to 100 MHz

Low Power

• Low Impedance Flash Switches

• Segmented Hierarchical Routing Structure

• Small Efficient Logic Cells

High Performance Routing Hierarchy

• Ultra Fast Local Network

• Efficient Long Line Network

• High Speed Bus Network

• High Performance Global Network

Nonvolatile and Reprogrammable Flash
Technology

• Live at Power-Up

• No Configuration Boot Device Required

• Retains Programmed Design During Power-Down/
Power-Up Cycles

500K Family

™

I/O

• Mixed 2.5/3.3 Volt Support

• 3.3V, 33 MHz PCI Compliance (PCI Revision 2.2)

• Individually Selectable 2.5V or 3.3V I/Os and Slew Rate
(25, 50, and 100 mA/nsec)

Secure Programming

• Security Bit Prevents Read Back of Programming Bit
Stream

Standard FPGA and ASIC Design Flow

• Flexibility to Choose Vendor-Specific Front-End Tools

• Provide Efficient Design Through Front-End Timing and
Gate Optimization

ISP Support

• In-System Programming (ISP) with Silicon Sculptor and
Silicon Explorer II

Embedded Memory Netlist Generator for
SRAMs and FIFOs

• Ensures Optimal Usage of Embedded Memory Blocks

• Up to 133 MHz Synchronous and Asynchronous Operation

JTAG Support

• IEEE Std. 1149.1 (JTAG) Compliant

Individual ProASIC Device ID

• Control and Restrict IP Delivery to Individual ProASIC
Device

ProASIC Product Profile

Device A500K050 A500K130 A500K180 A500K270 A500K350 A500K440 A500K510
Maximum System Gates

Typical Gates
Maximum Flip-Flops
Embedded RAM Bits
Embedded RAM Blocks (256 X 9)
Logic Tiles
Global Clocks
Maximum User I/Os
JTAG
PCI
Package (by Pin Count)

PQFP
PBGA
FBGA

December 1999

© 1999 Actel Corporation

98,000 287,000 369,000 473,000 638,000 956,000 1,100,000
43,000 105,000 150,000 215,000 280,000 350,000 410,000

5,376 12,800 18,432 26,880 34,816 43,776 51,200

14k 46k 55k 65k 74k 124k 138k

6 202428325460

5,376 12,800 18,432 26,880 34,816 43,776 51,200

4444444
210 312 368 446 496 570 623
Yes Yes Yes Yes Yes Yes Yes
Yes Yes Yes Yes Yes Yes Yes

208
272

208

272, 456

208
456
580

208
456
580 580 580 580

General Description

The ProASIC 500K family combines the advantages of ASICs
with the benefits of programmable devices through its
nonvolatile Flash technology. ProASIC 500K devices make it
possible to create high-density systems using existing ASIC or
FPGA design flows and tools, shortening time-to-production.
ASIC migration is not necessary for any volume because the
family offers cost effective reprogrammable solutions, ideal
for applications in the networking, telecom, computer, and
consumer markets.

The ProASIC 500K family offers seven devices with 98k to

1.1M system gates and includes up to 138k bits of embedded

Ordering Information

A500K130 – PQ 2081

two-port memory. These memory blocks include hardwired
FIFO circuitry as well as circuits to generate or check parity.
This minimizes external logic gate count and complexity
while maximizing flexibility and utility.

Process Technology

The ProASIC 500K family achieves its non-volatility and
reprogrammability through an advanced 4LM Flash-based

0.25µ channel length LVCMOS technology process. Standard
CMOS design techniques are used to implement logic and
control functions resulting in highly predictable performance
and gate array compatibility.

Package Lead Count

Package Type

BG = Ball Grid Array
PQ = Plastic Quad Flat Pack
FG = Fine Ball Grid Array

Speed Grade

Blank = Standard Speed

–1 = TBD

Part Number

A500K050 = 98,000 System Gates
A500K130 = 287,000 System Gates
A500K180 = 369,000 System Gates
A500K270 = 473,000 System Gates
A500K350 = 638,000 System Gates
A500K440 = 956,000 System Gates
A500K510 = 1,100,000 System Gates

Application (Ambient Temperature Range)
Blank = Commercial (0 to +70°C)
I = Industrial (–40 to +85°C)
PP = Pre-production
ES = Engineering Silicon (Room Temperature Only)

2

✔

✔

✔

✔

✔

✔

Product Plan

A500K050 Device

208-Pin Plastic Quad Flat Pack (PQFP)
272-Pin Plastic Ball Grid Array (PBGA)

A500K130 Device

™

ProASIC

500K Family

Speed Grade Application

Std –1* C I

✔
✔

PPP
PPP

208-Pin Plastic Quad Flat Pack (PQFP)
272-Pin Plastic Ball Grid Array (PBGA)
456-Pin Plastic Ball Grid Array (PBGA)

✔

PPP
PPP
PPP

A500K180 Device

208-Pin Plastic Quad Flat Pack (PQFP)
456-Pin Plastic Ball Grid Array (PBGA)

PPP
PPP

580-Pin Fine Ball Grid Array (FBGA) P P P P

A500K270 Device

208-Pin Plastic Quad Flat Pack (PQFP)
456-Pin Plastic Ball Grid Array (PBGA)

PPP
PPP

580-Pin Fine Ball Grid Array (FBGA) P P P P

A500K350 Device

580-Pin Fine Ball Grid Array (FBGA) P P P P

A500K440 Device

580-Pin Fine Ball Grid Array (FBGA) P P P P

A500K510 Device

580-Pin Fine Ball Grid Array (FBGA) P P P P

Contact your Actel sales representative for package availability.
Applications: C = Commercial Availability:

✔

= Limited Availability. Contact your Actel Sales representative for the latest

I = Industrial availability information.

*Speed Grade: –1 = TBD P = Planned

Plastic Device Resources

User I/Os

Device

208-Pin

A500K050 170 210 — —
A500K130 170 210 312 —
A500K180 170 — 368 368
A500K270 170 — 368 446
A500K350 — — — 496
A500K440 — — — 496
A500K510 — — — 496

Package Definitions (Contact your Actel sales representative for product availability.)

PQFP = Plastic Quad Flat Pack, PBGA = Plastic Ball Grid Array, FBGA = Fine Ball Grid Array

PQFP

PBGA

272-Pin

PBGA

456-Pin

FBGA

580-Pin

3

ProASIC 500K Architecture

The ProASIC 500K family utilizes a proprietary architecture
that results in granularity comparable to gate arrays. Unlike
SRAM-based FPGAs, ProASIC devices do not utilize look-up
tables or architectural mapping during design. Instead,
designs are directly synthesized to gates that streamline the
design flow, increase design productivity, and eliminate
dependencies on vendor-specific design tools.

The ProASIC 500K device core consists of a Sea-of-Tiles

™

(Figure 1). Each tile (Figure 2) can be configured into a
3-input logic function (i.e. NAND gate, D-Flip-Flop, etc.) by
programming the appropriate interconnect Flash switches,
shown in Figure 3 on page 5. Gates and larger functions are
connected together, utilizing the four levels of routing

hierarchy. Flash memory bits are distributed throughout each
device providing non-volatile, reconfigurable interconnect
programming. Flash switches are programmed to connect
signal lines to the appropriate logic cell inputs and outputs.
Dedicated high-performance lines are connected as needed
for fast, low-skew clock distribution throughout the core.
Maximum core utilization is possible for virtually any design.

The ProASIC 500K devices also contain embedded two-port
SRAM blocks that have built in FIFO/RAM control logic.
Programming options include synchronous or asynchronous
operation, two-port RAM configurations, user defined depth
and width, and parity generation or checking. Table 2 on

page 9 lists the 24 basic memory configurations.

Figure 1 • The ProASIC Device Architecture

In 1

256x9 Two-Port SRAM
or FIFO Block

Logic Tile

Local Routing
Efficient Long

Line Routing

In 2 (CLK)

In 3 (Reset)

Figure 2 • Core Logic Tile

4

Sel 1 Sel 2

Word

Figure 3 • Flash Switch

Routing Resources

The routing structure of the ProASIC 500K devices is
designed to provide high performance through routing
flexibility. It is composed of four levels of hierarchical
resources: ultra fast local resources, efficient long line
resources, high speed bus resources, and high performance
global networks.

The ultra fast local resources are high speed dedicated lines
that allow the output of each tile to directly connect to every
input of the eight surrounding tiles (Figure 4).

The efficient long line resources provide routing for longer
distance and higher fanout connections. These resources vary
in length (spanning 1, 2, or 4 tiles), run both vertically and
horizontally, and cover the entire ProASIC device (Figure 5

on page 6). Each tile can drive signals onto the efficient long

line resources, and the resources can access every input of a
tile. Active buffers are inserted automatically by the
ASICmaster software to limit the effects of loading due to
distance and fanout.

™

ProASIC

Switch In

Switch Out

500K Family

The high speed bus resources span across the entire device
with minimal delay and are used to route very long or very
high fanout nets. These resources run vertically and
horizontally, and provide multiple access to each group of
tiles throughout the device (Figure 6 on page 6).

The high performance global networks are low skew, high
fanout nets that are accessible from four dedicated pins or
from internal logic (Figure 7 on page 7). These nets are
typically used to distribute clocks, resets, and other high
fanout nets requiring a minimum skew. The global networks
are implemented as clock trees, and signals can be
introduced at any junction. These can be used hierarchically,
with signals accessing every input on all tiles.

L

L

L

L L

Figure 4 • Ultra Fast Local Resources

Efficient
Long Lines

L

Inputs

L

L

LL

L

Output

L L

L

L

L

(1, 2, or 4 tiles long)

Connection to
logic cell inputs

Ultra Fast
Local Lines
(connects a tile to the
adjacent tile, I/O buffer,
or memory block)

5

4 Tiles Long

LL LLLL

LL LLLL

LL LLLL

LL LLLL

LL LLLL

2 Tiles Long

1 Tile Long

Logic Tile

1 Tile Long
2 Tiles Long

4 Tilss Long

Logic Cell

Figure 5 • Efficient Long Line Resources

High Speed Bus Resouces

PAD RING

PAD RING

I/O RING

I/O RING

PAD RING

Figure 6 • High Speed Bus Resources

6

PAD RING

PAD RING

ProASIC

High Performace
Global Network

I/O RING

™

500K Family

Global

Pads

I/O RING

PAD RING

Figure 7 • High Performance Global Network

Global

Pads

7

Input/Output Blocks

To meet the needs of complex system designs, the ProASIC
500K family offers devices with a large number of I/O pins,
with the A500K510 device offering up to 623 user I/O pins. If
the I/O pad is powered at 3.3V, each I/O can be selectively
configured at 2.5V and 3.3V compliant threshold levels.

Table 1 shows the various supply voltage configurations

available in the ProASIC devices. Figure 8 illustrates I/O
interfaces with other devices. All I/Os also include an ESD
protection circuit. Each I/O is tested according to the
following models:

Human Body Model (HBM)

1500V

(Per Mil Std 883 Method 3015)

Machine Model 200V

Table 1 • ProASIC Power Supply Voltages

V

DDP

Input T olerance

2.5V 3.3V

2.5V 3.3V, 2.5V

• Selectable drive strengths

• Selectable slew rates (25mA/s, 50mA/s, 100mA/s)

• Three-state enable

2.5V

Device

2.5V

Device

3.3V

Device

ProASIC

V

DDL

V

DDP

ProASIC

V

DDL

V

DDP

= 2.5V
= 2.5V

= 2.5V
= 3.3V

2.5V

Device

2.5V

Device

3.3V

Device

Output Drive

Note: V

DDL

is always 2.5V.

2.5V 3.3V, 2.5V

The I/O pads are fully configurable to provide the maximum
flexibility and speed. Each pad can be configured as an input,
an output, a three-state driver, or a bi-directional buffer
(Figure 9). I/O pads configured as inputs have the following
features:

• Individually selectable 2.5V or 3.3V compliant threshold

1

levels

• Optional pull-up resistor

I/O pads configured as outputs have the following features:

• Individually selectable 2.5V or 3.3V compliant output

1

signals

• 3.3V PCI compliant

• Ability to drive LVTTL and LVCMOS levels

• Selectable drive strengths

• Selectable slew rates (25mA/s, 50mA/s, 100mA/s)

• Three-state enable

I/O pads configured as bi-directional buffers have the
following features:

• Individually selectable 2.5V or 3.3V compliant output
signals and threshold levels

1

• 3.3V PCI compliant

• Ability to drive LVTTL and LVCMOS levels

• Optional pull-up resistor

1. If V

= 2.5V, pads are compliant to 2.5V level signals as defined by JEDEC

DDP

JESD 8-5.

Figure 8 • I/O Interfaces

3.3V/2.5V

Signal Control

Y

EN

A

3.3V/2.5V Signal Control
Drive Strength and Slew

Rate Control

Pull-up
Control

Pad

Figure 9 • I/O Block Schematic Representation

User Security and Traceability

2

The ProASIC 500K devices have a read-protect bit that, once
programmed, prevents the programmed contents from being
read from the part. To clear the read-protect bit, the entire
part must be erased. This capability lets you secure the
programmed design and prevent it from being read back and
duplicated. For traceability a 12-character alphanumeric user
part number field allows the user to assign a user part ID,
which can subsequently be read back by the programmer.

2. Available after completion of full qualification/characterization 2H, 2000.

8

Embedded Memory Floorplan

The embedded memory is located across the top of the device
(see Figure 1 on page 4). Depending upon the device, 6 to 60
(256x9) blocks of memory are available to support a variety of
possible memory configurations. Each block can be
programmed as an independent memory or combined, using
dedicated memory routing resources, to form larger and more
complex memories.

Embedded Memory Configurations

The embedded memory in the ProASIC 500K family offers
great flexibility in memory configuration. Whereas other
programmable vendors typically provide single port memories
that can be transformed into a two-port memory at the loss of
half the memory, each ProASIC block is designed and
optimized as a two-port memory (1r1w). This provides 138k
total memory bits for two-port and single port memory usage
in the A500K510 device.

Each memory can be configured as a FIFO or SRAM, with
independent selection of synchronous or asynchronous read
and write ports (Table 2). However, multiple write ports are
not supported. Additional characteristics include
programmable FIFO flags and selectable depth, and parity
check and generation. Figure 10 and Figure 11 on page 10

™

ProASIC

500K Family

show the block diagram of the basic SRAM and FIFO blocks.
These memories are designed to operate at up to 133 MHz
when operated individually. Each block contains a 256 word
deep by 9-bit wide (1r, 1w) memory. The memory blocks,
shown in Figure 12 on page 11, may be combined in parallel
to form wider memories or stacked to form deeper memories.
This provides optimal bit widths of 9 (1 block), 18, 36, and 72,
and optimal depths of 256, 572, 768, and 1024. Refer to the

ProASIC Macro Library Guide for more information.

Figure 13 on page 11 shows an example of optimal memory

usage. Three memories have been compiled with various
widths and depths using 10 blocks and consuming all 23,040
bits. Figure 14 on page 11 shows an example of doubling up
memory to create extra read ports. In this example, 10 out of
60 blocks of the A500K510 are fully used, but yield an
effective 6,912 bits of multiple port memories. The
MEMORYmaster

™

software facilitates an easy means of
building wider and deeper memories for optimal memory
usage.

Table 2 • Basic Memory Configurations

Type Write Access Read Access Parity Library Cell Name

RAM Asynchronous Asynchronous Checked RAM256x9AA
RAM Asynchronous Asynchronous Generated RAM256x9AAP
RAM Asynchronous Synchronous T ransparent Chec ked RAM256xAST
RAM Asynchronous Synchronous T ransparent Gener ated RAM256xASTP
RAM Asynchronous Synchronous Pipelined Checked RAM256x9ASR
RAM Asynchronous Synchronous Pipelined Generated RAM256x9ASRP
RAM Synchronous Asynchronous Checked RAM256x9SA
RAM Synchronous Asynchronous Generated RAM256xSAP
RAM Synchronous Synchronous T r ansparent Chec ked RAM256x9SST
RAM Synchronous Synchronous T r ansparent Generated RAM256x9SSTP
RAM Synchronous Synchronous Pipelined Checked RAM256x9SSR
RAM Synchronous Synchronous Pipelined Generated RAM256x9SSRP
FIFO Asynchronous Asynchronous Checked FIFO256xAA
FIFO Asynchronous Asynchronous Generated FIFO256x9AAP
FIFO Asynchronous Synchronous Transparent Checked FIFO256xAST
FIFO Asynchronous Synchronous Transparent Generated FIFO256x9ASTP
FIFO Asynchronous Synchronous Pipelined Checked FIFO256x9ASR
FIFO Asynchronous Synchronous Pipelined Generated FIFO256x9ASRP
FIFO Synchronous Asynchronous Checked FIFO256x9SA
FIFO Synchronous Asynchronous Generated FIFO256xSAP
FIFO Synchronous Synchronous Transparent Checked FIFO256x9SST
FIFO Synchronous Synchronous Transparent Generated FIFO256x9SSTP
FIFO Synchronous Synchronous Pipelined Checked FIFO256x9SSR
FIFO Synchronous Synchronous Pipelined Generated FIFO256x9SSRP

9

WDATA <0:8>

WADDR <0:7>

WRB

WBLKB

WCLK

WPE

WDATA <0:8>

WADDR <0:7>

WRB

WBLKB

WCLK

WPE

SRAM

(256 X 9)

SyncWrite &

Sync Read

Ports

PARODD

SRAM

(259 X 9)

Sync Write

&

Async Read

ports

PARODD

Figure 10 • Example SRAM Block Diagrams

RDATA <0:8>
RADDR <0:7>

RDB
RBLKB
RCLK

RPE

RDATA <0:8>
RADDR <0:7>
RDB

RBLKB

RPE

WDATA <0:8>

WADDR <0:7>

WRB

WBLKB

WPE

WDATA <0:8>

WADDR <0:7>

WRB

WBLKB

WPE

SRAM

(256 X 9)

Async Write

&

Async Read

Ports

PARODD

SRAM

(259 X 9)

Async Write

&

Sync Read

Ports

PARODD

RDATA <0:8>
RADDR <0:7>

RDB
RBLKB

RPE

RDATA <0:8>
RADDR <0:7>

RDB
RBLKB

RCLK

RPE

WDATA<0:8>

LEVEL<0:7>

LGDEP<0:2>

WRB

WBLKB

RDB

RBLKB

PARODD

WCLK

WDATA <0:8>

LEVEL <0:7>
LGDEP<0:2>

WRB

WBLKB

RDB

RBLKB

PARODD

FIFO

(256 X 9)

Sync Write &

Sync Read

Ports

FIFO

(256 X 9)

Async Write &

Sync Read

Ports

Figure 11 • Basic FIFO Block Diagrams

RDATA <0:8>

WPE
RPE

FULL
EMPTY

EQTH
GEQTH

RCLK

RDATA <0:8>

WPE
RPE

FULL
EMPTY

EQTH
GEQTH

RCLK

WDATA <0:8>

LEVEL <0:7>
LGDEP<0:2>

WRB

WBLKB

RDB

RBLKB

PARODD

WCLK

WDATA <0:8>

LEVEL <0:7>
LGDEP<0:2>

WRB

WBLKB

RDB

RBLKB

PARODD

FIFO

(256 X 9)

Sync Write &

Async Read

Ports

FIFO

(256 X 9)

Async Write &

Async.Read

Ports

RDATA <0:8>

WPE
RPE
FULL
EMPTY

EQTH
GEQTH

RDATA <0:8>

WPE
RPE

FULL
EMPTY

EQTH
GEQTH

10

Word Width

ProASIC

™

500K Family

Word

256925692569256

Depth

Figure 12 • A500K510 Memory Block Architecture

Word Width

9

Word

Depth

256

9

9

18 bit x 512 word 1r1w

9

9

256

…

60 blocks

9

9

9

2569256925692569256

9

256

18 bit x 256 word 1r1w

9 bit x 1,024 word 1r1w

Figure 13 • Memories with Different Width and Depth

Word Width

9

9

Word

Depth

256

9

Read Ports

9 bit x 512 word, 4r1w

Figure 14 • Multiport Memory Usage

Total Memory Blocks Used = 10
Total Memory Bits = 23,040

Write Port Write Port

9

9

256

Read Ports

9 bit x 256 word, 2r1w

Total Memory Blocks Used = 10
Total Memory Bits = 6,912

11

Design Environment

ProASIC devices are supported by Actel’s ASICmaster and
MEMORYmaster software, as well as third party CAE tools.
Using the standard VHDL or Verilog HDL descriptions, no
special HDL design techniques, as required by some FPGA
vendors, are needed. This allows designers to use technology
independent HDL code for ProASIC devices. This and the
ProASIC design flow ensure a seamless transition to an ASIC,
should production volumes warrant a migration to a gate
array or a standard cell product (Figure 15).

MEMORYmaster automatically generates memories from
inputs given by the designer. The designer can select the
depth and width, usage of parity generation or check, and
synchronous or asynchronous functionality of the ports. If it is
a synchronous read port, the designer can choose whether the
output is pipelined or transparent. MEMORYmaster allows
any bit width up to 252 (for the A500K270 device), but if an
intermediate bit width is chosen, such as 16 bits, the
remaining two bits are no longer accessible for other

memories. MEMORYmaster also enables optimal memory
stacking in 256 word increments. However, any word depth
may be compiled for up to 7,168 words.

Place and route is performed by Actel’s ASICmaster software.
Available for SunOS

®

, Solaris

®

®

, HP

, and Windows NT

®

, it
accepts standard netlists in Verilog, VHDL, and in EDIF 2.0.0,
performs place and route of the design into the selected
device, and provides post layout delay information for back
annotation simulation or static timing analysis. The
ASICmaster software also contains very powerful interactive
layout capabilities for the experienced user.

Once the design is finalized, the programming bitstream is
downloaded into the device programmer for ProASIC part
programming. ProASIC 500K devices can be programmed
with the Silicon Sculptor programmer. In-system
programming is also available using the Silicon Sculptor
programmer or Silicon Explorer II.

Design Creation/Verification

Design Implementation

P&R User

Constraints

Programming

Programming

Data

Silicon

Sculptor

Silicon

Explorer II

Forward

Constraints

High-Level

Design

(Verilog or VHDL)

Synthesis T ool

ASICmaster

(P&R T ool)

Backannotation

Timing

Libraries

Timing

Analyzer

Simulation

(behavioral)

Synthesis

Library

Structural

Netlist

Placement

Constraints

SDF

Timing

File

Simulation

Library

MEMORYmaster

Timing Analysis and Simulation

Simulation

Library

Simulation

(mixed-level structural)

Figure 15 • Design Flow

12

Package Thermal Characteristics

P

TJTA–

Θ

ja

------------------=

The ProASIC 500K family is available in a number of package
types. Actel has selected packages based on high pin count,
reliability factors, and superior thermal characteristics.

The ability of a package to conduct heat away from the
silicon, through the package, to the surrounding air is
expressed in terms of thermal resistance. This
junction-to-ambient thermal resistance is measured in
degrees Celsius/Watt and is represented as Theta ja

(

Θ

ja

The lower this thermal resistance, the easier it is for the
package to dissipate heat.

The maximum allowed power (P) for a package is a function
of the maximum junction temperature (T
ambient operating temperature (T

), the maximum

J

), and the

A

™

ProASIC

junction-to-ambient thermal resistance

500K Family

Θ

junction temperature is the maximum temperature on the
active surface of the IC and is 110° C. P is defined as

Θ

is a function of the rate of airflow in contact with the

).

ja

package, in linear feet per minute (lfpm). When the
estimated power consumption exceeds the maximum allowed
power, other means of cooling must be used, such as
increasing the airflow rate.

.

ja

Maximum

:

Package T ype Pin Count

Plastic Quad Flat Pack (PQFP) 208 3.5 20 17 ˚C/W
Plastic Ball Grid Array (PBGA) 272 3 20 16.5 ˚C/W
Plastic Ball Grid Array (PBGA) 456 3 18 14.5 ˚C/W

Θ

jc

Still Air

Θ

ja

300 ft/min Units

Θ

ja

Calculating Power Dissipation

ProASIC device power is calculated in the same manner as
LVCMOS gate arrays and includes both a static and an active
component. The active component is a function of both the
number of tiles utilized and the system speed. ASICmaster
provides an automatic power calculator that can be used to
quickly and easily calculate power dissipation. Power
dissipation can also be calculated using the following
formula:

P = V

DD

* I

DD

where:

= I

I

DD

STATIC

+ I

OUTPUT

+ I

LOGIC

and

I

OUTPUT

I

LOGIC

= I

I

STATIC

STATIC CORE

is the current due to the outputs switching.

is the current due to the internal logic

+ I

STATIC I/O

signals switching.

The static power (I

) is the amount of current drawn

STATIC

when no inputs are switching. This is equal to the Quiescent
Supply Current I

specified under DC Electrical

DDQ

Specifications beginning on page 16.
Active power includes both the current due to outputs

switching and the current due to internal logic signals
switching.

n

I

OUTPUT

=

∑

i 1=

CiVifiI

+⋅⋅()

DCi

where:
C

V

i

f

i

= Capacitance on the i th output pad

i

= Voltage swing on the i th output pad

= Switching frequency on the i th output pad
n = Number of outputs
I

DCi

In most cases I

= Average DC load on each pad, if any

can be approximated by the following

OUTPUT

formula, measured in mA:

I

OUTPUT

= n * C

typ

* V * f

avg

where:
n = Number of active outputs

C

typ

= Typical capacitance load on an output
V = Average voltage swing
f

avg

= Average switching frequency of the outputs.

Typically this is less than 25% of the clock
frequency

is represented by this formula, measured in mA:

I

LOGIC

I

LOGIC

= I

* G * f * F

E

where:
I

E

= Effective µA per gate per MHz of the Actel parts.

For the ProASIC products the value is 1.2

G = Number of gates used in the design, in thousands

13

f = Operating frequency in MHz
F = Fraction of devices active on each clock edge. F

varies for different designs, but 0.15 is a
conservative and commonly used value.

For an A500K130 design that has 47,000 used gates, 20
memory blocks, 150 active outputs, an average load of 20pF,
and a 66 MHz clock, resulting in an average switching
frequency of 16.5 MHz, the power calculation appears below.

I

OUTPUT

= 150 * 20 * 10

–12

* 3.6 * 16.5 * 106 mA

= 140 mA

P

OUTPUT

I

LOGIC

= 3.6V * 140 mA = .5W
= 1.2 * 47 * 66 * 0.15 mA

= 558 mA
Therefore
I

LOGIC

P

Logic

= 558 mA

= 2.75V * 558 mA

= 1.5W
Assumptions .5k gates per 256x9 block
I

memory

= 1.2 * .5 * 66 * .15 * 20 mA

= 118 mA

P

memory

= 2.75V * 143 mA = .326

P = 1.5W + .5W + .32W = 2.32W

I

STATIC CORE

and I

STATIC I/O

are not included in this

calculation.

1000

900
800
700
600
500
400
300
200

Power Consumption (mW)

100

0

20

ProASIC

SRAM

30

110 instances of 16-bit binary counters

50 60

40

Frequency (MHz)

70

80

90

Figure 16 • Power Consumption of a 500K Device

100 120

Operating Conditions

Absolute Maximum Ratings

Parameter Condition Minimum Maximum Units

Supply Voltage Core (V
Supply Voltage IO Ring (V
DC Input Voltage –0.3 V
PCI DC Input Voltage –0.5 V
DC Input Clamp Current (IIK) V

Note: Stresses beyond those listed under Absolute Maximum ratings can cause permanent damage to the device. Exposure to maximum rated

conditions for extended periods can adversely affect device reliability. Operation of the device at these conditions or any others beyond
those listed in the Recommended Operating Conditions table on page 15 is not implied.

) –0.3 3.0 V

DDL

) –0.3 4.0 V

DDP

+ 0.3 V

DDP

+ 0.5 V

DDP

< 0 or > V

IN

DDP

–10 +10 mA

14

Temperature Maximums

ProASIC™ 500K Family

Parameter Min. Max. Units

Retention

Storage Temperature –65 +150 °C N/A
Storage Temperature—Programmed –65 +110 °C 20 years

Program

Programming Limits and Recommended Operating Conditions

Junction T emperature

Product Grade

Programming

Cycles

Program

Retention

Min. Max.

Commercial 500 20 years 0°C 110°C

Industrial 500 20 years –40°C 110°C

Supply Voltages

Mode V

DDL

V

DDP

V

PP

V

PN

Single V oltage 2.5V 2.5V 2.5V ≤ VPP ≤ 16.5 V –12V ≤ VPN ≤ 0V

Mixed V oltage 2.5V 3.3V 3.3V ≤ V

Recommended Operating Conditions

≤ 16.5V –12V ≤ VPN ≤ 0V

PP

Parameter Symbol Limits
Commercial

DC Supply Voltage (2.5V I/Os) V
DC Supply Voltage (3.3V, 2.5V I/Os) V

Operation Ambient Temperature Range T
Operation Junction Temperature (maximum) T

DDL

V

& V

DDP
DDL

A

J

DDP

2.3V to 2.7V

3.0V to 3.6V

2.3V to 2.7V
0°C to 70°C

≤ 110°C

Industrial

DC Supply Voltage (2.5V I/Os) V

DDL

DC Supply Voltage (2.5V, 3.3V I/Os) V

V
Operation Ambient Temperature Range T
Operation Junction Temperature (maximum) T

& V

DDP
DDL

A

J

DDP

2.3V to 2.7V

3.0V to 3.6V

2.3V to 2.7V

–40°C to 85°C

≤ 110°C

15

DC Electrical Specifications (V

DDP

= 2.5V)

Symbol Parameter Conditions Min. Typ. Max. Units

V
V

V

V
V
I

IN

I

DDQ

I

OZ

I

OSH

I

OSL

C
C

DDP
OH

OL

IH
IL

I/O
CLK

, V

DDL

Supply V oltage 2.3 2.7 V
Output High Voltage

High Drive

Low Drive

= –2.0 mA

I

OH

I

= –4.0 mA

OH

I

= –8.0 mA

OH

= –1.0 mA

I

OH

I

= –2.0 mA

OH

I

= –4.0 mA

OH

2.1

2.0

1.7

2.1

2.0

1.7

V

Output Low Voltage

High Drive

Low Drive

Input High Voltage 1.7 V

= 5.0 mA

I

OL

I

= 10.0 mA

OL

I

= 15.0 mA

OL

= 2.0 mA

I

OL

I

= 3.5 mA

OL

I

= 5.0 mA

OL

0.2

0.4

0.7

0.2

0.4

0.7
+ 0.3 V

DDP

V

Input Low Voltage –0.3 .7 V
Input Current

Input Current
Quiescent Supply Current VIN = V
3-State Output Leakage Current VOH = VSS or V

with pull-up
without pull-up

†

or V

SS

DDL

DDL

–20
–10

–100

10

µA

µA

1.0 10 mA

–10 +10 µA

Output Short Circuit Current High

High Drive
Low Drive

–120
–100

mA

Output Short Circuit Current Low

High Drive
Low Drive

100

30

mA

I/O Pad Capacitance 8pF
Clock Input Pad Capacitance 8 pF

Notes: All process conditions. Junction Temperature: –40 to +110°C.

† No pull-up resistor.

16

ProASIC™ 500K Family

DC Electrical Specifications (V

= 3.3V)

DDP

Symbol Parameter Conditions Min. Typ. Max. Units

V

DDP

V

DDL

V

OH

V

OL

V

IH

V

IL

I

IN

I

DDQ

Supply V oltage 3.0 3.6 V
Supply Voltage, Logic Array 2.3 2.7 V
Output High Voltage

3.3V I/O, High Drive

3.3V I/O, Low Drive

2.5V I/O, High Drive

2.5V I/O, Low Drive

= –3.0 mA

I

OH

I

= –5.0 mA

OH

I

= –10.0 mA

OH

= –2.0 mA

I

OH

I

= –3.0 mA

OH

I

= –6.0 mA

OH

= –0.5 mA

I

OH

I

= –1.0 mA

OH

I

= –2.0 mA

OH

= –0.5 mA

I

OH

I

= –1.0 mA

OH

I

= –2.0 mA

OH

V

DDP

0.9

V

DDP

0.9

– 0.2

* VDDP

2.4
– 0.2

* VDDP

2.4

2.1

2.0

1.7

2.1

2.0

1.7

Output Low Voltage

3.3V I/O, High Drive

3.3V I/O, Low Drive

2.5V I/O, High Drive

2.5V I/O, Low Drive

= 7.5 mA

I

OL

I

= 12.0 mA

OL

I

= 15.0 mA

OL

= 2.5 mA

I

OL

I

= 4.0 mA

OL

I

= 5.0 mA

OL

= 7.5 mA

I

OL

I

= 15.0 mA

OL

I

= 24.0 mA

OL

= 2.5 mA

I

OL

I

= 5.0 mA

OL

I

= 8.0 mA

OL

0.1

0.1

0.2

* VDDP

0.4

0.2

* VDDP

0.4

0.2

0.4

0.7

0.2

0.4

0.7

Input High Voltage

LVTTL/LVCMOS

2.5V Mode

2

1.7

V
V

DDP
DDP

+ 0.3
+ 0.3

Input Low Voltage

LVTTL/LVCMOS

2.5V Mode

–0.3
–0.3

0.8

0.7

Input Current

LVTTL/LVCMOS
LVTTL/LVCMOS

Quiescent Supply Current VIN = V

with pull-up
without pull-up

†

or V

SS

DD

–40
–10

–200

10

µA
µA

1.0 10 mA

V

V

V

V

V

V

Notes: Refer to PCI Specifications Revision 2.2. for 3.3V high drive, high slew-rate output pads, and all 3.3V input/clock pads.

† No pull-up resistor.

17

DC Electrical Specifications (V

= 3.3V) (Continued)

DDP

Symbol Parameter Conditions Min. Typ. Max. Units

I

OZ

I

OSH

I

OSL

C
C

I/O
CLK

3-State Output Leakage Current VOH = V
Output Short Circuit Current High

3.3V I/O, High Drive

3.3V I/O, Low Drive

2.5V I/O, High Drive

2.5V I/O, Low Drive

Output Short Circuit Current Low

3.3V I/O, High Drive

3.3V I/O, Low Drive

2.5V I/O, High Drive

2.5V I/O, Low Drive
I/O Pad Capacitance 8pF
Clock Input Pad Capacitance 8 pF

SS

†

or V

DD

–10 +10 µA

–200

mA

–140
–100

–100

160

mA

50

160

50

Notes: Refer to PCI Specifications Revision 2.2. for 3.3V high drive, high slew-rate output pads, and all 3.3V input/clock pads.

† No pull-up resistor.

18