ACT CT2561-FP, CT2561 Datasheet
CT2561
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www.aeroflex.com
Bus Controller, Remote Terminal and BUS Monitor
FOR MIL-STD-1553B
Features
■ Second Source Compatible to the BUS-65610
■ 16MHz CT2565 Replacement
■ RTU implements all dual redundant mode codes
■ Selective mode code illegalization available
■ 16 bit microprocessor compatibility
■ BC checks status word for correct address and set flags
■ RTU illegal mode codes externally selectable
■ 16 bit µProcessor compatibility
■ DMA handshaking for subsystem message transfers
■ Continuous On-Line and Initiated Built-In-Test
■ MIL-PRF-38534 compliant circuits available
■ Packaging – Hermetic Metal
• 78 Pin, 2.1" x 1.87" x .25" Plug-In type package
CIRCUIT TECHNOLOGY
ISO
9001
I
• 82 Lead, 2.2" x 1.61" x .18" Flat package
General Description
The CT2561 is a 16 MHz single chip dual redundant MIL-STD-1553 Bus Controller (BC), Remote
Terminal Unit (RTU) and Bus Monitor (MT). Packaged in a hybrid plug-in or flatpack, the CT2561
performs all the functions required to interface a MIL-STD-1553 dual redundant serial data bus such
as ACT4487 and a subsystem parallel three-state data bus.
Using a single Aeroflex custom monolithic ASIC design, the CT2561 features pin-for-pin and
functional CT2565 compatibility, user initiated self-test, and low power consumption.
Compatible with most microprocessors the CT2561 provides a 16bit three-state parallel data bus
and uses direct memory access (DMA type) handshaking for subsystem transfers. All message
transfer timing, DMA and control lines are provided internally, thereby reducing the subsystem
overhead associated with message transfers.
The CT2561 implements all dual redundant MIL-STD-1553 mode codes. In addition, any mode
code may (Optionally) be legalized through the use of an external PROM. Complete error detection
is provided by the CT2561 for BC and RTU operation. Error detection includes: response time-out,
inter-message gaps, sync, parity, Manchester, word count and bit count.
The CT2561 is fully compliant with MIL-STD-1553, is available screened in accordance with the
requirements of MIL-STD-883 and operates over the full military temperature range of -55°C to
+125°C.
eroflex Circuit Technology – Data Bus Modules For The Future © SCDCT2561 REV A 8/16/99
Aeroflex Circuit Technology
SCDCT2561 REV A 8/16/99 Plainview NY (516) 694-6700
BUSGRNT
BUSREQ
SOM
BUSACK
INCMD
EOMOECS
WR
CHA/CHB
BCSTART
MSGERR
LOOPERR
LWORD
STATERR
STATEN
HSFAIL
NBGRNT
BITEN
NODT
ADRINC
BSCTRCV
TIMEOUT
I/O LOGIC
BUFFERS
BUFENA
I/O0 - I/O16
LMC
WC0-WC4
ILLCMD
T/R
SERREQ
DBACCEPT
SSBUSY
SSERR
SSFLAG
DATA
BUFFERS
REMOTE
TERMINAL
LOGIC
BUS
CONTROLLER
LOGIC
DATA BUS
STATUS INPUTS
MODE CODE CONTROL
CH B
CONTROL
CH A
ENCODE/
DECODE
CH B
ENCODE/
DECODE
TXDATA A
TXINH A
RXDATA A
RXDATA A
TXDATA A
RTADDR
PARITY
CHECKER
TXDATA B
TXINH B
RXDATA B
RXDATA B
TXDATA B
RTADDR
RTADDR
RTADR2
RTADR0
RTADR4
RTADR3
RTADR1
RTADRP
CONTROL BUS
Figure 1 – CT2561 Block Diagram
16MHz
MT
RT/BC
TESTOUT
TESTIN
CH A
CONTROL
I/O BUS
ENR/W
2
Aeroflex Circuit Technology
SCDCT2561 REV A 8/16/99 Plainview NY (516) 694-6700
Table 1A – Pin Function Table (78 Pin Plug-In)
Pin # Symbol I/O Description
1 RT/BC
2 MT
I Mode Select input - logic "1" for RT mode, logic “0” for BC mode.
I Monitor mode enable. When unit is operating as a BC, a logic “0” will select
monitor mode.
3 STATEN
O Output signal in RT mode that indicates status word is being transferred on the
internal bus.
4 TIMEOUT
O Indicates No Response Timeout has occurred during BC and RTU (RT to RT
transfer).
5 HSFAIL
O Output in RT mode indicating the DMA transfer did not occur in time to allow
proper operation on the 1553 bus.
6 DBACCEPT
I Input signal used to set DBACCEPT bit in status register for response to a valid
mode command on the 1553 bus.
7 SSFLAG
8 SVCREQ
9 INCMD
10 SSER
11 TESTOUT
I Input which controls the SSFLAG bit in the status register.
I Input which controls the service request bit in the status word.
O Output signal indicating the RT is currently in a message transfer sequence.
I Input which controls the subsystem error bit in the status register.
- Factory test point. Do not connect.
12 WC1 O WC bit 1 - latched output of command word.
13 WC3 O WC bit 3 - latched output of command word.
14 TXINH B O Transmitter inhibit output for channel B.
15 T/R
16 CHA
/CHB O Output indicating current selected channel (0 = Channel A).
17 CS
18 OE
19 BUSREQ
O Output indicating T/R bit of current command word in RT mode.
O Chip Select output for subsystem memory control.
O Output Enable output for subsystem memory control.
O Output signal used to initiate transfer to/from subsystem.
20 +5V I +5 Volt DC input.
21 DB0(LSB) I/O Least significant bit - 16 bit parallel data bus.
22 DB2 I/O Bit 2 of data bus.
23 DB4 I/O Bit 4 of data bus.
24 DB6 I/O Bit 6 of data bus.
25 DB8 I/O Bit 8 of data bus.
26 DB10 I/O Bit 10 of data bus.
27 DB12 I/O Bit 12 of data bus.
28 DB14 I/O Bit 14 of data bus.
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