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Acer
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VQ730
Schematic
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Acer AF705, VQ730 Schematic

AF705 VQ730
ACER Service Guide 17-inch CRT Monitor
1. DISPLAY ALIGNMENT
A. TIMING & DISPLAY SIZE
For all presetting mode shall be within the limitation:
H. WIDTH 310 ± 5mm
V. HEIGHT 232 ± 3 mm
The external control range of the data area, shall be as follows;
Max. horizontal size : full the screen
Max. vertical size : full the screen
B. PICTURE POSITION
For all presetting mode shall be within the limitation:
H.PHASE SCREEN CENTE ± 4 mm
V.CENTER SCREEN CENTE ± 3 mm
C. LINEARITY
The linearity of an image displayed on the CRT must meet the following requirements, with reference to figure
4.05 for both X and Y and axis.
The measured value of linearity shall be less than 6%(p) or 8%(s) when calculated using all lattices and shall be less than 5%(p) or 6%(s) when calculated using adjcent lattices.
Xmax-Xmin
OR Ymax-Ymin
Xmax+Xmin Ymax+Ymin
Where: Xmax,Xmin,be Calculated Same Line
Ymax,Ymin,be Calculated Same Row
D. ALIGNMENT PROCEDURE
●
Warm up the monitor for at least 30 minutes before adjustment.
● Set the front of CRT to the east.
●
Turn all VR set to center position.
D-1. H.V
1. Use front control key adjust the display size about 300mm, adjust VR801 Let the Plus of C824 is
28.14V in Timing 68kmode FULL WHITE PATTERN, it can be got a stable H.V.
E. GEOMETRIC DISTORTION
E-1 Raster Rotation Signal No.1 to 6
| a - b | ≤ 2.0 mm
E-2 Pincushion Signal No.1 to 6
Top : d1 ≤2.0 mm
Bottom : b1 ≤ 2.0 mm
Leftside : a1 ≤ 1.5 mm
Rightside : c1 ≤ 1.5 mm
E-3 Barrel Signal No.1 to 6
Top : d2 ≤ 2.0 mm
Bottom : b2 ≤ 2.0 mm
Leftside : a2 ≤1.0 mm
Rightside : c2 ≤ 1.0 mm
E-4 Trapezoid Signal No.1 to 6
Top : d ≤ 2.5 mm
Bottom : b ≤2.5 mm
Leftside : a ≤ 2.5 mm
Rightside : c ≤ 2.5 mm
E-5 . Parallelogram Signal No.1 to 6
a ≤ 0.5 degree
Bezel
a1
a2
b
a
d1
c1
b1
d2
b2
a
c
a
c2
d
b
E-6 Overall Distortion Signal No.6 only
Top : d ≤ 2.5 mm
Bottom : b ≤2.5 mm
Leftside : a ≤ 2.5 mm
Rightside : c ≤ 2.5 mm
d
b
a
c
F. WHITE BALANCE ALIGNMENT
F. 1. 1 Select timing #6 (VESA 68K 1024X768) with crosshatch pattern, adjust both horizontal and vertical
??
OSD’s size control to get display size within 310x232p±2mm.
F.1.2 Disconnect R.G.B. signal inputs, adjust OSD’s brightness and G1 control to it’s maximum position.
??
F.1.3 Auto alignment(P103 must be short) Use automatic alignment equipment and program to get color temperature within specified coordinates.
F.1.4 Manual alignment P103 must be short in order to into factory mode. Select OSD function to color temperature adjustment.
F.1.5 For 9300( 7500 ; 6500 ) color coordinate ( notes: set the minimum value of R.G.B. bias is 0, set the value of sub-contrast “SC” is 0 ).
F.1.6 Disable the video pattern( for a raster pattern ), set the maximum value of contrast and brightness is 255, adjust G1 to Y=0.01 cd/mm
F.1.7 Adjust bias G to get Y=1.8 ± 0.06 cd/mm
Adjust bias B to get y=297 ( y=315 for 7500 ; y=329 for 6500 ) ± 5
Adjust bias R to get x=283 ( x=295 for 7500 ; x=313 for 6500 ) ± 3
F.1.8 Fine tune the bias G and R for x=283 , y=297 ( x=299, y=315 for 7500; x=313, y=329 for 6500 ) ± 3.
F. 1. 9 Select 7500 and 6500 color coordinate separately. Repeat item 2.5.5 ~ 2.5.8 to meet specificity.
F.1.10 Adjust brightness control to get raster is <= 0.25cd/mm, change pattern to 2 inch square.
F.1.11 Enable G signal output of pattern generator, adjust gain G to get Y=98 ± 1 cd/mm
F.1.12 Enable B signal output, adjust gain B to get y=297 ( y=315 for 7500 ; y=329 for 6500 ) ± 2
Enable B signal output, adjust gain R to get x=283 ( x=299 for 7500 ; x=313 for 6500 )
F.1.13 Fine tune the gain G and R for x=283 , y=297
??
( x=299, y=315 for 7500; x=313, y=329, for 6500 )
F.1.14 Check 150 >Y> 130 cd/mm, if not , adjust G to get Y>130 cd/mm, then repeat item 2.5.12
F.1.15 Change pattern to fall white, adjust SB to get 92< Y <113 cd/mm .
F.1.16 Select 7500 and 6500 color coordinate separately. Repeat item 2.5.11 ~ 2.5.15 to meet specificity. 7500 X=300 Y=315 6500 X=313 Y=329
±
2
±
1
G. PRESET TIMING
Preset Timing Chart
[ H-SYNC ]
[ VIDEO ]
[ V-SYNC ]
[ VIDEO ]
Signal Name Clock
No
1 VGA
640*480(60)
2 VESA
800*600(85)
3 VESA
1024*768(85)
4 VESA
800*600(75)
5 VESA
1024*768(75)
6 VESA
1280*1024(60)
(MHz)
25.175 31.469 59.940
56.250 53.674 85.061
94.500 68.677 84.997
49.500 46.875 75.000
78.750 60.023 75.029
108.00 63.981 60.020
Ts h
Tsv
Fh
(kHz)
Fv
(Hz)
Tbh
Tbv
Th
(uSec)
(dot)
31.778 (800)
18.631 (1048)
14.561 (1376)
21.333 (1056)
16.66 (1312)
15.630 (1688)
Ts h
(uSec)
(dot)
3.813 (96)
1.138 (64)
1.016 (96)
1.616 (80)
1.219 (96)
1.037 (112)
Tfh
(uSec)
(dot)
0.636 (16)
1.138 (64)
0.508 (48)
0.323 (16)
0.203 (16)
0.444 (48)
Th
Tdh
Tv
(uSec)
1.907 (48)
2.702 (152)
2.201 (208)
3.232 (160)
2.235 (176)
2.296 (248)
Tdv
Tbh
(dot)
Tdh
(uSec)
(dot)
25.422 (640)
14.222 (800)
10.836 (1024)
16.162 (800)
13.003 (1024)
11. 85 2 (1280)
Tv
(mSec)
(line)
16.683 (525)
11. 75 6 (631)
11. 76 5 (808)
13.333 (625)
13.328 (800)
16.661 (1066)
Tsv
(mSec)
(line)
0.064 (2)
0.056 (3)
0.044 (3)
0.064 (3)
0.050 (3)
0.047 (3)
Tfh
Tfv
Tfv
(mSec)
(line)
0.318 (10)
0.019 (1)
0.015 (1)
0.021 (1)
0.017 (1)
0.016 (1)
Tbv
(mSec)
(line)
1.049 (33)
0.503 (27)
0.524 (36)
0.448 (21)
0.466 (28)
0.594 (38)
Tdv
(mSec)
(line)
15.253 (480)
11.179 (600)
11.183 (768)
12.800 (600)
12.795 (768)
16.005 (1024)
Hs Vs
- -
+ +
+ +
+ +
+ +
+ +
2. CONTROL AND CONNECT LAYOUT
A. Main PCB
B. VIDEO PCB
C. PIN ASSIGNMENT
C-1. Connect Table
P102 P105-P202 P104-P203
1 DETECT V-OUT AFC
2 DDC-SCL OSD-SDA GHD
3 DDC-SDA OSD-SCL G1
4 GND H-out HEATER
5 V-sync GND 5V
6 H-sync 80V
7 5V from PC 12V
8 ABL
9
10
C-2. Connect Function
P803 : H-CENTER CONN
P501 : TILT CONN
P103: PRESET CONN
P902 : DEGAUSSING COIL CONN
P804 : X-RAY TEST PAD
3. INTRODUCTION:
C708 is a 17” multisync color monitor. The horizontal frequency range is from 30khz to 70khz, and the refresh rate is from 50hz to 160hz. The circuit includes four major parts, the power supply circuit, the deflection circuit, the video circuit and the digital control circuit. is the function block diagram.
A. POWER SUPPLY
Transfer AC source to DC source that supply all the circuit power. It includes:
(1) +13.5V: For horizontal and vertical deflection circuit.
(2) –11.5V: For vertical deflection circuit.
(3) +7.2V: For CRT heater, parts of video pre-amp circuit.
(4) +53V: For B
(5) +80V: For video circuit
(6) 9.2V: for MIRCO- P
Fig 2 is the function block diagram of power CKT.
B. DEFLECTION:
Produce YOKE deflection current of horizontal and vertical, CRT H.V and bias that makes screen raster.
+
Boost circuit.
C. VIDEO:
amplify the video signal and add the signal to the cathode of CRT to produce video on the screen.
D. DIGITAL CONTROLLOR:
With the EEPROM and PROGRAM, the micro-processor (u-P) control all the picture performance.
From the key control, the user can change the H-size, V-size, V-center, H-phase.
R
13.5V
G
B
5V
5V
Power generator
-12V
9.2V 53V 80V
LM1269
Vid e o Pr e-A MP
OSD generator
UP WT62P1
EE-P-ROM
24C08
OSD DATA
NT6827
5V
12V
53V
LM2467
Video Output AMP.
12V 80V
13.5V
-12V
B+
generator
R,G,B out
Heater 6.3V
TDA8172
Vertical Output AMP.
B++16V
+
-
V-sawtooth
TDA4856
H.V Sync Processor
12V 12V
H-center
ADJ.
13.3V
CRT &
DY
ASSY.
V-s c a n to DY
H-Driver &
H-Scan Stage
G1 ADJ. Voltage generator
D/A Output
from uP
-145V
H.V. 25KV to CRT
Dynamic Focus to CRT
G2 Voltage 550V to CRT
FBT
H.V generator
B++16V
+
-
Fig2
4. POWER SUPPLY
A. RECTIFIER AND FILTER CKT:
The 90Vac-265Vac input line voltage is rectified by BD901, and smoothed by C906 to provide DC operating voltage for the circuit.
B. FLYBACK AND PWM CKT :
When power is initially applied to the circuit,C909 charges through R903, Q902.When the voltage across C909 reaches a level of 16V, U901 is enabled, turning on Q903 and turning off Q902 to complete start-up action.
During the On-time of Q901, energy is stored in T900. At this time the polarity of the output windings is such that all output rectifiers are reverse biased and no energy is transferred. Primary current is sensed by R907 and compared to a DC level that is determined by voltage feedback. When this level is reached, Q901 is turned off and the polarity of all T900 windings reverses , forward biasing the output rectifiers. All the energy stored is now transferred to the output capacitors. Many cycles of this store/release action are needed to charge the outputs to their respective voltages.
The voltage across C946 is fed through a voltage divider,R970, R971, R973, C975, R976, R977 and VR901 to the error amplifier U904 compared to an internal 2.5V reference, then determine the feed back level of U901 pin 1.
C. SNUBBER CKT:
Energy stored in the leakage inductance of T900 cause a voltage spike which be added to the normal reset voltage across T900 when Q901 turn off. The clamp consisting of D905, R904 and C907 limits this voltage excursion from exceeding the Vds rating of Q901.
D. SYNCHRONIZED CKT:
The oscillator frequency is defined by R919, C916. The equation is approximately: Fosc=1.8/ (R919*C916). The external signal “SYN+ & SYN−”
E. POWER SAVING CKT:
The monitor has ON and OFF states. The monitor enters OFF mode if H-sync and/or V-sync are removed. When in the OFF State, PS1 should below simultaneously to turn off +13.5Vs outputs. PS2 should enter PWM Pulse to pre- CRT- heater. In this state, input power should be less than 5W and LED-1 LED illuminate yellow.
F. DEGAUSS CKT:
The DEGUSS signal which comes from micro-p to control degauss coil act or not.
When DEGUSS is high, Q950 will be saturated to make RL901 working, AC line provides a degaussing current to degauss coil.
G. OVERLOAD PROTECTION CKT:
The primary current flows through the current sensing resistor R907.
The sensing voltage through the R907, R911, C914 to U901 pin3, If the current up, the U901 pin 3 voltage will be follow up, When the voltage>1 V, the U901 duty-cycle shall be limited, Made the output voltage down in the meanwhile make the U901 VCC the U901 pin 7 fall down under 10 voltage in the then, U901 stop action, made over load for protection.
voltage down,
5. DEFLECTION
A. SYNC RPOCESSOR:
H-sync & V-sync input to U1(up), then up output the H-out, V-out signal to U401 TDA4856. The H-out, V-out always are positive.
B. HORIZONTAL PROCESSOR
Fig 3 is the block diagram of IC TDA4856.
The IC TDA4856 output vertical sawtooth and H-Drive signal to produce, H.V deflection. Meanwhile TDA4856 output. BDRV signal (IC pin 6) that can control B
C. VERTICAL OUTPUT
Fig 4 is the block diagram of IC TDA8172.
Input vertical sawtooth signal from TDA4856 to TDA8172, then TDA8172 produce vertical deflection current.
D. HORIZONTAL OUTPUT STAGE
F<33K 33K<F<36K 36K<F<41K 41K<F<52K 52K<F<58K 58K<F<65K 65K<F
SW1 L L L H H H H
SW2 L H H L L H H
SW3 L L H L H L H
E. FLYBLACK TRANSFORMER
In the primary of F.B.T, there is about 1000Vpp in the LC resonant interval, It convert to the secondary of F.B.T to produce about 25.3KV for CRT anode voltage.
+
voltage.
Fig4
6. VIDEO AMP. CIRCUIT
A. VIDEO PRE. AMP.
The video pre-amp IC is U201(LM1269). The input signal is 0.7Vpp, then pre-amp IC U201 amplify the video signal to 3~4Vpp. The U201 is controlled by up via I block diagram.
B. VIDEO AMPLIFIER
The video amplifier is U203(LM2467), it amplify video signal to about 40Vpp. Video output signal add to cathode by AC coupling, Fig6 is the block diagram.. The DC bias is controlled by the IC U204(LM2480), Fig7 is the block diagram..
Fig 6 is the block diagram
2
C bus, Fig5 is the
Fig5
Fig6
Fig7
7. TROUBLESHOOTING
A. POWER SUPPLY CHECK
B. MONITOR CHECK FLOW CHART
B-1. No Raster
B-2. No Picture
B-3. No Vertical Deflection ( rester become a horizontal line)
A. FRU BOM
A-1 Main PCBA-- 456A6630011
A-2 Video PCBA—452A6030001
B. BOM LIST
The item of parts marked with yellow are recommended and Unique parts list, and items marked with Blue are top 20 failures provided by our PE if component level repair is required.
Li
Leve
ne
l
1 1 5224A830003
2 2 51A11830011 40.16 1 VIDEO ASSY
3 3 452A6030001 9.86 1 PCBA CRT/B
4 4 442A6030001 3.13 1 AIS CRT/B
5 5
6 5
7 5
8 5
9 5
10 5
11 5
12 5
13 5
14 5
15 5
16 5
17 5
18 5
19 5
20 5
21 5
22 5
23 5
24 5
25 5
26 5
27 5
Part
BC101SS82T 2 0.10 9 DIODE
BC11N4148T 8 0.02 1 DIODE
BC1FR1040T 0 0.04 1 DIODE
BC4HZ5C10 T8 0.05 1 ZENER DIODE
CA001A601T 8 0.03 13 CERAMIC CAP.
CA001D600T 2 0.02 2 CERAMIC CAP.
CA010CCM0 T6 0.04 7 CERAMIC CAP.
CA010DEK0 T0 0.04 1 CERAMIC CAP.
CA018ELK0 T0 0.07 1 CER CAP
CA022E601T 4 0.03 1 CERAMIC CAP.
CB0010AM0 T0 0.05 3 CAPACITOR (N.P.)
CB0100A43T 2 0.04 1 CAPACITOR
CB0220A42T 5 0.07 2 CAPACITOR
CB047A6M0 TH 0.03 1 CAPACITOR
CB10003M0T H 0.04 3 CAPACITOR
CC033AI71T 0 0.03 1 RES FUSE
CC0560111T 6 0.01 1 RESISTOR
CC0680011T 1 0.01 3 RESISTOR
CC0750211T 3 0.01 3 RESISTOR
CC0820211T 5 0.01 3 RESISTOR
CC1000111T 2 0.01 1 RESISTOR
CC1000211T 8 0.01 14 RESISTOR
CC1001011T 1 0.01 1 RESISTOR
Model
MF708C0200 3 150.66 1 DIS ABO
Unit Price
USD
Usage Description
Spec
MF708C MPRII 15"CP
MF708C MPRII
VQ-730 MC708 LG
VQ-730 MC708 LG
1SS82
1N4148
FR104 DO-41
HZ5C1
.1U 50V Z Y5V P5
100P 50V +-5% NPO
.01U 500V M Z5U P5
1000P 1KV K Y5P P5
180P 2KV K Y5P P5
220P 50V +-5% NPO
1U 100V M A P5
10U 100V +-20% 85C
22U 100V +-20% 85C
4.7U 50V M A P5
100U 16V M A P5
1/2W 3.3 +-5% S
1/4W 56 +-5%
1/2W 68 +-5%
1/8W 75 +-5%
1/8W 82 +-5%
1/4W 100 +-5%
1/8W 100 +-5%
1/2W 1K +-5%
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