Acer V3-471G Schematics

5

4

3

2

1

ZQT/ZQS/ZQW CRV SYSTEM BLOCK DIAGRAM

D D

eDP Con.

DDRIII-SODIMM1
DDRIII-SODIMM2

P23

P13, 14

INT._eDP

Dual Channel DDR III
1066/1333/1600 MHZ

eDP

IMC

IVY Bridge

rPGA 989

P3, 4, 5, 6

GFX

FDI

DMI

PEG
TX/RX

DMI(x4)

FDI

CLK

C C

SATA - HDD

SATA - ODD

P26

P26

SATA 0

SATA

SATA 5

Cougar Point

DMI

Display

USB3.0/2.0

Panther Point

G-Sensor

Small Board
CONNECTOR

P31

B B

Bluetooth Con.

P26

P31

USB2-1& 9

USB2-4

Azalia

P8

BATTERY

SMBUS

USB2.0

RTC

IHDA

PCH

P7, 8, 9, 10, 11, 12

LPC

PCI-E x1

PCI-E x1

SPI

CLK

DIS._eDP

INT_LVDS

INT_CRT

INT_HDMI

USB3-3/USB2-2

X'TAL

32.768KHz

X'TAL 25MHz

SPI ROM

eDP

N13P-GL/GS/GT
/N13M-GS

Display

USB Charger

P8

P23

DIS._HDMI
DIS._CRT
DIS._LVDS

P31

PCIE-1
USB-3

PCIE-8
USB-10

PCIE-3

VRAM

P13, 14

Int. MIC

USB-8

USB3 Port
MB side

MINI-SSD

MINI CARD
WLAN

RTL8411

10/100/1G

Cardreader

P31

P25

P25

P29

LVDS/CCD/MIC
Con.

CRT Con.

HDMI Con.

RJ45

Cardreader
CONN.

P23

P23

P24

P29

P30

Int. MIC

A A

5

ALC271X-VB6

AUDIO CODEC

MIC JACK

P28

HP

P28

P28

Speaker

P28

4

K/B Con.

P33

EM-6781-T3

HALL SENSOR

EC

WPCE885

P23

Touch Pad
Board Con.

P26

X'TAL

P34

Fan Driver

(PWM Type)

3

32.768KHz

P33

bq24707A

Batery Charger

RT8223P

3V/5V

TPS51650

CPU core/VAXG

TPS51219

+1.05V_PCH / +1.05V_VTT

2

TPS51216

+1.5V_SUS

P35

RT8241A

VCCSA

36

TPS51728

VGPU Core

P37

MP2139DD

+1.5V_GFX/1.05V_GFX/3V_GFX

P38

Discharger

P39

Thermal Protection

P40

P41

P42

P43

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

PROJECT :

Block Diagram

Block Diagram

Block Diagram

1

ZQS 45W

ZQS 45W

ZQS 45W

1 46Wednesday, February 08, 2012

1 46Wednesday, February 08, 2012

1 46Wednesday, February 08, 2012

3C

3C

3C

1

2

VGA power up sequence

3

4

5

6

7

8

EC

A A

+3V

dGPU_RWR_EN

VIN

dGPU_VRON

MOSFET

PWM

+3V_GFX

+VGACORE

VGA_PG

+1.5VSUS

+1.5V_GFXMOSFET

+1.05V

MOSFET

+1.05V_GFX

DGPU_PWROK

VGA_VID

VGA_PG

B B

+1.8V

+1.8V_GFXMOSFET

Power States

POWER PLANE

VIN
+3V_RTC
+3VPCU
+5VPCU
+15V
+3V_S5

C C

D D

+5V_S5
+5V

+1.5VSUS
+0.75V_DDR_VTT
+VGFX_AXG S0VRONInternal GPU POWER
+1.8V
+1.5V
+1.05V
+VCCSA HWPG_VTT+0.9V
+VCC_CORE
LCDVCC

VOLTAGE

+10V~+19V
+3V~+3.3V
+3.3V
+5V
+15V
+3.3V
+5V
+5V
+3.3V
+1.5V
+0.75V
variation
+1.8V
+1.5V
+1.05V

variation
+3.3V

DESCRIPTION

RTC POWER
EC POWER
CHARGE POWER
CHARGE PUMP POWER
LAN/BT/CIR POWER
USB POWER
HDD/ODD/Codec/TP/CRT/HDMI POWER
PCH/GPU/Peripheral component POWER+3V
CPU/SODIMM CORE POWER
SODIMM Termination POWER

CPU/PCH/Braidwood POWER
MINI CARD/NEW CARD POWER
PCH CORE POWER/IVY/SNB bridge VCCIO MAINON

CPU CORE POWER
LCD POWER

CONTROL
SIGNAL

ALWAYSMAIN POWER
ALWAYS
ALWAYS
ALWAYS

S5_ON
S5_ON
MAINON
MAINON
SUSON
MAINON

MAINON
MAINON

VRON
LVDS_VDDEN
MAINON S0

ACTIVE IN

ALWAYS
ALWAYS
ALWAYS
ALWAYS
ALWAYSALWAYS
S0-S5
S0-S5
S0
S0
S0-S3
S0

S0
S0
S0
S0CPU POWER
S0
S0

Thermal Follow Chart

CPU
CORE PWR

H_ORICHOT#

H/W Throttling

NTC
Thermal
Protection

CPU

PCH

SM-Bus

EC

PM_THRMTRIP#

SML1ALERT#

CPUFAN#

WIRE-AND

SYS_SHDN#

3V/5 V
SYS PWR

FANFAN Driver

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

PWR Status & GPU PWR CRL & THRM

PWR Status & GPU PWR CRL & THRM

PWR Status & GPU PWR CRL & THRM

Date: Sheet of

Date: Sheet of

1

2

3

4

5

6

Date: Sheet of

7

PROJECT :

ZQS 45W

ZQS 45W

ZQS 45W

2 46Wednesday, February 08, 2012

2 46Wednesday, February 08, 2012

2 46Wednesday, February 08, 2012

8

3C

3C

3C

5

4

3

2

1

03

For Sandy Bridge processor only implementation:
PROC_SELECT can be left NC.

IVY Bridge Processor (DMI,PEG,FDI)

DMI_TXN07
DMI_TXN17

D D

DMI_TXN27
DMI_TXN37

DMI_TXP07
DMI_TXP17
DMI_TXP27
DMI_TXP37

DMI_RXN07
DMI_RXN17
DMI_RXN27
DMI_RXN37

DMI_RXP07
DMI_RXP17
DMI_RXP27
DMI_RXP37

FDI_TXN07
FDI_TXN17
FDI_TXN27
FDI_TXN37
FDI_TXN47
FDI_TXN57
FDI_TXN67
FDI_TXN77

FDI_TXP07
FDI_TXP17
FDI_TXP27
FDI_TXP37
FDI_TXP47
FDI_TXP57

C C

FDI_TXP67
FDI_TXP77

FDI_FSYNC07
FDI_FSYNC17

FDI_INT7

FDI_LSYNC07
FDI_LSYNC17

eDP_COMP

INT_eDP_HPD_Q23

EDP-AUX+23
EDP-AUX-23

EDP-ML0+23

EDP-ML0-23

B B

TP107TP107
TP104TP104
TP109TP109

TP106TP106
TP105TP105
TP108TP108

HPD disable

This signal can be left as no
connect if entire eDP interface
is disabled.

U15A

U15A

B27

DMI_RX#[0]

B25

DMI_RX#[1]

A25

DMI_RX#[2]

B24

DMI_RX#[3]

B28

DMI_RX[0]

B26

DMI_RX[1]

A24

DMI_RX[2]

B23

DMI_RX[3]

G21

DMI_TX#[0]

E22

DMI_TX#[1]

F21

DMI_TX#[2]

D21

DMI_TX#[3]

G22

DMI_TX[0]

D22

DMI_TX[1]

F20

DMI_TX[2]

C21

DMI_TX[3]

A21

FDI0_TX#[0]

H19

FDI0_TX#[1]

E19

FDI0_TX#[2]

F18

FDI0_TX#[3]

B21

FDI1_TX#[0]

C20

FDI1_TX#[1]

D18

FDI1_TX#[2]

E17

FDI1_TX#[3]

A22

FDI0_TX[0]

G19

FDI0_TX[1]

E20

FDI0_TX[2]

G18

FDI0_TX[3]

B20

FDI1_TX[0]

C19

FDI1_TX[1]

D19

FDI1_TX[2]

F17

FDI1_TX[3]

J18

FDI0_FSYNC

J17

FDI1_FSYNC

H20

FDI_INT

J19

FDI0_LSYNC

H17

FDI1_LSYNC

A18

eDP_COMPIO

A17

eDP_ICOMPO

B16

eDP_HPD

C15

eDP_AUX

D15

eDP_AUX#

C17

eDP_TX[0]

F16

eDP_TX[1]

C16

eDP_TX[2]

G15

eDP_TX[3]

C18

eDP_TX#[0]

E16

eDP_TX#[1]

D16

eDP_TX#[2]

F15

eDP_TX#[3]

Ivy Bridge_rPGA_2DPC_Rev0p61

Ivy Bridge_rPGA_2DPC_Rev0p61

PEG_COMP

J22

PEG_ICOMPI

J21

PEG_ICOMPO

H22

PEG_RCOMPO

K33

PEG_RX#[0]

M35

PEG_RX#[1]

L34

PEG_RX#[2]

J35

PEG_RX#[3]

J32

PEG_RX#[4]

H34

PEG_RX#[5]

H31

PEG_RX#[6]

DMI

DMI

Intel(R) FDI

Intel(R) FDI

PCI EXPRESS* - GRAPHICS

PCI EXPRESS* - GRAPHICS

eDP

eDP

G33

PEG_RX#[7]

G30

PEG_RX#[8]

F35

PEG_RX#[9]

E34

PEG_RX#[10]

E32

PEG_RX#[11]

D33

PEG_RX#[12]

D31

PEG_RX#[13]

B33

PEG_RX#[14]

C32

PEG_RX#[15]

J33

PEG_RX[0 ]

L35

PEG_RX[1 ]

K34

PEG_RX[2 ]

H35

PEG_RX[3 ]

H32

PEG_RX[4 ]

G34

PEG_RX[5 ]

G31

PEG_RX[6 ]

F33

PEG_RX[7 ]

F30

PEG_RX[8 ]

E35

PEG_RX[9 ]

E33

PEG_RX[1 0]

F32

PEG_RX[1 1]

D34

PEG_RX[1 2]

E31

PEG_RX[1 3]

C33

PEG_RX[1 4]

B32

PEG_RX[1 5]

M29

PEG_TX#[0 ]

M32

PEG_TX#[1 ]

M31

PEG_TX#[2 ]

L32

PEG_TX#[3 ]

L29

PEG_TX#[4 ]

K31

PEG_TX#[5 ]

K28

PEG_TX#[6 ]

J30

PEG_TX#[7 ]

J28

PEG_TX#[8 ]

H29

PEG_TX#[9 ]

G27

PEG_TX#[1 0]

E29

PEG_TX#[1 1]

F27

PEG_TX#[1 2]

D28

PEG_TX#[1 3]

F26

PEG_TX#[1 4]

E25

PEG_TX#[1 5]

M28

PEG_TX[0]

M33

PEG_TX[1]

M30

PEG_TX[2]

L31

PEG_TX[3]

L28

PEG_TX[4]

K30

PEG_TX[5]

K27

PEG_TX[6]

J29

PEG_TX[7]

J27

PEG_TX[8]

H28

PEG_TX[9]

G28

PEG_TX[10 ]

E28

PEG_TX[11 ]

F28

PEG_TX[12 ]

D27

PEG_TX[13 ]

E26

PEG_TX[14 ]

D25

PEG_TX[15 ]

DG 1.0 :
The recommended AC cap value is changed to 220nF for compatibility with
PCIe Gen3 on future platforms.
For Gen2 only designs, it is acceptable to continue to use the 100nF capacitor.

PEG_COMP connect to PIN H22&J22 W:4mils/S:15mils/L: 500mils.
PEG_COMP connect to PIN J21 W:12mils/S:15mils/L: 500mils.

PEG_RX#0 16
PEG_RX#1 16
PEG_RX#2 16
PEG_RX#3 16
PEG_RX#4 16
PEG_RX#5 16
PEG_RX#6 16
PEG_RX#7 16
PEG_RX#8 16
PEG_RX#9 16
PEG_RX#10 16
PEG_RX#11 16
PEG_RX#12 16
PEG_RX#13 16
PEG_RX#14 16
PEG_RX#15 16

PEG_RX0 16
PEG_RX1 16
PEG_RX2 16
PEG_RX3 16
PEG_RX4 16
PEG_RX5 16
PEG_RX6 16
PEG_RX7 16
PEG_RX8 16
PEG_RX9 16
PEG_RX10 16
PEG_RX11 16
PEG_RX12 16
PEG_RX13 16
PEG_RX14 16
PEG_RX15 16

R_PEG_TX#0

C411 EOP@0.22u/10V_4C411 EOP@0.22u/10V_4

R_PEG_TX#1

C414 EOP@0.22u/10V_4C414 EOP@0.22u/10V_4

R_PEG_TX#2

C416 EOP@0.22u/10V_4C416 EOP@0.22u/10V_4

R_PEG_TX#3

C419 EOP@0.22u/10V_4C419 EOP@0.22u/10V_4

R_PEG_TX#4

C421 EOP@0.22u/10V_4C421 EOP@0.22u/10V_4

R_PEG_TX#5

C425 EOP@0.22u/10V_4C425 EOP@0.22u/10V_4

R_PEG_TX#6

C426 EOP@0.22u/10V_4C426 EOP@0.22u/10V_4

R_PEG_TX#7

C430 EOP@0.22u/10V_4C430 EOP@0.22u/10V_4

R_PEG_TX#8

C435 EOP@0.22u/10V_4C435 EOP@0.22u/10V_4

R_PEG_TX#9

C438 EOP@0.22u/10V_4C438 EOP@0.22u/10V_4

R_PEG_TX#10

C440 EOP@0.22u/10V_4C440 EOP@0.22u/10V_4

R_PEG_TX#11

C444 EOP@0.22u/10V_4C444 EOP@0.22u/10V_4

R_PEG_TX#12

C446 EOP@0.22u/10V_4C446 EOP@0.22u/10V_4

R_PEG_TX#13

C448 EOP@0.22u/10V_4C448 EOP@0.22u/10V_4

R_PEG_TX#14

C451 EOP@0.22u/10V_4C451 EOP@0.22u/10V_4

R_PEG_TX#15

C452 EOP@0.22u/10V_4C452 EOP@0.22u/10V_4

R_PEG_TX0

C412 EOP@0.22u/10V_4C412 EOP@0.22u/10V_4

R_PEG_TX1

C415 EOP@0.22u/10V_4C415 EOP@0.22u/10V_4

R_PEG_TX2

C418 EOP@0.22u/10V_4C418 EOP@0.22u/10V_4

R_PEG_TX3

C420 EOP@0.22u/10V_4C420 EOP@0.22u/10V_4

R_PEG_TX4

C422 EOP@0.22u/10V_4C422 EOP@0.22u/10V_4

R_PEG_TX5

C424 EOP@0.22u/10V_4C424 EOP@0.22u/10V_4

R_PEG_TX6

C428 EOP@0.22u/10V_4C428 EOP@0.22u/10V_4

R_PEG_TX7

C432 EOP@0.22u/10V_4C432 EOP@0.22u/10V_4

R_PEG_TX8

C433 EOP@0.22u/10V_4C433 EOP@0.22u/10V_4

R_PEG_TX9

C436 EOP@0.22u/10V_4C436 EOP@0.22u/10V_4

R_PEG_TX10

C441 EOP@0.22u/10V_4C441 EOP@0.22u/10V_4

R_PEG_TX11

C442 EOP@0.22u/10V_4C442 EOP@0.22u/10V_4

R_PEG_TX12

C447 EOP@0.22u/10V_4C447 EOP@0.22u/10V_4

R_PEG_TX13

C449 EOP@0.22u/10V_4C449 EOP@0.22u/10V_4

R_PEG_TX14

C450 EOP@0.22u/10V_4C450 EOP@0.22u/10V_4

R_PEG_TX15

C455 EOP@0.22u/10V_4C455 EOP@0.22u/10V_4

N13P-GS--->Gen2

For IVY/Sandy processor compatibility:
Needs a pull-up resistor to PCH VccDFTERM rail (1.8V) through a 2.2 K±5% pull-up resistor.
Connect to the DF_TVS of PCH though a 1K±5% series resistor.

H_SNB_IVB#8

EC_PECI34

H_PROCHOT#

PM_THRMTRIP#10

PM_SYNC7

H_PWRGOOD10

PM_DRAM_PWRGD_R15

R103 75_4R103 75_4

CPU_PLTRST#

DIS.VGA-->EV@ + EOP@
Optimize-->IOP@ + EOP@
UMA-->IV@ + IOP@
Special-->SP@

PEG_TX#0 16
PEG_TX#1 16
PEG_TX#2 16
PEG_TX#3 16
PEG_TX#4 16
PEG_TX#5 16
PEG_TX#6 16
PEG_TX#7 16
PEG_TX#8 16
PEG_TX#9 16
PEG_TX#10 16
PEG_TX#11 16
PEG_TX#12 16
PEG_TX#13 16
PEG_TX#14 16
PEG_TX#15 16

PEG_TX0 16
PEG_TX1 16
PEG_TX2 16
PEG_TX3 16
PEG_TX4 16
PEG_TX5 16
PEG_TX6 16
PEG_TX7 16
PEG_TX8 16
PEG_TX9 16
PEG_TX10 16
PEG_TX11 16
PEG_TX12 16
PEG_TX13 16
PEG_TX14 16
PEG_TX15 16

H_PROCHOT#34,37

Intel recommended UNCOREPWRGOOD
routing on one layer

apply C5205 for nosie

+1.05V

PCI_PLTRST#9

IVY Bridge Processor (CLK,MISC,JTAG)

U15B

U15B

SKTOCC#

TP16TP16

TP_CATERR#

TP15TP15

H_PROCHOT#_R

PM_THRMTRIP#

PM_SYNC_R

H_PWRGOOD_R

R107 10K_4R107 10K_4

U4

U4

1

VCC5NC

2

IN
GND3OUT

74LVC1G07GW

74LVC1G07GW

PROC_SELECT#

CPU_PLTRST#_R

R106

R106
*750/F_4

*750/F_4

CPU_PLTRST#

4

C26

PROC_SEL ECT#

AN34

SKTOCC#

AL33

CATERR#

AN33

PECI

AL32

PROCHOT#

AN32

THERMTRIP#

AM34

PM_SYNC

AP33

UNCOREPW RGOOD

V8

SM_DRAMPW ROK

AR33

RESET#

Ivy Bridge_rPGA_2DPC_Rev0p61

Ivy Bridge_rPGA_2DPC_Rev0p61

+3V

C156

C156

0.1u/10V_4

0.1u/10V_4

MISCTHERMALPWR MANAGEMENT

MISCTHERMALPWR MANAGEMENT

CRB 1.0 : change to +3V(S0)

CLOCKS

CLOCKS

DDR3

MISC

DDR3

MISC

JTAG & BPM

JTAG & BPM

R398 *SHORT_4R398 *SHORT_4

R101 56_4R101 56_4

R81 *SHORT_4R81 *SHORT_4

C155 0.1u/10V_4C155 0.1u/10V_4

R102 *SHORT_4R102 *SHORT_4

R105 43_4R105 43_4

R104 *1.5K/F_4R104 *1.5K/F_4

BCLK

BCLK#

DPLL_REF_CLK

DPLL_REF_CLK#

SM_DRAMRST#

SM_RCOMP[0 ]
SM_RCOMP[1 ]
SM_RCOMP[2 ]

PRDY#

PREQ#

TRST#

DBR#

BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]

iGPU wo eDP and dGPU
Connect DPLL_REF_SSCLK on Processor to GND through 1K ± 5% resistor.
Connect DPLL_REF_SSCLK# on Processor to VCCP through 1K ± 5% resistor

CLK_CPU_BCLKP_R

A28

CLK_CPU_BCLKN_R

A27

CLK_DPLL_SSCLKP_R

A16

CLK_DPLL_SSCLKN_R

A15

CPU_DRAMRST#

R8

SM_RCOMP_0

AK1

SM_RCOMP_1

A5

SM_RCOMP_2

A4

CRB 1.0 : SM_RCOMP[2..0] W:20mils, S:15mils, L 500mils

XDP_PRDY#

AP29

XDP_PREQ#

AP27

XDP_TCLK

AR26

TCK

PCH_JTAG_TMS

AR27

TMS

XDP_TRST#

AP30

PCH_JTAG_TDI

AR28

TDI

PCH_JTAG_TDO

AP26

TDO

AL35

XDP_BPM0

AT28

XDP_BPM1

AR29

XDP_BPM2

AR30

XDP_BPM3

AT30

XDP_BPM4

AP32

XDP_BPM5

AR31

XDP_BPM6

AT31

XDP_BPM7

AR32

Rb

R414 EV@1K_4R414 EV@1K_4

Rc

R410 EV@1K_4R410 EV@1K_4

R460 140/F_4R460 140/F_4
R437 25.5./F_4R437 25.5./F_4
R438 200/F_4R438 200/F_4

4

3

2

1

R401 0_4P2RR401 0_4P2R

Ra

4

3

2

1

R412 IOP@0_4P2RR412 IOP@0_4P2R

CPU_DRAMRST# 15

TP25TP25
TP27TP27

TP29TP29
TP28TP28
TP20TP20

TP26TP26

XDP_DBRST# 7

TP102TP102
TP101TP101
TP97TP97
TP99TP99

For XDP

TP19TP19
TP22TP22
TP96TP96
TP95TP95

+1.05V

CLK_CPU_BCLKP 9
CLK_CPU_BCLKN 9

CLK_DPLL_SSCLKP 9
CLK_DPLL_SSCLKN 9

EV UMA/OPT.

Ra

NA1K0 ohm

Rb

1K

Rc

NA
NA

FDI Disabling (Discrete Only)

Reserve FDI Disabling (Discrete Only), add

C29

R665,R666,R667,R668,R669. 1/13

1/13 add

FDI_INT

R665 EV@0_4R665 EV@0_4
R668 EV@0_4R668 EV@0_4

R667

R667
EV@1K/F_4

EV@1K/F_4

R669 EV@0_4R669 EV@0_4

R666

R666
EV@1K/F_4

EV@1K/F_4

A A

FDI_FSYNC0
FDI_FSYNC1
FDI_LSYNC0
FDI_LSYNC1

FDI_FSYNC can gang
all these 4
signals together
and tie them with
only one 1K
resistor to GND
(DG V0.5 Ch2.2.9).

5

DP & PEG Compensation

+1.05V

Routed within 25 mils

R411 24.9/F_4R411 24.9/F_4

eDP_COMPIO and ICOMPO signals should
be shorted near balls and routed with
typical impedance <25 mohms

eDP_COMP

+1.05V

Routed within 500 mils

R409 24.9/F_4R409 24.9/F_4

PEG_ICOMPI and RCOMPO signals should
be routed within 500 mils
typical impedance = 43 mohms

PEG_ICOMPO signals should
be routed within 500 mils
typical impedance = 14.5 mohms

4

PEG_COMP

Processor pull-up(CPU)

H_PROCHOT#
PCH_JTAG_TDO

PCH_JTAG_TMS
PCH_JTAG_TDI
XDP_PREQ#
XDP_TCLK
XDP_TRST#

R98 62_4R98 62_4

R118 51_4R118 51_4
R119 51_4R119 51_4
R115 51_4R115 51_4
R114 *51_4R114 *51_4
R121 51_4R121 51_4
R111 51_4R111 51_4

+1.05V

3

PM_THRMTRIP#

2

1 3

IMVP_PWRGD7,37

+1.05V

3

Q8
FDV301NQ8FDV301N

1

R93

R93
1K_4

1K_4

2

Q7
MMBT3904Q7MMBT3904

2

SYS_SHDN# 19,36,43

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Wednesday, February 08, 2012

Date: Sheet of

Wednesday, February 08, 2012

Date: Sheet of

Wednesday, February 08, 2012

+1.05V5,7,8,9,11,23,34,37,38,42,43,46

+3V7,8,9,10,11,13,14,16,20,23,24,25,26,27,29,33,34,36,37,38,39,40,41,42,43,45,46

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

IVY Bridge 1/4

IVY Bridge 1/4

IVY Bridge 1/4

1

ZQS 45W

ZQS 45W

ZQS 45W

3 46

3 46

3 46

3C

3C

3C

5

4

3

2

1

IVY Bridge Processor (DDR3)

U15C

U15C

M_A_DQ[63:0]13

D D

C C

B B

M_A_BS#013
M_A_BS#113
M_A_BS#213

M_A_CAS#13
M_A_RAS#13
M_A_WE#13

M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63

G10

N10

M10

AG6
AG5
AK6
AK5
AH5
AH6

AK8
AK9

AH8
AH9
AL9
AL8

AP11

AN11

AL12
AM12
AM11

AL11
AP12
AN12

AJ14
AH14

AL15
AK15

AL14
AK14

AJ15
AH15

AE10

AF10

AE8
AD9
AF9

F10

AJ5
AJ6
AJ8

AJ9

C5
D5
D3
D2
D6
C6
C2
C3

F8

G9

F9

F7
G8
G7

K4

K5

K1

K2
M8

N8

N7
M9

N9
M7

V6

J1
J5
J4
J2

SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]

SA_BS[0]
SA_BS[1]
SA_BS[2]

SA_CAS#
SA_RAS#
SA_WE#

DDR SYSTEM MEMORY A

DDR SYSTEM MEMORY A

SA_CLK[0]

SA_CLK#[0]

SA_CKE[0]

SA_CLK[1]

SA_CLK#[1]

SA_CKE[1]

SA_CLK[2]

SA_CLK#[2]

SA_CKE[2]

SA_CLK[3]

SA_CLK#[3]

SA_CKE[3]

SA_CS#[0]
SA_CS#[1]
SA_CS#[2]
SA_CS#[3]

SA_ODT[0]
SA_ODT[1]
SA_ODT[2]
SA_ODT[3]

SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]

SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]

SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]

SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]

AB6
AA6
V9

AA5
AB5
V10

AB4
AA4
W9

AB3
AA3
W10

AK3
AL3
AG1
AH1

AH3
AG3
AG2
AH2

C4
G6
J3
M6
AL6
AM8
AR12
AM15

D4
F6
K3
N6
AL5
AM9
AR11
AM14

AD10
W1
W2
W7
V3
V2
W3
W6
V1
W5
AD8
V4
W4
AF8
V5
V7

M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7

M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15

M_A_CLK0 13
M_A_CLK0# 13
M_A_CKE0 13

M_A_CLK1 13
M_A_CLK1# 13
M_A_CKE1 13

M_A_CS#0 13
M_A_CS#1 13

M_A_ODT0 13
M_A_ODT1 13

M_A_DQS#[7:0] 13

M_A_DQS[7:0] 13

M_A_A[15:0] 13

M_B_DQ[63:0]14

M_B_BS#014
M_B_BS#114
M_B_BS#214

M_B_CAS#14
M_B_RAS#14
M_B_WE#14

M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63

D10

K10

AM5
AM6
AR3

AP3
AN3
AN2
AN1

AP2

AP5
AN9

AT5

AT6

AP6
AN8
AR6
AR5
AR9

AJ11

AT8

AT9

AH11

AR8

AJ12
AH12
AT11
AN14
AR14
AT14
AT12
AN15
AR15
AT15

AA9
AA7

AA10

AB8
AB9

C9

C8

D9
D8
G4

G1
G5

G2

J10

M5
N4
N2
N1
M4
N5
M2
M1

R6

A7

A9
A8

F4
F1

F5
F2

J7
J8

K9

J9

K8
K7

U15D

U15D

SB_DQ[0]
SB_DQ[1]
SB_DQ[2]
SB_DQ[3]
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]

SB_BS[0]
SB_BS[1]
SB_BS[2]

SB_CAS#
SB_RAS#
SB_WE#

AE2

SB_CLK[0]

AD2

SB_CLK#[0]

R9

SB_CKE[0]

AE1

SB_CLK[1]

AD1

SB_CLK#[1]

R10

SB_CKE[1]

AB2

SB_CLK[2]

AA2

SB_CLK#[2]

T9

SB_CKE[2]

AA1

SB_CLK[3]

AB1

SB_CLK#[3]

T10

SB_CKE[3]

AD3

SB_CS#[0]

AE3

SB_CS#[1]

AD6

SB_CS#[2]

AE6

SB_CS#[3]

AE4

SB_ODT[0]

AD4

SB_ODT[1]

AD5

SB_ODT[2]

AE5

SB_ODT[3]

M_B_DQS#0

D7

SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]

SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]

DDR SYSTEM MEMORY B

DDR SYSTEM MEMORY B

SB_DQS[7]

SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]

SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]

F3
K6
N3
AN5
AP9
AK12
AP15

C7
G3
J6
M3
AN6
AP8
AK11
AP14

AA8
T7
R7
T6
T2
T4
T3
R2
T5
R3
AB7
R1
T1
AB10
R5
R4

M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7

M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7

M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15

M_B_CLK0 14
M_B_CLK0# 14
M_B_CKE0 14

M_B_CLK1 14
M_B_CLK1# 14
M_B_CKE1 14

M_B_CS#0 14
M_B_CS#1 14

M_B_ODT0 14
M_B_ODT1 14

04

M_B_DQS#[7:0] 14

M_B_DQS[7:0] 14

M_B_A[15:0] 14

Ivy Bridge_rPGA_2DPC_Rev0p61

Ivy Bridge_rPGA_2DPC_Rev0p61

A A

5

4

3

Ivy Bridge_rPGA_2DPC_Rev0p61

Ivy Bridge_rPGA_2DPC_Rev0p61

2

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Wednesday, February 08, 2012

Date: Sheet of

Wednesday, February 08, 2012

Date: Sheet of

Wednesday, February 08, 2012

PROJECT :

IVY Bridge 2/4

IVY Bridge 2/4

IVY Bridge 2/4

ZQS 45W

ZQS 45W

ZQS 45W

1

4 46

4 46

4 46

3C

3C

3C

+

+

C510

C510
22u/6.3V_8

22u/6.3V_8

C178

C178

*22u/6.3V_8

*22u/6.3V_8

C176

C176
10u/6.3V_8

10u/6.3V_8

C498

C498
10u/6.3V_8

10u/6.3V_8

C146

C146
*10u/6.3V_8

*10u/6.3V_8

5

C179

C179

*22u/6.3V_8

*22u/6.3V_8

C504

C504
22u/6.3V_8

22u/6.3V_8

C181

C181
10u/6.3V_8

10u/6.3V_8

C499

C499
10u/6.3V_8

10u/6.3V_8

10uF (Reserved)

C194

C194
*10u/6.3V_8

*10u/6.3V_8

C457

C457

+

+

*470u/2V_7343

*470u/2V_7343

IVY Processor (POWER)

U15F

U15F

AG35

VCC1

AG34

VCC2

AG33

VCC3

AG32

VCC4

AG31

VCC5

AG30

VCC6

AG29

VCC7

AG28

VCC8

AG27

VCC9

AG26

VCC10

AF35

VCC11

AF34

VCC12

AF33

VCC13

AF32

VCC14

AF31

VCC15

AF30

VCC16

AF29

VCC17

AF28

VCC18

AF27

VCC19

AF26

VCC20

AD35

VCC21

AD34

VCC22

AD33

VCC23

AD32

VCC24

AD31

VCC25

AD30

VCC26

AD29

VCC27

AD28

VCC28

AD27

VCC29

AD26

VCC30

AC35

VCC31

AC34

VCC32

AC33

VCC33

AC32

VCC34

AC31

VCC35

AC30

VCC36

AC29

VCC37

AC28

VCC38

AC27

VCC39

AC26

VCC40

AA35

VCC41

AA34

VCC42

AA33

VCC43

AA32

VCC44

AA31

VCC45

AA30

VCC46

AA29

VCC47

AA28

VCC48

AA27

VCC49

AA26

VCC50

Y35

VCC51

Y34

VCC52

Y33

VCC53

Y32

VCC54

Y31

VCC55

Y30

VCC56

Y29

VCC57

Y28

VCC58

Y27

VCC59

Y26

VCC60

V35

VCC61

V34

VCC62

V33

VCC63

V32

VCC64

V31

VCC65

V30

VCC66

V29

VCC67

V28

VCC68

V27

VCC69

V26

VCC70

U35

VCC71

U34

VCC72

U33

VCC73

U32

VCC74

U31

VCC75

U30

VCC76

U29

VCC77

U28

VCC78

U27

VCC79

U26

VCC80

R35

VCC81

R34

VCC82

R33

VCC83

R32

VCC84

R31

VCC85

R30

VCC86

R29

VCC87

R28

VCC88

R27

VCC89

R26

VCC90

P35

VCC91

P34

VCC92

P33

VCC93

P32

VCC94

P31

VCC95

P30

VCC96

P29

VCC97

P28

VCC98

P27

VCC99

P26

VCC100

Ivy Bridge_rPGA_2DPC_Rev0p61

Ivy Bridge_rPGA_2DPC_Rev0p61

C164

C164
22u/6.3V_8

22u/6.3V_8

C180

C180
22u/6.3V_8

22u/6.3V_8

C511

C511
10u/6.3V_8

10u/6.3V_8

C500

C500
10u/6.3V_8

10u/6.3V_8

C454

C454

+

+

*470u/2V_7343

*470u/2V_7343

+VCC_CORE

C168

C168
22u/6.3V_8

22u/6.3V_8

C505

C505
22u/6.3V_8

22u/6.3V_8

C517

C517
10u/6.3V_8

10u/6.3V_8

C177

C177
10u/6.3V_8

10u/6.3V_8

C196

C196
*10u/6.3V_8

*10u/6.3V_8

POWER

POWER

CORE SUPPLY

CORE SUPPLY

+1.05V3,7,8,9,11,23,34,37,38,42,43,46

+VCC_CORE37,45,46

+1.8V8,11,43,46

+VCC_GFX37,45
+1.5V_CPU15

+VDDR_REF_CPU15

+VCCSA40

CPU Core Power

IVY 45W:TDC 52A
IVY SPEC

D D

22uF_8 x8 Socket TOP cavity
22uF_8 x10 Socket BOT cavity
22uF_8 x8 Socket TOP edge
470uF_7343 x4
total : 10uF x 10 , RSVD x 1
total : 22uF x 16 , RSVD x 3
tatal : 470u x 4, RSVD x2

SNB : Spec

470uF/4mohm x 4
22uF x 16
10uF x 10

C172

C172
22u/6.3V_8

22u/6.3V_8

C188

C188

C C

22u/6.3V_8

22u/6.3V_8

B B

A A

C513

C513
22u/6.3V_8

22u/6.3V_8

C189

C189

*22u/6.3V_8

*22u/6.3V_8

C167

C167
22u/6.3V_8

22u/6.3V_8

C175

C175

+

+

330u/2V_7343

330u/2V_7343

Cose down

330uF x2
22uF x 4
10uF x 20

reserved x 5

C515

C515
22u/6.3V_8

22u/6.3V_8

C506

C506
22u/6.3V_8

22u/6.3V_8

C514

C514
10u/6.3V_8

10u/6.3V_8

C195

C195

*10u/6.3V_8

*10u/6.3V_8

C197

C197
22u/6.3V_8

22u/6.3V_8

C174

C174

330u/2V_7343

330u/2V_7343

4

AH13

VCCIO1

AH10

VCCIO2

AG10

VCCIO3

AC10

VCCIO4

Y10

VCCIO5

U10

VCCIO6

P10

VCCIO7

L10

VCCIO8

J14

VCCIO9

J13

VCCIO10

J12

VCCIO11

J11

VCCIO12

H14

VCCIO13

H12

VCCIO14

H11

VCCIO15

G14

VCCIO16

G13

VCCIO17

G12

VCCIO18

F14

VCCIO19

F13

VCCIO20

F12

VCCIO21

F11

VCCIO22

E14

VCCIO23

E12

VCCIO24

E11

VCCIO25

D14

VCCIO26

D13

VCCIO27

D12

VCCIO28

D11

VCCIO29

C14

VCCIO30
VCCIO31
VCCIO32
VCCIO33
VCCIO34
VCCIO35
VCCIO36
VCCIO37
VCCIO38
VCCIO39

VCCIO40

VIDALERT#

VIDSCLK
VIDSOUT

VCC_SENSE
VSS_SENSE

VCCIO_SENSE

C13
C12
C11
B14
B12
A14
A13
A12
A11

J23

AJ29
AJ30
AJ28

AJ35
AJ34

B10
A10

PEG AND DDR

PEG AND DDR

VSS_SENSE_VCCIO

SENSE LINES SVID

SENSE LINES SVID

CPU VTT

IVY 45W:8.5A

SNB : Spec

330uF/6mohm x 2
22uF x 12

+1.05V

22uF x 7 (Non-stuff)

C526

C526
22u/6.3V_8

22u/6.3V_8

C528

C528
22u/6.3V_8

22u/6.3V_8

C205

C205
*22u/6.3V_8

*22u/6.3V_8

+1.05V_VTT_40

H_CPU_SVIDALRT#
H_CPU_SVIDCLK
H_CPU_SVIDDAT

R367 *SHORT_4R367 *SHORT_4
R368 *SHORT_4R368 *SHORT_4

VTT_VCCP_SENSE
VTT_VSSP_SENSE

Trace Route to Power IC area.

Cose down

330uF x1
22uF x 2
10uF x 10

reserved x 4

+

+

+

+

R407 *SHORT_4R407 *SHORT_4

C204

C204

C539

C539

330u/2V_7343

330u/2V_7343

330u/2V_7343

330u/2V_7343

C191

C191

C190

C190

C529

22u/6.3V_8

22u/6.3V_8

C527

C527
22u/6.3V_8

22u/6.3V_8

C536

C536
*22u/6.3V_8

*22u/6.3V_8

IVY SPEC

2uF_8 x7 Socket TOP cavity

2
22uF_8 x5 Socket BOT cavity
22uF_8 x2 Socket TOP cavity (no stuff)
22uF_8 x5 Socket BOT cavity (no stuff)
330uF_7343 x2

C529

22u/6.3V_8

22u/6.3V_8

22u/6.3V_8

22u/6.3V_8

C209

C209

C522

C522

22u/6.3V_8

22u/6.3V_8

22u/6.3V_8

22u/6.3V_8

C535

C535

C521

C521

*22u/6.3V_8

*22u/6.3V_8

*22u/6.3V_8

*22u/6.3V_8

+1.05V

DIS.VGA-->EV@ + EOP@
Optimus-->IOP@ + EOP@
UMA-->IV@ + IOP@
Ssecial-->SP@

CPU VCCPL

IVY 45W:1.5A

Spec

330uF/7mohm x 1
10uF x 1
1uF x 2

IVY SPEC
3

30uF x1, 10uF_8 x1, 1uF_4 x2

Socket BOT edge.

R360 100/F_4R360 100/F_4

R361 100/F_4R361 100/F_4

R421 10/F_4R421 10/F_4
R425 10/F_4R425 10/F_4

+VCC_CORE

VCC_SENSE 37
VSS_SENSE 37

VTT_VCCP_SENSE 38
VTT_VSSP_SENSE 38

3

CPU VGT

IVY 45W:TDC 38A

Spec

470uF/4mohm x 2
22uF x 12

+VCC_GFX

C206

C206

C530

C530

22u/6.3V_8

22u/6.3V_8

22u/6.3V_8

22u/6.3V_8

C532

C532

C525

C525

22u/6.3V_8

22u/6.3V_8 C217

22u/6.3V_8

22u/6.3V_8

C523

C523

C520

C520

*22u/6.3V_8

*22u/6.3V_8

*22u/6.3V_8

*22u/6.3V_8

R470 *SHORT_8R470 *SHORT_8

+1.8V

R471 *SHORT_8R471 *SHORT_8

Real

10uF x 1
1uF x 2

Layout note: need routing
together and ALERT need
between CLK and DATA

H_CPU_SVIDCLK

+

+

C503

C503

IOP@330u/2V_7343

IOP@330u/2V_7343

C187

C187

IOP@22u/6.3V_8

IOP@22u/6.3V_8

C183

C183

*IOP@22u/6.3V_8

*IOP@22u/6.3V_8

C184

C184

*IOP@22u/6.3V_8

*IOP@22u/6.3V_8

C507

C507

IOP@22u/6.3V_8

IOP@22u/6.3V_8

Cose down

330uF x1
22uF x 4
10uF x 10

Place PU resistor close to CPU

+1.05V

+1.05V

H_CPU_SVIDDAT

Place PU resistor close to CPU

IVY SPEC
22uF_8 x2 Socket TOP cavity
22uF_8 x2 Socket BOT cavity
22uF_8 x4 Socket TOP edge
22uF_8 x4 Socket BOT edge
470uF_7343 x2

+

+

C235

C235

IOP@330u/2V_7343

IOP@330u/2V_7343

C208

C208

C216

C216

IOP@22u/6.3V_8

IOP@22u/6.3V_8

IOP@22u/6.3V_8

IOP@22u/6.3V_8

C217

C186

C186

IOP@22u/6.3V_8

IOP@22u/6.3V_8

*IOP@22u/6.3V_8

*IOP@22u/6.3V_8

C185

C185

C201

C201

IOP@22u/6.3V_8

IOP@22u/6.3V_8

*IOP@22u/6.3V_8

*IOP@22u/6.3V_8

C516

C516

C501

C501

IOP@22u/6.3V_8

IOP@22u/6.3V_8

IOP@22u/6.3V_8

IOP@22u/6.3V_8

Ra

R129 EV@0/J_4R129 EV@0/J_4

DIS. VGANAUMA/ Optimus

Ra 0 ohm

CPU_VCCPLL

C555

C555

C551

C551

1u/6.3V_4

1u/6.3V_4

10u/6.3V_8

10u/6.3V_8

R354 *SHORT_4R354 *SHORT_4

R365

R365
130/F_4

130/F_4

R353 *SHORT_4R353 *SHORT_4

+1.05V

AT24
AT23
AT21

+

+

C550

C550
*330u/2V_7343

*330u/2V_7343

AT20
AT18
AT17
AR24
AR23
AR21
AR20
AR18
AR17
AP24
AP23
AP21
AP20
AP18
AP17
AN24
AN23
AN21
AN20
AN18
AN17
AM24
AM23
AM21
AM20
AM18
AM17
AL24
AL23
AL21
AL20
AL18
AL17
AK24
AK23
AK21
AK20
AK18
AK17

AH24
AH23
AH21
AH20
AH18
AH17

+

+

C534

C534

*IOP@330u/2V_7343

*IOP@330u/2V_7343

C207

C207

IOP@22u/6.3V_8

IOP@22u/6.3V_8

C193

C193

IOP@22u/6.3V_8

IOP@22u/6.3V_8

C200

C200

IOP@22u/6.3V_8

IOP@22u/6.3V_8

C512

C512

IOP@22u/6.3V_8

IOP@22u/6.3V_8

C556

C556
1u/6.3V_4

1u/6.3V_4

SVID CLK

Remove PU resistor 54.9/F,
stuff at IMVP7 page

SVID DATA

Remove PU resistor 130/F,
stuff at IMVP7 page

SVID ALERT

2

1

IVY Bridge Processor (GRAPHIC POWER)

POWER

U15G

U15G

VAXG1
VAXG2
VAXG3
VAXG4
VAXG5
VAXG6
VAXG7
VAXG8
VAXG9
VAXG10
VAXG11
VAXG12
VAXG13
VAXG14
VAXG15
VAXG16
VAXG17
VAXG18
VAXG19
VAXG20
VAXG21
VAXG22
VAXG23
VAXG24
VAXG25
VAXG26
VAXG27
VAXG28
VAXG29
VAXG30
VAXG31
VAXG32
VAXG33
VAXG34
VAXG35
VAXG36
VAXG37
VAXG38
VAXG39
VAXG40
VAXG41
VAXG42

AJ24

VAXG43

AJ23

VAXG44

AJ21

VAXG45

AJ20

VAXG46

AJ18

VAXG47

AJ17

VAXG48
VAXG49
VAXG50
VAXG51
VAXG52
VAXG53
VAXG54

B6

VCCPLL1

A6

VCCPLL2

A2

VCCPLL3

Ivy Bridge_rPGA_2DPC_Rev0p61

Ivy Bridge_rPGA_2DPC_Rev0p61

VR_SVID_CLK 37

VR_SVID_DATA 37

POWER

VAXG_SE NSE

VSSAXG_ SENSE

SENSE

LINES

SENSE

LINES

SA_DIMM_V REFDQ

VREFMISC

VREFMISC

SB_DIMM_V REFDQ

GRAPHICS

GRAPHICS

DDR3 -1.5V RAILS

DDR3 -1.5V RAILS

SA RAIL

SA RAIL

VCCSA_SE NSE

VCCSA_VID[0]
VCCSA_VID[1]

1.8V RAIL

1.8V RAIL

VCCIO_SEL

IVY SPEC

30uF x1, 10uF_8 x1 Socket BOT edge,

3
10uF_8 x2 Socket BOT cavity.

CPU SA

IVY 45W: 6A

Spec

330uF/7mohm x 1
10uF x 3

R369 100/F_4R369 100/F_4

AK35
AK34

R370 100/F_4R370 100/F_4

10 mil

+VDDR_REF_CPU

AL1

SM_VREF

Rb4

B4
D1

Rd1

IVY SPEC

30uF x1, 10uF_8 x6 Socket BOT edge.

3

AF7

VDDQ1

AF4

VDDQ2

AF1

VDDQ3

AC7

VDDQ4

AC4

VDDQ5

AC1

VDDQ6

Y7

VDDQ7

Y4

VDDQ8

Y1

VDDQ9

U7

VDDQ10

U4

VDDQ11

U1

VDDQ12

P7

VDDQ13

P4

VDDQ14

P1

VDDQ15

M27

VCCSA1

M26

VCCSA2

L26

VCCSA3

J26

VCCSA4

J25

VCCSA5

J24

VCCSA6

H26

VCCSA7

H25

VCCSA8

H23

C22
C24

VCCIO_SEL_NC

A19

Voltage selection for VCCIO:
this pin must be pulled high
on the motherboard

On CRB
H_SNB_IVB#_PWRCTRL = low, 1.0V
H_SNB_IVB#_PWRCTRL = high/NC, 1.05V

Real

10uF x 3

C546

C546

10u/6.3V_8

10u/6.3V_8

C245

C245

10u/6.3V_8

10u/6.3V_8

C182

C182

10u/6.3V_8

10u/6.3V_8

+VCC_GFX

+VDDR_REF_CPU

R466 *1K_4R466 *1K_4

R469 *1K_4R469 *1K_4

C547

C547

10u/6.3V_8

10u/6.3V_8

C240

C240

*10u/6.3V_8

*10u/6.3V_8

C169

C169

10u/6.3V_8

10u/6.3V_8

VCCSA_SENSE 40

VCCSA_VID0 40
VCCSA_VID1 40

TP103TP103

CPU MCH

IVY 45W: 5A

Spec

330uF/6mohm x 1
10uF x 6

Real

10uF x 8

C544

C544

10u/6.3V_8

10u/6.3V_8

C230

C230

*10u/6.3V_8

*10u/6.3V_8

C502

C502

10u/6.3V_8

10u/6.3V_8

VCC_AXG_SENSE 37
VSS_AXG_SENSE 37

For M3 solution
need Rb4, Rd1
W/O M3 then NC
ball B4 and D1

SMDDR_VREF_DQ0_M3 13
SMDDR_VREF_DQ1_M3 14

+1.5V_CPU

C543

C543

10u/6.3V_8

10u/6.3V_8

C558

C558

+

+

330u/2V_7343

330u/2V_7343

+

+

C445

C445
330u/2V_7343

330u/2V_7343

05

C234

C234

10u/6.3V_8

10u/6.3V_8

+VCCSA

R366

R366
75_4

H_CPU_SVIDALRT#

5

4

3

R359 43_4R359 43_4

75_4

R355 *SHORT_4R355 *SHORT_4

VR_SVID_ALERT# 37

2

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Wednesday, February 08, 2012

Date: Sheet of

Wednesday, February 08, 2012

Date: Sheet of

Wednesday, February 08, 2012

PROJECT :

IVY Bridge 3/4

IVY Bridge 3/4

IVY Bridge 3/4

1

ZQS 45W

ZQS 45W

ZQS 45W

5 46

5 46

5 46

3C

3C

3C

5

4

3

2

1

IVY Bridge Processor (GND)

U15H

U15H

AT35

VSS1

AT32

VSS2

AT29

VSS3

AT27

VSS4

AT25

VSS5

AT22

VSS6

AT19

VSS7

AT16

VSS8

AT13

VSS9

D D

C C

B B

AT10

AR25
AR22
AR19
AR16
AR13
AR10

AP34
AP31
AP28
AP25
AP22
AP19
AP16
AP13
AP10

AN30
AN27
AN25
AN22
AN19
AN16
AN13
AN10

AM29
AM25
AM22
AM19
AM16
AM13
AM10

AM7
AM4
AM3
AM2

AM1
AL34
AL31
AL28
AL25
AL22
AL19
AL16
AL13
AL10

AK33
AK30
AK27
AK25
AK22
AK19
AK16
AK13
AK10

AJ25

AT7
AT4
AT3

AR7
AR4
AR2

AP7
AP4
AP1

AN7
AN4

AL7
AL4
AL2

AK7
AK4

VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80

VSS

VSS

VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS98

VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160

AJ22
AJ19
AJ16
AJ13
AJ10
AJ7
AJ4
AJ3
AJ2
AJ1
AH35
AH34
AH32
AH30
AH29
AH28
AH25
AH22
AH19
AH16
AH7
AH4
AG9
AG8
AG4
AF6
AF5
AF3
AF2
AE35
AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE9
AD7
AC9
AC8
AC6
AC5
AC3
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
Y9
Y8
Y6
Y5
Y3
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
U9
U8
U6
U5
U3
U2

T35
T34
T33
T32
T31
T30
T29
T28
T27
T26

N35
N34
N33
N32
N31
N30
N29
N28
N27
N26
M34

K35
K32
K29
K26

H33
H30
H27
H24
H21
H18
H15
H13
H10

G35
G32
G29
G26
G23
G20
G17
G11
F34
F31
F29

U15I

U15I

VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170

P9

VSS171

P8

VSS172

P6

VSS173

P5

VSS174

P3

VSS175

P2

VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187

L33

VSS188

L30

VSS189

L27

VSS190

L9

VSS191

L8

VSS192

L6

VSS193

L5

VSS194

L4

VSS195

L3

VSS196

L2

VSS197

L1

VSS198
VSS199
VSS200
VSS201
VSS202

J34

VSS203

J31

VSS204
VSS205
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213

H9

VSS214

H8

VSS215

H7

VSS216

H6

VSS217

H5

VSS218

H4

VSS219

H3

VSS220

H2

VSS221

H1

VSS222
VSS223
VSS224
VSS225
VSS226
VSS227
VSS228
VSS229
VSS230
VSS231
VSS232
VSS233

VSS

VSS

VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285

F22
F19
E30
E27
E24
E21
E18
E15
E13
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
D35
D32
D29
D26
D20
D17
C34
C31
C28
C27
C25
C23
C10
C1
B22
B19
B17
B15
B13
B11
B9
B8
B7
B5
B3
B2
A35
A32
A29
A26
A23
A20
A3

IVY Bridge Processor (RESERVED, CFG)

U15E

U15E

VCC_DIE_SENSE

RSVD28
RSVD29
RSVD30
RSVD31

RSVD32

RSVD33
RSVD34
RSVD35

RSVD37
RSVD38
RSVD39
RSVD40

RSVD41
RSVD42
RSVD43
RSVD44
RSVD45

RSVD46
RSVD47
RSVD48
RSVD49
RSVD50

RSVD51
RSVD52

BCLK_ITP

BCLK_ITP#

RSVD56
RSVD57
RSVD58

KEY

AH27
AH26

L7
AG7
AE7
AK2

W8

AT26
AM33
AJ27

T8
J16
H16
G16

AR35
AT34
AT33
AP35
AR34

B34
A33
A34
B35
C35

AJ32
AK32

AN35
AM35

AT2
AT1
AR1

B1

VSS_DIE_SENSE

Rs

TP21TP21
TP18TP18

TP23TP23

TP98TP98
TP11TP11

XDP_CFG0
CFG1
CFG2
CFG3
CFG4CFG4
CFG5
CFG6
CFG7CFG7

AK28

CFG[0]

AK29

CFG[1]

AL26

CFG[2]

AL27

CFG[3]

AK26

CFG[4]

AL29

CFG[5]

AL30

CFG[6]

AM31

CFG[7]

AM32

CFG[8]

AM30

CFG[9]

AM28

CFG[10]

AM26

CFG[11]

AN28

CFG[12]

AN31

CFG[13]

AN26

CFG[14]

AM27

CFG[15]

AK31

CFG[16]

AN29

CFG[17]

AJ31

VAXG_VAL_SENSE

AH31

VSSAXG_VAL_SENSE

AJ33

VCC_VAL_SENSE

AH33

VSS_VAL_SENSE

AJ26

RSVD5

F25

RSVD8

F24

RSVD9

F23

RSVD10

D24

RSVD11

G25

RSVD12

G24

RSVD13

E23

RSVD14

D23

RSVD15

C30

RSVD16

A31

RSVD17

B30

RSVD18

B29

RSVD19

D30

RSVD20

B31

RSVD21

A30

RSVD22

C29

RSVD23

J20

RSVD24

B18

RSVD25

J15

RSVD27

Ivy Bridge_rPGA_2DPC_Rev0p61

Ivy Bridge_rPGA_2DPC_Rev0p61

CFG

CFG

RESERVED

RESERVED

VCC_DIE_SENSE

VSS_DIE_SENSE

R112

R112
*0_4

*0_4

TP100TP100
TP12TP12

TP14TP14
TP13TP13

TP17TP17
TP24TP24

For Sandy For IVY

Rs

06

Stuff NC

Ivy Bridge_rPGA_2DPC_Rev0p61

Ivy Bridge_rPGA_2DPC_Rev0p61

Processor Strapping

The CFG signals have a default value of '1' if not terminated on the board.

1 0

A A

CFG2

(PEG Static Lane Reversal)

CFG4

(DP Presence Strap)

CFG7

(PEG Defer Training)

Normal Operation

Disable; No physical DP attached to eDP

PEG train immediately following
xxRESETB de assertion

5

Ivy Bridge_rPGA_2DPC_Rev0p61

Ivy Bridge_rPGA_2DPC_Rev0p61

Lane Reversed

Enable; An ext DP device is connected to eDP

PEG wait for BIOS training

4

CFG2

CFG4

CFG7

R120 1K/F_4R120 1K/F_4

R113 1K/F_4R113 1K/F_4

R109 *1K/F_4R109 *1K/F_4

3

eDP_EN# 23

CFG5
CFG6

R110 *1K/F_4R110 *1K/F_4
R108 *1K/F_4R108 *1K/F_4

CFG[6:5] (PCIE Port Bifurcation Straps)

11: (Default) x16 - Device 1 functions 1 and 2 disabled
10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled
01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Wednesday, February 08, 2012

Date: Sheet of

Wednesday, February 08, 2012

Date: Sheet of

2

Wednesday, February 08, 2012

PROJECT :

IVY Bridge 4/4

IVY Bridge 4/4

IVY Bridge 4/4

1

ZQS 45W

ZQS 45W

ZQS 45W

6 46

6 46

6 46

3C

3C

3C

5

+1.05V3,5,8,9,11,23,34,37,38,42,43,46
+3V
+3V_S58,9,10,11,15,16,29,31,33,36,37,38,43,44

DPWROK_EC34

DMI_RXN03

+1.05V

SUS_PWR_ACK

R559

R559

R282 *0_4R282 *0_4

*SHORT_4

*SHORT_4

EC_PWROK_R

DMI_RXN13
DMI_RXN23
DMI_RXN33

DMI_RXP03
DMI_RXP13
DMI_RXP23
DMI_RXP33

DMI_TXN03
DMI_TXN13
DMI_TXN23
DMI_TXN33

DMI_TXP03
DMI_TXP13
DMI_TXP23
DMI_TXP33

R495 49.9/F_4R495 49.9/F_4
R499 750/F_4R499 750/F_4

R257 *0_4R257 *0_4

C607 *1u/10V_4C607 *1u/10V_4

*SHORT_4

*SHORT_4

SBA

R609 NSBA@0_4R609 NSBA@0_4

XDP_DBRST#

C698

C698
*0.1u/10V_4

*0.1u/10V_4

D D

C C

XDP_DBRST#3

SYS_PWROK

R294

R294

C15 Add 0Ω R609 to net EC_PWROK_R. 12/29

PM_DRAM_PWRGD15

PCH_RSMRST#34

DNBSWON#34

B B

EC_PWROK_R34,44

DPWROK_EC

DMI_COMP

SUSACK#_R

SYS_PWROK_R

EC_PWROK_RPWROK_EC

PM_DRAM_PWRGD

PCH_RSMRST#

SUS_PWR_ACK

AC_PRESENT

PM_BATLOW#

PM_RI#

CPT/PPT (DMI,FDI,PM)

U21C

U21C

BC24

DMI0RXN

BE20

DMI1RXN

BG18

DMI2RXN

BG20

DMI3RXN

BE24

DMI0RXP

BC20

DMI1RXP

BJ18

DMI2RXP

BJ20

DMI3RXP

AW24

DMI0TXN

AW20

DMI1TXN

BB18

DMI2TXN

AV18

DMI3TXN

AY24

DMI0TXP

AY20

DMI1TXP

AY18

DMI2TXP

AU18

DMI3TXP

BJ24

DMI_ZCOMP

BG25

DMI_IRCOMP

BH21

DMI2RBIAS

C12

SUSACK#

K3

SYS_RESET#

P12

SYS_PWROK

L22

PWROK

L10

APWROK

B13

DRAMPWROK

C21

RSMRST#

K16

SUSWARN#/SUSPWRDNACK/GPIO30

E20

PWRBTN#

H20

ACPRESENT / GPIO31

E10

BATLOW# / GPIO72

A10

RI#

PANTHER POINT

PANTHER POINT

DMI

FDI

DMI

FDI

+3V

CLKRUN# / GPIO32

+3V_S5

SUS_STAT# / GPIO61

+3V_S5

+3V_S5

SLP_S5# / GPIO63

System Power Management

System Power Management

DSW

+3V_S5

+3V_S5

SLP_LAN# / GPIO29

FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7

FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7

FDI_INT
FDI_FSYNC0
FDI_FSYNC1
FDI_LSYNC0
FDI_LSYNC1

DSWVRMEN

DPWROK

WAKE#

SUSCLK / GPIO62

SLP_S4#

+3V_S5

SLP_S3#

SLP_A#

SLP_SUS#

PMSYNCH

4

Pin K47 --->LVDS Enable

--->2.2K pull-up 3.3V

BJ14
AY14
BE14
BH13
BC12
BJ12
BG10
BG9

BG14
BB14
BF14
BG13
BE12
BG12
BJ10
BH9

AW16
AV12
BC10
AV14
BB10

A18

E22

B9

N3

G8

N14

D10

H4

F4

G10

G16

AP14

K14

PCIE_WAKE#

CLKRUN#

SUS_STAT#

PCH_SUSCLK

PCH_SLP_S5#

SLP_A#

SLP_SUS#

SLP_LAN#

TP127T P127

TP128T P128

TP130T P130

R2200_4 R2200_4
R646*0_4 R646*0_4

PCH_RSMRST#
DPWROK_EC

Disable ---> No connect

FDI_TXN0 3
FDI_TXN1 3
FDI_TXN2 3
FDI_TXN3 3
FDI_TXN4 3
FDI_TXN5 3
FDI_TXN6 3
FDI_TXN7 3

FDI_TXP0 3
FDI_TXP1 3
FDI_TXP2 3
FDI_TXP3 3
FDI_TXP4 3
FDI_TXP5 3
FDI_TXP6 3
FDI_TXP7 3

FDI_INT 3
FDI_FSYNC0 3
FDI_FSYNC1 3
FDI_LSYNC0 3
FDI_LSYNC1 3

DSWVREN 8

Change R220 from shortpad to 0Ω, reserve 0Ω R646 connect to DPWROK_EC. 01/05C22

PCIE_WAKE# 29

CLKRUN# 34

TP129T P129

SUSC# 34

SUSB# 34

SLP_A# 34

PM_SYNC 3

3

INT_LVDS_BLON23

INT_LVDS_DIGON23
INT_LVDS_BRIGHT23

INT_LVDS_EDIDCLK23
INT_LVDS_EDIDDATA23

+3V

INT_TXLCLKOUT-23

INT_TXLCLKOUT+23

INT_TXLOUT0-23
INT_TXLOUT1-23
INT_TXLOUT2-23

INT_TXLOUT0+23
INT_TXLOUT1+23
INT_TXLOUT2+23

INT_CRT_BLU23
INT_CRT_GRN23
INT_CRT_RED23

INT_CRT_DDCCLK23
INT_CRT_DDCDAT23

INT_HSYNC23
INT_VSYNC23

The required series-resistors are:

‧‧‧‧

Direct Connect - 33 Ω

‧‧‧‧

Docking Topology - 20 Ω

R place close to PCH

R451 IOP@150/F_4R451 IOP@150/F_4
R452 IOP@150/F_4R452 IOP@150/F_4
R453 IOP@150/F_4R453 IOP@150/F_4

R445 IOP@33_4R445 IOP@33_4
R446 IOP@33_4R446 IOP@33_4

INT_CRT_BLU
INT_CRT_GRN
INT_CRT_RED

R176 2.2K_4R176 2.2K_4
R168 2.2K_4R168 2.2K_4

R190 2.37K/F_4R190 2.37K/F_4

TP126T P126

INT_CRT_BLU
INT_CRT_GRN
INT_CRT_RED

INT_CRT_HSYNC_R
INT_CRT_VSYNC_R

DAC_IREF

R179

R179
IOP@1K/F_4

IOP@1K/F_4

2

CPT/PPT (LVDS,DDI)

U21D

U21D

J47

AF37
AF36

AE48
AE47

AK39
AK40

AN48
AM47
AK47

AJ48

AN47
AM49
AK49

AJ47

AF40
AF39

AH45
AH47
AF49
AF45

AH43
AH49
AF47
AF43

M45

P45
T40

K47
T45

P39

N48
P49
T49

T39

M40

M47
M49

T43
T42

L_BKLTEN
L_VDD_EN

L_BKLTCTL
L_DDC_CLK

L_DDC_DATA
L_CTRL_CLK

L_CTRL_DATA
LVD_IBG

LVD_VBG
LVD_VREFH

LVD_VREFL

LVDSA_CLK#
LVDSA_CLK

LVDSA_DATA#0
LVDSA_DATA#1
LVDSA_DATA#2
LVDSA_DATA#3

LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3

LVDSB_CLK#
LVDSB_CLK

LVDSB_DATA#0
LVDSB_DATA#1
LVDSB_DATA#2
LVDSB_DATA#3

LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3

CRT_BLUE
CRT_GREEN
CRT_RED

CRT_DDC_CLK
CRT_DDC_DATA

CRT_HSYNC
CRT_VSYNC

DAC_IREF
CRT_IRTN

PANTHER POINT

PANTHER POINT

SDVO_TVCLKINN

SDVO_TVCLKINP

SDVO_STALLN
SDVO_STALLP

SDVO_INTN

SDVO_INTP

SDVO_CTRLCLK

SDVO_CTRLDATA

DDPB_AUXN
DDPB_AUXP

DDPB_HPD

LVDS

LVDS

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPC_AUXN
DDPC_AUXP

DDPC_HPD

Digital Display Interface

Digital Display Interface

DDPD_CTRLCLK

DDPD_CTRLDATA

DDPD_AUXN
DDPD_AUXP

CRT

CRT

DDPD_HPD

DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P

DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P

DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P

AP43
AP45

AM42
AM40

AP39
AP40

P38
M39

AT49
AT47
AT40

AV42
AV40
AV45
AV46
AU48
AU47
AV47
AV49

P46
P42

AP47
AP49
AT38

AY47
AY49
AY43
AY45
BA47
BA48
BB47
BB49

M43
M36

AT45
AT43
BH41

BB43
BB45
BF44
BE44
BF42
BE42
BJ42
BG42

Pin M39 ---> Enable

--->2.2K pull-up 3.3V

DDPC_HPD_PU

DDPC_HPD_PU
DDPD_HPD_PU

Follow PDG DP disable guide

DDPD_HPD_PU

1

07

HDMI_DDCCLK_SW 24
HDMI_DDCDATA_SW 24

HDMI_HP 24

INT_HDMITX2N 24
INT_HDMITX2P 24
INT_HDMITX1N 24
INT_HDMITX1P 24
INT_HDMITX0N 24
INT_HDMITX0P 24
INT_HDMICLK- 24
INT_HDMICLK+ 24

Pin P42 ---> Enable

--->2.2K pull-up 3.3V

+3V

R153 *2.2K_4R153 *2.2K_4
R158 *2.2K_4R158 *2.2K_4

Pin M36 ---> Enable

--->2.2K pull-up 3.3V

INT. HDMI

Reserve 0.1u capacitor C698 to EC_PWROK_R. 01/17C35

PCH Pull-high/low(CLG)

+3V

CLKRUN#

R535 8.2K_4R535 8.2K_4

XDP_DBRST#

R543 4.99K/F_4R543 4.99K/F_4

A A

PCH_RSMRST#

SYS_PWROK

R533 *1K_4R533 *1K_4
R221 10K_4R221 10K_4

R558 *10K_4R558 *10K_4

PM_RI#
PM_BATLOW#
PCIE_WAKE#
SLP_LAN#
SUS_PWR_ACK
AC_PRESENT

PM_DRAM_PWRGD

R552 10K_4R552 10K_4
R286 8.2K_4R286 8.2K_4
R530 10K_4R530 10K_4
R260 *10K_4R260 *10K_4
R251 10K_4R251 10K_4
R219 10K_4R219 10K_4

R507 200/F_4R507 200/F_4

+3V_S5

System PWR_OK(CLG)

to PCH Pin12, XDP and EE debug

SYS_PWROK15

SYS_PWROK

U24

U24

4

TC7SH08FU

TC7SH08FU

wo S3 leakage, remove R

5

4

IMVP_PWRGD PU +3V
PWROK_EC PD

+3V_S5

so AND gate output dont need PD again

C651

C651
*0.1u/10V_4

*0.1u/10V_4

2

PWROK_EC

1

3 5

R572

R572
100K_4

100K_4

3

IMVP_PWRGD 3,37
PWROK_EC 34

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Wednesday, February 08, 2012

Date: Sheet of

Wednesday, February 08, 2012

Date: Sheet of

2

Wednesday, February 08, 2012

PROJECT :

Panther Point 1/6

Panther Point 1/6

Panther Point 1/6

ZQS 45W

ZQS 45W

ZQS 45W

7 46

7 46

1

7 46

3C

3C

3C

5

RTC Circuitry(RTC)

20mils

R568 *SHORT_6R568 *SHORT_6

+3VPCU

20MIL

20MIL

D D

R573

R573
1K_4

1K_4

CN12

CN12

1
2

RTC_CON.

RTC_CON.

+3V_RTC_1

HDA Bus(CLG)

PCH JTAG Debug (CLG)

C C

PCH Dual SPI (CLG)

+3V_M

+3V_M SBA function.

PCH_SPI_CS0#
PCH_SPI_CLK
PCH_SPI_SI
PCH_SPI_SO

B B

SPI_CS0#_UR_ME34

R159 3.3K_4R159 3.3K_4

PCH_SPI_CS1#
PCH_SPI_CLK
PCH_SPI_SI
PCH_SPI_SO

R156 3.3K_4R156 3.3K_4

+3V_PCH_ME

+3V_PCH_ME

A A

+3V_RTC

D20

D20

R564 20K_4R564 20K_4

BAT54C

BAT54C

30mils

R566 20K_4R566 20K_4

C630

C630
1u/6.3V_4

1u/6.3V_4

PCH_AZ_CODEC_BITCLK27

PCH_AZ_CODEC_SYNC27

PCH_AZ_CODEC_RST#27

PCH_AZ_CODEC_SDOUT27

R531

R531
51_4

51_4

+3V_S5

C623

C623
1u/6.3V_4

1u/6.3V_4

C624

C624
1u/6.3V_4

1u/6.3V_4

CN13
DFWF02MS118

R485 33_4R485 33_4
R185 33_4R185 33_4
R195 33_4R195 33_4
R199 33_4R199 33_4

R295

R295
210/F_4

210/F_4

R269

R269
100/F_4

100/F_4

12

J1

J1

*SHORT_PAD

*SHORT_PAD

12

J2

J2

*SHORT_PAD

*SHORT_PAD

R283

R283
210/F_4

210/F_4

PCH_JTAG_TMS_R
PCH_JTAG_TDI_R
PCH_JTAG_TCK

R270

R270
100/F_4

100/F_4

RTC_RST#

SRTC_RST#

ACZ_BITCLK_R
ACZ_SYNC_CODEC
ACZ_RST#_R
ACZ_SDOUT_R

(Default for WIN8)

W25Q64BVSSIG / AKE3EFP0N00----->8MB
W25Q32BVSSIG / AKE391P0N00----->4MB
W25Q16BVSSIG / AKE38FP0N01----->2MB

R144 NSBA@0_6R144 NSBA@0_6
R625 SBA@0_6R625 SBA@0_6

U20

U20

1

R626 33_4R626 33_4
R627 33_4R627 33_4
R628 33_4R628 33_4

C242

C242
*22p/50V_4

*22p/50V_4

R629 33_4R629 33_4
R630 33_4R630 33_4
R631 33_4R631 33_4

C243

C243
*22p/50V_4

*22p/50V_4

+3VPCU

C11 Change R641 from reserve to mount per EC request. 12/27

5

CE#

6

SCK

5

SI

2

SO

3

WP#

ROM-2M

ROM-2M

U19

U19

1

CE#

6

SCK

5

SI

2

SO

3

WP#

SP@ROM-4M

SP@ROM-4M

R641

R641

4.7K_4

4.7K_4

+3VPCU11,23,25,26,31,33,34,35,36,43,44,46
+5V11,23,24,26,27,33,36,43,46
+3V_S57,9,10,11,15,16,29,31,33,36,37,38,43,44

+1.05V3,5,7,9,11,23,34,37,38,42,43,46
+3V
+1.8V5,11,43,46

8

VDD

R149 3.3K_4R149 3.3K_4

7

HOLD#

4

VSS

8

VDD

R150 3.3K_4R150 3.3K_4

7

HOLD#

4

VSS

R146 *0_4R146 *0_4

R147 0_4R147 0_4

+3V_PCH_ME+3V_S5

+3V_PCH_ME

+3V_PCH_ME

PCH_SPI_CS0#

PCH_SPI_CS1#

battery
AHL03003022
AHL03003024

C222

C222

0.1u/10V_4

0.1u/10V_4

C223

C223

0.1u/10V_4

0.1u/10V_4

4

3

PCH2(CLG)

C591 18p/50V_4C591 18p/50V_4

C590 18p/50V_4C590 18p/50V_4

Add MOSFET to separate CODEC SYNC signal

+5V

ACZ_SYNC_CODEC

CRB 1.0

R184

R184
1M_4

1M_4

2

1

Q13

Q13
2N7002K

2N7002K

PCH_SPI_CLK34

PCH_SPI_SI34

PCH_SPI_SO34

32.768KHZY332.768KHZ

+3V_RTC

3

PCH_AZ_CODEC_SDIN027

+3VPCU

23

Y3

4 1

R214 1M_4R214 1M_4

R537 *10K_4R537 *10K_4

R502

R502
10M_4

10M_4

SPKR27

TP37TP37

TP112TP112
TP39TP39

TP121TP121

PCH Strap Table

Pin Name

Strap description

No reboot mode setting PWROKSPKR

GNT3# / GPIO55 Top-Block Swap Override

INTVRMEN Integrated 1.05V VRM enable ALWAYS Should be always pull-up

GNT1# / GPIO51

GPIO19

Boot BIOS Selection 1 [bit-1]

Boot BIOS Selection 0 [bit-0]

HDA_SDO Flash Descriptor Security RSMRST

DF_TVS

GPIO28

DMI/FDI Termination voltage

On-die PLL Voltage Regulator RSMRST#

HDA_SYNC On-Die PLL VR Voltage Select RSMRST

GPIO15

DSWVREN DSW

NV_ALE

4

Intel ME Crypto Transport Layer
Security (TLS) cipher suite
internal PD

DEEP S4/S5 well
On Die DSW VR Enable

Intel Anti-Theft HDD protection

Only for Interposer

Sampled

Configuration

0 = Default (weak pull-down 20K)

1 = Setting to No-Reboot mode

PWROK

0 = "top-block swap" mode

1 = Default (weak pull-up 20K)

PWROK

PWROK

0 = effect (default)(weak pull-down 20K)

1 = overridden

PWROK

0 = Set to Vss (weak pull-down 20K)

1 = Set to Vcc

0 = Disable

1 = Enable (weak pull-up 20K)

0 = Support by 1.8V (weak pull-down)

1 = Support by 1.5V

RSMRST

0 = Disable (Default)

1 = Enable

High = Enable (Default)

Low = Disable

PWROK 0 = Disable (Internal pull-down 20kohm)

3

CPT/PPT (HDA,JTAG,SATA)

RTC_X1
RTC_X2
RTC_RST#
SRTC_RST#
SM_INTRUDER#
PCH_INVRMEN

ACZ_BITCLK_R
ACZ_SYNC_R
SPKR
ACZ_RST#_R

ACZ_SDOUT_R

PCH_GPIO33
PCH_GPIO13

PCH_JTAG_TCK
PCH_JTAG_TMS_R
PCH_JTAG_TDI_R
PCH_JTAG_TDO_R

PCH_SPI_CLK
PCH_SPI_CS0#
PCH_SPI_CS1#

PCH_SPI_SI
PCH_SPI_SO

GNT0#GNT1#

11
00

U21A

U21A

A20

RTCX1

C20

RTCX2

D20

RTCRST#

G22

SRTCRST#

K22

INTRUDER#

C17

INTVRMEN

N34

HDA_BCLK

L34

HDA_SYNC

T10

SPKR

K34

HDA_RST#

E34

HDA_SDIN0

G34

HDA_SDIN1

C34

HDA_SDIN2

A34

HDA_SDIN3

A36

HDA_SDO

C36

HDA_DOCK_EN# / GPIO33

N32

HDA_DOCK_RST# / GPIO13

J3

JTAG_TCK

H7

JTAG_TMS

K5

JTAG_TDI

H1

JTAG_TDO

T3

SPI_CLK

Y14

SPI_CS0#

T1

SPI_CS1#

V4

SPI_MOSI

U3

SPI_MISO

PANTHER POINT

PANTHER POINT

Boot Location

SPI

*

LPC

RTCIHDA

RTCIHDA

JTAG

JTAG

SPI

SPI

+3V_RTC

+3V

+3V
+3V_S5

+3V
+3V

+3V_RTC

ME_WR34

+3V_S5

+1.8V

2

FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3

LPC

LPC

FWH4 / LFRAME#

LDRQ0#

LDRQ1# / GPIO23

SERIRQ

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP

SATA1RXN

SATA 6G

SATA 6G

SATA1RXP
SATA1TXN
SATA1TXP

SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP

SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP

SATA4RXN
SATA4RXP
SATA4TXN

SATA

SATA

SATA4TXP
SATA5RXN

SATA5RXP
SATA5TXN
SATA5TXP

SATAICOMPO

SATAICOMPI

SATA3RCOMPO

SATA3COMPI

SATA3RBIAS

SATALED#
SATA0GP / GPIO21
SATA1GP / GPIO19

R279 *1K_4R279 *1K_4

+3V

R458 *1K_4R458 *1K_4

R500 330K_4R500 330K_4

R456 *1K_4R456 *1K_4
R536 *1K_4R536 *1K_4

R256 2.2K_4R256 2.2K_4
R255 1K_4R255 1K_4

R292 *1K_4R292 *1K_4

+3V_S5

R542 1K_4R542 1K_4

R503 330K_4R503 330K_4

R504 *330K_4R504 *330K_4

R248 *1K_4R248 *1K_4

2

C38
A38
B37
C37

D36

PCH_DRQ#0

E36

PCH_DRQ#1

K36
V5

R265 8.2K_4R265 8.2K_4

AM3
AM1
AP7
AP5

AM10
AM8
AP11
AP10

AD7
AD5
AH5
AH4

AB8
AB10
AF3
AF1

Y7
Y5

Second HDD

AD3
AD1

Y3
Y1
AB3
AB1

Y11

SATA_COMP

Y10

SATA3_COMP

AB12
AB13

SATA3_RBIAS

AH1

SATA_ACT#

P3

SATA0GP

V14

BBS_BIT0

P1

SPKR

PCH_INVRMEN

R481 *SHORT_4R481 *SHORT_4

+1.8V

R166 1K_4R166 1K_4

TP32TP32
TP110TP110

R232 37.4/F_4R232 37.4/F_4

R229 49.9/F_4R229 49.9/F_4

R529 750/F_4R529 750/F_4

R547 10K_4R547 10K_4

R277 10K_4R277 10K_4

PCI_GNT3# 9

BBS_BIT1 9

BBS_BIT0

ACZ_SDOUT_R

DF_TVS 10
H_SNB_IVB# 3

PLL_ODVR_EN 10

ACZ_SYNC_R

PCH_GPIO15 10

DSWVREN 7

NV_ALE 9

1

LPC_LAD0 25,34
LPC_LAD1 25,34
LPC_LAD2 25,34
LPC_LAD3 25,34

LPC_LFRAME# 25,34

IRQ_SERIRQ 34

+3V

SATA_RXN0_C 26
SATA_RXP0_C 26
SATA_TXN0 26
SATA_TXP0 26

SATA_RXN_SSD 25
SATA_RXP_SSD 25
SATA_TXN_SSD 25

SATA_TXP_SSD 25

DG recommended that AC coupling capacitors should be
close to the connector (<100 mils) for optimal signal quality.

TP120TP120

TP119TP119

TP56TP56

SATA_RXN5_C 26
SATA_RXP5_C 26
SATA_TXN5 26
SATA_TXP5 26

+1.05V

+3V
SATA_ACT# 33

+3V

SATA0GP/GPIO21
SATA4GP/GPIO16
SATA5GP/GPIO49
If these pins are unused use 8.2k
to 10k pull-up to +Vcc3_3 or 8.2k
to 10k pull-down to ground

SATA HDD

SSD

SATA ODD

Used as GPIO only. at chklist 1.2

Default weak pull-up on GNT0/1#
[Need external pull-down for LPC BIOS]

ME_WR default EC setting folating

for future CPU, Sandy Bridge NC
DF_TVS needs to be pulled up to VccDFTERM power rail
through 2.2 kOhm ±5% - R8361 change to 0 or not??

Needs to be pulled High for Huron River platform.
chklist 1.2

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Wednesday, February 08, 2012

Date: Sheet of

Wednesday, February 08, 2012

Date: Sheet of

Wednesday, February 08, 2012

PROJECT :

Panther Point 2/6

Panther Point 2/6

Panther Point 2/6

ZQS 45W

ZQS 45W

ZQS 45W

1

08

8 46

8 46

8 46

3C

3C

3C

5

+3V
+3V_S57,8,10,11,15,16,29,31,33,36,37,38,43,44
+1.05V3,5,7,8,11,23,34,37,38,42,43,46

CPT/PPT (PCI,USB,NVRAM)

U21E

U21E

BG26

TP1

BJ26

TP2

BH25

TP3

BJ16

TP4

BG16

TP5

AH38

TP6

D D

TX AC cap place at connector side, AC cap to
connector < 400 mils

USB3.0

C C

CLK_LPC_DEBUG25

CLK_PCI_77534

B B

PLTRST#(CLG)

PCI_PLTRST#

A A

TP44TP44

USB30_RX3-31

TP50TP50

USB30_RX3+31

TP48TP48 TP133TP133

USB30_TX3-31

TP49TP49

USB30_TX3+31

BBS_BIT18

BOARD_ID210

PCI_GNT3#8

G_SENSOR_INT#_PCH26

dGPU_PWR_EN42

DGPU_HOLD_RST#16

PCI_PLTRST#3

CLK_PCI_FB CLK_PCI_FB_C

R447 22_4R447 22_4
R178 22_4R178 22_4
R177 22_4R177 22_4

Change U22 PLTRST# power source from +3V_S5 to +3V. 01/17C30

+3V

2
1

U22

U22

3 5

TC7SH08FU

TC7SH08FU

TP41TP41
TP117TP117
TP42TP42
TP116TP116
TP46TP46
TP43TP43
TP47TP47
TP45TP45

TP54TP54

TP30TP30

4

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

dGPU_EDIDSEL#
dGPU_SELECT#
REQ#3

G_SENSOR_INT#_PCH

dGPU_PWR_EN

DGPU_HOLD_RST#

EXTTS_SNI_DRV1_PCH

CLK_LPC_DEBUG_C
CLK_PCI_775_C

C622

C622

0.1u/10V_4

0.1u/10V_4

5

USB30_RX1­USB30_RX2­USB30_RX3­USB30_RX4­USB30_RX1+
USB30_RX2+
USB30_RX3+
USB30_RX4+
USB30_TX1­USB30_TX2­USB30_TX3­USB30_TX4­USB30_TX1+
USB30_TX2+
USB30_TX3+
USB30_TX4+

PCI_PME#
PCI_PLTRST#

R551

R551
100K_4

100K_4

AH37

TP7

AK43

TP8

AK45

TP9

C18

TP10

N30

TP11

H3

TP12

AH12

TP13

AM4

TP14

AM5

TP15

Y13

TP16

K24

TP17

L24

TP18

AB46

TP19

AB45

TP20

B21

TP21

M20

TP22

AY16

TP23

BG46

TP24

BE28

TP25

BC30

TP26

BE32

TP27

BJ32

TP28

BC28

TP29

BE30

TP30

BF32

TP31

BG32

TP32

AV26

TP33

BB26

TP34

AU28

TP35

AY30

TP36

AU26

TP37

AY26

TP38

AV28

TP39

AW30

TP40

K40

PIRQA#

K38

PIRQB#

H38

PIRQC#

G38

PIRQD#

C46

REQ1# / GPIO50

C44

REQ2# / GPIO52

E40

REQ3# / GPIO54

D47

GNT1# / GPIO51

E42

GNT2# / GPIO53

F46

GNT3# / GPIO55

G42

PIRQE# / GPIO2

G40

PIRQF# / GPIO3

C42

PIRQG# / GPIO4

D44

PIRQH# / GPIO5

K10

PME#

C6

PLTRST#

H49

CLKOUT_PCI0

H43

CLKOUT_PCI1

J48

CLKOUT_PCI2

K42

CLKOUT_PCI3

H40

CLKOUT_PCI4

PANTHER POINT

PANTHER POINT

PLTRST# 16,25,29,34

USB30_RX1N
USB30_RX2N
USB30_RX3N
USB30_RX4N
USB30_RX1P
USB30_RX2P
USB30_RX3P
USB30_RX4P
USB30_TX1N
USB30_TX2N
USB30_TX3N

USB30_TX4N
USB30_TX1P
USB30_TX2P
USB30_TX3P
USB30_TX4P

RSVD

RSVD

PCI

PCI

+3V
+3V
+3V

+3V
+3V
+3V

+3V
+3V
+3V
+3V

+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5

RSVD1
RSVD2
RSVD3
RSVD4

RSVD5
RSVD6

RSVD7
RSVD8

RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22

RSVD23
RSVD24

RSVD25
RSVD26

RSVD27
RSVD28

RSVD29

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P

USBP10N

USBP10P

USB

USB

USBP11N

USBP11P

USBP12N

USBP12P

USBP13N

USBP13P

USBRBIAS#

USBRBIAS

OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43

OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14

PCI/USBOC# Pull-up(CLG)

+3V

R479 *1K_4R479 *1K_4
R480 EOP@100K_4R480 EOP@100K_4

+3V

R155 SP_OPT@10K_4R155 SP_OPT@10K_4
R161

R161

+3V

R560 10K_4R560 10K_4
R548 *10K_ 4R548 *10K_4

AY7
AV7
AU3
BG4

AT10
BC8

AU2
AT4
AT3
AT1
AY3
AT5
AV3
AV1
BB1
BA3
BB5
BB3
BB7
BE8
BD4
BF6

AV5
AV10

AT8
AY5

BA2
AT12

BF3

C24
A24
C25
B25
C26
A26
K28
H28
E28
D28
C28
A28
C29
B29
N28
M28
L30
K30
G30
E30
C30
A30
L32
K32
G32
E32
C32
A32

C33

B33

USB_OC0#

A14

USB_OC1#

K20

USB_OC2#

B17

USB_OC3#

C16

USB_OC4#

L16

USB_OC5#

A16

USB_OC6#

D14

USB_OC7#

C14

USB_OC4#
USB_OC1#
USB_OC2#
USB_OC3#

SP_DIS_UMA@10K_4

SP_DIS_UMA@10K_4

4

NV_ALE 8

Port1 and port9 can be used on debug mode

USBP0-

TP131TP131

USBP0+

USBP3­USBP3+

USBP5­USBP5+

USBP11­USBP11+
USBP12­USBP12+
USBP13­USBP13+

USB_BIAS

+3V_S5

Reserve for USB I/O function

USBP1- 31
USBP1+ 31
USBP2- 31
USBP2+ 31
USBP3- 25
USBP3+ 25
USBP4- 31
USBP4+ 31

TP137TP137
TP138TP138

Reserve for SIM card

USB port6/7 may not be available on all PCH sku
(HM55 support 12port only)

USBP8- 23
USBP8+ 23
USBP9- 31
USBP9+ 31
USBP10- 25
USBP10+ 25

T25T25
T26T26

Reserve for card reader

TP145TP145
TP147TP147

Reserve for Touch pad

TP149TP149
TP150TP150

Reserve for FP

R482 22.6/F_4R482 22.6/F_4

R505

R505

10

1

9

2

8

3

7 4

56

10K_10P8R

10K_10P8R

dGPU_PW_CTRL# 10

SKU_ID1

SKU_ID0 10

4

3

LAN

Wireless

USB/B-USB1-1/USB debug
MB USB
Mini-SSD
BLUETOOTH

Camera
USB/B-USB1-2
MINI-CARD WLAN(MPC)

XHCI for USBP0-3

EHCI1

EHCI2

Wireless

USB_OC1# 31

USB_OC4# 31

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#

G_SENSOR_INT#_PCH

REQ#3
dGPU_PWR_EN

dGPU_PW_CTRL#
(GPIO68)
CTL : dGPU_VRON

100

0

PCI_PIRQD#

SKU_ID1
(GPIO64)

011

+3V

USB_OC6#
USB_OC0#
USB_OC7#
USB_OC5#

UMA Only

dGPU Only

Switchable
(Mux)

Optimize
(Muxless)

dGPU_PW_CTRL#
1 = GPU power is control by H/W (pure Discrete SKU)

0 = GPU power is control by PCH GPIO (Discrete, SG or Optimiz e)

--->(Default)

R541 10K_4R541 10K_4

R467

R467

10

9
8
7 4

10K_10P8R

10K_10P8R

SKU_ID0
(GPIO16)

0

1

LAN

R171 8.2K_4R171 8.2K_4
R192 8.2K_4R192 8.2K_4
R165 8.2K_4R165 8.2K_4
R172 8.2K_4R172 8.2K_4

DGPU_HOLD_RST#

1

EXTTS_SNI_DRV1_PCH

2

dGPU_EDIDSEL#

3

dGPU_SELECT#

56

VGA H/W

Setup

Signal

Menu

UMA

Hidden

GPU

Hidden

UMA+GPU

dGPU/SG

UMA

UMA/SG

3

CLK_PCH_SRC5#25
CLK_PCH_SRC525

PCIE_CLKREQ5#25

CLK_PCIE_LAN_REQ#29

UMA boot

GPU boot

UMA boot

UMA boot

PCIE_RX3-29
PCIE_RX3+29

PCIE_TX3-29
PCIE_TX3+29

PCIE_RX8-25
PCIE_RX8+25

PCIE_TX8-25
PCIE_TX8+25

CLK_PCIE_LOM#29
CLK_PCIE_LOM29

For XDP

+3V

+3V

TP132TP132
TP134TP134

TP115TP115
TP114TP114
TP40TP40
TP36TP36

C565 0.1u/10V_4C565 0.1u/10V_4
C567 0.1u/10V_4C567 0.1u/10V_4

TP34TP34

TP38TP38
TP111TP111

TP113TP113
TP33TP33
TP35TP35

TP31TP31

C256 0.1u/10V_4C256 0.1u/10V_4
C261 0.1u/10V_4C261 0.1u/10V_4

TP135TP135
TP136TP136

TP139TP139
TP140TP140

TP141TP141
TP142TP142

TP146TP146
TP148TP148

R162 *SHORT_4R162 *SHORT_4
R157 *SHORT_4R157 *SHORT_4

R175 *SHORT_4R175 *SHORT_4
R167 *SHORT_4R167 *SHORT_4

TP151TP151

TP152TP152

TP154TP154
TP155TP155

+3V_S5

+3V

+3V_S5

CLK_PEGA_REQ#
CLK_BUF_BCLKN

CLK_BUF_BCLKP

CLK_BUF_PCIE_3GPLLN
CLK_BUF_PCIE_3GPLLP
CLK_BUF_DREFCLKN
CLK_BUF_DREFCLKP
CLK_BUF_DREFSSCLKN
CLK_BUF_DREFSSCLKP
CLK_PCH_14M

CLOCK TERMINATION for FCIM

PER1­PER1+
PET1­PET1+

PCIE_TXN3_C
PCIE_TXP3_C

PET4+

PET5+
PER6-

PER6+
PET6­PET6+

PET7+

PCIE_TXN8_C
PCIE_TXP8_C

PCIE_CLK_USB30_REQ#

PCIE_CLKREQ1#

PCIE_CLK_REQ2#

PCIE_CLKREQ3#

PCIE_CLKREQ4#

PCIE_CLKREQ5#

CLK_PCIE_LOM#_R
CLK_PCIE_LOM_R

CLK_PCIE_LAN_REQ#

CLK_PCH_SRC6P
CLK_PCIE_REQ6#

CLK_PCH_SRC7P
CLK_PCIE_REQ7#
CLK_ITPN

CLK_ITPP

R556 10K_4R556 10K_4

R528 10K_4R528 10K_4
R262 10K_4R262 10K_4

R259 10K_4R259 10K_4
R284 10K_4R284 10K_4
R258 10K_4R258 10K_4
R273 10K_4R273 10K_4

R534 10K_4R534 10K_4
R249 10K_4R249 10K_4

R275

R275

PCIE_CLK_USB30_REQ#

PCIE_CLKREQ3#
PCIE_CLKREQ4#

PCIE_CLKREQ5#
CLK_PCIE_LAN_REQ#
CLK_PCIE_REQ6#
CLK_PCIE_REQ7#

PCIE_CLKREQ1#
PCIE_CLK_REQ2#

*10K_4

*10K_4

CLK_PEGA_REQ#

Pill-up in N13P side

R632 *10K_4R632 *10K_4
R490 10K_4R490 10K_4

R488 10K_4R488 10K_4

R225 10K_4R225 10K_4
R227 10K_4R227 10K_4
R206 10K_4R206 10K_4
R210 10K_4R210 10K_4
R238 10K_4R238 10K_4

R154 10K_4R154 10K_4

2

CPT/PPT (PCI-E,SMBUS,CLK)

U21B

U21B

BG34

PERN1

BJ34

PERP1

AV32

PETN1

AU32

PETP1

BE34

PERN2

BF34

PERP2

BB32

PETN2

AY32

PETP2

BG36

PERN3

BJ36

PERP3

AV34

PETN3

AU34

PETP3

BF36

PERN4

BE36

PERP4

AY34

PETN4

BB34

PETP4

BG37

PERN5

BH37

PERP5

AY36

PETN5

BB36

PETP5

BJ38

PERN6

BG38

PERP6

AU36

PETN6

AV36

PETP6

BG40

PERN7

BJ40

PERP7

AY40

PETN7

BB40

PETP7

BE38

PERN8

BC38

PERP8

AW38

PETN8

AY38

PETP8

Y40

CLKOUT_PCIE0N

Y39

CLKOUT_PCIE0P

J2

PCIECLKRQ0# / GPIO73

AB49

CLKOUT_PCIE1N

AB47

CLKOUT_PCIE1P

M1

PCIECLKRQ1# / GPIO18

AA48

CLKOUT_PCIE2N

AA47

CLKOUT_PCIE2P

V10

PCIECLKRQ2# / GPIO20

Y37

CLKOUT_PCIE3N

Y36

CLKOUT_PCIE3P

A8

PCIECLKRQ3# / GPIO25

Y43

CLKOUT_PCIE4N

Y45

CLKOUT_PCIE4P

L12

PCIECLKRQ4# / GPIO26

V45

CLKOUT_PCIE5N

V46

CLKOUT_PCIE5P

L14

PCIECLKRQ5# / GPIO44

AB42

CLKOUT_PEG_B_N

AB40

CLKOUT_PEG_B_P

E6

PEG_B_CLKRQ# / GPIO56

V40

CLKOUT_PCIE6N

V42

CLKOUT_PCIE6P

T13

PCIECLKRQ6# / GPIO45

V38

CLKOUT_PCIE7N

V37

CLKOUT_PCIE7P

K12

PCIECLKRQ7# / GPIO46

AK14

CLKOUT_ITPXDP_N

AK13

CLKOUT_ITPXDP_P

PANTHER POINT

PANTHER POINT

+3V_S5

+3V_S5

SMBUSController

SMBUSController

+3V_S5

SML1ALERT# / PCHHOT# / GPIO74

+3V_S5
+3V_S5

PCI-E*

PCI-E*

+3V_S5

+3V_S5

CLOCKS

CLOCKS

+3V

+3V

+3V_S5

+3V_S5

+3V_S5

+3V_S5

+3V_S5

+3V
+3V

+3V_S5

+3V
+3V

SMBALERT# / GPIO11

SML0ALERT# / GPIO60

SML1CLK / GPIO58

SML1DATA / GPIO75

Link

Link

PEG_A_CLKRQ# / GPIO47

CLKOUT_PEG_A_N
CLKOUT_PEG_A_P

CLKIN_PCILOOPBACK

CLKOUTFLEX0 / GPIO64
CLKOUTFLEX1 / GPIO65
CLKOUTFLEX2 / GPIO66
CLKOUTFLEX3 / GPIO67

FLEX CLOCKS

FLEX CLOCKS

SMBus(EC)CLK_REQ/Strap Pin(CLG)

R513 1K_4R513 1K_ 4
R274 10K_4R274 10K_4

R298 2.2K_4R298 2.2K_4
R297 2.2K_4R297 2.2K_4R242 10K_4R242 10K_4
R539 2.2K_4R539 2.2K_4
R250 2.2K_4R250 2.2K_4
R508 10K_4R508 10K_4

3

3

2ND_MBCLK34

2ND_MBDATA34

+3V_S5

2

SMBCLK

SMBDATA

SML0CLK

SML0DATA

CL_CLK1

CL_DATA1

CL_RST1#

CLKOUT_DMI_N
CLKOUT_DMI_P

CLKOUT_DP_N
CLKOUT_DP_P

CLKIN_DMI_N
CLKIN_DMI_P

CLKIN_GND1_N

CLKIN_GND1_P

CLKIN_DOT_96N
CLKIN_DOT_96P

CLKIN_SATA_N
CLKIN_SATA_P

REFCLK14IN

XTAL25_IN

XTAL25_OUT

XCLK_RCOMP

+3V_S5

2

1

Q15

Q15
2N7002K

2N7002K

+3V_S5

2

1

Q14

Q14
2N7002K

2N7002K

DRAMRST_CNTRL_PCH
SMBALERT#

SMB_PCH_CLK
SMB_PCH_DAT
SMB_ME0_CLK
SMB_ME0_DAT
SML1ALERT#_R

E12
H14
C9

A12
C8
G12

C13
E14
M16

M7

T11

P10

M10

AB37
AB38

AV22
AU22

AM12
AM13

BF18
BE18

BJ30
BG30

G24
E24

AK7
AK5

K45

H45

V47
V49

Y47

K43
F47
H47
K49

R244

R244

2.2K_4

2.2K_4

SMB_ME1_CLK

R240

R240

2.2K_4

2.2K_4

SMB_ME1_DAT

1

SMBALERT#
SMB_PCH_CLK
SMB_PCH_DAT

DRAMRST_CNTRL_PCH
SMB_ME0_CLK
SMB_ME0_DAT

SML1ALERT#_R
SMB_ME1_CLK
SMB_ME1_DAT

CL_CLK1

CL_DATA1

CL_RST1#

CLK_PEGA_REQ#

CLK_BUF_PCIE_3GPLLN
CLK_BUF_PCIE_3GPLLP

CLK_BUF_BCLKN
CLK_BUF_BCLKP

CLK_BUF_DREFCLKN
CLK_BUF_DREFCLKP

CLK_BUF_DREFSSCLKN
CLK_BUF_DREFSSCLKP

CLK_PCH_14M

CLK_PCI_FB

XTAL25_IN
XTAL25_OUT

XCLK_RCOMP

SKU_ID1

48M_CLK_CR

SMBus(PCH)

TP51TP51

TP118TP118

C25

SMB_PCH_CLK 25
SMB_PCH_DAT 25

DRAMRST_CNTRL_PCH 13,14,15

For LAN

R512 *0_4R512 *0_4

SML1ALERT# 10,33

For EC

TP57TP57

TP58TP58

TP52TP52

CLK_PEGA_REQ# 16

CLK_PCIE_VGA# 16
CLK_PCIE_VGA 16

CLK_CPU_BCLKN 3
CLK_CPU_BCLKP 3

CLK_DPLL_SSCLKN 3
CLK_DPLL_SSCLKP 3

R454

R454
1M_4

1M_4

R450 90.9/F_4R450 90.9/F_4

SMB_PCH_DAT

SMB_PCH_CLK

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

+1.05V

Zero_ODD_ID 10
BOARD_ID4 10,33

TP156TP156

+3V

S5 S0

2

3

1

Q16

Q16
2N7002K

2N7002K

+3V

2

3

1

Q17

Q17
2N7002K

2N7002K

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

Panther Point 3/6

Panther Point 3/6

Panther Point 3/6

Wednesday, February 08, 2012

Wednesday, February 08, 2012

Wednesday, February 08, 2012

1

21

R580

R580

4.7K_4

4.7K_4

R579

R579

4.7K_4

4.7K_4

ZQS 45W

ZQS 45W

ZQS 45W

C553 27p/50V_4C5 53 27p/50V_4

C552 27p/50V_4C5 52 27p/50V_4

09

Y2
25MHzY225MHz

CLK_SDATA 13,14,26,33

CLK_SCLK 13,1 4,26,33

9 46

9 46

9 46

3C

3C

3C

5

4

3

2

1

+3V
+3V_S57,8,9,11,15,16,29,31,33,36,37,38,43,44

S_GPIO

SIO_EXT_SMI#34

D D

C28 Change PCH_GPIO27 to WK_GPIO27. 01/12 C14 Change R234 from mount to reserve. 12/27

C C

B B

SATA2GP : strap for reserved at chklist 1.2
SATA3GP : strap for reserved at chklist 1.2
NOTE: The internal pull-down is disabled after PLTRST# deasserts.
NOTE: This signal should not be pulled high when strap is sampled.

A A

R268 100K_4R268 100K_4

FDI TERMINATION
VOLTAGE OVERRIDE

SIO_EXT_SCI#34

PCH_GPIO158

SKU_ID09

DGPU_PW ROK20

WK_GPIO2734
PLL_ODVR_EN8

dGPU_VRON41,42

SML1ALERT#9,33

FDI_OVRVLTG DMI_OVRVLTG G_Sensor_ID#

LOW - Tx, Rx terminated
to same voltage

5

TP55TP55

R281 *1K_4R281 *1K_4

SIO_EXT_SMI#
USB_Charger_ID
SIO_EXT_SCI#

G_Sensor_ID#
PCH_GPIO24
WK_GPIO27
PLL_ODVR_EN
STP_PCI#

DMI_OVRVLTG
FDI_OVRVLTG
MFG_MODE
BOARD_ID0
TEST_SET_UP

R561 *SHORT_4R561 *SHORT_4

SV_DET_NC

DMI TERMINATION
VOLTAGE OVERRIDE

CPT/PPT (GPIO,VSS_NCTF,RSVD)

U21F

U21F

R266 100_4R266 100_4

CRIT_TEMP_REP#

T7

BMBUSY# / GPIO0

A42

TACH1 / GPIO1

H36

TACH2 / GPIO6

E38

TACH3 / GPIO7

C10

GPIO8

C4

LAN_PHY_PWR_CTRL / GPIO12

G2

GPIO15

U2

SATA4GP / GPIO16

D40

TACH0 / GPIO17

T5

SCLOCK / GPIO22

E8

GPIO24 / MEM_LED

E16

GPIO27

P8

GPIO28

K1

STP_PCI# / GPIO34

K4

GPIO35

V8

SATA2GP / GPIO36

M5

SATA3GP / GPIO37

N2

SLOAD / GPIO38

M3

SDATAOUT0 / GPIO39

V13

SDATAOUT1 / GPIO48

V3

SATA5GP / GPIO49

D6

GPIO57

A4

VSS_NCTF_1

A44

VSS_NCTF_2

A45

VSS_NCTF_3

A46

VSS_NCTF_4

A5

VSS_NCTF_5

A6

VSS_NCTF_6

B3

VSS_NCTF_7

B47

VSS_NCTF_8

BD1

VSS_NCTF_9

BD49

VSS_NCTF_10

BE1

VSS_NCTF_11

BE49

VSS_NCTF_12

BF1

VSS_NCTF_13

BF49

VSS_NCTF_14

PANTHER POINT

PANTHER POINT

R267 *200K/F_4R267 *200K/F_4

Low = Tx, Rx terminated to
same voltage (DC Coupling Mode)
(DEFAULT)

4

+3V_S5

+3V_S5

DSW
+3V_S5

+3V

+3V_S5

+3V

+3V
+3V
+3V
+3V

+3V

+3V

+3V

+3V_S5

+3V

+3V

+3V

GPIO

GPIO

+3V_S5

+3V

+3V
+3V

+3V

+3V
+3V

+3V

NCTF

NCTF

+3V+3V +3V

TACH4 / GPIO68
TACH5 / GPIO69
TACH6 / GPIO70
TACH7 / GPIO71

PROCPWRGD

THRMTRIP#

CPU/MISC

CPU/MISC

VSS_NCTF_15
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21
VSS_NCTF_22
VSS_NCTF_23
VSS_NCTF_24
VSS_NCTF_25
VSS_NCTF_26
VSS_NCTF_27
VSS_NCTF_28
VSS_NCTF_29
VSS_NCTF_30
VSS_NCTF_31
VSS_NCTF_32

C40
B41
C41
A40

P4

A20GATE

AU16

PECI

P5

RCIN#

AY11
AY10
T14

INIT3_3V#

AY1

DF_TVS

AH8

TS_VSS1

AK11

TS_VSS2

AH10

TS_VSS3

AK10

TS_VSS4

P37

NC_1

BG2
BG48
BH3
BH47
BJ4
BJ44
BJ45
BJ46
BJ5
BJ6
C2
C48
D1
D49
E1
E49
F1
F49

Change BIO_REC to G_Sensor_ID# 10/21
Change MB ID for G-sensor
PCH GPIO22
Pull high=no G-Sensor
Pull low=have G-Sensor

G Sensor ID

BOARD_ID3

R475 10K_4R475 10K_4

SIO_A20GATE
PCH_PECI
SIO_RCIN#

PCH_THRMTRIP#

R290 NGS@10K_4R290 NGS@10K_4

R264 GS@1K_4R264 GS@1K_4

R243 390_4R243 390_4 R280 10K_4R280 10K_4

High = Disable (Default)
Low = Enable

3

TP53TP53

+3V

dGPU_PW _CTRL# 9
CABLE_ID 23

SIO_A20GATE 34

SIO_RCIN# 34
H_PWRGOOD 3
PM_THRMTRIP# 3

DF_TVS 8

USB_Charger_ID

USB Charger------->High
None Charger------->Low

+3V

R160 CH@10K_4R160 CH@10K_4
R174 NCH@10K_4R174 NCH@10K_4

SV_SET_UP

High = Strong (Default)

TEST_SET_UP

SGPIO

S_GPIO

R291 1K_4R291 1K_4
R278 *1K_4R278 *1K_4

MFG-TEST

MFG_MODE

R545 10K_4R545 10K_4

R546 *1K_4R546 *1K_4

2

GPIO Pull-up/Pull-down(CLG)

PCH_GPIO24
PLL_ODVR_EN

SIO_EXT_SMI#
SIO_EXT_SCI#

STP_PCI#
SIO_A20GATE
SIO_RCIN#
CRIT_TEMP_REP#

WK_GPIO27

GPIO27 : If not used then use 8.2-kΩ to 10-kΩ pull-down to GND.

Zero ODD ID

Zero ODD------->High

+3V

USB_Charger_ID

None Zero ODD------->Low

R501 ZP@10K_4R501 ZP@10K_4
R623 NZP@10K_4R623 NZP@10K_4

Reserve for future

+3V

R289 10K_4R289 10K_4 R448 *10K_4R448 *10K_4

R276 *1K_4R276 *1K_4

R544 *10K_4R544 *10K_4

R477 *10K_4R477 *10K_4

BOARD_ID2

8 Layer ------->High *

+3V

+3V

+3V

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet

6 Layer ------->Low

R163 10K_4R163 10K_4

R170 *SP_6L@10K_4R170 *SP_6L@10K_4

Panther Point 4/6

Panther Point 4/6

Panther Point 4/6

Wednesday, February 08, 2012

Wednesday, February 08, 2012

Wednesday, February 08, 2012

BOARD_ID0

BOARD_ID3BOARD_ID3

BOARD_ID3

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

1

10

R271 *10K_4R271 *10K_4
R293 10K_4R293 10K_4

R472 10K_4R472 10K_4
R173 10K_4R173 10K_4

R532 *10K_4R532 *10K_4
R287 10K_4R287 10K_4

R549 10K_4R549 10K_4

R234 *10K_4R234 *10K_4

Zero_ODD_ID 9

R557 *10K_4R557 *10K_4

R476 10K_4R476 10K_4
R440 10K_4R440 10K_4

BOARD_ID4 9,33
BOARD_ID3 33

BOARD_ID2 9

ZQS 45W

ZQS 45W

ZQS 45W

of

10 46

10 46

10 46

+3V_S5

+3V

+3V

3C

3C

3C

5

4

3

2

1

PCH5(CLG)

??mA(??mils)

+5V_S5
+3V_S5

+5V
+3V

+3V_S5

+3V

+1.05V

+1.05V

11

CPT/PPT (POWER)

POWER

POWER

U21G

+1.05V +1.05V_PCH_VCC

R261 0.00 2/F_1206R261 0.002/F_1206

D D

C C

B B

A A

R5285 near PCH ball for VCCP GND sense

+1.05V +1.05V_VCCAPLL_EXP

+1.05V +1.05V_VCCIO

+1.05V

R215 *SHORT_6R215 *SHORT_6

L37 *1uH/25mA_6L37 *1uH/25mA_6

R516 0.00 2/F_1206R516 0.002/F_1206

+1.5V

+1.05V_PCH_VCCDPLL_EXP+1.05V

R272 0_6R272 0_6
R263 *0_6R263 *0_6

+1.05V

+VCCAFDI_VRM

VccCORE =1.3 A(60mils)

C279

C279
1u/6.3V_4

1u/6.3V_4

C588

C588
*10u/6.3V_6

*10u/6.3V_6

VccIO =2.925 A(140mils)

C313

C313

C299

C299

1u/6.3V_4

1u/6.3V_4

1u/6.3V_4

1u/6.3V_4

C298

C298
1u/6.3V_4

1u/6.3V_4

R493 *SHORT_8R493 *SHORT_8

+VCCAFDI_VRM

R236 *0 _8R236 *0_8

R231 *SHORT_8R231 *SHORT_8

+1.1V_VCC_DMI

VCCVRM: 1.8V (Destop)

1.5V (Mobile)

+3V_S57,8,9,10,15,16,29,31,33,36,37,38 ,43,44
+5V_S527,31,36,37,38,39,40,41,45,46

+1.5VSUS13,14,15,39 ,42,46

+5V8,23,24,26,27,33,36,43,46
+3V

+1.5V25,39,43
+1.05V3,5,7,8,9,23,34,37,38,42,43,46
+1.8V5,8,43,46

+3V_RTC8

C280

C280
1u/6.3V_4

1u/6.3V_4

+3V_VCC_EXP+3V

C273

C273
1u/6.3V_4

1u/6.3V_4

C303

C303
1u/6.3V_4

1u/6.3V_4

C309

C309
10u/6.3V_6

10u/6.3V_6

C579

C579

0.1u/10V_4

0.1u/10V_4

+VCCAFDI_VRM

+1.05V_VCCAPLL_FDI

+1.05V_VCCDPLL_FDI

C269

C269
10u/6.3V_6

10u/6.3V_6

AA23
AC23
AD21
AD23
AF21
AF23
AG21
AG23
AG24
AG26
AG27
AG29
AJ23
AJ26
AJ27
AJ29
AJ31

AN19

BJ22

AN16
AN17

AN21
AN26
AN27
AP21
AP23
AP24
AP26
AT24

AN33
AN34

BH29

AP16

BG6

AP17

AU20

U21G

VCCCORE[1]
VCCCORE[2]
VCCCORE[3]
VCCCORE[4]
VCCCORE[5]
VCCCORE[6]
VCCCORE[7]
VCCCORE[8]
VCCCORE[9]
VCCCORE[10]
VCCCORE[11]
VCCCORE[12]
VCCCORE[13]
VCCCORE[14]
VCCCORE[15]
VCCCORE[16]
VCCCORE[17]

VCCIO[28]

VCCAPLLEXP

VCCIO[15]
VCCIO[16]

VCCIO[17]
VCCIO[18]
VCCIO[19]
VCCIO[20]
VCCIO[21]
VCCIO[22]
VCCIO[23]
VCCIO[24]

VCCIO[25]
VCCIO[26]

VCC3_3[3]

VCCVRM[2]

VccAFDIPLL

VCCIO[27]

VCCDMI[2]

PANTHER POINT

PANTHER POINT

CRTLVDS

CRTLVDS

VCC CORE

VCC CORE

DMI

DMI

VCCIO

VCCIO

DFT / SPI HVCMOS

DFT / SPI HVCMOS

FDI

FDI

VCCADAC

VSSADAC

VCCALVDS

VSSALVDS

VCCTX_LVDS[1]
VCCTX_LVDS[2]
VCCTX_LVDS[3]
VCCTX_LVDS[4]

VCC3_3[6]

VCC3_3[7]

VCCVRM[3]

VCCDMI[1]

VCCCLKDMI

VCCDFTERM[1]

VCCDFTERM[2]

VCCDFTERM[3]

VCCDFTERM[4]

VCCSPI

U48

U47

AK36
AK37

AM37
AM38
AP36
AP37

V33

V34

AT16

AT20

AB36

AG16

AG17

AJ16

AJ17

V1

VccADAC =1mA(8mils)

C231

C231

22u/6.3V_8

22u/6.3V_8

VccALVDS=1mA(8mils)

When Dis sku, LVDS power can short to GND

VccTX_LVDS=60mA(10mils)

C265

C265

IOP@0.01u/25V_4

IOP@0.01u/25V_4

R200 *SHORT_6R200 *SHORT_6

C268

C268

0.1u/10V_4

0.1u/10V_4

+VCCAFDI_VRM

C545

C545

C246

C246

*10u/6.3V_6

*10u/6.3V_6

1u/6.3V_4

1u/6.3V_4

R253 *SHORT_8R253 *SHORT_8

C329

C329

0.1u/10V_4

0.1u/10V_4

VCCSPI = 20mA(8mils)

+3V_VCCME_SPI

R296 NSBA@0_6R296 NSBA@0_6

R642 *SBA@0_6R64 2 *SBA@0_6

C342

C342
1u/6.3V_4

1u/6.3V_4

+VCCA_DAC_1_2

C248

C248

C247

C247

0.01u/25V_4

0.01u/25V_4

0.1u/10V_4

0.1u/10V_4

+VCCALVDS +3V

C549

C549

C264

C264

IOP@22u/6.3V_8

IOP@22u/6.3V_8

IOP@0.01u/25V_4

IOP@0.01u/25V_4

+3V+3V_VCC_GIO

VCCDMI = 42mA(10mils)

+1.1V_VCC_DMI

+VCCAFDI_VRM

VCCCLKDMI = 20mA(8mils)

+VCC_DMI_CCI +1.05V+1.1V_VCC_DMI_CCI

L33

L33

*10uH/100mA_8

*10uH/100mA_8

+1.8V+VCCP_NAND

VCCPNAND = 190 mA(15mils)

+3V_S5

Reserve +3V_S5 to VCCSPI for EC 795

+3V_M

+3V_M for SBA function.

L16

L16

BKP1608HS181-T/180ohm/1.5A_6

BKP1608HS181-T/180ohm/1.5A_6

C236

C236
10u/6.3V_6

10u/6.3V_6

R203 IOP@0_4R20 3 IOP@0_4
R201 EV@0_4R201 EV@0_4

L34

L34

IOP@0.1uH/250mA_8

IOP@0.1uH/250mA_8

R439 EV@0_4R439 EV@0_4

R224 *SHORT_4R224 *SHORT_4

C304

C304
1u/6.3V_4

1u/6.3V_4

R435 *1/F_4R435 *1/F_4
R434 0_4R434 0_4

+3V

Change R230 from shortpad to 0Ω, add 0Ω R636 connect to +3VPCU. 01/05C20

+1.8V+VCC_TX_LVDS

+1.05V

L38 *10uH/100mA_8L38 *10uH/100mA_8

VCCME(+1.05V) = ??A(??mils)

+1.05V

+1.05V

VCCRTC<1mA(8mils)

R550 NSBA@0.002 /F_1206R550 NSBA@0.002/F_1206

+1.05V_M

R633 *SBA@0_ 8R633 *SBA@0_8

+1.05V_M for SBA function.

+1.05V

+1.05V

+1.05V_M

+1.05V_M for SBA function.

+1.05V

1mA(8mils)

+3V_RTC

+3V

R151 1/F_4R15 1 1/F_4

+3VPCU

+3V_S5

+VCCAPLL_CPY_PCH

+1.05V_VCCEPW

R563 *SHORT_6R563 *SHORT_6

R164 *SHORT_6R164 *SHORT_6

R436 *SHORT_6R436 *SHORT_6

R217 *NSBA@0_6R217 *NSBA@0_6

R634

R634
*SBA@0_6

*SBA@0_6

R510 *SHORT_4R510 *SHORT_4

L15 10uH/100mA_8L15 10uH/100mA_8

R449 *0 _8R449 *0_8

+1.05V

R636 *0_4R636 *0_4

VCCDSW3_3= 3mA

R230 0_4R230 0_4

C305

C305

0.1u/10V_4

0.1u/10V_4

R441 *SHORT_6R441 *SHORT_6

+1.05V

C589

C589
*10u/6.3V_6

*10u/6.3V_6

VccASW =1.01 A(60mils)

C275

C275

C271

C271

1u/6.3V_4

1u/6.3V_4

1u/6.3V_4

1u/6.3V_4

C626

C626
22u/6.3V_8

22u/6.3V_8

C628

C628
1u/6.3V_4

1u/6.3V_4

C259

C259
1u/6.3V_4

1u/6.3V_4

C542

C542
1u/6.3V_4

1u/6.3V_4

C296

C296
*1u/6.3V_4

*1u/6.3V_4

C598

C598

4.7u/6.3V_6

4.7u/6.3V_6

C300

C300
1u/6.3V_4

1u/6.3V_4

C312 0.1u/10V_4C312 0.1u/10V_4

65mA(10mils)
8mA(8mils)

VCCDIFFCLKN= 55mA(10mils)

VCCSSC= 95mA(10mils)

C311 0.1u/10V_4C311 0.1u/10V_4

C597

C597

0.1u/10V_4

0.1u/10V_4

C314

C314

0.1u/10V_4

0.1u/10V_4

C241

C241
10u/6.3V_6

10u/6.3V_6

C270

C270
1u/6.3V_4

1u/6.3V_4

C282

C282
22u/6.3V_8

22u/6.3V_8

+VCCAFDI_VRM

C600

C600

0.1u/10V_4

0.1u/10V_4

C315

C315

0.1u/10V_4

0.1u/10V_4

C325

C325
*0.1u/10V_4

*0.1u/10V_4

C278

C278
*1u/6.3V_4

*1u/6.3V_4

+V1.05M_VCCSUS
+VTT_VCCPCPU

+3V_SUS_CLKF33

C244

C244
1u/10V_4

1u/10V_4

CPT/PPT (POWER)

+VCCACLK

AD49

+VCCPDSW

PCH_VCCDSW

+3V_SUS_CLKF33

BH23

+VCCDPLL_CPY

AL29

+VCCSUS1

AL24

AA19
AA21
AA24
AA26
AA27
AA29
AA31
AC26
AC27
AC29
AC31
AD29
AD31

+VCCRTCEXT

+VCCAFDI_VRM

+1.05V_VCCA_A_DPL
+1.05V_VCCA_B_DPL

+VCCDIFFCLK
+VCCDIFFCLKN

+V1.05V_SSCVCC

+VCCSST

BD47
BF47

AF17
AF33
AF34
AG34

AG33

T16

V12

T38

W21
W23
W24
W26
W29
W31
W33

N16

Y49

V16

T17
V19

BJ8

A22

U21J

U21J

VCCACLK

VCCDSW3_3

DCPSUSBYP

VCC3_3[5]

VCCAPLLDMI2
VCCIO[14]

DCPSUS[3]

VCCASW[1]
VCCASW[2]
VCCASW[3]
VCCASW[4]
VCCASW[5]
VCCASW[6]
VCCASW[7]
VCCASW[8]
VCCASW[9]
VCCASW[10]
VCCASW[11]
VCCASW[12]
VCCASW[13]
VCCASW[14]
VCCASW[15]
VCCASW[16]
VCCASW[17]
VCCASW[18]
VCCASW[19]
VCCASW[20]

DCPRTC

VCCVRM[4]

VCCADPLLA
VCCADPLLB

VCCIO[7]
VCCDIFFCLKN[1]
VCCDIFFCLKN[2]
VCCDIFFCLKN[3]

VCCSSC

DCPSST

DCPSUS[1]
DCPSUS[2]

V_PROC_IO

VCCRTC

PANTHER POINT

PANTHER POINT

+1.05V

POWER

POWER

VCCSUS3_3[10]

Clock and Miscellaneous

Clock and Miscellaneous

PCI/GPIO/LPCMISC

PCI/GPIO/LPCMISC

SATA USB

SATA USB

CPURTC

CPURTC

HDA

HDA

L36 10uH/100mA_8L36 10uH/100mA_8

L35 10uH/100mA_8L35 10uH/100mA_8

Change C562, C564 from 220U to 100U for cost down. 02/08C38

VCCIO[29]
VCCIO[30]
VCCIO[31]
VCCIO[32]
VCCIO[33]

VCCSUS3_3[7]
VCCSUS3_3[8]
VCCSUS3_3[9]

VCCSUS3_3[6]

VCCIO[34]

V5REF_SUS

DCPSUS[4]

VCCSUS3_3[1]

V5REF

VCCSUS3_3[2]
VCCSUS3_3[3]
VCCSUS3_3[4]
VCCSUS3_3[5]

VCC3_3[1]
VCC3_3[8]
VCC3_3[4]

VCC3_3[2]

VCCIO[5]

VCCIO[12]
VCCIO[13]

VCCIO[6]

VCCAPLLSATA

VCCVRM[1]

VCCIO[2]
VCCIO[3]
VCCIO[4]

VCCASW[22]

VCCASW[23]

VCCASW[21]

VCCSUSHDA

N26
P26
P28
T27
T29

+3V_VCCPUSB

T23
T24
V23
V24

+3V_VCCAUBG

P24

+VCCAUPLL

T26

+5V_PCH_VCC5REFSUS

M26

+VCCA_USBSUS

AN23

+3V_VCCPSUS

AN24

+5V_PCH_VCC5REF

P34

N20
N22

+3V_VCCPSUS

P20
P22

AA16

+3V_VCCPCORE

W16
T34

C239

C239

0.1u/10V_4

0.1u/10V_4

AJ2

AF13

+V1.05S_SATA3

AH13
AH14

AF14

+V1.1LAN_VCCAPLL

AK1

VCCVRM= 114mA(15mils)

+VCCAFDI_VRM

AF11

AC16
AC17
AD17

VCCME = 1.01A(60mils)

T21

V21

T19

+V3.3A_1.5A_HDA_IO

P32

C559

C559
*1u/6.3V_4

*1u/6.3V_4

12

C564

C564

100U/6.3V_3528

100U/6.3V_3528

12

C562

C562

100U/6.3V_3528

100U/6.3V_3528

R223 *SHORT_6R223 *SHORT_6

C294

C294
*1u/6.3V_4

*1u/6.3V_4

+3V

R222 *SHORT_6R222 *SHORT_6

C310

C310
1u/6.3V_4

1u/6.3V_4

C560

C560

0.1u/10V_4

0.1u/10V_4

+1.05V_VCCA_A_DPL

C566

C566
1u/6.3V_4

1u/6.3V_4

+1.05V_VCCA_B_DPL

C554

C554
1u/6.3V_4

1u/6.3V_4

R211 *SHORT_8R211 *SHORT_8

C274

C274
1u/6.3V_4

1u/6.3V_4

R228 *SHORT_6R228 *SHORT_6

C308

C308

0.1u/10V_4

0.1u/10V_4

R216 *SHORT_6R216 *SHORT_6

C281

C281

0.1u/10V_4

0.1u/10V_4

C272

C272

0.1u/10V_4

0.1u/10V_4

C266

C266
1u/6.3V_4

1u/6.3V_4

C297

C297
1u/10V_4

1u/10V_4

C341

C341

0.1u/10V_4

0.1u/10V_4

C330

C330

0.1u/10V_4

0.1u/10V_4

C323

C323
1u/10V_4

1u/10V_4

C606

C606
*10u/6.3V_6

*10u/6.3V_6

R463 *0_4R463 *0_4
R462 0_4R462 0_ 4

+1.05V+1.05V_VCCUSBCORE

VCCSUS3_3 = 119mA(15mils)

+3V_S5

+1.05V

VCC5REFSUS=1mA

R233 10 /F_4R233 10/F_4

D3 RB500V-40D3 RB500V- 40

V5REF= 1mA

R141 10 /F_4R141 10/F_4

D2 RB500V-40D2 RB500V- 40

R235 *SHORT_6R235 *SHORT_6

VCCSUS3_3 = 119mA(15mils)

R285 *SHORT_6R285 *SHORT_6

VCCPCORE = 28mA(10mils)

+3V

R254 *SHORT_8R254 *SHORT_8

L39

L39

*10uH/100mA_8

*10uH/100mA_8

+1.05V

+1.05V_VCCEPW

+1.5VSUS

VCCSUSHDA= 10mA(8mils)

+3V_S5

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

ZQS 45W

PROJECT :

ZQS 45W

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Panther Point 5/6

Panther Point 5/6

Panther Point 5/6

Wednesday, February 08, 2012

Date: Sheet o f

Wednesday, February 08, 2012

Date: Sheet o f

Wednesday, February 08, 2012

5

4

3

2

Date: Sheet

1

ZQS 45W

11 46

11 46

11 46

3C

3C

3C

of

5

4

3

2

1

PCH6(CLG)

12

U21I

U21I

AY4

VSS[159]

IBEX PEAK-M (GND)

D D

U21H

U21H

H5

VSS[0]

AA17

VSS[1]

AA2

VSS[2]

AA3

VSS[3]

AA33

VSS[4]

AA34

VSS[5]

AB11

VSS[6]

AB14

VSS[7]

AB39

VSS[8]

AB4

VSS[9]

AB43

VSS[10]

AB5

VSS[11]

AB7

VSS[12]

AC19

VSS[13]

AC2

VSS[14]

AC21

VSS[15]

AC24

VSS[16]

AC33

VSS[17]

AC34

VSS[18]

AC48

C C

B B

A A

5

AD10
AD11
AD12
AD13
AD19
AD24
AD26
AD27
AD33
AD34
AD36
AD37
AD38
AD39

AD4
AD40
AD42
AD43
AD45
AD46

AD8

AE2

AE3
AF10
AF12
AD14
AD16
AF16
AF19
AF24
AF26
AF27
AF29
AF31
AF38

AF4
AF42
AF46

AF5

AF7

AF8
AG19

AG2
AG31
AG48
AH11

AH3
AH36
AH39
AH40
AH42
AH46

AH7

AJ19
AJ21
AJ24
AJ33
AJ34

AK12

AK3

VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]

PANTHER POINT

PANTHER POINT

VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]

VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]

AK38
AK4
AK42
AK46
AK8
AL16
AL17
AL19
AL2
AL21
AL23
AL26
AL27
AL31
AL33
AL34
AL48
AM11
AM14
AM36
AM39
AM43
AM45
AM46
AM7
AN2
AN29
AN3
AN31
AP12
AP19
AP28
AP30
AP32
AP38
AP4
AP42
AP46
AP8
AR2
AR48
AT11
AT13
AT18
AT22
AT26
AT28
AT30
AT32
AT34
AT39
AT42
AT46
AT7
AU24
AU30
AV16
AV20
AV24
AV30
AV38
AV4
AV43
AV8
AW14
AW18
AW2
AW22
AW26
AW28
AW32
AW34
AW36
AW40
AW48
AV11
AY12
AY22
AY28

4

AY42
AY46

AY8
B11
B15
B19
B23
B27
B31
B35
B39

BB12
BB16
BB20
BB22
BB24
BB28
BB30
BB38

BB4
BB46
BC14
BC18

BC2
BC22
BC26
BC32
BC34
BC36
BC40
BC42
BC48
BD46

BD5
BE22
BE26
BE40
BF10
BF12
BF16
BF20
BF22
BF24
BF26
BF28

BD3
BF30
BF38
BF40

BF8
BG17
BG21
BG33
BG44

BG8
BH11
BH15
BH17
BH19

H10
BH27
BH31
BH33
BH35
BH39
BH43

BH7

D12

D16

D18

D22

D24

D26

D30

D32

D34

D38

D42

E18

E26

G18

G20

G26

G28

G36

G48

H12

H18

H22

H24

H26

H30

H32

H34

B7

F45

D3

D8

F3

VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]
VSS[199]
VSS[200]
VSS[201]
VSS[202]
VSS[203]
VSS[204]
VSS[205]
VSS[206]
VSS[207]
VSS[208]
VSS[209]
VSS[210]
VSS[211]
VSS[212]
VSS[213]
VSS[214]
VSS[215]
VSS[216]
VSS[217]
VSS[218]
VSS[219]
VSS[220]
VSS[221]
VSS[222]
VSS[223]
VSS[224]
VSS[225]
VSS[226]
VSS[227]
VSS[228]
VSS[229]
VSS[230]
VSS[231]
VSS[232]
VSS[233]
VSS[234]
VSS[235]
VSS[236]
VSS[237]
VSS[238]
VSS[239]
VSS[240]
VSS[241]
VSS[242]
VSS[243]
VSS[244]
VSS[245]
VSS[246]
VSS[247]
VSS[248]
VSS[249]
VSS[250]
VSS[251]
VSS[252]
VSS[253]
VSS[254]
VSS[255]
VSS[256]
VSS[257]
VSS[258]

PANTHER POINT

PANTHER POINT

3

VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]
VSS[302]
VSS[303]
VSS[304]
VSS[305]
VSS[306]
VSS[307]
VSS[308]
VSS[309]
VSS[310]
VSS[311]
VSS[312]
VSS[313]
VSS[314]
VSS[315]
VSS[316]
VSS[317]
VSS[318]
VSS[319]
VSS[320]
VSS[321]
VSS[322]
VSS[323]
VSS[324]
VSS[325]
VSS[328]
VSS[329]
VSS[330]
VSS[331]
VSS[333]
VSS[334]
VSS[335]
VSS[337]
VSS[338]
VSS[340]
VSS[342]
VSS[343]
VSS[344]
VSS[345]
VSS[346]
VSS[347]
VSS[348]
VSS[349]
VSS[350]
VSS[351]
VSS[352]

H46
K18
K26
K39
K46
K7
L18
L2
L20
L26
L28
L36
L48
M12
P16
M18
M22
M24
M30
M32
M34
M38
M4
M42
M46
M8
N18
P30
N47
P11
P18
T33
P40
P43
P47
P7
R2
R48
T12
T31
T37
T4
W34
T46
T47
T8
V11
V17
V26
V27
V29
V31
V36
V39
V43
V7
W17
W19
W2
W27
W48
Y12
Y38
Y4
Y42
Y46
Y8
BG29
N24
AJ3
AD47
B43
BE10
BG41
G14
H16
T36
BG22
BG24
C22
AP13
M14
AP3
AP1
BE16
BC16
BG28
BJ28

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Wednesday, February 08, 2012

Date: Sheet of

Wednesday, February 08, 2012

Date: Sheet of

2

Wednesday, February 08, 2012

PROJECT :

Panther Point 6/6

Panther Point 6/6

Panther Point 6/6

ZQS 45W

ZQS 45W

ZQS 45W

12 46

12 46

12 46

1

3C

3C

3C

5

M_A_A[15:0]4

D D

M_A_BS#04
M_A_BS#14
M_A_BS#24
M_A_CS#04
M_A_CS#14
M_A_CLK04
M_A_CLK0#4
M_A_CLK14
M_A_CLK1#4
M_A_CKE04
M_A_CKE14
M_A_CAS#4
M_A_RAS#4

R208 10K_4R208 10K_4
R207 10K_4R207 10K_4

C C

B B

M_A_WE#4

CLK_SCLK9,14,26,33

CLK_SDATA9,14,26,33

M_A_ODT04
M_A_ODT14

M_A_DQS[7:0]4

M_A_DQS#[7:0]4

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15

DIMM0_SA0
DIMM0_SA1
CLK_SCLK
CLK_SDATA

M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7

107

119

109
108

114
121
101
103
102
104

115
110
113
197
201
202
200

116
120

136
153
170
187

137
154
171
188

135
152
169
186

98
97
96
95
92
91
90
86
89
85

84
83

80
78

79

73
74

11
28
46
63

12
29
47
64

10
27
45
62

JDIM1A

JDIM1A

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
A14
A15

BA0
BA1
BA2
S0#
S1#
CK0
CK0#
CK1
CK1#
CKE0
CKE1
CAS#
RAS#
WE#
SA0
SA1
SCL
SDA

ODT0
ODT1

DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7

DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS#0
DQS#1
DQS#2
DQS#3
DQS#4
DQS#5
DQS#6
DQS#7

4

M_A_DQ4
M_A_DQ0
M_A_DQ2
M_A_DQ3
M_A_DQ1
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ12
M_A_DQ13
M_A_DQ11
M_A_DQ10
M_A_DQ8
M_A_DQ9
M_A_DQ14
M_A_DQ15
M_A_DQ17
M_A_DQ20
M_A_DQ18
M_A_DQ19
M_A_DQ16
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ28
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ29
M_A_DQ31
M_A_DQ30
M_A_DQ36
M_A_DQ33
M_A_DQ34
M_A_DQ39
M_A_DQ32
M_A_DQ37
M_A_DQ38
M_A_DQ35
M_A_DQ45
M_A_DQ44
M_A_DQ40
M_A_DQ42
M_A_DQ47
M_A_DQ41
M_A_DQ46
M_A_DQ43
M_A_DQ53
M_A_DQ52
M_A_DQ50
M_A_DQ55
M_A_DQ49
M_A_DQ48
M_A_DQ54
M_A_DQ51
M_A_DQ56
M_A_DQ57
M_A_DQ62
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ63
M_A_DQ58

PC2100 DDR3 SDRAM SO-DIMM

PC2100 DDR3 SDRAM SO-DIMM

5

DQ0

7

DQ1

15

DQ2

17

DQ3

4

DQ4

6

DQ5

16

DQ6

18

DQ7

21

DQ8

23

DQ9

33

DQ10

35

DQ11

22

DQ12

24

DQ13

34

DQ14

36

DQ15

39

DQ16

41

DQ17

51

DQ18

53

DQ19

40

DQ20

42

DQ21

50

DQ22

52

DQ23

57

DQ24

59

DQ25

67

DQ26

69

DQ27

56

DQ28

58

DQ29

68

DQ30

70

DQ31

129

DQ32

131

DQ33

141

DQ34

143

DQ35

130

DQ36

132

DQ37

140

DQ38

142

DQ39

147

DQ40

149

DQ41

157

DQ42

159

DQ43

146

DQ44

148

DQ45

158

DQ46

(204P)

(204P)

160

DQ47

163

DQ48

165

DQ49

175

DQ50

177

DQ51

164

DQ52

166

DQ53

174

DQ54

176

DQ55

181

DQ56

183

DQ57

191

DQ58

193

DQ59

180

DQ60

182

DQ61

192

DQ62

194

DQ63

3

M_A_DQ[63:0] 4

M3 solution

SMDDR_VREF_DQ0_M35

+SMDDR_VREF

+SMDDR_VREF_DIMM

change to 1K/F_4

R188 *0_6R188 *0_6

R204 *10K_4R204 *10K_4

+3V

DDR3_DRAMRST#14,15

R226 *M3@0_6R226 *M3@0_6

+1.5VSUS

R213

R213
1K/F_4

1K/F_4

R218

R218
1K/F_4

1K/F_4

+1.5VSUS

2.48A

+3V

PM_EXTTS#0

+SMDDR_VREF_DQ0

+SMDDR_VREF_DIMM

C307

C307
470p/50V_4

470p/50V_4

2

+SMDDR_VREF_DIMM 14

JDIM1B

JDIM1B

75

VDD1

76

VDD2

81

VDD3

82

VDD4

87

VDD5

88

VDD6

93

VDD7

94

VDD8

99

VDD9

100

VDD10

105

VDD11

106

VDD12

111

VDD13

112

VDD14

117

VDD15

118

VDD16

123

VDD17

124

VDD18

199

VDDSPD

77

NC1

122

NC2

125

NCTEST

198

EVENT#

30

RESET#

1

VREF_DQ

126

VREF_CA

2

VSS1

3

VSS2

8

VSS3

9

VSS4

13

VSS5

14

VSS6

19

VSS7

20

VSS8

25

VSS9

26

VSS10

31

VSS11

32

VSS12

37

VSS13

38

VSS14

43

VSS15

DDR3-DIMM1_H=9.2_Reverse

DDR3-DIMM1_H=9.2_Reverse

+1.5VSUS

PC2100 DDR3 SDRAM SO-DIMM

PC2100 DDR3 SDRAM SO-DIMM

(204P)

(204P)

VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52

VTT1
VTT2

GND
GND

44
48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196

203
204

205
206

1

+0.75V_DDR_VTT

R198

DDR3-DIMM1_H=9.2_Reverse

DDR3-DIMM1_H=9.2_Reverse

M1 solution

Place these Caps near So-Dimm0.

+1.5VSUS

C251

C253

C253

0.1u/16V_4

0.1u/16V_4

C258

C258
1u/6.3V_4

1u/6.3V_4

C251

0.1u/16V_4

0.1u/16V_4

C250

C250

0.1u/16V_4

0.1u/16V_4

C289

C289

0.1u/16V_4

0.1u/16V_4

C263

C263
1u/6.3V_4

1u/6.3V_4

C287

C287

0.1u/16V_4

0.1u/16V_4

C276

C276
1u/6.3V_4

1u/6.3V_4

+

+

C285

C288

C288
10u/6.3V_6

10u/6.3V_6

C283

C283

0.1u/16V_4

0.1u/16V_4

C285
10u/6.3V_6

10u/6.3V_6

+0.75V_DDR_VTT

C290

C249

C249
10u/6.3V_6

10u/6.3V_6

C277

C277

2.2u/6.3V_6

2.2u/6.3V_6

C290
10u/6.3V_6

10u/6.3V_6

5

C252

C252
10u/6.3V_6

10u/6.3V_6

C254

C254

10u/6.3V_6

10u/6.3V_6

A A

+3V

C302

C302

C345

C345
*330u/2V_7343

*330u/2V_7343

0.1u/16V_4

0.1u/16V_4

C284

C284
1u/6.3V_4

1u/6.3V_4

4

+SMDDR_VREF_DIMM

C293

C293

2.2u/6.3V_6

2.2u/6.3V_6

C577

C577

4.7u/6.3V_6

4.7u/6.3V_6

+SMDDR_VREF_DQ0

C295

C295

0.1u/16V_4

0.1u/16V_4

C580

C580

4.7u/6.3V_6

4.7u/6.3V_6

2.2u/6.3V_6

2.2u/6.3V_6

C583

C583

4.7u/6.3V_6

4.7u/6.3V_6

C301

C301

3

+SMDDR_VREF

SMDDR_VREF_DQ0_M3

REV:B Add

DRAMRST_CNTRL_PCH9,14,15

+1.5VSUS11,14,15,39,42,46

+3V3,7,8,9,10,11,14,16,20,23,24,25,26,27,29,33,34,36,37,38,39,40,41,42,43,45,46

+0.75V_DDR_VTT14,39,43

+SMDDR_VREF14,15,39

1

Mount Q12 at SBA sku. 01/17C34

R193 *0_6R193 *0_6

3

Q12

Q12

2

SBA@AP2302GN

SBA@AP2302GN

2

R198
1K/F_4

1K/F_4

change to 1K/F_4

+SMDDR_VREF_DQ0

C286

C286
470p/50V_4

470p/50V_4

R209

R209
1K/F_4

1K/F_4

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

DDRIII SO-DIMM-0

DDRIII SO-DIMM-0

DDRIII SO-DIMM-0

Date: Sheet of

Date: Sheet of

Date: Sheet of

PROJECT :

ZQS 45W

ZQS 45W

ZQS 45W

1

13 46Wednesday, February 08, 2012

13 46Wednesday, February 08, 2012

13 46Wednesday, February 08, 2012

3C

3C

3C

5

4

3

2

1

M_B_A[15:0]4

D D

M_B_BS#04
M_B_BS#14
M_B_BS#24
M_B_CS#04
M_B_CS#14
M_B_CLK04
M_B_CLK0#4
M_B_CLK14
M_B_CLK1#4
M_B_CKE04
M_B_CKE14
M_B_CAS#4
M_B_RAS#4

CLK_SCLK9,13,26,33

CLK_SDATA9,13,26,33

M_B_ODT04
M_B_ODT14

M_B_DQS[7:0]4

M_B_DQS#[7:0]4

C320

C320
10u/6.3V_6

10u/6.3V_6

+0.75V_DDR_VTT

M_B_WE#4

C317

C317
10u/6.3V_6

10u/6.3V_6

C321

C321

0.1u/16V_4

0.1u/16V_4

R538 10K_4R538 10K_4
R540 10K_4R540 10K_4

+3V

C C

B B

+1.5VSUS

C336

C336
10u/6.3V_6

10u/6.3V_6

+3V

Place these Caps near So-Dimm1.

C337

C337
10u/6.3V_6

10u/6.3V_6

C318

C318
10u/6.3V_6

10u/6.3V_6

C338

C338
10u/6.3V_6

10u/6.3V_6

C319

C319

0.1u/16V_4

0.1u/16V_4

M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15

DIMM1_SA0
DIMM1_SA1

M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7

C333

C333

0.1u/16V_4

0.1u/16V_4

C332

C332

0.1u/16V_4

0.1u/16V_4

C334

C334

0.1u/16V_4

0.1u/16V_4

JDIM2A

JDIM2A

98

A0

97

A1

96

A2

95

A3

92

A4

91

A5

90

A6

86

A7

89

A8

85

A9

107

A10/AP

84

A11

83

A12/BC#

119

A13

80

A14

78

A15

109

BA0

108

BA1

79

BA2

114

S0#

121

S1#

101

CK0

103

CK0#

102

CK1

104

CK1#

73

CKE0

74

CKE1

115

CAS#

110

RAS#

113

WE#

197

SA0

201

SA1

202

SCL

200

SDA

116

ODT0

120

ODT1

11

DM0

28

DM1

46

DM2

63

DM3

136

DM4

153

DM5

170

DM6

187

DM7

PC2100 DDR3 SDRAM SO-DIMM

12
29
47

64
137
154
171
188

10

27

45

62
135
152
169
186

DDR3-DIMM1_H=5.2_Reverse

DDR3-DIMM1_H=5.2_Reverse

+

+

C349

C349
330u/2V_7343

330u/2V_7343

PC2100 DDR3 SDRAM SO-DIMM

DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS#0
DQS#1
DQS#2
DQS#3
DQS#4
DQS#5
DQS#6
DQS#7

+SMDDR_VREF_DIMM

C257

C257

0.1u/16V_4

0.1u/16V_4

DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46

(204P)

(204P)

DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

2.2u/6.3V_6

2.2u/6.3V_6

5

DQ0

7

DQ1

15

DQ2

17

DQ3

4

DQ4

6

DQ5

16

DQ6

18

DQ7

21

DQ8

23

DQ9

33
35
22
24
34
36
39
41
51
53
40
42
50
52
57
59
67
69
56
58
68
70
129
131
141
143
130
132
140
142
147
149
157
159
146
148
158
160
163
165
175
177
164
166
174
176
181
183
191
193
180
182
192
194

+SMDDR_VREF_DQ1

C292

C292

0.1u/16V_4

0.1u/16V_4

C322

C322

M_B_DQ5
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ0
M_B_DQ4
M_B_DQ6
M_B_DQ7
M_B_DQ13
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ8
M_B_DQ14
M_B_DQ15
M_B_DQ20
M_B_DQ17
M_B_DQ23
M_B_DQ18
M_B_DQ16
M_B_DQ21
M_B_DQ19
M_B_DQ22
M_B_DQ28
M_B_DQ24
M_B_DQ31
M_B_DQ27
M_B_DQ29
M_B_DQ25
M_B_DQ30
M_B_DQ26
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ46
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ47
M_B_DQ42
M_B_DQ49
M_B_DQ53
M_B_DQ55
M_B_DQ54
M_B_DQ52
M_B_DQ48
M_B_DQ51
M_B_DQ50
M_B_DQ60
M_B_DQ56
M_B_DQ59
M_B_DQ58
M_B_DQ61
M_B_DQ57
M_B_DQ62
M_B_DQ63

C316

C316

2.2u/6.3V_6

2.2u/6.3V_6

M_B_DQ[63:0] 4

M3 solution

SMDDR_VREF_DQ1_M35

R554 *10K_4R554 *10K_4

+3V

DDR3_DRAMRST#13,15

R189 *M3@0_6R189 *M3@0_6

+SMDDR_VREF_DIMM

2.48A

+SMDDR_VREF_DQ1

SMDDR_VREF_DQ1_M3

DRAMRST_CNTRL_PCH9,13,15

+1.5VSUS

+3V

PM_EXTTS#1

+SMDDR_VREF

REV:B Add

JDIM2B

JDIM2B

75

VDD1

76

VDD2

81

VDD3

82

VDD4

87

VDD5

88

VDD6

93

VDD7

94

VDD8

99

VDD9

100

VDD10

105

VDD11

106

VDD12

111

VDD13

112

VDD14

117

VDD15

118

VDD16

123

VDD17

124

VDD18

199

VDDSPD

77

NC1

122

NC2

125

NCTEST

198

EVENT#

30

RESET#

1

VREF_DQ

126

VREF_CA

2

VSS1

3

VSS2

8

VSS3

9

VSS4

13

VSS5

14

VSS6

19

VSS7

20

VSS8

25

VSS9

26

VSS10

31

VSS11

32

VSS12

37

VSS13

38

VSS14

43

VSS15

DDR3-DIMM1_H=5.2_Reverse

DDR3-DIMM1_H=5.2_Reverse

M1 solution

R187 *0_6R187 *0_6

change to 1K/F_4

Q11

Q11

2

*AP2302GN

*AP2302GN

3

1

(204P)

(204P)

PC2100 DDR3 SDRAM SO-DIMM

PC2100 DDR3 SDRAM SO-DIMM

+1.5VSUS

VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52

VTT1
VTT2

GND
GND

R181

R181
1K/F_4

1K/F_4

R239

R239
1K/F_4

1K/F_4

44
48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196

203
204

205
206

+SMDDR_VREF_DQ1

C326

C326
470p/50V_4

470p/50V_4

+0.75V_DDR_VTT

C611

C586

A A

C614

C614

2.2u/6.3V_6

2.2u/6.3V_6

C608

C608

0.1u/16V_4

0.1u/16V_4

5

C586
1u/6.3V_4

1u/6.3V_4

C587

C587
1u/6.3V_4

1u/6.3V_4

C611
1u/6.3V_4

1u/6.3V_4

C612

C612
1u/6.3V_4

1u/6.3V_4

4.7u/6.3V_6

4.7u/6.3V_6

4

C574

C574

C570

C570

4.7u/6.3V_6

4.7u/6.3V_6

C610

C610

4.7u/6.3V_6

4.7u/6.3V_6

+SMDDR_VREF_DIMM13

3

+1.5VSUS11,13,15,39,42,46

+3V3,7,8,9,10,11,13,16,20,23,24,25,26,27,29,33,34,36,37,38,39,40,41,42,43,45,46

+0.75V_DDR_VTT13,39,43

+SMDDR_VREF13,15,39

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

DDRIII SO-DIMM-1

DDRIII SO-DIMM-1

DDRIII SO-DIMM-1

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

ZQS 45W

ZQS 45W

ZQS 45W

1

14 46Wednesday, February 08, 2012

14 46Wednesday, February 08, 2012

14 46Wednesday, February 08, 2012

3C

3C

3C

1

CPU XDP Connector(CPU)

A A

2

3

4

5

6

7

8

s3 leakage circuit

+1.5VSUS

R424

R424
1K/F_4

1K/F_4

R420 1K/F_4R420 1K/F_4

DRAMRST_CNTRL_PCH9,13,14

+3V_S5

Q34 2N7002KQ34 2N7002K

3

2

C541

C541

0.047u/16V_4

0.047u/16V_4

1

R433

R433

4.99K/F_4

4.99K/F_4

CPU_DRAMRST# 3DDR3_DRAMRST#13,14

+1.5VSUS

R429

R429
*1K/F_4

*1K/F_4

R431

R431
*1K/F_4

*1K/F_4

+1.5V_CPU

R416

R416
200/F_4

200/F_4
R418 130/F_4R418 130/F_4

R417 *39_4R417 *39_4

+VDDR_REF_CPU
+1.5V_CPU

3

Q32 *2N7002KQ32 *2N7002K

2

MAINON_ON_G

+VDDR_REF_CPU 5
+1.5V_CPU 5

+1.5VSUS 11,13,14,39,42,46

+SMDDR_VREF 13,14,39

PM_DRAM_PWRGD_R 3

1

C524

C524

0.1u/10V_4

0.1u/10V_4

U17

U17

Q33

Q33
2N7002K

2N7002K

2

4

C548

C548
470p/50V_4

470p/50V_4

MAINON_ON_G

2
1

+VDDR_REF_CPU+SMDDR_VREF

1

+1.5V_CPU

+1.5V_CPU

1
2
36

+1.5V_CPU+1.5VSUS

2

74AHC1G09

74AHC1G09

3 5

R432

R432
100K_4

100K_4

R444

R444
220_8

220_8

3

1

4

Q35

Q35
DMN601K-7

DMN601K-7

PM_DRAM_PWRGD_Q

SYS_PWROK7

PM_DRAM_PWRGD7

B B

R430 *0_8R430 *0_8

3

MAIND36,39,43

C C

4.5A

MAINON_ON_G43

D D

MAIND

R465 *0_8R465 *0_8
R464 *0_8R464 *0_8

Q37 AO4496Q37 AO4496

8
7

5

MAIND

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

1

2

3

4

5

6

Date: Sheet of

7

XDP

XDP

XDP

PROJECT :

ZQS 45W

ZQS 45W

ZQS 45W

15 46Wednesday, February 08, 2012

15 46Wednesday, February 08, 2012

15 46Wednesday, February 08, 2012

8

3C

3C

3C