Acer TravelMate 3300 Schematics

A

B

C

D

E

Myna II

Mobile CPU

4 4

DDR II

400/533 MHz

DDR II

400/533 MHz

3 3

CLK GEN.

IDT CV125

400/533MHz

11,12

400/533MHz

11,12

CLE-1.5G / Dothan2.13G

3

(CPU on board,no socket )

Int. MIC

Mic In

ACLINK

Line In

Line Out

Codec

ALC655

OP AMP

G1421B

2 2

INT.SPKR

MODEM

RJ11 CONN

IO Board

1 1

MDC Card

(co-lay with PCMCIA)

New card

PWR SW TPS2231

PCI-E

29

Easy Port 4 (124 PIN)

AC IN

RJ45-11

A

SEARIAL PORT

CRT

PRINTER

Dothan

HOST BUS

533MHz

Alviso-GM

KI.91501.017

6,7,8,9,10

DMI I/F

100MHz

ICH6-M

Ver. : B2, KI.80101.011

15,16,17,18

PATA

two USB port on IO Board

HDD

B

20

MINI USB Blue-tooth

PS2

MIC

4, 5

USB

3 PORT

21

LINE IN

G792

PCI BUS

LPC BUS

21

IO Board

LINE OUT

NS SIO

87392

FIR

TV OUT

C

19

CH7307C

TI

PCI 7411

1* Slot Cardbus 1* 1394 CardReader

24,25

LAN

MS/MS Pro/ xD/ MMC/SD

22, 23

Giga BCM5788-M

KBC

Renesas RE144B

31

Touch Pad

DVI PCIeX2 SMBUS

INT. KB

32 32

Project code: 91.4C201.001 PCB REVISION: 05216-SB

TV

(EZ4 only )

53

PCMCIA I/F

LVDS

RGB CRT

TMDS

(EZ4 only )

PCMCIA

LCD

CRT

DVI-D

13

14

35

SLOT

PWR SW

TSP2220A

26

5 in 1

26

Mini-PCI

802.11A/B/G

(only smaller)

Support TypeII

1394 6pin Conn

30

26

27

TXFM RJ45 CONN

23

BIOS ROM

4M BITS

PM49F004T-33VC

34, 35

33 3330

D

23

LPC

DEBUG CONN.

SYSTEM DC/DC

TPS5130

INPUTS

DCBATOUT

SYSTEM DC/DC

ISL6227

INPUTS OUTPUTS

DCBATOUT

TPS51100DGQ

41,42

OUTPUTS

5V_S5 3V_S5 1D5V_S0

2D5V_S0(LDO)

1D05V_S0 1D8V_S3

VTT_S0(0.9V)1D8V_S3

MAXIM CHARGER

MAX8725ETI

OUTPUTSINPUTS CHG_PWR

DCBATOUT

16.8V 3.2A

UP+5V

5V 100mA

CPU DC/DC

ISL6218CV-T

E

OUTPUTS VCC_CORE

0.844~1.3V 27A

147Monday, September 26, 2005

of

INPUTS

DCBATOUT

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

BLOCK DIAGRAM

Size Document Number Rev

Size Document Number Rev Custom

Custom

Custom Date: Sheet

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

Myna II

43

44

40

SB

A

B

C

D

E

Alviso Strapping Signals and Configuration

Pin Name

CFG[2:0]

4 4

CFG[3:4] CFG5

CFG6 CFG7

CFG[8:11] CFG[12:13]

CFG[14:15] CFG16

CFG17 CFG18

3 3

CFG19

CFG20 SDVOCRTL

_DATA

All strap signals are sampled with respect to the leading

NOTE:

edge of the Alviso GMCH PWORK In signal.

1.CHECK P5[1D5V & 1D5V-AVDD]

2.CHECK P8[PM & GM]

Strap Description

FSB Frequency Select

Reversed DMI x2 Select

DDR I / DDR II CPU Strap

Reversed XOR/ALL Z test

straps

Reversed FSB Dynamic ODT 0 = Dynamic ODT Disabled

Reversed CPU core VCC

Select CPU VTT Select

Reversed SDVO Present

Configuration

000 = Reserved 001 = FSB533 010 = FSB800 011-111 = Reversed

0 = DMI x2

1 = DMI x4

0 = DDR II 1 = DDR I

0 = Prescott

1 = Dothan

00 = Reserved 01 = XOR mode enabled 10 = All Z mode enabled

11 = Normal Operation

(Default)

1 = Dynamic ODT Enabled

(Default)

0 = 1.05V

1 = 1.5V

0 = 1.05V

1 = 1.2V

0 = No SDVO device present

(Default) 1= SDVO device present

(Default)

page 7

PCI Routing

7411 MiniPCI LAN

25 21 23

IRQ

B.F.G

E

REQ/GNTIDSEL

0 1 2

ICH6-M Integrated Pull-up and Pull-down Resistors

ACZ_BIT_CLK, EE_DOUT, GNT[6]#/GPO[16], LAD[3:0]#/FB[3:0]#, LDRQ[0], PME#, PWRBTN#,

LAN_RXD[2:0]

ACZ_RST#, ACZ_SDIN[2:0], ACZ_SYNC, ACZ_SDOUT,ACZ_BITCLK, SPKR,

USB[7:0][P,N]

DD[7],

LAN_CLK

DPRSLP#, EE_DIN,

GNT[5]#/GPO[17],

TP[3]

EE_CS,

SDDREQ

LDRQ[1]/GPI[41],

DPRSLPVR,

ICH6 internal 20K pull-ups

ICH6 internal 10K pull-ups

ICH6 internal 20K pull-downs

ICH6 internal 15K pull-downs

ICH6 internal 11.5K pull-downs

ICH6 internal 100K pull-downs

ICH6-M EDS 14308 0.8V1

ICH6-M IDE Integrated Series Termination Resistors

DD[15:0], DDACK#, DCS3#,

IORDY,

IDEIRQ

DIOR#, DREQ,DIOW#,

DA[2:0],

DCS1#,

approximately 33 ohm

RESISTOR

Symbol name

2 2

10KR3

33D3R5

1KR3F

The naming rule is value + R + size + tolerance For the value, it can be read by the number before R. (R means resistor) For the tolerance, it can be read from the last letter. For the rating, we don't show on the symbol name.

For the size, R2=>0402, R3=>0603, R5=>0805,....

Value

10K Ohm

33.3 Ohm

1K Ohm

Tolerance

(J: 5%, F: 1%, D: 0.5%, B: 0.1 %)

If no letter, it means J: 5%

F: 1%

Rating

0402=> 1/16W, 25V 0603 => 1/16W, 75V 0805 => 1/10W, 100V

1/16W, 75V

1/10W, 100V

1/16W, 75V

Size

2=>0402, 3=>0603, 5=>0805, 6=>1206, 0=>1210

0603

0805If no letter, it means J: 5%

0603

CAPACITOR

Symbol name

SCD1U10V2MX-1

SC10U6D3V5MX

SC2D2U16V5ZY

The naming rule is Capacitor type + value + rating + size + tolerance + material SCD1U10V2MX-1 SC=> SMT Ceremic, TC=> POS cap or SP cap D1U => 0.1uF 10V => the voltage rating is 10V 2=> 0402, 3=>0603, 5=>0805 M=>tolerance M, K, Z X=> X7R/X5R, Y=> Y5V

-1 => symbol version, nonsense to EE characteristic

Value

0.1uF

10uF

2.2uF

Tolerance

(M: +/-20, K: +/-10, Z: +80/-20)

M/X5R

Z/Y5V

Rating

10V

6.3V

16V

Size

2=>0402, 3=>0603, 5=>0805, 6=>1206, 0=>1210

0402

0805

1 1

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

A3 Date: Sheet

Date: Sheet

WISTRON

Myna2 SB

of

247Monday, September 26, 2005

3D3V_S0 3D3V_S03D3V_S0

12

C496

SCD1U16V

R386

1 2

0R0603-PAD

3D3V_APWR_S0 3D3V_CLKGEN_S03D3V_48MPWR_S0

12

C493

SC4D7U10V5ZY

12

C490

SCD1U16V

12

R392

1 2

4D7R3J-3-GP

C499

SCD1U16V

12

C507

SC4D7U10V5ZY

12

C522

SCD1U16V

DY

12

0R0603-PAD

0R0603-PAD R412

R412

1 2

C512

SCD1U16V

12

C515

C515 SC10U6D3V5MX

SC10U6D3V5MX

12

C492

SCD1U16V

DY

12

C491

SCD1U16V

12

C272

SCD1U16V

12

C489

SCD1U16V

DY

12

C523

SCD1U16V

12

C513

SCD1U16V

DY

12

C509

SCD1U16V

1907_PGOOD38,39

IN (3D3V_S0)

H X

3D3V_CLKGEN_S0

R154

R155

R155 1KR2

1KR2

DUMMY-R2

EN (1907_PGOOD)

12

R152

DUMMY-R2

12

R153

DUMMY-R2

L

R371

R372

12

DUMMY-R2

12

DUMMY-R2

3D3V_S0

12

R424

R424 10KR2

10KR2

D

Q27

1

2N7002

G

S

2 3

OUT (VTT_PWRGD#)

H

Hi - ZH

FS_A

FS_B

CFG2

0

0 0

0 1

0

1 0

1 1 100M

0 1

1 1

1

SC changed

DY

FS_A

0

01200M 1 00333M 1 0 1 Reserved

PCLK_SIO31 PCLK_MINI29

PCLK_LAN22 PCLK_PCM24 PCLK_KBC30

PCLK_FWH33 CLK_ICHPCI16

VTT_PWRGD# 39

C508

1 2

SC33P

C497

1 2

SC33P

3D3V_S0

12

R161

R161 10KR2

10KR2

12

R162

R162 10KR2

10KR2

CPU_SEL1 7 CPU_SEL0 4,7

CPU

266M 133M

166M

400M

PCLK_PCM & PCLK_SIO need equal length

R427 22R2R427 22R2 R373 33R2R373 33R2

R428 33R2R428 33R2 R426 10R2R426 10R2

-1

X3

X-14D31818M-1

1 2

12

R159

R159 10KR2

10KR2

R425 33R2R425 33R2 R158 33R2R158 33R2

R163 33R2R163 33R2

CLK_ICH14 & CLK14_SIO need equal length

R160

R160 10KR2

10KR2

ITP_EN SS_SEL

DY

CLK_PCIE_NEW CLK_PCIE_NEW#

CLK_PCIE_ICH CLK_PCIE_ICH#

DREFSSCLK# DREFSSCLK

DREFCLK DREFCLK#

1 2 1 2

1 2 1 2 1 2

1 2 1 2

PM_STPPCI#16

SMBC_ICH11,18

SMBD_ICH11,18

DREFCLK7 DREFCLK#7

XTAL_IN XTAL_OUT

CLK_ICH1416 CLK14_SIO31

PCLK_SIO_1 PCLK_MINI_1

PCLK_LAN_1 PCLK_KBC_1

H/L: 100/96MHz

SS_SEL ITP_EN

H/L : CPU_ITP/SRC7

4

RN64 SRN33-2-U2RN64 SRN33-2-U2

R369 22R2R369 22R2

1 2

R370 22R2R370 22R2

1 2

R136 475R2FR136 475R2F

1 2

SB_0817

NEW

RN39 SRN49D9F-GP

1 2 3

RN32

1 2 3

RN65

1 2 3

RN42

1 2 3

4

SRN49D9F-GP

4

SRN49D9F-GP

4

SRN49D9F-GP

4

VTT_PWRGD#

?cost

DREFCLK_1

23

DREFCLK#_1

1

CLK_ICH14_1 CLK14_SIO_1

U41

56

PCI0

3

PCI1

4

PCI2

5

PCI3

9

PCIF1/SEL100/96#

8

PCIF0/ITP_EN

55

PCI_STOP#

46

SCL

47

SDA

14

DOT96

15

DOT96#

50

XTAL_IN

49

XTAL_OUT

52

REF

39

IREF

10

VTT_PWRGD#/PD

2

VSS_PCI

6

VSS_PCI

51

VSS_REF

45

VSS_CPU

38

VSSA

13

VSS48

29

VSS_SRC

IDTCV125PA

CLK_CPU_BCLK CLK_CPU_BCLK#

CLK_MCH_BCLK CLK_MCH_BCLK#

CLK_MCH_3GPLL CLK_MCH_3GPLL#

CLK_XDP_CPU CLK_XDP_CPU#

CLK_PCIE_DOCK1 CLK_PCIE_DOCK1#

CLK_PCIE_DOCK2 CLK_PCIE_DOCK2#

CPU2_ITP/SRC7

CPU2_ITP#/SRC7#

CPU_STOP#

FSC/TEST_SEL

FSB/TEST_MODE

USB48/FSA

VDD_SRC VDD_SRC

VDD_PCI VDD_PCI

VDD_REF VDD_CPU

VDD_SRC

71.00125.00W

SRN49D9F-GP

RN36

1 2 3

SRN49D9F-GP

RN35

1 2 3

SRN49D9F-GP

RN33

1 2 3

SRN49D9F-GP

RN34

1 2 3

SRN49D9F-GP

RN41

1 2 3

SRN49D9F-GP

RN40

1

NEW

2 3

NEW

LVDS

LVDS#

SRC1

SRC1#

SRC2

SRC2#

SRC3

SRC3#

SRC4

SRC4#

SRC5

SRC5#

SRC6

SRC6#

CPU0

CPU0#

CPU1

CPU1#

VDDA

VDD48

4

17 18

19 20 22 23 24 25

CLK_PCIE_NEW1

26

CLK_PCIE_NEW#1

27

CLK_PCIE_ICH1

31

CLK_PCIE_ICH#1

30

CLK_MCH_3GPLL1

33

CLK_MCH_3GPLL#1

32

CLK_XDP_CPU1

36

CLK_XDP_CPU#1

35

CLK_CPU_BCLK1

44

CLK_CPU_BCLK#1

43

CLK_MCH_BCLK1

41

CLK_MCH_BCLK#1

40 54

53 16 12

34 21

7 1

48 42 37 11 28

DREFSSCLK1 DREFSSCLK#1

CLK_PCIE_DOCK_1 CLK_PCIE_DOCK_1#

CLK_PCIE_DOCK_2

CLK_PCIE_DOCK_2#

CPU_SEL0 CPU_SEL1 FS_A

R157 22R2R157 22R2 R156 22R2R156 22R2

3D3V_CLKGEN_S0

3D3V_APWR_S0 3D3V_48MPWR_S0

RN63 SRN33-2-U2RN63 SRN33-2-U2

2 3 1

4

RN62 SRN33-2-U2

2 3 1

4

RN61 SRN33-2-U2

2 3

EZ4

1

EZ4

RN60 SRN33-2-U2

2 3 1

NEW

RN57 SRN33-2-U2RN57 SRN33-2-U2

1 2 3

RN58 SRN33-2-U2RN58 SRN33-2-U2

1 2 3

RN59 SRN33-2-U2RN59 SRN33-2-U2

1 2 3

RN56 SRN33-2-U2RN56 SRN33-2-U2

1 2 3

RN55 SRN33-2-U2RN55 SRN33-2-U2

1 2 3

12 12

Dummy when no EZ4

4

Dummy when no new Card

4

CLK48_ICH 16 CLK48_CARDBUS 24

EMI capacitor

CLK_ICH14 CLK14_SIO PCLK_FWH PCLK_PCM PCLK_MINI PCLK_KBC CLK_ICHPCI CLK48_ICH

Title

Size Document Number Rev

Size Document Number Rev A3

A3

A3 Date: Sheet

Date: Sheet

C483 SC10P50V2JN-1

C288 SC10P50V2JN-1

C288 SC10P50V2JN-1 C528 SC10P50V2JN-1

C528 SC10P50V2JN-1 C485 SC10P50V2JN-1

C485 SC10P50V2JN-1 C527 SC10P50V2JN-1

C527 SC10P50V2JN-1 C285 SC10P50V2JN-1

C285 SC10P50V2JN-1 C287

C287

Clock Generator - IDT125

DY

C484

1 2

SC10P50V2JN-1

DY

DY DY

DY

1 2

SC10P50V2JN-1

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Myna2

347Monday, September 26, 2005

DREFSSCLK 7 DREFSSCLK# 7

CLK_PCIE_DOCK1 34 CLK_PCIE_DOCK1# 34

CLK_PCIE_DOCK2 34 CLK_PCIE_DOCK2# 34

CLK_PCIE_NEW 29 CLK_PCIE_NEW# 29

CLK_PCIE_ICH 16 CLK_PCIE_ICH# 16

CLK_MCH_3GPLL 7 CLK_MCH_3GPLL# 7

CLK_XDP_CPU 4 CLK_XDP_CPU# 4

CLK_CPU_BCLK 4 CLK_CPU_BCLK# 4

CLK_MCH_BCLK 6 CLK_MCH_BCLK# 6 PM_STPCPU# 16,39

SB

of

SB

A

U33A

H_A#3

4 4

3 3

2 2

H_A#[31..3]6

H_ADSTB#06 H_REQ#[4..0]6

H_ADSTB#16

H_A20M#15 H_FERR#15 H_IGNNE#15

0R0402-PAD

H_STPCLK#15

1 2

H_INTR15 H_NMI15 H_SMI#15

R291

H_STPCLK_R

H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16

H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4

H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31

AA3 AA2

AF4 AC4 AC7 AC3 AD3 AE4 AD2 AB4 AC6 AD5 AE2 AD6

AF3 AE1

AF1 AE5

P4 U4 V3 R3 V2

W1

T4

W2

Y4 Y1 U1

Y3 U3 R2

P3 T2 P1 T1

C2 D3 A3

C6 D1 D4 B4

A3# A4#

ADDR GROUP 0

A5# A6# A7# A8# A9# A10# A11# A12# A13# A14# A15# A16# ADSTB#0

REQ0# REQ1# REQ2# REQ3# REQ4#

A17# A18# A19# A20# A21# A22# A23# A24# A25# A26# A27# A28# A29# A30#

ADDR GROUP 1

A31# ADSTB#1

A20M# FERR# IGNNE#

STPCLK# LINT0 LINT1 SMI#

HCLK THERM XTP/ITP SIGNALS CONTROL

BANIAS-1D6G-1U

THERMTRIP#

SC changed

XDP_DBRESET#16

1 1

A

B

N2

ADS#

L1

BNR#

J3

BPRI#

L4

DEFER#

H2

DRDY#

M2

DBSY#

N4

BR0#

A4

IERR#

B5

INIT#

J2

LOCK#

B11

RESET#

RS0# RS1# RS2#

TRDY#

HIT#

HITM#

BPM#0 BPM#1 BPM#2 BPM#3 PRDY#

PREQ#

TCK

TDI TDO TMS

TRST#

DBR#

PROCHOT#

THERMDA THERMDC

ITP_CLK1 ITP_CLK0

BCLK1 BCLK0

CPU_PROCHOT# XDP_TDI XDP_TMS XDP_TDO H_CPURST#

XDP_DBRESET#

XDP_TCK XDP_TRST#

H_RS#0

H1

H_RS#1

K1

H_RS#2

L2 M3

K3 K4

XDP_BPM#0

C8

XDP_BPM#1

B8

XDP_BPM#2

A9

XDP_BPM#3

C9

XDP_BPM#4

A10

XDP_BPM#5

B10

XDP_TCK

A13

XDP_TDI

C12

XDP_TDO

A12

XDP_TMS

C11

XDP_TRST#

B13

XDP_DBRESET#

A7

CPU_PROCHOT#

B17 B18 A18

C17 A15

A16 B14 B15

R311 56R2FR311 56R2F

1 2

R297 150R2FR297 150R2F

1 2

R106 39D2R3FR106 39D2R3F

1 2

R299 54D9R2FR299 54D9R2F

1 2

R296 54D9R2FR296 54D9R2F

1 2

R293 150R2FR293 150R2F

1 2

R304 27D4R2FR304 27D4R2F

1 2

R302 680R3FR302 680R3F

1 2

All place within 2" to CPU

B

TP6

TP6 TPAD28

TPAD28

H_ADS# 6 H_BNR# 6

H_BPRI# 6

H_DEFER# 6 H_DRDY# 6 H_DBSY# 6

H_BREQ#0 6

H_INIT# 15 H_LOCK# 6

H_CPURST# 6

H_TRDY# 6 H_HIT# 6

H_HITM# 6

H_THERMDA 19

H_THERMDC 19

PM_THRMTRIP-A# 7

R313 0R0402-PADR313 0R0402-PAD

1 2

CLK_XDP_CPU# 3

CLK_XDP_CPU 3

CLK_CPU_BCLK# 3

CLK_CPU_BCLK 3

H_IERR#

1D05V_S0

3D3V_S0

1D05V_S0

H_RS#[2..0] 6

TP18TPAD28 TP18TPAD28 TP17TPAD28 TP17TPAD28 TP82TPAD28 TP82TPAD28 TP20TPAD28 TP20TPAD28 TP83TPAD28 TP83TPAD28 TP81TPAD28 TP81TPAD28 TP87TPAD28 TP87TPAD28 TP84TPAD28 TP84TPAD28 TP85TPAD28 TP85TPAD28 TP22TPAD28 TP22TPAD28 TP86TPAD28 TP86TPAD28 TP80TPAD28 TP80TPAD28

TP88TPAD28 TP88TPAD28

12

R288

R288 56R2F

56R2F

Place testpoint on H_IERR# with a GND

0.1" away

PM_THRMTRIP-I# 15,19

PM_THRMTRIP# should connect to ICH6 and Alviso without T-ing

( No stub)

CPU_SEL03,7

C

TP23 TPAD28TP23 TPAD28

R327

R327 1KR2F-L1-GP

1KR2F-L1-GP

C

To V-CORE SWITCH

1D05V_S0

12

TP8 TPAD28TP8 TPAD28 TP16 TPAD28TP16 TPAD28 TP5 TPAD28TP5 TPAD28 TP29 TPAD28TP29 TPAD28

12

R328

R328 2KR2F

2KR2F

0R0603-PAD

R310

1 2

Layout Note:

0.5" max length.

BSEL[1:0] Freq.(MHz) (A Stepping) L L 100 L H 133

BSEL[1:0] Freq.(MHz) (B Stepping) L H 100 L L 133

GTLREF0

H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_DSTBN#0 H_DSTBP#0 H_DINV#0

H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_DSTBN#1 H_DSTBP#1 H_DINV#1

A19 A25 A22 B21 A24 B26 A21 B20 C20 B24 D24 E24 C26 B23 E23 C25 C23 C22 D25

H23 G25 L23

M26

H24 F25 G24

M23

L26 N24

M25

H26 N25 K25 K24 L24

C16 C14

AF7

AC1

E26

AD26

J23 J25

J26

E1

C3

D

U33B

D0# D1# D2# D3# D4# D5# D6# D7# D8# D9# D10# D11# D12#

DATA GRP 0DATA GRP 1

D13# D14# D15# DSTBN0# DSTBP0# DINV0#

D16# D17# D18# D19# D20# D21# D22# D23# D24# D25# D26# D27# D28# D29# D30# D31# DSTBN1# DSTBP1# DINV1#

PSI# BSEL0

BSEL1

MISC

RSVD2 RSVD3 RSVD4

PWRGOOD

RSVD5 GTLREF0

BANIAS-1D6G-1U

D

Y26

D32#

AA24

D33#

T25

D34#

U23

D35#

V23

D36#

R24

D37#

R26

D38#

R23

D39#

AA23

D40#

U26

D41#

V24

D42#

U25

D43#

V26

D44#

DATA GRP 2

Y23

D45#

AA26

D46#

Y25

D47#

W25

DSTBN2#

W24

DSTBP2#

T24

DINV2#

AB25

D48#

AC23

D49#

AB24

D50#

AC20

D51#

AC22

D52#

AC25

D53#

AD23

D54#

AE22

D55#

AF23

D56#

AD24

D57#

AF20

D58#

AE21

D59#

AD21

D60#

DATA GRP 3

AF25

D61#

AF22

D62#

AF26

D63#

AE24

DSTBN3#

AE25

DSTBP3#

AD20

DINV3# COMP0

COMP1 COMP2 COMP3

DPRSTP#

DPSLP#

DPWR#

TEST1 TEST2

SLP#

P25 P26 AB2 AB1

G1 B7 C19 E4 A6

C5 F23

DY

COMP0 COMP1 COMP2 COMP3

TEST1 TEST2

R324

R324 1KR2

1KR2

E

H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_DSTBN#2 H_DSTBP#2 H_DINV#2

H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 H_DSTBN#3 H_DSTBP#3 H_DINV#3

R325 27D4R2FR325 27D4R2F R326 54D9R2FR326 54D9R2F R285 27D4R2FR285 27D4R2F R284 54D9R2FR284 54D9R2F

12

Title

Size Document Number Rev

Size Document Number Rev A3

A3

A3 Date: Sheet

Date: Sheet

Layout Note: Comp0, 2 connect with Zo=27.4 ohm, make trace length shorter than 0.5" . Comp1, 3 connect with Zo=55 ohm, make trace length shorter than 0.5" .

1 2 1 2 1 2 1 2

H_DPRSLP# 15 H_DPSLP# 15 H_DPWR# 6

H_CPUSLP# 6,15

R289

R289 1KR2

1KR2

NO STUFFNO STUFF

DY

H_D#[63..0] 6

H_DINV#[3..0] 6

H_DSTBN#[3..0] 6 H_DSTBP#[3..0] 6

1D05V_S0

12

R97

R97 200R2F

200R2F

H_PWRGD 15,19

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

CPU (1 of 2)

Myna2 SB

E

of

447Monday, September 26, 2005

A

VCC_CORE_S0

U33C

AA11

VCC0

AA13

VCC1

AA15

VCC2

AA17

VCC3

AA19

VCC4

AA21

VCC5

AA5

VCC6

4 4

3 3

2 2

1 1

AA7

AA9 AB10 AB12 AB14 AB16 AB18 AB20 AB22

AB6

AB8 AC11 AC13 AC15 AC17 AC19

AC9 AD10 AD12 AD14 AD16 AD18

AD8 AE11 AE13 AE15 AE17 AE19

AE9 AF10 AF12 AF14 AF16 AF18

AF8

D18

D20

D22

D6

D8 E17 E19 E21

E5

E7

E9

F18 F20 F22

F6

F8 G21

Layout Note:

VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 VCC49 VCC50 VCC51 VCC52 VCC53 VCC54 VCC55 VCC56 VCC57 VCC58

BANIAS-1D6G-1U

VCC59 VCC60 VCC61 VCC62 VCC63 VCC64 VCC65 VCC66 VCC67 VCC68 VCC69 VCC70 VCC71

VCCA0 VCCA1 VCCA2 VCCA3

VCCP0 VCCP1 VCCP2 VCCP3 VCCP4 VCCP5 VCCP6 VCCP7 VCCP8

VCCP9 VCCP10 VCCP11 VCCP12 VCCP13 VCCP14 VCCP15 VCCP16 VCCP17 VCCP18 VCCP19 VCCP20 VCCP21 VCCP22 VCCP23 VCCP24

VCCQ0 VCCQ1

VID0 VID1 VID2 VID3 VID4 VID5

VCCSENSE VSSSENSE

VCCSENSE and VSSSENSE lines should be of equal length.

Layout Note: Provide a test point (with no stub) to connect a differential probe between VCCSENSE and VSSSENSE at the location where the two 54.9ohm resistors terminate the 55 ohm transmission line.

A

G5 H22 H6 J21 J5 K22 U5 V22 V6 W21 W5 Y22 Y6

F26 B1 N1 AC26

D10 D12 D14 D16 E11 E13 E15 F10 F12 F14 F16 K6 L21 L5 M22 M6 N21 N5 P22 P6 R21 R5 T22 T6 U21

P23 W4

E2 F2 F3 G3 G4 H4

AE7 AF6

VCC_CORE_S0

CPU_D10

TP_VCCSENSE TP_VSSSENSE

1D5V_VCCA_S0

R104 0R0402-PADR104 0R0402-PAD

1 2

H_VID0 39 H_VID1 39 H_VID2 39 H_VID3 39 H_VID4 39 H_VID5 39

12

R102

R99

54D9R2F

DY

54D9R2F

DY

C462

12

C463

1D05V_S0

SCD01U16V2KX

1D05V_S0

12

VCC_CORE_S0

12

VCC_CORE_S0

DY

12

VCC_CORE_S0

12

DY

B

SC10U10V5ZY

12

C151

C196

SCD1U10V2MX-1

12

C212

C192

SC10U10V5ZY

12

C214

C168

SCD1U10V2MX-1

12

C164

C176

SC10U10V5ZY

DY

B

12

C149

SCD1U10V2MX-1

DY

12

C199

SC10U10V5ZY

DY

12

C233

SCD1U10V2MX-1

DY

12

C139

SC10U10V5ZY

DY

1D5V_S0 1D5V_VCCA_S0

0R0603-PAD

R331

1 2

12

C175

C148

SCD1U10V2MX-1

DY

12

C171

C181

SC10U10V5ZY

DY

12

C157

C232

SCD1U10V2MX-1

12

C231

SCD1U10V2MX-1

12

C218

SC10U10V5ZY

12

C147

SCD1U10V2MX-1

DY

12

C209

SCD1U10V2MX-1

DY

12

C184

SC10U10V5ZY

DY

12

C227

SCD1U10V2MX-1

DY

12

C228

C229

SCD1U10V2MX-1

DY

12

C195

C203

SC10U10V5ZY

12

C152

C153

SCD1U10V2MX-1

DY

C

12

C183

SCD1U10V2MX-1

DY

80.10710.101

12

C215

SC10U10V5ZY

DY

12

C222

SCD1U10V2MX-1

DY

C

12

TC3

TC3 ST100U6D3VM-U

ST100U6D3VM-U

DY

12

C223

SC10U10V5ZY

DY

12

C217

SC10U10V5ZY

12

C235

SC10U10V5ZY

DY

12

C210

SC10U10V5ZY

DY

12

C211

SC10U10V5ZY

DY

12

C197

SC10U10V5ZY

DY

?cost

12

C198

SC10U10V5ZY

DY

12

C190

SC10U10V5ZY

DY

12

C191

SC10U10V5ZY

12

C179

SC10U10V5ZY

12

C180

SC10U10V5ZY

DY

12

C169

SC10U10V5ZY

D

12

C170

SC10U10V5ZY

DY

C154

SC10U10V5ZY

D

C150

SC10U10V5ZY

U33D

A2

VSS0

A5

VSS1

A8

VSS2

A11

VSS3

A14

VSS4

A17

VSS5

A20

VSS6

A23

VSS7

A26

VSS8

AA1

VSS9

AA4

VSS10

AA6

VSS11

AA8

VSS12

AA10

VSS13

AA12

VSS14

AA14

VSS15

AA16

VSS16

AA18

VSS17

AA20

VSS18

AA22

VSS19

AA25

VSS20

AB3

VSS21

AB5

VSS22

AB7

VSS23

AB9

VSS24

AB11

VSS25

AB13

VSS26

AB15

VSS27

AB17

VSS28

AB19

VSS29

AB21

VSS30

AB23

VSS31

AB26

VSS32

AC2

VSS33

AC5

VSS34

AC8

VSS35

AC10

VSS36

AC12

VSS37

AC14

VSS38

AC16

VSS39

AC18

VSS40

AC21

VSS41

AC24

VSS42

AD1

VSS43

AD4

VSS44

AD7

VSS45

AD9

VSS46

AD11

VSS47

AD13

VSS48

AD15

VSS49

AD17

VSS50

AD19

VSS51

AD22

VSS52

AD25

VSS53

AE3

VSS54

AE6

VSS55

AE8

VSS56

AE10

VSS57

AE12

VSS58

AE14

VSS59

AE16

VSS60

AE18

VSS61

AE20

VSS62

AE23

VSS63

AE26

VSS64

AF2

VSS65

AF5

VSS66

AF9

VSS67

AF11

VSS68

AF13

VSS69

AF15

VSS70

AF17

VSS71

AF19

VSS72

AF21

VSS73

AF24

VSS74

B3

VSS75

B6

VSS76

B9

VSS77

B12

VSS78

B16

VSS79

B19

VSS80

B22

VSS81

B25

VSS82

C1

VSS83

C4

VSS84

C7

VSS85

C10

VSS86

C13

VSS87

C15

VSS88

C18

VSS89

C21

VSS90

C24

VSS91

D2

VSS92

D5

VSS93

D7

VSS94

D9

VSS95

D11

Title

Size Document Number Rev

Size Document Number Rev A3

A3

A3 Date: Sheet

Date: Sheet

VSS96

CPU (2 of 2)

Myna2 SB

E

D13

VSS97

D15

VSS98

D17

VSS99

D19

VSS100

D21

VSS101

D23

VSS102

D26

VSS103

E3

VSS104

E6

VSS105

E8

VSS106

E10

VSS107

E12

VSS108

E14

VSS109

E16

VSS110

E18

VSS111

E20

VSS112

E22

VSS113

E25

VSS114

F1

VSS115

F4

VSS116

F5

VSS117

F7

VSS118

F9

VSS119

F11

VSS120

F13

VSS121

F15

VSS122

F17

VSS123

F19

VSS124

F21

VSS125

F24

VSS126

G2

VSS127

G6

VSS128

G22

VSS129

G23

VSS130

G26

VSS131

H3

VSS132

H5

VSS133

H21

VSS134

H25

VSS135

J1

VSS136

J4

VSS137

J6

VSS138

J22

VSS139

J24

VSS140

K2

VSS141

K5

VSS142

K21

VSS143

K23

VSS144

K26

VSS145

L3

VSS146

L6

VSS147

L22

VSS148

L25

VSS149

M1

VSS150

M4

VSS151

M5

VSS152

M21

VSS153

M24

VSS154

N3

VSS155

N6

VSS156

N22

VSS157

N23

VSS158

N26

VSS159

P2

VSS160

P5

VSS161

P21

VSS162

P24

VSS163

R1

VSS164

R4

VSS165

R6

VSS166

R22

VSS167

R25

VSS168

T3

VSS169

T5

VSS170

T21

VSS171

T23

VSS172

T26

VSS173

U2

VSS174

U6

VSS175

U22

VSS176

U24

VSS177

V1

VSS178

V4

VSS179

V5

VSS180

V21

VSS181

V25

VSS182

W3

VSS183

W6

VSS184

W22

VSS185

W23

VSS186

W26

VSS187

Y2

VSS188

Y5

VSS189

Y21

VSS190

Y24

VSS191

BANIAS-1D6G-1U

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

of

547Monday, September 26, 2005

E

A

H_XRCOMP

12

R339

R339 24D9R2F

24D9R2F

4 4

1D05V_S0

R340

R340 54D9R2F

54D9R2F

1 2

H_XSCOMP

1D05V_S0

12

R337

R337 221R2F-2-GP

221R2F-2-GP

H_XSWING

3 3

2 2

12

1D05V_S0

1 2

1D05V_S0

12

R338

R338 100R2F

100R2F

H_YRCOMP

R333

R333 24D9R2F

24D9R2F

R336

R336 54D9R2F

54D9R2F

H_YSCOMP

R335

R335 221R2F-2-GP

221R2F-2-GP

H_YSWING

R334

R334 100R2F

100R2F

1 2

C472

C472 SCD1U16V

SCD1U16V

C470

C470 SCD1U16V

SCD1U16V

B

H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63

H_XRCOMP H_XSCOMP H_XSWING H_YRCOMP H_YSCOMP H_YSWING

C

U34A

E4 E1 F4 H7 E2 F1 E3 D3 K7 F2

J7

J8 H6 F3 K8 H5 H1 H2 K5 K6

J4

G3

H3

J1

L5 K4

J5 P7

L7

J3 P5

L3 U7 V6 R6 R5 P3 T8 R7 R8 U8 R4 T4 T5 R1 T3 V8 U6

W6

U3 V5

W8 W7

U2 U1 Y5 Y2 V4 Y7

W1 W3

Y3 Y6

W2

C1 C2 D1 T1

L1 P1

HD0# HD1# HD2# HD3# HD4# HD5# HD6# HD7# HD8# HD9# HD10# HD11# HD12# HD13# HD14# HD15# HD16# HD17# HD18# HD19# HD20# HD21# HD22# HD23# HD24# HD25# HD26# HD27# HD28# HD29# HD30# HD31# HD32# HD33# HD34# HD35# HD36# HD37# HD38# HD39# HD40# HD41# HD42# HD43# HD44# HD45# HD46# HD47# HD48# HD49# HD50# HD51# HD52# HD53# HD54# HD55# HD56# HD57# HD58# HD59# HD60# HD61# HD62# HD63#

HXRCOMP HXSCOMP HXSWING HYRCOMP HYSCOMP HYSWING

71.0GMCH.08U

HCPURST#

HOST

HDSTBN#0 HDSTBN#1 HDSTBN#2 HDSTBN#3

HCPUSLP#

HA3# HA4# HA5# HA6# HA7# HA8#

HA9# HA10# HA11# HA12# HA13# HA14# HA15# HA16# HA17# HA18# HA19# HA20# HA21# HA22# HA23# HA24# HA25# HA26# HA27# HA28# HA29# HA30# HA31#

HADS# HADSTB#0 HADSTB#1

HVREF

HBNR#

HBPRI#

HBREQ0#

HCLKINN HCLKINP

HDBSY#

HDEFER#

HDINV#0 HDINV#1 HDINV#2 HDINV#3 HDPWR#

HDRDY#

HDSTBP#0 HDSTBP#1 HDSTBP#2 HDSTBP#3

HEDRDY#

HHIT#

HHITM#

HLOCK#

HPCREQ#

HREQ#0 HREQ#1 HREQ#2 HREQ#3 HREQ#4

HRS0#

HRS1#

HRS2#

HTRDY#

G9 C9 E9 B7 A10 F9 D8 B10 E10 G10 D9 E11 F10 G11 G13 C10 C11 D11 C12 B13 A12 F12 G12 E12 C13 B11 D13 A13 F13

F8 B9 E13 J11 A5 D5 E7 H10

AB1 AB2

C6 E6 H8 K3 T7 U5 G6 F7 G4 K1 R3 V3 G5 K2 R2 W4 F6 D4 D6 B3 A11 A7 D7 B8 C7 A8 A4 C5 B4 G8 B5

H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31

H_VREF

H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3

H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3 TP_H_EDRDY#

TP_H_PCREQ# H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_RS#0 H_RS#1 H_RS#2 H_CPUSLP#_1

D

H_A#[31..3] 4H_D#[63..0]4

H_ADS# 4 H_ADSTB#0 4 H_ADSTB#1 4

H_BNR# 4

H_BPRI# 4

H_BREQ#0 4

H_CPURST# 4

CLK_MCH_BCLK# 3 CLK_MCH_BCLK 3

H_DBSY# 4

H_DEFER# 4

H_DPWR# 4

H_DRDY# 4

TP28TPAD28 TP28TPAD28

H_HIT# 4 H_HITM# 4

H_LOCK# 4

TP89TPAD28 TP89TPAD28

H_TRDY# 4

C237

1 2

SCD1U16V

H_DINV#[3..0] 4

H_DSTBN#[3..0] 4

H_DSTBP#[3..0] 4

H_REQ#[4..0] 4

H_RS#[2..0] 4

0R0402-PAD

R321

1 2

DUMMY FOR DOTHAN A STEPPING

1D05V_S0

12

R125

R125 100R2F

100R2F

R127

R127 200R2F

200R2F

E

H_CPUSLP# 4,15

1 1

A

Place them near to the chip

B

C

D

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

A3 Date: Sheet

Date: Sheet

GMCH (1 of 5)

Myna2 SB

E

of

647Monday, September 26, 2005

A

U34B

DMI_TXN0

DMI_TXN016

12

SC2D2U6D3V3MX-1

R120

R120 40D2R2F

40D2R2F

12

C418

3

M_CLK_DDR011 M_CLK_DDR111

M_CLK_DDR311 M_CLK_DDR411

M_CLK_DDR#011 M_CLK_DDR#111

M_CLK_DDR#311 M_CLK_DDR#411

M_OCDCOMP0 M_OCDCOMP1

12

SCD1U16V

BC11

PM_EXTTS#0 PM_EXTTS#1

A

DMI_TXN116 DMI_TXN216 DMI_TXN316

DMI_TXP016 DMI_TXP116 DMI_TXP216 DMI_TXP316

DMI_RXN016 DMI_RXN116 DMI_RXN216 DMI_RXN316

DMI_RXP016 DMI_RXP116 DMI_RXP216 DMI_RXP316

M_CKE011,12 M_CKE111,12 M_CKE211,12 M_CKE311,12

M_CS#011,12 M_CS#111,12 M_CS#211,12 M_CS#311,12

M_ODT011,12 M_ODT111,12 M_ODT211,12 M_ODT311,12

12

SC2D2U6D3V3MX-1

C466

12

SCD1U16V

BC10

M_RCOMPN M_RCOMPP

SMXSLEW SMYSLEW

4 4

3 3

Layout Note: Route as short as possible

12

R105

R105 40D2R2F

40D2R2F

DDR_VREF_S3

2 2

2D5V_S0

RN26

2 1 4

SRN10KJ

1D8V_S3

12

R124

R124 80D6R2F

80D6R2F

M_RCOMPN

M_RCOMPP

12

R126

R126 80D6R2F

80D6R2F

CFG[2:0] Freq.(MHz)

1 1

101 400 001 533

DMI_TXN1 DMI_TXN2 DMI_TXN3

DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3

DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3

DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3

AA31 AB35 AC31 AD35

AA35 AB31 AC35

AA33 AB37 AC33 AD37

AA37 AB33 AC37

AM33 AE11

AJ34 AC10 AN33 AE10

AJ33 AD10 AP21

AM21 AH21 AK21

AN16 AM14 AH15 AG16

AF22 AF16

AP14

AL15 AM11 AN10

AK10 AK11 AF37

AD1 AE27 AE28

AF9 AF10

Y31

Y33

AL1

AF6

AK1

AF5

DMIRXN0 DMIRXN1 DMIRXN2 DMIRXN3

DMIRXP0 DMIRXP1 DMIRXP2 DMIRXP3

DMITXN0 DMITXN1 DMITXN2 DMITXN3

DMITXP0 DMITXP1 DMITXP2 DMITXP3

SM_CK0 SM_CK1 SM_CK2 SM_CK3 SM_CK4 SM_CK5

SM_CK0# SM_CK1# SM_CK2# SM_CK3# SM_CK4# SM_CK5#

SM_CKE0 SM_CKE1 SM_CKE2 SM_CKE3

SM_CS0# SM_CS1# SM_CS2# SM_CS3#

SM_OCDCOMP0 SM_OCDCOMP1

SM_ODT0 SM_ODT1 SM_ODT2 SM_ODT3

SMRCOMPN SMRCOMPP SMVREF0 SMVREF1 SMXSLEWIN SMXSLEWOUT SMYSLEWIN SMYSLEWOUT

71.0GMCH.08U

PEG_RXN15_NB PEG_RXP15_NB PEG_RXN14_NB PEG_RXP14_NB

PEG_RXN13_NB PEG_RXP13_NB PEG_RXN12_NB PEG_RXP12_NB

PEG_TXP1 PEG_TXN1

DMI

DDR MUXING

CFG/RSVD

BM_BUSY#

EXT_TS0# EXT_TS1#

THRMTRIP#

PM

DREF_CLKN DREF_CLKP

DREF_SSCLKN

CLK

DREF_SSCLKP

NC

SB

C614 SCD1U16VC614 SCD1U16V

1 2

C615 SCD1U16VC615 SCD1U16V

1 2

C616 SCD1U16VC616 SCD1U16V

1 2

C617 SCD1U16VC617 SCD1U16V

1 2

SB

C618 SCD1U16VC618 SCD1U16V

1 2

C619 SCD1U16VC619 SCD1U16V

1 2

C620 SCD1U16VC620 SCD1U16V

1 2

C621 SCD1U16VC621 SCD1U16V

1 2

SB

C623 SCD1U16V

1 2

C622 SCD1U16V

1 2

B

CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8

CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 CFG18 CFG19 CFG20

RSVD21 RSVD22 RSVD23 RSVD24 RSVD25 RSVD26 RSVD27

PWROK

RSTIN#

NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8

NC9 NC10 NC11

DY

DY DY

DY

B

CFG0

G16 H13 G14 F16 F15 G15

CFG6

E16 D17 J16 D15 E15 D14

CFG12

E14

CFG13

H12 C14 H15 J15 H14 G22 G23 D23 G25 G24 J17 A31 A30 D26 D25

VGATE_PWRGD

J23

PM_EXTTS#0

J21

PM_EXTTS#1

H22 F5 AD30

PLT_RST1#_GMCH

AE29 A24

A23 C37 D37

AP37 AN37 AP36 AP2 AP1 AN1 B1 A2 B37 A36 A37

2D5V_S0

R118

1KR2

12

TPAD28

R98

10KR2

DY

CPU_SEL1 3 CPU_SEL0 3,4

R123

12

2K2R2F

TP26

TP26 TP27

TP27

-1

12

PM_BMBUSY# 16

PM_THRMTRIP-A# 4 VGATE_PWRGD 16,38

1 2

R96 100R2FR96 100R2F

DREFCLK# 3 DREFCLK 3 DREFSSCLK# 3 DREFSSCLK 3

12

C642

SC100P50V2JN-U

SDVOB_RN 45 SDVOB_RP 45 SDVOB_GN 45 SDVOB_GP 45

SDVOB_BN 45 SDVOB_BP 45 SDVOB_CLKN 45 SDVOB_CLKP 45

SDVOB_INTN 45 SDVOB_INTP 45

C645SC12P50V2JN-1 C645SC12P50V2JN-1 C646SC12P50V2JN-1 C646SC12P50V2JN-1 C644SC12P50V2JN-1 C644SC12P50V2JN-1

-1

1 2 1 2 1 2

GMCH_TV_COMP34 GMCH_TV_LUMA34 GMCH_TV_CRMA34

R107

R107 150R2F

150R2F

1 2

R110

R110 150R2F

150R2F

1 2

R112

R112 150R2F

150R2F

1 2

GMCH_VSYNC14 GMCH_HSYNC14

C

SDVOC_CTRLCLK45 SDVOC_CTRLDATA45

Alviso will provide SDVO_CTRLCLK and CTRLDATA pulldowns on-die

TP21 TPAD28TP21 TPAD28 TP19 TPAD28TP19 TPAD28

CLK_MCH_3GPLL#3 CLK_MCH_3GPLL3

12

R312

150R2F

150ohms150ohms 4K99ohms

GMCH_DDCCLK14 GMCH_DDCDATA14

GMCH_BLUE34

GMCH_GREEN34

GMCH_RED34

R111 39R2JR111 39R2J

1 2

R113 39R2JR113 39R2J

1 2

R109 255R2F-L-GPR109 255R2F-L-GP

1 2

SB_0823

GMCH_BL_ON30

PLT_RST1# 16,18,30,31,34

GMCH_LCDVDD_ON13

TP9 TPAD28TP9 TPAD28 TP13 TPAD28TP13 TPAD28 TP15 TPAD28TP15 TPAD28

LCTLA_CLK LCTLB_DATA

CLK_DDC_EDID DAT_DDC_EDID

GMCH_BL_ON LBKLT_CRTL LIBG

When Low choice lower than 3.5K Ohm

C

GMCH_TXACLK-13 GMCH_TXACLK+13 GMCH_TXBCLK-13 GMCH_TXBCLK+13

GMCH_TXAOUT0-13 GMCH_TXAOUT1-13 GMCH_TXAOUT2-13

GMCH_TXAOUT0+13 GMCH_TXAOUT1+13 GMCH_TXAOUT2+13

GMCH_TXBOUT0-13 GMCH_TXBOUT1-13 GMCH_TXBOUT2-13

GMCH_TXBOUT0+13 GMCH_TXBOUT1+13 GMCH_TXBOUT2+13

R309

CLK_DDC_EDID13 DAT_DDC_EDID13

12

R306

150R2F

1 2 3

R100 100KR2F-L1-GPR100 100KR2F-L1-GP

1 2

R101 100KR2F-L1-GPR101 100KR2F-L1-GP

1 2

R95 1K5R2FR95 1K5R2F

1 2

SDVOC_CTRLCLK SDVOC_CTRLDATA

SDVOC_CTRLDATA SDVOC_CTRLCLK

R115

R115 4K53R2F

4K53R2F

12

VSYNC HSYNC CRTIREF

LBKLT_CRTL LCTLA_CLK

LCTLB_DATA

LIBG

L_LVBG L_VREFH L_VREFL

SRN2K2J

RN30

4

SRN2K2J

RN29

4

AB29 AC29

2D5V_S0

H24

SDVOCTRL_DATA

H25

SDVOCTRL_CLK GCLKN GCLKP

A15

TVDAC_A

C16

TVDAC_B

A17

TVDAC_C

J18

TV_REFSET

B15

TV_IRTNA

B16

TV_IRTNB

B17

TV_IRTNC

E24

DDCCLK

E23

DDCDATA

E21

BLUE

D21

BLUE#

C20

GREEN

B20

GREEN#

A19

RED

B19

RED#

H21

VSYNC

G21

HSYNC

J20

REFSET

E25

LBKLT_CRTL

F25

LBKLT_EN

C23

LCTLA_CLK

C22

LCTLB_DATA

F23

LDDC_CLK

F22

LDDC_DATA

F26

LVDD_EN

C33

LIBG

C31

LVBG

F28

LVREFH

F27

LVREFL

B30

LACLKN

B29

LACLKP

C25

LBCLKN

C24

LBCLKP

B34

LADATAN0

B33

LADATAN1

B32

LADATAN2

A34

LADATAP0

A33

LADATAP1

B31

LADATAP2

C29

LBDATAN0

D28

LBDATAN1

C27

LBDATAN2

C28

LBDATAP0

D27

LBDATAP1

C26

LBDATAP2

U34G

71.0GMCH.08U

D

EXP_COMPI

EXP_ICOMPO

EXP_RXN0

MISCTVVGALVDS

EXP_RXN1 EXP_RXN2 EXP_RXN3 EXP_RXN4 EXP_RXN5 EXP_RXN6 EXP_RXN7 EXP_RXN8

EXP_RXN9 EXP_RXN10 EXP_RXN11 EXP_RXN12 EXP_RXN13 EXP_RXN14 EXP_RXN15

EXP_RXP0

EXP_RXP1

EXP_RXP2

EXP_RXP3

EXP_RXP4

EXP_RXP5

EXP_RXP6

EXP_RXP7

EXP_RXP8

EXP_RXP9

EXP_RXP10 EXP_RXP11 EXP_RXP12 EXP_RXP13 EXP_RXP14 EXP_RXP15

EXP_TXN0

EXP_TXN1

EXP_TXN2

EXP_TXN3

EXP_TXN4

EXP_TXN5

EXP_TXN6

PCI-EXPRESS GRAPHICS

EXP_TXN7

EXP_TXN8

EXP_TXN9

EXP_TXN10 EXP_TXN11 EXP_TXN12 EXP_TXN13 EXP_TXN14 EXP_TXN15

EXP_TXP0

EXP_TXP1

EXP_TXP2

EXP_TXP3

EXP_TXP4

EXP_TXP5

EXP_TXP6

EXP_TXP7

EXP_TXP8

EXP_TXP9

EXP_TXP10 EXP_TXP11 EXP_TXP12 EXP_TXP13 EXP_TXP14 EXP_TXP15

D

E

1D5V_PCIE_S0

PEG_COMP

D36

PEG_COMP

D34 E30

EXP_RXN1

F34

EXP_RXN2

G30 H34 J30 K34 L30 M34 N30 P34 R30 T34 U30 V34 W30 Y34

D30

EXP_RXP1

E34

EXP_RXP2

F30 G34 H30 J34 K30 L34 M30 N34 P30 R34 T30 U34 V30 W34

PEG_RXN15_NB

E32

PEG_RXN14_NB

F36

PEG_RXN13_NB

G32

PEG_RXN12_NB

H36 J32 K36 L32 M36 N32 P36 R32 T36 U32 V36 W32 Y36

PEG_RXP15_NB

D32

PEG_RXP14_NB

E36

PEG_RXP13_NB

F32

PEG_RXP12_NB

G36 H32 J36 K32 L36 M32 N36 P32 R36 T32 U36 V32 W36

Title

Size Document Number Rev

Size Document Number Rev Custom

Custom

Custom Date: Sheet of

Date: Sheet of

PEG_TXN1

PEG_TXP1

R9324D9R2F R9324D9R2F

12

TP7TPAD28 TP7TPAD28 TP10TPAD28 TP10TPAD28

TP4TPAD28 TP4TPAD28 TP11TPAD28 TP11TPAD28

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

GMCH (2 of 5)

Myna2 SB

747Monday, September 26, 2005

E

A

4 4

U34C

M_A_DQ[63..0]11 M_B_DQ[63..0]11

3 3

2 2

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

AG35 AH35

AL35 AL37

AH36

AJ35

AK37

AL34 AM36 AN35 AP32 AM31 AM34 AM35

AL32 AM32 AN31 AP31 AN28 AP28

AL30 AM30 AM28

AL28 AP27 AM27 AM23 AM22

AL23 AM24 AN22 AP22

AM9

AL9 AL6

AP7 AP11 AP10

AL7 AM7 AN5 AN6 AN3 AP3 AP6 AM6

AL4 AM3 AK2 AK3 AG2 AG1

AL3 AM2 AH3 AG3 AF3 AE3 AD6 AC4 AF2 AF1 AD4 AD5

U34C

SADQ0 SADQ1 SADQ2 SADQ3 SADQ4 SADQ5 SADQ6 SADQ7 SADQ8 SADQ9 SADQ10 SADQ11 SADQ12 SADQ13 SADQ14 SADQ15 SADQ16 SADQ17 SADQ18 SADQ19 SADQ20 SADQ21 SADQ22 SADQ23 SADQ24 SADQ25 SADQ26 SADQ27 SADQ28 SADQ29 SADQ30 SADQ31 SADQ32 SADQ33 SADQ34 SADQ35 SADQ36 SADQ37 SADQ38 SADQ39 SADQ40 SADQ41 SADQ42 SADQ43 SADQ44 SADQ45 SADQ46 SADQ47 SADQ48 SADQ49 SADQ50 SADQ51 SADQ52 SADQ53 SADQ54 SADQ55 SADQ56 SADQ57 SADQ58 SADQ59 SADQ60 SADQ61 SADQ62 SADQ63

SA_DQS0# SA_DQS1# SA_DQS2# SA_DQS3# SA_DQS4# SA_DQS5# SA_DQS6# SA_DQS7#

DDR SYSTEM MEMORY A

SA_RCVENIN#

SA_RCVENOUT#

SA_BS0# SA_BS1# SA_BS2#

SA_DM0 SA_DM1 SA_DM2 SA_DM3 SA_DM4 SA_DM5 SA_DM6 SA_DM7

SA_DQS0 SA_DQS1 SA_DQS2 SA_DQS3 SA_DQS4 SA_DQS5 SA_DQS6 SA_DQS7

SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8

SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13

SA_CAS# SA_RAS#

SA_WE#

B

AK15 AK16 AL21

M_A_DM0

AJ37

M_A_DM1

AP35

M_A_DM2

AL29

M_A_DM3

AP24

M_A_DM4

AP9

M_A_DM5

AP4

M_A_DM6

AJ2

M_A_DM7

AD3

M_A_DQS0

AK36

M_A_DQS1

AP33

M_A_DQS2

AN29

M_A_DQS3

AP23

M_A_DQS4

AM8

M_A_DQS5

AM4

M_A_DQS6

AJ1

M_A_DQS7

AE5

M_A_DQS#0

AK35

M_A_DQS#1

AP34

M_A_DQS#2

AN30

M_A_DQS#3

AN23

M_A_DQS#4

AN8

M_A_DQS#5

AM5

M_A_DQS#6

AH1

M_A_DQS#7

AE4

M_A_A0

AL17

M_A_A1

AP17

M_A_A2

AP18

M_A_A3

AM17

M_A_A4

AN18

M_A_A5

AM18

M_A_A6

AL19

M_A_A7

AP20

M_A_A8

AM19

M_A_A9

AL20

M_A_A10

AM16

M_A_A11

AN20

M_A_A12

AM20

M_A_A13

AM15 AN15

AP16

SA_RCVENIN#

AF29

SA_RCVENOUT#

AF28 AP15

Place Test PAD Near to Chip as could as possible

C

U34D

M_A_BS#0 11,12 M_A_BS#1 11,12 M_A_BS#2 11,12 M_A_DM[7..0] 11

M_A_DQS[7..0] 11

M_A_DQS#[7..0] 11

M_A_A[13..0] 11,12

M_A_CAS# 11,12 M_A_RAS# 11,12

TP12 TPAD28TP12 TPAD28 TP14 TPAD28TP14 TPAD28 TP24 TPAD28TP24 TPAD28

M_A_WE# 11,12

M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

AE31 AE32 AG32 AG36 AE34 AE33 AF31 AF30 AH33 AH32 AK31 AG30 AG34 AG33 AH31

AJ31

AK30

AJ30 AH29 AH28 AK29 AH30 AH27 AG28 AF24 AG23

AJ22 AK22 AH24 AH23 AG22

AJ21 AG10

AG9 AG8

AH8 AH11 AH10

AJ9

AK9

AJ7

AK6

AJ4 AH5 AK8

AJ8

AJ5 AK4 AG5 AG4 AD8 AD9 AH4 AG6 AE8 AD7 AC5 AB8 AB6 AA8 AC8 AC7 AA4 AA5

SBDQ0 SBDQ1 SBDQ2 SBDQ3 SBDQ4 SBDQ5 SBDQ6 SBDQ7 SBDQ8 SBDQ9 SBDQ10 SBDQ11 SBDQ12 SBDQ13 SBDQ14 SBDQ15 SBDQ16 SBDQ17 SBDQ18 SBDQ19 SBDQ20 SBDQ21 SBDQ22 SBDQ23 SBDQ24 SBDQ25 SBDQ26 SBDQ27 SBDQ28 SBDQ29 SBDQ30 SBDQ31 SBDQ32 SBDQ33 SBDQ34 SBDQ35 SBDQ36 SBDQ37 SBDQ38 SBDQ39 SBDQ40 SBDQ41 SBDQ42 SBDQ43 SBDQ44 SBDQ45 SBDQ46 SBDQ47 SBDQ48 SBDQ49 SBDQ50 SBDQ51 SBDQ52 SBDQ53 SBDQ54 SBDQ55 SBDQ56 SBDQ57 SBDQ58 SBDQ59 SBDQ60 SBDQ61 SBDQ62 SBDQ63

D

AJ15

SB_BS0#

AG17

SB_BS1#

AG21

SB_BS2#

AF32

SB_DM0

AK34

SB_DM1

AK27

SB_DM2

AK24

SB_DM3

AJ10

SB_DM4

AK5

SB_DM5

AE7

SB_DM6

AB7

SB_DM7

AF34

SB_DQS0

AK32

SB_DQS1

AJ28

SB_DQS2

AK23

SB_DQS3

AM10

SB_DQS4

AH6

SB_DQS5

AF8

SB_DQS6

AB4

SB_DQS7

SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8

SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13

SB_CAS# SB_RAS#

SB_WE#

AF35 AK33 AK28 AJ23 AL10 AH7 AF7 AB5

AH17 AK17 AH18 AJ18 AK18 AJ19 AK19 AH19 AJ20 AH20 AJ16 AG18 AG20 AG15

AH14 AK14 AF15 AF14 AH16

Place Test PAD Near to Chip ascould as possible

SB_DQS0# SB_DQS1# SB_DQS2# SB_DQS3# SB_DQS4# SB_DQS5# SB_DQS6# SB_DQS7#

DDR SYSTEM MEMORY B

SB_RCVENIN#

SB_RCVENOUT#

M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7

M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7

M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13

SB_RCVENIN# SB_RCVENOUT#

M_B_BS#0 11,12 M_B_BS#1 11,12 M_B_BS#2 11,12 M_B_DM[7..0] 11

M_B_DQS[7..0] 11

M_B_DQS#[7..0] 11

M_B_A[13..0] 11,12

M_B_CAS# 11,12 M_B_RAS# 11,12

TP25 TPAD28TP25 TPAD28

M_B_WE# 11,12

E

71.0GMCH.08U

1 1

A

B

C

71.0GMCH.08U

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

A3 Date: Sheet

Date: Sheet

D

Date: Sheet

GMCH (3 of 5)

Myna2 SB

E

of

847Monday, September 26, 2005

A

R315

1 2

0R0603-PAD

1KR2

R116

1 2

3D3V_S0

4 4

3 3

0R0603-PAD

R301

1 2

0R0603-PAD

R295

1 2

R292

1 2

10R3

D1U10V2MX

When PM replace to GM

3D3V_S0

12

C443

C443 SC10U10V5ZY

SC10U10V5ZY

Route ASSATVBG gnd from GMCH to decoupling cap groung lead and then connect to the gnd plane

3D3V_TVDACA_S0

12

C208

C208 SCD1U10V2MX-1

SCD1U10V2MX-1

3D3V_TVDACB_S0

12

C453

C453 SCD1U10V2MX-1

SCD1U10V2MX-1

3D3V_TVDACC_S0

12

C451

C451 SCD1U10V2MX-1

SCD1U10V2MX-1

3D3V_ATVBG_S0

12

C447

C447 SCD1U10V2MX-1

SCD1U10V2MX-1

D22

SSM5818SL

1D5V_S0

21

12

C202

C202 SC2D2U6D3V3MX-1-GP

SC2D2U6D3V3MX-1-GP

12

C452

C452 SC2D2U6D3V3MX-1-GP

SC2D2U6D3V3MX-1-GP

12

C450

C450 SC2D2U6D3V3MX-1-GP

SC2D2U6D3V3MX-1-GP

12

C446

C446 SC2D2U6D3V3MX-1-GP

SC2D2U6D3V3MX-1-GP

F17

VCCA_TVDACA0

1D5V_DLVDS_S0 1D8V_S3

G18

F18

E18

E17

D18

C18

VCCA_TVDACA1

VCCA_TVDACB0

VCCA_TVDACB1

VCCA_TVDACC0

VCCA_TVDACC1

H18

B26

B25

D19

H17

VSSA_TVBG

VCCA_TVBG

VCCD_LVDS0

VCCD_TVDAC

VCCDQ_TVDAC

1D5V_TVDAC_S0

1D5V_QTVDAC_S0

2D5V_ALVDS_S0

A35

A25

B22

VCCA_LVDS

VCCD_LVDS1

VCCD_LVDS2

B

D1U10V2MX

12

V1.8_DDR_CAP1

AM37

B21

A21

VCCHV0

VCCHV1

VCCHV2

VCCSM0

12

C454

C454 SCD1U10V2MX-1

SCD1U10V2MX-1

12

C455

C455 SCD1U10V2MX-1

SCD1U10V2MX-1

C416

C416 SCD1U10V2MX-1

SCD1U10V2MX-1

12

C417

C417 SCD1U10V2MX-1

SCD1U10V2MX-1

1 2

SCD1U10V2MX-1

V1.8_DDR_CAP2

V1.8_DDR_CAP5

AH37

AP29

AD28

AD27

AC27

AP26

VCCSM1

VCCSM2

VCCSM3

VCCSM4

VCCSM5

2D5V_TVDAC_S0

12

C448

Note: All VCCSM pins shorted internally

C442

AN26

AM26

AL26

AK26

AJ26

AH26

VCCSM6

VCCSM7

VCCSM8

VCCSM9

VCCSM10

VCCSM11

VCCSM12

AG26

AF26

VCCSM13

0R0603-PAD

1 2

0R0603-PAD

1 2

AE26

AP25

VCCSM14

VCCSM15

VCCSM16

R314

R320

12

C449

C449 SC10U10V5ZY

SC10U10V5ZY

AN25

AM25

AL25

VCCSM17

VCCSM18

VCCSM19

1D5V_S0

R294

1 2

AK25

AJ25

AH25

VCCSM20

VCCSM21

VCCSM22

POWER

0R3-U-GP

AG25

AF25

AE25

VCCSM23

VCCSM24

VCCSM25

2D5V_S0

AE24

AE23

VCCSM26

VCCSM27

C

1D5V_S0

0R0603-PAD

R290

1 2

C445

SCD1U10V2MX-1

2D5V_S0 2D5V_ALVDS_S0

0R0603-PAD

R286

1 2

SCD1U10V2MX-1

2D5V_S0 2D5V_TXLVDS_S0

0R0603-PAD

R287

1 2

SCD1U10V2MX-1

12

AE22

C182

AE21

AE20

VCCSM28

VCCSM29

VCCSM30

12

SC10U10V5ZY

AE19

AE18

AE17

AE16

AE15

VCCSM31

VCCSM32

VCCSM33

VCCSM34

C159

SC10U10V5ZY

AE14

AP13

AN13

VCCSM35

VCCSM36

VCCSM37

VCCSM38

AM13

VCCSM39

12

AL13

AK13

VCCSM40

VCCSM41

12

C428

12

C440

C224

SC10U10V5ZY

AJ13

AH13

AG13

AF13

VCCSM42

VCCSM43

VCCSM44

VCCSM45

1D5V_DLVDS_S0

12

C444

C444 SC10U10V5ZY

SC10U10V5ZY

12

C426

SCD01U16V2KX

12

C433

C433 SC4D7U10V5ZY

SC4D7U10V5ZY

AE13

AP12

AN12

AM12

AL12

VCCSM46

VCCSM47

VCCSM48

VCCSM49

VCCSM50

Note: All VCCSM pins shorted internally

SCD1U10V2MX-1

AK12

AJ12

AH12

AG12

VCCSM51

VCCSM52

VCCSM53

VCCSM54

C459

1 2

AF12

AE12

VCCSM55

VCCSM56

AD11

VCCSM57

AC11

AB11

VCCSM58

VCCSM59

D

12

V1.8_DDR_CAP4

V1.8_DDR_CAP6

AB10

AB9

AP8

AM1

VCCSM60

VCCSM61

VCCSM62

VCCSM63

C464

SCD1U10V2MX-1

12

C465

C465 SCD1U10V2MX-1

SCD1U10V2MX-1

2D5V_TXLVDS_S0

V1.8_DDR_CAP3

B28

A28

A27

AE1

VCCSM64

VCCTX_LVDS0

VCCTX_LVDS1

VCCTX_LVDS2

SCD1U10V2MX-1

AF20

AP19

AF19

AF18

VCCA_SM0

VCCA_SM1

VCCA_SM2

VCCA_SM3

AE37

VCC3G0

C187

W37

U37

VCC3G1

12

R37

VCC3G2

VCC3G3

12

C419

SC10U10V5ZY

12

N37

L37

J37

VCC3G4

VCC3G5

VCC3G6

12

C193

C193 ST100U6D3VM-U

ST100U6D3VM-U

12

C115

SC10U10V5ZY

DY

1D5V_3GPLL_S0

12

C146

SCD1U10V2MX-1

Y27

Y29

F37

Y28

VCCA_3GBG

VCCA_3GPLL2

VCCA_3GPLL0

VCCA_3GPLL1

E

R103

12

C118

1 2

SCD1U10V2MX-1

1D5V_S01D5V_DDRDLL_S0

0R0603-PAD

R276

0R0603-PAD

1 2

DY

?cost

1D5V_S0

0R0603-PAD

R277

1 2

C420

SC10U10V5ZY

2D5V_3GBG_S0 2D5V_S0

G37

VSSA_3GBG

0R0603-PAD

R92

1 2

12

C114

SCD1U10V2MX-1

U34E

71.0GMCH.08U

Route ASSA3GBG gnd from GMCH to decoupling cap groung lead and then connect to the gnd plane

1D5V_S01D5V_PCIE_S0

VCC 1D05_S0 for low speed graphic clock.1D5V_S0 for high speed clock.default

2 2

1 1

use 1D05V_S0

1D05V_S0

12

C137

SC10U10V5ZY

Graphic Freq. /Memory Freq.

200MHZ/DDR333

200MHZ/DDR2

-400/533

320MHZ/DDR2

-400/533

12

C207

SC10U10V5ZY

12

C178

SC10U10V5ZY

1D05V 1D5V

YES YES

NO YES

A

12

C201

SCD1U10V2MX-1

YESYES

VCC0

VCC1

T29

R29

12

VCC2

VCC3

VCC4

VCC5

J29

K29

N29

M29

C136

SCD1U10V2MX-1

VCC6

V28

U28

12

1D5V_S0

VCC7

VCC8

VCC9

VCC10

VCC11

T28

P28

R28

N28

C167

SCD1U10V2MX-1

VCC12

VCC13

VCC14

L28

K28

M28

12

R132

0R0805-PAD

VCC15

VCC16

VCC17

VCC18

VCC19

J28

V27

H28

U27

G28

C200

SCD1U10V2MX-1

12

VCC20

VCC21

VCC22

VCC23

T27

P27

R27

N27

L13

1 2

IND-D1UH-GP

L5

1 2

IND-D1UH-GP

L8

1 2

IND-D1UH-GP

L7

1 2

IND-D1UH-GP

B

M27

VCC24

L27

VCC25

K27

VCC26

J27

VCC27

H27

VCC28

K26

12

VCC29

VCC30

VCC31

VCC32

VCC33

VCC34

J25

K25

K24

K23

H26

C436

C436 SC10U10V5ZY

SC10U10V5ZY

C116

C116 SC10U10V5ZY

SC10U10V5ZY

C243

C243 SC10U10V5ZY

SC10U10V5ZY

C242

C242 SC10U10V5ZY

SC10U10V5ZY

VCC35

K22

K21

VCC36

W20

VCC37

VCC38

VCC39

VCC40

VCC41

T20

K20

V19

U20

12

C174

C174 SCD1U10V2MX-1

SCD1U10V2MX-1

12

C119

C119 SCD1U10V2MX-1

SCD1U10V2MX-1

12

C468

C468 SCD1U10V2MX-1

SCD1U10V2MX-1

12

C467

C467 SCD1U10V2MX-1

SCD1U10V2MX-1

VCC42

VCC43

VCC44

VCC45

VCC46

T18

K19

V18

K18

U19

W18

1D5V_HMPLL_S0

1D5V_DPLLA_S0

1D5V_DPLLB_S0

1D5V_HPLL_S0

1D5V_MPLL_S0

VCC47

K17

VCC48

VCCH_MPLL1

VCCH_MPLL0

VCCA_DPLLA

VCCA_DPLLB

VCCA_HPLL

VCCA_MPLL

VCCA_CRTDAC0

VCCA_CRTDAC1

VSSA_CRTDAC

VCC_SYNC

VTT0

VTT1

VTT2

VTT3

VTT4

VTT5

VTT6

VTT7

VTT8

VTT9

VTT10

VTT11

VTT12

VTT13

VTT14

VTT15

VTT16

VTT17

VTT18

VTT19

VTT20

VTT21

VTT22

VTT23Y9VTT24W9VTT25U9VTT26R9VTT27P9VTT28N9VTT29M9VTT30L9VTT31J9VTT32N8VTT33M8VTT34N7VTT35M7VTT36N6VTT37M6VTT38A6VTT39N5VTT40M5VTT41N4VTT42M4VTT43N3VTT44M3VTT45N2VTT46M2VTT47B2VTT48V1VTT49N1VTT50M1VTT51

F19

B23

AC2

AC1

E19

C35

AA1

AA2

G19

C

J13

K13

K12

H20

GMCH_VCC_SYNC

V11

U11

W11

2D5V_CRTDAC_S0

R117

1 2

0R0402-PAD

Layout Notes: VSSA_CRTDAC Route caps within 250mil of Alviso. Route FB within 3" of Alviso.

L11

T11

P11

R11

N11

M11

T10

K11

V10

U10

W10

0R0603-PAD

R114

1 2

12

C194

C194 SCD1U10V2MX-1

SCD1U10V2MX-1

12

C189

C189 SCD1U10V2MX-1

SCD1U10V2MX-1

Route VSSA_CRTDAC gnd from GMCH to decoupling cap ground lead and then connect to the gnd plane.

R10

P10

N10

2D5V_S0

J10

K10

M10

1 2

D

R119

1KR2

VCCP_GMCH_CAP1

12

C473

1D05V_S0

12

C469

SCD47U10V3ZY

12

C461

SCD47U10V3ZY

1D5V_S0

D10

21

SSM5818SL

SC4D7U10V5ZY

Title

Size Document Number Rev

Size Document Number Rev A3

A3

A3 Date: Sheet

Date: Sheet

G1

VCCP_GMCH_CAP3

VCCP_GMCH_CAP4

VCCP_GMCH_CAP2

12

C471

SCD22U16V3ZY

C138

GMCH (4 of 5)

SCD22U16V3ZY

12

SC2D2U6D3V3MX-1

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Myna2 SB

C163

12

C188

SCD1U10V2MX-1

of

947Monday, September 26, 2005

E

A

H29

G29

F29

E29

D29

A29

AC28

AB28

AA28

W28

E28

AN27

AL27

AJ27

AG27

AF27

AB27

AA27

W27

G27

E27

B27

J26

G26

E26

A26

AN24

U34F

4 4

71.0GMCH.08U

AL24

VSS110

VSS111

VSS112

VSS113

VSS114

VSS115

VSS116

VSS117

VSS118

VSS119

VSS120

VSS121

VSS122

VSS123

VSS124

VSS125

VSS126

VSS127

VSS128

VSS129

VSS261

VSS262

VSS263

VSS264

VSS265

VSS266

VSS267

VSS259P2VSS258T2VSS257V2VSS256

VSS255

VSS254

VSS253

VSS252

VSS251A3VSS250C3VSS249

VSS248

VSS247

VSS246

AA3

AB3

AC3

VSS245C4VSS244H4VSS243L4VSS242P4VSS241U4VSS240Y4VSS239

AJ3

AF4

VSSALVDS

B36

VSS260L2VSS268J2VSS269G2VSS270D2VSS271

Y1

AL2

AE2

AD2

AH2

AN2

B

V31

U31

T31

R31

P31

N31

M31

L31

K31

J31

H31

G31

F31

E31

D31

AP30

AE30

AC30

AB30

AA30

Y30

C30

AM29

AJ29

AG29

AD29

AA29

W29

V29

U29

P29

L29

VSS77

VSS78

VSS79

VSS80

VSS81

VSS82

VSS83

VSS84

VSS85

VSS86

VSS87

VSS88

VSS89

VSS90

VSS91

VSS92

VSS93

VSS94

VSS95

VSS96

VSS97

VSS98

VSS99

VSS100

VSS101

VSS102

VSS103

VSS104

VSS105

VSS106

VSS107

VSS108

VSS109

VSS238

VSS237E5VSS236W5VSS235

VSS234

VSS233B6VSS232J6VSS231L6VSS230P6VSS229T6VSS228

AL5

AP5

AN4

AA6

VSS227

VSS226

VSS225

VSS224G7VSS223V7VSS222

VSS221

VSS220

VSS219

VSS218C8VSS217E8VSS216L8VSS215P8VSS214Y8VSS213

AJ6

AE6

AA7

AC6

AK7

AN7

AG7

VSS212A9VSS211H9VSS210K9VSS209T9VSS208V9VSS207

AL8

AA9

W31

AC9

C

C34

AL33

AF33

AD33

W33

V33

U33

T33

R33

P33

N33

M33

L33

K33

J33

H33

G33

F33

E33

D33

AN32

AJ32

AD32

AC32

AB32

AA32

Y32

C32

A32

AL31

AG31

AD31

VSS45

VSS46

VSS47

VSS48

VSS49

VSS50

VSS51

VSS52

VSS53

VSS54

VSS55

VSS56

VSS57

VSS58

VSS59

VSS60

VSS61

VSS62

VSS63

VSS64

VSS65

VSS66

VSS67

VSS68

VSS69

VSS70

VSS71

VSS72

VSS73

VSS74

VSS75

VSS76

VSS

VSS196

VSS195

VSS194

VSS193

VSS192

VSS191

VSS190

VSS189

VSS188

VSS187

VSS186

VSS185

VSS184

VSS183

VSS182

VSS181

VSS180

VSS179

VSS178

VSS177

VSS176

VSS206

VSS205

VSS204

VSS203

VSS202

VSS201

VSS200

VSS199

VSS198

VSS197

J12

AE9

L10

F11

Y11

Y10

D10

AH9

AN9

H11

AA11

AA10

AF11

B12

AJ11

AL11

AN11

AG11

D12

J14

F14

A14

B14

K14

AG14

VSS175

K15

A16

C15

AJ14

D16

AL14

AN14

D

AF36

AE36

AD36

AC36

AB36

AA36

C36

AE35

Y35

W35

V35

U35

T35

R35

P35

N35

M35

L35

K35

J35

H35

G35

F35

E35

D35

B35

AN34

AH34

AD34

AC34

AB34

AA34

VSS12

VSS13

VSS14

VSS15

VSS16

VSS17

VSS18

VSS19

VSS20

VSS21

VSS22

VSS23

VSS24

VSS25

VSS26

VSS27

VSS28

VSS29

VSS30

VSS31

VSS32

VSS33

VSS34

VSS35

VSS36

VSS37

VSS38

VSS39

VSS40

VSS41

VSS42

VSS43

VSS44

VSS174

VSS173

VSS172

VSS171

VSS170

VSS169

VSS168

VSS167

VSS166

VSS165

VSS164

VSS163

VSS162

VSS161

VSS160

VSS159

VSS158

VSS157

VSS156

VSS155

VSS154

VSS153

VSS152

VSS151

VSS150

VSS149

VSS148

VSS147

VSS146

VSS145

VSS144

VSS143

VSS142

J19

H16

K16

AL16

C17

G17

AF17

A18

B18

AJ17

AN17

U18

T19

C19

H19

W19

AL18

F20

G20

F21

V20

A22

C21

D22

AF21

AK20

AN21

A20

E20

D20

AN19

AG19

E

AG37

Y37

V37

T37

P37

M37

K37

H37

E37

AN36

AL36

AJ36

VSS0

VSS1

VSS2

VSS3

VSS4

VSS5

VSS6

VSS7

VSS8

VSS9

VSS10

VSS11

VSS141

VSS140

VSS139

VSS138

VSS137

VSS136

VSS135

VSS134

VSS133

VSS132

VSS131

VSS130

J22

E22

AL22

AH22

H23

AF23

J24

F24

B24

D24

AJ24

AG24

1D8V_S3

AD14

AC14

VCCSM_NCTF25

VCCSM_NCTF26

SCD1U10V2MX-1

AC16

AD15

AC15

VCCSM_NCTF21

VCCSM_NCTF22

VCCSM_NCTF23

VCCSM_NCTF24

12

C156

AC17

AD16

VCCSM_NCTF19

VCCSM_NCTF20

1D05V_S0

AD17

12

C213

3 3

U34H

71.0GMCH.08U

2 2

71.0GMCH.08U

AC12

AB12

VCCSM_NCTF31

AB13

AD12

VCCSM_NCTF29

VCCSM_NCTF30

VCCSM_NCTF28

SC10U10V5ZY

AD13

AC13

VCCSM_NCTF27

Place these Hi-Freq decoupling caps near GMCH

DY

SCD1U10V2MX-1

AC19

AD18

AC18

VCCSM_NCTF15

VCCSM_NCTF16

VCCSM_NCTF17

VCCSM_NCTF18

12

C221

AC20

AD19

VCCSM_NCTF13

VCCSM_NCTF14

SCD1U10V2MX-1

AC22

AD21

AC21

AD20

VCCSM_NCTF10

VCCSM_NCTF11

VCCSM_NCTF12

VTT_NCTF17

VTT_NCTF16

L12

N12

M12

12

C226

AD22

VCCSM_NCTF9

VTT_NCTF15

P12

AD24

AC24

AD23

AC23

VCCSM_NCTF4

VCCSM_NCTF5

VCCSM_NCTF6

VCCSM_NCTF7

VCCSM_NCTF8

VTT_NCTF14

VTT_NCTF13

VTT_NCTF12

VTT_NCTF11

VTT_NCTF10

T12

V12

R12

U12

12

C162

SCD1U10V2MX-1

AD26

AC26

AD25

AC25

L17

VCC_NCTF78

VCCSM_NCTF0

VCCSM_NCTF1

VCCSM_NCTF2

VCCSM_NCTF3

VTT_NCTF9

VTT_NCTF8

VTT_NCTF7

VTT_NCTF6

VTT_NCTF5

VTT_NCTF4

L13

P13

N13

R13

M13

W12

12

C161

DY

SCD1U10V2MX-1

V17

U17

T17

P17

N17

M17

VCC_NCTF72

VCC_NCTF73

VCC_NCTF74

VCC_NCTF75

VCC_NCTF76

VCC_NCTF77

VTT_NCTF3

VTT_NCTF2

VTT_NCTF1

VTT_NCTF0

T13

V13

U13

W13

SCD1U16V

DY

W17

VCC_NCTF71

12

C225

P18

N18

L18

M18

VCC_NTTF69

VCC_NCTF68

VCC_NCTF70

VSS_NCTF68

Y12

AA12

12

C142

SCD1U16V

M19

L19

Y18

R18

VCC_NCTF64

VCC_NCTF65

VCC_NCTF66

VCC_NCTF67

VSS_NCTF67

VSS_NCTF66

VSS_NCTF65

VSS_NCTF64

L14

Y13

M14

AA13

SCD1U16V

Y19

R19

P19

N19

VCC_NCTF60

VCC_NCTF61

VCC_NCTF62

VCC_NCTF63

VSS_NCTF63

VSS_NCTF62

VSS_NCTF61

VSS_NCTF60

T14

P14

N14

R14

12

C238

P20

N20

M20

L20

VCC_NCTF56

VCC_NCTF57

VCC_NCTF58

VCC_NCTF59

NCTF

VSS_NCTF59

VSS_NCTF58

VSS_NCTF57

VSS_NCTF56

V14

Y14

U14

W14

12

C160

SCD1U16V

DY

M21

L21

Y20

R20

VCC_NCTF52

VCC_NCTF53

VCC_NCTF54

VCC_NCTF55

VSS_NCTF55

VSS_NCTF54

VSS_NCTF53

VSS_NCTF52

L15

M15

AA14

AB14

?cost

P21

N21

U21

T21

VCC_NCTF49

VCC_NCTF50

VCC_NCTF51

VCC_NCTF47

VCC_NCTF48

VSS_NCTF51

VSS_NCTF50

VSS_NCTF49

VSS_NCTF48

VSS_NCTF47

T15

P15

N15

R15

M22

L22

W21

V21

VCC_NCTF44

VCC_NCTF45

VCC_NCTF46

VSS_NCTF46

VSS_NCTF45

VSS_NCTF44

V15

Y15

U15

W15

R22

P22

N22

VCC_NCTF40

VCC_NCTF41

VCC_NCTF42

VCC_NCTF43

VSS_NCTF43

VSS_NCTF42

VSS_NCTF41

VSS_NCTF40

L16

AA15

AB15

W22

V22

U22

T22

VCC_NCTF37

VCC_NCTF38

VCC_NCTF39

VSS_NCTF39

VSS_NCTF38

VSS_NCTF37

P16

N16

R16

M16

P23

N23

M23

L23

VCC_NCTF33

VCC_NCTF34

VCC_NCTF35

VCC_NCTF36

VSS_NCTF36

VSS_NCTF35

VSS_NCTF34

VSS_NCTF33

T16

V16

U16

W16

V23

U23

T23

R23

VCC_NCTF29

VCC_NCTF30

VCC_NCTF31

VCC_NCTF32

VSS_NCTF32

VSS_NCTF31

VSS_NCTF30

VSS_NCTF29

Y16

R17

AA16

AB16

N24

M24

L24

W23

VCC_NCTF25

VCC_NCTF26

VCC_NCTF27

VCC_NCTF28

VSS_NCTF28

VSS_NCTF27

VSS_NCTF26

VSS_NCTF25

Y17

AA17

AB17

AA18

U24

T24

R24

P24

VCC_NCTF21

VCC_NCTF22

VCC_NCTF23

VCC_NCTF24

VSS_NCTF24

VSS_NCTF23

VSS_NCTF22

VSS_NCTF21

AB18

AA19

AB19

AA20

M25

L25

W24

V24

VCC_NCTF17

VCC_NCTF18

VCC_NCTF19

VCC_NCTF20

VSS_NCTF20

VSS_NCTF19

VSS_NCTF18

VSS_NCTF17

Y21

R21

AB20

AA21

R25

P25

N25

VCC_NCTF13

VCC_NCTF14

VCC_NCTF15

VCC_NCTF16

VSS_NCTF16

VSS_NCTF15

VSS_NCTF14

VSS_NCTF13

Y22

AB21

AA22

W25

V25

U25

T25

VCC_NCTF10

VCC_NCTF11

VCC_NCTF12

VSS_NCTF12

VSS_NCTF11

VSS_NCTF10

Y23

AB22

AA23

AB23

N26

M26

L26

VCC_NCTF6

VCC_NCTF7

VCC_NCTF8

VCC_NCTF9

VSS_NCTF9

VSS_NCTF8

VSS_NCTF7

VSS_NCTF6

Y24

AA24

AB24

T26

R26

P26

VCC_NCTF3

VCC_NCTF4

VCC_NCTF5

VSS_NCTF5

VSS_NCTF4

VSS_NCTF3

Y25

AA25

AB25

1D05V_S0

W26

V26

U26

VCC_NCTF0

VCC_NCTF1

VCC_NCTF2

VSS_NCTF2

VSS_NCTF1

VSS_NCTF0

Y26

AA26

AB26

1 1

A

B

C

D

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

A3 Date: Sheet

Date: Sheet

GMCH (5 of 5)

Myna2

E

of

10 47Monday, September 26, 2005

SB

A

DM1

MH1

M_B_A[13..0]8,12

4 4

M_B_BS#28,12

M_B_BS#08,12 M_B_BS#18,12

M_B_DQ[63..0]8

3 3

2 2

M_CS#27,12 M_CS#37,12 M_CKE27,12

M_CKE37,12 M_B_RAS#8,12 M_B_CAS#8,12

M_B_WE#8,12

SMBC_ICH3,18

1 1

DDR_VREF_S3

SMBD_ICH3,18

M_ODT37,12

C101

SC4D7U10V5ZY

12

BC3

BC3 SCD1U16V

SCD1U16V

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13

M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

SB

A

MH1

102

A0

101

A1

100

A2

99

A3

98

A4

97

A5

94

A6

92

A7

93

A8

91

A9

105

A10/AP

90

A11

89

A12

116

A13

86

A14

84

A15

85

A16_BA2

107

BA0

106

BA1

5

DQ0

7

DQ1

17

DQ2

19

DQ3

4

DQ4

6

DQ5

14

DQ6

16

DQ7

23

DQ8

25

DQ9

35

DQ10

37

DQ11

20

DQ12

22

DQ13

36

DQ14

38

DQ15

43

DQ16

45

DQ17

55

DQ18

57

DQ19

44

DQ20

46

DQ21

56

DQ22

58

DQ23

61

DQ24

63

DQ25

73

DQ26

75

DQ27

62

DQ28

64

DQ29

74

DQ30

76

DQ31

123

DQ32

125

DQ33

135

DQ34

137

DQ35

124

DQ36

126

DQ37

134

DQ38

136

DQ39

141

DQ40

143

DQ41

151

DQ42

153

DQ43

140

DQ44

142

DQ45

152

DQ46

154

DQ47

157

DQ48

159

DQ49

173

DQ50

175

DQ51

158

DQ52

160

DQ53

174

DQ54

176

DQ55

179

DQ56

181

DQ57

189

DQ58

191

DQ59

180

DQ60

182

DQ61

192

DQ62

194

DQ63

50

NC#50

69

NC#69

83

NC#83

120

NC#120

163

NC#163/TEST

110

CS0#

115

CS1#

79

CKE0

80

CKE1

108

RAS#

113

CAS#

109

WE#

197

SCL

195

SDA

114

ODT0

119

ODT1

1

VREF

201

GND

DDR2-200P-5-GP

BTN SIDE(H=5.2mm) BTN SIDE(H=9.2mm)

62.10017.771

MH2

13

DQS0

31

DQS1

51

DQS2

70

DQS3

131

DQS4

148

DQS5

169

DQS6

188

DQS7

11

DQS0#

29

DQS1#

49

DQS2#

68

DQS3#

129

DQS4#

146

DQS5#

167

DQS6#

186

DQS7#

10

DM0

26

DM1

52

DM2

67

DM3

130

DM4

147

DM5

170

DM6

185

DM7

30

CK0

32

CK0#

164

CK1

166

CK1#

198

SA0

200

SA1

199

VDD_SPD

81

VDD

82

VDD

87

VDD

88

VDD

95

VDD

96

VDD

103

VDD

104

VDD

111

VDD

112

VDD

117

VDD

118

VDD

2

VSS

3

VSS

8

VSS

9

VSS

12

VSS

15

VSS

18

VSS

21

VSS

24

VSS

27

VSS

28

VSS

33

VSS

34

VSS

39

VSS

40

VSS

41

VSS

42

VSS

47

VSS

48

VSS

53

VSS

54

VSS

59

Normal TYPE

VSS

60

VSS

65

VSS

66

VSS

71

VSS

72

VSS

77

VSS

78

VSS

121

VSS

122

VSS

127

VSS

128

VSS

132

VSS

133

VSS

138

VSS

139

VSS

144

VSS

145

VSS

149

VSS

150

VSS

155

VSS

156

VSS

161

VSS

162

VSS

165

VSS

168

VSS

171

VSS

172

VSS

177

VSS

178

VSS

183

VSS

184

VSS

187

VSS

190

VSS

193

VSS

196

VSS

202

GND

M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7 M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7

M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7

BC5

BC5 SCD1U16V

SCD1U16V

B

12

1D8V_S3

M_B_DQS[7..0] 8

M_B_DQS#[7..0] 8

M_B_DM[7..0] 8

M_CLK_DDR3 7 M_CLK_DDR#3 7 M_CLK_DDR4 7 M_CLK_DDR#4 7

3D3V_S0

12

C240

C240 SC2D2U6D3V3MX-1

SC2D2U6D3V3MX-1

DY

3D3V_S0

R129

1 2

10KR2

12

R128

R128 10KR2

10KR2

Place near DM2

12

C216 SC10P50V2JN-1

DY

12

C104 SC10P50V2JN-1

DY

M_CLK_DDR4

M_CLK_DDR#4 M_CLK_DDR3

M_CLK_DDR#3

C

M_A_A[13..0]8,12

M_A_DQ[63..0]8

M_A_DQS#[7..0]8

M_A_DQS[7..0]8

DDR_VREF_S3

SC4D7U10V5ZY

SB

C

D

DM2

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13

M_A_BS#28,12 M_A_BS#08,12

M_A_BS#18,12

M_ODT07,12 M_ODT17,12M_ODT27,12

12

C102

12

BC4

BC4 SCD1U16V

SCD1U16V

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7

M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7

DM2

102

A0

101

A1

100

A2

99

A3

98

A4

97

A5

94

A6

92

A7

93

A8

91

A9

105

A10/AP

90

A11

89

A12

116

A13

86

A14

84

A15

85

A16/BA2

107

BA0

106

BA1

5

DQ0

7

DQ1

17

DQ2

19

DQ3

4

DQ4

6

DQ5

14

DQ6

16

DQ7

23

DQ8

25

DQ9

35

DQ10

37

DQ11

20

DQ12

22

DQ13

36

DQ14

38

DQ15

43

DQ16

45

DQ17

55

DQ18

57

DQ19

44

DQ20

46

DQ21

56

DQ22

58

DQ23

61

DQ24

63

DQ25

73

DQ26

75

DQ27

62

DQ28

64

DQ29

74

DQ30

76

DQ31

123

DQ32

125

DQ33

135

DQ34

137

DQ35

124

DQ36

126

DQ37

134

DQ38

136

DQ39

141

DQ40

143

DQ41

151

DQ42

153

DQ43

140

DQ44

142

DQ45

152

DQ46

154

DQ47

157

DQ48

159

DQ49

173

DQ50

175

DQ51

158

DQ52

160

DQ53

174

DQ54

176

DQ55

179

DQ56

181

DQ57

189

DQ58

191

DQ59

180

DQ60

182

DQ61

192

DQ62

194

DQ63

11

/DQS0

29

/DQS1

49

/DQS2

68

/DQS3

129

/DQS4

146

/DQS5

167

/DQS6

186

/DQS7

13

DQS0

31

DQS1

51

DQS2

70

DQS3

131

DQS4

148

DQS5

169

DQS6

188

DQS7

114

ODT0

119

ODT1

1

VREF

2

VSS

202

GND

DDR2-200P-4-GP

62.10017.761

108

/RAS

109

/WE

113

/CAS

110

/CS0

115

/CS1

79

CKE0

80

CKE1

30

CK0

32

/CK0

164

CK1

166

/CK1 DM0

DM1 DM2 DM3 DM4 DM5 DM6 DM7

SDA

VDDSPD

NC#50 NC#69 NC#83

NC#120

NC#163/TEST

VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD

Normal TYPE

GND

D

SCL

SA0 SA1

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

M_A_DM0

10

M_A_DM1

26

M_A_DM2

52

M_A_DM3

67

M_A_DM4

130

M_A_DM5

147

M_A_DM6

170

M_A_DM7

185

SMBD_ICH

195

SMBC_ICH

197 199 198

200

12

50 69 83 120 163

81 82 87 88 95 96 103 104 111 112 117 118

3 8 9 12 15 18 21 24 27 28 33 34 39 40 41 42 47 48 53 54 59 60 65 66 71 72 77 78 121 122 127 128 132 133 138 139 144 145 149 150 155 156 161 162 165 168 171 172 177 178 183 184

187 190 193 196

201

Title

Size Document Number Rev

Date: Sheet

R131

R131 10KR2

10KR2

Custom

12

1D8V_S3

M_CLK_DDR0 7 M_CLK_DDR#0 7

M_CLK_DDR1 7 M_CLK_DDR#1 7

R130

R130 10KR2

10KR2

M_A_RAS# 8,12 M_A_WE# 8,12 M_A_CAS# 8,12

M_CS#0 7,12 M_CS#1 7,12

M_CKE0 7,12 M_CKE1 7,12

M_A_DM[7..0] 8

BC6

BC6 SCD1U16V

SCD1U16V

Place near DM1

12

C105 SC10P50V2JN-1

DY

12

C220 SC10P50V2JN-1

DY

DDR Socket

E

3D3V_S0

12

C241

C241 SC2D2U6D3V3MX-1

SC2D2U6D3V3MX-1

M_CLK_DDR0

M_CLK_DDR#0 M_CLK_DDR1

M_CLK_DDR#1

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Myna2 SB

11 47Monday, September 26, 2005

of

E

of

A

B

C

D

E

PARALLEL TERMINATION Decoupling Capacitor

VTT_S0

4 4

3 3

2 2

1 1

A

Put decap near power(0.9V) and pull-up resistor

RN53

1

8

2

7 6

SRN56-1

R275 56R2FR275 56R2F

1 2

R274 56R2FR274 56R2F

1 2

R108 56R2FR108 56R2F

1 2

R94 56R2FR94 56R2F

1 2

8 7 6

SRN56-1

8 7 6

SRN56-1

8 7 6

SRN56-1

8 7 6

SRN56-1

8 7 6

SRN56-1

8 7 6

SRN56-1

8 7 6

SRN56-1

8 7 6

SRN56-1

8 7 6

SRN56-1

8 7 6

SRN56-1

8 7 6

SRN56-1

RN49

RN52

RN51

RN50

RN54

RN31

RN27

RN23

RN28

RN24

RN25

3 45

1 2 3 45

M_B_A13

M_B_A12 M_B_A8

M_B_A9

M_B_A2 M_B_A0

M_B_A6 M_B_A4 M_B_A1 M_B_A10

M_B_A5 M_B_A3 M_B_A11 M_B_A7

M_A_A13

M_A_A3 M_A_A0

M_A_A10

M_A_A8 M_A_A9

M_A_A12 M_A_A6 M_A_A11 M_A_A7

M_A_A4 M_A_A5 M_A_A2 M_A_A1

M_B_WE# 8,11

M_B_CAS# 8,11

M_CS#2 7,11

M_ODT2 7,11

M_B_BS#0 8,11

M_CKE2 7,11

M_B_BS#2 8,11

M_ODT1 7,11 M_CKE0 7,11

M_CKE3 7,11

M_B_BS#1 8,11 M_B_RAS# 8,11

M_ODT3 7,11

M_CS#3 7,11

M_A_WE# 8,11

M_CS#1 7,11 M_ODT0 7,11

M_A_BS#1 8,11

M_CKE1 7,11

M_A_BS#2 8,11

M_A_BS#0 8,11

M_A_RAS# 8,11

M_CS#0 7,11

M_A_CAS# 8,11

B

M_A_A[13..0] 8,11 M_B_A[13..0] 8,11

VTT_S0

1D8V_S3

12

C429

C429 SCD1U16V

SCD1U16V

12

C438

C438 SCD1U16V

SCD1U16V

12

C439

C439 SC2D2U6D3V3MX-1

SC2D2U6D3V3MX-1

12

C144

DY

SCD1U16V

Put decap near power(0.9V) and pull-up resistor

DY

12

C427

SCD1U16V

12

C166

DY

SCD1U16V

12

C132

C132 SC2D2U6D3V3MX-1

SC2D2U6D3V3MX-1

12

C123

DY

12

DY

C

SCD1U16V

C124

SCD1U16V

12

DY

12

C430

C441

C441 SCD1U16V

SCD1U16V

C173

C173 SCD1U16V

SCD1U16V

C430 SCD1U16V

SCD1U16V

12

C122

C122 SCD1U16V

SCD1U16V

Place these Caps near DM1

12

C129

C129 SC2D2U6D3V3MX-1

SC2D2U6D3V3MX-1

C143

SCD1U16V

12

C120

SCD1U16V

12

Place these Caps near DM2

12

C435

C435 SC2D2U6D3V3MX-1

SC2D2U6D3V3MX-1

C121

SCD1U16V

DY

12

DY

C117

SCD1U16V

12

C432

C432 SCD1U16V

SCD1U16V

12

C125

C125 SCD1U16V

SCD1U16V

12

C140

C140 SC2D2U6D3V3MX-1

SC2D2U6D3V3MX-1

12

C431

C431 SC2D2U6D3V3MX-1

SC2D2U6D3V3MX-1

12

C434

C434 SCD1U16V

SCD1U16V

12

C130

C130 SCD1U16V

SCD1U16V

12

C423

C423 SCD1U16V

SCD1U16V

12

C127

C127 SCD1U16V

SCD1U16V

12

C126

C126 SC2D2U6D3V3MX-1

SC2D2U6D3V3MX-1

12

C425

C425 SC2D2U6D3V3MX-1

SC2D2U6D3V3MX-1

D

DY

12

C421

12

C135

SCD1U16V

DY

SCD1U16V

12

C424

C424 SC2D2U6D3V3MX-1

SC2D2U6D3V3MX-1

12

C422

C422 SCD1U16V

SCD1U16V

12

C133

C133 SCD1U16V

SCD1U16V

Title

Size Document Number Rev

A3

Date: Sheet

12

C131

C141

C141 SCD1U16V

SCD1U16V

C131 SCD1U16V

SCD1U16V

DDR2 Termination Resistor

12

C158

C145

SCD1U16V

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Myna2

12 47Monday, September 26, 2005

E

SB

of

SB

5V_S0

3D3V_S0

R525

R525 0R2J-GP

0R2J-GP

SB

DTC114EUA-U1

OUT

3

GND

1

1 2

1 2 1 2 1 2 1 2 1 2

WLAN_LED#

C19SC100P50V2JN-U C19SC100P50V2JN-U

C343SC100P50V2JN-U C343SC100P50V2JN-U

C338SC100P50V2JN-U C338SC100P50V2JN-U C337SC100P50V2JN-U C337SC100P50V2JN-U C342SC100P50V2JN-U C342SC100P50V2JN-U C339SC100P50V2JN-U C339SC100P50V2JN-U C336SC100P50V2JN-U C336SC100P50V2JN-U

DY

Q32

2

IN

2

IN

Q36

Q31DTC114EUA-U1

2

IN

2

IN

Q33

IN

Q34

MAIL_LED30

BLT_LED30

FRONT_PWRLED30

STDBY_LED30

DC_BATFULL30

CHARGE_LED30

R62

R62 10KR2

10KR2

1 2

80211_ACTIVE29

RF_ON/OFF#29,30

WLAN_TEST_LED30

MAIL_LED#

WLAN_LED#

DC_BATFULL# STDBY_LED# BLT_LED# CHARGE_LED# FRONT_PWRLED#

D

Q17

1

2N7002

G

S

2 3

D

Q16

1

2N7002

G

S

2 3

1 2

2

IN

12

DY

R74

0R2J-GP

Q21

R1

DY

R2

R12

1 2

DTC114EUA-U1

Q7

R1

R2

R193

1 2

R1

R2

DTC114EUA-U1

R187

1 2

R1

R2

R188

0R0402-PAD

1 2

R1

R2

DTC114EUA-U1

R189

0R0402-PAD

1 2

DTC114EUA-U1

R1

2

R2

R186

0R0402-PAD

1 2

R1

2

R2

DTC114EUA-U1

WLAN_LED#

0R0402-PAD

OUT

3

GND

1

0R0402-PAD

OUT

BLT_LED#

3

GND

1

0R0402-PAD

OUT

FRONT_PWRLED#

3

GND

1

OUT

STDBY_LED#

3

GND

1

OUT

3

GND

1

OUT

3

GND

1

MAIL_LED#

DC_BATFULL#

CHARGE_LED#

R205

1 2

150R2F

150R2F R14

R14

1 2

150R2F

R13

1 2

150R2F

R200

1 2

150R2F

R196

1 2

150R2F

R197

1 2

150R2F

R198

1 2

150R2F

R199

1 2

150R2F

SB

LED10 LED-O-7

12

83.00190.R70

LED2 LED-G-62-GP

12

83.00190.Q70

LED4 LED-G-62-GP

12

83.00190.Q70

LED1 LED-O-7

12

83.00190.R70

LED3 LED-O-7

12

83.00190.R70

LED9 LED-B-53

12

83.00190.Y70

LED5 LED-G-62-GP

12

83.00190.Q70

LED6 LED-O-7

12

83.00190.R70

LED7 LED-G-62-GP

12

83.00190.Q70

LED8 LED-O-7

12

83.00190.R70

SB_0817

5V_S5

2D5V_S0

LCDVDD

BRIGHTNESS30

EC_BL_ON30

C366 SC100P50V2JN-UC366 SC100P50V2JN-U

1 2

C365

1 2

12

C364

C364 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

DY

3D3V_S0

DCBATOUT

SC100P50V2JN-U

12

C22

C363

SCD1U25V3ZY-3GP

SC10U10V5ZY

DY

GMCH_TXACLK+7

GMCH_TXACLK-7

GMCH_TXAOUT2+7

GMCH_TXAOUT2-7

GMCH_TXAOUT1+7

GMCH_TXAOUT1-7

GMCH_TXAOUT0+7

GMCH_TXAOUT0-7

GMCH_TXBCLK+7

GMCH_TXBCLK-7

GMCH_TXBOUT2+7 GMCH_TXBOUT2-7

GMCH_TXBOUT1+7

GMCH_TXBOUT1-7

GMCH_TXBOUT0+7

GMCH_TXBOUT0-7

R533

0R2J-GP

DY

12

EDID_CLK EDID_DAT

-1

20.F0690.044

JAE-CON44-3-GP

45

1 2

3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

46

LCD1

47 MH1

48

49

50

51

52

53

54

MH2 55

SRN2K2J

1

G

1

Q8 2N7002-8-GP

CLK_DDC_EDID7

LCDVDD

U3

1

OUT

2

R15 1KR2R15 1KR2

GMCH_LCDVDD_ON7

1 2

LCDVDD_ON_1

12

C21

C21 SC1U10V3KX

SC1U10V3KX

GND ON/OFF#3IN

12

C17

C17 SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

AAT4280IGU-3-T1GP

GND

6

IN

5 4

3D3V_S0

12

C20

C20 SC1U10V3KX

SC1U10V3KX

DAT_DDC_EDID7

2 3

S

D

S

D

G

1

Q9 2N7002-8-GP

2 3

S

D

S

D

Title

Size Document Number Rev

Size Document Number Rev A3

A3

A3 Date: Sheet

Date: Sheet

4

RN9

LCD / LEDs

Myna2

3D3V_S0

23

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

EDID_CLK

EDID_DAT

13 47Monday, September 26, 2005

of

SB

L1

12

C11

SC3P50V2CN

14

1

TSAHCT125

7

L1

1 2

BLM18BA100SN1DGP

BLM18BA100SN1DGP L2

L2

1 2

BLM18BA100SN1DGP

BLM18BA100SN1DGP L3

L3

1 2

BLM18BA100SN1DGP

12

C12

C12 SCD1U16V

SCD1U16V

U1A

SC3D9P50V2CN-1GP

R217

0R2J-GP

1 2

R219

0R2J-GP

1 2

CRT_R

CRT_G

CRT_B

C1

12

C2

SC3D9P50V2CN-1GP

CRT_HSYNC1 34

CRT_VSYNC1 34

12

C4

SC3D9P50V2CN-1GP

SB_0817

JVGA_HS34 JVGA_VS34

-1

DAT_DDC1_5

L24 BLM18BB750SN1DL24 BLM18BB750SN1D

1 2

L25 BLM18BB750SN1DL25 BLM18BB750SN1D

1 2

CLK_DDC1_5

GMCH_DDCDATA7 DAT_DDC1_5 34

GMCH_DDCCLK7

5V_S0

12

D1

D1 RB751V-40-U

RB751V-40-U

1

23

RN8

RN8 SRN2K2J

SRN2K2J

4

12

C8

SC100P50V2JN-U

12

C3

SC100P50V2JN-U

12

C5

C5 SC33P50V2J

SC33P50V2J

12

CRT_R_SYS34

CRT_G_SYS34

CRT_B_SYS34

GMCH_HSYNC7

GMCH_VSYNC7

CRT_R_SYS

CRT_G_SYS

CRT_B_SYS

12

R1

150R2FR1150R2F

12

R2

150R2FR2150R2F

12

R3

150R2FR3150R2F

12

C9

SC3P50V2CN

DY

12

SC3P50V2CN

DY

14

4

5 6

7

C10

U1B

TSAHCT125

DY

5V_S0

2 3

1

23

4

C7

C7 SC33P50V2J

SC33P50V2J

DY

SB_0817

2D5V_S0

RN5

RN5 SRN2K2J

SRN2K2J

17

11

12 13 14 15 16

SYN-CONN15-U2

20.20326.015

G

1

2 3

S

Q5

Q5 2N7002

2N7002

CRT1

D

6 1

7 2 8 3 9 4 10 5

G

1

2 3

S

Q6

Q6 2N7002

2N7002

CRT_R

CRT_G

D

CRT_B

5V_CRT_S0

CLK_DDC1_5 34

C6

C6 SCD01U16V2KX

SCD01U16V2KX

DY

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

A3 Date: Sheet

Date: Sheet

CRT Connector

Myna2

of

14 47Monday, September 26, 2005

SB

A

B

C

D

E

DY

H_DPSLP#

1 2

1D05V_S0

R167

R167 10KR2

10KR2

12

1D05V_S0

12

R348

R348 56R2F

56R2F

R383

R383 56R2F

56R2F

R347

R347 75R2F

75R2F

NO_STUFF

3D3V_S0

H_FERR# 4

PM_THRMTRIP-I# 4,19

C506

SB

3D3V_AUX_S5

4 4

D11

21

CH751H-40-U

RTC_AUX_S5

12

C255

C255 SC1U10V3ZY

SC1U10V3ZY

4/28 RTC debug, change to 78.3R974.1F1.

RTC circuitry

D29

BAT_D

12

R434

R434 1KR2

1KR2

5

RTC1

RTC1 SCON3

3 3

2 2

SCON3

BAT

CH751H-40-U

BAT

123

4

21.D0010.103

C526 SCD01U16V2KXC526 SCD01U16V2KX

1 2

DY

R139 20KR2FR139 20KR2F

21

R138 1MR2R138 1MR2

RTC_AUX_S5

12

R137

R137 100KR2F-L1-GP

100KR2F-L1-GP

12

R134

R134 0R2J-GP

0R2J-GP

1 2 1 2

P.H. for internal VCCSUS1_5

INTVRMEN

C264

SCD1U16V

12

INTRUDER#19

ACZ_BITCLK28 ACZ_SYNC28

ACZ_RST#28

ACZ_SDATAOUT28

C506

XTAL-32D768K-4P

1 2

XTAL-32D768K-4P

SC4D7P50V2CN

2 3

C519

SC4D7P50V2CN

R497 0R3-U-GPR497 0R3-U-GP

1 2

R488 39R2JR488 39R2J

1 2

R489 39R2JR489 39R2J

1 2

ACZ_SDATAIN028 ACZ_SDATAIN128

R487 39R2JR487 39R2J

1 2

TP39TPAD28 TP39TPAD28

TP92TPAD28 TP92TPAD28 TP91TPAD28 TP91TPAD28

TP95TPAD28 TP95TPAD28 TP96TPAD28 TP96TPAD28

IDE_PDIORDY20 INT_IRQ1420 IDE_PDDACK#20 IDE_PDIOW#20 IDE_PDIOR#20

X4

41

12

R408

10MR3

RTC_RST# INTRUDER#

INTVRMEN

R490

1 2

10KR2

ACZ_SYNC_R ACZ_RST#_R

TP53 TPAD28TP53 TPAD28

ACZ_SDATAOUT_R

RCT_X1 RCT_X2

AC19

AD3 AG2

AD7 AC7

AG6 AC2

AC1

AG11

AF11

AF16 AB16 AB15 AC14 AE16

AA2 AA3

AA5

D12 B12 D11 F13

F12 B11 E12

E11 C13

C12 C11 E13

C10

A10 F11

F10 B10

AE3

AF2

AF6

Y1 Y2

B9

C9

RTCX1 RTCX2

RTCRST# INTRUDER#

INTVRMEN

EE_CS EE_SHCLK EE_DOUT EE_DIN

LAN_CLK LAN_RSTSYNC LANRXD[0]

LANRXD[1] LANRXD[2]

LANTXD[0] LANTXD[1] LANTXD[2]

ACZ_BIT_CLK ACZ_SYNC

ACZ_RST# ACZ_SDIN[0]

ACZ_SDIN[1] ACZ_SDIN[2]

ACZ_SDO

SATALED# SATA[0]RXN

SATA[0]RXP SATA[0]TXN SATA[0]TXP

SATA[2]RXN SATA[2]RXP SATA[2]TXN SATA[2]TXP

SATA_CLKN SATA_CLKP

SATARBIAS# SATARBIAS

IORDY IDEIRQ DDACK# DIOW# DIOR#

U44A

LAD[0]/FWH[0] LAD[1]/FWH[1] LAD[2]/FWH[2] LAD[3]/FWH[3]

LPC

RTCLAN

LDRQ[0]#

LDRQ[1]#/GPI[41]

LFRAME#/FWH[4]

A20GATE

CPUSLP# DPRSLP#

DPSLP#

CPU

CPUPWRGD/GPO[49]

IGNNE#

INIT3_3V#

STPCLK#

THRMTRIP#

SATA AC-97/AZALIA

IDE

DDREQ

A20M#

FERR#

INIT# INTR

RCIN#

NMI

SMI#

DA[0] DA[1] DA[2]

DCS1# DCS3#

DD[0] DD[1] DD[2] DD[3] DD[4] DD[5] DD[6] DD[7] DD[8]

DD[9] DD[10] DD[11] DD[12] DD[13] DD[14] DD[15]

P2 N3 N5 N4

N6 P4

P3

AF22 AF23

AE27 AE24

AD27 AF24 AG25 AG26

AE22 AF27 AG24

AD23 AF25

AG27 AE26 AE23

AC16 AB17 AC17

AD16 AE17

AD14 AF15 AF14 AD12 AE14 AC11 AD11 AB11 AE13 AF13 AB12 AB13 AC13 AE15 AG15 AD13

AB14

LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3

LPC_LDRQ1

H_CPUSLP#1 H_DPRSLP#1

H_FERR_R

H_THERMTRIP_R

IDE_PDD0 IDE_PDD1 IDE_PDD2 IDE_PDD3 IDE_PDD4 IDE_PDD5 IDE_PDD6 IDE_PDD7 IDE_PDD8 IDE_PDD9 IDE_PDD10 IDE_PDD11 IDE_PDD12 IDE_PDD13 IDE_PDD14 IDE_PDD15

LPC_LAD[0:3] 30,31,33

LPC_LDRQ#0 31

TP46 TPAD28TP46 TPAD28

LPC_LFRAME# 30,31,33

KA20GATE 30 H_A20M# 4

DY

R380 0R2J-GP

1 2

R355 0R2J-GPR355 0R2J-GP

1 2

H_DPSLP# 4

R354 56R2FR354 56R2F

1 2

H_PWRGD 4,19 H_IGNNE# 4

FWH_INIT# 33 H_INTR 4 KBRCIN# 30 H_NMI 4

H_SMI# 4 H_STPCLK# 4

R353

1 2

56R2F

IDE_PDA0 20 IDE_PDA1 20 IDE_PDA2 20

IDE_PDCS1# 20 IDE_PDCS3# 20

IDE_PDDREQ 20

LPC_LDRQ1

Open R253 for Dothan A step Shunt for Dothan B step & all Yonah

H_CPUSLP# 4,6 H_DPRSLP# 4

H_INIT# 4

Layout Note: R632 needs to placed within 2" of ICH6, R634 must be placed within 2" of R632 w/o stub.

IDE_PDD[15..0]20

1 1

A

B

C

D

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

A3 Date: Sheet

Date: Sheet

ICH6-M (1 of 4)

Myna2 SB

E

of

15 47Monday, September 26, 2005