Acer Nitro AN515-54 Schematic

A

1 1

B

C

D

E

C

2

ompal

E

H5

EH5VF/EH70F

M

B Schematic Document

Confidential

0F/EH51F

2

LA-H501P

3

R

ev

:1A

3

2019.02.22

4

S

c

ec

urity Classification

ec

e

I

ssued Date

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HI

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

2

01

7/10/30 2018/10/ 30

017/10/3 0 2018/10/ 30

7/10/30 2018/10/ 30

01

C

ompal Secret Data

Deciphered Date

Compal Electronics, Inc.

T

it

itle

le

itle

Cover Sheet

Size Document Number Re v

C

us

tom

EH5VF M/B LA-H501P

Date : Sheet

D

Date : Sheet

E

o

1 101Friday, February 22, 2019

f

4

1

A

H

1

DMI Conn.

p

age 40

H

DMI x 4 lanes

N

18P-G0 with gDDR5 x4

o

r

N17P-G0-K1 with gDDR5 x3

page 25~36

B

e

DP

p

age 38

e

DP

CoffeeLake H Processor BGA1440

P

EG x16

8GT/s

(42X28) (CFL-H_6+2)

P

ro

cessor

C

p

age 06~13

M

emory BUS

D

ual Channel

1

.2V DDR4 2400/2666

D

I

nterleaved Memory

F

an Control*2

2

60 pin DDR4-SO-DIMM X1

B

ANK 0, 1, 2, 3

2

60pin DDR4-SO-DIMM X1

B

ANK 4, 5, 6, 7

p

age 77

page 23

p

age 24

E

U

SB 3.0

1

conn x1

U

SB (port 1)

U

4

8MHz

D Audio

age 16

SB 3.0

c

onn x1

USB (port 3)

3

.3V 24MHz

2

3

N

GFF

W

LAN

U

SB port 7

R

TC CKT.

P

ower On/Off CKT.

p

age 52

P

CIE 1.0

2.5GT/s

p

ort 15

p

age 20

p

age 63

p

age 68

P

CIE 3.0 x4 8GT/s Port 9-12

p

age 51

PCIE 2.0 5GT/s

p

ort 14

L

AN(GbE)

R

ealtek 8118ASA

R

J45 conn.

p

age 32.

S

ub Board

H

S/B

I

O/B

F

lexible IO

S

P

S

ATA HDD Conn.

p

age 47

p

age 66

p

age 73

p

age 68

P

CIE 3.0 x4 8GT/s Port 21-24

p

age 67

S

ATA3.0

6

.0 Gb/s

p

ort 4

ATA Re-Driver

ARADE PS8527

T

ouch Pad Int.KBD

P

S2 / I2C

p

age 63

Cannonlake PCH - H FCBGA(25X24)

8

L

PC/eSPI BUS

C

=24MHz

LK

ENE K

B9022

p

age 58

X

4 DMI

74pin FCBGA

p

age 63

T

PM

p

age 14~21

age 66

USBx8

H

S

PI

S

PI ROM x1

p

U

SB 3.0

Type-C

U

SB (port 2)

p

age 72 page 38

I

C C

USB (port 5)

p

age 42,43

nt. Speaker

page 42

MOS amera

H

DA Codec

ALC255

I o

F

inger_Print

U

SB (port 8)

page 66

p

age 42

nt. DMIC

n Camera/B

p

age 48 page 48

U

AJ

o

n Sub/B

U

SB charger

S

LGC55544

p

2

age 71

3

DC/DC Interface CKT.

p

age 78

4

P

ower Circuit DC/DC

A

p

age 81~97

S

c

ec

urity Classification

ec

e

I

ssued Date

ued Date

ss

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HI

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

C

2

01

7/07/20 2018/07/20

017/07/20 2018/07/20

7/07/20 2018/07/20

01

C

ompal Secret Data

D

phered Date

eciphered Date

eci

C

om

pal Electronics, Inc.

ompal Electronics, Inc.

pal Electronics, Inc.

T

it

le

itle

S

Size Document Number Re v

ize Document Number Re v

C

us

tom

Date : Sheet

D

Date : Sheet

om

B

lo

lock Diagrams

E

H5V

F M/B LA-H501P

ck Diagrams

E

o

2 101Friday, February 22, 2019

f

4

1

A

B

C

D

E

Board ID Table for AD channel

Vcc 3 Ra

Board ID

0 1 2

1

3 4 5 6 7 8 9 1 1 1 13 14 15 16 17 18 19

2

I

2C Address Table

I2C_0 (+3VS) I

2C_1 (+3VS)

P

CH_SMBCLK

(+3VS)

PCH_SML1CLK EC_SMB_CK2

(+3VS)

EC_SMB_CK1 (+3VLP)

3

E

C_SMB_ CK3

(+3VALW)

.3V +/- 5%

100K +/- 1%

Rb V mi n

0 12K +/- 1% 0.347 V 0.345 V 0.360 V 1

5K +/- 1%

2

0K +/- 1%

2

7K +/- 1% 33K +/- 1% 43K +/- 1% 56K +/- 1% 7

5K +/- 1% 1

00K +/- 1% 130K +/- 1%

0 1

160K +/- 1%

2

200K +/- 1% 240K +/- 1% 270K +/- 1% 330K +/- 1% 430K +/- 1% 560K +/- 1% 750K +/- 1%

NC

B

US

TM-P3393-003 (Touch Pad) SA577C-12A0 (Touch Pad)

DIMM1 D

IMM2

N

18P-G0/N17P-G0-K1 (VGA)

Thermal Sensor (W83L771)

PCH 0x90

BQ24780 (Charger IC)

B

ATTERY PACK

LED driver 0xC0

BID

V ty p

BID

0.000 V

0

.423 V 0.430 V 0.438 V

1.398 V

1.634 V

1.849 V

2.015 V

2.185 V

2.316 V

2.395 V

2.521 V

2.667 V

2.791 V

2.905 V

3.000 V

D

evice

1.414 V

1.650 V

1.865 V

2.031 V

2.200 V

2.329 V

2.408 V

2.533 V

2.677 V

2.800 V

2.912 V

3.000 V

A

ddress(7 bit)

V

BID

0.300 V

1.430 V

1.667 V

1.881 V

2.046 V

2.215 V

2.343 V

2.421 V

2.544 V

2.687 V

2.808 V

2.919 V

W

rite Rea d

0x9E

1001_100xb 1001_1001b 1001_1000b

0x12 0

x16

max

Address( 8bit)

EC AD

0x00 - 0x13 0

x14 - 0x1E 0x1F - 0x25 0x26 - 0x300.541 V 0.550 V 0.559 V 0x31 - 0x3A0.691 V 0.702 V 0.713 V 0x3B - 0x450.807 V 0.819 V 0.831 V 0x46 - 0x540.978 V 0.992 V 1.006 V 0x55 - 0x641.169 V 1.185 V 1.200 V 0x65 - 0x76 0x77 - 0x87 0x88 - 0x96 0x97 - 0xA4 0xA5 - 0xAF 0xB0 - 0xB7 0xB8 - 0xBF 0xC0 - 0xC9 0xCA - 0xD4 0xD5 - 0xDD 0xDE - 0xF0 0xF1 - 0xFF

BOM Structure Table

BOM Option Table

Ite m BOM Structure

U

npop

C

onnector

C

MC CMC@

dGPU circuit VGA@

N

17P GPU N17P@

T

PM

F

or Acer IOAC

N

o Acer IOAC

K

B backlight

K

B LED driver OVRM-ON ON_X76@ OVRM-uPI

T

hermal sensor f

or SW debug board

I

ntel CNVi

F

inger Print

E

MI requirement

E

MI require reserve ESD requirement E

SD require reserve F

P ESD requirement FPESD@ P

idgey ESD requirementPGESD@ S

ATA HDD W REDRIVER S

ATA HDD WO REDRIVER

i

5 CPU i7 CPU H

62 CPU H62@

H

82 CPU

L

AN LDO mode

L

AN Switch mode

@

C

ONN@

N

18P@N18P GPU

T

PM@

I

OAC@

N

IOAC@

K

BLED@

L

ED14P@

u

PI_X76@

T

MS@

UART@ C

NVI@

F

P@

P

BA@FinerPrint(with PBA)

E

MI@

X

EMI@

E

SD@

X

ESD@

S

ATARD @

S

ATANRD@

i

5@

i

7@

H

82@

L

DO@

S

WR@

Power State

STATE

S0 (Full ON) ON ON ON ONHIGH HIGH HIGH

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

V

oltage Rails

P

ower Plane

+

RTCVCC

+

19V_VIN

+12.6V_B ATT Battery power supply

+

19VB

+

VLP

3

+5VALW

+3VALW System +3VALW always on power rail

+

3VALW_DSW +3VALW power for PCH DSW rails

+

1.05VALW +1.05V Always power rail

+

1.05V_VCCST

+5VS System +5V power rail

+

3VS

+

05VS_VCCSTG +1.05VALW_PRIM Gated version of VCCST

1.

+

0.6VS_VT T DDR +0.6VS power rail for DDR terminator .

+V

CC_CORE

+

VCC_GT

+VCCIO

+

VC

C_SA

+

1.8VSDGPU_AON

+

NVVDD1

+1.35VSDGPU +1.35VS power rail for GPU

+

1.0VSDGPU

+

1.8VALW System +1.8VALW always on power rail

SIGNA L

SLP_S3 # SLP_S4 # S LP_S5# +VALW +V +VS Clock

LOW HIGH

D

escription

RTC Battery Power

Adapter power supply

AC or battery power rail for power circuit.

+

19VB to +3VLP power rail for suspend power

+5V Always power rail

D

DR4 +1.2V power rail+1.2V_VDDQ

Sustain voltage for processor in Standby modes

S

ystem +3V power rail

Core voltage for CPU

S

liced graphics power r ail

CPU IO +0.95VS power r ail

S

ystem Agent power rail

+

1.

8VS power rail for GPU(AON rails)

+

1.

8VS power rail for GPU GC6+1.8VSDGPU_MAIN

C

ore voltage for VGA (mer ge core & core_s)

+

1.0VS power rail for GPU

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

HIGH

LOWLOW

HIGH

ONONON

ON

OFF

OFFLOW LOW LOW

OFF

S

0

3

O

N

ON

N

/A N/A N/A

N

/A

N/A

N

/A

N/A

ON

O

N

ON

O

ON

N

ON

O

N

N O

O

N

O

FF

O

N

OFF OFF

O

FF

O

N

ON

OFF

O

FF

O

N

O

FF

O

N

OFF OFF OFF

ON

O

N

OFF

O

N

OFF

O

N

O

FF

O

N

OFF OFF OFF

ON

OFF OFF OFF

ON

ONON

S4

S5

ON ON

N

N/A N/A

ON ON

ON*

O

N

ON ON

ON

O

FF

O

FF

O

FF

O

OFF

OFF OFF

OFF

O

FF

OFF

O

FF

O

FF

OFF

OFFOFF

O

FF

OFF OFF

OFF

ON*

O

N

1

/AN/AN/A

FF

2

3

4

3

level BOM table

4

31AC5BO L01

4

B

OM Structure43 Level De scripti on

S

MT MB AF952 DH53F I5PG1 4G 28P 8L HDMI 255@/CHG@/CMC @/CNVI@/FP@/G 0@/I5@/IOAC@ /LDO@/SAT ARD@/ TYPEC @/V1 5@/VG A@/X 76@

S

c

ec

urity Classification

ec

e

I

ssued Date

ued Date

ss

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HI

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

C

Board ID

0 1 2 3 4 5 6 7 8 9

C

ompal Secret Data

2

01

7/10/30 2018/10/30

017/10/30 2018/10/30

7/10/30 2018/10/30

01

ompal Secret Data

D

phered Date

eciphered Date

eci

D

B

OARD ID Table

PCB Revision

2

050 Rev0.1

2

050 Rev0.2 2050 Rev0.3 2050 Rev1.0/1A 2060 Rev0.1 2060 Rev0.2 2060 Rev0.3 2060 Rev1.0

T

S

Size Document Number Re v

C

us

Date : Sheet

Board ID

1

0 11 12 13 1

4 15 16 17 18 1

9

Compal Electronics, Inc.

it

le

itle

N

ot

es List

otes List

ize Document Number Re v

tom

EH5VF M/B LA-H501P

E

P

CB Revision

o

3 101Friday, February 22, 2019

4

1

A

f

5

DC_

IN

P

UB1

C

HARGER

PL101,2,3

+19V_V IN

+12.6V _BATT

+

19VB

+

19VB

+

19VB

+19VB

+

19VB

P

L201,2

IMVP8

P

UZ2,3,4,5

E

N:DRV ON

P

RG5

E

N:DRV ON

P

RA3

E

N:DRV ON

EN:3V_ EN

P

U301

EN:SYS ON

P

UM1

+12.6V_BATT+

+

19VB_C PU

P

+19VB_C PU

+

3V

ALWP

+

1.2VP

E

N:SM_P G_CTR L

+0.6VSP

P

JP201

LZ1,2,3,4

P

LG1

P

LA1

P

J30 2

P

JM2

P

JM3

PJP101

AC CONN.

D D

C

B

ATTERY

+

VCC_C ORE

+

VCC_ GT

+VCC_ SA

+

3VAL W

E

C,LID

+

3VLP

C

PU,Memory

+1.2V_ VDDQ

+

0.6VS _VTT

4

CPU

C

PU

C

PU

+

1.2V_V CCPLL _OC

R

C24

CPU

3

+2.5V P

PU2501 PJ2502

+

1.0VS DGPUP

P

U1002 PJ1003

U

Q1

R19

UM1

U

L1

UK1

UM2

U

M2

RH101

RH99

U

K2

J

PH1

R

H94

J

PQ1

+

3VALW _TPM

+3VS_W LAN

+

3V_L AN

+3V_P TP

R

M54

R

M55

+3VALW _HDA

+3VALW _DSW

+

FP_V CC

+2.5V

+

1.0VS DGPU

+

3VS

+

3VS_S SD1

+

3VS_S SD2

+

1.05VA LW_PR IM

+

1.05VA LW_PC H

R

H102

R

H103

R

H105

G

PU

U

5

TPM

J

NGFF1

WLAN CARD Conn.

UL2

LAN

JTP1

TP Conn.

J

SSD1

S

SD Conn.

JSSD2

SSD Conn.

PCH

J

FP1

F

P Conn.

PCH

+

1.05VAL W_VCC AZPLL

+1.05VAL W_VCC AMPHYP LL

+1.05VA LW_XT AL

JDIMM1

J

DIMM2

PCH

2

DDR4 Conn.

UO1

UV45

R

R20

U

R

1

+

3VS

+

3VSDG PU

M11

X1

A2

A4

+3VS_W LAN

+

3VS_T PM

+

LCDV DD

+

3VS_D VDDIO

+

3VS_D VDD

SATA Re-driver

G

PU

J

NGFF1

W

LAN CARD Conn.

U

5

TPM

J

EDP1

PANEL

C

ODEC

C

ODEC

C

+1.05VAL WP

P

+

19VB

+

19VB

B

+

19VB

+

19VB

+

19VB

+

A

19VB

+19VB

5

U1101

E

N:+1. 8_PG

P

UH1 PJH1

E

N:SUS P#

PU1801 PJ1801

EN:SPO K_3V

PU501

PUV1

E

N:1.35V SDGPU _EN

P

UW1

→ +

19VB_CPU

+1.0VS_V CCIOP

+

8VALWP

1.

+5VALWP

NVVDD_B +

P

G

_B+

PU

P

J110 1

PJ502

UV2,3

P

LW1

L

X1

+1.05V ALW

+

VCCI O

+

1.8VA LW

+

P

G

PU

+

1.35V SDGPU

+

INVPW R_B+

C

5VAL W

LV

2,3

4

E

N:DGPU _PWR_ EN

U

G27

U

Q2

R

H100

+1.8VSD GPU_A ON

+

1.8VSD GPU_M AIN

R

Q

9

+1.8VALW _PRIM

R

S127

J

IO1

U

S11

U

S12

U

S13

U

E5

UK2

+

.8VS

1

P

PU

G

PU

+

NVVD D1

P

ANEL

CH

J

UV48

G

PU

R

+

5VALW _MUX

+

5VAL W

+

USB3_ VCCC

+

USB_V CCA

+

USB_V CCB

+

5V_LE DPWR

+

FP_V CC

PQ2UQ1

UQ2

U

C4

+

FP_FUS E_GPU

+

1.8VS _VDDA

A3

U

J

JUSB1

J

+

5VS

3

R

Q5

S3

IO1

TYPEC1

USB2

BL2

FP1

+

1.05V_ VCCST

+

1.05VS _VCCS TG

G

PU

C

ODEC

CC logic/U3 MUX

I

O/B Conn.

T

ype-C Conn.

U

SB3.0 Conn.

U

SB3.0 Conn.

K

B BackLight Conn.

F

P Conn.

CPU

R

JPA1

U4

RO4

UY2

R

B

+

F4

F7

X7

VCC_F AN1

+

VCC_F AN2

+

VDDA

+

5VS_ BL

+

5VS_H DD

+

HDMI_5 V_OUT

+

TS_P WR

S

c

ec

urity Classification

ec

e

I

ssue

T

S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HI

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY O F THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY O F THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WR ITTEN CONSENT O F CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WR ITTEN CONSENT O F CO MPAL ELECTRONICS, INC.

2

JFAN1

FAN1 Conn.

JFAN1

FAN2 Conn.

U

A1

CODEC

J

BL1

K

JHDD1

H

J

HDMI1

HDMI Conn.

J

EDP1

T

2

01

7/10/30 2018/10/30

017/10/30 2018/10/3 0

7/10/30 2018/10/30

d Date

01

B BackLight Conn.

DD Conn.

ouch Screen

C

m

om

pal Secret Data

om

o

D

iphered Date

ec

Compal Electronics, Inc.

T

it

le

itle

P

ow

er Map

ower Map

S

Size Document Number Re v

ize Document Number Re v

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us

tom

ustom

EH5VF M/B LA-H501P

Date: Sheet

1

o

f

4 101Friday, February 22, 2019

A

1

A

BIOS ver: V0.02W1 EC: ver: V002AT04

A

C modeDH5VF_EVT Power Sequence

B

C

D

E

1

S

P

7

2.1us

2

75.9us

692.9us

910.1us

12.7ms

→

ower On

8.378us

8

77.7us

630.4us

4

12us

25.34ms

2

5.35ms

25.36ms

25.19ms

→

1.759ms

173.0ms

NA

12.42ms

150.3ms

1

52.3ms 318.7us

→

13.01us

→

26.91us

→

P

lug in

+

3VLP

E

C_ON

+

5VALW

O

N/OFFBTN #

+

3VALW

+

1.05VAL W

EC_RSMRS T#

PBTN_OUT #

P

M_SLP_S4 #

P

M_SLP_S3 #

S

2 2

3

YSON

+1.05V_V CCST

+1.2V_VD DQ

+2.5VS

SUSP#

+1.05VS_ VCCSTG

+

5VS

+

3V

S

+1.8VS

E

C_VCCST_ PG

SM_PG_CT RL

+0.6VS_V TT

V

R_ON

+VCC_S A

+

VCC_COR E

+VCC_G T

PCH_PWRO K

S

YS_PWRO K

P

LT_RST #

→

3

30.8ms

3

33.3ms

→

92.03ms

→

94.88ms

2.439ms

→

1

74.6ms

2

9.19ms

2

0.1ms

←

→

1

9.18ms

1

9.22ms

→

→ →

→

3 S3 Resume

55.47us

→

618.5us

8.679ms

3

47.6us

0

us

0us 13.97ms

3.819ms

51.25us

87.75us

NA

47.39us

61.95us

67.04ms

→

8

.502us

906.0us

6

56.1us

424.9us

25.25ms

25.26ms

25.59ms

→

1.757ms

12.18ms

167.1ms

150.6ms

1

51.8ms

NA

P

ower Off

100.5us

152.8us

→

88.37us

→

367.6us

→

2.266ms

→

13us

→

68.53us

→

686.0us

→

11.65ms

→

446.2us

0us

→

2.034ms

→

27.06us

→

48.00us

→

112.0us

→

NA

47.83us

→

62.37us

→

293.7us

+3VLP

EC_ON

+5VALW

O

N/OFFBTN #

+3VALW

+

1.05VAL W

EC_RSMRS T#

PBTN_OUT #

P

M_SLP_S4 #

P

M_SLP_S3 #

S

YSON

+1.05V_V CCST

+1.2V_VD DQ

+2.5VS

SUSP#

+1.05VS_ VCCSTG

+5VS

+

3VS

+1.8VS

EC_VCCST _PG

SM_PG_CT RL

+0.6VS_V TT

V

R_ON

+VCC_S A

+

VCC_COR E

+VCC_G T

PCH_PWRO K

S

YS_PWRO K

PLT_RST #

1

3

4

S

c

ec

urity Classification

ec

e

I

ssued Date

ued Date

ss

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPE RTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPE RTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HI

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUS TODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUS TODY OF THE C OMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHE R THIS SHEET NOR THE INFORM ATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHE R THIS SHEET NOR THE INFORM ATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHE R THIS SHEET NOR THE INFORM ATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS , INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS , INC.

A

B

C

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS , INC.

2

01

017/10/30 2018/10/30

01

C

m

om

ompal Secret Data

pal Secret Data

D

o

Deciphered Date

7/10/30 2018/10/30

Compal Electronics, Inc.

T

it

le

itle

T

itle

Power Sequence

S

ize

S

ize

D

ocument Number Re v

D

ocument Number Re v

C

us

tom

EH5VF M/B LA-H501P

Date : Sheet

E

5 101Friday, February 22, 2019

4

1

A

o

f

A

B

C

D

E

ZZZ

PCB10@

PCB EH5VF LA-H501P LS-H 501P/H502P

DAZ2K700100

1 1

Coffee Lake-H CPU SKU

UC1

I5@

S IC CL8068 403373522 SR3Z0 U0 2.3 G ABO!

SA0000BPJ40

UC1

I7@

S IC CL8068 403359524 SR3YY U0 2.2G ABO!

SA0000BPZ40

UC1

I5QS@

S IC CL8068 403373522 QP89 U0 2.3 G BGA

2 2

SA0000BPJ10

Cannon Lake PCH SKU

UH1

PCH@

S IC FH82HM370 SR40B B0 BG A 874P PCH-H ABO!

SA0000BVP10

UH1

3 3

PCHQS@

S IC FHHM370 QNYF B0 BGA 874 P PCH-H

SA0000BPF10

NV GPU SKU

UV1

N17P@

S IC N17P-G0-K 1-A1 FCBGA 9 08P GPU ABO !

SA0000CFM20

UV1

N18PQS@

S IC N18P-G0-A 1 QS FCBGA 9 60P GPU AB O !

SA0000CK210

UV1

4 4

N18PMP@

S IC N18P-G0-MP-A 1 FCBGA 960 P GPU ABO !

SA0000CK230

ZZZ1

PCB1A@

PCB EH5VF LA-H501P LS-H 501P/H502P

DAZ2K700101

UC1

I5RQS@

S IC CL8068 404121905 QRR5 U0 2.4G FCBGA

SA0000COG00

UC1

I7RQS@

S IC CL8068 404121817 QRR2 U0 2.6G FCBGA 1440

SA0000COF10

K36 K37

J35

J34 H37 H36

J37

J38

D27 E27

H34 H33 F37

G38

F34 F35 E37 E36

F26 E26

C34 D34 B36 B34 F33 E33 C33 B33

A27 B27

UC1D

DDI1_TXP_0 DDI1_TXN_0 DDI1_TXP_1 DDI1_TXN_1 DDI1_TXP_2 DDI1_TXN_2 DDI1_TXP_3 DDI1_TXN_3

DDI1_AUXP DDI1_AUXN

DDI2_TXP_0 DDI2_TXN_0 DDI2_TXP_1 DDI2_TXN_1 DDI2_TXP_2 DDI2_TXN_2 DDI2_TXP_3 DDI2_TXN_3

DDI2_AUXP DDI2_AUXN

DDI3_TXP_0 DDI3_TXN_0 DDI3_TXP_1 DDI3_TXN_1 DDI3_TXP_2 DDI3_TXN_2 DDI3_TXP_3 DDI3_TXN_3

DDI3_AUXP DDI3_AUXN

CFL-H_BG A1440

@

CFL-H

EDP_TXP_0 EDP_TXN_0 EDP_TXP_1 EDP_TXN_1 EDP_TXP_2 EDP_TXN_2 EDP_TXP_3 EDP_TXN_3

EDP_AUXP EDP_AUXN

EDP_DISP_UTIL

DISP_RCOMP

PROC_AUDIO_CLK

PROC_AUDIO_SDI

PROC_AUDIO_SDO

4 of 13

D29 E29 F28 E28 A29 B29 C28 B28

C26 B26

A33

D37

G27 G25 G29

EDP_TXP 0 EDP_TXN 0 EDP_TXP 1 EDP_TXN 1 EDP_TXP 2 EDP_TXN 2 EDP_TXP 3 EDP_TXN 3

EDP_AUX P EDP_AUX N

DP_RCOM P

Trace Width/Space: 15 mil/ 20 mil Max Trace Length: 600 mil

CPU_DISPA _SDI

RC1 24.9_04 02_1%

RC2 20_040 2_5%

1 2

follow CRB

12

EDP_TXP 0 <38> EDP_TXN 0 <38 > EDP_TXP 1 <38> EDP_TXN 1 <38 > EDP_TXP 2 <38> EDP_TXN 2 <38 > EDP_TXP 3 <38> EDP_TXN 3 <38 >

EDP_AUX P < 38> EDP_AUX N <38>

+VCCIO

CPU_DISPA _BCLK_R CPU_DISPA _SDO_R CPU_DISPA _SDI_R

eDP

CPU_DISPA _BCLK_R <18> CPU_DISPA _SDO_R <18>

CPU_DISPA _SDI_R <18>

Security Classification

2017/10/ 30 2018/10 /30

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

2017/10/ 30 2018/10 /30

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

CFL-H(1/8)DDI/eDP

Size Document Number Re v

Custom

EH5VF M/B LA-H501P

Date : Sheet o f

D

Date : Sheet o f

6 101Friday, February 22, 2019

E

1A

A

B

C

D

E

CH

Interleaved Memory

1 1

2 2

3 3

DDR_A_D [0..63]<23>

For ECC DIMM

DDR_A_D 0 DDR_A_D 1 DDR_A_D 2 DDR_A_D 3 DDR_A_D 4 DDR_A_D 5 DDR_A_D 6 DDR_A_D 7 DDR_A_D 8 DDR_A_D 9 DDR_A_D 10 DDR_A_D 11 DDR_A_D 12 DDR_A_D 13 DDR_A_D 14 DDR_A_D 15 DDR_A_D 16 DDR_A_D 17 DDR_A_D 18 DDR_A_D 19 DDR_A_D 20 DDR_A_D 21 DDR_A_D 22 DDR_A_D 23 DDR_A_D 24 DDR_A_D 25 DDR_A_D 26 DDR_A_D 27 DDR_A_D 28 DDR_A_D 29 DDR_A_D 30 DDR_A_D 31 DDR_A_D 32 DDR_A_D 33 DDR_A_D 34 DDR_A_D 35 DDR_A_D 36 DDR_A_D 37 DDR_A_D 38 DDR_A_D 39 DDR_A_D 40 DDR_A_D 41 DDR_A_D 42 DDR_A_D 43 DDR_A_D 44 DDR_A_D 45 DDR_A_D 46 DDR_A_D 47 DDR_A_D 48 DDR_A_D 49 DDR_A_D 50 DDR_A_D 51 DDR_A_D 52 DDR_A_D 53 DDR_A_D 54 DDR_A_D 55 DDR_A_D 56 DDR_A_D 57 DDR_A_D 58 DDR_A_D 59 DDR_A_D 60 DDR_A_D 61 DDR_A_D 62 DDR_A_D 63

ANNEL-A

UC1A

DDR4(IL)/LP3-DDR4(NIL) LP3/D DR4

BR6

DDR0_DQ_0/DDR0_DQ_0

BT6

DDR0_DQ_1/DDR0_DQ_1

BP3

DDR0_DQ_2/DDR0_DQ_2

BR3

DDR0_DQ_3/DDR0_DQ_3

BN5

DDR0_DQ_4/DDR0_DQ_4

BP6

DDR0_DQ_5/DDR0_DQ_5

BP2

DDR0_DQ_6/DDR0_DQ_6

BN3

DDR0_DQ_7/DDR0_DQ_7

BL4

DDR0_DQ_8/DDR0_DQ_8

BL5

DDR0_DQ_9/DDR0_DQ_9

BL2

DDR0_DQ_10/DDR0_DQ_10

BM1

DDR0_DQ_11/DDR0_DQ_11

BK4

DDR0_DQ_12/DDR0_DQ_12

BK5

DDR0_DQ_13/DDR0_DQ_13

BK1

DDR0_DQ_14/DDR0_DQ_14

BK2

DDR0_DQ_15/DDR0_DQ_15

BG4

DDR0_DQ_16/DDR0_DQ_32

BG5

DDR0_DQ_17/DDR0_DQ_33

BF4

DDR0_DQ_18/DDR0_DQ_34

BF5

DDR0_DQ_19/DDR0_DQ_35

BG2

DDR0_DQ_20/DDR0_DQ_36

BG1

DDR0_DQ_21/DDR0_DQ_37

BF1

DDR0_DQ_22/DDR0_DQ_38

BF2

DDR0_DQ_23/DDR0_DQ_39

BD2

DDR0_DQ_24/DDR0_DQ_40

BD1

DDR0_DQ_25/DDR0_DQ_41

BC4

DDR0_DQ_26/DDR0_DQ_42

BC5

DDR0_DQ_27/DDR0_DQ_43

BD5

DDR0_DQ_28/DDR0_DQ_44

BD4

DDR0_DQ_29/DDR0_DQ_45

BC1

DDR0_DQ_30/DDR0_DQ_46

BC2

DDR0_DQ_31/DDR0_DQ_47

AB1

DDR0_DQ_32/DDR1_DQ_0

AB2

DDR0_DQ_33/DDR1_DQ_1

AA4

DDR0_DQ_34/DDR1_DQ_2

AA5

DDR0_DQ_35/DDR1_DQ_3

AB5

DDR0_DQ_36/DDR1_DQ_4

AB4

DDR0_DQ_37/DDR1_DQ_5

AA2

DDR0_DQ_38/DDR1_DQ_6

AA1

DDR0_DQ_39/DDR1_DQ_7

V5

DDR0_DQ_40/DDR1_DQ_8

V2

DDR0_DQ_41/DDR1_DQ_9

U1

DDR0_DQ_42/DDR1_DQ_10

U2

DDR0_DQ_43/DDR1_DQ_11

V1

DDR0_DQ_44/DDR1_DQ_12

V4

DDR0_DQ_45/DDR1_DQ_13

U5

DDR0_DQ_46/DDR1_DQ_14

U4

DDR0_DQ_47/DDR1_DQ_15

R2

DDR0_DQ_48/DDR1_DQ_32

P5

DDR0_DQ_49/DDR1_DQ_33

R4

DDR0_DQ_50/DDR1_DQ_34

P4

DDR0_DQ_51/DDR1_DQ_35

R5

DDR0_DQ_52/DDR1_DQ_36

P2

DDR0_DQ_53/DDR1_DQ_37

R1

DDR0_DQ_54/DDR1_DQ_38

P1

DDR0_DQ_55/DDR1_DQ_39

M4

DDR0_DQ_56/DDR1_DQ_40

M1

DDR0_DQ_57/DDR1_DQ_41

L4

DDR0_DQ_58/DDR1_DQ_42

L2

DDR0_DQ_59/DDR1_DQ_43

M5

DDR0_DQ_60/DDR1_DQ_44

M2

DDR0_DQ_61/DDR1_DQ_45

L5

DDR0_DQ_62/DDR1_DQ_46

L1

DDR0_DQ_63/DDR1_DQ_47

LP3/DDR4

BA2

NC/DDR0_ECC_0

BA1

NC/DDR0_ECC_1

AY4

NC/DDR0_ECC_2

AY5

NC/DDR0_ECC_3

BA5

NC/DDR0_ECC_4

BA4

NC/DDR0_ECC_5

AY1

NC/DDR0_ECC_6

AY2

NC/DDR0_ECC_7

CFL-H_BG A1440

@

CFL-H

DDR CHANNEL A

DDR0_CKP_0/DDR0_CKP_0 DDR0_CKN_0/DDR0_CKN_0 DDR0_CKP_1/DDR0_CKP_1 DDR0_CKN_1/DDR0_CKN_1

DDR0_CKE_0/DDR0_CKE_0 DDR0_CKE_1/DDR0_CKE_1 DDR0_CKE_2/DDR0_CKE_2 DDR0_CKE_3/DDR0_CKE_3

DDR0_CS#_0/DDR0_CS#_0 DDR0_CS#_1/DDR0_CS#_1

DDR0_ODT_0/DDR0_ODT_0

DDR0_CAB_4/DDR0_BA_0 DDR0_CAB_6/DDR0_BA_1 DDR0_CAA_5/DDR0_BG_0

DDR0_CAB_3/DDR0_MA_16 DDR0_CAB_2/DDR0_MA_14 DDR0_CAB_1/DDR0_MA_15

DDR0_CAB_9/DDR0_MA_0 DDR0_CAB_8/DDR0_MA_1 DDR0_CAB_5/DDR0_MA_2

DDR0_CAA_0/DDR0_MA_5 DDR0_CAA_2/DDR0_MA_6 DDR0_CAA_4/DDR0_MA_7 DDR0_CAA_3/DDR0_MA_8

DDR0_CAA_1/DDR0_MA_9 DDR0_CAB_7/DDR0_MA_10 DDR0_CAA_7/DDR0_MA_11 DDR0_CAA_6/DDR0_MA_12 DDR0_CAB_0/DDR0_MA_13

DDR0_CAA_9/DDR0_BG_1

DDR0_CAA_8/DDR0_ACT#

DDR0_DQSN_0/DDR0_DQSN_0 DDR0_DQSN_1/DDR0_DQSN_1 DDR0_DQSN_2/DDR0_DQSN_4 DDR0_DQSN_3/DDR0_DQSN_5 DDR0_DQSN_4/DDR1_DQSN_0 DDR0_DQSN_5/DDR1_DQSN_1 DDR0_DQSN_6/DDR1_DQSN_4 DDR0_DQSN_7/DDR1_DQSN_5

DDR0_DQSP_0/DDR0_DQSP_0 DDR0_DQSP_1/DDR0_DQSP_1 DDR0_DQSP_2/DDR0_DQSP_4 DDR0_DQSP_3/DDR0_DQSP_5 DDR0_DQSP_4/DDR1_DQSP_0 DDR0_DQSP_5/DDR1_DQSP_1 DDR0_DQSP_6/DDR1_DQSP_4 DDR0_DQSP_7/DDR1_DQSP_5

DDR0_DQSP_8/DDR0_DQSP_8 DDR0_DQSN_8/DDR0_DQSN_8

1 OF 13

NC/DDR0_CKP_2 NC/DDR0_CKN_2 NC/DDR0_CKP_3 NC/DDR0_CKN_3

NC/DDR0_CS#_2 NC/DDR0_CS#_3

NC/DDR0_ODT_1 NC/DDR0_ODT_2 NC/DDR0_ODT_3

NC/DDR0_MA_3 NC/DDR0_MA_4

NC/DDR0_PAR

NC/DDR0_ALERT#

DDR4(IL)/LP3-DDR4(NIL)

AG1 AG2 AK2 AK1 AL3 AK3 AL2 AL1

AT1 AT2 AT3 AT5

AD5 AE2 AD2 AE5

AD3 AE4 AE1 AD4

AH5 AH1 AU1

AH4 AG4 AD1

AH3 AP4 AN4 AP5 AP2 AP1 AP3 AN1 AN3 AT4 AH2 AN2 AU4 AE3 AU2 AU3

AG3 AU5

BR5 BL3 BG3 BD3 AA3 U3 P3 L3

BP5 BK3 BF3 BC3 AB3 V3 R3 M3

AY3 BA3

DDR_A_C LK0 DDR_A_C LK#0 DDR_A_C LK1 DDR_A_C LK#1

DDR_A_C KE0 DDR_A_C KE1

DDR_A_C S#0 DDR_A_C S#1

DDR_A_O DT0 DDR_A_O DT1

DDR_A_B A0 DDR_A_B A1 DDR_A_B G0

DDR_A_M A16_RAS# DDR_A_M A14_WE# DDR_A_M A15_CAS#

DDR_A_M A0 DDR_A_M A1 DDR_A_M A2 DDR_A_M A3 DDR_A_M A4 DDR_A_M A5 DDR_A_M A6 DDR_A_M A7 DDR_A_M A8 DDR_A_M A9 DDR_A_M A10 DDR_A_M A11 DDR_A_M A12 DDR_A_M A13 DDR_A_B G1 DDR_A_A CT#

DDR_A_P AR DDR_A_A LERT#

DDR_A_D QS#0 DDR_A_D QS#1 DDR_A_D QS#2 DDR_A_D QS#3 DDR_A_D QS#4 DDR_A_D QS#5 DDR_A_D QS#6 DDR_A_D QS#7

DDR_A_D QS0 DDR_A_D QS1 DDR_A_D QS2 DDR_A_D QS3 DDR_A_D QS4 DDR_A_D QS5 DDR_A_D QS6 DDR_A_D QS7

DDR_A_C LK0 <23> DDR_A_C LK#0 <23> DDR_A_C LK1 <23> DDR_A_C LK#1 <23>

DDR_A_C KE0 <23> DDR_A_C KE1 <23>

DDR_A_C S#0 <23> DDR_A_C S#1 <23>

DDR_A_O DT0 <23> DDR_A_O DT1 <23>

DDR_A_B A0 < 23> DDR_A_B A1 < 23> DDR_A_B G0 < 23>

DDR_A_M A16_RAS# <23> DDR_A_M A14_WE# <23> DDR_A_M A15_CAS# <23>

DDR_A_M A0 <23> DDR_A_M A1 <23> DDR_A_M A2 <23> DDR_A_M A3 <23> DDR_A_M A4 <23> DDR_A_M A5 <23> DDR_A_M A6 <23> DDR_A_M A7 <23> DDR_A_M A8 <23> DDR_A_M A9 <23> DDR_A_M A10 <23 > DDR_A_M A11 <23 > DDR_A_M A12 <23 > DDR_A_M A13 <23 > DDR_A_B G1 < 23> DDR_A_A CT# <23>

DDR_A_P AR <23> DDR_A_A LERT# <23>

DDR_A_D QS#0 <23> DDR_A_D QS#1 <23> DDR_A_D QS#2 <23> DDR_A_D QS#3 <23> DDR_A_D QS#4 <23> DDR_A_D QS#5 <23> DDR_A_D QS#6 <23> DDR_A_D QS#7 <23>

DDR_A_D QS0 <23> DDR_A_D QS1 <23> DDR_A_D QS2 <23> DDR_A_D QS3 <23> DDR_A_D QS4 <23> DDR_A_D QS5 <23> DDR_A_D QS6 <23> DDR_A_D QS7 <23>

For ECC DIMM

4 4

Security Classification

2017/10/ 30 2018/10 /30

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

2017/10/ 30 2018/10 /30

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

CFL-H(2/8)DIMMA

Size Document Number Re v

Custom

EH5VF M/B LA-H501P

Date : Sheet o f

D

Date : Sheet o f

7 101Friday, February 22, 2019

E

1A

A

B

C

D

E

CHANNEL-B

terleaved Memory

In

1 1

2 2

3 3

DDR_B_D [0..63]<24>

For ECC DIMM

DDR_B_D 0 DDR_B_D 1 DDR_B_D 2 DDR_B_D 3 DDR_B_D 4 DDR_B_D 5 DDR_B_D 6 DDR_B_D 7 DDR_B_D 8 DDR_B_D 9 DDR_B_D 10 DDR_B_D 11 DDR_B_D 12 DDR_B_D 13 DDR_B_D 14 DDR_B_D 15 DDR_B_D 16 DDR_B_D 17 DDR_B_D 18 DDR_B_D 19 DDR_B_D 20 DDR_B_D 21 DDR_B_D 22 DDR_B_D 23 DDR_B_D 24 DDR_B_D 25 DDR_B_D 26 DDR_B_D 27 DDR_B_D 28 DDR_B_D 29 DDR_B_D 30 DDR_B_D 31 DDR_B_D 32 DDR_B_D 33 DDR_B_D 34 DDR_B_D 35 DDR_B_D 36 DDR_B_D 37 DDR_B_D 38 DDR_B_D 39

DDR_B_D 40 DDR_B_D 41 DDR_B_D 42 DDR_B_D 43 DDR_B_D 44 DDR_B_D 45 DDR_B_D 46 DDR_B_D 47 DDR_B_D 48 DDR_B_D 49 DDR_B_D 50 DDR_B_D 51 DDR_B_D 52 DDR_B_D 53 DDR_B_D 54 DDR_B_D 55 DDR_B_D 56 DDR_B_D 57 DDR_B_D 58 DDR_B_D 59 DDR_B_D 60 DDR_B_D 61 DDR_B_D 62 DDR_B_D 63

UC1B

DDR4(IL)/LP3-DDR4(NIL)

BT11

DDR1_DQ_0/DDR0_DQ_16

BR11

DDR1_DQ_1/DDR0_DQ_17

BT9

DDR1_DQ_2/DDR0_DQ_18

BR8

DDR1_DQ_3/DDR0_DQ_19

BP11

DDR1_DQ_4/DDR0_DQ_20

BN11

DDR1_DQ_5/DDR0_DQ_21

BP8

DDR1_DQ_6/DDR0_DQ_22

BN8

DDR1_DQ_7/DDR0_DQ_23

BL12

DDR1_DQ_8/DDR0_DQ_24

BL11

DDR1_DQ_9/DDR0_DQ_25

BL8

DDR1_DQ_10/DDR0_DQ_26

BJ8

DDR1_DQ_11/DDR0_DQ_27

BJ11

DDR1_DQ_12/DDR0_DQ_28

BJ10

DDR1_DQ_13/DDR0_DQ_29

BL7

DDR1_DQ_14/DDR0_DQ_30

BJ7

DDR1_DQ_15/DDR0_DQ_31

BG11

DDR1_DQ_16/DDR0_DQ_48

BG10

DDR1_DQ_17/DDR0_DQ_49

BG8

DDR1_DQ_18/DDR0_DQ_50

BF8

DDR1_DQ_19/DDR0_DQ_51

BF11

DDR1_DQ_20/DDR0_DQ_52

BF10

DDR1_DQ_21/DDR0_DQ_53

BG7

DDR1_DQ_22/DDR0_DQ_54

BF7

DDR1_DQ_23/DDR0_DQ_55

BB11

DDR1_DQ_24/DDR0_DQ_56

BC11

DDR1_DQ_25/DDR0_DQ_57

BB8

DDR1_DQ_26/DDR0_DQ_58

BC8

DDR1_DQ_27/DDR0_DQ_59

BC10

DDR1_DQ_28/DDR0_DQ_60

BB10

DDR1_DQ_29/DDR0_DQ_61

BC7

DDR1_DQ_30/DDR0_DQ_62

BB7

DDR1_DQ_31/DDR0_DQ_63

AA11

DDR1_DQ_32/DDR1_DQ_16

AA10

DDR1_DQ_33/DDR1_DQ_17

AC11

DDR1_DQ_34/DDR1_DQ_18

AC10

DDR1_DQ_35/DDR1_DQ_19

AA7

DDR1_DQ_36/DDR1_DQ_20

AA8

DDR1_DQ_37/DDR1_DQ_21

AC8

DDR1_DQ_38/DDR1_DQ_22

AC7

DDR1_DQ_39/DDR1_DQ_23

DDR4(IL)/LP3-DDR4(NIL)

W8

DDR1_DQ_40/DDR1_DQ_24

W7

DDR1_DQ_41/DDR1_DQ_25

V10

DDR1_DQ_42/DDR1_DQ_26

V11

DDR1_DQ_43/DDR1_DQ_27

W11

DDR1_DQ_44/DDR1_DQ_28

W10

DDR1_DQ_45/DDR1_DQ_29

V7

DDR1_DQ_46/DDR1_DQ_30

V8

DDR1_DQ_47/DDR1_DQ_31

R11

DDR1_DQ_48/DDR1_DQ_48

P11

DDR1_DQ_49/DDR1_DQ_49

P7

DDR1_DQ_50/DDR1_DQ_50

R8

DDR1_DQ_51/DDR1_DQ_51

R10

DDR1_DQ_52/DDR1_DQ_52

P10

DDR1_DQ_53/DDR1_DQ_53

R7

DDR1_DQ_54/DDR1_DQ_54

P8

DDR1_DQ_55/DDR1_DQ_55

L11

DDR1_DQ_56/DDR1_DQ_56

M11

DDR1_DQ_57/DDR1_DQ_57

L7

DDR1_DQ_58/DDR1_DQ_58

M8

DDR1_DQ_59/DDR1_DQ_59

L10

DDR1_DQ_60/DDR1_DQ_60

M10

DDR1_DQ_61/DDR1_DQ_61

M7

DDR1_DQ_62/DDR1_DQ_62

L8

DDR1_DQ_63/DDR1_DQ_63

LP3/DDR4

AW11

NC/DDR1_ECC_0

AY11

NC/DDR1_ECC_1

AY8

NC/DDR1_ECC_2

AW8

NC/DDR1_ECC_3

AY10

NC/DDR1_ECC_4

AW10

NC/DDR1_ECC_5

AY7

NC/DDR1_ECC_6

AW7

NC/DDR1_ECC_7

CFL-H

DDR CHANNEL B

DDR1_CKP_0/DDR1_CKP_0 DDR1_CKN_0/DDR1_CKN_0 DDR1_CKP_1/DDR1_CKP_1 DDR1_CKN_1/DDR1_CKN_1

DDR1_CKE_0/DDR1_CKE_0 DDR1_CKE_1/DDR1_CKE_1 DDR1_CKE_2/DDR1_CKE_2 DDR1_CKE_3/DDR1_CKE_3

DDR1_CS#_0/DDR1_CS#_0 DDR1_CS#_1/DDR1_CS#_1

DDR1_ODT_0/DDR1_ODT_0

DDR1_CAB_3/DDR1_MA_16 DDR1_CAB_2/DDR1_MA_14 DDR1_CAB_1/DDR1_MA_15

DDR1_CAB_4/DDR1_BA_0 DDR1_CAB_6/DDR1_BA_1

DDR1_CAA_5/DDR1_BG_0

DDR1_CAB_9/DDR1_MA_0 DDR1_CAB_8/DDR1_MA_1 DDR1_CAB_5/DDR1_MA_2

DDR1_CAA_0/DDR1_MA_5 DDR1_CAA_2/DDR1_MA_6 DDR1_CAA_4/DDR1_MA_7

DDR1_CAA_3/DDR1_MA_8

DDR1_CAA_1/DDR1_MA_9 DDR1_CAB_7/DDR1_MA_10 DDR1_CAA_7/DDR1_MA_11 DDR1_CAA_6/DDR1_MA_12 DDR1_CAB_0/DDR1_MA_13

DDR1_CAA_9/DDR1_BG_1

DDR1_CAA_8/DDR1_ACT#

DDR4(IL)/LP3-DDR4(NIL)

DDR1_DQSN_0/DDR0_DQSN_2 DDR1_DQSN_1/DDR0_DQSN_3 DDR1_DQSN_2/DDR0_DQSN_6 DDR1_DQSN_3/DDR0_DQSN_7 DDR1_DQSN_4/DDR1_DQSN_2 DDR1_DQSN_5/DDR1_DQSN_3 DDR1_DQSN_6/DDR1_DQSN_6 DDR1_DQSN_7/DDR1_DQSN_7

DDR1_DQSP_0/DDR0_DQSP_2 DDR1_DQSP_1/DDR0_DQSP_3 DDR1_DQSP_2/DDR0_DQSP_6 DDR1_DQSP_3/DDR0_DQSP_7 DDR1_DQSP_4/DDR1_DQSP_2 DDR1_DQSP_5/DDR1_DQSP_3 DDR1_DQSP_6/DDR1_DQSP_6 DDR1_DQSP_7/DDR1_DQSP_7

DDR1_DQSP_8/DDR1_DQSP_8 DDR1_DQSN_8/DDR1_DQSN_8

LP3/DDR4

NC/DDR1_CKP_2 NC/DDR1_CKN_2 NC/DDR1_CKP_3 NC/DDR1_CKN_3

NC/DDR1_CS#_2 NC/DDR1_CS#_3

NC/DDR1_ODT_1 NC/DDR1_ODT_2 NC/DDR1_ODT_3

NC/DDR1_MA_3 NC/DDR1_MA_4

NC/DDR1_PAR

NC/DDR1_ALERT#

AM9 AN9 AM7 AM8 AM11 AM10 AJ10 AJ11

AT8 AT10 AT7 AT11

AF11 AE7 AF10 AE10

AF7 AE8 AE9 AE11

AH10 AH11 AF8

AH8 AH9 AR9

AJ9 AK6 AK5 AL5 AL6 AM6 AN7 AN10

AN8 AR11 AH7 AN11 AR10 AF9 AR7 AT9

AJ7 AR8

BN9 BL9 BG9 BC9 AC9 W9 R9 M9

BP9 BJ9 BF9 BB9 AA9 V9 P9 L9

AW9 AY9

DDR_B_C LK0 DDR_B_C LK#0 DDR_B_C LK1 DDR_B_C LK#1

DDR_B_C KE0 DDR_B_C KE1

DDR_B_C S#0 DDR_B_C S#1

DDR_B_O DT0 DDR_B_O DT1

DDR_B_M A16_RAS# DDR_B_M A14_WE# DDR_B_M A15_CAS#

DDR_B_B A0 DDR_B_B A1 DDR_B_B G0

DDR_B_M A0 DDR_B_M A1 DDR_B_M A2 DDR_B_M A3 DDR_B_M A4 DDR_B_M A5 DDR_B_M A6 DDR_B_M A7

DDR_B_M A8 DDR_B_M A9 DDR_B_M A10 DDR_B_M A11 DDR_B_M A12 DDR_B_M A13 DDR_B_B G1 DDR_B_A CT#

DDR_B_P AR DDR_B_A LERT#

DDR_B_D QS#0 DDR_B_D QS#1 DDR_B_D QS#2 DDR_B_D QS#3 DDR_B_D QS#4 DDR_B_D QS#5 DDR_B_D QS#6 DDR_B_D QS#7

DDR_B_D QS0 DDR_B_D QS1 DDR_B_D QS2 DDR_B_D QS3 DDR_B_D QS4 DDR_B_D QS5 DDR_B_D QS6 DDR_B_D QS7

DDR_B_C LK0 <24> DDR_B_C LK#0 <24> DDR_B_C LK1 <24> DDR_B_C LK#1 <24>

DDR_B_C KE0 <24> DDR_B_C KE1 <24>

DDR_B_C S#0 <24> DDR_B_C S#1 <24>

DDR_B_O DT0 <24> DDR_B_O DT1 <24>

DDR_B_M A16_RAS# <24> DDR_B_M A14_WE# <24> DDR_B_M A15_CAS# <24>

DDR_B_B A0 < 24> DDR_B_B A1 < 24> DDR_B_B G0 < 24>

DDR_B_M A0 <24> DDR_B_M A1 <24> DDR_B_M A2 <24> DDR_B_M A3 <24> DDR_B_M A4 <24> DDR_B_M A5 <24> DDR_B_M A6 <24> DDR_B_M A7 <24>

DDR_B_M A8 <24> DDR_B_M A9 <24> DDR_B_M A10 <24 > DDR_B_M A11 <24 > DDR_B_M A12 <24 > DDR_B_M A13 <24 > DDR_B_B G1 < 24> DDR_B_A CT# <24>

DDR_B_P AR <24> DDR_B_A LERT# <24>

DDR_B_D QS#0 <24> DDR_B_D QS#1 <24> DDR_B_D QS#2 <24> DDR_B_D QS#3 <24> DDR_B_D QS#4 <24> DDR_B_D QS#5 <24> DDR_B_D QS#6 <24> DDR_B_D QS#7 <24>

DDR_B_D QS0 <24> DDR_B_D QS1 <24> DDR_B_D QS2 <24> DDR_B_D QS3 <24> DDR_B_D QS4 <24> DDR_B_D QS5 <24> DDR_B_D QS6 <24> DDR_B_D QS7 <24>

For ECC DIMM

1 2

RC3 121 _0402_1%

1 2

RC4 75_040 2_1%

1 2

RC5 100_04 02_1%

Trace Width/Space: 15 mil/ 25 mil

4 4

A

Max Trace Length: 500 mil

B

SM_RCOM P0 SM_RCOM P1 SM_RCOM P2

G1

DDR_RCOMP_0

H1

DDR_RCOMP_1

J2

DDR_RCOMP_2

CFL-H_BG A1440

@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2 OF 13

DDR_VREF_CA DDR0_VREF_DQ DDR1_VREF_DQ

Compal Secret Data

2017/10/ 30 2018/10 /30

C

Compal Secret Data

BN13 BP13 BR13

Deciphered Date

+0.6V_VR EFCA

+0.6V_B_ VREFDQ

+0.6V_VR EFCA

+0.6V_B_ VREFDQ

D

Compal Electronics, Inc.

Title

CFL-H(3/8)DIMMB

Size Document Number Re v

Custom

EH5VF M/B LA-H501P

Date : Sheet o f

8 101Friday, February 22, 2019

E

1A

A

PEG&DMI

B

C

D

E

1 1

2 2

3 3

To DGPU PEG Lane Reversed

PEG_CRX _C_GTX_P15<27> PEG_CRX _C_GTX_N15<27>

PEG_CRX _C_GTX_P14<27> PEG_CRX _C_GTX_N14<27>

PEG_CRX _C_GTX_P13<27> PEG_CRX _C_GTX_N13<27>

PEG_CRX _C_GTX_P12<27> PEG_CRX _C_GTX_N12<27>

PEG_CRX _C_GTX_P11<27> PEG_CRX _C_GTX_N11<27>

PEG_CRX _C_GTX_P10<27> PEG_CRX _C_GTX_N10<27>

PEG_CRX _C_GTX_P9<27> PEG_CRX _C_GTX_N9<27>

PEG_CRX _C_GTX_P8<27> PEG_CRX _C_GTX_N8<27>

PEG_CRX _C_GTX_P7<27> PEG_CRX _C_GTX_N7<27>

PEG_CRX _C_GTX_P6<27> PEG_CRX _C_GTX_N6<27>

PEG_CRX _C_GTX_P5<27> PEG_CRX _C_GTX_N5<27>

PEG_CRX _C_GTX_P4<27> PEG_CRX _C_GTX_N4<27>

PEG_CRX _C_GTX_P3<27> PEG_CRX _C_GTX_N3<27>

PEG_CRX _C_GTX_P2<27> PEG_CRX _C_GTX_N2<27>

PEG_CRX _C_GTX_P1<27> PEG_CRX _C_GTX_N1<27>

PEG_CRX _C_GTX_P0<27> PEG_CRX _C_GTX_N0<27>

+VCCIO

To PCH

1 2

CC1 0.22U_020 1_6.3V6KVGA@

1 2

CC3 0.22U_020 1_6.3V6KVGA@

1 2

CC5 0.22U_020 1_6.3V6KVGA@

1 2

CC6 0.22U_020 1_6.3V6KVGA@

1 2

CC7 0.22U_020 1_6.3V6KVGA@

1 2

CC14 0.22U_02 01_6.3V6KVGA@

1 2

CC16 0.22U_02 01_6.3V6KVGA@

1 2

CC17 0.22U_02 01_6.3V6KVGA@

1 2

CC19 0.22U_02 01_6.3V6KVGA@

1 2

CC20 0.22U_02 01_6.3V6KVGA@

1 2

CC10 0.22U_02 01_6.3V6KVGA@

1 2

CC23 0.22U_02 01_6.3V6KVGA@

1 2

CC25 0.22U_02 01_6.3V6KVGA@

1 2

CC27 0.22U_02 01_6.3V6KVGA@

1 2

CC29 0.22U_02 01_6.3V6KVGA@

1 2

CC31 0.22U_02 01_6.3V6KVGA@

1 2

CC33 0.22U_02 01_6.3V6KVGA@

1 2

CC35 0.22U_02 01_6.3V6KVGA@

1 2

CC37 0.22U_02 01_6.3V6KVGA@

1 2

CC39 0.22U_02 01_6.3V6KVGA@

1 2

CC41 0.22U_02 01_6.3V6KVGA@

1 2

CC43 0.22U_02 01_6.3V6KVGA@

1 2

CC45 0.22U_02 01_6.3V6KVGA@

1 2

CC47 0.22U_02 01_6.3V6KVGA@

1 2

CC49 0.22U_02 01_6.3V6KVGA@

1 2

CC51 0.22U_02 01_6.3V6KVGA@

1 2

CC53 0.22U_02 01_6.3V6KVGA@

1 2

CC55 0.22U_02 01_6.3V6KVGA@

1 2

CC57 0.22U_02 01_6.3V6KVGA@

1 2

CC59 0.22U_02 01_6.3V6KVGA@

1 2

CC61 0.22U_02 01_6.3V6KVGA@

1 2

CC63 0.22U_02 01_6.3V6KVGA@

1 2

RC6 24.9_04 02_1%

DMI_CRX_P TX_P0<14> DMI_CRX_P TX_N0<14>

DMI_CRX_P TX_P1<14> DMI_CRX_P TX_N1<14>

DMI_CRX_P TX_P2<14> DMI_CRX_P TX_N2<14>

DMI_CRX_P TX_P3<14> DMI_CRX_P TX_N3<14>

PEG_CRX _GTX_P15 PEG_CRX _GTX_N15

PEG_CRX _GTX_P14 PEG_CRX _GTX_N14

PEG_CRX _GTX_P13 PEG_CRX _GTX_N13

PEG_CRX _GTX_P12 PEG_CRX _GTX_N12

PEG_CRX _GTX_P11 PEG_CRX _GTX_N11

PEG_CRX _GTX_P10 PEG_CRX _GTX_N10

PEG_CRX _GTX_P9 PEG_CRX _GTX_N9

PEG_CRX _GTX_P8 PEG_CRX _GTX_N8

PEG_CRX _GTX_P7 PEG_CRX _GTX_N7

PEG_CRX _GTX_P6 PEG_CRX _GTX_N6

PEG_CRX _GTX_P5 PEG_CRX _GTX_N5

PEG_CRX _GTX_P4 PEG_CRX _GTX_N4

PEG_CRX _GTX_P3 PEG_CRX _GTX_N3

PEG_CRX _GTX_P2 PEG_CRX _GTX_N2

PEG_CRX _GTX_P1 PEG_CRX _GTX_N1

PEG_CRX _GTX_P0 PEG_CRX _GTX_N0

PEG_RCO MP

Trace Width/Space: 15 mil/ 15 mil Max Trace Length: 600 mil

DMI_CRX_P TX_P0 DMI_CRX_P TX_N0

DMI_CRX_P TX_P1 DMI_CRX_P TX_N1

DMI_CRX_P TX_P2 DMI_CRX_P TX_N2

DMI_CRX_P TX_P3 DMI_CRX_P TX_N3

E25

PEG_RXP_0

D25

PEG_RXN_0

E24

PEG_RXP_1

F24

PEG_RXN_1

E23

PEG_RXP_2

D23

PEG_RXN_2

E22

PEG_RXP_3

F22

PEG_RXN_3

E21

PEG_RXP_4

D21

PEG_RXN_4

E20

PEG_RXP_5

F20

PEG_RXN_5

E19

PEG_RXP_6

D19

PEG_RXN_6

E18

PEG_RXP_7

F18

PEG_RXN_7

D17

PEG_RXP_8

E17

PEG_RXN_8

F16

PEG_RXP_9

E16

PEG_RXN_9

D15

PEG_RXP_10

E15

PEG_RXN_10

F14

PEG_RXP_11

E14

PEG_RXN_11

D13

PEG_RXP_12

E13

PEG_RXN_12

F12

PEG_RXP_13

E12

PEG_RXN_13

D11

PEG_RXP_14

E11

PEG_RXN_14

F10

PEG_RXP_15

E10

PEG_RXN_15

G2

PEG_RCOMP

D8

DMI_RXP_0

E8

DMI_RXN_0

E6

DMI_RXP_1

F6

DMI_RXN_1

D5

DMI_RXP_2

E5

DMI_RXN_2

J8

DMI_RXP_3

J9

DMI_RXN_3

CFL-H_BG A1440

@

UC1C

CFL-H

PEG_TXP_10 PEG_TXN_10

PEG_TXP_11 PEG_TXN_11

PEG_TXP_12 PEG_TXN_12

PEG_TXP_13 PEG_TXN_13

PEG_TXP_14 PEG_TXN_14

PEG_TXP_15 PEG_TXN_15

3 OF 13

PEG_TXP_0 PEG_TXN_0

PEG_TXP_1 PEG_TXN_1

PEG_TXP_2 PEG_TXN_2

PEG_TXP_3 PEG_TXN_3

PEG_TXP_4 PEG_TXN_4

PEG_TXP_5 PEG_TXN_5

PEG_TXP_6 PEG_TXN_6

PEG_TXP_7 PEG_TXN_7

PEG_TXP_8 PEG_TXN_8

PEG_TXP_9 PEG_TXN_9

DMI_TXP_0 DMI_TXN_0

DMI_TXP_1 DMI_TXN_1

DMI_TXP_2 DMI_TXN_2

DMI_TXP_3 DMI_TXN_3

B25 A25

B24 C24

B23 A23

B22 C22

B21 A21

B20 C20

B19 A19

B18 C18

A17 B17

C16 B16

A15 B15

C14 B14

A13 B13

C12 B12

A11 B11

C10 B10

B8 A8

C6 B6

B5 A5

D4 B4

PEG_CTX _GRX_P15

PEG_CTX _GRX_N15

PEG_CTX _GRX_P14

PEG_CTX _GRX_N14

PEG_CTX _GRX_P13

PEG_CTX _GRX_N13

PEG_CTX _GRX_P12

PEG_CTX _GRX_N12

PEG_CTX _GRX_P11

PEG_CTX _GRX_N11

PEG_CTX _GRX_P10

PEG_CTX _GRX_N10

PEG_CTX _GRX_P9

PEG_CTX _GRX_N9

PEG_CTX _GRX_P8

PEG_CTX _GRX_N8

PEG_CTX _GRX_P7

PEG_CTX _GRX_N7

PEG_CTX _GRX_P6

PEG_CTX _GRX_N6

PEG_CTX _GRX_P5

PEG_CTX _GRX_N5

PEG_CTX _GRX_P4

PEG_CTX _GRX_N4

PEG_CTX _GRX_P3

PEG_CTX _GRX_N3

PEG_CTX _GRX_P2

PEG_CTX _GRX_N2

PEG_CTX _GRX_P1

PEG_CTX _GRX_N1

PEG_CTX _GRX_P0

PEG_CTX _GRX_N0

DMI_CTX_P RX_P0 DMI_CTX_P RX_N0

DMI_CTX_P RX_P1 DMI_CTX_P RX_N1

DMI_CTX_P RX_P2 DMI_CTX_P RX_N2

DMI_CTX_P RX_P3 DMI_CTX_P RX_N3

12

CC20.22U_02 01_6.3V6K V GA@

12

CC40.22U_02 01_6.3V6K V GA@

12

CC110.22U_02 01_6.3V6K V GA@

12

CC120.22U_02 01_6.3V6K V GA@

12

CC130.22U_02 01_6.3V6K V GA@

12

CC150.22U_02 01_6.3V6K V GA@

12

CC80.22U_02 01_6.3V6K V GA@

12

CC180.22U_02 01_6.3V6K V GA@

12

CC90.22U_02 01_6.3V6K V GA@

12

CC210.22U_02 01_6.3V6K V GA@

12

CC220.22U_02 01_6.3V6K V GA@

12

CC240.22U_02 01_6.3V6K V GA@

12

CC260.22U_02 01_6.3V6K V GA@

12

CC280.22U_02 01_6.3V6K V GA@

12

CC300.22U_02 01_6.3V6K V GA@

12

CC320.22U_02 01_6.3V6K V GA@

12

CC340.22U_02 01_6.3V6K V GA@

12

CC360.22U_02 01_6.3V6K V GA@

12

CC380.22U_02 01_6.3V6K V GA@

12

CC400.22U_02 01_6.3V6K V GA@

12

CC420.22U_02 01_6.3V6K V GA@

12

CC440.22U_02 01_6.3V6K V GA@

12

CC460.22U_02 01_6.3V6K V GA@

12

CC480.22U_02 01_6.3V6K V GA@

12

CC500.22U_02 01_6.3V6K V GA@

12

CC520.22U_02 01_6.3V6K V GA@

12

CC540.22U_02 01_6.3V6K V GA@

12

CC560.22U_02 01_6.3V6K V GA@

12

CC580.22U_02 01_6.3V6K V GA@

12

CC600.22U_02 01_6.3V6K V GA@

12

CC620.22U_02 01_6.3V6K V GA@

12

CC640.22U_02 01_6.3V6K V GA@

DMI_CTX_P RX_P0 <14> DMI_CTX_P RX_N0 <14>

DMI_CTX_P RX_P1 <14> DMI_CTX_P RX_N1 <14>

DMI_CTX_P RX_P2 <14> DMI_CTX_P RX_N2 <14>

DMI_CTX_P RX_P3 <14> DMI_CTX_P RX_N3 <14>

PEG_CTX _C_GRX_P15 <27>

PEG_CTX _C_GRX_N15 <2 7>

PEG_CTX _C_GRX_P14 <27>

PEG_CTX _C_GRX_N14 <2 7>

PEG_CTX _C_GRX_P13 <27>

PEG_CTX _C_GRX_N13 <2 7>

PEG_CTX _C_GRX_P12 <27>

PEG_CTX _C_GRX_N12 <2 7>

PEG_CTX _C_GRX_P11 <27>

PEG_CTX _C_GRX_N11 <2 7>

PEG_CTX _C_GRX_P10 <27>

PEG_CTX _C_GRX_N10 <2 7>

PEG_CTX _C_GRX_P9 <27>

PEG_CTX _C_GRX_N9 <27 >

PEG_CTX _C_GRX_P8 <27>

PEG_CTX _C_GRX_N8 <27 >

PEG_CTX _C_GRX_P7 <27>

PEG_CTX _C_GRX_N7 <27 >

PEG_CTX _C_GRX_P6 <27>

PEG_CTX _C_GRX_N6 <27 >

PEG_CTX _C_GRX_P5 <27>

PEG_CTX _C_GRX_N5 <27 >

PEG_CTX _C_GRX_P4 <27>

PEG_CTX _C_GRX_N4 <27 >

PEG_CTX _C_GRX_P3 <27>

PEG_CTX _C_GRX_N3 <27 >

PEG_CTX _C_GRX_P2 <27>

PEG_CTX _C_GRX_N2 <27 >

PEG_CTX _C_GRX_P1 <27>

PEG_CTX _C_GRX_N1 <27 >

PEG_CTX _C_GRX_P0 <27>

PEG_CTX _C_GRX_N0 <27 >

To PCH

To DGPU PEG Lane Reversed

4 4

Security Classification

2017/10/ 30 2018/10 /30

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

2017/10/ 30 2018/10 /30

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

PEG/DMI

Size Document Number Re v

Custom

EH5VF M/B LA-H501P

Date : Sheet o f

D

Date : Sheet o f

9 101Friday, February 22, 2019

E

1A

A

571391_CFL_H_PDG_Rev0p5

1. The total Length of Data and Clock (from CPU to each VR) must be equal (± 0.1 inch).

2. Route the Alert signal between the Clock and the Data signals.

1 1

3. Place those resistors close CPU side.

2 2

PGESD@

1 2

PGESD@

1 2

PGESD@

1 2

PGESD@

1 2

XESD@

1 2

PGESD@

1 2

PGESD@

1 2

PGESD@

1 2

PGESD@

1 2

CC951000P _0402_50V7K

CC961000P _0402_50V7K

CC971000P _0402_50V7K

CC981000P _0402_50V7K

CC991000P _0402_50V7K

CC1001000P_0 402_50V7K

CC1011000P_0 402_50V7K

CC1021000P_0 402_50V7K

CC1031000P_0 402_50V7K

PROC_S ELECT # should be unconnected on CFL processor EDS1.2 8/21

XESD@

1 2

ESD@

1 2

XESD@

1 2

ESD@

1 2

CC650.1U_020 1_10V6K

CC661000P _0402_50V7K

CC670.1U_020 1_10V6K

CC681000P _0402_50V7K

H_CPUPW RGD

H_PROCH OT#_R

H_THERM TRIP#

EC_VCCS T_PG

Sensitive

H_CPUPW RGD<18> H_PLTRS T_CPU#<17> H_PM_SYNC _R<17>

H_PECI<17,58>

PCH_THE RMTRIP#_R<1 7>

Near CPU side

follow 1050 Request 8/

+1.05V_V CCST

3 3

21

1 2

RH1 1K_040 2_5%

+1.05VS_ VCCSTG

12

RC21 1K_0402 _5%

H_THERM TRIP#

PCH_CPU _PCIBCLK_P<15> PCH_CPU _PCIBCLK_N<1 5>

PCH_CPU _24M_CLK_P<15> PCH_CPU _24M_CLK_N<15>

PCH_CPU _BCLK_P<15> PCH_CPU _BCLK_N<15>

CPU_SVID_ CLK<89>

RC17 0_ 0402_5%@

B

1 2

TC5@

TC6@

DDR_PG_ CTRL

PCH_CPU _BCLK_P PCH_CPU _BCLK_N

PCH_CPU _PCIBCLK_P PCH_CPU _PCIBCLK_N

PCH_CPU _24M_CLK_P PCH_CPU _24M_CLK_N

CPU_SVID_ ALERT# CPU_SVID_ CLK CPU_SVID_ DAT H_PROCH OT#_R

DDR_PG_ CTRL

EC_VCCS T_PG

H_CPUPW RGD H_PLTRS T_CPU# H_PM_SYNC _R H_PM_DO WN H_PECI H_THERM TRIP#

SKTOCC#

CATERR#

+1.2V_VD DQ

2

A4Y

B31 A32

D35 C36

E31 D31

BH31 BH32 BH29 BR30

BT13

H13

BT31 BP35 BM34 BP31

BT34

J31

BR33

BN1

BM30

AT13

AW13

AU13 AY13

CC69

0.1U_020 1_10V6K

12

5

1

UC3

Vcc

NC

G

74AUP1G 07SE-7_SOT353 -5

3

C

UC1E

BCLKP BCLKN

PCI_BCLKP PCI_BCLKN

CLK24P CLK24N

VIDALERT# VIDSCK VIDSOUT PROCHOT#

DDR_VTT_CNTL

VCCST_PWRGD

PROCPWRGD RESET# PM_SYNC PM_DOWN PECI THERMTRIP#

SKTOCC# PROC_SELECT#

CATERR#

ZVM# MSM#

RSVD1 RSVD2

CFL-H_BG A1440

@

CFL-H

BN25

CFG_0

BN27

CFG_1

BN26

CFG_2

BN28

CFG_3

BR20

CFG_4

BM20

CFG_5

BT20

CFG_6

BP20

CFG_7

BR23

CFG_8

BR22

CFG_9

BT23

CFG_10

BT22

CFG_11

BM19

CFG_12

BR19

CFG_13

BP19

CFG_14

BT19

CFG_15

BN23

CFG_17

BP23

CFG_16

BP22

CFG_19

BN22

CFG_18

BR27

BPM#_0

BT27

BPM#_1

BM31

BPM#_2

BT30

BPM#_3

PROC_TDI

+3VS

12

RC23 330K_04 02_5%

BT28 BL32 BP28 BR28

BP30 BL30 BP27

BT25

PROC_TDO

PROC_TMS PROC_TCK

PROC_TRST# PROC_PREQ# PROC_PRDY#

CFG_RCOMP

5 OF 13

PU 330K follow CRB 8/21

CFG0

CFG2

CFG4 CFG5 CFG6 CFG7

XDP_BPM #0 XDP_BPM #1 XDP_BPM #2 XDP_BPM #3

CPU_XDP _TDO CPU_XDP _TDI CPU_XDP _TMS CPU_XDP _TCK0

CPU_XDP _TRST# XDP_PRE Q# XDP_PRD Y#

CFG_RCO MP

Trace Width/Space: 4 mil/ 12 mil Max Trace Length: 600 mil

SM_PG_C TRL <85>

RC18

1 2

TC1 @ TC2 @ TC3 @ TC4 @

TC19 @ TC20 @

49.9_040 2_1%

D

CPU_XDP _TDO <18> CPU_XDP_TDI <18> CPU_XDP_TMS <18> CPU_XDP_TCK0 <18>

CPU_XDP_TRST# <21 >

+1.05VS_ VCCSTG

RC76 51_0402 _5%CMC@

RC77 51_0402 _5%CMC@

RC78 51_0402 _5%CMC@

RC79 51_0402 _5%CMC@

RC80 51_0402 _5%@

RC81 51_0402 _5%@

E

CFG0 CFG2 CFG4 CFG5 CFG6 CFG7

The CFG signals have a default value of '1' if not terminated on the board.

CFG[0]: Stall reset sequence after PCU PLL lock until de-asserted

*

1 = (Default) Normal Operation; 0 = Stall.

CFG[2]: PCI Express* Static x16 Lane Numbering Rever

1 = Normal operation 0 = Lane numbers reversed.

*

CFG[4]: eDP enable:

1 = Disabled. 0 = Enabled.

*

CFG[6:5]: PCI Express* Bifurcation:

00 = 1 x8, 2 x4 PCI Express* 01 = reserved 10 = 2 x8 PCI Express* 11 = 1 x16 PCI Express*

*

CFG[7]: PEG Training:

*

1 = (default) PEG Train immediately following RESET# de assertion. 0 = PEG Wait for BIOS for training.

*CFG Pin Use CMC debug on DDX03 R02 Schematic.

To be confirm

XDP_PRE Q# XDP_PRD Y#

1 2

RC7 1K_040 2_5%@

1 2

RC8 1K_040 2_5%

1 2

RC9 1K_040 2_5%

1 2

RC10 1K _0402_5%@

1 2

RC11 1K _0402_5%@

1 2

RC12 1K _0402_5%@

XDP_PREQ# <21> XDP_PRD Y# < 21>

sal.

Place to CPU side

12

CPU_XDP _TMS

CPU_XDP _TDI

CPU_XDP _TDO

Place to CPU side

12

CPU_XDP _TCK0

PCH_JTA G_TCK1

CPU_XDP _TRST#

PCH_JTA G_TCK1 <18>

SVID

1 2

H_PROCH OT#<58,83>

EC_VCCS T_PG_R<58,78>

H_PM_DO WN_R<17>

4 4

A

RC14 49 9_0402_1%

+1.05V_V CCST

12

RC22 1K_0402 _5%

1 2

RC15 60.4_0402_ 1%

1 2

RC16 20 _0402_5%

12

RH2

@

13_0402 _5%

H_PROCH OT#_R

+1.05V_V CCST

12

RC19

Issued Date

56_0402 _1%

EC_VCCS T_PG

H_PM_DO WN CPU_SVID_ ALERT#

B

CPU_SVID_ALERT#_R<89>

CPU_SVID_ DAT<89>

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

RC20 100_040 2_1%

1 2

RC13 22 0_0402_5%

CPU_SVID_ DAT

Compal Secret Data

2017/10/ 30 2018/10 /30

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

CFL-H(5/8)CFG,SVID

Size Document Number Re v

Custom

EH5VF M/B LA-H501P

Date : Sheet o f

D

Date : Sheet o f

10 1 01Friday, February 22, 201 9

E

1A

A

B

C

D

E

GT

2000mA(Hexa Core GT2)

3

AT14 AT31 AT32 AT33 AT34 AT35 AT36 AT37

1 1

2 2

3 3

4 4

AT38 AU14 AU29 AU30 AU31 AU32 AU35 AU36 AU37 AU38 AV29 AV30 AV31 AV32 AV33 AV34 AV35 AV36

AW14 AW31 AW32 AW33 AW34 AW35 AW36 AW37 AW38

AY29 AY30 AY31 AY32 AY35 AY36 AY37 AY38 BA13 BA14 BA29 BA30 BA31 BA32 BA33 BA34 BA35 BA36 BB13 BB14 BB31 BB32 BB33 BB34 BB35 BB36 BB37 BB38 BC29 BC30 BC31 BC32 BC35 BC36 BC37 BC38 BD13 BD14 BD29 BD30 BD31 BD32 BD33 BD34 BP37 BP38 BR15 BR16 BR17

CFL-H

UC1K

VCCGT1 VCCGT2 VCCGT3 VCCGT4 VCCGT5 VCCGT6 VCCGT7 VCCGT8 VCCGT9 VCCGT10 VCCGT11 VCCGT12 VCCGT13 VCCGT14 VCCGT15 VCCGT16 VCCGT17 VCCGT18 VCCGT19 VCCGT20 VCCGT21 VCCGT22 VCCGT23 VCCGT24 VCCGT25 VCCGT26 VCCGT27 VCCGT28 VCCGT29 VCCGT30 VCCGT31 VCCGT32 VCCGT33 VCCGT34 VCCGT35 VCCGT36 VCCGT37 VCCGT38 VCCGT39 VCCGT40 VCCGT41 VCCGT42 VCCGT43 VCCGT44 VCCGT45 VCCGT46 VCCGT47 VCCGT48 VCCGT49 VCCGT50 VCCGT51 VCCGT52 VCCGT53 VCCGT54 VCCGT55 VCCGT56 VCCGT57 VCCGT58 VCCGT59 VCCGT60 VCCGT61 VCCGT62 VCCGT63 VCCGT64 VCCGT65 VCCGT66 VCCGT67 VCCGT68 VCCGT69 VCCGT70 VCCGT71 VCCGT72 VCCGT73 VCCGT74 VCCGT75 VCCGT76 VCCGT77 VCCGT78 VCCGT79 VCCGT159 VCCGT160 VCCGT161 VCCGT162 VCCGT163

11 OF 13

CFL-H_BG A1440

@

+VCC_GT+VCC_GT

BD35

VCCGT80

BD36

VCCGT81

BE31

VCCGT82

BE32

VCCGT83

BE33

VCCGT84

BE34

VCCGT85

BE35

VCCGT86

BE36

VCCGT87

BE37

VCCGT88

BE38

VCCGT89

BF13

VCCGT90

BF14

VCCGT91

BF29

VCCGT92

BF30

VCCGT93

BF31

VCCGT94

BF32

VCCGT95

BF35

VCCGT96

BF36

VCCGT97

BF37

VCCGT98

BF38

VCCGT99

BG29

VCCGT100

BG30

VCCGT101

BG31

VCCGT102

BG32

VCCGT103

BG33

VCCGT104

BG34

VCCGT105

BG35

VCCGT106

BG36

VCCGT107

BH33

VCCGT108

BH34

VCCGT109

BH35

VCCGT110

BH36

VCCGT111

BH37

VCCGT112

BH38

VCCGT113

BJ16

VCCGT114

BJ17

VCCGT115

BJ19

VCCGT116

BJ20

VCCGT117

BJ21

VCCGT118

BJ23

VCCGT119

BJ24

VCCGT120

BJ26

VCCGT121

BJ27

VCCGT122

BJ37

VCCGT123

BJ38

VCCGT124

BK16

VCCGT125

BK17

VCCGT126

BK19

VCCGT127

BK20

VCCGT128

BK21

VCCGT129

BK23

VCCGT130

BK24

VCCGT131

BK26

VCCGT132

BK27

VCCGT133

BL15

VCCGT134

BL16

VCCGT135

BL17

VCCGT136

BL23

VCCGT137

BL24

VCCGT138

BL25

VCCGT139

BL26

VCCGT140

BL27

VCCGT141

BL28

VCCGT142

BL36

VCCGT143

BL37

VCCGT144

BM15

VCCGT145

BM16

VCCGT146

BM17

VCCGT147

BM36

VCCGT148

BM37

VCCGT149

BN15

VCCGT150

BN16

VCCGT151

BN17

VCCGT152

BN36

VCCGT153

BN37

VCCGT154

BN38

VCCGT155

BP15

VCCGT156

BP16

VCCGT157

BP17

VCCGT158

BR37

VCCGT164

BT15

VCCGT165

BT16

VCCGT166

BT17

VCCGT167

BT37

VCCGT168

VSSGT_S ENSE

VSSGT_SENSE VCCGT_SENSE

AH37

VCCGT_S ENSE

AH38

1. VccGT_SENSE / VssGT_SEN SE Trace L ength Match < 25 mils

2. Maint ain 25-mil separation distance away from any other dynamic signals.

+VCC_CO RE +VCC_CO RE +VCC_CO RE +VCC_CO RE

AA13 AA31 AA32 AA33 AA34 AA35 AA36 AA37 AA38 AB29 AB30 AB31 AB32 AB35 AB36 AB37 AB38 AC13 AC14 AC29 AC30 AC31 AC32 AC33 AC34 AC35 AC36 AD13 AD14 AD31 AD32 AD33 AD34 AD35 AD36 AD37 AD38 AE13 AE14 AE30 AE31 AE32 AE35 AE36 AE37 AE38

AF29 AF30 AF31 AF32 AF33 AF34 AF35 AF36 AF37

AF38 AG14 AG31 AG32 AG33 AG34 AG35 AG36

VSSGT_S ENSE <89>

VCCGT_S ENSE < 89>

UC1I

VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 VCC49 VCC50 VCC51 VCC52 VCC53 VCC54 VCC55 VCC56 VCC57 VCC58 VCC59 VCC60 VCC61 VCC62 VCC63

CFL-H_BG A1440

@

CFL-H

AH13

VCC64

AH14

VCC65

AH29

VCC66

AH30

VCC67

AH31

VCC68

AH32

VCC69

AJ14

VCC70

AJ29

VCC71

AJ30

VCC72

AJ31

VCC73

AJ32

VCC74

AJ33

VCC75

AJ34

VCC76

AJ35

VCC77

AJ36

VCC78

AK31

VCC79

AK32

VCC80

AK33

VCC81

AK34

VCC82

AK35

VCC83

AK36

VCC84

AK37

VCC85

AK38

VCC86

AL13

VCC87

AL29

VCC88

AL30

VCC89

AL31

VCC90

AL32

VCC91

AL35

VCC92

AL36

VCC93

AL37

VCC94

AL38

VCC95

AM13

VCC96

AM14

VCC97

AM29

VCC98

AM30

VCC99

AM31

VCC100

AM32

VCC101

AM33

VCC102

AM34

VCC103

AM35

VCC104

AM36

VCC105

AN13

VCC106

AN14

VCC107

AN31

VCC108

AN32

VCC109

AN33

VCC110

AN34

VCC111

AN35

VCC112

AN36

VCC113

AN37

VCC114

AN38

VCC115

AP13

VCC116

AP30

VCC117

AP31

VCC118

AP32

VCC119

AP35

VCC120

AP36

VCC121

AP37

VCC122

AP38

VCC123

K13

VCC124

VCC_SENSE

9 OF 13

VSS_SENSE

1. Vcc_SENS E/ Vss_SENSE Trace Le ngth Match < 25 m ils

2. Maint ain 25-mil separation distance away from any other dynamic signals.

AG37 AG38

128000mA(Hexa Core GT2)

VCCSENS E VSSSENS E

VCCSENS E <8 9>

VSSSENS E <89>

W13 W14 W29 W30 W31 W32

K14

N13 N14 N30 N31 N32 N35 N36 N37 N38 P13 P14 P29 P30 P31 P32 P33 P34 P35 P36 R13 R31 R32 R33 R34 R35 R36 R37 R38 T29 T30 T31 T32 T35 T36 T37 T38 U29 U30 U31 U32 U33 U34 U35 U36 V13 V14 V31 V32 V33 V34 V35 V36 V37 V38

L13 L14

CFL-H_BG A1440

@

UC1J

VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 VCC49 VCC50 VCC51 VCC52 VCC53 VCC54 VCC55 VCC56 VCC57 VCC58 VCC59 VCC60 VCC61 VCC62 VCC63

CFL-H

10 OF 13

VCC64 VCC65 VCC66 VCC67 VCC68 VCC69 VCC70 VCC71 VCC72 VCC73 VCC74 VCC75

W35 W36 W37 W38 Y29 Y30 Y31 Y32 Y33 Y34 Y35 Y36

Security Classification

2017/10/ 30 2018/10 /30

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

2017/10/ 30 2018/10 /30

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

CFL-H(6/8)VCC_CORE/GT

Size Document Number Re v

Custom

EH5VF M/B LA-H501P

Date : Sheet o f

D

Date : Sheet o f

11 1 01Friday, February 22, 201 9

E

1A

A

+1.2V_VDDQ

+VCC_SA

M29 M30 M31 M32 M33 M34 M35 M36

AG12

G15 G17 G19 G21

K29 K30 K31 K32 K33 K34 K35 L31 L32 L35 L36 L37 L38

H15 H16 H17 H19 H20 H21 H26 H27

J30

J15 J16 J17 J19 J20 J21 J26 J27

CFL-H_BG A1440

@

+VCC_SA Max: 11100mA

1 1

+VCC_IO Max: 6400mA

2 2

+VCCIO

UC1L

VCCSA1 VCCSA2 VCCSA3 VCCSA4 VCCSA5 VCCSA6 VCCSA7 VCCSA8 VCCSA9 VCCSA10 VCCSA11 VCCSA12 VCCSA13 VCCSA14 VCCSA15 VCCSA16 VCCSA17 VCCSA18 VCCSA19 VCCSA20 VCCSA21 VCCSA22

VCCIO1 VCCIO2 VCCIO3 VCCIO4 VCCIO5 VCCIO6 VCCIO7 VCCIO8 VCCIO9 VCCIO10 VCCIO11 VCCIO12 VCCIO13 VCCIO14 VCCIO15 VCCIO16 VCCIO17 VCCIO18 VCCIO19 VCCIO20 VCCIO21

CFL-H

12 OF 13

VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8

VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 VDDQ16 VDDQ17 VDDQ18 VDDQ19 VDDQ20 VDDQ21 VDDQ22 VDDQ23 VDDQ24 VDDQ25

VCCPLL_OC1 VCCPLL_OC2 VCCPLL_OC3

VCCST

VCCSTG2

VCCSTG1

VCCPLL1 VCCPLL2

VCCSA_SENSE

VSSSA_SENSE

VCCIO_SENSE VSSIO_SENSE

Max: 3300mA

+1.2V_VD DQ

AA6 AE12 AF5 AF6 AG5 AG9 AJ12 AL11 AP6 AP7 AR12 AR6 AT12 AW6 AY6 J5 J6 K12 K6 L12 L6 R6 T6 W6 Y12

+1.2V_VC CPLL_OC

BH13 BJ13 G11

H30

H29

G30

H28 J28

M38 M37

H14 J14

B

+1.2V_VD DQ

+1.2V_VCCPLL_OC Max: 130mA

+1.05V_V CCST

Max: 60mA

Max: 20mA

Max: 150mA

VCCIO_SEN SE VSSIO_SEN SE

1. VccGT_SENSE / VssGT_SEN SE Trace L ength Match < 25 mils

2. Maint ain 25-mil separation distance away from any other dynamic signals.

+1.05VS_ VCCSTG

+1.05V_V CCSFR

VCCSA_S ENSE VSSSA_S ENSE

VCCSA_S ENSE <89>

VSSSA_S ENSE <89 >

VCCIO_SEN SE <88>

VSSIO_SEN SE <8 8>

C

10U_0402_6.3V6M

1

2

CC71

CC70

2

571483_CFL_H_RVP_CRB_TDK_Rev0p5 +1.2V_VDDQ_CPU: 10uF * 12 22uF * 4

1

CC72

2

10U_0402_6.3V6M

CC73

10U_0402_6.3V6M

1

CC74

2

RC24 0_ 0402_5%@

D

10U_0402_6.3V6M

1

CC75

CC76

2

10U_0402_6.3V6M

1

2

CC78

CC77

2

10U_0402_6.3V6M

1

2

CC80

CC79

2

PLACE CAP BACKSIDE

+1.2V_VC CPLL_OC+1.2V_VD DQ

1 2

571483_CFL_H_RVP_CRB_TDK_Rev0p5 +1.2V_VCCPLL_OC: 1uF * 2

PLACE CAP BACKSIDE

+1.05V_V CCST

1U_0201_6.3V6M

1

CC86

CC87

2

1 2

RC25 0_ 0402_5%@

1U_0201_6.3V6M

1

CC92

2

571483_CFL_H_RVP_CRB_TDK_Rev0p5 +1.05V_VCCST: 1uF * 1

PLACE CAP BACKSIDE PL

22U_0603_6.3V6M

10U_0402_6.3V6M

1

CC81

2

+VCCIO

1

2

+1.05V_V CCSFR

150mA

1

CC82

2

10U_0402_6.3V6M

1

CC89

CC88

2

571483_CFL_H_RVP_CRB_TDK_Rev0p5 +0.95VS_VCCIO: 10uF * 12 22uF * 4

1U_0201_6.3V6M

1

CC93

2

571483_CFL_H_RVP_CRB_TDK_Rev0p5 +1.05V_VCCSFR: 1uF * 1

ACE CAP BACKSIDE

E

22U_0603_6.3V6M

CC83

10U_0402_6.3V6M

22U_0603_6.3V6M

1

CC84

CC85

2

10U_0402_6.3V6M

1

@

CC91

CC90

2

3 3

4 4

Security Classification

2017/10/ 30 2018/10 /30

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

2017/10/ 30 2018/10 /30

C

Compal Secret Data

Deciphered Date

D

+1.05VS_ VCCSTG

1U_0201_6.3V6M

1

CC94

2

571483_CFL_H_RVP_CRB_TDK_Rev0p5 +1.05VS_VCCSTG: 1uF * 1

Compal Electronics, Inc.

Title

CFL-H(7/8)VCCSA/VCCIO/VDDQ

Size Document Number Re v

Custom

EH5VF M/B LA-H501P

Date : Sheet o f

12 1 01Friday, February 22, 201 9

E

1A

A

B

C

D

E

CFL-H

UC1F

A10

VSS_1

A12

VSS_2

A16

VSS_3

A18

VSS_4

A20

VSS_5

A22

VSS_6

A24

VSS_7

A26

VSS_8

1 1

2 2

3 3

A28 A30

AA12 AA29 AA30 AB33 AB34

AB6

AC1

AC12

AC2

AC3 AC37 AC38

AC4

AC5

AC6 AD10 AD11 AD12 AD29 AD30

AD6

AD8

AD9 AE33 AE34

AE6

AF1 AF12 AF13 AF14

AF2

AF3

AF4 AG10 AG11 AG13 AG29 AG30

AG6 AG7

AG8 AH12 AH33 AH34 AH35 AH36

AH6

AJ1

AJ13

AJ2

AJ3 AJ37 AJ38

AJ4

AJ5

AJ6

Y10

Y11

Y13

Y14

Y37

Y38

AK29 AK30

A6 A9

W4 W5

Y7 Y8 Y9

VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80

6 OF 13

VSS_81

CFL-H_BG A1440

@

VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98

VSS_99 VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162

AK4 AL10 AL12 AL14 AL33 AL34 AL4 AL7 AL8 AL9 AM1 AM12 AM2 AM3 AM37 AM38 AM4 AM5 AN12 AN29 AN30 AN5 AN6 AP10 AP11 AP12 AP33 AP34 AP8 AP9 AR1 AR13 AR14 AR2 AR29 AR3 AR30 AR31 AR32 AR33 AR34 AR35 AR36 AR37 AR38 AR4 AR5 AT29 AT30 AT6 AU10 AU11 AU12 AU33 AU34 AU6 AU7 AU8 AU9 AV37 AV38 AW1 AW12 AW2 AW29 AW3 AW30 AW4 U6 V12 V29 V30 A14 AD7 V6 W1 W12 W2 W3 W33 W34

AW5 AY12 AY33 AY34

BA10 BA11 BA12 BA37 BA38

BB12

BB29

BB30

BC12 BC13 BC14 BC33 BC34

BC6 BD10 BD11 BD12 BD37

BD6

BD7

BD8

BD9

BE1

BE2

BE29

BE3

BE30

BE4

BE5

BE6

BF12 BF33 BF34

BF6 BG12 BG13 BG14 BG37 BG38

BG6

BH1 BH10 BH11 BH12 BH14

BH2

BH3

BH4

BH5

BH6

BH7

BH8

BH9

U37

U38

BJ12 BJ14

BA6 BA7 BA8 BA9 BB1

BB2

BB3

BB4 BB5 BB6

T33 T34

UC1G

VSS_163 VSS_164 VSS_165 VSS_166

B9

VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 VSS_180 VSS_181 VSS_182 VSS_183 VSS_184 VSS_185 VSS_186 VSS_187 VSS_188 VSS_189 VSS_190 VSS_191 VSS_192 VSS_193 VSS_194 VSS_195 VSS_196 VSS_197 VSS_198 VSS_199 VSS_200 VSS_201 VSS_202 VSS_203 VSS_204 VSS_205 VSS_206 VSS_207 VSS_208 VSS_209 VSS_210 VSS_211 VSS_212 VSS_213 VSS_214 VSS_215 VSS_216 VSS_217 VSS_218 VSS_219 VSS_220 VSS_221 VSS_222 VSS_223 VSS_224 VSS_225 VSS_226 VSS_227 VSS_228 VSS_229 VSS_230

T2

VSS_231

T3

VSS_232 VSS_233 VSS_234

T4

VSS_235

T5

VSS_236

T7

VSS_237

T8

VSS_238

T9

VSS_239 VSS_240 VSS_241 VSS_242 VSS_243

CFL-H_BG A1440

@

CFL-H

7 OF 13

VSS_244 VSS_245 VSS_246 VSS_247 VSS_248 VSS_249 VSS_250 VSS_251 VSS_252 VSS_253 VSS_254 VSS_255 VSS_256 VSS_257 VSS_258 VSS_259 VSS_260 VSS_261 VSS_262 VSS_263 VSS_264 VSS_265 VSS_266 VSS_267 VSS_268 VSS_269 VSS_270 VSS_271 VSS_272 VSS_273 VSS_274 VSS_275 VSS_276 VSS_277 VSS_278 VSS_279 VSS_280 VSS_281 VSS_282 VSS_283 VSS_284 VSS_285 VSS_286 VSS_287 VSS_288 VSS_289 VSS_290 VSS_291 VSS_292 VSS_293 VSS_294 VSS_295 VSS_296 VSS_297 VSS_298 VSS_299 VSS_300 VSS_301 VSS_302 VSS_303 VSS_304 VSS_305 VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 VSS_312 VSS_313 VSS_314 VSS_315 VSS_316 VSS_317 VSS_318 VSS_319 VSS_320 VSS_321 VSS_322 VSS_323 VSS_324

BJ15 BJ18 BJ22 BJ25 BJ29 BJ30 BJ31 BJ32 BJ33 BJ34 BJ35 BJ36 BK13 BK14 BK15 BK18 BK22 BK25 BK29 BK6 BL13 BL14 BL18 BL19 BL20 BL21 BL22 BL29 BL33 BL35 BL38 BL6 BM11 BM12 BM13 BM14 BM18 BM2 BM21 BM22 BM23 BM24 BM25 BM26 BM27 BM28 BM29 BM3 BM33 BM35 BM38 BM5 BM6 BM7 BM8 BM9 BN12 BN14 BN18 BN19 BN2 BN20 BN21 BN24 BN29 BN30 BN31 BN34 P38 P6 R12 R29 AY14 BD38 R30 T1 T10 T11 T12 T13 T14

BN4

BN7 BP12 BP14 BP18 BP21 BP24 BP25 BP26 BP29 BP33 BP34

BP7 BR12 BR14 BR18 BR21 BR24 BR25 BR26 BR29 BR34 BR36

BR7

BT12 BT14 BT18 BT21 BT24 BT26 BT29 BT32

BT5

C11

C13

C15

C17

C19

C21

C23

C25

C27

C29

C31

C37

D10

D12

D14

D16

D18

D20

D22

D24

D26

D28

D30

D33

E34

E35

E38

N33

N34

P12

P37

M14

M6

F11 F13

UC1H

VSS_325 VSS_326 VSS_327 VSS_328 VSS_329 VSS_330 VSS_331 VSS_332 VSS_333 VSS_334 VSS_335 VSS_336 VSS_337 VSS_338 VSS_339 VSS_340 VSS_341 VSS_342 VSS_343 VSS_344 VSS_345 VSS_346 VSS_347 VSS_348 VSS_349 VSS_350 VSS_351 VSS_352 VSS_353 VSS_354 VSS_355 VSS_356 VSS_357 VSS_358 VSS_359 VSS_360 VSS_361 VSS_362 VSS_363 VSS_364 VSS_365 VSS_366 VSS_367 VSS_368 VSS_369

C5

VSS_370

C8

VSS_371

C9

VSS_372 VSS_373 VSS_374 VSS_375 VSS_376 VSS_377 VSS_378 VSS_379 VSS_380 VSS_381 VSS_382

D3

VSS_383 VSS_384 VSS_385

D6

VSS_386

D9

VSS_387 VSS_388 VSS_389 VSS_390

E4

VSS_391

E9

VSS_392

N3

VSS_393 VSS_394 VSS_395

N4

VSS_396

N5

VSS_397

N6

VSS_398

N7

VSS_399

N8

VSS_400

N9

VSS_401 VSS_402 VSS_403 VSS_404 VSS_405

N1

VSS_406 VSS_407 VSS_408

CFL-H_BG A1440

@

CFL-H

VSS_409 VSS_410 VSS_411 VSS_412 VSS_413 VSS_414 VSS_415 VSS_416 VSS_417 VSS_418 VSS_419 VSS_420 VSS_421 VSS_422 VSS_423 VSS_424 VSS_425 VSS_426 VSS_427 VSS_428 VSS_429 VSS_430 VSS_431 VSS_432 VSS_433 VSS_434 VSS_435 VSS_436 VSS_437 VSS_438 VSS_439 VSS_440 VSS_441 VSS_442 VSS_443 VSS_444 VSS_445 VSS_446 VSS_447 VSS_448 VSS_449 VSS_450 VSS_451 VSS_452 VSS_453 VSS_454 VSS_455 VSS_456 VSS_457 VSS_458 VSS_459 VSS_460 VSS_461 VSS_462 VSS_463 VSS_464 VSS_465 VSS_466 VSS_467 VSS_468 VSS_469 VSS_470 VSS_471 VSS_472 VSS_473 VSS_474 VSS_475 VSS_476 VSS_477 VSS_478 VSS_479

VSS_A34

VSS_B37

VSS_BR38

VSS_BT3 VSS_BT35 VSS_BT36

VSS_BT4

8 OF 13

VSS_D38

VSS_A3

VSS_A4 VSS_B3

VSS_C2

F15 F17 F19 F2 F21 F23 F25 F27 F29 F3 F31 F36 F4 F5 F8 F9 G10 G12 G14 G16 G18 G20 G22 G23 G24 G26 G28 G4 G5 G6 G8 G9 H11 H12 H18 H22 H25 H32 H35 J10 J18 J22 J25 J32 J33 J36 J4 J7 K1 K10 K11 K2 K3 K38 K4 K5 K7 K8 K9 L29 L30 L33 L34 M12 M13 N10 N11 N12 N2 BT8 BR9

A3 A34 A4 B3 B37 BR38 BT3 BT35 BT36 BT4 C2 D38

Impedance Spectrum Tool Trigger

PCH_TRIGO UT_R<21> CPU_TRIGO UT_R<21>

1 2

RC26 30 _0402_5%

TC7@

IST_TRIG

TC8@

TC9@ TC10@

TC11@ TC12@

PCH_TRIGO UT_R CPU_TRIGO UT

BR1 BT2

BN35

H24

BN33

BL34

N29

R14 AE29 AA14 AP29 AP14

H23

C30

BR35 BR31 BH30

J24

A36

A37

J23

F30

E30

B30

E2 E3 E1 D1

G3

J3

UC1M

RSVD_TP5 IST_TRIG RSVD_TP4 RSVD_TP3

RSVD_TP1 RSVD_TP2

RSVD15

RSVD28 RSVD27 RSVD14 RSVD13

RSVD30 RSVD31 RSVD2 RSVD1 RSVD5 RSVD4 VSS_A36

VSS_A37

PROC_TRIGIN PROC_TRIGOUT

RSVD24

RSVD23

RSVD7 RSVD21

RSVD26 RSVD29

RSVD19 RSVD18 RSVD9

CFL-H_BG A1440

@

CFL-H

13 OF 13

BK28

RSVD11

BJ28

RSVD10

BL31

RSVD12

AJ8

RSVD3

G13

RSVD25

C38

RSVD22

C1

RSVD20

BR2

RSVD17

BP1

RSVD16

B38

RSVD8

B2

RSVD6

Add for Corner NCTF testing

TC13 @ TC14 @ TC15 @ TC16 @ TC17 @ TC18 @

4 4

Security Classification

2017/10/ 30 2018/10 /30

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

2017/10/ 30 2018/10 /30

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

CFL-H(8/8)GND/RSVD

Size Document Number Re v

Custom

EH5VF M/B LA-H501P

Date : Sheet o f

D

Date : Sheet o f

13 1 01Friday, February 22, 201 9

E

1A

A

DMI_CTX_P RX_N0<9> DMI_CTX_P RX_P0< 9>

DMI_CRX_P TX_N0<9>

DMI_CRX_P TX_P0< 9>

DMI_CTX_P RX_N1<9> DMI_CTX_P RX_P1< 9>

DMI_CRX_P TX_N1<9>

DMI_CRX_P TX_P1< 9>

DMI_CTX_P RX_N2<9> DMI_CTX_P RX_P2< 9>

1 1

The 30 HSIO lanes on PCH-H supports the following configurations:

1. Up to 24 PCIe* Lanes

— A maximum of 16 PCIe* Ports (or devices) can be enabled

‧‧‧‧

When a GbE Port is enabled, the maximum number of PCIe* Ports (or devices) that can be enabled reduces based off the following: Max PCIe* Ports (or devices) = 16 - GbE (0 or 1) — PCIe* Lanes 1-4 (PCIe* Controller #1), 5-8 (PCIe* Controller #2), 9-12 (PCIe* Controller #3), 13-16 (PCIe* Controller #4), 17-20 (PCIe* Controller #5), and 21-24 (PCIe* Controller #6) can be individually configured

2. Up to 6 SATA Lanes — A maximum of 6 SATA Ports (or devices) can be enabled — SATA Lane 0 has the flexibility to be mapped to Flex I/O Lane 16 or 18 — SATA Lane 1 has the flexibility to be mapped to Flex I/O Lane 17 or 19

3. Up to 10 USB 3.1 Lanes — A maximum of 10 USB 3.1 Ports (or devices) can be enabled

4. Up to 4 GbE Lanes — A maximum of 1 GbE Port (or device) can be enabled

5. Supports up to 3 Remapped (IntelR Rapid Storage Technology) PCIe* storage devices — x2 and x4 PCIe* NVMe SSD — x2 IntelR Optane? Memory Device — See the “ PC I Express* (PCIe*)” chapter f or the P CH PCI e* Controllers,configurations , and lanes that can be used for IntelR Rapid Storage Technology PCIe* storage support

6. For unused SATA/PCIe* Combo Lanes, Flex I/O Lanes that can be configured as PCIe* or SATA, the lanes must be statically assigned to SATA or PCIe* via the SATA/PCIe Combo Port Soft Straps discussed in the SPI Programming Guide and through the IntelR Flash Image Tool (FIT) tool.

2 2

3 3

DMI_CRX_P TX_N2<9>

DMI_CRX_P TX_P2< 9>

DMI_CTX_P RX_N3<9> DMI_CTX_P RX_P3< 9>

DMI_CRX_P TX_N3<9>

DMI_CRX_P TX_P3< 9>

B

DMI_CTX_P RX_N0

DMI_CTX_P RX_P0 DMI_CRX_P TX_N0 DMI_CRX_P TX_P0

DMI_CTX_P RX_N1

DMI_CTX_P RX_P1 DMI_CRX_P TX_N1 DMI_CRX_P TX_P1

DMI_CTX_P RX_N2

DMI_CTX_P RX_P2 DMI_CRX_P TX_N2 DMI_CRX_P TX_P2

DMI_CTX_P RX_N3

DMI_CTX_P RX_P3 DMI_CRX_P TX_N3 DMI_CRX_P TX_P3

UH1B

K34

DMI0_RXN

J35

DMI0_RXP

C33

DMI0_TXN

B33

DMI0_TXP

G33

DMI1_RXN

F34

DMI1_RXP

C32

DMI1_TXN

B32

DMI1_TXP

K32

DMI2_RXN

J32

DMI2_RXP

C31

DMI2_TXN

B31

DMI2_TXP

G30

DMI3_RXN

F30

DMI3_RXP

C29

DMI3_TXN

B29

DMI3_TXP

A25

RSVD

B25

RSVD

P24

RSVD

R24

RSVD

C26

RSVD

B26

RSVD

F26

RSVD

G26

RSVD

B27

RSVD

C27

RSVD

L26

RSVD

M26

RSVD

D29

RSVD

E28

RSVD

K29

RSVD

M29

RSVD

G17

PCIE1_RXN/USB31_7_RXN

F16

PCIE1_RXP/USB31_7_RXP

A17

PCIE1_TXN/USB31_7_TXN

B17

PCIE1_TXP/USB31_7_TXP

R21

PCIE2_RXN/USB31_8_RXN

P21

PCIE2_RXP/USB31_8_RXP

B18

PCIE2_TXN/USB31_8_TXN

C18

PCIE2_TXP/USB31_8_TXP

K18

PCIE3_RXN/USB31_9_RXN

J18

PCIE3_RXP/USB31_9_RXP

B19

PCIE3_TXN/USB31_9_TXN

C19

PCIE3_TXP/USB31_9_TXP

N18

PCIE4_RXN/USB31_10_RXN

R18

PCIE4_RXP/USB31_10_RXP

D20

PCIE4_TXN/USB31_10_TXN

C20

PCIE4_TXP/USB31_10_TXP

F20

PCIE5_RXN

G20

PCIE5_RXP

B21

PCIE5_TXN

A22

PCIE5_TXP

K21

PCIE6_RXN

J21

PCIE6_RXP

D21

PCIE6_TXN

C21

PCIE6_TXP

B23

PCIE7_TXP

C23

PCIE7_TXN

J24

PCIE7_RXP

L24

PCIE7_RXN

F24

PCIE8_RXN

G24

PCIE8_RXP

B24

PCIE8_TXN

C24

PCIE8_TXP

CNP-H_BG A874

@

C

CNP-H

GPP_E9/USB2_OC0# GPP_E10/USB2_OC1# GPP_E11/USB2_OC2# GPP_E12/USB2_OC3# GPP_F15/USB2_OC4# GPP_F16/USB2_OC5# GPP_F17/USB2_OC6# GPP_F18/USB2_OC7#

USB2_VBUSSENSE

2 OF 13

USB2N_1 USB2P_1 USB2N_2 USB2P_2 USB2N_3 USB2P_3 USB2N_4 USB2P_4 USB2N_5 USB2P_5 USB2N_6 USB2P_6 USB2N_7 USB2P_7 USB2N_8 USB2P_8 USB2N_9

USB2P_9 USB2N_10 USB2P_10 USB2N_11 USB2P_11 USB2N_12 USB2P_12 USB2N_13 USB2P_13 USB2N_14 USB2P_14

USB2_COMP

RSVD1

USB2_ID

GPD7

PCIE24_TXP PCIE24_TXN PCIE24_RXP PCIE24_RXN

PCIE23_TXP PCIE23_TXN PCIE23_RXP PCIE23_RXN

PCIE22_TXP PCIE22_TXN PCIE22_RXP PCIE22_RXN

PCIE21_TXP PCIE21_TXN PCIE21_RXP PCIE21_RXN

D

USB20_N 1

J3

USB20_P 1

J2

USB20_N 2

N13

USB20_P 2

N15

USB20_N 3

K4

USB20_P 3

K3

USB20_N 4

M10

USB20_P 4

L9

USB20_N 5

M1

USB20_P 5

L2

USB20_N 6

K7

USB20_P 6

K6 L4 L3

USB20_N 8

G4

USB20_P 8

G5 M6 N8 H3 H2 R10 P9 G1 G2 N3 N2

USB20_N 14

E5

USB20_P 14

F6

USB_OC0 #

AH36

USB_OC1 #

AL40 AJ44 AL41 AV47 AR35 AR37 AV43

USB2_RC OMP

F4

USB2_VB US_SENSE

F3 U13

USB2_ID

G3

GPD_7

BE41

G45 G46 Y41 Y40 G48 G49 W44 W43 H48 H47 U41 U40 F46 G47 R44 T43

v1.0

Re

USB20_N 1 <71> USB20_P 1 <71> USB20_N 2 <43> USB20_P 2 <43> USB20_N 3 <72> USB20_P 3 <72> USB20_N 4 <73> USB20_P 4 <73> USB20_N 5 <38> USB20_P 5 <38> USB20_N 6 <38> USB20_P 6 <38>

USB20_N 8 <66> USB20_P 8 <66>

USB20_N 14 <52> USB20_P 14 <52>

USB_OC0 # <43> USB_OC1 # <71>

1 2

RH4 113_0402 _1%

1 2

RH5 0_0402_5 %@

1 2

RH6 0_0402_5 %@

PCIE_PTX_ DRX_P24 <68> PCIE_PTX_ DRX_N24 < 68>

PCIE_PRX_ DTX_P24 <68> PCIE_PRX_ DTX_N24 < 68> PCIE_PTX_ DRX_P23 <68> PCIE_PTX_ DRX_N23 < 68>

PCIE_PRX_ DTX_P23 <68> PCIE_PRX_ DTX_N23 < 68> PCIE_PTX_ DRX_P22 <68> PCIE_PTX_ DRX_N22 < 68>

PCIE_PRX_ DTX_P22 <68> PCIE_PRX_ DTX_N22 < 68> PCIE_PTX_ DRX_P21 <68> PCIE_PTX_ DRX_N21 < 68>

PCIE_PRX_ DTX_P21 <68> PCIE_PRX_ DTX_N21 < 68>

USB3 MB

PE C

TY

USB3 MB

USB2 (SUB/B)

Camera

TS

FingerPrint

USB_OC0 # USB_OC1 #

BT

For CNVI follow 571906_CNL_PCH_TA_WW11.pdf

STRAP

E

1 2

RH200 10K_ 0402_5%

1 2

RH201 10K_ 0402_5%

+3VALW

12

GPD_7

12

X'tal Input: High: Differential Low: Single ended

RH3 10K_040 2_5%

RH7 10K_040 2_5%

@

+3VALW

4 4

Security Classification

2017/10/ 30 2018/10 /30

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

2017/10/ 30 2018/10 /30

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

PCH(1/8)DMI/PCIE/USB2

Size Document Number Re v

Custom

EH5VF M/B LA-H501P

Date : Sheet o f

D

Date : Sheet o f

14 1 01Friday, February 22, 201 9

E

1A

A

B

C

D

E

PCH-H XTAL_IN/OUT POR is 24MHz for 571697_CNL_MOW_WW16_2017.pdf

RH8 1M_0402_ 5%

YH1 24MHZ_1 8PF_7R240000 01

1 1

2 2

3

33P_0402_50V8J

3

CH5

10P_0402_50V8J

1

32.768KH Z_9PF_X1A000 141000200

CH7

2

Trace Space: 15 mil Max Trace Length: 1000 mil

XTAL_24 M_PCH_OUT

NC

2

XTAL_24 M_PCH_IN

1

1 2

NC

4

1 2

RH12 10M_ 0402_5%

YH2

1 2

EMI@

RH11 33_ 0402_1%

1 2

EMI@

RH9 33_0402_1 %

1

18P_0402_50V8J

CH6

PCH_RTC X1

PCH_RTC X2

XTAL_24 M_PCH_OUT_R

XTAL_24 M_PCH_IN_R

PCH_CPU _24M_CLK_P<10> PCH_CPU _24M_CLK_N<10>

PCH_CPU _BCLK_P<10> PCH_CPU _BCLK_N<10> PCH_CPU _PCIBCLK_P <10>

1 2

XCLK_BIASREF (PDG) Trace Width/Space: 15mil /15 mil Max Trace Length: 1000 mil 8/24

RH10 60 .4_0402_1%

WLAN _CLKREQ#<52> SSD1_CL KREQ#<68> SSD2_CL KREQ#<68>

remove no use srcclkreq

10P_0402_50V8J

1

CH8

2

remove TP as C5PRH

PCH_CPU _24M_CLK_P PCH_CPU _24M_CLK_N

PCH_CPU _BCLK_P PCH_CPU _BCLK_N

XTAL_24 M_PCH_OUT_R XTAL_24 M_PCH_IN_R

XCLK_BIAS REF

PCH_RTC X1 PCH_RTC X2

LAN_CLK REQ#<51>

VGA_CLK REQ#

use same part w C5MMH

+3VS

12

A

LAN_CLK REQ#

WLAN _CLKREQ# SSD1_CL KREQ# SSD2_CL KREQ#

CNV_BRI_P TX_DRX

GPP_J9

CNV_RGI_P TX_DRX

VGA_CLK REQ# <2 7>

STRAP

AW13

BE9 BF8 BF9

BG8

remove SD signal from PCH

remove CPU_C10_GATE#

CNV_BRI_P TX_DRX<52>

CNV_BRI_P RX_DTX<52>

CNV_RGI_P TX_DRX<52>

CNV_RGI_P RX_DTX<52>

+1.8VALW _PRIM

1 2

RH181 20K_0402 _1%CNVI@

1 2

571391_CFL_H_PDG_Rev0p71 To avoid floating input at the I/O pin BRI_RSP and RGI_RSP it is recommended to add a weak pull up resistor to the SoC pin with a recommended value of 20K ohm.

B

RH182 20K_0402 _1%CNVI@

CNV_BRI_P TX_DRX CNV_BRI_P RX_DTX CNV_RGI_P TX_DRX CNV_RGI_P RX_DTX

GPP_J9

CNV_BRI_P RX_DTX

CNV_RGI_P RX_DTX

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

BE8

BD8

AV13

AP3 AP2 AN4

AM7

AV6 AY3

AR13

AV7 AW3 AT10

AV4

AY2

BA4

AV3 AW2

AU9

2017/10/ 30 2018/10 /30

C

1 2

RH204 10K_ 0402_5%

1 2

RH205 10K_ 0402_5%

1 2

RH206 10K_ 0402_5%

1 2

RH207 10K_ 0402_5%

1 2

RH220 10K_ 0402_5%

For DDX03 R02

+1.8VALW _PRIM

3 3

+1.8VALW _PRIM

4 4

XTAL Frequency Select

1 2

RH15 4.7K_0 402_5%

This signal has a weak internal pull-down 20K. 0 = 38.4/19.2MHz XTAL frequency selected. 1 = 24MHz XTAL frequency selected. (DDX03) Notes:

1. The internal pull-down is disabled after RSMRST# de-asserts.

2. This signal is in the primary well.

VCCPSPI Select

@

1 2

RH21 4.7K_0 402_5%

The signal has a weak internal pull-down 20K 0 = VCCPSPI is connected to 3.3V rail 1 = VCCPSPI is connected to 1.8V rail Note: If VCCPSPI is connected to 1.8V rail, this pin

strap must be a ‘ 1’ fo r the proper functionality of the SPI (Flash) I/Os

M.2 CNV Mode Select

RH22 10K_040 2_5%

RH23 10K_040 2_5%@

An external pull-up or pull-down is required. 0 = Integrated CNVi enable. 1 = Integrated CNVi disable.

Pulled down by CRF CNVi RGI_DT pin

UH1G

BE33

GPP_A16/CLKOUT_48

D7

CLKOUT_CPUNSSC_P

C6

CLKOUT_CPUNSSC#

B8

CLKOUT_CPUBCLK_P

C8

CLKOUT_CPUBCLK#

U9

XTAL_OUT

U10

XTAL_IN

T3

XCLK_BIASREF

BA49

RTCX1

BA48

RTCX2

BF31

GPP_B5/SRCCLKREQ0#

BE31

GPP_B6/SRCCLKREQ1#

AR32

GPP_B7/SRCCLKREQ2#

BB30

GPP_B8/SRCCLKREQ3#

BA30

GPP_B9/SRCCLKREQ4#

AN29

GPP_B10/SRCCLKREQ5#

AE47

GPP_H0/SRCCLKREQ6#

AC48

GPP_H1/SRCCLKREQ7#

AE41

GPP_H2/SRCCLKREQ8#

AF48

GPP_H3/SRCCLKREQ9#

AC41

GPP_H4/SRCCLKREQ10#

AC39

GPP_H5/SRCCLKREQ11#

AE39

GPP_H6/SRCCLKREQ12#

AB48

GPP_H7/SRCCLKREQ13#

AC44

GPP_H8/SRCCLKREQ14#

AC43

GPP_H9/SRCCLKREQ15#

V2

CLKOUT_PCIE_N15

V3

CLKOUT_PCIE_P15

T2

CLKOUT_PCIE_N14

T1

CLKOUT_PCIE_P14

AA1

CLKOUT_PCIE_N13

Y2

CLKOUT_PCIE_P13

AC7

CLKOUT_PCIE_N12

AC6

CLKOUT_PCIE_P12

CNP-H_BG A874

@

UH1M

GPP_G0/SD_CMD GPP_G1/SD_DATA0 GPP_G2/SD_DATA1 GPP_G3/SD_DATA2 GPP_G4/SD_DATA3 GPP_G5/SD_CD# GPP_G6/SD_CLK GPP_G7/SD_WP

GPP_I11/M2_SKT2_CFG0 GPP_I12/M2_SKT2_CFG1 GPP_I13/M2_SKT2_CFG2 GPP_I14/M2_SKT2_CFG3

GPP_J0/CNV_PA_BLANKING GPP_J1/CPU_C10_GATE# GPP_J11/A4WP_PRESENT GPP_J10 GPP_J_2 GPP_J_3 GPP_J4/CNV_BRI_DT/UART0B_RTS# GPP_J5/CNV_BRI_RSP/UART0B_RXD GPP_J6/CNV_RGI_DT/UART0B_TXD GPP_J7/CNV_RGI_RSP/UART0B_CTS# GPP_J8/CNV_MFUART2_RXD GPP_J9/CNV_MFUART2_TXD

CNP-H_BG A874

@

Compal Secret Data

CNP-H

CLKOUT_ITPXDP#

CLKOUT_ITPXDP_P

CLKOUT_CPUPCIBCLK#

CLKOUT_CPUPCIBCLK_P

CLKOUT_PCIE_N0 CLKOUT_PCIE_P0

CLKOUT_PCIE_N1 CLKOUT_PCIE_P1

CLKOUT_PCIE_N2 CLKOUT_PCIE_P2

CLKOUT_PCIE_N3 CLKOUT_PCIE_P3

CLKOUT_PCIE_N4 CLKOUT_PCIE_P4

CLKOUT_PCIE_N5 CLKOUT_PCIE_P5

CLKOUT_PCIE_N6 CLKOUT_PCIE_P6

CLKOUT_PCIE_N7 CLKOUT_PCIE_P7

CLKOUT_PCIE_N8 CLKOUT_PCIE_P8

CLKOUT_PCIE_N9 CLKOUT_PCIE_P9

CLKOUT_PCIE_N10 CLKOUT_PCIE_P10

CLKOUT_PCIE_N11 CLKOUT_PCIE_P11

7 OF 13

CNP-H

3.3V

1.8V

13 OF 13

Deciphered Date

Y3 Y4

B6 A6

AJ6 AJ7

AH9 AH10

AE14 AE15

AE6 AE7

AC2 AC3

AB2 AB3

W4 W3

W7 W6

AC14 AC15

U2 U3

AC9 AC11

AE9 AE11

CLKIN_XTAL

GPPJ_RCOMP_1P81 GPPJ_RCOMP_1P82 GPPJ_RCOMP_1P83

R6

v1.0

Re

CNV_WR_CLKN CNV_WR_CLKP

CNV_WR_D0N CNV_WR_D0P CNV_WR_D1N CNV_WR_D1P

CNV_WT_CLKN CNV_WT_CLKP

CNV_WT_D0N CNV_WT_D0P CNV_WT_D1N CNV_WT_D1P

CNV_WT_RCOMP

PCIE_RCOMPN

PCIE_RCOMPP SD_1P8_RCOMP SD_3P3_RCOMP

RSVD2 RSVD3

RSVD1

TH2@ TH3@

PCH_CPU _PCIBCLK_N <10>

CLK_PEG_VGA# <27> CLK_PEG_VGA <27>

CLK_PCIE_ LAN# <51>

CLK_PCIE_ LAN <51>

CLK_PCIE_ WLAN# <52 >

CLK_PCIE_ WLAN <52>

CLK_PCIE_ NGFF1# <68> CLK_PCIE_ NGFF1 < 68>

CLK_PCIE_ NGFF2# <68> CLK_PCIE_ NGFF2 < 68>

REFCLK_ CNV <52>

12

RH14

10K_040 2_5%

CLK_CNV _PRX_DTX_N

BD4

CLK_CNV _PRX_DTX_P

BE3

CNV_PRX _DTX_N0

BB3

CNV_PRX _DTX_P0

BB4

CNV_PRX _DTX_N1

BA3

CNV_PRX _DTX_P1

BA2

CLK_CNV _PTX_DRX_N

BC5

CLK_CNV _PTX_DRX_P

BB6

CNV_PTX _DRX_N0

BE6

CNV_PTX _DRX_P0

BD7

CNV_PTX _DRX_N1

BG6

CNV_PTX _DRX_P1

BF6

CNV_W T_RCOMP

BA1

PCIE_RCOM PN

B12

PCIE_RCOM PP

A13

SD_RCOM P_1P8

BE5

SD_RCOM P_3P3

BE4 BD1

GPPJ_RC OMP_1P8

BE1 BE2

Y35 Y36

BC1 AL35

TP

Re

v1.0

D

RH16

1 2

RH17 10 0_0402_1%

1 2

RH18 20 0_0402_1%

1 2

RH19 20 0_0402_1%

1 2

RH20 20 0_0402_1%

#571483_CFL_H_RVP_CRB_TDK_Rev0p5 Recommend external test point

TH4@

Title

Size Document Number Re v

Custom

Date : Sheet o f

150_040 2_1%

Compal Electronics, Inc.

PCH(2/8)CLK/CNVI/SD

EH5VF M/B LA-H501P

DGPU

GLAN

NGFF WL+BT(KEY E)

M2 SSD1

M2 SSD2

CLK_CNV _PRX_DTX_N <52> CLK_CNV _PRX_DTX_P <52>

CNV_PRX _DTX_N0 <52> CNV_PRX _DTX_P0 <52> CNV_PRX _DTX_N1 <52> CNV_PRX _DTX_P1 <52>

CLK_CNV _PTX_DRX_N <52> CLK_CNV _PTX_DRX_P <52>

CNV_PTX _DRX_N0 <52>

CNV_PTX _DRX_P0 <52>

CNV_PTX _DRX_N1 <52>

CNV_PTX _DRX_P1 <52>

checked CRB

15 1 01Friday, February 22, 201 9

E

1A

A

UH1E

no follow naming

can remove if no use DP 08/1 8

remove PCH DP SCLK/SDATA

DDP[B..F]CTRLDATA This signal has a weak internal Pull-down. 0 = Port B~D is not detected. 1 = Port B,C,D is detected. (Default) Notes:

1. The internal Pull-down is disabled after PCH_PWROK de-asserts.

2. This signal is in the primary well.

HDMI_HPD_ PCH<2 7,40>

EDP_HPD<38>

EC_PME#<51,58>

1 2

RH24 0_04 02_5%

EC_PME# _R

@

CRB connect GND

1 2

RH186 0_0402_5 %@

PCH_SPI_S I_R<66>

PCH_SPI_S O_R<66>

PCH_SPI_C LK_R<66>

* wait confirm CG7 PDG P348 quad mode support PH1K

+3VALW

1 1

+3VALW

CRB PU 20k #571182_CFL_PCH_ EDS_Rev1.0 recomme nd 100k

#571391_CFL_H_PDG_Rev0p71

RH25 1K_040 2_5%

RH26 1K_040 2_5%

RH27 1K_040 2_5%

RH29 10 0K_0402_5%

#571182_CNL_PCH_H_EDS_V1_Rev0.7 External pull-up is required. Recommend 100K if pulled up to 3.3V or 75K if pulled up to 1.8V. 571007_CFL_MOW_Archive_WW22_2017 STUFF R on GPP_H15

PCH_SPI_C LK_R

12

RH195 100K_020 1_5%@

1 2

PCH_SPI_IO2

PCH_SPI_IO3

PCH_SPI_S I_R

GPP_H15

STRAP

RH258 0_04 02_5%NTPM@

1 2

RH259 0_04 02_5%NTPM@

1 2

RH260 0_04 02_5%NTPM@

PCH_SPI_C S#2<6 6>

RH258

TPM@

4.99_040 2_1%

SD034499B80

TH6 @

1 2

PCH_SPI_S I PCH_SPI_S O PCH_SPI_C S#0 PCH_SPI_C LK

PCH_SPI_IO2 PCH_SPI_IO3

RH259

TPM@

4.99_040 2_1%

SD034499B80

AT6

AN10

AP9

AL15

AN6

CNP-H_BG A874

@

BE36

R15 R13

AL37

AN35

AU41 BA45

AY47 AW47 AW48

AY48

BA46

AT40

BE19

BF19

BF18

BE18

BC17

BD17

CNP-H_BG A874

@

RH260

TPM@

4.99_040 2_1%

SD034499B80

GPP_I0/DDPB_HPD0/DISP_MISC0 GPP_I1/DDPC_HPD1/DISP_MISC1 GPP_I2/DDPD_HPD2/DISP_MISC2 GPP_I3/DDPF_HPD3/DISP_MISC3

GPP_I4/EDP_HPD/DISP_MISC4

UH1A

GPP_A11/PME#/SD_VDD2_PWR_EN#

RSVD2 RSVD1

VSS TP

SPI0_MOSI SPI0_MISO SPI0_CS0# SPI0_CLK SPI0_CS1#

SPI0_IO2 SPI0_IO3 SPI0_CS2#

GPP_D1/SPI1_CLK/SBK1_BK1 GPP_D0/SPI1_CS#/SBK0_BK0 GPP_D3/SPI1_MOSI/SBK3_BK3 GPP_D2/SPI1_MISO/SBK2_BK2 GPP_D22/SPI1_IO3 GPP_D21/SPI1_IO2

CNP-H

5 OF 13

CNP-H

GPP_K15/GSXSRESET#

GPP_H18/SML4ALERT#

GPP_H15/SML3ALERT#

GPP_H12/SML2ALERT#

1 OF 13

GPP_I5/DDPB_CTRLCLK

GPP_I6/DDPB_CTRLDATA

GPP_I7/DDPC_CTRLCLK

GPP_I8/DDPC_CTRLDATA

GPP_I9/DDPD_CTRLCLK

GPP_I10/DDPD_CTRLDATA

GPP_F23/DDPF_CTRLDATA

GPP_F22/DDPF_CTRLCLK

GPP_F14/PS_ON#

GPP_K23/IMGCLKOUT1 GPP_K22/IMGCLKOUT0

GPP_H23/TIME_SYNC0

GPP_B13/PLTRST#

GPP_K16/GSXCLK

GPP_K12/GSXDOUT

GPP_K13/GSXSLOAD

GPP_K14/GSXDIN

GPP_E3/CPU_GP0 GPP_E7/CPU_GP1 GPP_B3/CPU_GP2 GPP_B4/CPU_GP3

GPP_H17/SML4DATA

GPP_H16/SML4CLK

GPP_H14/SML3DATA

GPP_H13/SML3CLK

GPP_H11/SML2DATA

GPP_H10/SML2CLK

INTRUDER#

Rev1.0

GPP_K21 GPP_K20

AL13 AR8 AN13 AL10 AL9 AR3 AN40 AT49

AP41

M45 L48 T45 T46 AJ47

R

AV29

Y47 Y46 Y48 W46 AA45

AL47 AM45 BF32 BC33

AE44 AJ46 AE43 AC47 AD48 AF47 AB47 AD47 AE48

BB44

remove CIO_PLUG_EVENT#

v1.0

e

PLT_RST #

TP_INT#

GPP_H15

GPP_H12

SM_INTRUD ER#

RVP: 330K A 1 M pull-up is used on the customer reference board (CRB). This is needed to reduce leakage from Coin Cell Battery in G3 state.

PLT_RST # <27,58,6 6>

GPIO Serial Expander (GSX) is the capability provided by the PCH to expand the GPIOs on a platform that needs more GPIOs than the ones provided by the PCH.

12

DH1 RB751V-4 0_SOD323-2

GPP_H12 <19>

EC_TP_INT# <5 8,63>

+RTCVCC

12

RH301M_0402 _5%

intel critical net recommend

1 2

RH198 100K_020 1_5%

PLT_RST #

1 2

CH9 100 P_0402_50V8J

XESD@

TP_INT#

RH28 10 0K_0402_5%

+3VS

12

intel critical net recommend

SPI ROM ( 16MByte )

PCH_SPI_C S#0

PCH_SPI_IO2_ 0_R

UH2

1 2 3 4

W25Q 128FVSIQ_SO8

XM

PCH_SPI_C LK_0_R

+3VALW

/CS DO(IO1) /WP(IO2) GND

/HOLD(IO3)

VCC

CLK

DI(IO0)

8 7 6 5

C P/N: SA0000B8400

XEMI@

1 2

RH33 0_0402_ 5%

XEMI@

CH12 68P_040 2_50V8J

CH10 0.1U_ 0201_10V6K

1 2

PCH_SPI_IO3_ 0_RPCH_SPI_S O_0_R PCH_SPI_C LK_0_R PCH_SPI_S I_0_R

1 2

PCH_SPI_S I_0_R PCH_SPI_S O_0_R PCH_SPI_IO3_ 0_R PCH_SPI_C LK_0_R

PCH_SPI_C S#0

RH107 33_0 402_1% RH108 33_0 402_1% RH109 33_0 402_1% RH110 33_0 402_1% RH111 33_0 402_1%

PCH PLTRST Buffer

+3VALW +3VS

1 2

@

RH31 4.7K_ 0402_5%

PLT_RST #

1 2 1 2 1 2 1 2 1 2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PCH_SPI_S I_R PCH_SPI_S O_R PCH_SPI_IO3 PCH_SPI_C LK_R PCH_SPI_IO2PCH_SPI_IO2_ 0_R

Compal Secret Data

2017/10/ 30 2018/10 /30

A

Compal Secret Data

Deciphered Date

1 2

RH32 0_ 0402_5%@

CH11

0.1U_020 1_10V6K

1 2

5

1

2

MC74VHC 1G08DFT2G_SC 70-5

UH3

IN1

VCC

4

OUT

IN2

GND

3

12

Compal Electronics, Inc.

Title

PCH(3/8)DDC/SPI

Size Document Number Re v

Custom

Date : Sheet o f

PLT_RST _BUF# <51,5 2,68>

RH199 100K_02 01_5%

@

EH5VF M/B LA-H501P

16 1 01Friday, February 22, 201 9

1A

A

USB3 MB

1 1

B3 Type C

US

USB3 MB

2 2

For Intel CLINK

M.2 SSD PCIE L1

3 3

GLAN

PCIE_PTX_ C_DRX_N14<51>

PCIE_PTX_ C_DRX_P14<51>

PCIE_PRX_DTX_N14<51> PCIE_PRX_DTX_P14<51>

CH3 .1U_0402_ 16V7K CH4 .1U_0402_ 16V7K

M.2 SSD PCIE L0

+3VALW

12

RH43

10K_040 2_5%

4 4

UMA@

DGPU_PR SNT#

12 12

TH10 @ TH11 @ TH12 @

PCIE_PTX_ DRX_P11<68> PCIE_PTX_ DRX_N11<68> PCIE_PRX_ DTX_P11<68> PCIE_PRX_ DTX_N11<68>

PCIE_PTX_ DRX_P12<68> PCIE_PTX_ DRX_N12<68> PCIE_PRX_ DTX_P12<68> PCIE_PRX_ DTX_N12<68>

USB3_PT X_DRX_N1<71> USB3_PT X_DRX_P1<71> USB3_PR X_DTX_N1<71> USB3_PR X_DTX_P1<71>

USB3_PT X_DRX_N2<42> USB3_PT X_DRX_P2<42> USB3_PR X_DTX_N2<42> USB3_PR X_DTX_P2<42>

USB3_PT X_DRX_P3<72> USB3_PT X_DRX_N3<72> USB3_PR X_DTX_P3<72> USB3_PR X_DTX_N3<72>

DGPU_PR SNT#

PCIE_PTX_ DRX_N14 PCIE_PTX_ DRX_P14

PCIE_PRX_ DTX_N14 PCIE_PRX_ DTX_P14

B

CL_CLK CL_DATA CL_RST#

UH1F

F9

USB31_1_TXN

F7

USB31_1_TXP

D11

USB31_1_RXN

C11

USB31_1_RXP

C3

USB31_2_TXN

D4

USB31_2_TXP

B9

USB31_2_RXN

C9

USB31_2_RXP

C17

USB31_6_TXN

C16

USB31_6_TXP

G14

USB31_6_RXN

F14

USB31_6_RXP

C15

USB31_5_TXN

B15

USB31_5_TXP

J13

USB31_5_RXN

K13

USB31_5_RXP

G12

USB31_3_TXP

F11

USB31_3_TXN

C10

USB31_3_RXP

B10

USB31_3_RXN

C14

USB31_4_TXP

B14

USB31_4_TXN

J15

USB31_4_RXP

K16

USB31_4_RXN

CNP-H_BG A874

@

UH1C

AR2

CL_CLK

AT5

CL_DATA

AU4

CL_RST#

P48

GPP_K8

V47

GPP_K9

V48

GPP_K10

W47

GPP_K11

L47

GPP_K0

L46

GPP_K1

U48

GPP_K2

U47

GPP_K3

N48

GPP_K4

N47

GPP_K5

P47

GPP_K6

R46

GPP_K7

C36

PCIE11_TXP/SATA0A_TXP

B36

PCIE11_TXN/SATA0A_TXN

F39

PCIE11_RXP/SATA0A_RXP

G38

PCIE11_RXN/SATA0A_RXN

AR42

GPP_F10/SATA_SCLOCK

AR48

GPP_F11/SATA_SLOAD

AU47

GPP_F13/SATA_SDATAOUT0

AU46

GPP_F12/SATA_SDATAOUT1

C39

PCIE14_TXN/SATA1B_TXN

D39

PCIE14_TXP/SATA1B_TXP

D46

PCIE14_RXN/SATA1B_RXN

C47

PCIE14_RXP/SATA1B_RXP

B38

PCIE13_TXN/SATA0B_TXN

C38

PCIE13_TXP/SATA0B_TXP

C45

PCIE13_RXN/SATA0B_RXN

C46

PCIE13_RXP/SATA0B_RXP

E37

PCIE12_TXP/SATA1A_TXP

D38

PCIE12_TXN/SATA1A_TXN

J41

PCIE12_RXP/SATA_1A_RXP

H42

PCIE12_RXN/SATA1A_RXN

B44

PCIE20_TXP/SATA7_TXP

A44

PCIE20_TXN/SATA7_TXN

R37

PCIE20_RXP/SATA7_RXP

R35

PCIE20_RXN/SATA7_RXN

D43

PCIE19_TXP/SATA6_TXP

C44

PCIE19_TXN/SATA6_TXN

N42

PCIE19_RXP/SATA6_RXP

M44

PCIE19_RXN/SATA6_RXN

CNP-H_BG A874

@

C

CNP-H

GPP_A1/LAD0/ESPI_IO0

1.8V

GPP_A2/LAD1/ESPI_IO1

(eSPI)

GPP_A3/LAD2/ESPI_IO2 GPP_A4/LAD3/ESPI_IO3

GPP_A5/LFRAME#/ESPI_CS0#

GPP_A6/SERIRQ/ESPI_CS1#

GPP_A7/PIRQA#/ESPI_ALERT0#

GPP_A0/RCIN#/ESPI_ALERT1#

GPP_A14/SUS_STAT#/ESPI_RESET#

GPP_A9/CLKOUT_LPC0/ESPI_CLK

GPP_A10/CLKOUT_LPC1

GPP_K19/SMI#

GPP_K18/NMI#

GPP_E6/SATA_DEVSLP2 GPP_E5/SATA_DEVSLP1 GPP_E4/SATA_DEVSLP0

GPP_F9/SATA_DEVSLP7 GPP_F8/SATA_DEVSLP6 GPP_F7/SATA_DEVSLP5 GPP_F6/SATA_DEVSLP4 GPP_F5/SATA_DEVSLP3

6 OF 13

CNP-H

PCIE9_RXN PCIE9_RXP

PCIE9_TXN PCIE9_TXP

PCIE10_RXN PCIE10_RXP PCIE10_TXN PCIE10_TXP

PCIE15_RXN/SATA2_RXN

PCIE15_RXP/SATA2_RXP

PCIE_15_SATA_2_TXN

PCIE15_TXP/SATA2_TXP

PCIE16_RXN/SATA3_RXN

PCIE16_RXP/SATA3_RXP

PCIE16_TXN/SATA3_TXN PCIE16_TXP/SATA3_TXP

PCIE17_RXN/SATA4_RXN

PCIE17_RXP/SATA4_RXP PCIE17_TXN/SATA4_TXN

PCIE17_TXP/SATA4_TXP

PCIE18_RXN/SATA5_RXN

PCIE18_RXP/SATA5_RXP

PCIE18_TXN/SATA5_TXN PCIE18_TXP/SATA5_TXP

GPP_E8/SATA_LED#

GPP_E0/SATAXPCIE0/SATAGP0 GPP_E1/SATAXPCIE1/SATAGP1 GPP_E2/SATAXPCIE2/SATAGP2

GPP_F0/SATAXPCIE3/SATAGP_3

GPP_F1/SATAXPCIE4/SATAGP4 GPP_F2/SATAXPCIE5/SATAGP5 GPP_F3/SATAXPCIE6/SATAGP6 GPP_F4/SATAXPCIE7/SATAGP7

GPP_F21/EDP_BKLTCTL

GPP_F20/EDP_BKLTEN

GPP_F19/EDP_VDDEN

THRMTRIP#

PECI

PM_SYNC

3 OF 13

PLTRST_CPU#

PM_DOWN

Rev1.0

Re

v1.0

BB39 AW37 AV37 BA38

BE38 AW35 BA36 BE39 BF38

BB36 BB34

T48 T47

AH40 AH35 AL48 AP47 AN37 AN46 AR47 AP48

G36 F36 C34 D34

K37 J37 C35 B35

F44 E45 B40 C40

L41 M40 B41 C41

K43 K44 A42 B42

P41 R40 C42 D42

AK48

AH41 AJ43 AK47 AN47

RH187 10K_0402_ 5%PBA@

AM46 AM43 AM47 AM48

AU48 AV46 AV44

AD3 AF2 AF3 AG5 AE2

#571391_CFL_H_PDG_Rev0p5

‧‧‧‧ ‧‧‧‧ ‧‧‧‧

* If DATA signals are entirely routed on MS, stuff the resistor with 15 Ohm.

LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3

LPC_FRA ME# TPM_SER IRQ LPC_PIRQA #

RCIN# ESPI_RST#

CLK_LPC

SSD_DEV SLP1

PCIE_PRX_ DTX_N9 PCIE_PRX_ DTX_P9 PCIE_PTX_ DRX_N9 PCIE_PTX_ DRX_P9

PCIE_PRX_ DTX_N10 PCIE_PRX_ DTX_P10 PCIE_PTX_ DRX_N10 PCIE_PTX_ DRX_P10

PCIE_PRX_ DTX_N15 PCIE_PRX_ DTX_P15 PCIE_PTX_ DRX_N15 PCIE_PTX_ DRX_P15

SATA_PR X_DTX_N4 SATA_PR X_DTX_P4 SATA_PT X_DRX_N4 SATA_PT X_DRX_P4

1 2

SATA_GP 5

PCH_BKL _PWM ENBKL

PCH_ENV DD

PCH_THE RMTRIP# PCH_PEC I

H_PM_SYNC H_PLTRS T_CPU# H_PM_DO WN_R

D

and eSPI data mismatched: <500 mils.

eSPI clock eSPI clock and eSPI chip select mismatched: <500 mils. eSPI signal maximum 9 Vias

LPC_AD0 <58> LPC_AD1 <58> LPC_AD2 <58> LPC_AD3 <58>

LPC_FRA ME# <58 > TPM_SER IRQ <58,66 >

1 2

RH261 0_04 02_5%@

RH35 22 _0402_5%

12

SSD_DEV SLP1 <6 8>

LPC Bus

LPC : +3.3V

OVRM_EN <36,58>

CLK_LPC _R < 58>

CONFIRM WITH SW

PCIE_PRX_ DTX_N9 <68> PCIE_PRX_ DTX_P9 <68> PCIE_PTX_ DRX_N9 <6 8>

PCIE_PTX_ DRX_P9 <68>

PCIE_PRX_ DTX_N10 <68 > PCIE_PRX_ DTX_P10 <68> PCIE_PTX_ DRX_N10 < 68>

PCIE_PTX_ DRX_P10 <68>

PCIE_PRX_DTX_N15 <52>

1 2

CH1.1U_0402 _16V7K

1 2

CH2.1U_0402 _16V7K

SATA_PR X_DTX_N4 < 67> SATA_PR X_DTX_P4 <67> SATA_PT X_DRX_N4 < 67>

SATA_PT X_DRX_P4 <67>

SATA_GP 1 <68>

PCIE_PRX_DTX_P15 <52> PCIE_PTX_ C_DRX_N15 <52>

PCIE_PTX_ C_DRX_P15 <52>

SATA_GP 1

M.2 SSD PCIE/SATA select pin

TH13@

CONFIRM WITH SW

PCH_BKL _PWM < 38> ENBKL <58> PCH_ENV DD <38>

1 2

RH40 620_0 402_5%

1 2

RH41 13_04 02_5%@

1 2

RH42 30 _0402_5%

#571391_CFL_H_PDG_Rev0p5.pdf

H_PECI H_PM_SYNC _R

check straps

TPM_SER IRQ

LPC_PIRQA #

M.2 SSD PCIE L3

M.2 SSD PCIE L2

HDD

RH39 10 K_0402_5%

PCH_THE RMTRIP#_R <10 >

H_PECI <10,58>

H_PM_SYNC _R <10> H_PLTRS T_CPU# <10> H_PM_DO WN_R <10>

H_PECI

RCIN#

NGFF WL

+BT(KEY E)

12

E

10K_040 2_5%

1 2

10K_040 2_5%

+3VS

XESD@

1 2

+3VS

12

RH219

+3VS

12

RH37

RH38

CH500.1U_020 1_10V6K

RH44

10K_040 2_5%

12

VGA@

DI

S,Optimus10

UMA

A

GPP_F13

DGPU_PRSNT#

Security Classification

2017/10/ 30 2018/10 /30

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

2017/10/ 30 2018/10 /30

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

PCIE/SATA/USB3/eSPI

Size Document Number Re v

Custom

EH5VF M/B LA-H501P

Date : Sheet o f

D

Date : Sheet o f

17 1 01Friday, February 22, 201 9

E

1A

A

1 2

ME_EN<58>

1 2

HDA_RST #_R<56> HDA_BIT_C LK_R<5 6> HDA_SDO UT_R<56> HDA_SYNC_ R<56>

1 1

RH208 33_0 402_5%

1 2

RH209 33_0 402_5%

1 2

RH210 33_0 402_5%

1 2

RH211 33_0 402_5%

12

RH196100K _0201_5%

12

RH197100K _0201_5%

@

RH45 0_04 02_5%

HDA_BIT_C LK HDA_RST #

HDA_RST # HDA_BIT_C LK HDA_SDO UT HDA_SYNC

intel critical net recommend

del RF reserve cap on HDA

CPU_DISPA _SDO_R< 6>

CPU_DISPA _SDI_R<6>

FOR Jefferson Peak RESET pin is glitch free,it is recommended that a pull-down resistor of 75K ohm on GPP_D5(CNV_RF_RESET#)

+RTCVCC

1 2

RH50 20 K_0402_1%

1 2

2 2

3 3

+3VS

+3VALW

4 4

CH18 1U _0201_6.3V6M

1 2

RH52 20 K_0402_1%

1 2

CH19 1U _0201_6.3V6M

1 2

JCMOS1 0_0603_ 5%@

+3VALW _DSW

RH55 1K _0402_5%

RH56 8.2 K_0402_5%

1 2

RH57 10 0K_0402_5%@

1 2

RH58 10 0K_0402_5%@

RH60 8.2 K_0402_5%

RH191 2.2K_ 0402_5% RH192 2.2K_ 0402_5%

RH251 2.2K_ 0402_5% RH252 2.2K_ 0402_5% RH253 2.2K_ 0402_5% RH254 2.2K_ 0402_5%

1 2

RH63 499_0402_1%

1 2

RH64 499_0402_1%

12

12 12

12 12 12 12

PCH_SML 0CLK

PCH_SML 0DATA

A

CPU_DISPA _BCLK_R<6>

PCH_SRT CRST#

CLR ME Delay 18~25 ms

PCH_RTC RST#

ECLR CMOS Delay 18~25 ms

WAKE #

PM_BATL OW#

AC_PRES ENT_R

PBTN_OU T#_R

PM_CLKR UN#

D_CK_SC LK D_CK_SD ATA

PCH_SMB CLK PCH_SMB DATA

2N7002K DW_SOT363 -6

PCH_SMB CLK

PCH_SML 1CLK <2 7,58,66> PCH_SML 1DATA <27 ,58,66>

B

HDA_SDIN0<56>

RH48

1 2

RH49

1 2

CLKREQ_ CNV#<5 2> CNV_RF_ RESET#<52> PCH_DMIC_ DATA0<56> PCH_DMIC_ CLK0<56>

TH22 @ TH24 @

PCH_RTC RST#<58>

PCH_PW ROK<58,78> EC_RSMR ST#<58>

PCH_SMB ALERT#<19>

PCH_SML 0ALERT#<19>

PCH_SML 1ALERT#<19>

QH7B

3 4

2N7002K DW_SOT363 -6

B

HDA_BIT_C LK HDA_SDIN0 HDA_SDO UT HDA_SYNC

HDA_RST #

S

2

G

6 1

D

CPU_DISPA _SDO CPU_DISPA _SDI_R CPU_DISPA _BCLK

CLKREQ_ CNV# CNV_RF_ RESET#

PCH_RTC RST# PCH_SRT CRST#

PCH_PW ROK EC_RSMR ST#

PCH_DPW ROK PCH_SMB ALERT# PCH_SMB CLK PCH_SMB DATA PCH_SML 0ALERT# PCH_SML 0CLK PCH_SML 0DATA PCH_SML 1ALERT# PCH_SML 1CLK PCH_SML 1DATA

D_CK_SC LK

D_CK_SD ATAPCH_SMB DATA

S

30_0402 _5%

+3VS

5

G

D

QH7A

,VGA,Thermal Sensor)

(EC

C

UH1D

BD11

HDA_BCLK/I2S0_SCLK

BE11

HDA_SDI0/I2S0_RXD

BF12

HDA_SDO/I2S0_TXD

BG13

HDA_SYNC/I2S0_SFRM

BE10

HDA_RST#/I2S1_SCLK

BF10

HDA_SDI1/I2S1_RXD

BE12

I2S1_TXD/SNDW2_DATA

BD12

I2S1_SFRM/SNDW2_CLK

AM2

HDACPU_SDO

AN3

HDACPU_SDI

AM3

HDACPU_SCLK

AV18

GPP_D8/I2S2_SCLK

AW18

GPP_D7/I2S2_RXD

BA17

GPP_D6/I2S2_TXD/MODEM_CLKREQ

BE16

GPP_D5/I2S2_SFRM/CNV_RF_RESET#

BF15

GPP_D20/DMIC_DATA0/SNDW4_DATA

BD16

GPP_D19/DMIC_CLK0/SNDW4_CLK

AV16

GPP_D18/DMIC_DATA1/SNDW3_DATA

AW15

GPP_D17/DMIC_CLK1/SNDW3_CLK

BE47

RTCRST#

BD46

SRTCRST#

AY42

PCH_PWROK

BA47

RSMRST#

AW41

DSW_PWROK

BE25

GPP_C2/SMBALERT#

BE26

GPP_C0/SMBCLK

BF26

GPP_C1/SMBDATA

BF24

GPP_C5/SML0ALERT#

BF25

GPP_C3/SML0CLK

BE24

GPP_C4/SML0DATA

BD33

GPP_B23/SML1ALERT#/PCHHOT#

BF27

GPP_C6/SML1CLK

BE27

GPP_C7/SML1DATA

CNP-H_BG A874

@

(DDR,G- Sens or)

D_CK_SC LK < 23,24>

D_CK_SD ATA <23 ,24>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2017/10/ 30 2018/10 /30

C

CNP-H

GPP_A12/BM_BUSY#/ISH_GP6/SX_EXIT_HOLDOFF#

GPP_B1/GSPI1_CS1#/TIME_SYNC1

1.8V

GPP_A13/SUSWARN#/SUSPWRDNACK

4 OF 13

Compal Secret Data

GPP_A8/CLKRUN#

GPD11/LANPHYPC

GPD9/SLP_WLAN#

DRAM_RESET#

GPP_B2/VRALERT#

GPP_B0/GSPI0_CS1#

GPP_K17/ADR_COMPLETE

GPP_B11/I2S_MCLK

SYS_PWROK

WAKE#

GPD6/SLP_A#

SLP_LAN#

GPP_B12/SLP_S0#

GPD4/SLP_S3# GPD5/SLP_S4#

GPD10/SLP_S5#

GPD8/SUSCLK

GPD0/BATLOW#

GPP_A15/SUSACK#

GPD2/LAN_WAKE# GPD1/ACPRESENT

SLP_SUS#

GPD3/PWRBTN#

SYS_RESET#

GPP_B14/SPKR

CPUPWRGD

ITP_PMODE

PCH_JTAGX PCH_JTAG_TMS PCH_JTAG_TDO

PCH_JTAG_TDI

PCH_JTAG_TCK

+3VALW

RH183 10K_ 0402_5%

1 2

Deciphered Date

v1.0

Re

XESD@

From ESD Team Request

Near PCH side

BF36 AV32

BF41

BD42

BB46 BE32 BF33 BE29 R47 AP29 AU3

BB47 BE40 BF40 BC28 BF42 BE42 BC42

BE45 BF44 BE35 BC37

BG44 BG42 BD39 BE46 AU2 AW29 AE3

AL3 AH4 AJ4 AH3 AH2 AJ3

12

CH200.1U_020 1_10V6K

CH210.1U_020 1_10V6K

CH220.1U_020 1_10V6K

CH51100P_ 0402_50V8J

D

DRAM_RE SET#

PM_CLKR UN#

LAN_DISAB LE_N

SLP_W LAN#

DRAM_RE SET# PCH_VRA LERT# TYPEC_3A LAN_GPO PCH_GPP _K17 PCH_GPP _B11 SYS_PW ROK

WAKE # PM_SLP_ A#

SLP_LAN # PM_SLP_ S0# PM_SLP_ S3# PM_SLP_ S4# PM_SLP_ S5#

SUSCLK PM_BATL OW#

SUSACK# _R

RH51 0_04 02_5%

LAN_W AKE# AC_PRES ENT_R SLP_SUS # PBTN_OU T#_R SYS_RESET # PCH_SPK R H_CPUPW RGD

XDP_ITP_P MODE CPU_XDP _TCK0 CPU_XDP _TMS CPU_XDP _TDO CPU_XDP _TDI PCH_JTA G_TCK1

SYS_RESET #

SYS_PW ROK

RH184100K_04 02_5% @

PCH_DPW ROK

RH61100K_ 0402_5% @

SYS_RESET #

SYS_PW ROK

PCH_PW ROK

EC_RSMR ST#

D

1 2

1 2 1 2

AC_PRES ENT <58 >

PBTN_OU T# < 58>

E

DDR_DRA MRST#_R < 23,24>

Connect CPU & PCH

+1.2V_VD DQ

RH46 470_040 2_1%

1 2

@

RH47 0_0402_5%

12

CH13 0.1U_ 0201_10V6K

@

TH14@

TH15@

TYPEC_3A <43> LAN_GPO <51>

TH19@ TH20@

SYS_PW ROK <58,78>

TH37@ TH21@ TH38@

PM_SLP_ S3# <58 ,78> PM_SLP_ S4# <58 ,78>

TH23@

@

T207@

SUSPW RDNACK <5 8>

1 2

RH53 0_ 0402_5%@

T208

@

1 2

RH54

PCH_SPK R <1 9,56>

H_CPUPW RGD <10 >

T209

@

CPU_XDP _TCK0 <10 >

CPU_XDP _TMS < 10> CPU_XDP _TDO <10>

CPU_XDP _TDI <10 >

PCH_JTA G_TCK1 <10>

PM_SLP_ S3# PM_SLP_ S4#

SUSCLK <52,68>

--No Support Deep Sx

0_0402_ 5%@

RH193 100K_020 1_5% RH194 100K_020 1_5%

intel critical net recommend

12

E

PCH_DPW ROK

+3VALW _DSW

+3VALW

18 1 01Friday, February 22, 201 9

1A

EC_RSMR ST#

Title

Size Document Number Re v

Custom

Date : Sheet o f

1 2

@

RH59 0_04 02_5%

LAN_W AKE# PCH_PW ROK EC_RSMR ST#

PCH_VRA LERT#

Compal Electronics, Inc.

PCH(5/8)PMU/HDA/SMBUS/DMIC

EH5VF M/B LA-H501P

1 2

RH212 10K_ 0402_5%

1 2

RH213 10K_ 0402_5%

1 2

RH214 10K_ 0402_5%

RH62 10 K_0402_5%@

A

+3VALW

1 2

RH215 2.2K_ 0402_5%

1 2

RH216 2.2K_ 0402_5%

1 2

RH217 2.2K_ 0402_5%

1 2

RH218 2.2K_ 0402_5%

+3VS

RH66 10K_0402 _5%@

1 1

2 2

3 3

4 4

RH68 4 9.9K_0402_1%

RH69 4 9.9K_0402_1%

RH70 4 9.9K_0402_1%@

RH71 4 9.9K_0402_1%@

RH72 10K_0402 _5%VGA@

RH73 10K_0402 _5%VGA@

+3VALW

RH74 4.7 K_0402_5%@

This signal has a weak internal pull-down. 0 = Master Attached Flash Sharing (MAFS) enabled (Default) 1 = Slave Attached Flash Sharing (SAFS) enabled. Notes:

1. This signal is in the primary well.

Warning: This strap must be configured to ‘ 0’ i f the eSPI or LPC strap is configured to ‘ 0’

+3VALW

+3VS

12

1 2

RH112 4.7K_0402 _5%@

SMBALERT# / GPP_C2 has a weak internal Pull-down. 0 = Disable Intel ME (TLS) (Default) 1 = Enable Intel ME (TLS)

1 2

RH113 4.7K_0402 _5%@

SML0ALERT# / GPP_C5 has a weak internal Pull-down. 0 = LPC is selected (for EC 9022). 1 = eSPI is selected

1 2

RH114 1 50K_0402_1%

SML1ALERT# / GPP_B23 has an internal pull-down. 0 = Disable IntelR DCI-OOB (Default) 1 = Enable IntelR DCI-OOB

*

1 2

RH77 4.7 K_0402_5%@

The signal has a weak internal Pull-down.

0 = Disable “ No Reboot” mode . (Default) 1 = Enable “ No Reboot” mod e (PCH will disabl e the TCO Timer system reboot feature). This function is useful when running ITP/XDP. Notes:

1. The internal Pull-down is disabled after PCH_PWROK is high.

2. This signal is in the primary well.

@

1 2

RH80 150K_ 0402_1%

This Signal has a weak internal Pull-down. 0: SPI (Default) 1: LPC Notes:

1. The internal Pull-down is disabled after PCH_PWROK is high.

2. This signal is in the primary well.

RH83 10 0K_0402_5%@

Top Swap Override

0 = Disable “ Top Swap” mode . (Default) 1 = Enable “ Top Swap” mode. The internal Pull-down is disabled after PCH_PWROK is high.

12

I2C_1_SCL I2C_1_SDA I2C_0_SCL I2C_0_SDA

EC_SCI# GC6_FB_ EN3V3 GC6_FB_ EN

UART_2_ PRXD_DTXD

UART_2_ PTXD_DRXD

UART_2_ PRTS_DCTS

UART_2_ PCTS_DRTS

DGPU_PW R_EN

DGPU_HO LD_RST#

GPP_H12

GC6_FB_ EN3V3<27>

check needed?

CG11 connect to GPP_B15

GPP_H12 <16>

STRAP

PCH_SMB ALERT# < 18>

PCH_SML 0ALERT# <18>

PCH_SML 1ALERT# <18>

GSPI0_MOS I

GSPI1_MOS I

PCH_SPK R

STRAP

PCH_SPK R <1 8,56>

STRAP

B

STRAP

GSPI1_MOS I

1 2

EC_SCI#

GSPI0_MOS I

EC_SCI#<58>

RH67 0_0402_ 5%@

TS_EN<38,58>

check for remove (PCH or Both)

DGPU_AC _DETECT<27 ,58,83>

GPU_EVENT#<27>

DGPU_HO LD_RST#<27>

DGPU_PW R_EN<27,37>

UART_2_ PTXD_DRXD<52>

UART_2_ PRXD_DTXD<52>

I2C_1_SCL<6 3>

I2C_1_SDA<63>

Re Reserved 0 Reserved for 8 Layer

TS_EN

DGPU_AC _DETECT

GPU_EVE NT#

DGPU_HO LD_RST# DGPU_PW R_EN

UART_2_ PCTS_DRTS UART_2_ PRTS_DCTS UART_2_ PTXD_DRXD UART_2_ PRXD_DTXD

I2C_1_SCL I2C_1_SDA I2C_0_SCL I2C_0_SDA

GPP_D9

GPP_D10

served

C

BA26

GPP_B22/GSPI1_MOSI

BD30

GPP_B21/GSPI1_MISO

AU26

GPP_B20/GSPI1_CLK

AW26

GPP_B19/GSPI1_CS0#

BE30

GPP_B18/GSPI0_MOSI

BD29

GPP_B17/GSPI0_MISO

BF29

GPP_B16/GSPI0_CLK

BB26

GPP_B15/GSPI0_CS0#

BB24

GPP_C9/UART0A_TXD

BE23

GPP_C8/UART0A_RXD

AP24

GPP_C11/UART0A_CTS#

BA24

GPP_C10/UART0A_RTS#

BD21

GPP_C15/UART1_CTS#/ISH_UART1_CTS#

AW24

GPP_C14/UART1_RTS#/ISH_UART1_RTS#

AP21

GPP_C13/UART1_TXD/ISH_UART1_TXD

AU24

GPP_C12/UART1_RXD/ISH_UART1_RXD

AV21

GPP_C23/UART2_CTS#

AW21

GPP_C22/UART2_RTS#

BE20

GPP_C21/UART2_TXD

BD20

GPP_C20/UART2_RXD

BE21

GPP_C19/I2C1_SCL

BF21

GPP_C18/I2C1_SDA

BC22

GPP_C17/I2C0_SCL

BF23

GPP_C16/I2C0_SDA

BE15

GPP_D4/ISH_I2C2_SDA/I2C3_SDA/SBK4_BK4

BE14

GPP_D23/ISH_I2C2_SCL/I2C3_SCL

CNP-H_BG A874

@

1 2

RH84 1K_0402 _5%@

1 2

RH85 10K_040 2_5%

1 2

RH86 1K_0402 _5%@

1 2

RH87 10K_040 2_5%

GPP_D10 GPP_D9

UH1K

+1.8VALW _PRIM

00 1 01 11

D

CNP-H

GPP_D9

Rev1.0

1 2

BA20

GPP_D10

BB20

PROJECT _ID0

BB16

PROJECT _ID1

AN18

BF14 AR18

SUB_DET

BF17

CPU_ID

BE17

AG45 AH46

AH47 AH48

AV34 AW32 BA33 BE34 BD34 BF35 BD38

+1.8VALW _PRIM

Project_ID0Project_ID1

GPP_D11GPP_D12 0 0 0 1 1 1

CPU_ID

1 0

SUB_DET

PANEL_O D_EN <38>

RH255 1K_0 402_5%H82 @

RH256 10K_ 0402_5%H62@

RH185 1K_0 402_5%@

GPP_D9/ISH_SPI_CS#/GSPI2_CS0#

GPP_D11/ISH_SPI_MISO/GP_BSSB_CLK/GSPI2_MISO

GPP_D12/ISH_SPI_MOSI/GP_BSSB_DI/GSPI2_MOSI

GPP_D15/ISH_UART0_RTS#/GSPI2_CS1#/CNV_WFEN

GPP_D10/ISH_SPI_CLK/GSPI2_CLK

GPP_D16/ISH_UART0_CTS#/CNV_WCEN

GPP_D14/ISH_UART0_TXD/I2C2_SCL

GPP_D13/ISH_UART0_RXD/I2C2_SDA

GPP_H20/ISH_I2C0_SCL GPP_H19/ISH_I2C0_SDA

GPP_H22/ISH_I2C1_SCL GPP_H21/ISH_I2C1_SDA

GPP_A23/ISH_GP5 GPP_A22/ISH_GP4 GPP_A21/ISH_GP3 GPP_A20/ISH_GP2 GPP_A19/ISH_GP1

GPP_A17/SD_VDD1_PWR_EN#/ISH_GP7

11 OF 13

PROJECT _ID0

PROJECT _ID1

GPP_A18/ISH_GP0

RH88 1K_0402 _5%SATARD @

RH89 10K_040 2_5%SAT ANRD@

RH90 1K_0402 _5%

RH91 10K_040 2_5%@

Project ID

EH50F(2060 WO RD) EH50F(2060 W RD) EH5VF(2050 WO RD)

*

EH5VF(2050 W RD)

SCI capability is available on all GPIOs PCH GPIOs that can be routed to generate SMI# or NMI:

GPP_B14, GPP_B20, GPP_B23

‧‧‧‧

GPP_C[23:22]

‧‧‧‧

GPP_D[4:0]

‧‧‧‧

GPP_E[8:0]

‧‧‧‧

GPP_I[3:0]

‧‧‧‧

GPP_G[7:0] (support SMI# only).

‧‧‧‧

The voltage of all GPIO pads in each GPP group is determined by the voltage supplied to the group (either 3.3V or 1.8V), except for GPP_I and GPD group, (which are 3.3V only), and GPP_J group (which is 1.8V only).

All GPIOs have programmable internal pull-up/pull-down resistors which are off by default. The internal pull-up/pull-down for each GPIO can be enabled by BIOS programming.

E

+1.8VALW _PRIM

1 2

+1.8VALW _PRIM

1 2

Security Classification

2017/10/ 30 2018/10 /30

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

2017/10/ 30 2018/10 /30

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

PCH(6/8)GPIO/I2C/UART/STRAP

Size Document Number Re v

Custom

EH5VF M/B LA-H501P

Date : Sheet o f

D

Date : Sheet o f

19 1 01Friday, February 22, 201 9

E

1A

A

B

C

D

E

GPIO Group Voltag e

GPP A

GPP B GPP C

GPP D

GPP E GPP F

GPP G

GPP H GPP K

GPP I

GPP J

GPD

1U_0201_6.3V6M

CH28

Close to BB11

+1.24V_VCCLDOSR AM_IN +1.24V_PRIM_DPHY

RH96 0_0402_5%@

RH174 for 571391_CFL_H_PDG_Rev0p71.pdf

CH39

@

1-3MM FROM PACKAGE FOR VCCPRIM AY8/BB7

E

+1.05VALW

+1.05VALW_PC H_PRIM

+3VALW

1P_0402_50V8

1

CH41

2

@

5.95A

6.6A

0.0012A

0.2A

0.42A

BG45 BG46

0.109A

0.015A

0.213A

0.00428A

0.169A

0.0198A

0.0085A

0.021A

1 2

RH99 0_0402_5%@

RH101 0_0402 _5%@

UH1H

AA22

VCCPRIM_1P051

AA23

VCCPRIM_1P052

AB20

VCCPRIM_1P053

AB22

VCCPRIM_1P054

AB23

VCCPRIM_1P055

AB27

VCCPRIM_1P056

AB28

VCCPRIM_1P057

AB30

VCCPRIM_1P058

AD20

VCCPRIM_1P059

AD23

VCCPRIM_1P0510

AD27

VCCPRIM_1P0511

AD28

VCCPRIM_1P0512

AD30

VCCPRIM_1P0513

AF23

VCCPRIM_1P0516

AF27

VCCPRIM_1P0517

AF30

VCCPRIM_1P0518

U26

VCCPRIM_1P0523

U29

VCCPRIM_1P0524

V25

VCCPRIM_1P0525

V27

VCCPRIM_1P0526

V28

VCCPRIM_1P0527

V30

VCCPRIM_1P0528

V31

VCCPRIM_1P0529

AD31

VCCPRIM_1P0514

AE17

VCCPRIM_1P0515

W22

VCCDUSB_1P051

W23

VCCDUSB_1P052

VCCDSW_1P051 VCCDSW_1P052

W31

VCCPRIM_MPHY_1P05

D1

VCCPRIM_1P0521

E1

VCCPRIM_1P0522

C49

VCCAMPHYPLL_1P051

D49

VCCAMPHYPLL_1P052

E49

VCCAMPHYPLL_1P053

P2

VCCA_XTAL_1P051

P3

VCCA_XTAL_1P052

W19

VCCA_SRC_1P051

W20

VCCA_SRC_1P052

C1

VCCAPLL_1P054

C2

VCCAPLL_1P055

V19

VCCA_BCLK_1P05

B1

VCCAPLL_1P051

B2

VCCAPLL_1P052

B3

VCCAPLL_1P053

CNP-H_BGA874

@

12

+1.05VALW

JPH1

@

2

112

JUMP_43X79

1 1

1 2

RH94 0_0603_5%@

+1.05VALW_PC H

2 2

place near VCCDUSB FOR W22/W23

1-5MM FROM PACKAGE EDGE FOR VCCAPLL C1/C2

3 3

+1.05VALW_PC H

0.1U_0201_10V6K

1

2

+1.05VALW_PC H

1U_0201_6.3V6M

1

2

CH29

CH33

1 2

RH102 0_04 02_5%@

1P_0402_50V8

1

CH43

2

@

1-3MM FROM PACKAGE EDGE FOR VCCA_BCLK V19

+1.05VALW_PC H_PRIM

5.95A

1U_0201_6.3V6M

CH23

1

2

+1.05VALW

6.6A

+1.05VALW_PC H

+1.05VALW_PC H +1.05V_VCCDSW

1

2

1-

3MM FROM PACKAGE

VCCPRIM_MPHY W31

+1.05VALW_PC H

1

2

+1.05VALW_VCCAZPL L

1U_0201_6.3V6M

22U_0603_6.3V6M

CH26

1

CH25

2

Place Near UH1 VCCPRIM_1_0523~29 3-5MM FROM PACKAGE EDGE

0.1U_0201_10V6K CH30

1-3MM FROM PACKAGE EDGE

0.1U_0201_10V6K CH34

1-5MM FROM PACKAGE EDGE FOR VCCAPLL B1/B2/B3

1P_0402_50V8

1

CH44

2

@

1U_0201_6.3V6M

1

2

+1.05VALW_PC H

1U_0201_6.3V6M

1

2

HSIO for DMIU/USB3.1/PCIE=4162mA

+1.05VALW_PC H

+1.05V_VCCDSW

+1.05VALW_VCCAZPL L

+1.05VALW_VCCAMP HYPLL

+1.05VALW_XTAL

CH31

0.1U_0201_10V6K CH54

1

CH35

2

1-3MM FROM PACKAGE EDGE

A

+1.05VALW_VCCAMP HYPLL

22U_0603_6.3V6M

1

CH45

2

+1.05VALW_XTAL

22U_0603_6.3V6M

1

CH49

2

1U_0201_6.3V6M

CH46

+RTCBATT

change to 10k

RH104 1K_0 402_5%

+CHGRTC

B

12

DH2

2

3

BAV70W_SOT32 3-3

+RTCVCC

1

1U_0201_6.3V6M

0.1U_0201_10V6K CH48

1

CH47

2

1 2

RH103 0_04 02_5%@

LC filter close to pin

4 4

1uF 1-3MM FROM PACKAGE EDGE

1 2

RH105 0_04 02_5%@

CNP-H

VCCPRIM_3P32

VCCPRIM_3P35

VCCPGPPG_3P3

VCCPRIM_3P33 VCCPRIM_3P34

VCCPRIM_3P31 VCCDSW_3P31 VCCDSW_3P32

VCCPRIM_1P83 VCCPRIM_1P84 VCCPRIM_1P85 VCCPRIM_1P86 VCCPRIM_1P87

VCCPRIM_1P81 VCCPRIM_1P82

VCCPRIM_1P0520 VCCPRIM_1P0519

VCCPRIM_1P241 VCCPRIM_1P242

VCCDPHY_1P241 VCCDPHY_1P242 VCCDPHY_1P243

VCCMPHY_SENSE VSSMPHY_SENSE

8 OF 13

+3VALW_DSW

0.1U_0201_10V6K CH40

1

2

+3VALW_HDA

1P_0402_50V8

1

CH42

2

@

reserve filter follow CRB 8/21

+RTCBATT

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

DCPRTC1 DCPRTC2

VCCSPI

VCCRTC1 VCCRTC2

VCCPGPPHK1 VCCPGPPHK2 VCCPGPPEF1 VCCPGPPEF2

VCCPGPPD VCCPGPPBC1 VCCPGPPBC2

VCCPGPPA

VCCHDA

v1.0

Re

JRTC1

1

2

3

GND

4

GND

ACES_50271-00 20N-001

CONN@

SP02000RO00

AW9

BF47 BG47

V23

AN44

BC49 BD49

AN21 AY8 BB7

AC35 AC36 AE35 AE36

AN24 AN26 AP26

AN32

AT44 BE48 BE49

BB14 AG19 AG20 AN15 AR15 BB11

AF19 AF20

AG31 AF31 AK22 AK23

AJ22 AJ23 BG5

K47 K46

RH100 0_06 03_5%

2017/10/30 2018/10/30

0.182A

+VCCRTCEXT

0.0

0.05A

0.145A

0.97A

0.262A

0.174A

0.

0.343A

0.101A

0.106A

0.113A

0.00767A

0.766A

0.882A

+1.8V_PHVLDO

0.193A

0.0895A

VCCMPHY_SENSE VSSMPHY_SENSE

1 2

Compal Secret Data

14A

Internal LDO

95A

Deciphered Date

+3VALW

+1.8VALW_PRIM

+1.8V_PHVLDO

RH95 0_0402_5%@

TH27@ TH28@

+1.8VALW_PRIM+1.8VALW

+VCCRTCEXT

+3VALW

+RTCVCC

+1.8VALW_PRIM

+3VALW_DSW

+3VALW_HDA

1 2

+1.05VALW_PC H +1.05VALW_PC H

+1.24V_VCCLDOSR AM_IN

+1.24V_PRIM_DPHY

+1.24V_PRIM_MAR

1-3MM FROM PACKAGE FOR PGPPEF AE35/AE37

+1.8VALW_PRIM

Short pins AJ22,AJ23,AK22,AK23 together at surface layer from PDG Rev0.71

0.1U_0201_10V6K CH36

1

2

@

reserved for c nvi

+1.8VALW_PRIM + 1.8VALW_PRIM

0.1U_0201_10V6K CH52

1

2

near AG19/AG20

D

+VCCRTCEXT

0.1U_0201_10V6K CH24

1

2

+1.8VALW_PRIM

4.7U_0402_6.3V6M

1

CH27

2

VCCPHVLDO_1P8 (External VRM mode RH172 unmount)

For DDX03 R02

+1.24V_PRIM_MAR

4.7U_0402_6.3V6M

1

CH32

2

+3VALW+3VALW

0.1U_0201_10V6K

1

2

1-3MM FROM PACKAGE FOR PGPPHK AC35/AC36

0.1U_0201_10V6K CH53

1

2

@

Compal Electronics, Inc.

Title

PCH(7/8)Power

Size Document Number Re v

Custom

EH5VF M/B LA-H501P

Date : Sheet o f

1 2

1

2

1U_0201_6.3V6M

*

+3VALW

CH37

3.3 V

3.3 V 8V

1.

3.3 V

3.3V Only

1.8V Only

3.3V Only

0.1U_0201_10V6K CH38

1

2

20 1 01Friday, February 22, 2019

1A

A

B

C

D

E

CNP-H

UH1I

A2

VSS

1 1

2 2

3 3

A28

A33 A37

A45 A46 A47 A48

AA19 AA20 AA25 AA27 AA28 AA30 AA31 AA49

AA5 AB19 AB25 AB31 AC12 AC17 AC33 AC38

AC4 AC46

AD1 AD19

AD2 AD22 AD25 AD49 AE12 AE33 AE38

AE4 AE46 AF22 AF25 AF28

AG1 AG22 AG23 AG25 AG27 AG28 AG30 AG49 AH12 AH17 AH33 AH38

AJ19 AJ20 AJ25 AJ27 AJ28 AJ30

AJ31 AK19 AK20 AK25 AK27 AK28 AK30 AK31

AK4

AK46

A3

A4

A5 A8

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

9 OF 13

VSS

CNP-H_BG A874

@

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

Rev1.0

AL12 AL17 AL21 AL24 AL26 AL29 AL33 AL38 AM1 AM18 AM32 AM49 AN12 AN16 AN34 AN38 AP4 AP46 AR12 AR16 AR34 AR38 AT1 AT16 AT18 AT21 AT24 AT26 AT29 AT32 AT34 AT45 AV11 AV39 AW10 AW4 AW40 AW46 B47 B48 B49 BA12 BA14 BA44 BA5 BA6 BB41 BB43 BB9 BC10 BC13 BC15 BC19 BC24 BC26 BC31 BC35 BC40 BC45 BC8 BD43 BE44 BF1 BF2 BF3 BF48 BF49 BG17 BG2 BG22 BG25 BG28

BG3 BG33 BG37

BG4 BG48

C12 C25 C30

C48

D12 D16 D17 D30 D33

E10 E13 E15 E17 E19 E22 E24 E26 E31 E33 E35 E40 E42

F41 F43 F47

G44

K11

K39 M16 M18 M21

C4

C5

D8

E8

G6

H8 J10 J26 J29

J4 J40 J46 J47 J48

J9

UH1L

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

12 OF 13

VSS

CNP-H_BG A874

@

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

Rev1.0

M24 M32 M34 M49 M5 N12 N16 N34 N35 N37 N38 P26 P29 P4 P46 R12 R16 R26 R29 R3 R34 R38 R4 T17 T18 T32 T4 T49 T5 T7 U12 U15 U17 U21 U24 U33 U38 V20 V22 V4 V46 W25 W27 W28 W30 Y10 Y12 Y17 Y33 Y38 Y9

CNP-H

UH1J

RSVD7 RSVD8 RSVD6 RSVD5

RSVD3 RSVD4

RSVD2 RSVD1

PREQ# PRDY#

CPU_TRST#

TRIGGER_OUT

TRIGGER_IN

10 OF 13

CNP-H_BG A874

@

Rev1.0

Y14 Y15 U37 U35

N32 R32

AH15 AH14

XDP_PRE Q#

AL2

XDP_PRD Y#

AM5

CPU_XDP _TRST#

AM4

PCH_TRIGO UT PCH_TRIGO UT_R

AK3

CPU_TRIGO UT_R

AK2

1 2

RH106 30_0402_ 5%

XDP_PRE Q# <10> XDP_PRD Y# < 10> CPU_XDP _TRST# <10>

PCH_TRIGO UT_R <13> CPU_TRIGO UT_R <13>

4 4

Security Classification

2017/10/ 30 2018/10 /30

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

2017/10/ 30 2018/10 /30

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

PCH(8/8)GND/RSVD

Size Document Number Re v

Custom

EH5VF M/B LA-H501P

Date : Sheet o f

D

Date : Sheet o f

21 1 01Friday, February 22, 201 9

E

1A

5

D D

C C

4

3

2

1

Reserve Page

B B

A A

Security Cl assification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2017/11/23 2017/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document N umber Re v

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

N18E-GDDR6_D

EH5VF M/B LA-H501P

1

1A

22 101Friday, February 22, 2019

1A

5

4

3

2

1

CHANNEL-A

BOT

REVERSE TYPE

Interleaved Memory

TOP: JDIMM1 CONN Non-ECC DIMM

D D

+1.2V_VDDQ

+3VS

0.1U_0201_10V6K

2.2U_0402_6.3V6M

+0.6V_DDR_VREFC A

CD1

2

CD2

1

SPD ADDRESS FOR CHANNEL A : WRITE ADDRESS: 0XA0 READ ADDRESS: 0XA1 SA0 = 0; SA1 = 0; SA2 = 0. DDR4 POR OPERATING SPEED: 1867 MT/S

C C

STRETCH GOAL IS 2133 MT/S

Layout Note: Place near JDIMM1.257,259

+2.5V +0.6VS_VTT

10U_0402_6.3V6M

1

CD3

2

Layout Note: PLACE THE CAP near JDIMM1. 164

B B

+0.6V_DDR_VREFC A

2

CD11

0.1U_0201_ 10V6K

1

10uF* 2 1uF*2

1U_0201_6.3V6M

1

CD4

2

CD5

2

1

CD6

2.2uF* 1

0.1uF* 1

CD12

2.2U_0402_ 6.3V6M

Layout Note: Place near JDIMM1.258

10uF* 2

10U_0402_6.3V6M

1

2

1uF*1

1U_0201_6.3V6M

10U_0402_6.3V6M

1

CD7

CD9

CD8

2

1

PLACE NEAR TO PIN

Part Number: SP07001CY00 Part Value: S SOCKET LOTES ADDR0206-P001A 260P DDR4

DDR_A_D[0..15]<7>

DDR_A_D[16..31 ]<7>

DDR_A_D[32..47 ]<7>

DDR_A_D[48..63 ]<7>

JDIMM1B

REVERSE

111

VDD1

112

VDD2

117

VDD3

118

VDD4

123

VDD5

124

VDD6

129

VDD7

130

VDD8

135

VDD9

136

VDD10

255

VDDSPD

164

VREFCA

1

VSS

2

VSS

5

VSS

6

VSS

9

VSS

10

VSS

14

VSS

15

VSS

18

VSS

19

VSS

22

VSS

23

VSS

26

VSS

27

VSS

30

VSS

31

VSS

35

VSS

36

VSS

39

VSS

40

VSS

43

VSS

44

VSS

47

VSS

48

VSS

51

VSS

52

VSS

56

VSS

57

VSS

60

VSS

61

VSS

64

VSS

65

VSS

68

VSS

69

VSS

72

VSS

73

VSS

77

VSS

78

VSS

81

VSS

82

VSS

85

VSS

86

VSS

89

VSS

90

VSS

93

VSS

94

VSS

98

VSS

262

GND

LOTES_ADDR02 06-P001A

CONN@

VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18 VDD19

VPP1 VPP2

GND

141 142 147 148 153 154 159 160 163

258

VTT

257 259

99

VSS

102

VSS

103

VSS

106

VSS

107

VSS

167

VSS

168

VSS

171

VSS

172

VSS

175

VSS

176

VSS

180

VSS

181

VSS

184

VSS

185

VSS

188

VSS

189

VSS

192

VSS

193

VSS

196

VSS

197

VSS

201

VSS

202

VSS

205

VSS

206

VSS

209

VSS

210

VSS

213

VSS

214

VSS

217

VSS

218

VSS

222

VSS

223

VSS

226

VSS

227

VSS

230

VSS

231

VSS

234

VSS

235

VSS

238

VSS

239

VSS

243

VSS

244

VSS

247

VSS

248

VSS

251

VSS

252

VSS

261

+1.2V_VDDQ

+0.6VS_VTT

+2.5V

+1.2V_VDDQ

RD7 240_04 02_1%

DDR_DRAMRST #_R

2

1

+1.2V_VDDQ

(4 mm)

DDR_A_CLK0<7> DDR_A_CLK#0<7> DDR_A_CLK1<7> DDR_A_CLK#1<7>

DDR_A_CKE0<7> DDR_A_CKE1<7>

DDR_A_CS#0<7> DDR_A_CS#1<7>

DDR_A_ODT0<7> DDR_A_ODT1<7>

DDR_A_BG0<7> DDR_A_BG1<7> DDR_A_BA0<7> DDR_A_BA1<7>

DDR_A_MA0<7> DDR_A_MA1<7> DDR_A_MA2<7> DDR_A_MA3<7> DDR_A_MA4<7> DDR_A_MA5<7> DDR_A_MA6<7> DDR_A_MA7<7> DDR_A_MA8<7> DDR_A_MA9<7> DDR_A_MA10<7> DDR_A_MA11<7> DDR_A_MA12<7> DDR_A_MA13<7> DDR_A_MA14_W E#< 7> DDR_A_MA15_CAS#<7> DDR_A_MA16_RAS#<7>

DDR_A_ACT#<7>

DDR_A_PAR<7> DDR_A_ALERT#<7 >

12

DDR_DRAMRST #_R<1 8,24>

D_CK_SDATA<18,24> D_CK_SCLK<18,24>

For ECC DIMM

+1.2V_VDDQ

CD10

ESD@

33P_0201_5 0V8J

PLACE NEAR TO SODIMM

DDR_A_CLK0 DDR_A_CLK#0 DDR_A_CLK1 DDR_A_CLK#1

DDR_A_CKE0 DDR_A_CKE1

DDR_A_CS#0 DDR_A_CS#1

DDR_A_ODT0 DDR_A_ODT1

DDR_A_BG0 DDR_A_BG1 DDR_A_BA0 DDR_A_BA1

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14_W E# DDR_A_MA15_CAS# DDR_A_MA16_RAS#

DDR_A_ACT#

DDR_A_PAR DDR_A_ALERT# DIMM1_CHA_EVENT# DDR_DRAMRST #_R

JDIMM1A

REVERSE

137

CK0(T)

139

CK0#(C)

138

CK1(T)

140

CK1#(C)

109

CKE0

110

CKE1

149

S0#

157

S1#

162

S2#/C0

165

S3#/C1

155

ODT0

161

ODT1

115

BG0

113

BG1

150

BA0

145

BA1

144

A0

133

A1

132

A2

131

A3

128

A4

126

A5

127

A6

122

A7

125

A8

121

A9

146

A10_AP

120

A11

119

A12

158

A13

151

A14_WE#

156

A15_CAS#

152

A16_RAS#

114

ACT#

143

PARITY

116

ALERT#

134

EVENT#

108

RESET#

254

SDA

253

SCL

166

SA2

260

SA1

256

SA0

92

CB0_NC

91

CB1_NC

101

CB2_NC

105

CB3_NC

88

CB4_NC

87

CB5_NC

100

CB6_NC

104

CB7_NC

97

DQS8(T)

95

DQS8#(C)

12

DM0#/DBI0#

33

DM1#/DBI1#

54

DM2#/DBI2#

75

DM3#/DBI3#

178

DM4#/DBI4#

199

DM5#/DBI5#

220

DM6#/DBI6#

241

DM7#/DBI7#

96

DM8#/DBI8#

LOTES_ADDR02 06-P001A

CONN@

DQS0(T)

DQS0#(C)

DQ10 DQ11 DQ12 DQ13 DQ14 DQ15

DQS1(T)

DQS1#(C)

DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23

DQS2(T)

DQS2#(C)

DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31

DQS3(T)

DQS3#(C)

DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39

DQS4(T)

DQS4#(C)

DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47

DQS5(T)

DQS5#(C)

DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55

DQS6(T)

DQS6#(C)

DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63

DQS7(T)

DQS7#(C)

DDR_A_D0

8

DQ0

DDR_A_D1

7

DQ1

DDR_A_D2

20

DQ2

DDR_A_D3

21

DQ3

DDR_A_D4

4

DQ4

DDR_A_D5

3

DQ5

DDR_A_D6

16

DQ6

DDR_A_D7

17

DQ7

DDR_A_DQS0

13

DDR_A_DQS#0

11

DDR_A_D8

28

DQ8

DDR_A_D9

29

DQ9

DDR_A_D10

41

DDR_A_D11

42

DDR_A_D12

24

DDR_A_D13

25

DDR_A_D14

38

DDR_A_D15

37

DDR_A_DQS1

34

DDR_A_DQS#1

32

DDR_A_D16

50

DDR_A_D17

49

DDR_A_D18

62

DDR_A_D19

63

DDR_A_D20

46

DDR_A_D21

45

DDR_A_D22

58

DDR_A_D23

59

DDR_A_DQS2

55

DDR_A_DQS#2

53

DDR_A_D24

70

DDR_A_D25

71

DDR_A_D26

83

DDR_A_D27

84

DDR_A_D28

66

DDR_A_D29

67

DDR_A_D30

79

DDR_A_D31

80

DDR_A_DQS3

76

DDR_A_DQS#3

74

DDR_A_D32

174

DDR_A_D33

173

DDR_A_D34

187

DDR_A_D35

186

DDR_A_D36

170

DDR_A_D37

169

DDR_A_D38

183

DDR_A_D39

182

DDR_A_DQS4

179

DDR_A_DQS#4

177

DDR_A_D40

195

DDR_A_D41

194

DDR_A_D42

207

DDR_A_D43

208

DDR_A_D44

191

DDR_A_D45

190

DDR_A_D46

203

DDR_A_D47

204

DDR_A_DQS5

200

DDR_A_DQS#5

198

DDR_A_D48

216

DDR_A_D49

215

DDR_A_D50

228

DDR_A_D51

229

DDR_A_D52

211

DDR_A_D53

212

DDR_A_D54

224

DDR_A_D55

225

DDR_A_DQS6

221

DDR_A_DQS#6

219

DDR_A_D56

237

DDR_A_D57

236

DDR_A_D58

249

DDR_A_D59

250

DDR_A_D60

232

DDR_A_D61

233

DDR_A_D62

245

DDR_A_D63

246

DDR_A_DQS7

242

DDR_A_DQS#7

240

DDR_A_DQS0 <7>

DDR_A_DQS#0 <7>

DDR_A_DQS1 <7>

DDR_A_DQS#1 <7>

DDR_A_DQS2 <7>

DDR_A_DQS#2 <7>

DDR_A_DQS3 <7>

DDR_A_DQS#3 <7>

DDR_A_DQS4 <7>

DDR_A_DQS#4 <7>

DDR_A_DQS5 <7>

DDR_A_DQS#5 <7>

DDR_A_DQS6 <7>

DDR_A_DQS#6 <7>

DDR_A_DQS7 <7>

DDR_A_DQS#7 <7>

DIMM Side

+0.6V_DDR_VREFC A

Layout Note:

ace near JDIMM1

Pl

10uF* 6

*8

1uF 330uF* 1

10U_0402_6.3V6M

CD16

A A

1

2

CD18

CD17

1

2

5

10U_0402_6.3V6M

CD19

CD21

CD20

1

2

1

2

+1.2V_VDDQ+1.2V_VDDQ

10U_0402_6.3V6M

CD23

CD22

1

2

@

1U_0201_6.3V6M

1

CD24

2

1U_0201_6.3V6M

1

CD25

2

1U_0201_6.3V6M

1

CD26

CD27

2

4

1U_0201_6.3V6M

1

CD30

CD29

CD28

2

+1.2V_VDDQ

1U_0201_6.3V6M

1

2

1

+

2

CD32 330U_D2_2 V_Y

CD31

2

CD13

@

0.1U_0201_ 10V6K

1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

RD8 1K_0402_1%

1 2

RD10 1K_0402_1%

1 2

2017/10/30 2018/10/30

2

CD14

0.1U_0201_ 10V6K

1

Compal Secret Data

Deciphered Date

1 2

RD9

2_0402_1%

2

CPU Side

+0.6V_VREFCA

VR

EF traces should be at least 20 mils

wide with 20 mils spacing to other

1

sign als

CD15

0.022U_040 2_16V7K

2

RD11

24.9_0402_1 %

1 2

Compal Electronics, Inc.

Title

Size Document Number Re v

Date : Sheet o f

Compal Electronics, Inc.

DDRIV_CHA: DIMM0

EH5VF M/B LA-H501P

1

23 1 01Friday, February 22, 2019

1A

5

4

3

2

1

CHANNEL-B

TOP: JDIMM2 CONN

D D

Non-ECC DIMM

SPD ADDRESS FOR CHANNEL B : WRITE ADDRESS: 0XA4 READ ADDRESS: 0XA3 SA0 = 0; SA1 = 1; SA2 = 0. DDR4 POR OPERATING SPEED: 1867 MT/S STRETCH GOAL IS 2133 MT/S

C C

Layout Note: Place near JDIMM3.257,259

10uF* 2 1uF*2

10U_0402_6.3V6M

1

CD35

2

Layout Note: PLACE THE CAP WITHIN 200 MILS FROM THE JDIMM3

B B

+0.6V_DDRB_VREFC A

2

CD42

0.1U_0201_ 10V6K

1

Layout Note: Place near JDIMM3

10U_0402_6.3V6M

1

A A

2

1U_0201_6.3V6M

1

CD36

CD46

2

1

2

CD37

10U_0402_6.3V6M

CD47

CD38

2

2.2uF* 1

0.1uF* 1

2

CD43

2.2U_0402_ 6.3V6M

1

10U_0402_6.3V6M

CD48

1

2

10U_0402_6.3V6M

CD49

10uF* 6 1uF*8 330uF* 1

10U_0402_6.3V6M

CD50

1

2

Layout Note: Place near JDIMM3.258

+0.6VS_VTT+2.5V

10U_0402_6.3V6M

1

2

10U_0402_6.3V6M

CD52

CD53

1

2

@

10uF* 2 1uF*1

1U_0201_6.3V6M

10U_0402_6.3V6M

1

CD39

CD41

CD40

2

+1.2V_VDDQ+1.2V_VDDQ

1U_0201_6.3V6M

CD54

@

1

CD57

CD56

2

Interleaved Memory

+3VS

0.1U_0201_10V6K

CD33

2

1

PLACE NEAR TO PIN

1U_0201_6.3V6M

1

2

1U_0201_6.3V6M

1

CD58

2

1U_0201_6.3V6M

1

CD60

CD59

2

+1.2V_VDDQ

2.2U_0402_6.3V6M

+0.6V_DDRB_VREFC A

2

CD34

1

1U_0201_6.3V6M

1

CD61

CD62

2

DDR_B_D[0..15 ]<8>

DDR_B_D[16 ..31]<8>

DDR_B_D[32 ..47]<8>

DDR_B_D[48 ..63]<8>

111 112 117 118 123 124 129 130 135 136

255

164

10 14 15 18 19 22 23 26 27 30 31 35 36 39 40 43 44 47 48 51 52 56 57 60 61 64 65 68 69 72 73 77 78 81 82 85 86 89 90 93 94 98

262

Part Number: SP07001HW00

t Value: S SOCKET LOTES ADDR0205-P001A DDR4 STD

Par

1U_0201_6.3V6M

1

CD63

2

JDIMM2B

STD

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10

VDDSPD

VREFCA

1

VSS

2

VSS

5

VSS

6

VSS

9

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

GND

LOTES_ADDR02 05-P001A

CONN@

VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18 VDD19

VPP1 VPP2

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

GND

141 142 147 148 153 154 159 160 163

258

VTT

257 259

99 102 103 106 107 167 168 171 172 175 176 180 181 184 185 188 189 192 193 196 197 201 202 205 206 209 210 213 214 217 218 222 223 226 227 230 231 234 235 238 239 243 244 247 248 251 252

261

+1.2V_VDDQ

+0.6VS_VTT

+2.5V

+1.2V_VDDQ

2

CD44

0.1U_0201_ 10V6K

1

2

CD51

0.1U_0201_ 10V6K

1

@

1 2

RD19 1K_0402_1%

RD21 1K_0402_1%

DDR_B_CLK 0<8> DDR_B_CLK #0< 8>

DDR_B_CLK #1< 8>

DDR_B_CKE0<8> DDR_B_CKE1<8>

DDR_B_CS# 0<8> DDR_B_CS# 1<8>

DDR_B_ODT 0<8 > DDR_B_ODT 1<8 >

DDR_B_BG0<8> DDR_B_BG1<8> DDR_B_BA0<8 > DDR_B_BA1<8 >

DDR_B_MA0<8> DDR_B_MA1<8> DDR_B_MA2<8> DDR_B_MA3<8> DDR_B_MA4<8> DDR_B_MA5<8> DDR_B_MA6<8> DDR_B_MA7<8> DDR_B_MA8<8> DDR_B_MA9<8> DDR_B_MA10<8> DDR_B_MA11<8> DDR_B_MA12<8> DDR_B_MA13<8> DDR_B_MA14_ WE#<8> DDR_B_MA15_ CAS#<8> DDR_B_MA16_ RAS#<8>

DDR_B_ACT#<8>

DDR_B_PAR<8>

DDR_B_ALERT #<8>

RD18

240_0402_ 1%

DDR_DRAMRST #_R<1 8,23>

DIMM Side

+0.6V_DDRB_VREFC A

STD

DDR_B_CLK 1<8>

12

D_CK_SDATA<18,23> D_CK_SCLK<18,23>

For ECC DIMM

1 2

RD20

2_0402_1%

2

CD45

0.1U_0201_ 10V6K

1

DIMM3_CHB_EVENT # DDR_DRAMRST #_R

+3VS

(4 mm)BOT

DDR_B_CLK 0 DDR_B_CLK #0 DDR_B_CLK 1 DDR_B_CLK #1

DDR_B_CKE0 DDR_B_CKE1

DDR_B_CS# 0 DDR_B_CS# 1

DDR_B_ODT 0 DDR_B_ODT 1

DDR_B_BG0 DDR_B_BG1 DDR_B_BA0 DDR_B_BA1

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14_ WE# DDR_B_MA15_ CAS# DDR_B_MA16_ RAS#

DDR_B_ACT#

DDR_B_PAR DDR_B_ALERT #

CPU Side

1

CD55

0.022U_040 2_16V7K

2

RD22

24.9_0402_1 %

1 2

JDIMM2A

STD

137

CK0(T)

139

CK0#(C)

138

CK1(T)

140

CK1#(C)

109

CKE0

110

CKE1

149

S0#

157

S1#

162

S2#/C0

165

S3#/C1

155

ODT0

161

ODT1

115

BG0

113

BG1

150

BA0

145

BA1

144

A0

133

A1

132

A2

131

A3

128

A4

126

A5

127

A6

122

A7

125

A8

121

A9

146

A10_AP

120

A11

119

A12

158

A13

151

A14_WE#

156

A15_CAS#

152

A16_RAS#

114

ACT#

143

PARITY

116

ALERT#

134

EVENT#

108

RESET#

254

SDA

253

SCL

166

SA2

260

SA1

256

SA0

92

CB0_NC

91

CB1_NC

101

CB2_NC

105

CB3_NC

88

CB4_NC

87

CB5_NC

100

CB6_NC

104

CB7_NC

97

DQS8(T)

95

DQS8#(C)

12

DM0#/DBI0#

33

DM1#/DBI1#

54

DM2#/DBI2#

75

DM3#/DBI3#

178

DM4#/DBI4#

199

DM5#/DBI5#

220

DM6#/DBI6#

241

DM7#/DBI7#

96

DM8#/DBI8#

261

GND1

262

GND2

LOTES_ADDR02 05-P001A

CONN@

+0.6V_B_VREFDQ

VREF traces should be at least 20 mils wide with 20 mils spacing to other sign als

DQS0(T)

DQS0#(C)

DQS1(T)

DQS1#(C)

DQS2(T)

DQS2#(C)

DQS3(T)

DQS3#(C)

DQS4(T)

DQS4#(C)

DQS5(T)

DQS5#(C)

DQS6(T)

DQS6#(C)

DQS7(T)

DQS7#(C)

DQ10 DQ11 DQ12 DQ13 DQ14 DQ15

DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23

DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31

DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39

DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47

DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55

DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63

DDR_B_D0

8

DQ0

DDR_B_D1

7

DQ1

DDR_B_D2

20

DQ2

DDR_B_D3

21

DQ3

DDR_B_D4

4

DQ4

DDR_B_D5

3

DQ5

DDR_B_D6

16

DQ6

DDR_B_D7

17

DQ7

DQ8 DQ9

DDR_B_DQS0

13

DDR_B_DQS# 0

11

DDR_B_D8

28

DDR_B_D9

29

DDR_B_D11

41

DDR_B_D15

42

DDR_B_D14

24

DDR_B_D10

25

DDR_B_D12

38

DDR_B_D13

37

DDR_B_DQS1

34

DDR_B_DQS# 1

32

DDR_B_D16

50

DDR_B_D17

49

DDR_B_D19

62

DDR_B_D20

63

DDR_B_D22

46

DDR_B_D18

45

DDR_B_D23

58

DDR_B_D21

59

DDR_B_DQS2

55

DDR_B_DQS# 2

53

DDR_B_D30

70

DDR_B_D25

71

DDR_B_D26

83

DDR_B_D24

84

DDR_B_D28

66

DDR_B_D27

67

DDR_B_D29

79

DDR_B_D31

80

DDR_B_DQS3

76

DDR_B_DQS# 3

74

DDR_B_D34

174

DDR_B_D35

173

DDR_B_D36

187

DDR_B_D32

186

DDR_B_D39

170

DDR_B_D38

169

DDR_B_D37

183

DDR_B_D33

182

DDR_B_DQS4

179

DDR_B_DQS# 4

177

DDR_B_D40

195

DDR_B_D41

194

DDR_B_D42

207

DDR_B_D43

208

DDR_B_D44

191

DDR_B_D45

190

DDR_B_D46

203

DDR_B_D47

204

DDR_B_DQS5

200

DDR_B_DQS# 5

198

DDR_B_D48

216

DDR_B_D52

215

DDR_B_D50

228

DDR_B_D55

229

DDR_B_D51

211

DDR_B_D54

212

DDR_B_D49

224

DDR_B_D53

225

DDR_B_DQS6

221

DDR_B_DQS# 6

219

DDR_B_D61

237

DDR_B_D57

236

DDR_B_D60

249

DDR_B_D56

250

DDR_B_D62

232

DDR_B_D59

233

DDR_B_D63

245

DDR_B_D58

246

DDR_B_DQS7

242

DDR_B_DQS# 7

240

DDR_B_DQS# 0 <8>

DDR_B_DQS# 1 <8>

DDR_B_DQS# 2 <8>

DDR_B_DQS# 3 <8>

DDR_B_DQS# 4 <8>

DDR_B_DQS# 5 <8>

DDR_B_DQS# 6 <8>

DDR_B_DQS# 7 <8>

DDR_B_DQS0 <8>

DDR_B_DQS1 <8>

DDR_B_DQS2 <8>

DDR_B_DQS3 <8>

DDR_B_DQS4 <8>

DDR_B_DQS5 <8>

DDR_B_DQS6 <8>

DDR_B_DQS7 <8>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2017/10/30 2018/10/30

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Re v

Date : Sheet o f

2

Date : Sheet o f

Compal Electronics, Inc.

DDRIV_CHB: DIMM0

EH5VF M/B LA-H501P

1

1A

24 1 01Friday, February 22, 2019

1A

5

D D

C C

4

3

2

1

Reserve Page

B B

A A

Security Cl assification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2017/11/23 2017/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document N umber Re v

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

N18E-GDDR6_D

EH5VF M/B LA-H501P

1

1A

25 101Friday, February 22, 2019

1A

5

D D

C C

4

3

2

1

Reserve Page

B B

A A

Security Cl assification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2017/11/23 2017/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document N umber Re v

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

N18E-GDDR6_D

EH5VF M/B LA-H501P

1

1A

26 101Friday, February 22, 2019

1A

A

UV1A

PEX_TREMP

1

IN B

2

IN A

+1.8VSDGPU_AON

AN12

AM12

AN14

AM14

AP14 AP15 AN15

AM15

AN17

AM17

AP17 AP18 AN18

AM18

AN20

AM20

AP20 AP21 AN21

AM21

AN23

AM23

AP23 AP24 AN24

AM24

AN26

AM26

AP26 AP27 AN27

AM27

AK14 AJ14 AH14 AG14 AK15 AJ15 AL16 AK16 AK17 AJ17 AH17 AG17 AK18 AJ18 AL19 AK19 AK20 AJ20 AH20 AG20 AK21 AJ21 AL22 AK22 AK23 AJ23 AH23 AG23 AK24 AJ24 AL25 AK25

AJ11

AL13 AK13 AK12

AJ26 AK26

AJ12 AP29

N18P-G0_FCBGA960~D

@

UV2 NL17SZ08DFT2G_SC70-5

5

VGA@

VCC

4

OUT Y

GND

RV16 100K_0201_5%VGA@

3

CV200 0.1U_0 201_10V6K

PEG_CTX_C_GRX_P0<9> PEG_CTX_C_GRX_N0<9> PEG_CTX_C_GRX_P1<9> PEG_CTX_C_GRX_N1<9> PEG_CTX_C_GRX_P2<9> PEG_CTX_C_GRX_N2<9> PEG_CTX_C_GRX_P3<9> PEG_CTX_C_GRX_N3<9> PEG_CTX_C_GRX_P4<9> PEG_CTX_C_GRX_N4<9> PEG_CTX_C_GRX_P5<9>

CLK_PEG_VGA<15> CLK_PEG_VGA#<15>

PEG_CTX_C_GRX_N5<9> PEG_CTX_C_GRX_P6<9> PEG_CTX_C_GRX_N6<9> PEG_CTX_C_GRX_P7<9> PEG_CTX_C_GRX_N7<9> PEG_CTX_C_GRX_P8<9> PEG_CTX_C_GRX_N8<9> PEG_CTX_C_GRX_P9<9> PEG_CTX_C_GRX_N9<9> PEG_CTX_C_GRX_P10<9> PEG_CTX_C_GRX_N10<9> PEG_CTX_C_GRX_P11<9> PEG_CTX_C_GRX_N11<9> PEG_CTX_C_GRX_P12<9> PEG_CTX_C_GRX_N12<9> PEG_CTX_C_GRX_P13<9> PEG_CTX_C_GRX_N13<9> PEG_CTX_C_GRX_P14<9> PEG_CTX_C_GRX_N14<9> PEG_CTX_C_GRX_P15<9> PEG_CTX_C_GRX_N15<9>

PEG_CRX_C_GTX_P0<9> PEG_CRX_C_GTX_N0<9> PEG_CRX_C_GTX_P1<9> PEG_CRX_C_GTX_N1<9> PEG_CRX_C_GTX_P2<9> PEG_CRX_C_GTX_N2<9> PEG_CRX_C_GTX_P3<9> PEG_CRX_C_GTX_N3<9> PEG_CRX_C_GTX_P4<9> PEG_CRX_C_GTX_N4<9> PEG_CRX_C_GTX_P5<9> PEG_CRX_C_GTX_N5<9> PEG_CRX_C_GTX_P6<9> PEG_CRX_C_GTX_N6<9> PEG_CRX_C_GTX_P7<9> PEG_CRX_C_GTX_N7<9> PEG_CRX_C_GTX_P8<9> PEG_CRX_C_GTX_N8<9> PEG_CRX_C_GTX_P9<9> PEG_CRX_C_GTX_N9<9> PEG_CRX_C_GTX_P10<9> PEG_CRX_C_GTX_N10<9> PEG_CRX_C_GTX_P11<9> PEG_CRX_C_GTX_N11<9> PEG_CRX_C_GTX_P12<9> PEG_CRX_C_GTX_N12<9> PEG_CRX_C_GTX_P13<9> PEG_CRX_C_GTX_N13<9> PEG_CRX_C_GTX_P14<9> PEG_CRX_C_GTX_N14<9> PEG_CRX_C_GTX_P15<9> PEG_CRX_C_GTX_N15<9>

RV7 10K_0201_5%VGA@

PLT_RST#

DGPU_HOLD_RST#

VGA_CLKREQ#_R

1 2

PLTRST_VGA#_1V8

1 2

RV10

VGA@

2.49K_0402_1%

No support S0ix

1 1

2 2

+1.8VSDGPU_AON

3 3

PLT_RST#<16,58,66>

DGPU_HOLD_RST#<19>

PEX_RX0 PEX_RX0_N PEX_RX1 PEX_RX1_N PEX_RX2 PEX_RX2_N PEX_RX3 PEX_RX3_N PEX_RX4 PEX_RX4_N PEX_RX5 PEX_RX5_N PEX_RX6 PEX_RX6_N PEX_RX7 PEX_RX7_N PEX_RX8 PEX_RX8_N PEX_RX9 PEX_RX9_N PEX_RX10 PEX_RX10_N PEX_RX11 PEX_RX11_N PEX_RX12 PEX_RX12_N PEX_RX13 PEX_RX13_N PEX_RX14 PEX_RX14_N PEX_RX15 PEX_RX15_N

PEX_TX0 PEX_TX0_N PEX_TX1 PEX_TX1_N PEX_TX2 PEX_TX2_N PEX_TX3 PEX_TX3_N PEX_TX4 PEX_TX4_N PEX_TX5 PEX_TX5_N PEX_TX6 PEX_TX6_N PEX_TX7 PEX_TX7_N PEX_TX8 PEX_TX8_N PEX_TX9 PEX_TX9_N PEX_TX10 PEX_TX10_N PEX_TX11 PEX_TX11_N PEX_TX12 PEX_TX12_N PEX_TX13 PEX_TX13_N PEX_TX14 PEX_TX14_N PEX_TX15 PEX_TX15_N

PEX_WAKE#

PEX_REFCLK PEX_REFCLK_N PEX_CLKREQ_N

NC NC

PEX_RST_N PEX_TERMP

1 2

VGA@

Part 1 of 7

OVR-M

Thermal Sensor

PCI EXPRESS

+1.8VSDGPU_AON

12

RV100 10K_0201_5%

PLTRST_VGA#_1V8

GPIO

RESI2C

GPCPLL_AVDD

CLK

XTAL_OUTBUFF

EXT_REFCLK_FL

@

ADC_IN_N

I2CC_SDA

XSN_PLLVDD

SP_PLLVDD

VID_PLLVDD

XTAL_OUT

GC6 2.0 function

+3VS

12

RV113

QV8A

VGA@

5

10K_0201_5%

GC6_FB_EN3V3

34

D

G

S

PJT138KA 2N SOT363-6

A

VGA@

4 4

GC6_FB_EN1V8

PJT138KA 2N SOT363-6

RV111

VGA@

100K_0201_5%

2

QV8B

VGA@

12

61

D

G

S

GC6_FB_EN3V3

1VSDGPU_PG<94>

GC6_FB_EN3V3 <19>

DV3

2

3

BAV70W_SOT323-3

VGA@

1

12

GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8

GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19 GPIO20 GPIO21 GPIO22 GPIO23 GPIO24 GPIO25 GPIO26 GPIO27

ADC_IN

TS_AVDD

RES RES RES RES

TS_VREF

I2CB_SCL I2CB_SDA

I2CC_SCL

I2CS_SCL I2CS_SDA

XTAL_IN

1.35VSDGPU_EN <37,93>

RV12 100K_0201_5%

VGA@

B

P6

GC6_FB_EN1V8

M3

GPU_EVENT#_1

L6 P5

1.8VSDGPU_MAIN_EN

P7

FRM_LCK#

L7 M7 N8 L3

VGA_ALERT#

M2 L1 M5

ACIN_BUF

N3 M4 N4 P2

SYS_PEX_RST_MON#

R8 M6 R1 P3 P4 P1 P8

GPU_PEX_RST_HOLD#

T8 L2 R4 R5

HDMI_HPD_GPU#

U3

AN9 AM9

AG10

AK9 AL10 AL9 AP8

AP9

R7 R6

VGA_I2CC_SCL

R2

VGA_I2CC_SDA

R3

VGA_I2CS_SCL

T4

VGA_I2CS_SDA

T3

H26

AD8

AE8

AD7

H3

XTALIN

H2

XTALOUT

XTAL_OUTBUFF

J4

XTAL_SSIN

H1

B

TS_AVDD

1 2

RV385 0_0402_5%N18P@

CV377 1U_0201_6.3V6M

unused pin PH 2K to 1V8AON

1 2

RV86 2K_0402_5%VGA@

1 2

RV85 2K_0402_5%VGA@

1

2

Near H26

RV9 100K_0201_5%VGA@ RV11 10K_0201_5%VGA@

NVVDD_VID <95>

NVVDD_PSI <95>

VRAM_VDD_CTL <93>

VRAM_VREF_CTL <32,33>

DV2

VGA@

RB751S40T1G_SOD523-2

GPIO22_OC_WARN# <36>

FBVDDQ_PSI <93 > GPIO26_FP_FUSE <37>

ADC_IN_P <36> ADC_IN_N <36>

1 2

N18P@

1U_0201_6.3V6M

CV195

CV5

1

VGA@

2

Near

AD8

AD7

1 2 1 2

+1.8VSDGPU_AON

+GPU_PLLVDD

1U_0201_6.3V6M

CV6

1

VGA@

2

Near AE8

DV8

12

4.7U_0402_6.3V6M

1U_0201_6.3V6M

CV3

1

VGA@

2

VGA_OVERT#<29>

VGA@

12

GPU_EVENT# <19>

RB751S40T1G_SOD523-2

DGPU_AC_DETECT <19,58,83>

SM01000JX00 3000ma 33ohm@100mhz DCR 0.04

1

CV42

VGA@

2

LV1 TAI-TECH HCB1608KF-330T30

22U_0603_6.3V6M

1

CV4

VGA@

2

Near GPU

VGA_OVERT#

VGA@

1 2

SM01000JX00

+1.8VSDGPU_MAIN

QV1B

PJT138KA 2N SOT363-6

VGA@

2

12

61

D

G

S

C

+1.8VSDGPU_MAIN

RV131 100K_0201_5%

VGA@

C

G

5

HDMI_HPD_PCH<16,40>

1.35VSDGPU_PG<93>

1.8VSDGPU_MAIN_EN

PU at EC side

34

D

QV1A

S

PJT138KA 2N SOT363-6

VGA@

QV13A

PJT138KA 2N SOT363-6

VGA_I2CC_SCL

PJT138KA 2N SOT363-6

VGA_I2CC_SDA

0.1U_0201_10V6K

PLTRST_VGA#_1V8

NL17SZ08DFT2G_SC70-5

1VSDGPU_PG

PJT138KA 2N SOT363-6

GPU_OVERT# <58>

D

VGA_OVERT# VGA_ALERT# FRM_LCK# ACIN_BUF GPU_EVENT#_1

1.8VSDGPU_MAIN_EN NVVDD_PSI

SYS_PEX_RST_MON# GPU_PEX_RST_HOLD#

FBVDDQ_PSI GPIO22_OC_WARN#

VGA_I2CS_SDA VGA_I2CS_SCL

VGA_I2CC_SDA VGA_I2CC_SCL

NVVDD_PSI

VRAM_VREF_CTL GC6_FB_EN1V8

GPU_PEX_RST_HOLD#

+1.8VSDGPU_MAIN

N18P@

5

34

SGD

QV13B

N18P@

2

G

61

S

D

+1.8VSDGPU_AON +1.8VSDGPU_AON

VGA@

CG340

12

5

1

IN B

VCC

OUT Y

2

IN A

GND

VGA@

3

UG28

+1.8VSDGPU_AON

UV11

VGA@

5

1

IN B

VCC

OUT Y

2

IN A

GND

3

+3VS

12

RV106 100K_0201_5%

VGA@

5

61

D

G

2

QV7A

S

QV7B

VGA@

GPU_OVERT#

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY P ROPERTY OF COMPAL ELECTRONICS , INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY P ROPERTY OF COMPAL ELECTRONICS , INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUS TODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUS TODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUS TODY OF THE C OMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHE R THIS SHEET NOR THE INFORM ATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHE R THIS SHEET NOR THE INFORM ATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHE R THIS SHEET NOR THE INFORM ATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS , INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS , INC.

VGA_I2CC_SCL_PWR <95>

VGA_I2CC_SDA_PWR <95>

XTALOUT

12

VGA@

RG180 10K_0201_5%

HDMI_HPD_GPU#

61

D

G

2

4

12

34

D

G

S

QV5B

S

PJT138KA 2N SOT363-6

1

VGA@

@

CV201

0.1U_0201_10V6K

2

+1.8VSDGPU_AON

RV83

@

10K_0201_5%

1 2

ALL_GPWRGD

1

VGA@

CV226

0.1U_0201_10V6K

2

VGA@

RV108 10K_0201_5%

PJT138KA 2N SOT363-6

1 2

DV7

RB751S40T1G_SOD523-2

VGA@

2017/10/30 2018/10/30

PU at PCH side

34

QV5A

D

G

5

PJT138KA 2N SOT363-6

S

VGA@

VGA_CLKREQ#_R

1.8VSDGPU_MAIN_EN3V3 <37>

+3VS

UV10

5

NL17SZ08DFT2G_SC70-5

1

IN B

VCC OUT Y

2

IN A

GND

3

Compal Secret Data

D

Deciphered Date

RV80 470_0402_1%

18P_0402_50V8J

VGA_CLKREQ# <15>

VGA@

4

QV2A

PJT138KA 2N SOT363-6

VGA_I2CS_SCL

PJT138KA 2N SOT363-6

VGA_I2CS_SDA

VGA@

XTALOUT_R

12

CV1

VGA@

@

DV4

RB751S40T1G_SOD523-2

RV105 12K_0402_1%

VGA@

1 2

DV5

RB751S40T1G_SOD523-2

1 2

RV103

28.7K_0402_1%

VGA@

RV327 10K_0201_5%VGA@ RV328 10K_0201_5%VGA@ RV329 10K_0201_5%VGA@ RV330 10K_0201_5%VGA@ RV331 10K_0201_5%VGA@ RV1 10K_0201_5%VGA@ RV4 10K_0201_5%VGA@

RV332 10K_0201_5%N17P@ RV82 10K _0201_5%N17P@

RV335 10K_0201_5%N18P@ RV386 10K_0201_5%N18P@

1 2

RV2 1.8K_0402_1%VGA@

1 2

RV3 1.8K_0402_1%VGA@

1 2

RV5 2K_0402_5%VGA@

1 2

RV6 2K_0402_5%VGA@

RV398 10K_0201_5%@

RV333 100K_0201_5%VGA@ RV334 10K_0201_5%VGA@

RV396 100K_0201_5%N18P@

+1.8VSDGPU_MAIN

VGA@

5

34

SGD

QV2B

VGA@

2

G

S

D

27MHZ_10PF_XRCGB27M000F2P18R0 XV1

1

VGA@

2

Crystals must have a max ESR of 80 ohm

12

2

CV197

0.22U_0402_16V7K

1

2

CV196

0.22U_0402_16V7K

1

E

+1.8VSDGPU_AON

12 12 12 12 12 12 12

12 12

12

12 12

12

PCH_SML1CLK <18,58,66>

61

NC

2

4

GPUCORE_EN < 37>

NVVDD1_EN <37,95>DGPU_PWR_EN <19,37>

VGA@

1VSDGPU_EN <94>

VGA@

Title

Size

Custom

Date : Sheet of

PCH_SML1DATA <18,58,66>

3

XTALIN

3

1

CV2

VGA@

18P_0402_50V8J

2

Compal Electronics, Inc.

N17P PEG 1/7

Document Number Re v

EH5VF M/B LA-H501P

N17P PEG 1/7

E

1A

27 101Friday, February 22, 2019

1A

A

FBA_D[63..0]< 32>

1 1

2 2

FBA_DBI[7..0]<32>

FBA_EDC[7..0]<32>

3 3

FBA_D0 FBA_D1 FBA_D2 FBA_D3 FBA_D4 FBA_D5 FBA_D6 FBA_D7 FBA_D8 FBA_D9 FBA_D10 FBA_D11 FBA_D12 FBA_D13 FBA_D14 FBA_D15 FBA_D16 FBA_D17 FBA_D18 FBA_D19 FBA_D20 FBA_D21 FBA_D22 FBA_D23 FBA_D24 FBA_D25 FBA_D26 FBA_D27 FBA_D28 FBA_D29 FBA_D30 FBA_D31 FBA_D32 FBA_D33 FBA_D34 FBA_D35 FBA_D36 FBA_D37 FBA_D38 FBA_D39 FBA_D40 FBA_D41 FBA_D42 FBA_D43 FBA_D44 FBA_D45 FBA_D46 FBA_D47 FBA_D48 FBA_D49 FBA_D50 FBA_D51 FBA_D52 FBA_D53 FBA_D54 FBA_D55 FBA_D56 FBA_D57 FBA_D58 FBA_D59 FBA_D60 FBA_D61 FBA_D62 FBA_D63

FBA_DBI0 FBA_DBI1 FBA_DBI2 FBA_DBI3 FBA_DBI4 FBA_DBI5 FBA_DBI6 FBA_DBI7

FBA_EDC0 FBA_EDC1 FBA_EDC2 FBA_EDC3 FBA_EDC4 FBA_EDC5 FBA_EDC6 FBA_EDC7

UV1B

L28

FBA_D0

M29

FBA_D1

L29

FBA_D2

M28

FBA_D3

N31

FBA_D4

P29

FBA_D5

R29

FBA_D6

P28

FBA_D7

J28

FBA_D8

H29

FBA_D9

J29

FBA_D10

H28

FBA_D11

G29

FBA_D12

E31

FBA_D13

E32

FBA_D14

F30

FBA_D15

C34

FBA_D16

D32

FBA_D17

B33

FBA_D18

C33

FBA_D19

F33

FBA_D20

F32

FBA_D21

H33

FBA_D22

H32

FBA_D23

P34

FBA_D24

P32

FBA_D25

P31

FBA_D26

P33

FBA_D27

L31

FBA_D28

L34

FBA_D29

L32

FBA_D30

L33

FBA_D31

AG28

FBA_D32

AF29

FBA_D33

AG29

FBA_D34

AF28

FBA_D35

AD30

FBA_D36

AD29

FBA_D37

AC29

FBA_D38

AD28

FBA_D39

AJ29

FBA_D40

AK29

FBA_D41

AJ30

FBA_D42

AK28

FBA_D43

AM29

FBA_D44

AM31

FBA_D45

AN29

FBA_D46

AM30

FBA_D47

AN31

FBA_D48

AN32

FBA_D49

AP30

FBA_D50

AP32

FBA_D51

AM33

FBA_D52

AL31

FBA_D53

AK33

FBA_D54

AK32

FBA_D55

AD34

FBA_D56

AD32

FBA_D57

AC30

FBA_D58

AD33

FBA_D59

AF31

FBA_D60

AG34

FBA_D61

AG32

FBA_D62

AG33

FBA_D63

P30

FBA_DQM0

F31

FBA_DQM1

F34

FBA_DQM2

M32

FBA_DQM3

AD31

FBA_DQM4

AL29

FBA_DQM5

AM32

FBA_DQM6

AF34

FBA_DQM7

M31

FBA_DQS_WP0

G31

FBA_DQS_WP1

E33

FBA_DQS_WP2

M33

FBA_DQS_WP3

AE31

FBA_DQS_WP4

AK30

FBA_DQS_WP5

AN33

FBA_DQS_WP6

AF33

FBA_DQS_WP7

M30

RES

H30

RES

E34

RES

M34

RES

AF30

RES

AK31

RES

AM34

RES

AF32

RES

N18P-G0_FCBGA96 0~D

@

Part 2 of 7

MEMORY INTERFACE

FBA_CMD0 FBA_CMD1 FBA_CMD2 FBA_CMD3 FBA_CMD4 FBA_CMD5 FBA_CMD6 FBA_CMD7 FBA_CMD8

FBA_CMD9 FBA_CMD10 FBA_CMD11 FBA_CMD12 FBA_CMD13 FBA_CMD14 FBA_CMD15 FBA_CMD16 FBA_CMD17 FBA_CMD18 FBA_CMD19 FBA_CMD20 FBA_CMD21 FBA_CMD22 FBA_CMD23 FBA_CMD24 FBA_CMD25 FBA_CMD26 FBA_CMD27 FBA_CMD28 FBA_CMD29 FBA_CMD30 FBA_CMD31 FBA_CMD32 FBA_CMD33 FBA_CMD34 FBA_CMD35

FBA_CLK0

FBA_CLK0_N

FBA_CLK1

FBA_CLK1_N

FBA_WCK01

FBA_WCK01_N

FBA_WCK23

FBA_WCK23_N

FBA_WCK45

FBA_WCK45_N

FBA_WCK67

FBA_WCK67_N

A

FBA_WCKB01

FBA_WCKB01_N

FBA_WCKB23

FBA_WCKB23_N

FBA_WCKB45

FBA_WCKB45_N

FBA_WCKB67

FBA_WCKB67_N

FB_REFPLL_AVDD

FBA_PLL_AVDD

FB_VREF

U30 T31 U29 R34 R33 U32 U33 U28 V28 V29 V30 U34 U31 V34 V33 Y32 AA31 AA29 AA28 AC34 AC33 AA32 AA33 Y28 Y29 W31 Y30 AA34 Y31 Y34 Y33 V31 R28 AC28 R32 AC32

R30 R31 AB31 AC31

K31 L30 H34 J34 AG30 AG31 AJ34 AK34

J30 J31 J32 J33 AH31 AJ31 AJ32 AJ33

K27

U27

H31

B

FBA_CMD0 FBA_CMD1 FBA_CMD2 FBA_CMD3 FBA_CMD4 FBA_CMD5 FBA_CMD6 FBA_CMD7 FBA_CMD8 FBA_CMD9 FBA_CMD10 FBA_CMD11 FBA_CMD12 FBA_CMD13 FBA_CMD14 FBA_CMD15 FBA_CMD16 FBA_CMD17 FBA_CMD18 FBA_CMD19 FBA_CMD20 FBA_CMD21 FBA_CMD22 FBA_CMD23 FBA_CMD24 FBA_CMD25 FBA_CMD26 FBA_CMD27 FBA_CMD28 FBA_CMD29 FBA_CMD30 FBA_CMD31

+FB_PLLAVDD

FB_VREF

FBA_CMD[31..0] <32> FBB_D[63..0]< 33>

FBA_CLKA0 <32> FBA_CLKA0# <32> FBA_CLKA1 <32> FBA_CLKA1# <32>

FBA_WCK01 <32 > FBA_WCK01# <3 2> FBA_WCK23 <32 > FBA_WCK23# <3 2> FBA_WCK45 <32 > FBA_WCK45# <3 2> FBA_WCK67 <32 > FBA_WCK67# <3 2>

+1.8VSDGPU_MAIN

1 2

LV3 TAI-TECH HCB160 8KF-330T30

4.7U_0402_6.3V6M

1

2

Near U27

FBA_CMD14

FBA_CMD30

FBA_CMD13

FBA_CMD29

1U_0201_6.3V6M

CV9

VGA@

Near K27

RV87 10K_0402_5%

RV88 10K_0402_5%

RV89 10K_0402_5%

RV90 10K_0402_5%

22U_0603_6.3V6M

1U_0201_6.3V6M

CV10

1

VGA@

2

VGA@

CV11

1

VGA@

2

+1.35VSDGPU

12

CV379

1

SM01000JX00

SM01000J X00

VGA@

30

00ma 33ohm@100mhz DCR 0.04

2

VGA@

FB_VREF

C

UV1C

FBB_D0

G9

FBB_D1

E9

FBB_D2

G8

FBB_D3

F9

FBB_D4

F11

FBB_D5

G11

FBB_D6

F12

FBB_D7

G12

FBB_D8

G6

FBB_D9

F5

FBB_D10

E6

FBB_D11

F6

FBB_D12

F4

FBB_D13

G4

FBB_D14

E2

FBB_D15

F3

FBB_D16

C2

FBB_D17

D4

FBB_D18

D3

FBB_D19

C1

FBB_D20

B3

FBB_D21

C4

FBB_D22

B5

FBB_D23

C5

FBB_D24

A11

FBB_D25

C11

FBB_D26

D11

FBB_D27

B11

FBB_D28

D8

FBB_D29

A8

FBB_D30

C8

FBB_D31

B8

FBB_D32

F24

FBB_D33

G23

FBB_D34

E24

FBB_D35

G24

FBB_D36

D21

FBB_D37

E21

FBB_D38

G21

FBB_D39

F21

FBB_D40

G27

FBB_D41

D27

FBB_D42

G26

FBB_D43

E27

FBB_D44

E29

FBB_D45

F29

FBB_D46

E30

FBB_D47

D30

FBB_D48

A32

FBB_D49

C31

FBB_D50

C32

FBB_D51

B32

FBB_D52

D29

FBB_D53

A29

FBB_D54

C29

FBB_D55

B29

FBB_D56

B21

FBB_D57

C23

FBB_D58

A21

FBB_D59

C21

FBB_D60

B24

FBB_D61

C24

FBB_D62

B26

FBB_D63

FBB_DBI[7..0]<33>

FBB_EDC[7..0]<33>

CV378

3.9P_0402_50V8C

RV393

49.9_0402_1%

12

1

N18P@

2

FBB_DBI0 FBB_DBI1 FBB_DBI2 FBB_DBI3 FBB_DBI4 FBB_DBI5 FBB_DBI6 FBB_DBI7

FBB_EDC0 FBB_EDC1 FBB_EDC2 FBB_EDC3 FBB_EDC4 FBB_EDC5 FBB_EDC6 FBB_EDC7

C26

E11

E3 A3

C9 F23 F27 C30 A24

D10

D5

C3

B9 E23 E28 B30 A23

D9

E4

B2

A9 D22 D28 A30 B23

CKE

signal

RST signal

Part 3 of 7

FBB_D0 FBB_D1 FBB_D2 FBB_D3 FBB_D4 FBB_D5 FBB_D6 FBB_D7 FBB_D8 FBB_D9 FBB_D10 FBB_D11 FBB_D12 FBB_D13 FBB_D14 FBB_D15 FBB_D16 FBB_D17 FBB_D18 FBB_D19 FBB_D20 FBB_D21 FBB_D22 FBB_D23 FBB_D24 FBB_D25 FBB_D26 FBB_D27 FBB_D28 FBB_D29 FBB_D30 FBB_D31 FBB_D32 FBB_D33 FBB_D34 FBB_D35 FBB_D36 FBB_D37 FBB_D38 FBB_D39 FBB_D40 FBB_D41 FBB_D42 FBB_D43 FBB_D44 FBB_D45 FBB_D46 FBB_D47 FBB_D48 FBB_D49 FBB_D50 FBB_D51 FBB_D52 FBB_D53 FBB_D54 FBB_D55 FBB_D56 FBB_D57 FBB_D58 FBB_D59 FBB_D60 FBB_D61 FBB_D62 FBB_D63

FBB_DQM0 FBB_DQM1 FBB_DQM2 FBB_DQM3 FBB_DQM4 FBB_DQM5 FBB_DQM6 FBB_DQM7

FBB_DQS_WP0 FBB_DQS_WP1 FBB_DQS_WP2 FBB_DQS_WP3 FBB_DQS_WP4 FBB_DQS_WP5 FBB_DQS_WP6 FBB_DQS_WP7

RES RES RES RES RES RES RES RES

N18P-G0_FCBGA96 0~D

@

FBB_CMD14

FBB_CMD30

FBB_CMD13

FBB_CMD29

D

FBB_CMD0 FBB_CMD1 FBB_CMD2 FBB_CMD3 FBB_CMD4 FBB_CMD5 FBB_CMD6 FBB_CMD7 FBB_CMD8

FBB_CMD9 FBB_CMD10 FBB_CMD11 FBB_CMD12 FBB_CMD13 FBB_CMD14 FBB_CMD15 FBB_CMD16 FBB_CMD17 FBB_CMD18 FBB_CMD19 FBB_CMD20 FBB_CMD21 FBB_CMD22 FBB_CMD23 FBB_CMD24 FBB_CMD25 FBB_CMD26 FBB_CMD27 FBB_CMD28 FBB_CMD29 FBB_CMD30 FBB_CMD31 FBB_CMD32 FBB_CMD33 FBB_CMD34 FBB_CMD35

FBB_CLK0

FBB_CLK0_N

MEMORY INTERFACE B

FBB_CLK1

FBB_CLK1_N

FBB_WCK01

FBB_WCK01_N

FBB_WCK23

FBB_WCK23_N

FBB_WCK45

FBB_WCK45_N

FBB_WCK67

FBB_WCK67_N

FBB_WCKB01

FBB_WCKB01_N

FBB_WCKB23

FBB_WCKB23_N

FBB_WCKB45

FBB_WCKB45_N

FBB_WCKB67

FBB_WCKB67_N

FBB_PLL_AVDD

12

VGA@

RV91 10K_0402_5%

12

VGA@

RV92 10K_0402_5%

12

VGA@

RV93 10K_0402_5%

12

VGA@

RV94 10K_0402_5%

D13 E14 F14 A12 B12 C14 B14 G15 F15 E15 D15 A14 D14 A15 B15 C17 D18 E18 F18 A20 B20 C18 B18 G18 G17 F17 D16 A18 D17 A17 B17 E17 G14 G20 C12 C20

D12 E12 E20 F20

F8 E8 A5 A6 D24 D25 B27 C27

D6 D7 C6 B6 F26 E26 A26 A27

H17

+1.35VSDGPU

FBB_CMD0 FBB_CMD1 FBB_CMD2 FBB_CMD3 FBB_CMD4 FBB_CMD5 FBB_CMD6 FBB_CMD7 FBB_CMD8 FBB_CMD9 FBB_CMD10 FBB_CMD11 FBB_CMD12 FBB_CMD13 FBB_CMD14 FBB_CMD15 FBB_CMD16 FBB_CMD17 FBB_CMD18 FBB_CMD19 FBB_CMD20 FBB_CMD21 FBB_CMD22 FBB_CMD23 FBB_CMD24 FBB_CMD25 FBB_CMD26 FBB_CMD27 FBB_CMD28 FBB_CMD29 FBB_CMD30 FBB_CMD31

Near H17

1

2

FBB_CLKA0 <33> FBB_CLKA0# <33> FBB_CLKA1 <33> FBB_CLKA1# <33>

FBB_WCK01 <3 3> FBB_WCK01 # <33 > FBB_WCK23 <3 3> FBB_WCK23 # <33 > FBB_WCK45 <3 3> FBB_WCK45 # <33 > FBB_WCK67 <3 3> FBB_WCK67 # <33 >

+FB_PLLAVDD

1U_0201_6.3V6M

CV7

1

VGA@

2

FBB_CMD[31..0] <33>

4.7U_0402_6.3V6M CV12

VGA@

E

GDDR5 Mode H Mapping

DA

Addr ess

CMD0

D1

CM

CMD2

CMD3

CMD4

CMD5

CMD6

CMD7

CMD8

CMD9

CMD10

CMD11

CMD12

CMD13

CMD14

CMD15

CMD16

CMD17

CMD18

CMD19

CMD20

CMD21

CMD22

CMD23

CMD24

CMD25

CMD26

CMD27

CMD28

CMD29

CMD30

CMD31

TA Bus

0..31 32..6 3

CS#

A3_BA 3

A2_BA 0

A4_BA 2

A5_BA 1

WE#

A7_A8

A6_A1 1

ABI#

A12_RF U

A0_A1 0

A1_A9

RAS#

RST#

CKE#

CAS#

CS#

A3_BA 3

A2_BA 0

A4_BA 2

A5_BA 1

WE#

A7_A8

A6_A1 1

ABI#

A12_RF U

A0_A1 0

A1_A9

RAS#

RST#

CKE#

CAS#

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2017/10/30 2018/10/30

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Re v

Custom

Date : Sheet o f

D

Date : Sheet o f

Compal Electronics, Inc.

N17P VRAM 2/7

EH5VF M/B LA-H501P

E

1A

28 1 01Friday, February 22, 2019

1A

A

1 1

GPU_DP2_P0< 40> GPU_DP2_N0<40> GPU_DP2_P1< 40>

HDMI

2.0

2 2

GPU_DP2_N1<40> GPU_DP2_P2< 40> GPU_DP2_N2<40> GPU_DP2_P3< 40> GPU_DP2_N3<40>

GPU_DP2_CT RL_CLK<40> GPU_DP2_CT RL_DAT<40>

UV1D

AM6 AN6 AP3 AN3 AN5 AM5

AL6

AK6

AJ6

AH6

AJ9 AH9 AP6 AP5 AM7

AL7 AN8 AM8 AK8

AL8

AK1

AJ1

AJ3

AJ2 AH3 AH4 AG5 AG4

AM1 AM2 AM3 AM4

AL3

AL4 AK4 AK5

AD2 AD3 AD1 AC1 AC2 AC3 AC4 AC5

AE3 AE4

AF4

AF5 AD4 AD5 AG1

AF1

AG3 AG2

AK3 AK2

AB3 AB4

AF3

AF2

IFPA_L3 IFPA_L3_N IFPA_L2 IFPA_L2_N IFPA_L1 IFPA_L1_N IFPA_L0 IFPA_L0_N IFPA_AUX_SCL IFPA_AUX_SDA_N

IFPB_L3 IFPB_L3_N IFPB_L2 IFPB_L2_N IFPB_L1 IFPB_L1_N IFPB_L0 IFPB_L0_N IFPB_AUX_SCL IFPB_AUX_SDA_N

IFPC_L0 IFPC_L0_N IFPC_L1 IFPC_L1_N IFPC_L2 IFPC_L2_N IFPC_L3 IFPC_L3_N

IFPD_L0 IFPD_L0_N IFPD_L1 IFPD_L1_N IFPD_L2 IFPD_L2_N IFPD_L3 IFPD_L3_N

IFPE_L0 IFPE_L0_N IFPE_L1 IFPE_L1_N IFPE_L2 IFPE_L2_N IFPE_L3 IFPE_L3_N

NC NC NC NC NC NC NC NC

IFPC_AUX_SCL IFPC_AUX_SDA_N

IFPD_AUX_SCL IFPD_AUX_SDA_N

IFPE_AUX_SCL IFPE_AUX_SDA_N

NC NC

Part 4 of 7

TMDS

NC

VDD_SENSE

GND_SENSE

TEST

NVJTAG_SEL

JTAG_TCK

JTAG_TDI JTAG_TDO JTAG_TMS

JTAG_TRST_N

SERIAL

ROM_CS_N

ROM_SCLK

GENERAL

BUFRST_N

THERMDP THERMDN

ROM_SI

ROM_SO

OVERT

STRAP0 STRAP1 STRAP2 STRAP3 STRAP4 STRAP5

B

+1.8VSDGPU_MAIN

AC6

NC

AJ28

NC

AJ4

NC

AJ5

NC

AL11

NC

C15

NC

D19

NC

D20

NC

D23

NC

D26

NC

V32

NC

L4

L5

NVVDD1_VCC_SENSE <95>

NVVDD1_VSS_SENSE < 95>

STRAP0 STRAP1 STRAP2 STRAP3 STRAP4 STRAP5

C

+1.8VSDGPU_AON

RV26 100K_0402_ 5%

@

1 2

RV34 100K_0402_ 5%

@

1 2

RV27 100K_0402_ 5%

@

1 2

RV35 100K_0402_ 5%

@

1 2

MULTI LEVEL STRAPS

strap3strap2strap1str ap0 strap5

RV28 100K_0201_ 5%

@

1 2

RV36 100K_0201_ 5%

@

1 2

RV29 100K_0201_ 5%

VGA@

1 2

RV37 100K_0201_ 5%

@

1 2

strap4

RV30 100K_0201_ 5%

@

1 2

RV38 100K_0201_ 5%

VGA@

1 2

D

RV78 100K_0402_ 5%

@

1 2

RV79 100K_0402_ 5%

VGA@

1 2

RV31 100K_0402_ 5%

N17P@

1 2

RV39 100K_0402_ 5%

N18P@

1 2

RV32 100K_0402_ 5%

N17P@

1 2

RV40 10K_0402_5 %

N18P@

1 2

RV33 100K_0201_ 5%

N17P@

1 2

ROM_SI ROM_SO ROM_SCLK

RV41 100K_0201_ 5%

N18P@

1 2

E

X76 BOM

RV336 10K_0402_5 %

ROM_CS_R# ROM_SO_R

+1.8VSDGPU_AON

12

N18P@

UV49

1

CS#

2

DO(IO1)

3

WP#(IO2)

4

GND

W25Q80EW SSIG_SO8

N18P@

SA00009QP00

D

GPU VBIOS ROM 8Mb

VCC

HOLD#(IO3)

DI(IO0)

8 7 6

CLK

5

+1.8VSDGPU_AON

1

2

ROM_SCLK_R ROM_SI_R

CV355

N18P@

0.1U_0201_ 10V6K

N18P@

RV339 33_0402_5 %

1 2 1 2

RV340 33_0402_5 %

N18P@

ROM_SCLK ROM_SI

AK11

AM10 AM11 AP12 AP11 AN11

H6 H4 H5 H7

E1

M1

J2 J7 J6 J5 J3 J1

K3 K4

TESTMODE

JTAG_TCK_VGA JTAG_TDI JTAG_TDO JTAG_TMS JTAG_RST

ROM_CS# ROM_SCLK ROM_SI ROM_SO

GPU_BUFRST#

STRAP0 STRAP1 STRAP2 STRAP3 STRAP4 STRAP5

1 2

RV42 10K_04 02_5%VGA@

TV5@ TV6@ TV7@ TV8@

1 2

RV43 10K_04 02_5%VGA@

TV9@

VGA_OVERT# <27>

ROM_CS# ROM_SO

N18P@

RV337 33_0402_5 %

1 2 1 2

RV338 0_0402_5%

@

3 3

4 4

A

N18P-G0_FCBGA96 0~D

@

*

SMB_ATL_ADDR

LO

W

High

DEVID_SEL

LOW

High

VGA_DEVICE

LOW

High

PCIE_CFG

LOW

High

Orig. Device ID

Support G-Sync GPUID

Single GPU

Dual GPU

3D Device

VGA Device

Normal signal swing

Reduce the signal amplitude

B

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2017/10/30 2018/10/30

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Re v

Custom

Date : Sheet o f

Compal Electronics, Inc.

N17P STRAP 3/7

EH5VF M/B LA-H501P

E

29 1 01Friday, February 22, 2019

1A

A

+1.35VSDGPU

CHA /6*1uF+2*10 uF

CV395

0.47U_0201_6.3V6K

CV396

0.47U_0201_6.3V6K

1

2

@

CV397

0.47U_0201_6.3V6K

1

2

@

22uF+2*1 0uF

10U_0402_6.3V6M

CV37

1

2

VGA@

10U_0402_6.3V6M

CV217

1

2

@

reserve

1

2

re

0.47U_0201_6.3V6K

serve

CV398

@

10U_0402_6.3V6M

CV38

1

2

VGA@

10U_0402_6.3V6M

CV218

1

2

@

1 1

CHB

*1uF+2*10 uF

/6

GPU /5*

2 2

1U_0201_6.3V6M

1

2

1U_0201_6.3V6M

1

2

1

2

1

2

CV18

1

VGA@

2

CV126

1

VGA@

2

22U_0603_6.3V6M

CV202

VGA@

Place close to GPU

22U_0603_6.3V6M

CV219

@

Under GPU

1U_0201_6.3V6M

CV23

CV19

CV20

1U_0201_6.3V6M

CV21

1U_0201_6.3V6M

1

VGA@

2

CV129

1U_0201_6.3V6M

CV128

1U_0201_6.3V6M

CV127

VGA@

1

VGA@

2

22U_0603_6.3V6M

1

2

22U_0603_6.3V6M

1

2

22U_0603_6.3V6M

CV36

VGA@

CV220

@

CV39

1

2

VGA@

22U_0603_6.3V6M

CV221

1

2

@

1U_0201_6.3V6M

CV22

1U_0201_6.3V6M

1

VGA@

2

CV131

1U_0201_6.3V6M

CV130

1U_0201_6.3V6M

1

VGA@

2

22U_0603_6.3V6M

CV40

1

2

VGA@

22U_0603_6.3V6M

CV222

1

2

@

near GPU for NV update s pec 1210

FB_VDDQ_SENSE<93>

+1.35VSDGPU

3 3

1 2

RV47 40.2_040 2_1%VGA@

1 2

RV48 40.2_040 2_1%VGA@

1 2

N17P@

RV49 60.4_04 02_1%

RV49

40.2_0402_1%

SD034402A80

10U_0402_6.3V6M

1

2

10U_0402_6.3V6M

1

2

22U_0603_6.3V6M

CV41

1

2

VGA@

22U_0603_6.3V6M

CV223

1

2

@

FB_VDDQ_SENSE

N18P@

CV24

VGA@

CV132

VGA@

B

1

2

1

2

TV10@

CV26

10U_0402_6.3V6M

VGA@

CV133

10U_0402_6.3V6M

VGA@

+1.35VSDGPU

@

1 2

FB_GND_SENSE

FB_CAL_PD_VDDQ

FB_CAL_PU_GND

FB_CAL_TERM_ GND

RV45 0_0402_5%

UV1E

AA27

FBVDDQ_0

AA30

FBVDDQ_1

AB27

FBVDDQ_2

AB33

FBVDDQ_3

AC27

FBVDDQ_4

AD27

FBVDDQ_5

AE27

FBVDDQ_6

AF27

FBVDDQ_7

AG27

FBVDDQ_8

B13

FBVDDQ_9

B19

FBVDDQ_11

E13

FBVDDQ_12

E19

FBVDDQ_14

H10

FBVDDQ_15

H11

FBVDDQ_16

H12

FBVDDQ_17

H13

FBVDDQ_18

H14

FBVDDQ_19

H18

FBVDDQ_22

H19

FBVDDQ_23

H20

FBVDDQ_24

H21

FBVDDQ_25

H22

FBVDDQ_26

H23

FBVDDQ_27

H24

FBVDDQ_28

H8

FBVDDQ_29

H9

FBVDDQ_30

L27

FBVDDQ_31

M27

FBVDDQ_32

N27

FBVDDQ_33

P27

FBVDDQ_34

R27

FBVDDQ_35

T27

FBVDDQ_36

T30

FBVDDQ_37

T33

FBVDDQ_38

Y27

FBVDDQ_43

B16

FBVDDQ

E16

FBVDDQ

H15

FBVDDQ

H16

FBVDDQ

V27

FBVDDQ

W27

FBVDDQ

W30

FBVDDQ

W33

FBVDDQ

F1

FBVDDQ_SENSE

F2

PROBE_FB_GND

J27

FB_CAL_PD_VDDQ

H27

FB_CAL_PU_GND

H25

FB_CAL_TERM_GND

N18P-G0_FCBGA96 0~D

@

Part 5 of 7

PEX_HVDD_10 PEX_HVDD_11 PEX_HVDD_12 PEX_HVDD_13

PEX_PLL_HVDD

FP_FUSE_SRC

POWER

IFPAB_PLLVDD

IFPCD_PLLVDD

PEX_DVDD_0 PEX_DVDD_1 PEX_DVDD_2 PEX_DVDD_3 PEX_DVDD_4 PEX_DVDD_5

PEX_HVDD_0 PEX_HVDD_1 PEX_HVDD_2 PEX_HVDD_3 PEX_HVDD_4 PEX_HVDD_5 PEX_HVDD_6 PEX_HVDD_7 PEX_HVDD_8 PEX_HVDD_9

1V8_AON 1V8_AON

IFPAB_RSET

IFPCD_RSET

IFPE_PLLVDD

IFPE_RSET

IFP_IOVDD IFP_IOVDD

AG19 AG21 AG22 AG24 AH21 AH25

AG13 AG15 AG16 AG18 AG25 AH15 AH18 AH26 AH27 AJ27 AK27 AL27 AM28 AN28

AH12

AG12

AG26

NC

J8 K8 L8

NC

M8

NC

AH8 AJ8

AF7 AF8

AB8 AD6

AG8 AG9

AF6 AG6

AC7 AC8

AG7

NC

AN2

NC

C

+FP_FUSE_GPU

12mils

+1.8VSDGPU_MAIN

12

RG38 1K_ 0402_1%

VGA@

2*22uF+3*10uF+3*4.7u F+6*1uF

Under GPU

CV134

1U_0201_6.3V6M

CV13

1U_0201_6.3V6M

1

2

1U_0201_6.3V6M

1

VGA@

2

2*22uF+3*10uF+3*4.7u F+7*1uF

CV381

1U_0201_6.3V6M

CV399

1

2

1U_0201_6.3V6M

Under GP

VGA@

U

1

VGA@

2

1

2

1

2

CV380

1U_0201_6.3V6M

1

VGA@

2

+1.8VSDGPU_MAIN

CV43

1U_0201_6 .3V6M

Near GPU

CV135

1U_0201_6.3V6M

1

VGA@

2

RV394 0_0402_5%N17P@

CV33

1U_0201_6.3V6M

CV14

1

VGA@

2

Under GPU

CV137

1U_0201_6.3V6M

1

VGA@

2

VGA@

*

4.7uF+5*1uF

3

CV49

1U_0201_6.3V6M

1

VGA@

2

12

3*4.7uF+9*1uF

D

Near GPU

CV28

CV29

CV385

1U_0201_6.3V6M

1

VGA@

2

CV136

1U_0201_6.3V6M

1

VGA@

2

CV51

1U_0201_6.3V6M

1

VGA@

2

Near GPU

Under GPU

CV214

1U_0201_6.3V6M

1

VGA@

2

4.7U_0402_6.3V6M

CV386

1U_0201_6.3V6M

1

VGA@

2

1U_0201_6.3V6M

CV25

1U_0201_6.3V6M

1

VGA@

2

CV391

1U_0201_6.3V6M

1

VGA@

2

1U_0201_6.3V6M

1

2

CV16

4.7U_0402_6.3V6M

1

2

CV15

VGA@

CV392

VGA@

1U_0201_6.3V6M

1

2

CV213

VGA@

1

2

VGA@

CV17

4.7U_0402_6.3V6M

CV382

4.7U_0402_6.3V6M

1

2

VGA@

CV393

4.7U_0402_6.3V6M

CV50

4.7U_0402_6.3V6M

1

VGA@

2

0.1U_0201_10V6K

CV52

0.1U_0201_10V6K

1

N17P@

2

CV216

1U_0201_6.3V6M

CV215

1

VGA@

2

Under GPU 1 per ball

CV212

1U_0201_6.3V6M

1

VGA@

2

10U_0402_6.3V6M

CV387

4.7U_0402_6.3V6M

1

2

VGA@

CV32

4.7U_0402_6.3V6M

1

2

VGA@

CV394

4.7U_0402_6.3V6M

1

VGA@

2

2*4.7uF+1*1uF+2*0. 1uF

CV53

1

N17P@

2

Near GPU

+GPU_PLLVDD

4.7U_0402_6.3V6M

CV205

4.7U_0402_6.3V6M

1

2

VGA@

CV388

10U_0402_6.3V6M

1

2

VGA@

CV30

10U_0402_6.3V6M

CV27

10U_0402_6.3V6M

1

2

VGA@

+1.8VSDGPU_AON

CV54

1U_0201_6.3V6M

N17P@

CV204

4.7U_0402_6.3V6M

1

2

VGA@

1

2

Near GPU

1

2

CV203

VGA@

CV389

10U_0402_6.3V6M

VGA@

10U_0402_6.3V6M

1

2

CV55

4.7U_0402_6.3V6M

N17P@

CV34

22U_0603_6.3V6M

1

2

VGA@

+1.8VSDGPU_MAIN

22U_0603_6.3V6M

CV383

1

2

VGA@

+1.8VSDGPU_MAIN

+1.0VSDGPU

1

2

CV31

VGA@

+1.0VSDGPU

22U_0603_6.3V6M

1

2

E

CV390

VGA@

CV384

22U_0603_6.3V6M

VGA@

Near GPU

CV206

1U_0201_6.3V6M

CV207

1U_0201_6.3V6M

CV208

1U_0201_6.3V6M

CV209

1U_0201_6.3V6M

CV210

1U_0201_6.3V6M

CV211

1U_0201_6.3V6M

1

VGA@

2

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2017/10/30 2018/10/30

Under GPU 1 per ball

Compal Secret Data

Deciphered Date

1

VGA@

2

D

1

VGA@

2

Compal Electronics, Inc.

Title

Size Document Number Re v

Custom

Date : Sheet o f

Compal Electronics, Inc.

N17P POWER 4/7

EH5VF M/B LA-H501P

E

1A

30 1 01Friday, February 22, 2019

1A

A

N17P VDDS 1uF*5/4.7uF*5 (under GPU) 330uF*1/22uF *3/10uF*2/4. 7uF*2

+NVVDD1

1 1

2 2

3 3

4 4

AA14 AA21 AB13 AB15 AB17 AB18 AB20 AB22 AC12 AC16 AC19 AC23

AA12 AA16 AA19 AA23 AC14 AC21

AB11 AB24 AD11 AD13 AD15 AD17 AD18 AD20 AD22 AD24

A

UV1G

VDD_1 VDD_4 VDD_6 VDD_7 VDD_8 VDD_9 VDD_10 VDD_11 VDD_12 VDD_14 VDD_15 VDD_17

M12

VDD_18

M16

VDD_20

M19

VDD_21

M23

VDD_23

N13

VDD_24

N15

VDD_25

N17

VDD_26

N18

VDD_27

N20

VDD_28

N22

VDD_29

P14

VDD_31

P21

VDD_34

R13

VDD_36

R15

VDD_37

R17

VDD_38

R18

VDD_39

R20

VDD_40

R22

VDD_41

T12

VDD_42

T16

VDD_44

T19

VDD_45

T23

VDD_47

U13

VDD_48

U15

VDD_49

U18

VDD_51

U20

VDD_52

U22

VDD_53

V13

VDD_54

V15

VDD_55

VDD_72 VDD_73 VDD_74 VDD_75 VDD_76 VDD_77

M14

VDD_78

M21

VDD_79

P12

VDD_80

P16

VDD_81

P19

VDD_82

P23

VDD_83

T14

VDD_84

T21

VDD_85

U17

VDD_86

V18

VDD_87

W14

VDD_88

W21

VDD_89

VDD_90 VDD_91 VDD_92 VDD_93 VDD_94 VDD_95 VDD_96 VDD_97 VDD_98 VDD_95

L11

VDD_96

L13

VDD_97

L15

VDD_98

L17

VDD_99

L18

VDD_100

L20

VDD_101

L22

VDD_102

L24

VDD_103

N11

VDD_104

N24

VDD_105

N18P-G0_FCBGA96 0~D

@

Part 7 of 7

RSVD_VDDS_SENSE RSVD_GNDS_SENSE

POWER

VDD_56 VDD_58 VDD_59 VDD_60 VDD_62 VDD_63 VDD_65 VDD_66 VDD_67 VDD_68 VDD_69 VDD_70 VDD_71

XVDD_4 XVDD_5 XVDD_6 XVDD_7 XVDD_8

XVDD_9 XVDD_10 XVDD_11 XVDD_12 XVDD_13 XVDD_14 XVDD_15 XVDD_16

XVDD_17 XVDD_18 XVDD_19 XVDD_20 XVDD_21 XVDD_22

XVDD_20 XVDD_21 XVDD_22 XVDD_23 XVDD_24 XVDD_25 XVDD_26 XVDD_27

XVDD_28 XVDD_29 XVDD_30 XVDD_31 XVDD_32 XVDD_33 XVDD_34 XVDD_35

VDD_106 VDD_107 VDD_108 VDD_109 VDD_110 VDD_111 VDD_112 VDD_113

V17 V20 V22 W12 W16 W19 W23 Y13 Y15 Y17 Y18 Y20 Y22

U1

NVVDD & NVVDDS merge

U2

confirm NV nc or not

U4 U5 U6 U7 U8

V1 V2 V3 V4 V5 V6 V7 V8

W2 W3 W4 W5 W7 W8

Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8

AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8

R11 R24 U11 U24 V11 V24 Y11 Y24

+NVVDD1

B

AA17 AA18 AA20 AA22 AB12 AB14 AB16 AB19

AB2

AB21

AB23 AB28 AB30 AB32

AB5

AB7 AC13 AC15 AC17 AC18 AA13 AC20 AC22

AE2 AE28 AE30 AE32 AE33

AE5

AE7 AH10 AA15 AH13 AH16 AH19

AH2 AH22 AH24 AH28 AH29 AH30 AH32 AH33

AH5

AH7

AK10

AK7 AL12 AL14 AL15 AL17 AL18

AL20 AL21 AL23 AL24 AL26 AL28 AL30 AL32 AL33

AM13 AM16 AM19 AM22 AM25

AN1 AN10 AN13 AN16 AN19 AN22 AN25 AN30 AN34

AN4

AN7

AP2 AP33

M11

M24

W11

W24

B

UV1F

A2

GND_0 GND_1 GND_2 GND_3 GND_4 GND_5 GND_6 GND_7 GND_8 GND_9 GND_10

A33

GND_11 GND_12 GND_13 GND_14 GND_15 GND_16 GND_17 GND_18 GND_19 GND_20 GND_21 GND_22 GND_23 GND_24 GND_25 GND_26 GND_27 GND_28 GND_29 GND_30 GND_31 GND_32 GND_33 GND_34 GND_35 GND_36 GND_37 GND_38 GND_39 GND_40 GND_41 GND_42 GND_43 GND_44 GND_45 GND_46

AJ7

GND_47 GND_48 GND_49 GND_50 GND_51 GND_52 GND_53 GND_54

AL2

GND_55 GND_56 GND_57 GND_58 GND_59 GND_60 GND_61 GND_62 GND_63 GND_64

AL5

GND_65 GND_66 GND_67 GND_68 GND_69 GND_70 GND_71 GND_72 GND_73 GND_74 GND_75 GND_76 GND_77 GND_78 GND_79 GND_80 GND_81 GND_82 GND_83

B1

GND_84

B10

GND_85

B22

GND_86

B25

GND_87

B28

GND_88

B31

GND_89

B34

GND_90

B4

GND_91

B7

GND_92

C10

GND_93

C13

GND_94

C19

GND_95

C22

GND_96

C25

GND_97

C28

GND_98

C7

GND_99

L21

GND_214

L23

GND_215 GND_216 GND_217

P11

GND_218

T11

GND_219

T24

GND_220 GND_221 GND_222

P24

GND_223

N18P-G0_FCBGA96 0~D

@

C

Part 6 of 7

GND

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

GND_100 GND_101 GND_102 GND_103 GND_104 GND_105 GND_106 GND_107 GND_108 GND_109 GND_110 GND_111 GND_112 GND_113 GND_114 GND_115 GND_116 GND_117 GND_118 GND_119 GND_120 GND_121 GND_122 GND_123 GND_124 GND_125 GND_126 GND_127 GND_128 GND_129 GND_130 GND_131 GND_132 GND_133 GND_134 GND_135 GND_136 GND_137 GND_138 GND_139 GND_140 GND_141 GND_142 GND_143 GND_144 GND_145 GND_146 GND_147 GND_148 GND_149 GND_150 GND_151 GND_152 GND_153 GND_154 GND_155 GND_156 GND_157 GND_158 GND_159 GND_160 GND_161 GND_162 GND_163 GND_164 GND_165 GND_166 GND_167 GND_168 GND_169 GND_170 GND_171 GND_172 GND_173 GND_174 GND_175 GND_176 GND_177 GND_178 GND_179 GND_180 GND_181 GND_182 GND_183 GND_184 GND_185 GND_186 GND_187 GND_188 GND_189 GND_190 GND_191 GND_192 GND_193 GND_194 GND_195 GND_196 GND_197 GND_198

GND_200 GND_201 GND_202 GND_203 GND_204 GND_205 GND_206 GND_207 GND_208 GND_209 GND_210 GND_211 GND_212 GND_213

GND_OPT GND_OPT

D2 D31 D33 E10 E22 E25 E5 E7 F28 F7 G10 G13 G16 G19 G2 G22 G25 G28 G3 G30 G32 G33 G5 G7 K2 K28 K30 K32 K33 K5 K7 M13 M15 M17 M18 M20 M22 N12 N14 N16 N19 N2 N21 N23 N28 N30 N32 N33 N5 N7 P13 P15 P17 P18 P20 P22 R12 R14 R16 R19 R21 R23 T13 T15 T17 T18 T2 T20 T22 AG11 T28 T32 T5 T7 U12 U14 U16 U19 U21 U23 V12 V14 V16 V19 V21 V23 W13 W15 W17 W18 W20 W22 W28 Y12 Y14 Y16 Y19 Y21 Y23

AA11 AA24 AC11 AC24 AD12 AD14 AD16 AD19 AD21 AD23 L12 L14 L16 L19

AH11

RV395 0_0402_5%N17P@

NC

C16 W32

2017/10/30 2018/10/30

12

Compal Secret Data

D

Deciphered Date

D

E

Compal Electronics, Inc.

Title

Size Document Number Re v

Custom

Date : Sheet o f

Compal Electronics, Inc.

N17P POWER & GND 5/7

EH5VF M/B LA-H501P

E

31 1 01Friday, February 22, 2019

1A

A

B

C

D

E

MF=1

FBA_D[63:0]<28>

FBA_CMD6<28> FBA_CMD11<28> FBA_CMD10<28> FBA_CMD7<28> FBA_CMD9<28>

FBA_CMD2<28>

1 1

FBA_CMD4<28> FBA_CMD3<28> FBA_CMD1<28>

FBA_CMD8<28> FBA_CMD12<28> FBA_CMD0<28> FBA_CMD15<28> FBA_CMD5<28>

FBA_CLKA0<28> FBA_CLKA0#<28> FBA_CMD14<28>

FBA_DBI0<28> FBA_DBI1<28> FBA_DBI2<28> FBA_DBI3<28>

FBA_CMD13<28>

FBA_WCK01<28> FBA_WCK01#<28>

FBA_WCK23<28> FBA_WCK23#<28>

2 2

+1.35VSDGPU

CV61

1U_0201_6.3V6M

CV62

1U_0201_6.3V6M

1

VRAM4G@

2

1

3 3

4 4

2

1

2

CV166

1U_0201_6.3V6M

1

VRAM4G@

2

VRAM4G@

2

CV77

1U_0201_6.3V6M

CV78

1U_0201_6.3V6M

1

VRAM4G@

2

CV86

10U_0402_6.3V6M

CV87

10U_0402_6.3V6M

1

2

VRAM4G@

CV167

1U_0201_6.3V6M

CV168

1U_0201_6.3V6M

1

VRAM4G@

2

FBA0_ZQ1

12

VRAM4G@

RV58 121_0402_ 1%

CV64

1U_0201_6.3V6M

CV63

1U_0201_6.3V6M

1

VRAM4G@

2

Close to VRAM

CV79

1U_0201_6.3V6M

1

VRAM4G@

2

Close to VR

CV143

22U_0603_6.3V6M

1

2

VRAM4G@

Around VRAM

CV170

1U_0201_6.3V6M

1

VRAM4G@

2

x32 only

1

VRAM4G@

2

CV169

10U_0402_6.3V6M

1

2

VRAM4G@

AM

CV144

22U_0603_6.3V6M

1

2

VRAM4G@

CV80

1U_0201_6.3V6M

1

VRAM4G@

2

UV4B

K4

A8/A7

H5

A9/A1

H4

A10/A0

K5

A11/A6

J5

A12/RFU#J5/NC#J5

H11

BA0/A2

K10

BA1/A5

K11

BA2/A4

H10

BA3/A3

J4

ABI#

G3

RAS#

G12

CS#

L3

CAS#

L12

WE#

J12

CK

J11

CK#

J3

CKE#

D2

DBI0#

D13

DBI1#

P13

DBI2#

P2

DBI3#

J2

RESET#

J10

SEN

J13

ZQ

J1

MF

D4

WCK01

D5

WCK01#

P4

WCK23

P5

WCK23#

@

H5GC2H24BFR -T2C_FBGA170

CV65

1U_0201_6.3V6M

1

VRAM4G@

2

CV81

10U_0402_6.3V6M

1

2

VRAM4G@

CV145

22U_0603_6.3V6M

1

2

VRAM4G@

CV172

1U_0201_6.3V6M

1

VRAM4G@

2

MF=0

CV66

1U_0201_6.3V6M

VRAM4G@

CV82

10U_0402_6.3V6M

VRAM4G@

CV146

22U_0603_6.3V6M

VRAM4G@

CV171

1U_0201_6.3V6M

VRAM4G@

2 OF 2

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31

EDC0 EDC1 EDC2 EDC3

CV69

1U_0201_6.3V6M

1

VRAM4G@

2

CV83

10U_0402_6.3V6M

1

2

VRAM4G@

CV147

22U_0603_6.3V6M

1

2

VRAM4G@

FBA0_VREFC

CV141

1U_0201_6.3V6M

1

CV89

VRAM4G@

2

A4 A2 B4 B2 E4 E2 F4 F2 A11 A13 B11 B13 E11 E13 F11 F13 U11 U13 T11 T13 N11 N13 M11 M13 U4 U2 T4 T2 N4 N2 M4 M2

C2 C13 R13 R2

+1.35VSDGPU

820P_0402_50V7K

1

2

FBA_D0 FBA_D1 FBA_D2 FBA_D3 FBA_D4 FBA_D5 FBA_D6 FBA_D7 FBA_D8 FBA_D9 FBA_D10 FBA_D11 FBA_D12 FBA_D13 FBA_D14 FBA_D15 FBA_D16 FBA_D17 FBA_D18 FBA_D19 FBA_D20 FBA_D21 FBA_D22 FBA_D23 FBA_D24 FBA_D25 FBA_D26 FBA_D27 FBA_D28 FBA_D29 FBA_D30 FBA_D31

UV4A

C5

VDD

C10

VDD

D11

VDD

G1

VDD

G4

VDD

G11

VDD

G14

VDD

L1

VDD

L4

VDD

L11

VDD

L14

VDD

P11

VDD

R5

VDD

R10

VDD

B1

VDDQ

B3

VDDQ

B12

VDDQ

B14

VDDQ

D1

VDDQ

D3

VDDQ

D12

VDDQ

D14

VDDQ

E5

VDDQ

E10

VDDQ

F1

VDDQ

F3

VDDQ

F12

VDDQ

F14

VDDQ

G2

VDDQ

G13

VDDQ

H3

VDDQ

H12

VDDQ

K3

VDDQ

K12

VDDQ

L2

VDDQ

L13

VDDQ

M1

VDDQ

M3

VDDQ

M12

VDDQ

M14

VDDQ

N5

VDDQ

N10

VDDQ

P1

VDDQ

P3

VDDQ

P12

VDDQ

P14

VDDQ

T1

VDDQ

T3

VDDQ

T12

VDDQ

T14

VDDQ

J14

VREFC

A10

VREFD

U10

VREFD

@

H5GC2H24BFR -T2C_FBGA170

1

QV3 LBSS139W T1G_SC70-3

Drain

Gate2Source

3

VRAM_VREF_CTL<27,33>

FBA_EDC0 <28 > FBA_EDC1 <28 > FBA_EDC2 <28 > FBA_EDC3 <28 > FBA_EDC4 <28>

1 OF 2

B5

VSS

B10

VSS

D10

VSS

G5

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

VPP/NC#A5 VPP/NC#U5

VSS

G10

VSS

H1

VSS

H14

VSS

K1

VSS

K14

VSS

L5

VSS

L10

VSS

P10

VSS

T5

VSS

T10

VSS

A1 A3 A12 A14 C1 C3 C4 C11 C12 C14 E1 E3 E12 E14 F5 F10 H2 H13 K2 K13 M5 M10 N1 N3 N12 N14 R1 R3 R4 R11 R12 R14 U1 U3 U12 U14

A5 U5

FBA_CLKA0

40.2_0402_1 %

FBA_CLKA1

40.2_0402_1 %

RV63

VRAM4G@

0.01U_0402_16V7K

RV96

VGA@

0.01U_0402_16V7K

(3GHz and up)

12

FBA_CLKA0#

12

RV95

40.2_0402_1 %

VRAM4G@

1

VRAM4G@

CV190

2

FBA_CLKA1#

12

RV62

40.2_0402_1 %

VGA@

1

VGA@

CV191

2

RV51 931_0402_ 1%

1 2

VGA@

+1.35VSDGPU

12

RV50 549_0402_ 1%

VGA@

FBA0_VREFCFBA_VREFC_R

RV52

1.33K_0402_ 1%

VGA@

+1.35VSDGPU

1

2

UV5B

FBA1_ZQ3

12

VGA@

RV61 121_0402_ 1%

CV60

1U_0201_6.3V6M

1

VGA@

2

CV75

10U_0402_6.3V6M

1

2

VGA@

CV138

22U_0603_6.3V6M

1

2

VGA@

1U_0201_6.3V6M

1

2

CV159

VGA@

K4

A8/A7

H5

A9/A1

H4

A10/A0

K5

A11/A6

J5

A12/RFU#J5/NC#J5

H11

BA0/A2

K10

BA1/A5

K11

BA2/A4

H10

BA3/A3

J4

ABI#

G3

RAS#

G12

CS#

L3

CAS#

L12

WE#

J12

CK

J11

CK#

J3

CKE#

D2

DBI0#

D13

DBI1#

P13

DBI2#

P2

DBI3#

J2

RESET#

J10

SEN

J13

ZQ

J1

MF

D4

WCK01

D5

WCK01#

P4

WCK23

P5

WCK23#

@

CV68

1U_0201_6.3V6M

1

VGA@

2

CV76

10U_0402_6.3V6M

1

2

VGA@

CV139

22U_0603_6.3V6M

1

2

VGA@

1U_0201_6.3V6M

1

2

H5GC2H24BFR -T2C_FBGA170

CV165

VGA@

FBA_CMD26<28> FBA_CMD23<28> FBA_CMD22<28> FBA_CMD27<28> FBA_CMD25<28>

FBA_CMD19<28> FBA_CMD17<28> FBA_CMD18<28> FBA_CMD20<28>

FBA_CMD24<28> FBA_CMD31<28> FBA_CMD21<28> FBA_CMD28<28> FBA_CMD16<28>

FBA_CLKA1<28> FBA_CLKA1#<28> FBA_CMD30<28>

FBA_DBI7<28> FBA_DBI6<28> FBA_DBI5<28> FBA_DBI4<28>

FBA_CMD29<28>

+1.35VSDGPU

FBA_WCK67<28> FBA_WCK67#<28>

FBA_WCK45<28> FBA_WCK45#<28>

CV56

1U_0201_6.3V6M

CV57

CV59

1U_0201_6.3V6M

CV58

1U_0201_6.3V6M

1

VGA@

2

CV173

1U_0201_6.3V6M

1

VGA@

2

CV84

10U_0402_6.3V6M

1

2

VGA@

CV160

1U_0201_6.3V6M

CV161

1U_0201_6.3V6M

1

VGA@

2

CV67

1U_0201_6.3V6M

1

VGA@

2

Close to VRAM

CV85

1U_0201_6.3V6M

CV140

1U_0201_6.3V6M

1

VGA@

2

Close to VRAM

CV142

10U_0402_6.3V6M

CV70

22U_0603_6.3V6M

1

2

VGA@

Around VRAM

CV162

1U_0201_6.3V6M

CV158

1U_0201_6.3V6M

1

VGA@

2

x32 only

1U_0201_6.3V6M

1

VGA@

2

1

2

1

2

VGA@

2

CV74

10U_0402_6.3V6M

CV73

10U_0402_6.3V6M

1

2

VGA@

CV71

22U_0603_6.3V6M

CV72

22U_0603_6.3V6M

1

2

VGA@

CV164

1U_0201_6.3V6M

CV163

1U_0201_6.3V6M

1

VGA@

2

FBA0_VREFC

CV88

VGA@

2 OF 2

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31

EDC0 EDC1 EDC2 EDC3

+1.35VSDGPU

1

820P_0402_50V7K

2

FBA_D56

A4

FBA_D57

A2

FBA_D58

B4

FBA_D59

B2

FBA_D60

E4

FBA_D61

E2

FBA_D62

F4

FBA_D63

F2

FBA_D48

A11

FBA_D49

A13

FBA_D50

B11

FBA_D51

B13

FBA_D52

E11

FBA_D53

E13

FBA_D54

F11

FBA_D55

F13

FBA_D40

U11

FBA_D41

U13

FBA_D42

T11

FBA_D43

T13

FBA_D44

N11

FBA_D45

N13

FBA_D46

M11

FBA_D47

M13

FBA_D32

U4

FBA_D33

U2

FBA_D34

T4

FBA_D35

T2

FBA_D36

N4

FBA_D37

N2

FBA_D38

M4

FBA_D39

M2

C2 C13 R13 R2

UV5A

C5

VDD

C10

VDD

D11

VDD

G1

VDD

G4

VDD

G11

VDD

G14

VDD

L1

VDD

L4

VDD

L11

VDD

L14

VDD

P11

VDD

R5

VDD

R10

VDD

B1

VDDQ

B3

VDDQ

B12

VDDQ

B14

VDDQ

D1

VDDQ

D3

VDDQ

D12

VDDQ

D14

VDDQ

E5

VDDQ

E10

VDDQ

F1

VDDQ

F3

VDDQ

F12

VDDQ

F14

VDDQ

G2

VDDQ

G13

VDDQ

H3

VDDQ

H12

VDDQ

K3

VDDQ

K12

VDDQ

L2

VDDQ

L13

VDDQ

M1

VDDQ

M3

VDDQ

M12

VDDQ

M14

VDDQ

N5

VDDQ

N10

VDDQ

P1

VDDQ

P3

VDDQ

P12

VDDQ

P14

VDDQ

T1

VDDQ

T3

VDDQ

T12

VDDQ

T14

VDDQ

J14

VREFC

A10

VREFD

U10

VREFD

@

H5GC2H24BFR -T2C_FBGA170

1 OF 2

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

VPP/NC#A5 VPP/NC#U5

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

FBA_EDC7 <28> FBA_EDC6 <28> FBA_EDC5 <28>

B5 B10 D10 G5 G10 H1 H14 K1 K14 L5 L10 P10 T5 T10

A1 A3 A12 A14 C1 C3 C4 C11 C12 C14 E1 E3 E12 E14 F5 F10 H2 H13 K2 K13 M5 M10 N1 N3 N12 N14 R1 R3 R4 R11 R12 R14 U1 U3 U12 U14

A5 U5

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2017/10/30 2018/10/30

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Re v

Custom

Date : Sheet o f

D

Date : Sheet o f

Compal Electronics, Inc.

N17P GDDR5 CHA 6/7

EH5VF M/B LA-H501P

E

1A

32 1 01Friday, February 22, 2019

1A

A

B

C

D

E

MF=1

+1.35VSDGPU

FBB0_VREFC

CV122

VGA@

2 OF 2

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ8

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31

EDC0 EDC1 EDC2 EDC3

1

820P_0402_50V7K

2

FBB_D56

A4

FBB_D57

A2

FBB_D58

B4

FBB_D59

B2

FBB_D60

E4

FBB_D61

E2

FBB_D62

F4

FBB_D63

F2

FBB_D48

A11

FBB_D49

A13

FBB_D50

B11

FBB_D51

B13

FBB_D52

E11

FBB_D53

E13

FBB_D54

F11

FBB_D55

F13

FBB_D40

U11

FBB_D41

U13

FBB_D42

T11

FBB_D43

T13

FBB_D44

N11

FBB_D45

N13

FBB_D46

M11

FBB_D47

M13

FBB_D32

U4

FBB_D33

U2

FBB_D34

T4

FBB_D35

T2

FBB_D36

N4

FBB_D37

N2

FBB_D38

M4

FBB_D39

M2

C2 C13 R13 R2

UV7A

C5

VDD

C10

VDD

D11

VDD

G1

VDD

G4

VDD

G11

VDD

G14

VDD

L1

VDD

L4

VDD

L11

VDD

L14

VDD

P11

VDD

R5

VDD

R10

VDD

B1

VDDQ

B3

VDDQ

B12

VDDQ

B14

VDDQ

D1

VDDQ

D3

VDDQ

D12

VDDQ

D14

VDDQ

E5

VDDQ

E10

VDDQ

F1

VDDQ

F3

VDDQ

F12

VDDQ

F14

VDDQ

G2

VDDQ

G13

VDDQ

H3

VDDQ

H12

VDDQ

K3

VDDQ

K12

VDDQ

L2

VDDQ

L13

VDDQ

M1

VDDQ

M3

VDDQ

M12

VDDQ

M14

VDDQ

N5

VDDQ

N10

VDDQ

P1

VDDQ

P3

VDDQ

P12

VDDQ

P14

VDDQ

T1

VDDQ

T3

VDDQ

T12

VDDQ

T14

VDDQ

J14

VREFC

VPP/NC#A5

A10 U10

VPP/NC#U5 VREFD VREFD

@

H5GC2H24BFR -T2C_FBGA170

1 OF 2

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

FBB_EDC7 <28> FBB_EDC6 <28> FBB_EDC5 <28> FBB_EDC4 <28>

B5 B10 D10 G5 G10 H1 H14 K1 K14 L5 L10 P10 T5 T10

A1 A3 A12 A14 C1 C3 C4 C11 C12 C14 E1 E3 E12 E14 F5 F10 H2 H13 K2 K13 M5 M10 N1 N3 N12 N14 R1 R3 R4 R11 R12 R14 U1 U3 U12 U14

A5 U5

FBB1_ZQ3

12

VGA@

RV72 121_0402_ 1%

CV95

1U_0201_6.3V6M

VGA@

CV189

10U_0402_6.3V6M

VGA@

CV156

22U_0603_6.3V6M

VGA@

CV187

1U_0201_6.3V6M

1

VGA@

2

UV7B

K4

A8/A7

H5

A9/A1

H4

A10/A0

K5

A11/A6

J5

A12/RFU#J5/NC#J5

H11

BA0/A2

K10

BA1/A5

K11

BA2/A4

H10

BA3/A3

J4

ABI#

G3

RAS#

G12

CS#

L3

CAS#

L12

WE#

J12

CK

J11

CK#

J3

CKE#

D2

DBI0#

D13

DBI1#

P13

DBI2#

P2

DBI3#

J2

RESET#

J10

SEN

J13

ZQ

J1

MF

D4

WCK01

D5

WCK01#

P4

WCK23

P5

WCK23#

@

H5GC2H24BFR -T2C_FBGA170

CV98

1U_0201_6.3V6M

1

VGA@

2

CV110

10U_0402_6.3V6M

1

2

VGA@

CV157

22U_0603_6.3V6M

1

2

VGA@

CV109

1U_0201_6.3V6M

1

VGA@

2

FBB_D[63:0]<28>

FBB_CMD6<28> FBB_CMD11<28> FBB_CMD10<28> FBB_CMD7<28> FBB_CMD9<28>

1 1

FBB_CMD2<28> FBB_CMD4<28> FBB_CMD3<28> FBB_CMD1<28>

FBB_CMD8<28> FBB_CMD12<28> FBB_CMD0<28> FBB_CMD15<28> FBB_CMD5<28>

FBB_CLKA0<28> FBB_CLKA0#<28> FBB_CMD14<28>

FBB_DBI0<28> FBB_DBI1<28> FBB_DBI2<28> FBB_DBI3<28>

FBB_CMD13<28>

FBB_WCK01<28> FBB_WCK01 #<28>

FBB_WCK23<28> FBB_WCK23 #<28>

2 2

+1.35VSDGPU

CV99

1U_0201_6.3V6M

CV100

1U_0201_6.3V6M

1

VGA@

2

1

2

3 3

1

2

CV107

1U_0201_6.3V6M

1

VGA@

2

4 4

VGA@

2

CV111

1U_0201_6.3V6M

CV112

1U_0201_6.3V6M

1

VGA@

2

CV121

10U_0402_6.3V6M

CV120

10U_0402_6.3V6M

1

2

VGA@

CV186

1U_0201_6.3V6M

CV176

1U_0201_6.3V6M

1

VGA@

2

FBB0_ZQ1

12

VGA@

RV74 121_0402_ 1%

CV92

1U_0201_6.3V6M

CV101

1U_0201_6.3V6M

1

VGA@

2

Close to VRAM

CV113

1U_0201_6.3V6M

1

VGA@

2

Close to VRAM

CV148

22U_0603_6.3V6M

1

2

VGA@

Around VR

AM

CV177

1U_0201_6.3V6M

1

VGA@

2

x32 only

1U_0201_6.3V6M

1

VGA@

2

CV114

10U_0402_6.3V6M

1

2

VGA@

CV149

22U_0603_6.3V6M

1

2

VGA@

CV178

1U_0201_6.3V6M

1

VGA@

2

UV6B

K4

A8/A7

H5

A9/A1

H4

A10/A0

K5

A11/A6

J5

A12/RFU#J5/NC#J5

H11

BA0/A2

K10

BA1/A5

K11

BA2/A4

H10

BA3/A3

J4

ABI#

G3

RAS#

G12

CS#

L3

CAS#

L12

WE#

J12

CK

J11

CK#

J3

CKE#

D2

DBI0#

D13

DBI1#

P13

DBI2#

P2

DBI3#

J2

RESET#

J10

SEN

J13

ZQ

J1

MF

D4

WCK01

D5

WCK01#

P4

WCK23

P5

WCK23#

@

H5GC2H24BFR -T2C_FBGA170

1U_0201_6.3V6M

CV93

1

VGA@

2

CV115

10U_0402_6.3V6M

1

2

VGA@

22U_0603_6.3V6M

CV150

1

2

VGA@

CV179

1U_0201_6.3V6M

1

VGA@

2

MF=0

CV102

VGA@

CV116

VGA@

CV152

VGA@

CV105

1U_0201_6.3V6M

VGA@

2 OF 2

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31

EDC0 EDC1 EDC2 EDC3

CV103

1U_0201_6.3V6M

1

VGA@

2

CV117

10U_0402_6.3V6M

1

2

VGA@

CV151

22U_0603_6.3V6M

1

2

VGA@

CV106

1U_0201_6.3V6M

1

FBB0_VREFC

VGA@

2

CV123

VGA@

A4 A2 B4 B2 E4 E2 F4 F2 A11 A13 B11 B13 E11 E13 F11 F13 U11 U13 T11 T13 N11 N13 M11 M13 U4 U2 T4 T2 N4 N2 M4 M2

C2 C13 R13 R2

+1.35VSDGPU

1

820P_0402_50V7K

2

FBB_D0 FBB_D1 FBB_D2 FBB_D3 FBB_D4 FBB_D5 FBB_D6 FBB_D7 FBB_D8 FBB_D9 FBB_D10 FBB_D11 FBB_D15 FBB_D13 FBB_D14 FBB_D12 FBB_D16 FBB_D17 FBB_D18 FBB_D19 FBB_D22 FBB_D21 FBB_D23 FBB_D20 FBB_D24 FBB_D25 FBB_D26 FBB_D27 FBB_D28 FBB_D29 FBB_D31 FBB_D30

UV6A

C5

VDD

C10

VDD

D11

VDD

G1

VDD

G4

VDD

G11

VDD

G14

VDD

L1

VDD

L4

VDD

L11

VDD

L14

VDD

P11

VDD

R5

VDD

R10

VDD

B1

VDDQ

B3

VDDQ

B12

VDDQ

B14

VDDQ

D1

VDDQ

D3

VDDQ

D12

VDDQ

D14

VDDQ

E5

VDDQ

E10

VDDQ

F1

VDDQ

F3

VDDQ

F12

VDDQ

F14

VDDQ

G2

VDDQ

G13

VDDQ

H3

VDDQ

H12

VDDQ

K3

VDDQ

K12

VDDQ

L2

VDDQ

L13

VDDQ

M1

VDDQ

M3

VDDQ

M12

VDDQ

M14

VDDQ

N5

VDDQ

N10

VDDQ

P1

VDDQ

P3

VDDQ

P12

VDDQ

P14

VDDQ

T1

VDDQ

T3

VDDQ

T12

VDDQ

T14

VDDQ

J14

VREFC

VPP/NC#A5

A10 U10

VPP/NC#U5 VREFD VREFD

@

H5GC2H24BFR -T2C_FBGA170

VRAM_VREF_CTL<27,32>

FBB_EDC0 <28 > FBB_EDC1 <28 > FBB_EDC2 <28 > FBB_EDC3 <28 >

1 OF 2

B5

VSS

B10

VSS

D10

VSS

G5

VSS

G10

VSS

H1

VSS

H14

VSS

K1

VSS

K14

VSS

L5

VSS

L10

VSS

P10

VSS

T5

VSS

T10

VSS

A1

VSSQ

A3

VSSQ

A12

VSSQ

A14

VSSQ

C1

VSSQ

C3

VSSQ

C4

VSSQ

C11

VSSQ

C12

VSSQ

C14

VSSQ

E1

VSSQ

E3

VSSQ

E12

VSSQ

E14

VSSQ

F5

VSSQ

F10

VSSQ

H2

VSSQ

H13

VSSQ

K2

VSSQ

K13

VSSQ

M5

VSSQ

M10

VSSQ

N1

VSSQ

N3

VSSQ

N12

VSSQ

N14

VSSQ

R1

VSSQ

R3

VSSQ

R4

VSSQ

R11

VSSQ

R12

VSSQ

R14

VSSQ

U1

VSSQ

U3

VSSQ

U12

VSSQ

U14

VSSQ

A5 U5

Gate2Source

40.2_0402_1 %

1

Drain

RV76

VGA@

0.01U_0402_16V7K

RV97

VGA@

0.01U_0402_16V7K

(3GHz and up)

3

12

VGA@

12

VGA@

QV4 LBSS139W T1G_SC70-3

12

1

2

12

1

2

RV68 931_0402_ 1%

1 2

VGA@

FBB_CLKA0#FBB_CLKA0

RV77

40.2_0402_1 %

VGA@

CV193

FBB_CLKA1#FBB_CLKA1

RV98

40.2_0402_1 %

VGA@

CV192

+1.35VSDGPU

12

RV67 549_0402_ 1%

VGA@

FBB0_VREFCFBB_VREFC_R

RV70

1.33K_0402_ 1%

VGA@

+1.35VSDGPU

CV182

1U_0201_6.3V6M

1

VGA@

2

FBB_CMD26<28> FBB_CMD23<28> FBB_CMD22<28> FBB_CMD27<28> FBB_CMD25<28>

FBB_CMD19<28> FBB_CMD17<28> FBB_CMD18<28> FBB_CMD20<28>

FBB_CMD24<28> FBB_CMD31<28> FBB_CMD21<28> FBB_CMD28<28> FBB_CMD16<28>

FBB_CLKA1<28> FBB_CLKA1#<28> FBB_CMD30<28>

FBB_DBI7<28> FBB_DBI6<28> FBB_DBI5<28> FBB_DBI4<28>

FBB_CMD29<28>

+1.35VSDGPU

FBB_WCK67<28> FBB_WCK67 #<28>

FBB_WCK45<28> FBB_WCK45 #<28>

CV97

1U_0201_6.3V6M

CV91

1U_0201_6.3V6M

1

VGA@

2

CV104

1U_0201_6.3V6M

1

VGA@

2

CV118

10U_0402_6.3V6M

1

2

VGA@

CV184

1U_0201_6.3V6M

1

VGA@

2

1

VGA@

2

Close to VRAM

CV181

1U_0201_6.3V6M

CV180

1U_0201_6.3V6M

1

VGA@

2

Close to VRAM

CV119

10U_0402_6.3V6M

CV153

1

2

22U_0603_6.3V6M

1

2

VGA@

Around VRAM

CV185

1U_0201_6.3V6M

CV183

1U_0201_6.3V6M

1

VGA@

2

x32 only

CV96

1U_0201_6.3V6M

CV94

1U_0201_6.3V6M

CV90

1U_0201_6.3V6M

1

VGA@

2

1

2

1

2

VGA@

2

CV174

10U_0402_6.3V6M

CV108

10U_0402_6.3V6M

1

2

VGA@

CV154

22U_0603_6.3V6M

CV155

22U_0603_6.3V6M

1

2

VGA@

CV175

1U_0201_6.3V6M

CV188

1U_0201_6.3V6M

1

VGA@

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2017/10/30 2018/10/30

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Re v

Custom

Date : Sheet o f

D

Date : Sheet o f

Compal Electronics, Inc.

N17P GDDR5 CHB 7/7

EH5VF M/B LA-H501P

E

1A

33 1 01Friday, February 22, 2019

1A

5

D D

C C

4

3

2

1

Reserve Page

B B

A A

Security Cl assification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2017/11/23 2017/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document N umber Re v

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

N18E-GDDR6_D

EH5VF M/B LA-H501P

1

1A

34 101Friday, February 22, 2019

1A

5

D D

C C

4

3

2

1

Reserve Page

B B

A A

Security Cl assification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2017/11/23 2017/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document N umber Re v

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

N18E-GDDR6_D

EH5VF M/B LA-H501P

1

1A

35 101Friday, February 22, 2019

1A

A

CSSP_B+

1 1

CSSP_NV VDD

1 2

RV359 47 5_0402_1%ON_X76 @

1 2

2 2

3 3

4 4

RV360 47 5_0402_1%ON_X76 @ RV361 16 9_0402_1%@ RV363 16 9_0402_1%@

+3V_OVR M

12

RV370

@

10K_040 2_1%

12

RV373 10K_040 2_1%

N18P@

+3V_OVR M

12

RV374

@

10K_040 2_1%

PFM_ADC _FILTER_MODE

12

RV375 10K_040 2_1%

@

1 2 1 2

GPIO22_OC _WARN#<27>

PFM_ADC _FILTER_EN

13

D

S

1 2

RV343 75 K_0402_1%N18 P@

1000P_0 402_50V7K

1 2

RV349 75 K_0402_1%N18 P@

CV362

1000P_0 402_50V7K

0.015U_0402_16V7K

1

CV366

2

@

2

G

QV16

@

L2N7002 WT1G_SC-70 -3

SB00001GE00

CV361

N18P@

0.015U_0402_16V7K CV367

12

N18P@

1

2

@

0.015U_0402_16V7K CV368

N18P@

RV344

1 2

649_040 2_1%

ON_X76@

RV350

1 2

649_040 2_1%

ON_X76@

1 2

RV354

0_0402_ 5%

0.015U_0402_16V7K

1

CV369

2

12

RV400 100K_04 02_5%

OVRM_EN <17,58>

VGA@

B

PFM_CH1 _BS_IN1

PFM_CH1 _BS_IN2

0_0402_5%

RV352

0_0402_5%

1 2

@

PFM_FILTE R_GND_FET

RV365

1 2

0_0402_ 5%

PFM_ADC _MUX_SEL_R

@

PFM_ADC _FILTER_EN

PFM_SKIP_ R

PFM_ADC _FILTER_MODE

S IC US5650Q QKI WQFN 32P P OWER MONITOR

SA0000CMA00

487_040 2_1%

SD00000EL80

487_040 2_1%

SD00000EL80

0730 FAE CF suggest

RV353

@

UV47

3

BS_IN1

6

PFM_CH1 _BS_IN3 PFM_CH1 _BS_IN4

+3V_OVR M

12

RV371 1K_0402 _1%

N18P@

UV47 u PI_X76@

RV344

uPI_X76@

RV350

uPI_X76@

BS_IN2

11

BS_IN3

14

BS_IN4

9

GND_FET

32

SH_O1

7

SH_O2

10

SH_O3

17

SH_O4

29

MUX_SEL

28

ENABLE

25

SKIP

26

MODE_SEL

NCP4549 1XMNTWG_Q FN32_4X4

SA0000C9Q00

ON_X76@

PFM_SKIP_ R

RV359

357_040 2_1%

SD034357080

RV360

357_040 2_1%

SD034357080

uPI_X76@

VCC

SH_IN_P1 SH_IN_N1 SH_IN_P2 SH_IN_N2 SH_IN_P3 SH_IN_N3 SH_IN_P4 SH_IN_N4

DIFF_OUT_P DIFF_OUT_N

BS_OK

BG_REF_OUT

BS_REF

CM_REF_IN

GND

RV366

324K_04 02_1%

SD034324380

C

+3V_OVR M

1 2

RV351 0_ 0402_5%uPI_X7 6@

1 2

RV399 0_ 0402_5%ON_ X76@

1

N18P@

CV363 1U_0201 _6.3V6M

27

PFM_CH1 _SH_IN_P1 CSSP_B+

2

PFM_CH1 _SH_IN_N1 CSSN_B+

1

PFM_CH1 _SH_IN_P2 CSSP_NV VDD

5

PFM_CH1 _SH_IN_N2 CSSN_NVVD D

4

PFM_CH1 _SH_IN_P3

12

PFM_CH1 _SH_IN_N3

13

SNN_PFM _CH1_SH_IN_P4

15

SNN_PFM _CH1_SH_IN_N4

16

ADC_IN_P

20

ADC_IN_N

19

PFM_PF_ BSOK_R

30

SNN_ADC _CUSTOM8

8

NC

SNN_ADC _CUSTOM18

18

NC

SNN_ADC _CUSTOM21

21

NC

SNN_ADC _CUSTOM31

31

NC

PFM_BG_ REF_OUT

23

PFM_BS_ REF

24

PFM_CM_ REF_IN

22

33

2

1 2

RV355 10 0_0402_1%N18P@

1 2

RV356 0_ 0402_5%@

1 2

RV357 10 0_0402_1%N18P@

1 2

RV358 0_ 0402_5%@

1

2

N18P@

RV362 0_ 0402_5%@ RV364 0_ 0402_5%@

CV370

1000P_0402_50V7K

1

2

N18P@

PFM_PF_ BSOK_R

+3VSDGP U

+3VLP

1 2 1 2

CV371

1000P_0402_50V7K

N18P@

0730 FAE CF suggest , reserve pull high only

uPI_X76@

1

2

1000P_0402_50V7K

N18P@

CV372

+3V_OVR M

12

RV372 10K_040 2_1%

D

N18P@

1 2

CV364 47P _0402_50V8J

1 2

CV365 47P _0402_50V8J

1 2

RV367

365K_04 02_1%

N18P@

243K_04 02_1%ON_X 76@

ADC_IN_P <27> ADC_IN_N <27>

RV366

1 2

PFM_CH1 _SH_IN_P3 PFM_CH1 _SH_IN_N3 SNN_PFM _CH1_SH_IN_P4 SNN_PFM _CH1_SH_IN_N4

N18P@

0727 FAE CF suggest

CSSP_B+ <96> CSSN_B+ <96> CSSP_NV VDD <96> CSSN_NV VDD <96>

RV369

10K_0402_1%

12

RV368

681K_0402_1%

12

N18P@

CV373

1000P_0402_50V7K

1

N18P@

2

N18P@

+3V_OVR M

12

2K_0402_5%

RV345

N18P@

E

12

RV346

2K_0402_5%

N18P@

12

RV347

2K_0402_5%

N18P@

RV348

2K_0402_5%

Security Classification

2017/11/ 23 2018/09 /01

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

2017/11/ 23 2018/09 /01

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

OVR-M

Size Document Number Re v

Custom

D

EH5VF M/B LA-H501P

Date : Sheet o f

36 1 01Friday, February 22, 201 9

E

1A

5

4

3

2

1

+1.8V_AON/+3VSDGPU

+3VSDGPU

+1.8VSDGPU_AON

10U_0402_6.3V6M

CG334

1

2

VGA@

1.8VSDGPU_MAIN_EN3V3< 27>

VGA@

1U_0201_6.3V6M

PU at GPU side

@

0.1U_0201_10V6K

DGPU_PWR_EN

1.8VSDGPU_MAIN_EN3V3

CV357

CV400

+1.8VALW

CG337

VGA@

+5VALW

1

2

1V8_AON_EN

3VSDGPU_EN_R

+3VS

+1.8VALW

12

VGA@

D D

0.1U_0201_10V6K

22U_0603_6.3V6M

CG339

UG27

1 2

3

4

5

6 7

VOUT1

VIN1

VOUT1

VIN1

ON1

VBIAS

ON2

VIN2

VOUT2

VIN2

VOUT2

GPAD

EM5209VF_DFN14_2X3

VGA@

CT1

GND

CT2

14 13

12

11

10

9 8

15

CG335 220P_0402_50V8J

1 2

VGA@

CG336 220P_0402_50V8J

1 2

VGA@

10U_0402_6.3V6M

CG338

1

2

VGA@

1

2

+5VALW

1

VGA@

0.1U_0201_10V6K

2

+1.8VALW

1

2

+1.8V_MAIN

UV45

1

VIN1

2

VIN2

7

VIN thermal

3

VBIAS

4

ON

1

CV358

+3VS

IN B

IN A

AOZ1334DI-01_DFN8-7_3X3

VGA@ SA000070V00

2

5

UV46

VCC

3VSDGPU_EN_1 3VSDGPU_EN_R

4

OUT Y

GND

NL17SZ08DFT2G_SC70-5

3

N18P@

+1.8VSDGPU_MAIN

6

VOUT

GND

5

10U_0402_6.3V6M

CV359

1

2

VGA@

For Power down sequence

DV9

N18P@

1 2

RB751S40T1G_SOD523-2

RV341

10K_0402_5%

1 2

N18P@

0.1U_0201_10V6K

CV356

1

2

CV360

0.1U_0201_10V6K

1

2

VGA@

12

RV342 1M_0402_5%

VGA@

For Power down sequence

C C

DGPU_PWR_EN<19,27>

B B

DV1

VGA@

1 2

RV22

200K_0402_1%

VGA@

12

RB751S40T1G_SOD523-2

1V8_AON_EN

1

CV35

0.1U_0201_10V6K

2

VGA@

+1.8VSDGPU_AON

1

CV374

2.2U_0402_6.3V6M

N18P@

2

GPIO26_FP_FUSE_R

12

GPIO26_FP_FUSE<27>

@

RV382

0_0402_5%

1

@

CV375

N18P@

0.1U_0201_10V6K

2

RV383

1 2

10K_0201_5%

UV48

6

VIN1

VOUT1

5

VIN2

VOUT2

4

EN

VSS

GS7616SC-R_SOT363-6

@

+1.8VSDGPU_AON

+5VALW

1 2

3

UV50

1

VIN1

2

VIN2

7

VIN thermal

3

VBIAS

4

ON

AOZ1334DI-01_DFN8-7_3X3

N18P@ SA000070V00

12mils

2.2U_0402_6.3V6M

6

VOUT

5

GND

CV376

N18P@

+FP_FUSE_GPU

1

2

+FP_FUSE_GPU

12

RV384

2.21K_0402_1%

N18P@

2

G

+1.0VSDGPU

VGA@

RV377 20_0402_5%

1 2

61

D

QV14A

VGA@

2N7002KDW_SOT363-6

S

Security Cl assification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

1.35VSDGPU_EN<27,93>

2017/11/23 2017/12/31

+5VS

VGA@

RV115

100K_0402_5%

1 2

1.35VSDGPU_EN#

34

D

5

G

S

QV11B 2N7002KDW_SOT363-6

VGA@

Compal Secret Data

Deciphered Date

+1.35VSDGPU

VGA@

RV116 20_0402_5%

2

G

2N7002KDW_SOT363-6

VGA@

2

QV11A

+NVVDD1

+5VS

VGA@

RV117

1 2

61

D

S

NVVDD1_EN< 27,95>

Size Document N umber Re v

Date: Sheet of

100K_0402_5%

5

G

S

QV10B 2N7002KDW_SOT363-6

VGA@

Compal Electronics, Inc.

Title

Compal Electronics, Inc.

GPU DC INTERFACE

EH5VF M/B LA-H501P

1 2

34

D

VGA@

RV118 1_0603_5%

2

G

2N7002KDW_SOT363-6

1

QV10A

VGA@

37 101Friday, February 22, 2019

1 2

61

D

S

1A

+3VSDGPU

+5VS

N18P@

RV381

100K_0402_5%

1 2

3VSDGPU_EN_R#

34

3VSDGPU_EN_R

A A

5

D

5

G

S

QV15B 2N7002KDW_SOT363-6

N18P@

RV380 1_0603_5%

1 2

61

D

2

G

QV15A 2N7002KDW_SOT363-6

N18P@

S

GPUCORE_EN<27>

4

+5VS

VGA@

RV376

100K_0402_5%

1 2

GPUCORE_EN# NVVDD_EN#

34

D

5

G

S

QV14B 2N7002KDW_SOT363-6

VGA@

A

LCD POWER CIRCUIT

12

RX1 100K_04 02_5%

UX1

5

4

SY6288C20 AAC_SOT23-5

CX2

1U_0201_6.3V6M

1 1

1

2

PCH_ENV DD<1 7>

B

IN

EN

GND

2

3

OC

1

OUT

W=60mils

1

2

10U_0402_6.3V6M

CX3

1

CX4

0.1U_020 1_10V6K

2

@

C

SM01000EJ00 3000ma 220 ohm@ 100m hz

DCR 0.04

+INVPW R_B++19VB_C PU+LCDV DD+3VS

W=60mils W=60mils

LX1

EMI@

HCB2012 KF-221T30_080 5

1 2

CX5

68P_040 2_50V8J

XEMI@

1

2

CX6 1000P_0 402_50V7K

EMI@

2

D

Place closed to

DP1

JE

+3VS

CX7

1

2

0.1U_0201_10V6K

+LCDVDD

@

CX8

E

10U_0402_6.3V6M

1

2

1

CX1

2

0.1U_0201_10V6K

RX3

+LCDVDD

12

RX11 10K_040 2_5%

PANEL_O D_EN

2 2

12

RX12 10K_040 2_5%

@

PCH_BKL _PWM<17>

BKOFF#<5 8>

EDP_HPD<16>

PCH_BKL _PWM

BKOFF#

0_0402_ 5%

1 2

@

RX10 100K_0402 _5%

CX9 220P_040 2_50V7K

CX10 220P_040 2_50V7K

RX5 10K_ 0402_5%@

12

1 2

@

XESD@

1 2

XESD@

1 2

EDP_HPD _R

RX4 100K_04 02_5%

1 2

RX13 0_06 03_5%@

EDP_AUXN<6>

EDP_AUXP<6>

EDP_TXP0<6> EDP_TXN0<6>

EDP_TXP1<6> EDP_TXN1<6>

EDP_TXP2<6> EDP_TXN2<6>

EDP_TXP3<6> EDP_TXN3<6>

USB Touch Screen

+5VS

+3VS

3 3

Cam

era

USB20_N 5<14>

USB20_P 5<14>

1 2

RX6 0_06 03_5%@

1 2

RX7 0_06 03_5%

USB20_P 5

RX8 0_040 2_5%@

RX9 0_040 2_5%@

+TS_PW R

1 2

USB20_N 5_CAMERAUSB20_N 5

USB20_P 5_CAMERA

+INVPW R_B++INVPW R_B+_BOOST

EDP_AUX N

CX20 0.1U_0201_1 0V6K

EDP_AUX P

CX19 0.1U_0201_1 0V6K

EDP_TXP 0

CX11 0.1U_0201_1 0V6K

EDP_TXN 0

CX12 0.1U_0201_1 0V6K

EDP_TXP 1

CX13 0.1U_0201_1 0V6K

EDP_TXN 1

CX14 0.1U_0201_1 0V6K

EDP_TXP 2

CX15 0.1U_0201_1 0V6K

EDP_TXN 2

CX16 0.1U_0201_1 0V6K

EDP_TXP 3

CX17 0.1U_0201_1 0V6K

EDP_TXN 3

CX18 0.1U_0201_1 0V6K

Touch Sc

reen

For

mera

Ca

1 2 1 2

LED PANEL Conn.

+INVPW R_B+

+LCDVDD

PANEL_O D_EN<19>

USB20_P 6<14>

USB20_N 6<14>

+TS_PW R

TS_EN<19,58>

+3VS

DMIC_CLK_ R<56> DMIC_DATA _R<56>

DMIC_CLK_ R

DMIC_DATA _R

2

3

DX1 YSLC05CH_ SOT23-3

XESD@

W=60mils

PCH_BKL _PWM BKOFF#

EDP_HPD _R

EDP_AUX N_C EDP_AUX P_C

EDP_TXP 0_C EDP_TXN 0_C

EDP_TXP 1_C EDP_TXN 1_C

EDP_TXP 2_C EDP_TXN 2_C

EDP_TXP 3_C EDP_TXN 3_C

USB20_P 6 USB20_N 6

TS_EN

USB20_N 5_CAMERA USB20_P 5_CAMERA

DMIC_CLK_ R DMIC_DATA _R

JEDP1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

GND

36

GND

37

GND

38

GND

39

GND

40

GND

ACES_50 203-04001-002

CONN@

SP010014B10

41 42 43 44 45 46

1

4 4

Security Classification

2017/10/ 30 2018/10 /30

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

2017/10/ 30 2018/10 /30

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Re v

Custom

Date : Sheet o f

D

Date : Sheet o f

Compal Electronics, Inc.

eDP CONN.

EH5VF M/B LA-H501P

E

1A

38 1 01Friday, February 22, 201 9

A

1 1

2 2

B

C

D

E

Reserve Page

3 3

4 4

Security Cl assification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2017/11/23 2017/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document N umber Re v

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

DP CONN

EH5VF M/B LA-H501P

E

1A

39 101Friday, February 22, 2019

1A

A

B

C

D

E

HDMI_CLKN HDMI_CLKP HDMI_TX_N 0 HDMI_TX_P 0

HDMI_TX_N 1 HDMI_TX_P 1 HDMI_TX_N 2 HDMI_TX_P 2

HDMI_R_CL KN

HDMI_R_CL KP

HDMI_R_TX _N0

HDMI_R_TX _P0

RY36

XEMI@

150_040 2_1%

RY37

XEMI@

150_040 2_1%

RY38

XEMI@

150_040 2_1%

RY39

XEMI@

150_040 2_1%

HDMI_CLKP HDMI_CLKN

HDMI_TX_P 0 HDMI_TX_N 0

HDMI_TX_P 1 HDMI_TX_N 1

HDMI_TX_P 2 HDMI_TX_N 2

1 2

GPU_DP2 _P3<29>

1 1

2 2

GPU_DP2 _N3<29>

GPU_DP2 _P2<29> GPU_DP2 _N2<29>

GPU_DP2 _P1<29> GPU_DP2 _N1<29>

GPU_DP2 _P0<29> GPU_DP2 _N0<29>

RY15 6.04_ 0402_1%

CY26

3.3P_040 2_50V8

1 2

RY14 6.04_ 0402_1%

RY16 6.04_ 0402_1%

RY17 6.04_ 0402_1%

RY18 6.04_ 0402_1%

RY19 6.04_ 0402_1%

RY20 6.04_ 0402_1%

RY22 6.04_ 0402_1%

CY22 .1U_0402_16V 7K

1 2

CY24 .1U_0402_16V 7K

1 2

CY16 .1U_0402_16V 7K

1 2

CY17 .1U_0402_16V 7K

1 2

CY18 .1U_0402_16V 7K

1 2

CY19 .1U_0402_16V 7K

1 2

CY20 .1U_0402_16V 7K

1 2

CY21 .1U_0402_16V 7K

1 2

XEMI@

1 2

HDMI_R_CL KPHDMI_CLKP

12

HDMI_R_CL KNHDMI_CLKN

HDMI_R_TX _P0HDMI_TX_P 0

12

HDMI_R_TX _N0HDMI_TX_N0

HDMI_R_TX _P1HDMI_TX_P 1

12

HDMI_R_TX _N1HDMI_TX_N1

HDMI_R_TX _P2HDMI_TX_P 2

12

HDMI_R_TX _N2HDMI_TX_N2

1 2

RY27 499_0402_ 1%

1 2

RY28 499_0402_ 1%

1 2

RY29 499_0402_ 1%

1 2

RY30 499_0402_ 1%

1 2

RY31 499_0402_ 1%

1 2

RY32 499_0402_ 1%

1 2

RY33 499_0402_ 1%

1 2

RY34 499_0402_ 1%

DY2

XESD@

1

2

4

5

3

TVW DF1004AD0_DF N9

9

8

7

6

SC300003Z00

DY3

HDMI_R_TX _N1

3 3

RY24

1M_0402 _5%

HDMI_HPD_ PCH<16 ,27>

RY11 design guide rev2.0 use 20K pull down.

+1.8VSDG PU_AON

4 4

GPU_DP2 _CTRL_CLK<2 9>

GPU_DP2 _CTRL_DAT<29>

PJT138K A_SOT363-6

QY1A

PJT138K A_SOT363-6

+3VS+3 VS

G

2

S

5

34

QY2A

2N7002K DW_SOT363 -6

61

D

2

QY1B

G

61

S

D

HDMI_HPD

RY11

100K_04 02_5%

1 2

HDMI_CTRL _CLK

HDMI_CTRL _DAT

1 2

SGD

3ohm/10pF

A

B

HDMI_R_TX _P1

HDMI_R_TX _N2

HDMI_R_TX _P2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

XESD@

1

2

4

5

3

TVW DF1004AD0_DF N9

9

8

7

6

SC300003Z00

HDMI_HPD

HDMI_CTRL _CLK

2017/10/ 30 2018/10 /30

C

HDMI_GND

5

+3VS

G

HDMI_R_CL KN

HDMI_R_CL KP

HDMI_R_TX _N0

HDMI_R_TX _P0

HDMI_R_TX _N1

HDMI_R_TX _P1

HDMI_R_TX _N2

HDMI_R_TX _P2

DY1

6

I/O4

5

VDD

4

I/O3

AZC099-0 4S.R7G_SOT23-6

XESD@

SC300001G00

Compal Secret Data

34

D

QY2B 2N7002K DW_SOT363 -6

S

I/O2

GND

I/O1

Deciphered Date

HDMI_CTRL _DAT

3

2

1

+HDMI_5V_ OUT

D

+5VS +HDMI_5V_ OUT

W=40mils

UY2

1

IN

AP2330W -7_SC59-3

HDMI_CTRL _DAT HDMI_CTRL _CLK GPU_DP2 _CTRL_CLK GPU_DP2 _CTRL_DAT

+HDMI_5V_ OUT

OUT

GND

HDMI_HPD

HDMI_CTRL _DAT HDMI_CTRL _CLK

HDMI_R_CL KN

HDMI_R_CL KP HDMI_R_TX _N0

HDMI_R_TX _P0 HDMI_R_TX _N1

HDMI_R_TX _P1 HDMI_R_TX _N2

HDMI_R_TX _P2

3

2

RY40 2.2K_0402_5 % RY41 2.2K_0402_5 % RY42 2.2K_0402_5 % RY43 2.2K_0402_5 %

1 2 1 2 1 2 1 2

1

CY23

0.1U_020 1_10V6K

2

+HDMI_5V_ OUT

HDMI connector

JHDMI1

19

HP_DET

18

+5V

17

DDC/CEC_GND

16

SDA

15

SCL

14

Reserved

13

CEC

12

CK-

11 10

9 8 7 6 5 4 3 2 1

GND

CK_shield

GND

CK+

GND

D0-

GND D0_shield D0+ D1D1_shield D1+ D2D2_shield D2+

ACON_HM R2E-AK120D

CONN@

DC232000Y00

Compal Electronics, Inc.

Title

Size Document Number Re v

Custom

Date : Sheet o f

Compal Electronics, Inc.

HDMI CONN.

EH5VF M/B LA-H501P

E

+1.8VSDG PU_AON

20 21 22 23

40 1 01Friday, February 22, 201 9

1A

5

D D

C C

4

3

2

1

Reserve Page

B B

A A

Security Cl assification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2017/11/23 2017/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document N umber Re v

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

N18E-GDDR6_D

EH5VF M/B LA-H501P

1

1A

41 101Friday, February 22, 2019

1A

5

+5VALW +5 VALW_MUX

US14

5

IN

D D

USB_EN<5 8,72,73>

4

EN

SY6288C20 AAC_SOT23-5

OUT

GND

1

2

3

OC

10U_0402_6.3V6M

1

CS116

2

4

0.1U_0201_10V6K

1

CS15

2

Close to Pin19

3

2

1

+5VALW _MUX +USB3_VCC C

12

RS20

4.7K_040 2_5%

OCP_DET #

12

RS128 10K_040 2_5%

C C

+3VO_MU X

B B

12

RS114

10K_040 2_5%

@

PLUG_OR I

12

RS115

12

RS134 200K_04 02_1%

VMON

12

RS135 10K_040 2_1%

USB3_PR X_DTX_P2<17> USB3_PR X_DTX_N2<17>

USB3_PT X_DRX_P2<17> USB3_PT X_DRX_N2<17>

RS1

10K_040 2_5%

RS2

10K_040 2_5%

USB3.0 (Port 2)

1 2

CS125 0.22U _0201_6.3V6M

1 2

CS126 0.22U _0201_6.3V6M

1 2

CS127 0.22U _0201_6.3V6M

1 2

CS128 0.22U _0201_6.3V6M

+3VO_MU X

12

M1 M0

12

@

RS3

10K_040 2_5%

RS4

10K_040 2_5%

12

@

OCP_DET #<43>

USBC_EN<43>

1 2

RS137 0_0402 _5%

VMON

OCP_DET #

USBC_EN

USB3_PR X_C_DTX_P2 USB3_PR X_C_DTX_N2

USB3_PT X_C_DRX_P2 USB3_PT X_C_DRX_N2

PLUG_OR I M1

M0

12

RS129

6.2K_040 2_1%

4.7U_040 2_6.3V6M

TYPEC_1P5 A_EC <43,58>

17

16

15

23 21 22

18

25

+3VO_MU X

CS14

US3

VMON

OCP_DET

VBUS_EN

System side

4

SSRX_1P/2N

5

SSRX_1N/2P

6

SSTX_1P/2N

7

SSTX_1N/2P

GPIO CURRENT_M1 CURRENT_M0

REXT

E-PAD

1

2

LDO_3V3

20

10 Gbps 2:1 MUX

5V_IN19VCON_IN

CC1 CC2

Type-C Port Side

C_TX2_1P/2N C_TX2_1N/2P

C_RX2_1P/2N C_RX2_1N/2P

C_TX1_1P/2N C_TX1_1N/2P

C_RX1_1P/2N C_RX1_1N/2P

RTS5441 E-GRT_QFN24_4 X4

13

+5VALW _MUX

1

CS117

0.1U_020 1_10V6K

2

Close to Pin13

12 14

11 10

24 1

8 9

2 3

CC1_VCO NN CC2_VCO NN

USB3_CC _TX_P2 USB3_CC _TX_N2

USB3_CC _RX_P2 USB3_CC _RX_N2

USB3_CC _TX_P1 USB3_CC _TX_N1

USB3_CC _RX_P1 USB3_CC _RX_N1

CC1_VCO NN <43> CC2_VCO NN <43>

1 2

CS112 .1U_04 02_16V7K

1 2

CS113 .1U_04 02_16V7K

1 2

CS121 0.33U_ 0201_6.3V6M

1 2

CS122 0.33U_ 0201_6.3V6M

1 2

CS114 .1U_04 02_16V7K

1 2

CS115 .1U_04 02_16V7K

1 2

CS123 0.33U_ 0201_6.3V6M

1 2

CS124 0.33U_ 0201_6.3V6M

USB3_CC _RX_P2_C USB3_CC _RX_N2_C

RS130

220K_02 01_1%

1 2

USB3_CC _RX_P1_C USB3_CC _RX_N1_C

RS132

220K_02 01_1%

1 2

USB3_CC _TX_P2_C USB3_CC _TX_N2_C

USB3_CC _RX_P2_C USB3_CC _RX_N2_C

USB3_CC _TX_P1_C USB3_CC _TX_N1_C

USB3_CC _RX_P1_C USB3_CC _RX_N1_C

RS131 220K_02 01_1%

1 2

RS133 220K_02 01_1%

1 2

CC1_VCO NN

CS130 220 P_0402_50V8J

CC2_VCO NN

CS129 220 P_0402_50V8J

USB3_CC _TX_P2_C <43> USB3_CC _TX_N2_C <43>

USB3_CC _RX_P2_C <43> USB3_CC _RX_N2_C <43>

USB3_CC _TX_P1_C <43> USB3_CC _TX_N1_C <43>

USB3_CC _RX_P1_C <43> USB3_CC _RX_N1_C <43>

1 2 1 2

5441E Current Limit

M0M1

L

H

A A

H

0.9A

L

1.5A

H

3A

MODE

H

TYPEC_1P5A_EC

RTS5441 M0 truth table by 2018 BIOS spec

limit point

MODE

H

L

3A

1.5A

3.5A

1.92A

AC mode o r Battery >30%

Battery <30% when DC mode

Condition

confirm realtek hand-shake

Security Classification

2017/07/ 20 2018/07 /20

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

2017/07/ 20 2018/07 /20

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Re v

Custom

Date : Sheet o f

2

Date : Sheet o f

Compal Electronics, Inc.

CC+USB TYPE C

EH5VF M/B LA-H501P

42

1

1A

101Friday, February 22, 2019

5

D D

USBC_EN<42> USB_OC0 # <14>

4

+5VALW +USB3_VCCC

CS95

150U_D2_6.3VY_R15M

SGA00003700

1

+

2

12

RB77 47K_040 2_5%

0.1U_0201_10V6K CS96

1

2

US11

6

IN

5

RSET

SET

4

EN

G518B1T P1U_TSOT23-6

footprint : G 518 PN : SA0000BDN00(SILERGY SY6861B1)

OUT

GND

FLAG

1

2

3

0.1U_0402_25V6 CS97

1

@

2

1 2

RS136 0_0402 _5%

1 2

RS112 0_0402 _5%

1

CS100

0.1U_020 1_10V6K

2

22U_0805_25V6M

CS99

CS98

1

@

2

@

OCP_DET # <42>

RSET

RS113

6.2K_040 2_5%

12

RS109

8.2K_040 2_5%

12

RS110

4.3K_040 2_5%

61

D

2

G

S

QS2A

2N7002K DW_SOT363 -6

12

34

D

5

G

S

QS2B

2N7002K DW_SOT363 -6

check bios 1050 is use PCH output

1

TYPEC_3A <18>

TYPEC_1P5 A_EC <42,58>

For ESD request

DS3

ESD@

USB3_CC _TX_P1_C<42>

USB3_CC _TX_N1_C<42>

CC1_VCO NN

TBTA_SB U1 TB TA_SBU1

C C

USB3_CC _TX_N2_C<4 2>

USB3_CC _TX_P2_C<42>

USB20_P 2_L USB20_P2_L

B B

USB20_N 2_L USB20_N2_L

USB3_CC _RX_N2_C<42>

USB3_CC _RX_P2_C<42>

CC2_VCO NN

USB3_CC _RX_N1_C<42>

USB3_CC _RX_P1_C<42>

1

2

4

5

3

TVW DF1004AD0_DF N9

SC300003 Z00

DS4

ESD@

1

2

4

5

3

TVW DF1004AD0_DF N9

SC300003 Z00

DS6

ESD@

1

2

4

5

3

TVW DF1004AD0_DF N9

SC300003 Z00

DS5

ESD@

1

2

4

5

USB3_CC _TX_P1_C

9

USB3_CC _TX_N1_C

8

CC1_VCO NN

7

6

9

8

USB3_CC _TX_N2_C

7

USB3_CC _TX_P2_C

6

9

8

USB3_CC _RX_N2_C

7

USB3_CC _RX_P2_C

6

CC2_VCO NN

9

TBTA_SB U2TBTA_SB U2

8

USB3_CC _RX_N1_C

7

USB3_CC _RX_P1_C

6

CS13

10U_060 3_25V6M

DS19

ESD@

PESD24V S2UT_SOT23-3

SCA0000 4500

+USB3_V CCC +USB3_VCCC

JTYPEC1

A1

USB3_CC _TX_P1_C USB3_CC _TX_N1_C

1

2

3

1

CC1_VCO NN<4 2>

2

0.1U_040 2_25V6

USB3_CC _RX_N2_C USB3_CC _RX_P2_C USB3_CC _TX_P2_C

12

CS840.1U_0 402_25V6

USB20_P 2_L USB20_N 2_L USB20_P 2_L

TBTA_SB U1

12

CS86

GND

A2

SSTXP1

A3

SSTXN1

A4

VBUS

A5

CC1

A6

DP1

A7

DN1

A8

SBU1

A9

VBUS

A10

SSRXN2

A11

SSRXP2

A12

GND

1

GND

2

GND

3

GND

4

GND

DEREN_4 0-42407-024630 0RHF

CONN@

DC23300RC00

GPP_B1

(TYPEC_1P5A)

L

H

*H

GND

SSRXP1 SSRXN1

VBUS

SBU2

DN2 DP2

CC2

VBUS

SSTXN2

SSTXP2

GND

GND GND GND GND

GPP_B4

(TYPEC_3A)

LL

H

L

H

B12

B11 B10

B9

B8

B7 B6

B5

B4

B3 B2

B1

5 6 7 8

limit point

MODERSET(kΩ )

1 2

TBTA_SB U2

1 2

0.9A

1.5A

2A

3A

1.09A

1.92A

2.67A

3.5A

CC2_VCO NN <42>

6.2

3.53

2.54

1.94

USB3_CC _RX_P1_C USB3_CC _RX_N1_C

CS87 0.1U_0 402_25V6

USB20_N 2_L

CS85 0.1U_0 402_25V6

USB3_CC _TX_N2_C

G518 MOS Current Limit

3

TVW DF1004AD0_DF N9

A A

USB20_P 2<14>

USB20_N 2<14>

USB20_P 2

USB20_N 2

5

SC300003 Z00

LS10

EMI@

2

3

DLM0NSN 900HY2D_4P

SM

0700 05U0 0

1

USB20_N 2_L

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2017/07/ 20 2018/07 /20

3

USB20_P 2_L

1

CC1_VCONN & CC2_VCONN need 20miil trace width.

Compal Secret Data

Deciphered Date

Title

Size Document Number Re v

Custom

Date : Sheet o f

2

Date : Sheet o f

Compal Electronics, Inc.

CC+USB TYPE C

EH5VF M/B LA-H501P

43

1

1A

101Friday, February 22, 2019

5

D D

C C

4

3

2

1

Reserve Page

B B

A A

Security Cl assification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2017/11/23 2017/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document N umber Re v

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

N18E-GDDR6_D

EH5VF M/B LA-H501P

1

1A

44 101Friday, February 22, 2019

1A

5

D D

C C

4

3

2

1

Reserve Page

B B

A A

Security Cl assification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2017/11/23 2017/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document N umber Re v

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

N18E-GDDR6_D

EH5VF M/B LA-H501P

1

1A

45 101Friday, February 22, 2019

1A

5

D D

C C

4

3

2

1

Reserve Page

B B

A A

Security Cl assification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2017/11/23 2017/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document N umber Re v

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

N18E-GDDR6_D

EH5VF M/B LA-H501P

1

1A

46 101Friday, February 22, 2019

1A

5

D D

C C

4

3

2

1

Reserve Page

B B

A A

Security Cl assification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2017/11/23 2017/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document N umber Re v

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

N18E-GDDR6_D

EH5VF M/B LA-H501P

1

1A

47 101Friday, February 22, 2019

1A

5

D D

C C

4

3

2

1

Reserve Page

B B

A A

Security Cl assification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2017/11/23 2017/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document N umber Re v

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

N18E-GDDR6_D

EH5VF M/B LA-H501P

1

1A

48 101Friday, February 22, 2019

1A

5

D D

C C

4

3

2

1

Reserve Page

B B

A A

Security Cl assification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2017/11/23 2017/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document N umber Re v

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

N18E-GDDR6_D

EH5VF M/B LA-H501P

1

1A

49 101Friday, February 22, 2019

1A

5

D D

C C

4

3

2

1

Reserve Page

B B

A A

Security Cl assification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2017/11/23 2017/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document N umber Re v

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

N18E-GDDR6_D

EH5VF M/B LA-H501P

1

1A

50 101Friday, February 22, 2019

1A

A

B

C

D

E

+3V_LAN Rising time (10%~90%) must >0.5mS and <100mS

+3VALW +3V_LAN

60mil

1 1

2

CL16

1U_0201_6.3V6M

+3VS

12

2 2

1 2

1

From EC

High active. EN

threshold v oltage min:1.2V typ:1.6V max:2.0 V Current lim it threshold 1.5~2.8A

+3V_LAN Rising ti me must >0.5ms and < 100ms

RL3 1K_0402_5%

ISOLATEB

RL5 15K_0402_5%

RL2 0_0805_5%

1 2

UL1

5

IN

4

EN

SY6288C20AAC_SOT23-5

LAN_PWR_EN

@

OUT

GND

OC

1

2

3

LAN_PWR_EN <58>

60mil

LAN_CLKREQ# pull up at PCH side

YL1

CL21

18P_0402_50V8J

25MHZ_20PF_XRCGB25M000F2P 18R0

3

XTLI

3

NC

1

2

NC

2

4

XTLO_R

1

RL14

1

CL22 18P_0402_50V8J

2

1 2

680_0402_5%

P/N: SJ10000UP00 (S CRYSTAL 25MHZ 10PF XRCGB25M000F2P34R0)

3 3

RTL8111H LDO mode

RT

W=60mi l

+REGOUT

CL1

0.1U_0201_10V6K

1

LDO@

2

XTLO

L8118ASA SWR mode

LDO@

1 2

RL1 0_0603_ 5%

SWR@

1 2

LL1

2.2UH_HPC252012NF-2R2M_20%

IDC=1200mA

Using fo r Switch mode

The trac e length from Lx

to PIN48 (R EGOUT) and from C to Lx must < 200mils.

1

/27: P/N change to SH00000RT00

1

( S COIL 2.2UH +-20% HP

C252012NF-2R2M 1.3A)

+3V_LAN

+LAN_VDD

LAN_CLKREQ#<15> PCIE_PTX_C_DRX_P14<17> PCIE_PTX_C_DRX_N14<17>

CLK_PCIE_LAN<15> CLK_PCIE_LAN#<15>

W=60mi l

300mA

CL3

0.1U_0201_10V6K

CL2

4.7U_0402_6.3V6M

1

SWR@

2

CL4

0.1U_0201_10V6K

1

2

CL6

0.1U_0201_10V6K

CL7

CL5

0.1U_0201_10V6K

1

2

0.1U_0201_10V6K

1

2

1

2

CL8

0.1U_0201_10V6K

+LAN_VDD

1

2

CL9

1U_0201_6.3V6M

Place near Pin 22Place near Pin 3,8,22,30

+3V_LAN

300mA

CL10

0.1U_0201_10V6K

1

2

Place near Pin 11,32

Using for Switch mode

The trace length from C to PIN46,47(VDDREG) must < 200mils.

UL2

LAN_MIDI0+ LAN_MIDI0-

LAN_MIDI1+ LAN_MIDI1LAN_MIDI2+ LAN_MIDI2-

LAN_MIDI3+ LAN_MIDI3-

1

MDIP0

2

MDIN0

3

AVDD10

4

MDIP1

5

MDIN1

6

MDIP2

7

MDIN2

8

AVDD10

9

MDIP3

10

MDIN3

11

AVDD33

12

CLKREQB

13

HSIP

14

HSIN

15

REFCLK_P

16

REFCLK_N

RTL8111GS-CG_QFN32_4X4

SA0000B9F20

HSOP HSON

PERSTB

ISOLATEB

LANWAKEB

DVDD10 VDDREG REGOUT

LED2

LED1/GPIO

LED0 CKXTAL1 CKXTAL2

AVDD10

RSET

AVDD33

GND

PCIE_PRX_C_DTX_P14

17

PCIE_PRX_C_DTX_N14

18 19 20

ISOLATEB LAN_PME#

21 22 23 24

+REGOUT LAN_LED2

25

LAN_LED1_GPO

26

LAN_LED0

27 28

XTLI

29

XTLO

30

LAN_RST

31 32 33

T1 @

T2 @ RL70_0402_5%

1 2

2.49K_0402_1%

Place near Pin 11,32

W=60mi l

CL11

0.1U_0201_10V6K

1

2

+LAN_VDD +3V_LAN

12

@

RL8

CL14

CL13

0.1U_0201_10V6K

CL12

4.7U_0402_6.3V6M

1

SWR@

2

4.7U_0402_6.3V6M

1

@

2

Reserve for surge improvement

Place near Pin 11,32

12

CL17.1U_0402_16V 7K

12

CL18.1U_0402_16V 7K

reserve EC_PME# pull high 47K to +3VLP_EC

1 2

LAN_GPO <18>

for disable PHY reserve 0 ohm

LAN_LED1_GPO

PCIE_PRX_DTX_P14 <17> PCIE_PRX_DTX_N14 <17>

PLT_RST_BUF# <16,52,68>

RL40_040 2_5% @

12

RL610K_0402_5%

+3V_LAN

CL15

4.7U_0402_6.3V6M

1

@

2

EC_PME# <16,58>

+3V_LAN

12

RL910K_0402_5% @

SA0000B9F20, S IC RTL8118ASA-CG QFN 32P E-LAN CTRL

LAN Connector

LAN_MIDI3LAN_MIDI3+

LAN_MIDI2LAN_MIDI2+

LAN_MIDI1LAN_MIDI1+

LAN_MIDI0LAN_MIDI0+

0.1U_0201_10V6K

4 4

LAN_TERMAL

1

2

TL1

1 2 3

4 5 6

7 8 9

10 11 12

GST5009-E

SP050006B10

TCT1 TD1+ TD1-

TCT2 TD2+ TD2-

TCT3 TD3+ TD3-

TCT4 TD4+ TD4-

MCT1

MX1+

MX1-

MCT2

MX2+

MX2-

MCT3

MX3+

MX3-

MCT4

MX4+

MX4-

24 23 22

21 20 19

18 17 16

15 14 13

12

RL11

RL12

75_0402_1%

RJ45_MIDI3RJ45_MIDI3+

RJ45_MIDI2RJ45_MIDI2+

RJ45_MIDI1RJ45_MIDI1+

RJ45_MIDI0RJ45_MIDI0+

12

RL13

RL10

75_0402_1%

RJ45_GND

RJ45_MIDI3-

RJ45_MIDI3+

RJ45_MIDI1-

RJ45_MIDI2-

RJ45_MIDI2+

RJ45_MIDI1+

RJ45_MIDI0-

RJ45_MIDI0+

JRJ45

8

PR4-

7

PR4+

6

PR2-

5

PR3-

4

PR3+

3

PR2+

2

PR1-

1

PR1+

SANTA_130460-5

CONN@

DC234007W00

GND GND GND GND

12 11 10 9

LANGND

il

10P_0402_50V8J

3

1

40mil40m

RJ45_GND

12

2

MESC5V02BD03_SOT23-3

DL1

ESD@

@

JPL1 JUMP_43X118CL24

CL23

Security Cl assification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2017/10/30 2018/10/30

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document N umber Re v

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

LAN RTL8118ASA

EH5VF M/B LA-H501P

E

1A

51 101Friday, February 22, 2019

1A

A

Wireless LAN

B

C

D

E

+3VALW +3VS_W LAN

CM15

1U_0201_6.3V6M

1

1 1

2 2

@

2

+3VALW

RM44 0_0805_ 5%@

+3VS

RM11 0_0805_ 5%NIOA C@

60mil

WLAN _ON<58>

1 2

4.7U_040 2_6.3V6M

+3VS_W LAN

CM12

5

4

1

2

NGFF WL+BT (KEY E)

3 3

W=60mils

UM1

IN

EN

SY6288C20 AAC_SOT23-5

IOAC@

1

2

1

OUT

2

GND

3

OC

CM14

0.1U_0201_10V6K

0.1U_0201_10V6K CM13

1

@

2

(link to PICE Port 3)

(From PCH CLKOUT2 )

PCIE CLK

re

serve for cnvi

@

1

CM19

4.7U_040 2_6.3V6M

2

PCIE X1

+3VS_W LAN

(For BT)

PCIE_PTX_ C_DRX_P15<17>

PCIE_PRX_ DTX_P15<17> PCIE_PRX_ DTX_N15<17>

CLK_PCIE_ WLAN<15> CLK_PCIE_ WLAN#<15>

WLAN _CLKREQ#<15>

RM16 10K _0402_5%

UART_2_ PRXD_R_DTXD UART_2_ PTXD_R_DRXD

1 2

RM42 0_0402_ 5%UA RT@

1 2

RM43 0_0402_ 5%UA RT@

UART_2_ PRXD_DTXD <19>

UART_2_ PTXD_DRXD <1 9>

Co-layout with CNVi for SW debug

reserve 1000p for cnvi

2 4 6 8 10 12 14 16 18 20 22

24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66

68

+3VS_W LAN

CNV_RF_ RESET#_R

CLKREQ_ CNV#_R

UART_2_ PRXD_R_DTXD

UART_2_ PTXD_R_DRXD

E51TXD_ P80DATA_R E51RXD_ P80CLK_R

SUSCLK_ R WL_R ST#_R BT_ON WL_O FF#

REFCLK_ CNV_R

T52@

T53@

RM34 0_0201_ 5%@

RM35 0_0201_ 5%@

1 2

RM36 0_0402_ 5%CN VI@

1 2

RM37 0_0402_ 5%CN VI@

1 2

RM12 0_0201_ 5%@

1 2

RM13 0_0201_ 5%@

1 2

RM14 0_0201_ 5%@

1 2

RM15 0_0201_ 5%@

1 2

RM40 0_0402_5%E SD@

E51TXD_ P80DATA_R

1 2

1

CM17

0.1U_020 1_10V6K

For ESD req reserve LC filter

2

cl

12

RM19 100K_04 02_5%

JNGFF1

KEY E

1

GND_1

USB20_P 14<1 4> USB20_N 14<14>

CNV_PRX _DTX_N1<1 5>

CNV_PRX _DTX_P1<15>

CNV_PRX _DTX_N0<1 5>

CNV_PRX _DTX_P0<15>

CLK_CNV _PRX_DTX_N<1 5> CLK_CNV _PRX_DTX_P<15>

WLAN _PME#

CNV_PTX _DRX_N1<1 5> CNV_PTX _DRX_P1<15>

CNV_PTX _DRX_N0<1 5> CNV_PTX _DRX_P0<15>

CLK_CNV _PTX_DRX_N<1 5> CLK_CNV _PTX_DRX_P<15>

WLAN _PME#

12

3

USB_D+

5

USB_D-

7

GND_7

9

SDIO_CLK

11

SDIO_CMD

13

SDIO_DAT0

15

SDIO_DAT1

17

SDIO_DAT2

19

SDIO_DAT3

21

SDIO_WAKE

23

SDIO_RST

25

GND_33

27

PET_RX_P0

29

PET_RX_N0

31

GND_39

33

PER_TX_P0

35

PER_TX_N0

37

GND_45

39

REFCLK_P0

41

REFCLK_N0

43

GND_51

45

CLKREQ0#

47

PEWAKE0#

49

GND_57

51

RSVD/PCIE_RX_P1

53

RSVD/PCIE_RX_N1

55

GND_63

57

RSVD/PCIE_TX_P1

59

RSVD/PCIE_TX_N1

61

GND_69

63

RSVD_71

65

RSVD_73

67

GND_75

69

GND2

BELLW _80152-3221

CONN@

SP070013E00

3.3VAUX_2

3.3VAUX_4 LED1#

PCM_CLK

PCM_SYNC

PCM_OUT

PCM_IN

LED2#

GND_18

UART_WAKE

UART_TX

UART_RX UART_RTS UART_CTS

CLink_RST

CLink_DATA

CLink_CLK

COEX3 COEX2 COEX1

SUSCLK(32KHz)

PERST0# W_DISABLE2# W_DISABLE1#

I2C_DAT

I2C_CLK

I2C_IRQ RSVD_64 RSVD_66 RSVD_68 RSVD_70

3.3VAUX_72

3.3VAUX_74

GND1

@

1 2

CM18 100 0P_0402_50V7 K

CNVI@

1 2

RM41

75K_040 2_1%

CNV_RF_ RESET# <18>

CLKREQ_ CNV# <18>

E51TXD_ P80DATA <58>PCIE_PTX_ C_DRX_N15<17> E51RXD_ P80CLK <5 8>

SUSCLK <18,68> PLT_RST _BUF# <16,5 1,68>

BT_ON <5 8> WL_O FF# <58 >

REFCLK_ CNV <15>

For CNVi Feature

XESD@

ose PCH

CNV_BRI_P RX_DTX <15>

CNV_RGI_P TX_DRX <15> CNV_RGI_P RX_DTX <15>

CNV_BRI_P TX_DRX <15>

reserve for BT_ON OD pull high (1.0)

4 4

Security Classification

2017/10/ 30 2018/10 /30

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

2017/10/ 30 2018/10 /30

C

Compal Secret Data

Deciphered Date

D

BT_ON

1 2

@

RM458.2K_040 2_5%

Compal Electronics, Inc.

Title

Size Document Number Re v

Custom

Date : Sheet o f

Compal Electronics, Inc.

M.2 Key E (WLAN)

EH5VF M/B LA-H501P

+3VS_W LAN

52 1 01Friday, February 22, 201 9

E

1A

5

D D

C C

4

3

2

1

Reserve Page

B B

A A

Security Cl assification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2017/11/23 2017/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document N umber Re v

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

N18E-GDDR6_D

EH5VF M/B LA-H501P

1

1A

53 101Friday, February 22, 2019

1A

5

D D

C C

4

3

2

1

Reserve Page

B B

A A

Security Cl assification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2017/11/23 2017/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document N umber Re v

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

N18E-GDDR6_D

EH5VF M/B LA-H501P

1

1A

54 101Friday, February 22, 2019

1A

5

D D

C C

4

3

2

1

Reserve Page

B B

A A

Security Cl assification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2017/11/23 2017/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document N umber Re v

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

N18E-GDDR6_D

EH5VF M/B LA-H501P

1

1A

55 101Friday, February 22, 2019

1A

A

B

C

D

E

HD

Audio Codec

1 1

Reserved for RF

2 2

+3VS

RA13 100K_0402_1%

3 3

SENSE_A

12

HDA_RST#_R<1 8>

HP_PLUG#<7 3>

+5VS

12

XEMI@

GNDA

2000mA 600ohm@100MHz DCR 0.1

LA1

TAI-TECH HCB160 8KF-601T20

1 2

SM01000UN0 0

Use LV1 symbol.

+3VS

RA2 0_0402_5%

+3VS

RA4 0_0402_5%

DMIC_CLK

CA2710P _0402_50V8J

EC_MUTE#<58>

Close codec

RA12 200K_0402_1%

RA17 20K_0402_5%@

GND

1 2

@

1 2

@

+MICBIAS

40mil

12

1

CA15 1U_0201_6 .3V6M

2

+3VS_DVDD

GNDA

RA19 0_0402_ 5%@

CA1

10U_0402_6.3V6M

1

2

r Pin41

ne

ar Pin9

near Pin1

LINE1_L LINE1_R

RING2 SLEEVE

DMIC_DATA DMIC_CLK

MONO_IN

+3VALW

CA19

10U_0402_ 6.3V6M

40mil

CA2

0.1U_0201_10V6K

1

2

1 2

CA7 0.1U_0201_ 10V6K

1 2

CA8 10U_0402_ 6.3V6M

mil

20

CA9

10U_0402_6.3V6M

1

2

22 21

24 23

31 30

17 18

2 3

47

11

12

SENSE_A

13 14 15

37 35

36

20

19

1 2

12

4

49

CA3

0.1U_0201_10V6K

CA29

10U_0402_6.3V6M

1

2

near Pin46nea

+3VS_DVDDIO

+3VS_DVDD

CA10

0.1U_0201_10V6K

1

2

1

UA1

LINE1-L(PORT-C-L) LINE1-R(PORT-C-R)

LINE2-L(PORT-E-L) LINE2-R(PORT-E-R)

LINE1-VREFO-L LINE1-VREFO-R

MIC2-L(PORT-F-L) /RING MIC2-R(PORT-F-R) /SLEEVE

GPIO0/DMIC-DATA GPIO1/DMIC-CLK

PDB

RESETB

PCBEEP

HP/LINE1 JD(JD1) MIC2/LINE2 JD(JD2) SPDIFO/FRONT JD(JD3)/GPIO3

CBP CBN

CPVDD

VD33 STB

MIC CAP

DC DET Thermal PAD

ALC255-CG_MQFN 48_6X6

SA000082700

DVDD

+5VS_PVDD

9

DVDD-IO

41

PVDD1

+5VS_AVDD

26

46

AVDD1

PVDD2

20mil

GNDA

near Pin26

+1.8VS_VDDA

GNDA

40

AVDD2

SPK-OUT-L-

SPK-OUT-L+

SPK-OUT-R+

SPK-OUT-R-

HPOUT-L(PORT-I-L)

HPOUT-R(PORT-I-R)

SYNC BCLK

SDATA-OUT

SDATA-IN

SPDIF-OUT/GPIO2

MONO-OUT

MIC2-VREFO

LDO3-CAP LDO2-CAP LDO1-CAP

VREF

CPVEE

AVSS1 AVSS2

CA5

0.1U_0201_10V6K

10U_0402_6.3V6M

1

2

CA11

0.1U_0201_10V6K

1

2

Place near Pin40

43

SPKL-

42

SPKL+

45

SPKR+

44

SPKR-

HP_LEFT

32

HP_RIGHT

33

HDA_SYNC_R

10

HDA_BIT_CLK_R

6

HDA_SDOUT_R

5

HDA_SDIN0_AUDIO

8

48

16

29

7 39 27

10mil

CODEC_VREF

28

34

CPVEE

25 38

GNDA

RA1

@

0_0603_5%

1 2

CA6

1 2

RA3 0_0402_5%

CA12

10U_0402_6.3V6M

1

2

SPKR+ <73 > SPKR- <7 3>

+MIC2_VREFO

CA14 10U_0402_ 6.3V6M CA16 10U_0402_ 6.3V6M CA17 10U_0402_ 6.3V6M RA14 100K_0 402_5%

CA20 2.2U_0402_ 6.3V6M

CA21 0.1U_0201_ 10V6K@

CA22

1U_0201_6.3V6M

1

2

+5VS

@

HDA_BIT_CLK_R

1 2

RA10 33_0402_5%

1 2 1 2 1 2

1 2

+1.8VS

1 2

2

1

RA5 0_0402_5%

XEMI@

CA13 22P_0402_5 0V8J

XEMI@

GNDA

HDA_SYNC_R <18> HDA_BIT_CLK_R <18> HDA_SDOUT_R <18> HDA_SDIN0 <18>

GND

GNDA

Int. Speaker Conn.

SPKL+ SPKL-

1 2

LA4 EMI@ PBY160 808T-121Y-N_2P

1 2

LA5 EMI@ PBY160 808T-121Y-N_2P

Digital MIC

MIC BOM upload by Audio Team

PCH_DMIC_DATA0<18>

PCH_DMIC_CLK 0<18>

40mil

DMIC_DATA

PCH_DMIC_DATA0

PCH_DMIC_CLK 0

DMIC_CLK

@

RA7 0_0402_5%

@

RA8 33 _0402_5%

@

RA9 33 _0402_5%

LA6 B LM15PX221SN1D_2PEM I@

SM01000Q500

change PN to SM01000Q500

SPK_L+ SPK_L-

DMIC_DATA_R

12

DMIC_CLK_R

12

JSPK2

1

2

3

G1

4

G2

CVILU_CI4202M2HR 0-NH

CONN@

SP02001CK0 0

TO eDP cable

DMIC_DATA_R <38>

DMIC_CLK_R <38>

GND

Headphone Out

+MIC2_VREFO

RA15 2.2K_0402_5%

RA18 2.2K_0402_5%

1 2

O

IO/B

T

SLEEVE

RING2

SLEEVE <73 >

RING2 <73>

HP_RIGHT HPOUT_R _1

RA22

22K_0402_5 %

RA27

22K_0402_5 %

A

12

BEEP#<58>

4 4

PCH_SPKR<18,19>

BEEP#_R

XESD@

100P_0402_50V8J

1

CA26

2

1 2

GND

1U_0201_6 .3V6M

1 2

RA24

4.7K_0402_5 %

CA25

MONO_IN

1 2

RA25 0_0402_ 5%@

1 2

RA29 0_0402_ 5%@

1 2

RA31 0_0402_ 5%@

1 2

RA33 0_0402_ 5%@

B

1 2

RA26 0_0402_ 5%@

1 2

RA30 0_0402_ 5%@

1 2

RA32 0_0402_ 5%@

1 2

RA34 0_0402_ 5%@

GNDAGND GND GNDA

+MICBIAS

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2017/10/30 2018/10/30

Compal Secret Data

Deciphered Date

D

LINE1_L

LINE1_R

DA3

1

BAT54A-7-F_SOT23 -3

SCSBAT54100

1 2

RA21 0_0603 _5%@

1 2

CA23 4.7 U_0402_6.3V6M

1 2

CA24 4.7 U_0402_6.3V6M

2

RA23

4.7K_0402_5 %

3

RA28

4.7K_0402_5 %

Title

Size Document Number Re v

Custom

Date : Sheet o f

1 2

RA20 0_0603 _5%@

HPOUT_L_1HP_LEFT

12

Compal Electronics, Inc.

HD Audio Codec ALC255

EH5VF M/B LA-H501P

E

HPOUT_L_1 <73>

HPOUT_R_1 <73>

56 1 01Friday, February 22, 2019

1A

5

D D

C C

4

3

2

1

Reserve Page

B B

A A

Security Cl assification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2017/11/23 2017/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document N umber Re v

Date: Sheet o f

2

Date: Sheet o f

Compal Electronics, Inc.

N18E-GDDR6_D

EH5VF M/B LA-H501P

1

1A

57 101Friday, February 22, 2019

1A

A

B

C

D

E

Board ID

+3VLP

JPB1

2

e

asurement

112

JUMP_43X39

@

SUSPWRD NACK<18> CHG_CTL3< 71>

TPM_SERIRQ<17,66>

LPC_FRAME#<17> LPC_AD3<17> LPC_AD2<17> LPC_AD1<17> LPC_AD0<17>

CLK_LPC_R<17> PLT_RST#<16,27 ,66> EC_RST#<77>

EC_SCI#<19>

WLAN_ON<52>

KSI[0..7]<63>

KSO[0..17]< 63>

EC_SMB_CK1<82,83>

EC_SMB_DA1<82,83> PCH_SML1CL K<18,27,66> PCH_SML1DAT A< 18,27,66>

PU at CPU side

PM_SLP_S3#<18,78>

OVRM_EN< 17,36>

SPOK_3V<84 ,87>

TP_EN<63>

TS_EN<19 ,38> WL_OFF#<52> AC_PRESENT< 18>

KBL_EN<63>

FAN_SPEED1<77> FAN_SPEED2<77>

E51TXD_P80D ATA<52 >

E51RXD_P80CL K<52>

PCH_PWR OK<18,78>

PWR_SUSP _LED#<73>

PBTN_OUT#<18>

PM_SLP_S4#<18,78>

RB76 0_0402_5 %@

12

B

0.1U_0201_10V6K

ES

PI Bus Pin : 1~5.7.8.10.12.14

LPC Bus Pin : 3~5.7.8.10.12.13

CB1

1

2

SUSPWRD NACK CHG_CTL3

TPM_SERIRQ LPC_FRAME# LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0

CLK_LPC_R PLT_RST# EC_RST# EC_SCI# WLAN_ON

KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16 KSO17

EC_SMB_CK1 EC_SMB_DA1

PM_SLP_S3#

TP_EN TS_EN WL_OFF# AC_PRESENT

FAN_SPEED1 FAN_SPEED2 E51TXD_P80D ATA E51RXD_P80CL K

PWR_SUSP _LED# TURBO_EN#

PBTN_OUT# PM_SLP_S4#

CB2

1

2

CO-LAY with K B9032QA (SA000080J00)

VR_PWRGD

+3VLP_EC

1 2

RB4 47K_0 402_5%@

+3VALW

1 1

+3VLP_EC

2 2

+5VALW

1 2

RB78 10K_0402 _5%

1 2

CB14 0.1U_0201_ 10V6K

For turn off internal LPC module of KB9032

XESD@

1 2

CB5 100P_0402 _50V8J

1 2

CB6 100P_0402 _50V8J

XEMI@

12

CB7 22P_0402_5 0V8J

1 2

RB10 2.2K_0402 _5%

1 2

RB11 2.2K_0402 _5%

1 2

RB79 4.7K_0402 _5%

1 2

RB80 4.7K_0402 _5%

SPOK_3V

SPOK_5V

1 2

RB72 0_0402 _5%@

1 2

RB73 0_0402_ 5%@

XEMI@

RB6

33_0402_5 %

CLK_LPC_R

12

EC_PME#

TURBO_EN#

EC_RST#

PLT_RST#

AC_IN

EC_SMB_CK1 EC_SMB_DA1

EC_SMB_CK3 EC_SMB_DA3

SPOK_3V5V

For Power consumption M

For abnormal shutdown

1 2

DB2 RB 751V-40_SOD323-2

1 2

DB3 RB 751V-40_SOD323-2

1 2

3 3

VCOUT1_PROCH OT VCOUT1_PROCHOT

4 4

DB4 RB 751V-40_SOD323-2

DGPU_AC_DETE CT SW_PROCHOT#

2N7002KDW _SOT363-6

@

QB1A

61

D

2

G

S

XESD@

1 2

CB10 .1U_0402_1 6V7K

XESD@

1 2

CB11 .1U_0402_1 6V7K

XESD@

1 2

CB12 .1U_0402_1 6V7K

XESD@

1 2

CB13 .1U_0402_1 6V7K

EC_RSMRST#SPOK_3V5V

PCH_PWR OK

EC_VCCST_PG_ R

VCOUT1_PROCH OT

RB19

@

0_0402_5%

1 2

@

QB1B

34

D

2N7002KDW _SOT363-6

5

G

S

SUSP#

SYSON

A

VCCCORE_VR_PW RGD<89>

+3VLP_EC

UB1

1

GATEA20/GPIO00

2

KBRST#/GPIO01

3

SERIRQ

4

LPC_FRAME#

5

LPC_AD3

7

LPC_AD2

8

LPC_AD1

10

LPC_AD0

12

CLK_PCI_EC

13

PCIRST#/GPIO05

37

EC_RST#

20

EC_SCI#/GPIO0E

38

CLKRUN#/GPIO1D

55

KSI0/GPIO30

56

KSI1/GPIO31

57

KSI2/GPIO32

58

KSI3/GPIO33

59

KSI4/GPIO34

60

KSI5/GPIO35

61

KSI6/GPIO36

62

KSI7/GPIO37

39

KSO0/GPIO20

40

KSO1/GPIO21

41

KSO2/GPIO22

42

KSO3/GPIO23

43

KSO4/GPIO24

44

KSO5/GPIO25

45

KSO6/GPIO26

46

KSO7/GPIO27

47

KSO8/GPIO28

48

KSO9/GPIO29

49

KSO10/GPIO2A

50

KSO11/GPIO2B

51

KSO12/GPIO2C

52

KSO13/GPIO2D

53

KSO14/GPIO2E

54

KSO15/GPIO2F

81

KSO16/GPIO48

82

KSO17/GPIO49

77

EC_SMB_CLK1/GPIO44

78

EC_SMB_DAT1/GPIO45

79

EC_SMB_CLK2/GPIO46

80

EC_SMB_DAT2/GPIO47

6

PM_SLP_S3#/GPIO04

14

GPIO07

15

GPIO08

16

GPIO0A

17

GPIO0B

18

GPIO0C

19

AC_PRESENT/GPIO0D

25

PWM2/GPIO11

28

FAN_SPEED1/GPIO14

29

FANFB1/GPIO15

30

EC_TX/GPIO16

31

EC_RX/GPIO17

32

PCH_PWROK/GPIO18

34

SUSP_LED#/GPIO19

36

NUM_LED#/GPIO1A

122

PBTN_OUT#/GPIO5D

123

PM_SLP_S4#/GPIO5E

RB2

@

0_0402_5%

1 2

+3VLP_LPC

LPC & MISC

Int. K/B Matrix

LB1 FBMA-L11-16080 8-800LMT_0603

1 2

22

33

96

125

67

111

9

VCC

VCC0

VCC_LPC

PWM Output

VCIN1_BATT_TEMP/AD0/GPIO38 VCIN1_BATT_DROP/AD1/GPIO39

AD Input

DA Output

EC_MUTE#/PSCLK1/GPIO4A

USB_EN#/PSDAT1/GPIO4B

PS2 Interface

SPI Device Interface

SPI Flash ROM

SYS_PWROK/AD7/GPIO41

BATT_CHG_LED#/GPIO52

GPIO

BATT_LOW_LED#/GPIO55

SM Bus

EC_RSMRST#/GPXIOA03

VCIN1_ADP_PROCHOT/GPXIOA05

VCOUT1_PROCHOT#/GPXIOA06

VCOUT0_MAIN_PWR_ON/GPXIOA07

GPO

GPIO

PCH_PWR_EN/GPXIOA10

PWR_VCCST_PG/GPXIOA11

GPI

GND

11

24

35

69

94

113

ECAGND

2015/1/9 acer require:

erved protact circuit when

res adaptor 107% happen

EC_VCCST_PG/GPIO0F

EN_DFAN1/DA1/GPIO3D

EC_CIR_RX/AD6/GPIO40

VCIN1_AC_IN/GPXIOD01

+3VLP_ECA

1

CB3

0.1U_0201_ 10V6K

2

ECAGND

ECAGND <66,82>

AVCC

BEEP#/GPIO10

EC_FAN_PWM/GPIO12

AC_OFF/GPIO13

ADP_I/AD2/GPIO3A

AD_BID/AD3/GPIO3B

AD4/GPIO42 AD5/GPIO43

DA0/GPIO3C

DA2/GPIO3E

DA3/GPIO3F

PSCLK2/GPIO4C PSDAT2/GPIO4D TP_CLK/GPIO4E

TP_DATA/GPIO4F

ENKBL/GPXIOA00

WOL_EN/GPXIOA01

ME_EN/GPXIOA02

VCIN0_PH1/GPXIOD00

MISO/GPIO5B MOSI/GPIO5C

SPICLK/GPIO58

SPICS#/GPIO5A

GPIO50

CAPS_LED#/GPIO53

PWR_LED#/GPIO54

SYSON/GPIO56

VR_ON/GPIO57

DPWROK_EC/GPIO59

GPXIOA04

BKOFF#/GPXIOA08

GPXIOA09

EC_ON/GPXIOD02 ON/OFF#/GPXIOD03 LID_SW#/GPXIOD04

SUSP#/GPXIOD05

GPXIOD06

PECI/GPXIOD07

V18R/VCC_IO2

AGND

KB9022QD_LQFP 128_14X14

20mil

1 2

CB9

100P_0402_ 50V8J

LB2

FBMA-L11-16080 8-800LMT_0603

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

21 23 26 27

63 64 65 66 75 76

68 70 71 72

83 84 85 86 87 88

97 98 99 109

119 120 126 128

73 74 89 90 91 92 93 95 121 127

100 101 102 103 104 105 106 107 108

110 112 114 115 116 117 118

124

BATT_TEMP

12

EC_VCCST_PG_ R

BEEP# FAN_PWM1

FAN_PWM2

BATT_TEMP CHG_CTL1 ADP_I AD_BID

LAN_PWR_E N EC_TP_INT# VR_PWRGD

EC_MUTE# USB_EN

TP_CLK TP_DATA

ENBKL TP_PWR_ EN

ME_EN VCIN0_PH

BT_ON EC_CLR_CM OS FP_PWR_EN

SYS_PWROK_R

BATT_BLUE_L ED#

PWR_LED # BATT_AMB_LED#

SYSON VR_ON

CHG_ILMSEL

EC_RSMRST# DGPU_AC_DETE CT VCIN1_ADP_PROCHOT VCOUT1_PROCH OT

MAINPWON BKOFF#

THERMAL_ALERT # 3V_EN_R

AC_IN EC_ONPCH_PWR OK

ON/OFFBTN# LID_SW#

SUSP# SW_PROCH OT#

EC_PECI

2017/10/30 2018/10/30

EC_VCCST_PG_ R <10,78> BEEP# <56>

FAN_PWM1 <77> FAN_PWM2 <77>

BATT_TEMP <82,83>

CHG_CTL1 <71> ADP_I < 82,83>

VRAM_TEMP <66 > EC_PME# < 16,51>

LAN_PWR_E N <51>

EC_TP_INT# <16,63>

GPU_OVERT# <27>

EC_MUTE# < 56> USB_EN <42,72,73>

EC_SMB_CK3 <63> EC_SMB_DA3 <63> TP_CLK <63> TP_DATA <63>

ENBKL < 17> TP_PWR_ EN <63>

ME_EN <18>

VCIN0_PH < 82>

SPOK_5V < 84> BT_ON <52>

FP_PWR_EN <66>

TYPEC_1P5A_EC <42,43>

BATT_4S <83> BATT_BLUE_L ED# <73> LEDPWR_ EN <63> PWR_LED # <73> BATT_AMB_LED# <73>

SYSON <78,85,87> VR_ON <78,88,89> CHG_ILMSEL <71>

EC_RSMRST# <18> DGPU_AC_DETE CT <19,27,83> VCIN1_ADP_PROCHOT <82>

MAINPWON <77 ,82,84>

BKOFF# <38>

THERMAL_ALERT # <66>

CHG_EN <71>

AC_IN <83>

EC_ON <84>

ON/OFFBTN# <63> LID_SW# <66> SUSP# < 68,78,83,85,87,88>

1 2

RB16 33_0402_1 %

+3VLP_EC

Compal Secret Data

H_PECI <10,17>

Deciphered Date

D

near SOC

CB8

0.1U_0201_ 10V6K

XESD@

H_PROCHOT#<10,83 >

Analog B oard ID definition, Ple

ase see page 3.

EC_CLR_CM OS

RB26

10K_0402_5 %

SYS_PWROK_R

GPU_OVERT#

EC Internal PU

LID_SW#

DB1 RB751V-40_SOD 323-2

MAINPWON

1

3V_EN_R

2

Title

Size Document Number Re v

Custom

EH5VF M/B LA-H501P

Date : Sheet o f

+3VLP_EC

RB1

100K_0402_ 1%

RB3 20K_0402_1 %

12

RB7 0_0 402_5%

RB12 10K_04 02_5%VGA@

RB13 100K_0 402_1%

2

G

1 2

@

1 2

Ra

1 2

AD_BID

Rb

1 2

13

D

QB6 L2N7002W T1G_SC-70-3

S

SB00001GE00

PCH_RTCR ST# < 18>

+3VS

+3VLP_EC

For Thermal Portect Shutdown

1 2

RB14

1 2

1K_0402_5%

Compal Electronics, Inc.

EC ENE-KB9022

3V_EN

RB15 1M_0402_5%

RB17

@

0_0402_5%

1 2

RB18

@

0_0402_5%

1 2

VR_HOT#

SW_PROCH OT#H_PROCHOT#

E

1

CB4

@

0.1U_0201_ 10V6K

2

SYS_PWROK <18,78>

3V_EN < 84>

VR_HOT# <89>

58 1 01Friday, February 22, 2019

1A

5

D D

C C

4

3

2

1

Reserve Page

B B

A A

Security Cl assification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2017/11/23 2017/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document N umber Re v

Date: Sheet o f

2

Date: Sheet o f

Compal Electronics, Inc.

N18E-GDDR6_D

EH5VF M/B LA-H501P

1

1A

59 101Friday, February 22, 2019

1A

5

D D

C C

4

3

2

1

Reserve Page

B B

A A

Security Cl assification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2017/11/23 2017/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document N umber Re v

Date: Sheet o f

2

Date: Sheet o f

Compal Electronics, Inc.

N18E-GDDR6_D

EH5VF M/B LA-H501P

1

1A

60 101Friday, February 22, 2019

1A

5

4

3

2

1

BATTERY

CONN

Charger

2.2K

+3V S

SO-DIMM A & B

+1.8V SDGP U_M AIN

(QV2) PJT138KA

(QF1) 2N7002DW

2.2K

+5VS _BL

1.8K

VGA_I2CS_SCL

VGA_I2CS_SDA

2.2K

+3V S 2.2K

TMS_SMB_CLK

TMS_SM B_DATA

LED driver

+1.8V SDGP U_A ON

N17P-G0-K1 N18P-G0

+3V S

THERMAL SENSOR

I2CB_SCL

I2CB_SDA

I2CC_SCL

I2CC_SDA

2K

NVVDD controller

+1.8V SDGP U_A ON

2.2K

+3VA LW

(QH7) 2N

+3VA LW

(RH189/RH190) R-short

+3V S

7002DW

D_CK_SCL K

D_CK_SDATA

EC_SMB_ CK2

EC_SMB_DA2

499

49

9

2.2K

D D

Cannonlake

PCH - H

PCH_SMBCLK

PCH_SMBDATA

PCH_SML0CLK

PCH_SML0 DATA

2.2K

PCH_SML1CLK

PCH_SML1 DATA

2.2K

EC_SMB_ CK1

C C

KB

9022

EC_SMB_DA1

EC_SMB_ CK2

EC_SMB_DA2

+3VL P_E C

100 ohm

0 ohm

EC_SMB_CK1-1

EC_SMB_DA1-1

EC_SMB_CK1_ CHGR

EC_SMB_DA1_ CHGR

4.7K

EC_SMB_ CK3

EC_SMB_DA3

+5VA LW

+5VS _BL

(QE62) 2N7002DW

0 ohm

EC_SMB_CK3 _LEDDRV

EC_SMB_DA3 _LEDDRV

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELE CTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELE CTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2017/10/30 2018/10/30

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size

Date: Sheet of

Compal Electronics, Inc.

N17E-GDDR5_D

Document Number Rev

EH5VF M/B LA-H501P

1

61 101Friday, February 22, 2019

1A

5

D D

C C

4

3

2

1

Reserve Page

B B

A A

Security Cl assification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2017/11/23 2017/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document N umber Re v

Date: Sheet o f

2

Date: Sheet o f

Compal Electronics, Inc.

N18E-GDDR6_D

EH5VF M/B LA-H501P

1

1A

62 101Friday, February 22, 2019

1A

A

ON/OFF BTN

R17

+3VLP

1 1

ON/OFFBTN#<58 >

t Only

Tes

TOP

LED driver

2 2

EC_SMB_CK3 EC_SMB_DA3

2N7002KDW _SOT363-6

RE1 0_0 402_5%@ RE2 0_0 402_5%@

EC_SMB_CK3<58>

EC_SMB_DA3<58>

3 3

4 4

set RE7 to 10k / output = 1.875mA

A

100K_0402_ 5%

1 2

RK18 0_0603 _5%@

+5VS_BL

QE62B

@

S

2N7002KDW _SOT363-6

12 12

Raptor: NC for 59116F

12

G

5

34

D

G

2

S

D

QE62A

@

EC_SMB_CK3_ LEDDRV EC_SMB_DA3_LE DDRV

12

@

ON/OFFBTN#

+5VS_BL

12

61

12

RE65

4.7K_0402_1 %

RE64 10K_0402_5 %

RE70

2.2K_0402_5%

RE69

2.2K_0402_5%

12

@

EC_SMB_CK3_ LEDDRV

EC_SMB_DA3_LE DDRV

AD3 AD2 AD1 AD0

0 0 1

0

LED14P@

UE4

24

RESET

25

SCL

26

SDA

31

AD0

A0

32

AD1

A1

1

AD2

A2

2

AD3

A3

12

N.C.

13

N.C.

28

N.C.

29

N.C.

30

N.C.

7

GND

18

GND

TLC59116FIRH BR_VQFN32_5X5

LED14P@

B

Touch Pad

TP_DATA

+3V_PTP

TP_CLK

+5VALW

KBL_EN< 58>

LEDPWR_EN<58>

+5VS_BL+5VS_B L +5VS_BL

27

Vcc

KB_A_LED_R_D RV#

3

OUT0

KB_A_LED_G_DR V#

4

OUT1

KB_A_LED_B_DR V#

5

OUT2

KB_B_LED_R_ DRV#

6

OUT3

KB_B_LED_G_D RV#

8

OUT4

KB_B_LED_B_ DRV#

9

OUT5

KB_C_LED_R _DRV#

10

OUT6

KB_C_LED_G_ DRV#

11

OUT7

KB_C_LED_B_ DRV#

14

OUT8

KB_D_LED_R _DRV#

15

OUT9

KB_D_LED_G_ DRV#

16

OUT10

KB_D_LED_B_ DRV#

17

OUT11

19

OUT12

20

OUT13

21

OUT14

22

OUT15

23

GND

33

GND

B

DK2

XESD@

6

I/O4

5

VDD

4

I/O3

AZC099-04S.R7G_ SOT23-6

+5VS

1 2

R41 0_0603_5%

KBLED@

1 2

R42 0_0603_5%

LED14P@

1 2

R18 0_0201_5%

KBLED@

1 2

R43 0_0201_5%

LED14P@

llow SYSON

fo

1

CE3

LED14P@

0.1U_0201_ 10V6K

2

C

+3VALW

5

2

CK3

1U_0201_6 .3V6M

TP_PWR_EN<58>

TP_PWR_EN follow SYSON behavior

TP_EN

3

I/O2

2

GND

EC_TP_INT#

1

I/O1

5

4

AD0 AD1 AD2 AD3

12

4

1

SY6288C20AAC_SOT 23-5

U4

IN

EN

SY6288C20AAC_SOT 23-5

RE75

4.7K_0402_1 %

LED14P@

1

OUT

2

GND

3

OC

12

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

IN

EN

I2C_1_SCL<19>

+5VS_BL

RE74

4.7K_0402_1 %

LED14P@

Issued Date

OUT

GND

UK1

OC

12

+3V_PTP

1

2

3

2N7002KDW _SOT363-6

I2C_1_SDA<19>

0.1U_0201_10V6K C32

1

@

2

RE73

4.7K_0402_1 %

LED14P@

D

4.7U_0402_6.3V6M

CK2

1

2

+3V_PTP +3V_PTP

2

G

QK1A

6 1

S

D

1 2

@

RK12 0_0402_5%

QK1B

2N7002KDW _SOT363-6

1 2

RK13

3 4

D

2.2K_0402_5 %

5

G

0_0402_5%@

+3V_PTP

RK7 10K_0402_5 %

1 2

EC_TP_INT#

12

RK8

S

RK9

2.2K_0402_5 %

I2C_1_SCL_R

CK6 33P_0402_ 50V8J

CK7 33P_0402_ 50V8J

I2C_1_SDA_R

KB Conn. / Backlight

+5VS_BL

KB_A_LED_R_D RV# KB_A_LED_G_DR V# KB_A_LED_B_DR V# KB_B_LED_R_ DRV# KB_B_LED_G_D RV# KB_B_LED_B_ DRV# KB_C_LED_R _DRV# KB_C_LED_G_ DRV# KB_C_LED_B_ DRV# KB_D_LED_R _DRV#

D

KB_D_LED_G_ DRV# KB_D_LED_B_ DRV#

12

RE72

4.7K_0402_1 %

LED14P@

Compal Secret Data

2017/10/30 2018/10/30

Compal Secret Data

Deciphered Date

+3VALW

+3VS

XESD@

KSI[0..7]

KSO[0..17]

JBL1

1

2

3

4

5

GND

6

GND

ACES_51524-00 40N-001

CONN@

SP010022M00

JBL2

16

GND

15

GND

14

13

12

11

10

9

8

7

6

5

4

3

2

1

ACES_51522-01 401-P01

CONN@

SP01001R800

E

+3V_PTP

12

@

RK50_0402_ 5%

12

@

RK60_0402_ 5%

CK1

@

0.1U_0201_ 10V6K

12

TP_CLK

PS2

EC

PCH I2C

EC_TP_INT#<16,58>

TP_EN<58>

KSI[0..7] < 58>

KSO[0..17] <5 8>

Title

Size Document Number Re v

Custom

EH5VF M/B LA-H501P

Date : Sheet o f

TP_DATA

I2C_1_SDA_R I2C_1_SCL_R EC_TP_INT# TP_EN

+3V_PTP

12

RK10

4.7K_0402_5 %

TP_CLK TP_DATA

Compal Electronics, Inc.

KB & TP & TPM Connector

12

RK11

4.7K_0402_5 %

E

KSO16 KSO17

KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8

KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15

KSI0

KSI1

KSI2

KSI3

KSI4

KSI5

KSI6

KSI7

ON/OFFBTN#

JTP1

1

2

3

4

5

6

7

8

9

GND

10

GND

JXT_FP202DH-0 08M10M

CONN@

SP010020L00

TP_CLK <58> TP_DATA <58>

JKB1

30

GND2

29

GND1

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

ACES_85201-28 05

CONN@

SP01000GO00

63 1 01Friday, February 22, 2019

1A

5

D D

C C

4

3

2

1

Reserve Page

B B

A A

Security Cl assification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2017/11/23 2017/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document N umber Re v

Date: Sheet o f

2

Date: Sheet o f

Compal Electronics, Inc.

N18E-GDDR6_D

EH5VF M/B LA-H501P

1

1A

64 101Friday, February 22, 2019

1A

5

D D

C C

4

3

2

1

Reserve Page

B B

A A

Security Cl assification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2017/11/23 2017/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document N umber Re v

Date: Sheet o f

2

Date: Sheet o f

Compal Electronics, Inc.

N18E-GDDR6_D

EH5VF M/B LA-H501P

1

1A

65 101Friday, February 22, 2019

1A

5

4

3

2

1

THERMAL SENSOR

To Hall sensor/B

D D

LID_SW#<58>

C C

TPM

+3VALW +3VALW_T PM +3VS +3VS_TPM

R45 0_0603_5%

1 2

@

+3VALW

B B

A A

PCH_SPI_SO_R<16>

PCH_SPI_SI_R<16> PCH_SPI_CLK_R<16>

R48

TPM@

10K_0402_5%

1 2

TPM_SERIRQ<17,58>

PCH_SPI_CS#2<16>

PLT_RST#<16,27,58>

10U_0402_6.3V6M

1

2

PCH_SPI_CS#2

R50 33_0402 _1%TPM@ R51 33_0402 _1%TPM@ R52 33_0402 _1%TPM@

1 2

0.1U_0201_10V6K

C56

C59

1

2

TPM@

1 2 1 2 1 2

TH41

@

TPM_BADD

R470_0402_5% @

PCH_SPI_SO_TPM_R PCH_SPI_SI_TPM_R

PCH_SPI_CLK_TPM_R

near pin1

PCH_SPI_SO_TPM_R PCH_SPI_SI_TPM_R PCH_SPI_CLK_TPM_R

U9

29

SDA/GPIO0

30

SCL/GPIO1

6

GPIO3

24

MISO

21

MOSI/GPIO7

18

PIRQ/GPIO2

19

SCLK

20

SCS/GPIO5

17

PLTRST

27

NC

13

GPIO4

4

PP/GPIO6

NPCT750AAAYX_QFN32_5X5

TPM@

SA0000AQ250

SA0000AQ250, S IC NPCT750AABYX QFN 32P TPM

5

R46 0_0603_5%

1 2

@

1

2

VSB

VHIO VHIO

GND GND

PGND

10U_0402_6.3V6M

NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC

4

+3VLP

JHS1

1

2

3

4

5

GND

6

GND

ACES_51524-0040N-001

CONN@

SP010022M00

TMS@

0.1U_0201_10V6K

+3VS

RF23 10K_0 402_5%

1

2

0.1U_0201_10V6K C60

PGESD@

Finger Print

C55

0.1U_0201_10V6K

1

2

TPM@

near pin8,22

+3VS_TPM

0.1U_0201_10V6K

C58

1

2

TPM@

+3VALW

+5VALW

Security Cl assification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

@

1 2

RK14 0_0402_5%

1 2

RK15 0_0402_5%FP@

1U_0201_6.3V6M

FP_PWR_EN<58>

USB20_N8<14>

USB20_P8<14>

+FP_VCC

3

C57

0.1U_0201_10V6K

C54

1

TPM@

2

TPM@

+3VALW_TPM

1

8 22

2 3 5 7 9 10 11 12 14 15 26 25 28 31 32

16 23 33

2N7002KDW_SOT363-6

PCH_SML1CLK<18,27,58>

PCH_SML1DATA<18,27,58>

+3VS

1

CF20

2

1 2

TMS@

CK4

FP@

2017/11/23 2017/12/31

TMS@

QF1B

2N7002KDW_SOT363-6

TH_THERM#

2

1

FP_PWR_EN

1 2

@

RK16 0_0402_5%

1 2

@

RK17 0_0402_5%

DK1

FPESD@

6

I/O4

5

VDD

4

I/O3

AZC099-04S.R7G_SOT23-6

Compal Secret Data

+3VS

5

G

3 4

S

D

2

TMS@

QF1A

6 1

D

UF2

1

VDD

2

D+

3

ALERT#

D-

T_CRIT#4GND

NCT7718W_MSOP8

TMS@ SA000067P00

UK2

5

OUT

IN

GND

4

OC

EN

SY6288C20AAC_SOT23-5

FP@

USB20_N8_L

USB20_P8_L

3

I/O2

2

GND

USB20_N8_L

1

I/O1

Deciphered Date

RF10

2.2K_0402_5%

TMS@

G

S

8

SCL

7

SDA

6

5

1

2

3

+3VS

12

TMS_SMB_CLK

TMS_SMB_DATA

+FP_VCC

1

4.7U_0402_6.3V6M

2

12

RF9

2.2K_0402_5%

TMS@

TMS_SMB_CLK

TMS_SMB_DATA

SMBUS ADDRESS 10

01_1 000b

FP@

CK5

Close to VRAM choke

+3VLP_ECA

12

RF12

16.5K_0402_1%

VRAM_TEMP<58>

+3VS

12

TMS@

RF24 10K_0402_5%

THERMAL_ALERT# <58>

+FP_VCC

USB20_P8_L USB20_N8_L

ETU801 FA577E -1200

+FP_ VCC(5V) +FP_ VCC(3V)

1

USB P

2

USB N

3

GND

4

NC

5

NC

6

8 7 6 5 4 3 2 1

ACES_51522-00801-001

SP01001AE00

CONN@

7 8

Compal Electronics, Inc.

Title

Size Document N umber Re v

Date: Sheet o f

Compal Electronics, Inc.

Sensors/FP/TPM

EH5VF M/B LA-H501P

12

RH250 100K_0402_1%_TSM0B104F4251RZ

SL200002H00

JFP1

8

10

7

G2

9

6

G1 5 4 3 2 1

D+ DGND NC NC NC NC

1

TMS@

ECAGND <58,82>

66 101Friday, February 22, 2019

1A

A

B

SATA Re-Driver and cable HDD Conn.

C

D

E

1 2

SATA_PTX_DRX_P4<17>

SATA_PTX_DRX_N4<17>

SATA_PRX_DTX_N4<17> SATA_PRX_DTX_P4<17>

1 1

SATA_PTX_DRX_P4 SATA_PTX_DRX_N4

SATA_PRX_DTX_N4 SATA_PRX_DTX_P4

+3VS

2 2

1 2

RO6 4.7K_0402_5%@

1 2

RO8 4.7K_0402_5%@

1 2

RO10 4.7K_0402_5%@

1 2

RO11 4.7K_0402_5%@

1 2

RO12 4.7K_0402_5%@

1 2

RO13 4.7K_0402_5%@

1 2

RO14 4.7K_0402_5%@

1 2

RO15 4.7K_0402_5%@

1 2

RO16 4.7K_0402_5%@

1 2

RO17 4.7K_0402_5%@

1 2

RO18 4.7K_0402_5%SATARD@

1 2

RO19 4.7K_0402_5%SATARD@

1 2

RO20 4.7K_0402_5%SATARD@

RO21 0_0201_5%SATANRD@ RO22 0_0201_5%SATANRD@

RO23 0_0201_5%SATANRD@ RO24 0_0201_5%SATANRD@

A_DE

B_DE

B_EQ1

A_EQ1

A_EQ2

B_EQ2

DEW

A_DE

B_DE

B_EQ1

A_EQ1

A_EQ2

B_EQ2

1 2

1 2 1 2

CO4 0.01U_0201_6.3V7KSATARD@ CO5 0.01U_0201_6.3V7KSATARD@

CO8 0.01U_0201_6.3V7KSATARD@ CO9 0.01U_0201_6.3V7KSATARD@

SATA_PTX_C_DRX_P4_NR D SATA_PTX_C_DRX_N4_NR D

SATA_PRX_C_DTX_N4_NR D SATA_PRX_C_DTX_P4_NR D

12 12

0.01U_0201_6.3V7K

SATA_PTX_C_RD_DRX_P 4 SATA_PTX_C_RD_DRX_N 4

SATA_PRX_C_RD_DTX_N 4 SATA_PRX_C_RD_DTX_P 4

RO7

+3VS

CO1

SATARD@

12

1

A_INP

2

A_INN

3

GND1

4

B_OUTN

5

B_OUTP

21

GND2

SATARD@

12

4.99K_0402_1%

1 2

RO9

@

4.7K_0402_5%

USE 8527 re-driver SA

00007JU1 0

A_EQ2

B_EQ1

20

VDD2

B_EQ119A_EQ218A_EQ1

REXT6EN7B_DE8A_DE9VDD1

B_DE

A_EQ1

DEW

UO1

16

17

PS8527CTQFN20GTR2A_TQFN20_4X4

SATARD@

DEW

A_OUTP A_OUTN

B_EQ2

B_INN B_INP

SATA_PTX_RD_DRX_P4

15

SATA_PTX_RD_DRX_N4

14

B_EQ2

13

SATA_PRX_RD_DTX_N4

12

SATA_PRX_RD_DTX_P4

11

FFC Type

10

0.1U_0201_10V6K

+3VS

1

SATARD@

A_DE

CO10

2

SATA_PRX_RD_DTX_P4 SATA_PRX_RD_DTX_N4

SATA_PTX_RD_DRX_N4 SATA_PTX_RD_DRX_P4

SATA_PRX_C_DTX_P4_NR D SATA_PRX_C_DTX_N4_NR D

SATA_PTX_C_DRX_N4_NR D SATA_PTX_C_DRX_P4_NR D

+3VS +5VS_HDD

+5VS +5VS_HDD

1 2

CO7 0.01U_0201_6.3V7KSATARD@

1 2

CO6 0.01U_0201_6.3V7KSATARD@

1 2

CO3 0.01U_0201_6.3V7KSATARD@

1 2

CO2 0.01U_0201_6.3V7KSATARD@

12

CO14 0.01U_ 0201_6.3V7KSATANRD@

12

CO15 0.01U_ 0201_6.3V7KSATANRD@

12

CO16 0.01U_ 0201_6.3V7KSATANRD@

12

CO17 0.01U_ 0201_6.3V7KSATANRD@

1 2

RO4 0_0805_5%@

RO25 0_0201_5%

1 2

G_INT2_R

SATA_PRX_C_DTX_P4 SATA_PRX_C_DTX_N4

SATA_PTX_C_DRX_N4 SATA_PTX_C_DRX_P4

JHDD1

14

GND

13

GND

12

11

10

9

8

7

6

5

4

3

2

1

ACES_51625-01201-001

CONN@

SP010028W00

100mils

CO12

1

CO11

0.1U_0201_10V6K

3 3

2

@

10U_0402_6.3V6M

1

12

CO13

0.1U_0201_10V6K

2

@

4 4

Security Cl assification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2017/10/30 2018/10/30

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document N umber Re v

Custom

Date: Sheet o f

D

Date: Sheet o f

Compal Electronics, Inc.

HDD/ Re-Driver/ G-sensor

EH5VF M/B LA-H501P

E

1A

67 101Friday, February 22, 2019

1A

5

D D

PCIE_PRX_DTX_N9

1 2

PCIE_PRX_DTX_P9

PCIE_PTX_C_DRX_N9 PCIE_PTX_C_DRX_P9

PCIE_PRX_DTX_N10 PCIE_PRX_DTX_P10

PCIE_PTX_C_DRX_N10 PCIE_PTX_C_DRX_P10

PCIE_PRX_DTX_N11 PCIE_PRX_DTX_P11

PCIE_PTX_C_DRX_N11 PCIE_PTX_C_DRX_P11

PCIE_PRX_DTX_P12 PCIE_PRX_DTX_N12

PCIE_PTX_C_DRX_N12 PCIE_PTX_C_DRX_P12

SSD1_DET#

PCIE_PRX_DTX_N9<17> PCIE_PRX_DTX_P9<17>

PCIE_PTX_DRX_N9<17> PCIE_PTX_DRX_P9<17>

PCIE_PRX_DTX_N10<17> PCIE_PRX_DTX_P10<17>

PCIE_PTX_DRX_N10<17>

PCIE_PTX_DRX_P10<17>

PCIE_PRX_DTX_N11<17> PCIE_PRX_DTX_P11<17>

PCIE_PTX_DRX_N11<17>

PCIE_PTX_DRX_P11<17>

PCIE_PRX_DTX_P12<17> PCIE_PRX_DTX_N12<17>

PCIE_PTX_DRX_N12<17> PCIE_PTX_DRX_P12<17>

CLK_PCIE_NGFF1#<15> CLK_PCIE_NGFF1<15>

C C

SATA_GP1<17>

1 2

CM6 0.22U_0402_16V7K

1 2

CM4 0.22U_0402_16V7K

1 2

CM5 0.22U_0402_16V7K

1 2

CM7 0.22U_0402_16V7K

1 2

CM8 0.22U_0402_16V7K

1 2

CM9 0.22U_0402_16V7K

1 2

CM10 0.22U_0402_16V7K

1 2

CM11 0.22U_0402_16V7K

Pull high at PCH side

RM10 0_020 1_5%@

SSD_DET # SATA Device 0 PCIE Device 1

4

M.2 SSD

JSSD1

1

GND

3

GND

5

PERn3

7

PERp3

9

GND

11

PETn3

13

PETp3

15

GND

17

PERn2

19

PERp2

21

GND

23

PETn2

25

PETp2

27

GND

29

PERn1

31

PERp1

33

GND

35

PETn1

37

PETp1

39

GND

41

PERn0/SATA-B+

43

PERp0/SATA-B-

45

GND

47

PETn0/SATA-A-

49

PETp0/SATA-A+

51

GND

53

REFCLKN

55

REFCLKP

57

GND

67

NC

69

PEDET(NC-PCIE/GND-SATA)

71

GND

73

GND

75

GND

LOTES_APCI0079-P005A

CONN@

3P3VAUX 3P3VAUX

DAS/DSS#

3P3VAUX 3P3VAUX 3P3VAUX 3P3VAUX

DEVSLP

PERST#

CLKREQ#

PEWake#

SUSCLK(32kHz)

3P3VAUX 3P3VAUX 3P3VAUX

GND1 GND2

NC NC

NC NC NC NC NC NC NC NC NC

NC NC NC NC NC

NC NC

+3VS_SSD1

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58

68 70 72 74

76 77

3

+3VS_SSD1

10U_0402_6.3V6M

1

CM2

CM1

2

PLT_RST_BUF#

Place close to JSSD pin 50

SD

request to reserve.

E

SSD1_CLKREQ#_R

SUSCLK_SSD1

0.1U_0201_10V6K

2

1

CM16 100P_0402_50V8J

1 2

RM7 0_0201_5%@

1 2

RM8 0_0201_5%@

SUSP#<58,78,83,85,87,88>

1

+

CM3 150U_D2_6.3VY_R15M

SGA00003700

2

XESD@

12

1 2

RM53 0_0201_5%@

SSD_DEVSLP1 <17>

PLT_RST_BUF# <16,51,52> SSD1_CLKREQ# <15>

SUSCLK <18,52,68>

2

+3VALW

UM2

1

VIN1

2

1U_0201_6.3V6M

CM34

2

1

VIN1

3

ON1

4

VBIAS

5

ON2

6

VIN2

7

VIN2

EM5209VF_DFN14_2X3

+3V_NGFF_GATE

0.1U_0201_10V6K CM32

1

+5VALW

@

2

+3VALW

1U_0201_6.3V6M

CM33

2

1

Place CM33 close UM2 pin 1&2 Place CM34 close UM2 pin 6&7

14

VOUT1

13

VOUT1

VOUT2 VOUT2

GPAD

1 2

12

CT1

CM37 1000P_0402_50V7K

11

GND

10

1 2

CT2

CM38 1000P_0402_50V7K

9 8

15

1

+3VS_SSD_1

1 2

@

RM54 0_0805_5%

+3VS_SSD_2

1 2

@

RM55 0_0805_5%

+3VS_SSD_1 +3VS_SSD_2

2

CM35

0.1U_0201_10V6K

1

+3VS_SSD1

+3VS_SSD2

2

CM36

0.1U_0201_10V6K

1

SP07001EZ00

+3VS_SSD2

M.2 SSD

JSSD2

1

GND

3

GND

5 PCIE_PRX_DTX_N24<14> PCIE_PRX_DTX_P24<14>

PCIE_PTX_DRX_N24<14>

PCIE_PTX_DRX_P24<14>

B B

A A

PCIE_PRX_DTX_N23<14> PCIE_PRX_DTX_P23<14>

PCIE_PTX_DRX_N23<14>

PCIE_PTX_DRX_P23<14>

PCIE_PRX_DTX_N22<14> PCIE_PRX_DTX_P22<14>

PCIE_PTX_DRX_N22<14>

PCIE_PTX_DRX_P22<14>

PCIE_PRX_DTX_P21<14> PCIE_PRX_DTX_N21<14>

PCIE_PTX_DRX_N21<14>

PCIE_PTX_DRX_P21<14>

CLK_PCIE_NGFF2#<15> CLK_PCIE_NGFF2<15>

1 2

CM23 0.22U_0402_16V 7K

1 2

CM31 0.22U_0402_16V 7K

1 2

CM29 0.22U_0402_16V 7K

1 2

CM22 0.22U_0402_16V 7K

1 2

CM30 0.22U_0402_16V 7K

1 2

CM24 0.22U_0402_16V 7K

1 2

CM27 0.22U_0402_16V 7K

1 2

CM25 0.22U_0402_16V 7K

PCIE_PTX_C_DRX_N24 PCIE_PTX_C_DRX_P24

PCIE_PTX_C_DRX_N23 PCIE_PTX_C_DRX_P23

PCIE_PTX_C_DRX_N22 PCIE_PTX_C_DRX_P22

PCIE_PTX_C_DRX_N21 PCIE_PTX_C_DRX_P21

T210 @

SSD2_DET#

PERn3

7

PERp3

9

GND

11

PETn3

13

PETp3

15

GND

17

PERn2

19

PERp2

21

GND

23

PETn2

25

PETp2

27

GND

29

PERn1

31

PERp1

33

GND

35

PETn1

37

PETp1

39

GND

41

PERn0/SATA-B+

43

PERp0/SATA-B-

45

GND

47

PETn0/SATA-A-

49

PETp0/SATA-A+

51

GND

53

REFCLKN

55

REFCLKP

57

GND

67

NC

69

PEDET(NC-PCIE/GND-SATA)

71

GND

73

GND

75

GND

LOTES_APCI0079-P005A

CONN@

SUSCLK(32kHz)

3P3VAUX 3P3VAUX

DAS/DSS#

3P3VAUX 3P3VAUX 3P3VAUX 3P3VAUX

DEVSLP

PERST#

CLKREQ#

PEWake#

3P3VAUX 3P3VAUX 3P3VAUX

GND1 GND2

2 4 6

NC

8

NC

10 12 14 16 18 20

NC

22

NC

24

NC

26

NC

28

NC

30

NC

32

NC

34

NC

36

NC

38 40

NC

42

NC

44

NC

46

NC

48

NC

NC NC

50 52 54 56 58

68 70 72 74

76 77

PLT_RST_BUF#

SSD2_CLKREQ#_R

SUSCLK_SSD2

+3VS_SSD2

0.1U_0201_10V6K

10U_0402_6.3V6M

2

1

CM26

CM28

PLT_RST_BUF#

1

2

CM21 100P_0402_50V8J

XESD@

Place close to JSSD pin 50

ESD request to reserve.

1 2

RM48 0_0201_5%@

1 2

RM52 0_0201_5%@

1

+

CM20 150U_D2_6.3VY_R15M

SGA00003700

2

12

SUSCLK <18,52,68>

SSD2_CLKREQ# <15>

SP07001EZ00

Security Cl assification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2017/10/30 2018/10/30

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document N umber Re v

Custom

Date: Sheet o f

2

Date: Sheet o f

Compal Electronics, Inc.

SATA/PCIE-SSD

EH5VF M/B LA-H501P

1

1A

68 101Friday, February 22, 2019

1A

5

D D

C C

4

3

2

1

Reserve Page

B B

A A

Security Cl assification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2017/11/23 2017/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document N umber Re v

Date: Sheet o f

2

Date: Sheet o f

Compal Electronics, Inc.

N18E-GDDR6_D

EH5VF M/B LA-H501P

1

1A

69 101Friday, February 22, 2019

1A

5

D D

C C

4

3

2

1

Reserve Page

B B

A A

Security Cl assification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2017/11/23 2017/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document N umber Re v

Date: Sheet o f

2

Date: Sheet o f

Compal Electronics, Inc.

N18E-GDDR6_D

EH5VF M/B LA-H501P

1

1A

70 101Friday, February 22, 2019

1A

A

B

C

D

E

USB3.0

DS1

USB3_PTX_L_DRX_P1

USB3_PTX_C_DRX_P1

USB3_PTX_DRX_P1<17>

1 1

2 2

3 3

USB3_PTX_DRX_N1<17>

USB3_PRX_DTX_P1<17>

USB3_PRX_DTX_N1<17>

USB Host Charger

0

1

+5VALW

1

CHG_EN

1 2

RS14 10K_0402_5%

@

1 2

RS15 10K_0402_5%

0911 Rerserve PU, vendor suggest to EC control if

future need support SDP2

USB Host Charger Truth Table

CTL1

CTL2 CTL3 ILIM_SEL

0 1 10

0

0 1 1 1

1 111

1 2

CS2 .1U_0402_16V7K

USB3_PTX_C_DRX_N1

1 2

CS3 .1U_0402_16V7K

CHG_CTL2

CHG_ILMSEL

MODE

SDP1-OFF

SDP1

101

DCP Aut o

CDP

RS90 0_0402_5%@

RS91 0_0402_5%@

CHR_USB20_P1

CHR_USB20_N1

Current Limit Setti ng

ILIM_H

RS86 0_0402_5%@

RS89 0_0402_5%@

1 2

LS3

EMI@

2

3

DLM0NSN900HY2D_4P

SM070005U00

Note

Port power off

Data Lines Connected

Data Lines Disconnected

Data Lines Connected

USB3_PTX_L_DRX_P1

USB3_PTX_L_DRX_N1

USB3_PRX_L_DTX_P1

USB3_PRX_L_DTX_N1

CHR_USB20_P1_R

1

CHR_USB20_N1_R

4

USB_OC1#<14>

0.1U_0201_10V6K

+5VALW

CS8

@

USB3_PTX_L_DRX_N1

USB3_PRX_L_DTX_P1

USB3_PRX_L_DTX_N1

+USB3_VCCA

CHR_USB20_P1_R

0904 vendor recommend

1

2

22U_0603_6.3V6M

@

RS11

0_0201_5%

@

0.1U_0201_10V6K

1

CS9

2

12

CHG_ILMSEL<58>

1

2

USB20_N1<14> USB20_P1<14>

CHG_EN<58>

CHG_CTL1<58>

CHG_CTL3<58>

ESD@

1

2

4

5

3

TVWDF1004AD0_DFN 9

SC300003Z00

DS2

6

I/O4

5

VDD

4

I/O3

AZC099-04S.R7G_SOT23-6

SC300001G00

CS7

CHG_CTL2

USB3_PTX_L_DRX_P1

9

USB3_PTX_L_DRX_N1

8

USB3_PRX_L_DTX_P1

7

USB3_PRX_L_DTX_N1

6

ESD@

CHR_USB20_N1_R

3

I/O2

2

GND

1

I/O1

US12

1

VIN

2

DM_OUT

3

DP_OUT

13

FAULT#

4

ILIM_SEL

5

EN

6

CTL1

7

CTL2

8

CTL3

SLGC55544CVTR_TQFN16_3X3

VOUT

DP_IN

DM_IN

ILIM_L

ILIM_HI

GND

Thermal Pad

150U_D2_6.3VY_R15M

SGA00003700

12

10 11

15 16

9

NC

14 17

CS5

USB3_PRX_L_DTX_N1 USB3_PRX_L_DTX_P1

USB3_PTX_L_DRX_N1 USB3_PTX_L_DRX_P1

CHR_USB20_P1 CHR_USB20_N1

12

22.1K_0402_1% RS12

+USB3_VCCA

W=100mi ls

2

1

+

CS6

EMI@

0.1U_0201_10V6K

1

2

+USB3_VCCA

CHR_USB20_N1_R CHR_USB20_P1_R

USB3.0 Conn.

JUSB1

1

VBUS

2

D-

3

D+

4

GND

5

StdA-SSRX-

6

StdA-SSRX+

7

GND-DRAIN

8

StdA-SSTX-

9

StdA-SSTX+

ACON_TARAC-9V1391

CONN@

DC23300AG00

GND GND GND GND

10 11 12 13

0831 Reserve ILIM_L R as vendor recommend

12

39K_0402_1%

RS13

ILM R vaule

@

s(mA)=5025 0/R(Ko hm)

Io ILIM_Hi=22 73mA ILIM_L=128 8mA(rese rve)

4 4

Security Cl assification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2017/10/30 2018/10/30

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document N umber Re v

Custom

Date: Sheet o f

D

Date: Sheet o f

Compal Electronics, Inc.

USB3.0 Conn/USB Charger

EH5VF M/B LA-H501P

E

1A

71 101Friday, February 22, 2019

1A

USB3.0

5

4

3

2

1

D D

USB3_PTX_DRX_P3<17>

USB3_PTX_DRX_N3<17>

USB3_PRX_DTX_P3<17>

USB3_PRX_DTX_N3<17>

USB3_PTX_C_DRX_P3

1 2

CS109 .1U_0402_16V7 K

USB3_PTX_C_DRX_N3

1 2

CS108 .1U_0402_16V7 K

USB3_PRX_DTX_P3

USB3_PRX_DTX_N3

RS124 0_0402_5%@

RS123 0_0402_5%@

1 2

RS126 0_0402_5%@

1 2

RS125 0_0402_5%@

1 2

USB3_PTX_L_DRX_P3

USB3_PTX_L_DRX_N3

USB3_PRX_L_DTX_P3

USB3_PRX_L_DTX_N3

USB3_PTX_L_DRX_P3

USB3_PTX_L_DRX_N3

USB3_PRX_L_DTX_P3

USB3_PRX_L_DTX_N3

For ESD request

DS20

ESD@

1

2

4

5

3

TVWDF1004AD0_DFN 9

C3

00003 Z00

S

USB3_PTX_L_DRX_P3

9

USB3_PTX_L_DRX_N3

8

USB3_PRX_L_DTX_P3

7

USB3_PRX_L_DTX_N3

6

USB_EN<42,58,73>

+5VALW

CS107

EMI@

0.1U_0201_10V6K

1 2

US13

5

IN

4

EN

SY6288C20AAC_SOT23-5

OUT

GND

OC

+USB3_VCCB

1

2

3

+USB3_VCCB

W=60mil s

W=100mi ls

2

1

+

CS110

CS111

150U_D2_6.3VY_R15M

DS21

U2DN3_L

LS13

C C

USB20_N3<14>

USB20_P3<14>

EMI@

3

2

DLM0NSN900HY2D_4P

SM070 005U00

U2DN3_L

4

U2DP3_L

1

+USB3_VCCB

ESD@

6

I/O4

I/O2

5

VDD

GND

4

I/O3

AZC099-04S.R7G_SOT23-6

SC300001G00

I/O1

3

2

U2DP3_L

1

SGA00003700

2

USB3_PRX_L_DTX_N3 USB3_PRX_L_DTX_P3

USB3_PTX_L_DRX_N3 USB3_PTX_L_DRX_P3

EMI@

0.1U_0201_10V6K

1

U2DN3_L U2DP3_L

USB3.0 Conn.

JUSB2

1

VBUS

2

D-

3

D+

4

GND

5

StdA-SSRX-

6

StdA-SSRX+

7

GND-DRAIN

8

StdA-SSTX-

9

StdA-SSTX+

ACON_TARAC-9V1391

CONN@

DC23300AG00

GND GND GND GND

10 11 12 13

B B

A A

Security Cl assification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2017/11/23 2017/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document N umber Re v

Date: Sheet o f

2

Date: Sheet o f

Compal Electronics, Inc.

N18E-GDDR6_D

EH5VF M/B LA-H501P

1

1A

72 101Friday, February 22, 2019

1A

A

B

C

D

E

IO/B CONN

JIO2

26

GND2

25

HPOUT_L _1<56> HPOUT_R _1<56>

1 1

DLM0NSN 900HY2D_4P

USB20_P 4

USB20_N 4

1

4

LS12

EMI@

USB20_P 4<14>

USB20_N 4<14>

USB20_L _P4

2

USB20_L _N4

3

SLEEVE<5 6> RING2<56> HP_PLUG #<5 6>

GNDA

SPKR+< 56>

SPKR-<56>

BATT_AM B_LED#<58>

BATT_BL UE_LED#<58>

PWR_ SUSP_LED#<58>

PWR_ LED#<58>

+5VALW

HPOUT_L _1 HPOUT_R _1

SLEEVE RING2

HP_PLUG #

BATT_AMB_LED# BATT_BLUE_LED# PWR_SUSP_L ED# PWR_ LED#

SM070005U00

USB_EN<42,58,72 >

2 2

USB_EN

USB20_L _P4 USB20_L _N4

GND1

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

CVILU_CF3 5242D0RD-NH

CONN@

3 3

4 4

Security Classification

2017/10/ 30 2018/10 /30

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

2017/10/ 30 2018/10 /30

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Re v

Custom

Date : Sheet o f

D

Date : Sheet o f

Compal Electronics, Inc.

IO/B

EH5VF M/B LA-H501P

E

1A

73 1 01Friday, February 22, 201 9

5

D D

C C

4

3

2

1

Reserve Page

B B

A A

Security Cl assification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2017/11/23 2017/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document N umber Re v

Date: Sheet o f

2

Date: Sheet o f

Compal Electronics, Inc.

N18E-GDDR6_D

EH5VF M/B LA-H501P

1

1A

74 101Friday, February 22, 2019

1A

5

D D

C C

4

3

2

1

Reserve Page

B B

A A

Security Cl assification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2017/11/23 2017/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document N umber Re v

Date: Sheet o f

2

Date: Sheet o f

Compal Electronics, Inc.

N18E-GDDR6_D

EH5VF M/B LA-H501P

1

1A

75 101Friday, February 22, 2019

1A

5

D D

C C

4

3

2

1

Reserve Page

B B

A A

Security Cl assification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2017/11/23 2017/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document N umber Re v

Date: Sheet o f

2

Date: Sheet o f

Compal Electronics, Inc.

N18E-GDDR6_D

EH5VF M/B LA-H501P

1

1A

76 101Friday, February 22, 2019

1A

1000P_0402 _50V7K

FAN_SPEED1<5 8>

FAN_SPEED2<5 8>

+5VS

CF6

@

+3VS

1

2

@

12

RF3 10K_0402_5 %

1

CF7 1000P_0402 _50V7K

XEMI@

2

12

RF5 10K_0402_5 %

1

CF10 1000P_0402 _50V7K

XEMI@

2

RF4 0_0603_5%

RF7 0_0603_5%

CF5 10U_0402_ 6.3V6M

FAN_PWM1<58>

FAN_PWM2<58>

1 2

@

+VCC_FAN2

1

4.7U_0402_ 6.3V6M

2

+VCC_FAN1

FAN_PWM1

1

2

FAN_PWM2

+VCC_FAN1

1 2

@

40mil

CF13

CF12

4.7U_0402_ 6.3V6M

+VCC_FAN2

FAN Conn

JFAN1

1

2

3

4

5

G1

6

G2

ACES_50278-00 401-001

CONN@

SP02000RR00

JFAN2

1

2

3

4

5

G1

6

G2

ACES_50278-00 401-001

CONN@

SP02000RR00

Screw Hole

H2

@

H3

@

H_3P0

@

H_4P0

@

H_3P3

@

H_3P8

@

H_3P0

1

@

H7

@

H6

H_4P0

1

H10

H11

@

H_3P3

1

H15

@

H14

@

H_3P8

1

H19

H4

H5

@

H_3P0

1

H8

H9

@

H_4P0

1

H12

H13

@

H_3P3

1

H16

1

@

H_2P5N

H18

@

H17

H_3P2

1

FD1

FIDUCIAL_C40M80

FD3

FIDUCIAL_C40M80

@

H20

@

H_3P2

H_3P0X2P5N

1

@

1

FD2

@

1

FIDUCIAL_C40M80

FD4

@

1

FIDUCIAL_C40M80

1

GASKET1

@

GS-002C-3025 20

1

GASKET2

@

GS-002C-3025 20

1

GASKET3

@

GS-002C-3025 20

1

Reset Circuit

I

_GATE PH to +RTCVCC at PWR

B side

BI_GATE<82>

change PN to SN10000CV00

BI_GATE

Reset Button

BI_GATE BI_GATE

1 2

3 4

SN10000CV00

@

SW3

SKRPABE010_4P

Q1B

5

G

+3VLP

1 2

1

34

D

2

2N7002KDW _SOT363-6

S

R25 10K_0402_5 %

BI_GATE#

C40

0.1U_0201_ 10V6K

Q1A

2

G

1 2

@

R23 0_ 0402_5%

1 2

@

R24 0_ 0402_5%

61

D

2N7002KDW _SOT363-6

S

MAINPWON <58,82,84>

EC_RST# <58>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2017/10/30 2018/10/30

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Re v

Custom

Date : Sheet o f

Compal Electronics, Inc.

FAN & Screw Hole

EH5VF M/B LA-H501P

77 1 01Friday, February 22, 2019

1A

A

B

C

D

E

System DC inferface

@

1 2

CQ2 0 .1U_0201_10V6K

RQ1 0_0402_5 %@

RQ2 0_0402_5 %@

CQ4 0.1 U_0201_10V6K

SUSP

SUSP#<58 ,68,83,85,87,88>

2N7002KDW _SOT363-6

R32

10K_0402_5 %

1 2

12

@

1 2

2

1

Place CQ7 close UQ1 pin 1&2 Place CQ8 close UQ1 pin 6&7

R27

@

100K_0402_ 5%

Q7A

2

G

@

12

@

SUSP#

1 1

2 2

+5VALW +5VS

5VS_ON

+5VALW

3VS_ON

+3VALW

+0.6VS_VTT+5VALW

R28

@

100K_0402_ 5%

1 2

dischar ge tra

34

D

Q7B

S

2N7002KDW _SOT363-6

2

1

ce 20 mils

G

CQ7 1U_0201_6 .3V6M

1 2

61

D

S

CQ8 1U_0201_6 .3V6M

5

SUSP

@

UQ1

1

VOUT1

VIN1

2

VOUT1

VIN1

3

ON1

4

VBIAS

5

ON2

6

VIN2

VOUT2

7

VIN2

VOUT2

EM5209VF_DFN14 _2X3

SYSON<58 ,85,87>

14 13

12

1 2

CT1

CQ1 1000P_04 02_50V7K

11

GND

10

1 2

CT2

CQ3 10 00P_0402_50V7K

9 8

15

GPAD

SYSON

2N7002KDW _SOT363-6

+5VS_OUT

+3VS_OUT

+3VS_OUT +5VS_OUT+3VALW +5VALW

100K_0402_ 5%

SYSON#

Q8B

5

G

@

JUMP_43X118

@

JUMP_43X118

2

CQ5

0.1U_0201_ 10V6K

1

R30

@

1 2

34

D

S

JPQ2

2

112

JPQ1

2

112

+1.2V_VDDQ+5 VALW

R29 100K_0402_ 5%

@

1 2

dischar ge trace 20 mils

61

D

Q8A

S

2N7002KDW _SOT363-6

@

+3VS

2

CQ6

0.1U_0201_ 10V6K

1

2

SYSON#

G

For Power ON/Off Sequence

PM_SLP_S3

+3VALW

12

R37

100K_0402_ 5%

Q11A

61

PM_SLP_S3#<18,58>

PM_SLP_S4#<18,58>

2N7002KDW _SOT363-6

2

G

R38

100K_0402_ 5%

Q13A

2

G

D

S

+3VALW

S

12

61

D

PM_SLP_S4

P/N: SB00000EO00 footprint use SB00000ZU00

G

2

Q10A 2N7002KDW _SOT363-6

S

D

G

5

Q10B 2N7002KDW _SOT363-6

S

D

G

5

Q11B 2N7002KDW _SOT363-6

S

D

G

2

Q12A 2N7002KDW _SOT363-6

S

D

G

5

Q12B 2N7002KDW _SOT363-6

S

D

G

5

Q13B 2N7002KDW _SOT363-6

S

D

61

EC_VCCST_PG_ R <10,58>

MOW14, For tCPU28 200us(max) SLP_S3# to VCCST_PWRGD deassertion

34

VR_ON <58,88,89>

MOW14, For tPLT17 200us(max) SLP_S3# to IMVP VR_ON deassertion

34

SUSP#

MOW14, For tPLT18 200us(max) SL

@

61

@

34

P_S3# to VCCIO VR disable

SYS_PWROK <18,58>

PCH_PWR OK < 18,58>

SYSON

MOW14, For tPLT15 200us(max) SLP_S4# to VDDQ ramp down

+1.05VALW TO +1.05V_VCCST /+1.8VALW TO +1.8VS +1.05VALW TO +1.05VS_VCCSTG

+1.05VALW

2

CQ22

0.1U_0201_ 10V6K

1

+1.05V_VCCST

+1.8VS

2

CQ12

1U_0201_6 .3V6M

Issued Date

12

SUSP#

RQ3 0_0402_5 %@

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

1

+5VALW

EN_1.0V_VCCSTG

1

@

CQ13

0.1U_0201_ 10V6K

2

2017/10/30 2018/10/30

UC4

1

VIN1

2

VIN2

7

VIN thermal

3

VBIAS

4

ON

AOZ1334DI-01_DFN8 -7_3X3

+1.0VS_VCCSTG: 60mA R ON = 4.4m ohm VDROP= 11mV Delay time: 9.3us

Compal Secret Data

Deciphered Date

VOUT

D

GND

6

5

+1.05VS_VCCSTG

2

CQ10

0.1U_0201_ 10V6K

1

Compal Electronics, Inc.

Title

Size Document Number Re v

Custom

Date : Sheet o f

Compal Electronics, Inc.

DC Interface

EH5VF M/B LA-H501P

1A

78 1 01Friday, February 22, 2019

E

78 1 01Friday, February 22, 2019

1A

@

1 2

3 3

4 4

CQ15 0.1U_02 01_10V6K

SYSON

RQ4 0_0402_5 %@

SUSP#

RQ8 0_0402_5 %@

CQ20 0.1U_02 01_10V6K

+1.05VALW

1 2

@

1 2

2

CQ11 1U_0201_6 .3V6M

1

Place CQ11 close UQ2 pin 1&2

ace CQ24 close UQ2 pin 6&7

Pl

EN_1.0V_VCCSTU

+5VALW

EN_1.8VS

+1.8VALW

2

CQ24 1U_0201_6 .3V6M

1

A

UQ2

1

VIN1

2

VIN1

3

ON1

4

VBIAS

5

ON2

6

VIN2

7

VIN2

EM5209VF_DFN14 _2X3

14

VOUT1

13

VOUT1

VOUT2 VOUT2

1 2

12

CT1

CQ14 1 000P_0402_50V7K

11

GND

10

1 2

CT2

CQ16 1 000P_0402_50V7K

9 8

15

GPAD

+1.05V_VCCST_OU T

+1.8VS_OUT

+1.05V_VCCST_OU T+1.05VALW

2

CQ9

0.1U_0201_ 10V6K

1

B

1 2

RQ5 0_0603_5 %@

1 2

RQ9 0_0603_5 %@

+1.8VS_OUT

5

D D

C C

4

3

2

1

Reserve Page

B B

A A

Security Cl assification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2017/11/23 2017/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document N umber Re v

Date: Sheet o f

2

Date: Sheet o f

Compal Electronics, Inc.

N18E-GDDR6_D

EH5VF M/B LA-H501P

1

1A

79 101Friday, February 22, 2019

1A

5

D D

C C

4

3

2

1

Reserve Page

B B

A A

Security Cl assification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2017/11/23 2017/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document N umber Re v

Date: Sheet o f

2

Date: Sheet o f

Compal Electronics, Inc.

N18E-GDDR6_D

EH5VF M/B LA-H501P

1

1A

80 101Friday, February 22, 2019

1A

A

1 1

2 2

@

ACES_50299-00601-001

1 2 3

G7 G8

PJP101

4 5 6

7 8

1 2 3 4 5 6

12

B

PR103

4.7_1206_5%

PC101

EMI@

0.1U_0603_25V7K

C

PL101

EMI@

FBMA-L11-201209-8 00LMA50T

1 2

PL102

EMI@

FBMA-L11-201209-8 00LMA50T

PC102

12

EMI@

100P_0402_50V8J

1 2

PL103

EMI@

FBMA-L11-201209-8 00LMA50T

1 2

Bead SM01000U600

+19V_VIN+19V_ADPIN

PC104

12

EMI@

12

PR102

4.7_1206_5%

1000P_0402_50V7K

12

PC105

EMI@

0.1U_0603_25V7K

D

E

3 3

+3VLP

4 4

A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECT RONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECT RONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECT RONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PR101

@0@

0_0402_5%

1 2

B

+CHGRTC

Compal Secret Data

2016/11/03 2017/06/14

Compal Secret Data

Deciphered Date

C

Compal Electronics, Inc.

Title

DCIN

Size

Document Number Re v

Document Number Re

Custom

Date : She et o f

D

DH53F M/B LA-F991P

v

1A

81 100Friday, February 22, 2019

E

A

B

C

D

E

+3VLP

1 1

PR207 100_0402_1%

1 2

PR205 100_0402_1%

1 2

Battery Bot Side

PJP201

PIN1 GND PIN2 GND PIN3 SMD PIN4 SMC PIN5 TEMP PIN6 BI PIN7 Batt+ PIN8 Batt+

2 2

@

1

2

3

4

5

6

7

8

9

GND

10

GND

CVILU_CI9908M2HR0-NH

EC_SMB_DA1-1 EC_SMB_CK1-1 BATT_TS BATT_B/I

PR202

200K_0402_1%

1 2

PR203 1K_0402_ 1%

+3VLP

BATT_TEMP <58,83>

+RTCVCC

12

PR212 100K_0402_5%

BI_GATE<77>

+12.6V_BATT+

PL201

EMI@

FBMA-L11-201209-800LMA50T

1 2

PL202

EMI@

FBMA-L11-201209-800LMA50T

1 2

12

PC201

EMI@

1000P_0402_50V7K

3 3

12

PC202

0.01U_0402_50V7K

+12.6V_BATT

EMI@

EC_SMB_DA1 <58,83>

EC_SMB_CK1 <58,83>

13

D

2

G

S

12

PR217 0_0402_5%

design reserve

PQ201 LBSS139LT1G 1N SOT-23-3

BI_S

<45,47>

MAINPWON<58,77,84>

PR206

10K_0402_1%

1 2

MAINPWON

12

PR213

100K_0402_1%

@

ADP_I <58,83>

VCIN1_ADP_PROCHOT <58>

12

PC205

0.1U_0603_25V7K

PU201

1

VCC

TMSNS1

2

GND

RHYST1

3

OT1

TMSNS2

4

RHYST2

OT2

G718TM1U_SOT23-8

@

26.7K_0402_1%

@

8

7

6

5

@

14K_0402_1%

(Common Part) SL

200002H 00

@

PR218

PR215

12

PH3 Near VGA.

When PR204=18.7K

For KB9022 OTP

8

9'C, 1V 56'C, 2VVCIN0_P H(V)

PH202(oh m) 8.0524K 26.1 1K

+3VLP_ECA

12

PR204

18.7K_0402_1%

3/27 thermal PH1 92'C ->89'C

@

10K_0402_1%

100K_0402_1%_NCP15WF104F03RC

PH203

@

PR216

RecoveryActive

12

@

PR214

21.5K_0402_1%

(Common Part)

12

SL200002 H00

12

100K_0402_1%_NCP15WF104F03RC

@

PH202

VCIN0_PH <58>

12

PR208 10K_0402_1%

100K_0402_1%_NCP15WF104F0 3RC

T202@

T201@

PH201

12

PC203 must close to EC pin

PC203

@

0.1U_0402_25V6

1 2

PH201 is Common Part SL200002H00

ECAGND <58,66>

T202 T201 must close to PH201

ADP_I =20* I(adapt er)*0.01

dapt er)=adapter (W)*130%/19

4 4

Security Cl assification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

I(a

Compal Secret Data

2016/11/03 2017/06/14

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

BATTERY CONN/OTP

Size Document N umber Re v

Custom

DH53F M/B LA-F991P

Date: Sheet o f

E

82 100Friday, February 22, 2019

1A

5

4

3

2

1

Module model information

ISL95 520_Hy brid_B oost_V 2.mdd

Protection for reverse input

Vgs = 20V Vds = 60V

PQB3

D D

1 2

PRB1

1M_0402_1%

Need check the SOA for inrush

+19V_VIN

L->H

C C

0x3CH <BIT9> PSYS current gain Rs1 = 10mΩ and Rs2 = 5mΩ o r Rs 1 = 10m Ω a nd Rs2 = 10mΩ BIT0 = 1.14uA/W BIT

1 = 0.285uA/W ===== ====== ====== ====== ======= ====== ====== ====== ====== === Rs1 = 20m Ω and Rs2 = 10mΩ o r Rs1 = 20mΩ a nd Rs2 = 20mΩ BIT0 = 2.28uA/W BIT1 = 0.57uA/W

Ipsys = KPSYS x ( VAD P x IAD P + VBA T x IBAT ) R_Psys = 1.2V / Ipsys KPSYS = 1.14uA/W adapter wattage = 45W Battery wattage = 40Wh Ipsys = 1.14 x (45+40) = 96.9uA R_Psys = 1 .2V / 96.9uA = 12.3K-ohm. ===== ====== ====== ====== ======= ====== = adapter wattage = 65W Battery wattage = 40Wh Ipsys = 1.14 x (65+40) = 119.7uA R_Psys = 1.2V / 96.9uA = 10K-ohm.

**Design Notes** For 45W/65W /90W system, 2S/3S/4S battery

B B

Maximum Charging current 3.5A Maximum Battery discharge power 55W #Register Setting

1. 0X3DH bit10 set 0 (default 1) to enable turbo boost function

2. Disable turbo when AC only #Circuit Design

1. ACLIM and CCLIM are devider voltage control.

2. Use 7X7 choke and 3X3 H/L side MOSFET Charge current 3A Power loss : 1.79W (H/S=0.227W,L/S=1.2738W,Choke=0.297W) Power density : 0.61 (23X16) #Protect function

1. ACOVP : VCC voltage > 24V

2. SMBus timeout : 0X3DH bit15 set 0 (default 0) to enable 175s(default).

3. ACOC : OX3CH bit4 set1 release adapter limit function (default:Enable).

4. CHGOCP : based on charge current setting

5. BATOVP : 4.6V/Cell

6. BATLOWV : No.

7. TSHUT : 150C

A A

  

RUM001L02_VMT3

2.04 vin min w/ o 2M =17.41

H->L

2.02 vin min w 2M =17.77

AC_IN<58>

DGPU_AC_DETECT<19,27,58>

@VGA@

PQB6

1

2

3

5

+3VS

@VGA@

PRB35

10K_0402_1%

@VGA@

PQB5B

2N7002KDW_SOT363-6

AC_INH_PROCHOT#

5

G

PRB12

PRB15

12

10K_0402_1%

34

D

S

100K_0402_1%

158K_0402_1%

VDD_CHG

12

@VGA@

PRB36

2

G

H_PROCHOT#<10,58>

12

61

D

S

Id = 250mA

1 2

PRB2

3M_0402_5%

EMP21N03HC_N_DFN56-8-5

5

12

PRB7 499K_0402_1%

12

PRB11

66.5K_0402_1%

ACIN_CHG BST_CHG_R

EC_SMB_DA1<58,82>

EC_SMB_CK1<58,82>

ADP_I<58,82>

0.1U_0402_25V6

Close to EC.

Pull high on HW side

L2N7002WT1G_SC70-3

AC_IN

@VGA@

PQB5A 2N7002KDW_SOT363-6

L2N7002WT1G_SC70-3

13

D

2

G

S

PQB11

1 2 3

4

1 2

PCB1

@

1000P_0402_50V7K

12

PRB8 4.02K_0402_1%

12

PCB8

2200P_0402_50V7K

support Turbo boost : 2200P no support Turbo boost : 0.1u

PRB20 1K_0402_1%

PRB22 1K_0402_1%

Close to EC.

12

PCB18

PCB19

0.1U_0402_25V6

Follow adapter and battery wattage in Vsys current source. Base on CPU Core VR design. The resistor is pop on CPU VR schematic.

VDD=5V

@

PRB32

76.8K_0402_1%

1 2

@

PQB7

13

D

2

G

S

Battery current limimed by CCLIm ~ 3.89A. Ada (PR779 and PQ74 1 are for change ACLIm when AC in)

(Rs1 = 10mΩ a nd Rs2 = 5mΩ o r Rs1 = 20mΩ a nd Rs2 = 10mΩ). CC_LIM = VccLIM / 64 x Rs2 ===== ====== ====== ====== ======= ====== ====== ====== ====== ====== = (Rs1 = 10mΩ a nd Rs2 = 10mΩ o r Rs1 = 20mΩ a nd Rs2 = 20mΩ). CC_LIM = VccLIM / 32 x Rs2 ===== ====== ====== ====== ======= ====== ====== ====== ====== ====== = AC_LIM = Vac_LIM / 32 x Rs1

4

PQB12

+19V_P1

PRB9 4.02K_0402_1%

PRB14 0_0402_5%@0@

1 2

PRB17 0_0402_5%@0@

1 2

PRB18 0_0402_5%@0@

1 2

VDD_CHG

12

PRB29

12

PRB41

AON7380_DFN3X3-8-5

1 2 3

12

PRB30 200K_0402_1%

200K_0402_1%

OCCP setting

12

110K_0402_1%

+19V_P2 +19VB_CHG

5

4

CSIP_CHG_R

12

PRB5

1_0402_5%

12

PCB24

0.033U_0402_25V7K

CMSRC_CHG

ASGATE_CHG

CSIP_CHG

32

PUB1

1

ACIN

2

EC_SMB_DA1_R

EC_SMB_CK1_R

AMON_ISL95520

BMON_ISL95520

PRB39

300K_0402_1%

Hybrid boost power mod e Cell = 4s

ACOK

3

SDA

4

SCL

5

PROCHOT#

6

AMON

7

BMON

8

NC

12

AGND

@0@

PRB23

33

0_0402_5%

CCLIM_CHG

ACLIM_CHG

PROG_CHG

COMP_CHG

12

PCB22

@

PRB37

150K_0402_1%

ICClimit : 7.73A Delta I : 1.44A 1C charge current :6.48A

9

560P_0402_50V7K

pter current limimed by ACLIm ~ 4.33A.

max Power loss 0.22W for 90W;0.12W for 65W system;0.05W for 45W CSR rating: 1W VCSIP-VCSIN spec < 81mV

PRB4

0.005_1206_1%

1

4

3

2

CSIN_CHG_R

12

PRB6

2_0402_5%

PCB7

1 2

0.1U_0402_25V6

12

PCB9 0.22U_0603_25V7K

CSIN_CHG

OPCP_CHG

OPCN_CHG

28

29

31

27

30

CSIP

CSIN

QPCP

OPCN

CMSRC

ASGATE

ISL88739AHRZ-T_QFN32_4X4

CCLIM11COMP

PROG

FSET12BATGONE13CSON14CSOP

10

12

PRB27

FSET_CHG

10K_0402_1%

12

@0@

PRB34

PRB33

0_0402_5%

100_0402_1%

12

PCB23

BATGO NE(BAT T_TEMP ) logic high: above 2.4V logic low: under 0.8V

0.033U_0402_16V7K

PLB11

EMI@

FBMA-L11-201209-800LMA50T

1 2

Isat: 10A DCR: 14mohm

12

PCB25

@

BGATE_CHG

VBAT_CHG

25

26

VBAT

BGATE

BOOT

UGATE

PHASE

LGATE

VDDP

VDD

DCIN

NTC

ACLIM

15

16

0.1U_0402_25V6

CSOP_CHG

24

23

22

21

20

19

18

17

100_0402_1%

BST_CHG

UG_CHG

LX_CHG

LG_CHG

VDDP_CHG

VDD_CHG

PRB24

12

100K_0402_1%

PCB20

PRB10

1 2

PRB13

0_0603_5%

1 2

PRB25 10_1206_5%

1 2

VF = 0.38V

1 2

1U_0603_25V6

12

PR333=0 ohm, Fs=500KHZ ~ +/- 15%

CSON_CHG

BATT_TEMP <58,82>

3

+19VB

EMI@

12

PCB3

PCB2

PCB4

0.1U_0402_25V6

10U_0603_25V6M

+12.6V_BATT

PDB2

@

30MA_30V_0.5UA_0.4V_SOD323-2

PRB21 4.7_0402_5%

PCB15 1U_0402_6.3V6K

21

PCB11

0.22U_0603_25V7K

BST_CHG_R

1 2

PDB1

3

1

2

S SCH DIO BAS40CW SOT-323

1 2

PRB31 2_0402_5%

12

PCB21

0.1U_0402_25V6

1 2

PRB38 0_0402_5%@0@

Security Classification Compal Secret Data

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

12

PCB6

PCB5

2200P_0402_50V7K

0.1U_0402_25V6

VDDP_CHG

4

EMB12N03V_N_DFN33-8-5

12

PCB16 1U_0402_6.3V6K

+19V_VIN

CSOP_CHG_R

CSON_CHG_R

PQB13

AON7380_DFN3X3-8-5

5

PQB1

5

AON7506_DFN33-8-5

123

4.7UH_PCMB063T-4R7MS_8A_20%

12

PQB2

5

4

12

123

PRB26

@0@

0_0603_5%

1 2

2014/11/05 2014/12/15

1 2 3

4

PCB10

@

1 2

0.1U_0402_25V7K

Choke 4.7uH SH00000YC00 (Common Part) (Size:6.6 x 7.3 x 3 mm) (DCR:28m~3 3m)

PLB1

1 2

PRB19

4.7_1206_5%

EMI@

PCB17

680P_0402_50V7K

EMI@

+17.4V_BATT_CHG

+12.6V_BATT

Compal Secret Data

Deciphered Date

2

PRB16

0.01_1206_1%

1

2

Support max charge 3.5A Power loss: 0.245W CSR rating: 1W VCSPP-VCSON spec < 81mV

12

PCB13

10U_0603_25V6M

+12.6V_BATT

12

PCB14

PCB26

@

10U_0603_25V6M

4

3

PCB12

10U_0603_25V6M

For 4S per cell 4 .35V ba ttery

PQB4

4S_BATT@

LTC015EUBFS8TL_UMT3F

PRB40

4S_BATT@

100K_0402_1%

BATT_4S<58>

1 2

SUSP#<58,68,78,85,87,88>

Title

Size

Document Number Re v

Date: Sheet o f

2

4S_BATT@

L2N7002WT1G_SC70-3

13

D

2

G

S

Compal Electronics, Inc.

PWR_CHARGER

1

ACIN_CHG

PQB8

12

4S_BATT@

13

2M_0402_1%

83 100Friday, February 22, 2019

PRB28

1A

A

1 1

+19VB

PL311

EMI@

FBMA-L11-201209-800LMA50T

1 2

+19VB_3V

12

PC304

PC302

PC303

2200P_0402_50V7K

EMI@

0.1U_0402_25V6

@EMI@

+3VALWP

PR305

100K_0402_5%

SPOK_3V<58,87>

2 2

+19VB

PL511

EMI@

FBMA-L11-201209-800LMA50T

1 2

12

PC502

PC517

0.1U_0402_25V6

10U_0603_25V6M

@EMI@

+3VLP

12

PR503

100K_0402_5%

SPOK_5V<58>

PR504

2.2K_0402_5%

EC_ON<58>

3 3

4 4

MAINPWON<58,77,82>

A

@0@

0_0402_5%

1 2

PR505

1 2

5V_3V_EN

12

PC516

4.7U_0402_6.3V6M

PR507

1M_0402_1%

B

EN1 and EN2 dont't floating

12

PC306

PC305

@

10U_0603_25V6M

PC503

EN1 and EN2 dont't be floating. EN :H>0.8V ; L<0.4V

12

10U_0603_25V6M

12

10U_0603_25V6M

SPOK_3V

3V_EN<58>

12

PC505

PC504

2200P_0402_50V7K

EMI@

@EMI@

Fsw : 600K Hz

B

LX_3V

0.1U_0402_25V6

ENLDO_3V5V

12

LX_5V

ENLDO_3V5V

6

LX

7

GND

8

GND

SY8288BRAC_QFN20_3X3

9

PG

10

NC

+19VB_5V

2

3

4

5V_3V_EN

C

PC301

PR303

@0@

0_0603_5%

BST_3V

1 2

1

2

5

11

LX

GND

PG

PU301

IN

IN3IN4IN

BS

20

LX

19

LX

18

GND

17

LDO

NC

GND

EN112EN2

FF13OUT14NC

15

3.3V LDO

PC315

1000P_0402_50V7K

3V_FB

1 2

5V10A@

1

13

SY8270CTMC_QFN13_4X3

IN

BS

GND

VCC

EN16EN2

FF7OUT8LDO

5

9

12

5V10A@

1000P_0402_50V7K

5V_FB 5V_FB_1

+19VB_5V BST_5V_8A BST_5V_8A_R

LX_5V

6

LX

7

GND

8

GND

SPOK_5V VCC_5V_8A

9

PG

10

NC

ENLDO_3V5V

5V_3V_EN

12

16

21

PC313

4.7U_0402_6.3V6M

150mA~300mA

PR306

1K_0402_5%

1 2

keep short pad, snubber is for EMI only.

@0@

0_0402_5%

BST_5V BST_5V_RBST_5V_R

1 2

PU501

12

LX

11

VCC_5V

10

5V10A@

2.2U_0402_6.3V6M

+5VLP

5V LDO 150mA~300mA

PC514

4.7U_0402_6.3V6M

5V10A@

PC515

1K_0402_1%

1 2

2

5

1

IN

IN3IN4IN

EN112EN2

FF13OUT14LDO

11

15

12

5V_8A_FB 5V_8A_FB_1

BS

GND

VCC

GND

0.1U_0603_25V7K

1 2

LX_3V

+3VLP

3V_SN

20

19

18

17

16

21

PC506

PR506

PU502

LX_5V

5V10A@

PC501

0.1U_0603_25V7K

1 2

@EMI@

PR509

@0@

0_0402_5%

1 2

5V8A@

PC518

2.2U_0402_6.3V6M

12

PR502

5V_SN

12

PC513

PR501

LX_5V

1 2

5V8A@

SY8288CRAC_QFN20_3X3

LX

NC

+5VLP_5V_8A

PC519

4.7U_0402_6.3V6M

5V8A@

PC520

Issued Date

C

1 2

5V8A@

1K_0402_1%

PR508

1 2

5V8A@

1000P_0402_50V7K

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D

Choke 2.2uH SH00000YV00 (Common Part)

PL301

2.2UH_7.8A_20%_7X7X3_M

1 2

12

@EMI@

PR304

4.7_1206_5%

12

@EMI@

PC314 680P_0402_50V7K

oke 1.5uH SH000016700 (Common Part)

Ch (Size:6.8 x 6.47 x 3 mm) (DCR:14m~15m Ohm)

PL501

1.5UH_9A_20%_7X7X3_M

1 2

4.7_1206_5%

680P_0402_50V7K

PC521

5V8A@

0.1U_0603_25V7K

1 2

12

PC308

PC307

@

22U_0603_6.3V6M

Vout is 3.234V~3.366V

12

PC508

PC507

@

22U_0603_6.3V6M

+5VALWP

Compal Secret Data

2017/11/15 2019/11/15

Compal Secret Data

Deciphered Date

D

PC309

PC509

22U_0603_6.3V6M

ENLDO_3V5V

12

PR302

150K_0402_1%

+3VALWP

12

PC312

PC310

PC311

@

22U_0603_6.3V6M

PJ302

@

2

112

JUMP_43X118

+5VALWP

12

PC512

PC511

PC510

22U_0603_6.3V6M

Iocp =12 A

PJ502

+5VALWP +5VALW

@

112

JUMP_43X118

Title

Size Document Number R ev

Custom

DH5AV_JV_0V_LA-G021P

Date: Sheet of

E

PR301 499K_0402_1%

1 2

+19VB

+3VALW+3VALWP

2

Compal Electronics, Inc.

+3VALW/+5VALW

84 100Friday, February 22, 2019

E

1A

A

PJM1

@

JUMP_43 X79

2

112

+19VB

1 1

1 2

PLM11

@EMI@

HCB2012 KF-121T50_080 5

1UH_PCM C063T-1R0MN_1 1A_20%

+1.2VP

PCM922U_0603_6.3V6M

PCM1022U_0603_6.3V6M

PCM1122U_0603_6.3V6M

PCM1222U_0603_6.3V6M

1

2 2

Choke 1uH SH00000YE00 (Common Part) (S

ize:6.86 x 6.47 x 3 mm)

(DCR:6.2m~7.2m Ohm)

3 3

Mode Level +0.675VSP VTTREF_1.35V S5 L off off S3 L off on S0 H on on

Note: S3 - sleep ; S5 - power off

1

2

1

2

PCM1422U_0603_6.3V6M

PCM1322U_0603_6.3V6M

1

2

1

2

+19VB_1.2VP

+19VB_1 .2VP

12

PCM20

0.1U_0402_25V6

EMI@

1 2

12

PCM1

PCM2

0.1U_0402_25V6

EMI@

@EMI@

PLM1

H/S AON7408 Rds(on) :typ:27m Ohm, max:34m Ohm Idsm(TA=25)=7.5A, Idsm(TA=70)=5.5A

L/S AON7506 Rds(on) :typ:13m Ohm, max:15.8m Ohm Idsm(TA=25)=12A, Idsm(TA=70)=10.5A

Choke: SH00000YE00 Size:7x7x3 (Common Part) Rdc=6.7mohm(Typ), 7.4mohm(Max) CYNTEC Rdc=Xmohm(Typ), 11mohm(Max) TOKO Rdc=6.2mohm(Typ), 7.2mohm(Max) Maglayers Rdc=8.3mohm(Typ), 10mohm(Max) Tai-Tech Rdc=6.7mohm(Typ), 7.4mohm(Max) Chilisin Rdc=6.9± 15% Panasonic

Switching Frequency: 530kHz Imax=A, Iocp=A Iocp=10 .63~1 2.76A OVP: 110%~120% VFB=0.607V, Vout=1.214V

2200P_0402_50V7K

PRM2

@EMI@

4.7_1206 _5%

PCM15

@EMI@

680P_04 02_50V7K

12

PCM3

10U_0603_25V6M

LX_1.2VP

12

B

12

PCM4

5

10U_0603_25V6M

4

PQM1

123

EMB20N0 3V_DFN8-5

PQM2

5

EMB12N0 3V_N_DFN33-8-5

0.1U_060 3_25V7K

PCM5

12

PRM3

5.1_0603 _5%

1 2

+5VALW

4

123

1U_0201 _6.3V6K

C

BST_1.2V P_R

IOCP

12

PCM17

30MA_30 V_0.5UA_0.4V_S OD323-2

35.4

+5VALW

SM_PG_CTRL<10>

PRM11

2.2_0603 _5%

1 2

LG_1.2VP

PRM1

20K_040 2_1%

1 2

PCM8

1U_0201 _6.3V6K

1 2

35.4

VDD_1.2V P

2 1

PDM1

@

+19VB_1 .2VP

SYSON<58,78,87>

SUSP#<58,68,78,83,87,88>

CS_1.2VP

12

BST_1.2V P

UG_1.2VP

LX_1.2VP

PUM1

15

LGATE

14

PGND

13

CS

12

VDDP

11

VDD

PRM4

2.2_0402 _1%

Frequency

PRM6

470K_04 02_1%

1 2

@0@

0_0402_ 5%

1 2

0.1U_040 2_16V7K

@0@

0_0402_ 5%

1 2

D

Pin19 need pull separate from +1.35VP. If you have +1.35V and +0.675V sequence question, you can change from +1.35VP to +1.35VS.

+1.2VP

12

17

16

PHASE

RT8207P GQW_W QFN20_3X3

PGOOD

9

10

TON_1.2VP

PRM8

PCM18

@

PRM9 0_0402_ 5%

1 2

PRM10

0.1U_040 2_16V7K

19

18

UGATE

TON

8

EN_1.2VP

12

20

21

VTT

BOOT

S5

PAD

VTTGND

VTTSNS

GND

VTTREF

VDDQ

FB

6

FB_1.2VP

1

2

3

4

5

VTTREF_ 1.2VP

6.19K_04 02_1%

1 2

12

PRM7 10K_040 2_1%

PRM5

VLDOIN

S3

7

EN_0.6VSP

PCM6

+1.2VP

Vout=0.75V* (1+Rup/Rdown) =0.75*(1+(6.19/10)) =1.214V 1.2%

Vout=0.75V* (1+Rup/Rdown) =0.75*(1+(8.2/10)) =1.365V 1.1%

PJM2

@

+1.2VP

12

PCM19

@

+0.6VSP

JUMP_43 X118

112

PJM3

@

JUMP_43 X39

112

12

10U_0603_6.3V6M

12

PCM16

0.033U_0 402_16V7K

+1.2VP

2

E

0.6Volt +/- 5% TDC 0.7A Peak Current 1A

+0.6VSP

PCM7

10U_0603_6.3V6M

+1.2V_VDDQ

+0.6VS_VTT

4 4

Security Classification

2016/11/ 03 2017/06 /14

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

2016/11/ 03 2017/06 /14

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

DDR4

Size Document Number Re v

Custom

DH53F M/B LA-F991P

Date : Sheet o f

D

Date : Sheet o f

85 1 00Friday, February 22, 201 9

E

1A

A

2

12

PC1102

EMI@

0.1U_0603_25V7K

+19VB_1VALW

12

PC1103

PC1104

EMI@

2200P_0402_50V7K

@EMI@

PR1109

1M_0402_1%

12

PC1105

0.1U_0402_25V6 10U_0603_25V6M

EN_1VALW

ILMT_1VALW

+3VALW

EN_1VALW

12

1 1

+19VB

PJ1102

@

JUMP_43X79

112

LDO_3V

12

@0@

PR1103 0_0402_5%

ILMT_1VALW

12

@

PR1105 0_0402_5%

2 2

8288RAC Min ILMT='0' 8A ILMT=Floating 12A ILMT='1' 16A

B

EN pin don't floating If have pull down resistor at HW side, pls delete PR702

+19VB_1VALW

PC1115

@

0.22U_0402_16V7K

12

PR1107

10K_0402_1%

1 2

PR1108

@

10K_0402_1%

1 2

PU1101

2

IN

3

IN

4

IN

5

IN

7

GND

8

GND

18

GND

11

EN

13

ILMT

15

BYP

SY8288RAC_QFN20_3X3

PC1114 1U_0201_6.3V6M

PG

BS

LX

FB

VCC

NC

PAD

+1.8_PG <87>

+3VALW

9

1

LX_1VALW

6

19

20

FB_1VALW

14

LDO_3V

17

10

12

16

21

@0@

0_0603_5%

1 2

12

PC1113

2.2U_0402_6.3V6M

PR1102

C

Choke 1uH SH00000YE00 (Common Part)

ize:6.86 x 6.47 x 3 mm)

(S (DCR:6.2m~7.2m Ohm)

Choke: SH00000YE00 Size:7x7x3 (Common Part) Rdc=6.7mohm(Typ), 7.4mohm(Max) CYNTEC Rdc=Xmohm(Typ), 11mohm(Max) TOKO Rdc=6.2mohm(Typ), 7.2mohm(Max) Maglayers Rdc=8.3mohm(Typ), 10mohm(Max) Tai-Tech Rdc=6.7mohm(Typ), 7.4mohm(Max) Chilisin Rdc=6.9± 15% Panasonic

PR1101

@EMI@

4.7_1206_5%

PC1106

0.1U_0603_25V7K

BST_1VALW_RBST_1VALW

1 2

1UH_11A_20%_7X7X3_M

1 2

FB = 0.6V

@EMI@

680P_0402_50V7K

SNUB_1VALW

1 2

PL1101

12

Rup

PR1104

15.4K_0402_1%

1K_0402_1%

1 2

12

PR1106

Rdo wn

20K_0402_1%

Vout=0.6V* (1+Rup/Rdown ) =0.6*(1+ (15.4/20)) Vout=1.062V

PC1101

PR1110

D

PJ1101

@

JUMP_43X118

+1.05VALWP

12

PC1109

PC1108

PC1107

22U_0603_6.3V6M

330P_0402_50V7K

12

PC1110

22U_0603_6.3V6M

2

112

+1.05VALWP

1

+

PC1112

PC1111

2

@

22U_0603_6.3V6M

220U_B2_4VM_R35M

E

+1.05VALW

3 3

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELE CTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELE CTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2016/11/03 2017/06/14

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

1V

Size

Document Number Rev

C

DH53F M/B LA-F991P

Date: Sheet of

E

86 100Friday, February 22, 2019

1A

5

4

3

PR1809

100K_0402_5%

2

12

+3VALW

+1.8_PG <86>

1

+19VB

D D

1.8VALWP_LDO

12

@0@

PR1807 0_0402_5%

1.8VALWP_ILMT

12

@

PR1806 0_0402_5%

C C

82

88RAC Min ILMT='0' 8A ILMT=Floating 12A ILMT='1' 16A

PJ1802

@

2

112

JUMP_43X79

SPOK_3V<58,84>

PC1816

EMI@

PR1801

@0@

0_0402_5%

1 2

PR1805

1M_0402_1%

12

0.1U_0402_25V6

12

PC1808

PC1815

0.1U_0402_25V6

2200P_0402_50V7K

EMI@

@EMI@

12

PC1811

@

0.47U_0402_6.3V6K

+19VB_1.8VALWP

12

PC1802

PC1801

10U_0603_25V6M

1.8VALWP_ILMT

+3VALW

PJ2501 JUMP_43X79

@

12

+5VALW

PR2502

1M_0402_5%

2

1

12

PC2502

22U_0603_6.3V6M

PR2501

@0@

SYSON<58,78,85>

0_0402_5%

1 2

12

PC2503

@

0.1U_0402_16V7K

12

VIN_2.5V EN_2.5V

12

PU1801

2

IN

3

IN

4

IN

5

IN

7

GND

8

GND

18

GND

11

EN

13

ILMT

15

BYP

PC1807 1U_0201_6.3V6M

PC2501

1U_0402_6.3V6K

4 3 2 1

SY8286RAC_QFN20_3X3

PU2501 G9661MF11U_SO8

VPP

NC

VIN

VO

VEN

ADJ

POK

GND

9

PG

1

BS

6

LX

19

LX

1.8VALWP_LX

20

LX

1.8VALWP_FB

14

FB

1.8VALWP_LDO

17

VCC

10

NC

12

NC

16

NC

21

PAD

@0@

0_0603_5%

PR1808

1 2

12

PC1809

2.2U_0402_6.3V6M

PC1810

0.1U_0603_25V7K

1 2

PR1802

@EMI@

4.7_1206_5%

1 2

PL1801

1UH_6.6A_20%_5X5X3_M

1 2

PC1806

@EMI@

1.8VALWP_SNB1.8VALWP_BST

680P_0402_50V7K

1 2

+1.8VALWP

(R

12

PR1803

20.5K_0402_1%

1K_0402_1%

1 2

1)

PR1810

12

PC1803

330P_0402_50V7K

12

PC1812

PC1813

22U_0603_6.3V6M

12

PC1814

22U_0603_6.3V6M

12

PC1817

PC1805

PC1804

22U_0603_6.3V6M

@

FB = 0.6V

PJ1801

@

12

PR1804

10K_0402_1%

(R2 )

FB=0.8V

21.5K_0402_1%

FB_2.5V

10K_0402_1%

PR2503

PR2504

Note:Iloa d(max)=4A

12

Rup

12

Rdo wn

12

PC2504

0.01U_0402_25V7K

Vout=0.8V* (1+Rup/Rdown ) Vout=0.8V* (1+(21.5/10)) = 2.52V (x1.00 8)

+2.5VP

12

PC2505

PC2506

22U_0603_6.3V6M

@

+2.5VP +2.5V

5 6 7 8

+1.8VALWP +1.8VALW

Vout=0.6V* (1+Rup/Rdown) Vout=0.6V*(1+20 .5/10) =1.83V (x1.017)

PJ2502

@

JUMP_43X79

2

112

JUMP_43X79

112

2

B B

2s_battery_EMI@

PCT1

4.7UH_PCME051E-4R7MS_3A_20%

12

PCT4

PCT3

10U_0603_25V6M

1500P_0402_50V7K

2s_battery@

680P_0603_50V7K

2s_battery@

1 2

SH00000OG00

2s_battery@

10U_0603_25V6M

EN_12VSP

RT9297GQW_WDFN10_3X3

SA00004JV00

P-MOS

PQT1

2s_battery@

5A_Z120_25M_0805_2P

1 2

2s_battery@

PRT5

2s_battery@

PCT13

PLT12

100K_0402_1%

10K_0402_1%

12

PRT2

PRT4

12

13

D

2

G

S

2s_battery bead@

+5VALW

@2s_battery@

0_0402_5%

SUSP#<58,68,78,83,85,88>

A A

5

1 2

0.1U_0402_25V7K

AONR21321_DFN8-5

1

3

12

2s_battery@

PCT2

0.022U_0402_25V7K

2s_battery@

PQT2

2N7002KW_SOT323-3

52

4

12

2s_battery_EMI@

PRT1

4.7_1206_5%

12

PUT1

PLT1

PCT6

12

PDT1

2s_battery@

SS3P4-M3-84A_SMP2

2 1

LX_12VSP

8

Vin

FREQ9SS

3

EN

PAD

11

7

LX6LX

COMP

GND5GND

4

12

2s_battery@

88.7K_0402_1%

FB_12VSP

2

FB

SS_12VSP

1 2

10

2s_battery@

COMP_12VSP

1

0.01U_0402_50V7K

12

2s_battery@

PRT7 10K_0402_1%

12

2s_battery@

PCT14 4700P_0402_25V7K

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELE CTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELE CTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

PRT3

PCT12

12

PCT5@2s_battery@

12

2s_battery@

PRT6 10K_0402_1%

2017/11/23 2017/12/31

+12VSP

PCT9

PCT8

12

100P_0402_50V8J

10U_0603_25V6M

2s_battery@

PCT10

12

10U_0603_25V6M

2s_battery@

Vout= 1.24* (1+88 .7/ 10) =12 .2V

Compal Secret Data

Deciphered Date

2

1 2

2s_battery bead@

5A_Z120_25M_0805_2P

PCT7

12

PCT11

0.1U_0402_25V6 2200P_0402_50V7K

2s_battery_EMI@

PLT11

+INVPWR_B+_BOOST

Compal Electronics, Inc.

Title

Size

Date: Sheet of

Compal Electronics, Inc.

1.5VS/2.5V

Document Number Re v

EH5VF M/B LA-H501P

1

1A

87 100Friday, February 22, 2019

1A

5

4

3

2

1

D D

can improve CNVI lose issue

PLH11

EMI@

HCB2012KF-121T50_0805

1 2

PJH2

@

2

+19VB

C C

112

JUMP_43X79

PCH2

2200P_0402_50V7K

EMI@

12

PCH3

0.1U_0402_25V6

@EMI@

+3VALW

12

+VCCIOP_B+

12

PCH5

10U_0603_25V6M

+VCCIOP_EN

+VCCIOP_ILMT

12

PUH1

2

IN

3

IN

4

IN

5

IN

7

GND

8

GND

18

GND

11

EN

13

ILMT

15

BYP

PCH14 1U_0201_6.3V6M

SY8286RAC_QFN20_3X3

Pin 7 BYP is for CS. Common NB can delete +3VALW and PC15

PG

BS

LX

FB

VCC

NC

PAD

9

+VCCIOP_BST +VCCIOP_BST_R

1

6

19

20

14

+VCCIOP_LDO_3V

17

10

12

16

21

+VCCIOP_FB

0_0603_5%@0@

PRH2

1 2

+VCCIOP_LX

12

2.2U_0402_6.3V6M

0.1U_0603_25V7K

PCH13

+VCCIOP_LDO_3V

12

PRH10

@

0_0402_5%

+VCCIOP_ILMT

12

PRH12

@

0_0402_5%

8286RAC Min Typ Max ILMT='0' 6.5A 7.5A 8.5A ILMT=Floating 9.5A 10.5A 11.5A ILMT='1' 12.5A 13.5A 14.5A

B B

VR_ON<58,78,89>

SUSP#<58,68,78,83,85,87>

VR_ON

SUSP#

check delay time with HW

@

0_0402_5%

1 2

1K_0402_5%

1 2

PRH9

PRH11

PRH13

12

1M_0402_5%

+VCCIOP_EN

12

PCH15

0.1U_0402_25V6

Choke: SH00000Z300 (Common Part) Rdc=10mohm(Typ), 12mohm(Max) Size:6*5.4*3 Tai-Tech Rdc=11mohm(Typ), 12mohm(Max) Size:5.3*4.9*3 Maglayers

PRH1

PCH4

1 2

@EMI@

FB = 0.6V

4.7_1206_5%

SNB_+VCCIOP

1 2

PLH1

0.68UH_7.9A_20%_5X5X3_M

1 2

PRH4

@

Rdo wn

12

1 2

1K_0402_1%

12

PRH6

20.5K_0402_1%

PCH1

@EMI@

680P_0402_50V7K

1 2

PCH10

@

330P_0402_50V7K

Rup

1 2

PRH5

12K_0402_1%

12

PRH3

VCCIO_SENSE_R

10_0402_1%

PJH1

@

2

+1.0VS_VCCIOP +VCCIO

112

JUMP_43X118

Imax=3.85A, Ipeak=5.5A, Iocp:6.6A

+1.0VS_VCCIOP

12

PCH8

22U_0603_6.3V6M

1 2

PCH9

12

22U_0603_6.3V6M

12

PCH11

@

22U_0603_6.3V6M

VCCIO_SENSE

VSSIO_SENSE

Note: Iload (ma x)= 5.5 A

PCH12

IOCP= 7A~8 A(t yp)

22U_0603_6.3V6M

VCCIO_SENSE <12>

VSSIO_SENSE <12>

Vout=0.6V* (1+Rup/Rdown ) = 0.6*(1+(12k/20.5k)) OVP=0 .95V* 115% =1. 092 5V

Vout=0.951 V 2%

12

PCH6

PCH7

22U_0603_6.3V6M

PRH7 0_0402_5%@0@

PRH8 0_0402_5%@0@

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELE CTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELE CTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2016/11/03 2017/06/14

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size

Date: Sheet of

Compal Electronics, Inc.

DH53F M/B LA-F991P

Document Number Re v

1.0VS_VCCIO

1

88 100Friday, February 22, 2019

1AC

1

2

3

4

5

Place close to Choke in VCCSA first phase circuit

PCZ1

PRZ9

0_0402_5%

1 2

PRZ11

0_0402_5%

PRZ24

0_0402_5%

1 2

PCZ12

1 2

PRZ27

0_0402_5%

PCZ25

1 2

PCZ4

PCZ17

470P_0402_50V8J

1 2

680P_0402_50V7K

2200P_0402_50V7K

1 2

PRZ10

1K_0402_5%

1 2

PRZ12

1 2

1.62K_0402_1%

1 2

PCZ9

1000P_0402_50V7K

PRZ28

1 2

1K_0402_1%

1 2

PCZ13

2200P_0402_50V7K

CSSUM_4PH

VSN_1PH

VSP_1PH

VSP_4PH

VSN_4PH

+19VB_CPU

PRZ3 100_0402_1%

+VCC_SA

VCCSENSE<11>

VSSSENSE<11>

PRZ36

3.65K_0402_1%

1 2

12

1 2

PRZ15 100_0402_1%

PRZ21 100_0402_1%

PRZ29 100_0402_1%

PCZ16

15P_0402_50V8J

1 2

2200P_0402_50V7K

PRZ48

165K_0402_1%

CSP1_4PH

@

100K_0402_1%

1 2

CSP2_4PH

@

100K_0402_1%

1 2

CSP3_4PH

@

100K_0402_1%

1 2

CSP4_4PH

@

100K_0402_1%

1 2

12

PRZ60

PRZ68

PRZ70

PRZ74

A A

VSSSA_SENSE<12>

VCCSA_SENSE<12>

+VCC_CORE

B B

Place close to Choke in VCORE fi

rst phase circuit

SW1_4PH<89,90>

SW2_4PH<89,90>

SW3_4PH<89,90>

SW4_4PH<89,90>

CSREF_4PH<90>

SW1_4PH<89,90>

C C

SW2_4PH<89,90>

SW3_4PH<89,90>

SW4_4PH<89,90>

PHZ2

220K_0402_5%_ERTJ0EV224J

PRZ47

90.9K_0603_1%

1 2

PRZ50

90.9K_0603_1%

1 2

PRZ52

90.9K_0603_1%

1 2

PRZ54

90.9K_0603_1%

1 2

PRZ59

2.15K_0402_1%

1 2

PCZ34

0.1U_0402_25V6

CSREF_4PH

PRZ67

2.15K_0402_1%

1 2

PCZ36

0.1U_0402_25V6

CSREF_4PH

PRZ69

2.15K_0402_1%

1 2

PCZ37

0.1U_0402_25V6

CSREF_4PH

PRZ71

2.15K_0402_1%

1 2

PCZ38

0.1U_0402_25V6

CSREF_4PH

1 2

PCZ18

@0@

1000P_0402_50V7K

@0@

1000P_0402_50V7K

@0@

PRZ34

49.9_0402_1%

1 2

PRZ37

1K_0402_1%

1 2

12

PRZ44

75K_0402_1%

PCZ24

220P_0402_50V8J

CSREF_4PH

CSN_1PH<91 >

10_0402_1%

PCZ5

3300P_0402_50V7-K

PRZ35

H62@

28K_0402_1%

PRZ35

H82@

25.5K_0402_1%

12

PCZ21

470P_0402_50V8J

12

DIFFOUT_4PH FB_4PH

30.1K_0402_1%

PRZ55

1K_0402_1%

1 2

PCZ31

0.01U_0402_50V7K

1 2

+5VALW

PRZ61

COMP_4PH

2.2_0603_5%

PWM1_4PH/ICCMAX4<90>

PWM2_4PH/ADDR<90>

PWM3_4PH/VBOOT<90>

PWM4_4PH/ROSCM< 90>

220K_0402_5%_ERTJ0EV224J

1 2

PRZ42

PCZ26

0.1U_0402_25V7K

1 2

H62@

102K_0402_1%

Place close to H-side,L-side MOS in VCORE first phase

PHZ1

100K_0402_1%_TSM0B104F4251RZ

12

PRZ4

12

PRZ22

1.5K_0402_1%

VSP_4PH VSN_4PH

CSP1_4PH CSP2_4PH CSP3_4PH

1 2

PRZ56

ILIM_4PH

PHZ4

10 11 12 13

PCZ30

0.1U_0402_25V6

12

PRZ72

0_0402_5%

@0@

12

1 2 3 4 5 6 7 8 9

12

PCZ33

TSENSE_4PH

15P_0402_50V8J

VSP_4PH VSN_4PH IMON_4PH DIFFOUT_4PH FB_4PH COMP_4PH ILIM_4PH CSCOMP_4PH CSSUM_4PH CSREF_4PH CSP1_4PH CSP2_4PH CSP3_4PH

TSENSE_4PH

1U_0402_6.3V6K

12

PRZ1

12K_0402_1%

1 2

PCZ2

0.01U_0402_50V7K

1 2

PCZ6

2200P_0402_50V7K

CSN_1PH_R

PCZ8

1000P_0402_50V7K

1 2

PRZ19

12.4K_0402_1%

PCZ10

0.01U_0402_25V7K

12

1 2

PCZ11

VSN_1PH

VSP_1PH

52

53

TAB

15

DRVON<90,91>

12

PRZ61

110K_0402_1%

H82@

Place close to H-side,L-side MOS

VCCGT first phase

in

PRZ75

61.9K_0402_1%

VSP_1PH

12

COMP_1PH

51

VSN_1PH

VCC16TSENSE_4PH14VRMP

ILIM_1PH

49

50

ILIM_1PH

COMP_1PH

PWM1_4PH/ICCMAX_4PH18PWM2_4PH/ADDR19PWM3_4PH/VBOOT20PWM4_4PH/ROSC_MPH21PWM2_2PH/ROSC_1PH22PWM1_2PH/ICCMAX_2PH

DRON

17

PRZ62

4.32K_0402_1%

48

12

PRZ2

7.5K_0603_1%

1 2

12

CSP_1PH

PCZ7

IMON_1PH

470P_0402_50V8J

43

46

41

42

45

47

44

EN

SCLK

ALERT#

VR_RDY

CSP_1PH

CSN_1PH

IMON_1PH

PWM_1PH/ICCMAX_1PH

TTSENSE_1PH/PSYS24TTSENSE_2PH25CSP4_4PH

23

26

TSENSE_2PH

12

PRZ63

24.9K_0402_1%

220K_0402_5%_ERTJ0EV224J

SW_1PH <91>

+3VS

PRZ14

12

28K_0402_1%

CPU_EN 81215_SCLK 81215_ALERT 81215_SDIO

PUZ1 NCP81215MNTXG_QFN52_6X6

40

SDIO

VRHOT# VSP_2PH VSN_2PH

IMON_2PH

DIFFOUT_2PH

FB_2PH

COMP_2PH

ILIM_2PH

CSCOMP_2PH

CSSUM_2PH CSREF_2PH

CSP1_2PH CSP2_2PH

CSP4_4PH

0.1U_0402_25V6

1 2

PWM2_2PH/ROSC1

12

PRZ64

PRZ65

97.6K_0402_1%

PRZ73

0_0402_5%

@0@

PHZ5

LA-F611PR01_0531C.DSN PCH_PWROK change to IMVP_VR_PG(P.72 PUZ01.45)

1 2

@0@

0_0402_5%

VSP_2PH VSN_2PH

DIFFOUT_2PH

FB_2PH

COMP_2PH

ILIM_2PHCSCOMP_4PH

CSSUM_2PH

12

+5VALW

12

+5VALW

PRZ57

24.9K_0402_1%

1 2

PRZ58

25.5K_0402_1%

PWM1_2PH/ICCMAX2 <9 1>

PWM1_1PH/ICCMAX1 <9 1>

PRZ23

34.8K_0402_1%

1 2

VR_ON <58,78,88>

PRZ25

2200P_0402_50V7K

1 2

PRZ43 12K_0402_1%

12

PCZ29

0.1U_0402_25V7K

1.37K_0402_1%

1 2

29.4K_0402_1%

1 2

470P_0402_50V8J

PRZ17

10K_0402_1%

39 38 37 36 35 34 33 32 31 30 29 28 27

PCZ32

12

TSENSE_2PH

12

VCCCORE_VR_PWRGD<58>

CSP1_2PH

1K_0402_1%

PRZ53

@

1K_0402_1%

12

PRZ76

61.9K_0402_1%

81215_VR_HOT

PRZ46

+1.05V_VCCST

81215_VR_HOT

81215_SCLK

81215_ALERT

81215_SDIO

LA-F611PR01_0531C.DSN IMVP_VR_ON change to VR_ON(P.72 PUZ01.43)

@0@

0_0402_5%

1 2

12

PCZ14

1000P_0402_50V7K

PRZ31

1 2

@0@

1 2

0_0402_5%

PCZ15

PRZ39

PCZ23

1 2

@

CSP1_2PH

12

PRZ5

@

499_0402_1%

PRZ13

100_0402_1%

1 2

PRZ16 49.9_0402_1%

12

PRZ18 0_0402_5%@0@

1 2

PRZ20 10_0402_1%

PRZ26 100_0402_1%

1 2

PRZ30

PRZ32

PRZ33 100_0402_1%

1 2

CSCOMP_2PH

12

PCZ27

PCZ28

100P_0402_50V8J

680P_0402_50V7K

CSREF_2PH

2.15K_0402_1%

1 2

PCZ35

0.1U_0402_25V6

1 2

PRZ6

100_0402_1%

PRZ45

75K_0402_1%

PRZ66

CSREF_2PH

1 2

12

PR1199 NA, need confirm

12

PRZ7

@

45.3_0402_1%

PRZ8

45.3_0402_1%

PCZ3

0.1U_0402_25V6

1 2

LA-F611PR01_0531D.DSN

OCHOT# change to H_PROCHOT#(P.72 PUZ01.39)

PR

VR_HOT# <58>

CPU_SVID_CLK <10>

CPU_SVID_ALERT#_R <10>

CPU_SVID_DAT < 10>

+VCC_GT

VCCGT_SENSE <11>

VSSGT_SENSE <11>

PRZ38

PCZ19

49.9_0402_1%

470P_0402_50V8J

1 2

12

PRZ40

1K_0402_1%

12

PHZ3 220K_0402_5%_ERTJ0EV224J

Place close to Choke in VCCGT first phase circuit

PRZ49 274K_0402_1%

100K_0603_1%

CSREF_2PH <91>

SW1_2PH <89,91>

PRZ51

1 2

15P_0402_50V8J

1 2

PRZ41

3.65K_0402_1%

PCZ20

1 2

PCZ22

2200P_0402_50V7K

SW1_2PH <89,91>

D D

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY P ROPERTY OF COMPAL ELECTRONICS , INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY P ROPERTY OF COMPAL ELECTRONICS , INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUS TODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUS TODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUS TODY OF THE C OMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHE R THIS SHEET NOR THE INFORM ATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHE R THIS SHEET NOR THE INFORM ATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHE R THIS SHEET NOR THE INFORM ATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS , INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS , INC.

1

2

3

2016/02/01 2017/12/31

Compal Secret Data

Deciphered Date

4

Title

Size

Document Number Re v

Custom

Date : Sheet of

Compal Electronics, Inc.

SKL_H 42

CPU IC

5

89 100Friday, February 22, 2019

1A

Main Func = CORE

D D

5

BOOT1_VCORE

1

12

PCZ49

2.2U_0402_6.3V6M

2

3

4

PWM1_4PH/ICCMAX4<89>

DRVON<89,91>

+5VALW

4

PRZ77

2.2_0603_5%

1 2

PUZ2 NCP81151MNTBG_DF N8_2X2

9

BST

FLAG

8

PWM

DRVH

7

EN

SW

6

VCC

GND

5

DRVL

PCZ50

0.22U_0603_25V7K

DRVH1_VCORE

VSW1_VCORE

DRVL1_VCORE

3

MOS

FET: DFN 5X6E

H/S Rds(on): 5.2mohm(Typ), 7mohm(Max)

PRZ85

0_0603_5%

1 2

12

L/S Rds(on): 0.8mohm( Typ), 1.05mohm(Max)

DRVH1_VCORE-1

PQZ1@

AON6962_DFN5X6D -8-7

2

1

D1

G1

7

D2/S1

S24S2

S2

5

3G26

7

1

G1

D2/S1

AON6962_DFN5X6D -8-7

2

D1

S24S2

5

3G26

PQZ2

S2

12

SNB1_VCORE

12

@EMI@

PRZ78

4.7_1206_5%

@EMI@

PCZ51 680P_0402_50V7K

2

PCZ39

PCZ46

10U_0603_25V6M

12

PLZ1

0.15UH_NA__36A_20 %

1

2

10U_0603_25V6M

1

+

2

4

3

SH00001D 800 7x7X4 Isat:45 A DCR:0.67mΩ +/-5%

1

+

PCZ47

PCZ48

2

33U_25V_M

@

1 2

PRZ89 10_0402_1%

1

+

PCZ65

2

33U_25V_M

+VCC_CORE

12

PCZ58

33U_25V_M

EMI@

0.1U_0603_25V7K

SW1_4PH <89>

PLZ11

EMI@

+19VB_CPU

12

PCZ59

EMI@

HCB2012KF-121T50 _0805

1 2

PLZ12

EMI@

HCB2012KF-121T50 _0805

12

0.1U_0603_25V7K

1 2

PCZ60

EMI@

0.1U_0603_25V7K

ke: SH00001D800 Size:7x7x4 Maglayers

Cho DCR:0.67mΩ +/-5% Isat: 45A

CSREF_4PH <89>

1

+19VB

PRZ84

0_0603_5%

DRVH2_VCORE-1

1 2

PRZ79

2.2_0603_5%

BOOT2_VCORE

1 2

PUZ3 NCP81151MNTBG_DF N8_2X2

1

BST

C C

PWM2_4PH/ADDR<89>

DRVON

+5VALW

12

PCZ52

2.2U_0402_6.3V6M

BOOT3_VCORE

PWM3_4PH/VBOOT<89 >

DRVON

+5VALW

12

DRVON

PCZ55

2.2U_0402_6.3V6M

BOOT4_VCORE

B B

PWM4_4PH/ROSCM<89>

+5VALW

12

A A

2

3

4

PRZ81

2.2_0603_5%

1 2

PUZ4 NCP81151MNTBG_DF N8_2X2

1

2

3

4

2.2_0603_5%

1

2

3

4

PCZ61

2.2U_0402_6.3V6M

FLAG

PWM

DRVH

EN

VCC

DRVL

BST

FLAG

PWM

DRVH

EN

VCC

DRVL

PRZ87

1 2

PUZ5 NCP81151MNTBG_DF N8_2X2

BST

PWM

EN

VCC

PCZ53

0.22U_0603_25V7K

DRVH2_VCORE

VSW2_VCORE

DRVL2_VCORE

PCZ56

0.22U_0603_25V7K

DRVH3_VCORE

VSW3_VCORE

DRVL3_VCORE

PCZ62

0.22U_0603_25V7K

DRVH4_VCORE

VSW4_VCORE

DRVL4_VCORE

12

9

8

7

SW

6

GND

5

9

8

7

SW

6

GND

5

9

FLAG

8

DRVH

7

SW

6

GND

5

DRVL

AON6962_DFN5X6D -8-7

PRZ83

0_0603_5%

1 2

PRZ86

0_0603_5%

1 2

PQZ3@

DRVH3_VCORE-1

PQZ5

DRVH4_VCORE-1

PQZ7

PQZ4

7

1

G1

D2/S1

1

G1

D2/S1

1

G1

D2/S1

AON6962_DFN5X6D -8-7

2

D1

S24S2

5

3G26

AON6962_DFN5X6D -8-7

2

D1

S24S2

5

3G26

AON6962_DFN5X6D -8-7

2

D1

S24S2

5

3G26

S2

PQZ6@

S2

PQZ8@

S2

2

1

D1

G1

7

D2/S1

S24S2

S2

5

3G26

2

1

D1

G1

7

D2/S1

S24S2

S2

5

3G26

AON6962_DFN5X6D -8-7

2

1

D1

G1

7

D2/S1

S24S2

S2

5

3G26

AON6962_DFN5X6D -8-7

PCZ66

10U_0603_25V6M

12

@EMI@

PRZ80

4.7_1206_5%

SNB2_VCORE

12

@EMI@

PCZ54 680P_0402_50V7K

PCZ45

12

@EMI@

PRZ82

4.7_1206_5%

SNB3_VCORE

12

@EMI@

PCZ57 680P_0402_50V7K

12

@EMI@

PRZ88

4.7_1206_5%

SNB4_VCORE

12

@EMI@

PCZ64 680P_0402_50V7K

PCZ67

10U_0603_25V6M

12

0.15UH_NA__36A_20 %

PCZ44

10U_0603_25V6M

12

0.15UH_NA__36A_20 %

1

2

PCZ70

10U_0603_25V6M

12

0.15UH_NA__36A_20 %

1

2

10U_0603_25V6M

PCZ71

1

2

PLZ2

PLZ3

10U_0603_25V6M

PLZ4

4

3

0001D 800

SH0 7x7X4 Isat:45 A DCR:0.67mΩ +/-5%

4

3

SH00001D 800 7x7X4 Isat:45 A DCR:0.67mΩ +/-5%

PRZ91 10_0402_1%

4

3

SH00001D 800 7x7X4 Isat:45 A DCR:0.67mΩ +/-5%

+VCC_CORE

1 2

PRZ90 1 0_0402_1%

+VCC_CORE

1 2

+VCC_CORE

1 2

PRZ92 10_0402_1%

+19VB_CPU

SW2_4PH <89>

+19VB_CPU

SW3_4PH <89>

+19VB_CPU

SW4_4PH <89>

+VCC CORE

C= 80A->86A

TD Peak Current= 128A->140A OCP Current= 154A->168A Load Line= 1.8mV/A Vboot= 0V

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2016/02 /01 2017 /12/31

Compal Secret Data

Deciphered Date

2

Title

CPU_CORE

Size

Document N umber Re v

Custom

Date: Sheet o f

1

90 10 0Friday, February 22, 2019

1A

5

Main Func = VCCGT/+VCCSA

4

3

2

1

PCG4

12

PRG1

D D

PWM1_2PH/ICCMAX2<89>

BOOT1_VCCGT

DRVON

+5VALW

12

C C

PRA2

2.2_0603_5%

1 2

B B

PWM1_1PH/ICCMAX1<89>

DRVON<89,90>

BST_+VCC_SA

+5VALW

12

PCA4

2.2U_0402_6.3V6M

2.2_0603_5%

1 2

PUG1 NCP81151MNTBG_DFN8_2X2

1

BST

2

PWM

3

EN

4

VCC

PCG5

2.2U_0402_6.3V6M

0.22U_0603_25V7K

BST_R_+VCC_SA

PUA1 NCP81253MNTBG_DFN8_2X2

1

BST

PWM

EN

VCC

DRVH

SW

GND

DRVL

PAD

9

2

3

4

FLAG

DRVH

SW

GND

DRVL

PCA5

1 2

8

SW_+VCC_SA

7

6

5

0.22U_0603_25V7K

9

DRVH1_VCCGT

8

VSW1_VCCGT

7

6

5

PCG6

HG_+VCC_SA

12

LG_+VCC_SA

1 2

PRG3 0_0603_5%

DRVL1_VCCGT

1

2

D1

G1

9

D2/S1

S2

G2

7

8

DRVH1_VCCGT-1

PQA1

4

3

EMB09A03VP_EDFN3X3-8-10

D1

10

D1

S2

6

5

7

1

D2/S1

6

G1

G2

5

12

2

PQG1 AON6962_DFN5X6D-8-7

D1

S24S2

PCA2

12

SW_+VCC_SA

@EMI@

PRA1

4.7_1206_5%

SNB_SA

@EMI@

PCA6 680P_0402_50V7K

VSW1_VCCGT

S2

3

PCA1

10U_0603_25V6M

12

Ch

oke 0.47uH SH00001ED00 (Commom Part) (Size:5.7 x 5.4 x 3.0 mm) (DCR:6.2m +-5%)

PLA1

0.47UH_MMD05CZR47M_12A_20%

1

2

12

@EMI@

SNB1_GT

12

@EMI@

PCG7 680P_0402_50V7K

4

3

10U_0603_25V6M

12

PRG2

4.7_1206_5%

10U_0603_25V6M

0.15UH_NA__36A_20%

10U_0603_25V6M

12

PLG1

1

2

+19VB_CPU

CSN_1PH <89>

PCG9

10U_0603_25V6M

12

SH00001D 800 7x7 Isat:4 5A DCR:0.67 m

4

3

near choke

10_0402_1%

1 2

SW_1PH <89>

X4

PRG4

+VCC_SA

PCG8

PCG3

+19VB_CPU

Ω +/-5 %

+VCC_GT

+VCCGT TDC= 25A Peak Current= 32A OCP Current= 39A Load Line= 2.7mV/A Vboot= 0V

CSREF_2PH <89>

SW1_2PH <89>

+VCCSA TDC= 10A Peak Current = 11A OCP Current= 13A Load Line= 10.3mV/A Vboot= 1.05V

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SE CRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SE CRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SE CRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2016/01/06 2017/01/06

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Re v

Date : Sheet o f

2

Date : Sheet o f

Compal Electronics, Inc.

+VCC_GT/+VCC_SA

C1PRG LA-E051P

91 100Friday, February 22, 2019

1

1A

5

+VCC_CORE

Reve rse for Acou sti c

D D

+VCC_CORE

C C

1

+

PCZ176

2

@

220U_D7_2VM_R4.5M

12

PCZ104

@

22U_0603_6.3V6M

12

PCZ114

22U_0603_6.3V6M

H82@

12

PCZ124

@

22U_0603_6.3V6M

12

PCZ134

@

22U_0603_6.3V6M

H82 Total VCORE Output Capacitor: 3 X 220uF_D2_2V 28 +13@ X 22uF_0603_X5R for H82 22 +19@ X 22uF_0603_X5R for H62 24 +6@ X 1uF_0201

1

+

PCZ101

PCZ102

2

220U_D2_2V_Y

12

PCZ105

PCZ106

22U_0603_6.3V6M

12

PCZ115

PCZ116

22U_0603_6.3V6M

H82@

12

PCZ126

PCZ125

@

22U_0603_6.3V6M

12

PCZ136

PCZ135

@

22U_0603_6.3V6M

12

+

PCZ103

PCZ170

2

220U_D2_2V_Y

@

22U_0603_6.3V6M

12

PCZ107

PCZ108

22U_0603_6.3V6M

@

22U_0603_6.3V6M

H82@

12

PCZ117

PCZ118

@

22U_0603_6.3V6M

12

PCZ127

PCZ128

22U_0603_6.3V6M

H82@

12

PCZ137

PCZ138

@

22U_0603_6.3V6M

12

PCZ171

12

PCZ109

12

PCZ119

12

PCZ129

12

PCZ172

22U_0603_6.3V6M

12

PCZ110

22U_0603_6.3V6M

@

22U_0603_6.3V6M

12

PCZ120

@

22U_0603_6.3V6M

12

PCZ130

22U_0603_6.3V6M

4

3

2

1

+VCC_GT

1

+

2

PCG101

12

PCZ173

PCZ174

22U_0603_6.3V6M

PCZ111

22U_0603_6.3V6M

PCZ121

22U_0603_6.3V6M

PCZ131

22U_0603_6.3V6M

PCZ175

22U_0603_6.3V6M

12

PCZ112

PCZ113

22U_0603_6.3V6M

H82@

12

PCZ122

PCZ123

22U_0603_6.3V6M

H82@

12

PCZ132

PCZ133

22U_0603_6.3V6M

+VCC_GT +VCC_SA

12

PCG103

22U_0603_6.3V6M

12

PCG113

22U_0603_6.3V6M

12

PCG123

1U_0201_6.3V6M

12

PCG133

1U_0201_6.3V6M

2

220U_D2_2V_Y

@

12

PCG104

22U_0603_6.3V6M

PCG114

22U_0603_6.3V6M

PCG124

1U_0201_6.3V6M

PCG134

1U_0201_6.3V6M

PCG106

PCG105

22U_0603_6.3V6M

12

PCG115

12

PCG125

12

PCG135

@

12

PCG116

22U_0603_6.3V6M

12

PCG126

1U_0201_6.3V6M

12

PCG136

@

1U_0201_6.3V6M

Total VCCGT Output Capacitor: 2 X 220uF_D2_2V 18+2@ X 22uF_0603_X5R 12+8@ X 1uF_0201

PCG102

220U_D2_2V_Y

12

PCG107

PCG108

22U_0603_6.3V6M

PCG117

22U_0603_6.3V6M

PCG127

1U_0201_6.3V6M

PCG137

@

1U_0201_6.3V6M

PCG109

22U_0603_6.3V6M

12

PCG118

PCG119

22U_0603_6.3V6M

12

PCG128

PCG129

1U_0201_6.3V6M

12

PCG138

PCG139

@

1U_0201_6.3V6M

12

PCG110

PCG111

22U_0603_6.3V6M

12

PCG120

22U_0603_6.3V6M

12

PCG130

1U_0201_6.3V6M

12

PCG140

@

1U_0201_6.3V6M

PCG112

22U_0603_6.3V6M

12

PCG121

PCG122

@

22U_0603_6.3V6M

12

PCG131

PCG132

1U_0201_6.3V6M

12

PCG141

PCG142

@

1U_0201_6.3V6M

Total VCCSA Output Capacitor: 10+2@ X 22uF_0603 1+4@ X 1uF_0201

12

PCA104

PCA103

PCA102

PCA101

22U_0603_6.3V6M

12

PCA107

PCA108

@

22U_0603_6.3V6M

12

PCA113

PCA114

@

1U_0201_6.3V6M

22U_0603_6.3V6M

12

PCA110

PCA109

@

22U_0603_6.3V6M

12

PCA115

PCA116

@

1U_0201_6.3V6M

12

PCA106

PCA105

22U_0603_6.3V6M

12

PCA111

PCA112

@

22U_0603_6.3V6M

12

PCA117

@

1U_0201_6.3V6M

12

PCZ140

PCZ139

1U_0201_6.3V6M

B B

12

PCZ150

PCZ149

1U_0201_6.3V6M

12

PCZ159

PCZ160

1U_0201_6.3V6M

A A

5

12

PCZ142

PCZ141

1U_0201_6.3V6M

12

PCZ152

PCZ151

1U_0201_6.3V6M

12

PCZ162

PCZ161

1U_0201_6.3V6M

12

PCZ144

PCZ143

1U_0201_6.3V6M

12

PCZ153

PCZ154

1U_0201_6.3V6M

12

PCZ163

PCZ164

@

1U_0201_6.3V6M

12

PCZ146

PCZ145

1U_0201_6.3V6M

12

PCZ155

PCZ156

1U_0201_6.3V6M

12

PCZ166

PCZ165

@

1U_0201_6.3V6M

12

PCZ148

PCZ147

1U_0201_6.3V6M

12

1U_0201_6.3V6M

12

1U_0201_6.3V6M

12

PCZ158

PCZ157

1U_0201_6.3V6M

12

PCZ167

PCZ168

@

1U_0201_6.3V6M

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

NA 2014/07/04

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Re v

Date : Sheet o f

2

Date : Sheet o f

Compal Electronics, Inc.

DH53F M/B LA-F991P

1

1ACustom

92 1 00Friday, February 22, 2019

1ACustom

PCW20

Inside@

PCW21

Inside@

PCW22

Inside@

ef1

0.1U_0402_25V6

2200P_0402_50V7K

5

VREF_+1.35VS_VGAP

REFIN_+1.35VS_VGAP

PRW22

@

4.7K_0402_1%

REFAD J

@

PRW25

33.2K_0402_1%

1 2

PRW23

@

3.92K_0402_1%

PRW24

@

25.5K_0402_1%

@

68.1K_0402_1%

12

PRW5

Outside@

52.3K_0402_1%

3

PQW2B

4

DMN53D0LDW-7 2N SOT363-6

Outside@

REFADJ_+1.35VS_VGAP

PRW5

+3VALW

12

Outside@

PRW21 10K_0402_1%

61

VID_+1.35VS_VGAP_R

2

5

PQW2A

DMN53D0LDW-7 2N SOT363-6

Outside@

PRW25

@

42.2K_0402_1%

PRW9

@0@

0_0402_5%

1 2

12

PCW15

@

0.1U_0402_16V7K

B+_+1.35VS_VGAP

VRAM_VDD_CTL <27>

Samesung VRAM

n,VRA M_VDD_ CTL=H igh

Whe Vboot=V ref*R2 /(R1+ R2+80 ) =2*35.7K/(10K +35.7K+80) =1.56V When,VR AM_VDD _CTL= Low Vboot=V ref*R2 /(R1+ R2+80 ) =2*(35.7K //52.3K)/(10K+(35.7K //52.3K)+80) =1.356V

D D

Micron & Hynix VRAM When,VR AM_VDD _CTL= High Vboot=2* 30.9K /(10K+ 30.9K +80) =1.51V When,VR AM_VDD _CTL= Low Vboot=2*(30 .9K// 68.1K) /(10K +(30. 9K//6 8.1K)+ 80) =1.36V

12

Rr

Outside@

PRW2

12

PCW7

Outside@

0.1U_0402_25V6

C C

REF1

B B

RBOOT

REF2

10K_0402_1%

Rref2

12

Outside@

PRW7

PCW8

35.7K_0402_1%

0.033U_0402_16V7K

Outside@

PRW7

@

30.9K_0402_1%

VREF_+1.35VS_VGAP

12

PRW22

4.99K_0402_1%

@

REFADJ_+1.35VS_VGAP_R

12

PRW23

@

3.3K_0402_1%

REFIN_+1.35VS_VGAP

12

PRW24

@

28K_0402_1%

PRW12

2.2_0402_1%

PCW18

0.1U_0402_25V6

4

FBVDDQ_PSI<27>

VID_+1.35VS_VGAP_R

12

TON_+1.35VS_VGAP_R

12

FB_VDDQ_SENSE<30>

PRW13

383K_0402_1%

+1.35VSDGPU

1.35VSDGPU_EN<27,37>

Inside@

0_0402_5%

1 2

Outside@

REFADJ_+1.35VS_VGAP

REFIN_+1.35VS_VGAP

VREF_+1.35VS_VGAP

TON_+1.35VS_VGAP

12

PRW3

@

0_0402_5%

1 2

PRW26

0_0402_5%

+3VALW

PRW27

RGND

PRW14

1 2

0_0402_5%

@

PRW19

100_0402_1%

1 2

PCW27

@

0.1U_0402_25V6

1 2

@

0_0402_5%

12

PRW20

PRW1 1K_0402_1%

1 2

PCW6

0.1U_0402_25V6

1 2

PRW10

31.6K_0402_1%

PRW6 10K_0402_1%

6

REFADJ

7

REFIN

8

VREF

9

TON

10

RGND

21

PSI_+1.35VS_VGAP

EN_+1.35VS_VGAP

VID_+1.35VS_VGAP

3

5

4

PSI

VID

OCSET/SS

VSNS11PGOOD13BOOT2

GND

12

1.35VSDGPU_PG

OCset_+1.35VS_VGAP

12

Vsense_+1.35VS_VGAP

PRW17 36.5K_0402_1%

UG1_+1.35VS_VGAP

EN

10K_0402_1%

1 2

2

14

PRW18

UGATE1

UGATE2

3

MOSFET: DFN 5X6E

S Rds(on): 5.2mohm(Typ), 7mohm(Max)

H/ L/S Rds(on): 0.8mohm(Typ), 1.05mohm(Max)

UG1_+1.35VS_VGAP

SW1_+1.35VS_VGAP

PRW4

2.2_0603_5%

12

BOOT1_+1.35VS_VGAP

PUW1

1

RT8816BGQW_WQFN20_3X3

BOOT1

20

PHASE1

19

LGATE1

18

PVCC

17

LGATE2

16

PHASE2

15

+3VS

1.35VSDGPU_PG < 27>

SW1_+1.35VS_VGAP

LG1_+1.35VS_VGAP

PVCC_+1.35VS_VGAP

BOOT1_+1..35VS_VGAP_R

12

PCW14

0.22U_0603_25V7K

LG1_+1.35VS_VGAP

PRW11

2.2_0603_5%

1 2

PCW17

12

2.2U_0402_6.3V6M

2

PLW11

EMI@

1

+

PCW23

2

@

330U_D1_2VY_R9M

FBMA-L11-201209-800LMA50T

1 2

1

+

PCW9

PCW10

2

330U_D1_2VY_R9M

12

PCW11

報報報報報報報報，，，，最最最最最最最最最最最最最最最最

GPU_B+

22U_0603_6.3V6M

12

33 0 U

12

PCW12

22U_0603_6.3V6M

B+_+1.35VS_VGAP

12

PCW4

PCW3

10U_0603_25V6M

SW1_+1.35VS_VGAP -1

12

PCW19

PCW5

0.1U_0402_25V6

10U_0603_25V6M

EMI@

13X8X4 Isat:55 A DCR:1.3m Ω (+/-5%)

PLW1

0.47UH_MHT-MHDZIR47MEM1-RT_30A_20%

1 2

12

PRW8

@EMI@

4.7_1206_5%

SNB1_+1.35VS_VGAP

12

PCW16

@EMI@

680P_0402_50V7K

fo r co st

12

PCW1

PCW2

0.1U_0402_25V6

2200P_0402_50V7K

@EMI@

PQW1

4

3

1

2

AOE6930_DFN5X6E8-10

G1

D1_2

D1_1

S1/D2

D1_3

8

+5VALW

10

S2

D2/S1_2

D2/S1_3

D2/S1_1

G2

6

7

5

9

1

+1.35V SDGPU TDC 14A Peak Current 20A OCP c urrent 30A fsw=4 00kHz

+1.35VSDGPU

PCW13

22U_0603_6.3V6M

改改改改改改改改

220U

Rocset for 75.6A

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY P ROPERTY OF COMPAL ELECTRONICS , INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY P ROPERTY OF COMPAL ELECTRONICS , INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUS TODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUS TODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUS TODY OF THE C OMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHE R THIS SHEET NOR THE INFORM ATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHE R THIS SHEET NOR THE INFORM ATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHE R THIS SHEET NOR THE INFORM ATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS , INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS , INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS , INC.

2016/02/01 2017/12/31

Compal Secret Data

2

Deciphered Date

Compal Electronics, Inc.

Title

PWR_+1.5VRAM

Size

Document Number Re v

Date : Sheet of

1

93 100Friday, February 22, 2019

1A

SKL_H 42

A

1 1

Current limit = 4.7A(min)

PR1009

10K_0402_5%

2

PC1013

12

+3VALW

1VSDGPU_PG<27>

PJ1001

@

JUMP_43X79

+3VALW

2 2

112

22U_0603_6.3V6M

B

PU1002

9

PGND

1

VIN_1.0VSDGPUP LX_1.0VSDGPUP

2

3

4

FB=0.6V

Note:Iloa d(max)=3A

8

FB

SGND

7

PG

EN

6

IN

LX

5

NC

PGND

SY8003ADFC_DFN8_2X2

EMI@

PR1007

4.7_0603_5%

EMI@

PC1008

680P_0402_50V7K

1VSDGPU_EN_R

12

PR1008

1M_0402_5%

PL1002

1UH_2.8A_30%_4X4X2_F

1 2

12

13.7K_0402_1%

FB_1.0VSDGPUP

Rdo wn

12

20K_0402_1%

Rup

PR1011

PR1012

12

PC1014

@

0.1U_0402_16V7K

12

C

PR1010

@0@

0_0402_5%

1 2

12

PC1012

68P_0402_50V8J

12

PC1009

PC1010

22U_0603_6.3V6M

VFB= 0.6 V Vout=0.6V* (1+Rup/Rdown ) =0.6V * ( 1+13.7/20) Vout= 1.0 11V

1VSDGPU_EN <27>

12

PC1011

@

22U_0603_6.3V6M

+1.0VSDGPUP

D

Choke 1uH SH00000YG00 (Common Part) (Size:3.8 x 3.8 x 1.9 mm) (DCR:20m~ 25m)

Choke: SH00000YG00 Size:4x4x2 (Common Part) Rdc=27± 20% Taiyo Rdc=20mohm(Typ), 25mohm(Max) Cyntec Rdc=27± 20% 3L Rdc=30± 20% Tai-Tech Rdc=32± 20% Chilisin Rdc=36mohm(Typ), Xmohm(Max) Maglayers

PJ1003

@

JUMP_43X79

2

+1.0VSDGPUP +1.0VSDGPU

112

E

3 3

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELE CTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELE CTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2016/11/03 2017/06/14

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

1.05VSDGPU

Size

Document Number Rev

C

DH53F M/B LA-F991P

Date: Sheet of

E

94 100Friday, February 22, 2019

1A

5

+3VS

12

D D

NVVDD1_VCC_SENSE<29>

+NVVDD1

NVVDD1_EN<27,37>

+5VS

EN_GPU

VOUT_S

+3VALW

+3VS

PCV9

@

1U_0402_6.3V6K

1 2

C C

NVVDD1_VSS_SENSE<29>

B B

A A

@0@

0_0402_5%

1 2

PRV22 10_0402_1%

PRV34

@0@

0_0402_5%

1 2

PRV35 10_0402_1%

1

2

PRV51

0_0402_5%

PRV139

10K_0402_1%

12

PRV142

0_0402_5%

@

PRV20

12

PCV14

@

12

NVVDD1_FBRTN

1 2

PRV39 10K_0402_1%

1 2

PRV46

@

0_0402_5%

+5VS

PUV8

@

TC7SH08FU_SSOP5~D

5

P

B

O

A

G

3

12

PRV140

10K_0402_1%

VGA_I2CC_SDA_PWR

VGA_I2CC_SCL_PWR

12

PRV141

0_0402_5%

@

1 2

0.1U_0402_25V6

4

61

2

NVVDD_PSI <27>

5

PQV01A

DMN53D0LDW-7 2N SOT363-6

GPU_DRVON <96>

PWMVID

PWMVID 的的的的 RC BOM

PWMVID PWMVID

請根據

請根據GPU 's conf i g

請根據請根據

4

PCV2

0.1U_0402_25V6

1 2

PRV11 10K_0402_1%

PCV4

0.1U_0402_25V6

1 2

PRV18 0_0402_5%

@

PRV25

@

0.1U_0402_25V6

0_0402_5%

1 2

PRV31

1K_0402_1%

TSENSE_GPU<96>

VGA_I2CC_SDA_PWR<27>

VGA_I2CC_SCL_PWR<27>

12

PRV40

3

4

+3VS

GPU's confi g 設定

GPU's confi g GPU 's conf i g

PQV01B

DMN53D0LDW-7 2N SOT363-6

PRV50

0_0402_5%

1 2

PRV52

@

0_0402_5%

RC BOM

RC BOMRC BOM

10K_0402_1%

12

PRV61

100K_0402_1%

1 2

NVVDD_VID<27>

設定

設定設定

NVVDD_B+

12

PRV21

@

PCV11

1 2

12

NVVDD1_FBRTN

VGA_I2CC_SDA_PWR

VGA_I2CC_SCL_PWR

@0@

0_0402_5%

1 2

12

PRV8

91K_0402_1%

PRV12 0_0402_5%

1 2

PCV6

0.015U_0402_16V7K

PCV7

@

0.1U_0402_25V6

0_0402_5%

1 2

TSENSE_GPU

EN_GPU

PSI_GPU

NVVDD1_PG

PRV70

PCV26

4700P_0402_50V7K

PCV1

@

0.1U_0402_25V6

PRV1

1 2

0_0402_5%

+5VCC

PCV5

@

0.1U_0402_25V6

1 2

12

PRV15

2.4K_0402_1%

1 2

25

26

27

28

29

30

31

32

33

12

R1

PRV44

6.19K_0402_1%

4.32K_0402_1%

20.5K_0402_1%

12

C

12

PRV3

1 2

34K_0402_1%

PRV6

4.3K_0402_1%

PRV9

3.6K_0402_1%

12

PRV13 0_0402_5%

12

COMP_GPU

EAP_GPU

24

23

PUV1

COMP

FB

FBRTN

TSENSE

SDA

UP9512QQKI_WQFN32_4X4

SCL

EN

PSI

PGOOD

GND

VID1REFADJ2REFIN3VREF4CH_OC5PWM46PWM37PWM2

VID_GPU

REFADJ_GPU

12

PRV53

R3

R4

PRV57

R2

PRV66

12

R5

PRV64

3

12

PRV16

0_0402_5%

VINMON_GPU

DAC_GPU

ADDR/FSW_GPU

IMON_GPU

22

19

21

20

EAP

DAC

IMON

ADDR

VINMON

VREF_GPU

PWM4_GPU

REFIN_GPU

CH_OC_GPU

12

16.5K_0402_1%

309_0402_1%

PRV72 22.6K_04 02_1%@

PRV71 133K_0402 _1%

12

PCV25

1 2

1U_0402_6.3V6K

PRV2

4.99K_0402_1%

3.4K_0402_1%

PRV7 442_0402_1%

1 2

1U_0402_6.3V6K

1 2

LPC_GPU

FDMF3170_REFIN

17

18

LPC

REFOUT

CSPSUM

CSNSUM

CSP1

CSP2

CSP3

CSP4

5VCC

PWM1

8

PWM3_GPU

PWM2_GPU

12

PRV69 232K_0402 _1%

PRV73 63.4K_04 02_1%

PRV4

PCV3

16

15

14

13

12

11

10

9

12

PRV14 2K_0402_1%

1 2

CSPSUM_GPU

CSNSUM_GPU

CSP1_GPU

CSP2_GPU

CSP3_GPU

+5VCC

12

PWM1_GPU

PRV54

@0@

0_0402_5%

PRV56

@0@

0_0402_5%

PRV63

12

100K_0402_1%@

+5VCC

12

2

NVVD D1 T

45A

DC Peak Current 150A OCP 200A Fsw=300kHz

12

PRV19

@

1K_0402_1%

12

@

1K_0402_1%

PRV30

PRV42

2.2_0603_5%

GPU_PWM1 <96>

GPU_PWM2 <96>

+5VCC

12

PRV29

100K_0402_1%

+5VS

12

PRV10

100K_0402_1%

4.7U_0402_6.3V6M PCV18

12

1

PRV145

@0@

0_0402_5%

12

PRV146

12

FDMF3170_IMON1 <96>

FDMF3170_IMON2 <96>

FDMF3170_REFIN <96>

12

PCV8

@

0.1U_0402_25V6

@0@

0_0402_5%

12

PCV13

@

0.1U_0402_25V6

NVVDD1_FBRTN

Security Classifi cation

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R &D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R &D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R &D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF C OMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF C OMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF C OMPAL ELECTRONICS, INC.

2016/01/06 2017/01/06

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Re v

Date : Sheet of

2

Date : Sheet of

Compal Electronics, Inc.

PWR_VGA_UP9512P

LA-F551P

1

1A

95 100Friday, February 22, 2019

1A

1

+19VB

2

PLV11

EMI@

HCB2012KF-121T50_080 5

1 2

PLV12

EMI@

HCB2012KF-121T50_080 5

1 2

PRV74

1

2

0.005_1206_1%

3

GPU_B+

4

3

PRV75

1

2

0.005_1206_1%

4

3

NVVDD_B+

4

5

A A

PRV76

30K_0402_5%

TMON1_FDMF3170

VOS1_FDMF3170

VCC1_FDMF3170

PWM1_FDMF3 170

EN1_FDMF3170

FDMF3170_IMON1

FDMF3170_REFIN1

TMON2_FDMF3170

VOS2_FDMF3170

VCC2_FDMF3170

PWM2_FDMF3 170

EN2_FDMF3170

FDMF3170_IMON2

FDMF3170_REFIN2

1 2

PRV88

30K_0402_5%

1 2

PRV82

+NVVDD1

@0@

0_0402_5%

1 2

@0@

0_0402_5%

1 2

12

PCV37

2.2U_0402_6.3V6M

1 2

PRV79 0_0402 _5%@0@

1 2

PRV84 0_0402 _5%@0@

1 2

PRV81 0_0402 _5%@0@

@0@

0_0402_5%

1 2

@0@

0_0402_5%

1 2

12

PCV54

2.2U_0402_6.3V6M

1 2

PRV89 0_0402 _5%@0@

1 2

PRV94 0_0402 _5%@0@

1 2

PRV91 0_0402 _5%@0@

PRV85

PRV92

PRV95

TSENSE_GPU

+5VS

PCV27

2.2U_0402_6.3V6M

1 2

B B

FDMF3170_IMON1<95>

C C

PCV44

2.2U_0402_6.3V6M

1 2

FDMF3170_IMON2<95>

FDMF3170_REFIN <95>

D D

1 2

PRV78

2_0402_5%

GPU_PWM1<95>GPU_DRVON <95 >

+5VS

1 2

PRV86

2_0402_5%

GPU_PWM2<95>

+5VS

NCP303150@

PRV77 0_0402_5%

1 2

CSSN_B+<36>CSSP_B+<36> CSSN_NVVDD<36>CSSP_NVVDD <36>

NVVDD_B+

Use 0603 size

1

BST1_FDMF3170

1 2

PRV80

2.2_0603_1%

PHASE1_FDMF3170

12

LX1_FDMF3170

8

PRV90

2.2_0603_1%

PHASE2_FDMF3170

12

LX2_FDMF3170

8

12

PCV40

0.1U_0603_25V7K

12

PCV57

0.1U_0603_25V7K

PCV255

EMI@

680P_0402_50V7K

PCV60

EMI@

680P_0402_50V7K

11

10

17

16

FAULT

1

4

3

2

5

20

14

15

18

19

1

4

3

2

5

20

14

15

18

19

NC

PVCC

VCC

AGND

PGND

PGND2

PWM

DISB#

IMON

REFIN

NC

PVCC

VCC

AGND

PGND

PGND2

PWM

DISB#

IMON

REFIN

16

FAULT

ZCD_EN

GL6TP

+5VS

NCP303150@

PRV87 0_0402_5%

1 2

17

ZCD_EN

PUV3 QD9619AQR1

GL6TP

N/C

PUV2

QD9619AQR1

21

11

10

N/C

21

9

13

VIN

VIN1

9

VIN

BOOT

PHASE

SW

PGND1

7

BST2_FDMF3170

13

BOOT

PHASE

SW

PGND1

7

1 2

PCV30

EMI@

12

EMI@

4.7_1206_5%

GPU1_SNB1

12

PCV47

@EMI@

12

EMI@

4.7_1206_5%

GPU1_SNB2

12

PCV31

EMI@

PRV154

PCV32

10U_0603_25V6M

2200P_0402_50V7K

0.1U_0402_25V6

12

PCV34

PCV33

10U_0603_25V6M

S COIL 0.22UH 20% MMD-1 0DZIR22MER1L 50A

PLV2

1 2

10X10X 4

at:90 A

Is DCR:0.5 5mΩ (+/- 5%)

12

PCV39

PCV35

10U_0603_25V6M

Use 0603 size

12

PCV48

0.1U_0402_25V6 2200P_0402_50V7K

@EMI@

PRV93

12

PCV50

PCV49

10U_0603_25V6M

S COIL 0.22UH 20% MMD-1 0DZIR22MER1L 50A

10X10X 4 Isat:9 0A DCR:0.5 5mΩ (+/- 5%)

12

PCV52

PCV51

10U_0603_25V6M

PLV3

1 2

12

PCV41

10U_0603_25V6M

1

12

PCV38

10U_0603_25V6M

+

2

NVVDD_B+

+

PCV36

PCV249

2

33U_25V_M

@

+NVVDD1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

2

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2016/01/06 2017/01/06

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Num ber Re v

Date : Sheet o f

4

Date : Sheet o f

Compal Electronics, Inc.

PWR_+NVVDD1

LA-F551P

1A

96 100Friday, February 22, 2019

5

1A

5

D D

4

N18P -G0 +NVVDD 560uF X 6 22uF_0603 X 15 10uF_0402X 34 1uF_0201 X 28

3

2

1

+NVVDD1

1

+

PCV135

2

@

560U_D2_2VM_R4.5M

C C

12

PCV251

1U_0201_6.3V6M

12

PCV159

B B

1U_0201_6.3V6M

12

PCV155

1U_0201_6.3V6M

1

+

PCV137

PCV136

2

560U_D2_2VM_R4.5M

12

PCV141

PCV140

1U_0201_6.3V6M

12

PCV160

PCV161

1U_0201_6.3V6M

12

PCV157

PCV156

1U_0201_6.3V6M

1

+

PCV138

PCV139

PCV272

2

560U_D2_2VM_R4.5M

12

PCV142

PCV143

1U_0201_6.3V6M

12

PCV258

PCV149

1U_0201_6.3V6M

12

PCV162

PCV158

1U_0201_6.3V6M

12

PCV145

PCV144

1U_0201_6.3V6M

12

PCV151

PCV150

1U_0201_6.3V6M

12

PCV164

PCV163

1U_0201_6.3V6M

12

PCV146

PCV152

PCV165

PCV148

PCV147

1U_0201_6.3V6M

12

PCV153

PCV154

1U_0201_6.3V6M

12

PCV215

10U_0402_6.3V6M

12

PCV235

10U_0402_6.3V6M

12

PCV225

10U_0402_6.3V6M

12

PCV283

10U_0402_6.3V6M

12

PCV217

PCV216

10U_0402_6.3V6M

12

PCV279

PCV236

10U_0402_6.3V6M

12

PCV226

PCV227

10U_0402_6.3V6M

12

PCV280

PCV237

10U_0402_6.3V6M

12

PCV218

10U_0402_6.3V6M

12

PCV282

10U_0402_6.3V6M

12

PCV229

10U_0402_6.3V6M

12

PCV276

10U_0402_6.3V6M

12

PCV220

PCV219

12

PCV221

PCV222

10U_0402_6.3V6M

12

PCV287

PCV250

10U_0402_6.3V6M

12

PCV228

PCV230

10U_0402_6.3V6M

PCV223

10U_0402_6.3V6M

12

PCV281

PCV275

10U_0402_6.3V6M

12

PCV232

PCV231

10U_0402_6.3V6M

+NVVDD1+NVVDD1

12

PCV224

10U_0402_6.3V6M

12

PCV277

PCV284

10U_0402_6.3V6M

12

PCV234

PCV233

10U_0402_6.3V6M

12

PCV243

22U_0603_6.3V6M

12

PCV254

22U_0603_6.3V6M

12

PCV244

PCV245

22U_0603_6.3V6M

12

PCV253

PCV252

22U_0603_6.3V6M

12

PCV247

PCV246

22U_0603_6.3V6M

12

PCV257

PCV256

22U_0603_6.3V6M

12

PCV248

PCV358

22U_0603_6.3V6M

12

PCV359

PCV360

PCV361

22U_0603_6.3V6M

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2016/01/06 2017/01/06

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document N umber R ev

Date : Sheet o f

Compal Electronics, Inc.

PWR_VGA DECOUPLING

LA-F551P

1

97 1 00Friday, February 22, 2019

1A

5

D D

C C

4

3

2

1

Reserve Page

B B

A A

Security Cl assification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2017/11/23 2017/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document N umber Re v

Date: Sheet o f

2

Date: Sheet o f

Compal Electronics, Inc.

N18E-GDDR6_D

EH5VF M/B LA-H501P

1

1A

98 100Friday, February 22, 2019

1A

5

D D

C C

4

3

2

1

Reserve Page

B B

A A

Security Cl assification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2017/11/23 2017/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document N umber Re v

Date: Sheet o f

2

Date: Sheet o f

Compal Electronics, Inc.

N18E-GDDR6_D

EH5VF M/B LA-H501P

1

1A

99 100Friday, February 22, 2019

1A

5

4

3

2

1

Version change list (P.I.R. List) Page 1 of 1

for PWR

Reason for change PG# Modify List Date PhaseFixed IssueItem

change PR1009 from 100K_0402_5% (SD028100380) to 10K_0402_5% (SD028100280)

D D

01

Design Update For EA Turning and HW

02

sequence

solution changeDesign Update

03

C C

04

Design Update

For CPU transient

05

93, 94 95, 97 89, 92

83, 85 90, 91

89, 92

84

change PG pull high from +3VS to +3VALW change PRW1 from 20K_0402_1% (SD034200280) to 1K_0402_1% (SD034100180) Change the PCW27 from pop to un-pop, and . PCW27.2 net name change from +1.35VSDGPU to Vsense_+1.35VS_VGAP. unpop PCV135 Change the PUV8, PCV9 from pop to un-pop. Add location PRV51 0_0402_5% (SD028000080), and pop.

Change the PCW21, PCW22 From 4700P_0402_50V (SE074472K80) to 2200P_0402_50V(SE074222K80).

e

lete PL1111 (HCB2012KF-121T50_0805)

D

Change the PQB2,PQM2 from AON7506 (SB000010A00) to EMB12N03V (SB00001HV00) update location PRG5 PRA3 to PUG1 PUA1 PLZ1,PLG1,PLZ2,PLZ3,PLZ4 change to common part P/N (SH00001EE00) pop PQZ2, PQZ4 unpop PQZ1, PQZ3

Change PRM10, PRM8, PRV82, PRV85, PRV92, PRV95, PRV79, PRV81, PRV84, PRV89, PRV91, PRV94, PRV54, PRV56, PRV70, PRV145, PRV146, PRZ72, PRZ73, PRZ25, PRZ30, PRZ32, PRZ18, PRZ9, PRZ11, PRZ24, PRZ27,PRV20, PRV34

change PRZ12 from 1.78K_0402_1%(SD00000WY80) to 1.62K_0402_1%(SD000003380) change PRZ14 from 31.6K_0402_1%(SD034316280) to 28K_0402_1%(SD034280280) change PCZ24 from 470P_0402_50V8J(SE071471J80) to 220P_0402_50V8J(SE082221J80) change PRZ51 from 84.5K_0603_1%(SD014845280) to 100K_0603_1%(SD014100380) PRZ61=110k ohm @H82, PRZ61=102k ohm @H62 PRZ35=25.5k ohm @H82, PRZ35=28k ohm @H62 unpop PCZ101, PCZ103, PCG102 pop PCZ176 un pop PCZ120, PCZ104, PCZ105, PCZ118, PCZ111, PCZ108, PCZ126, PCZ124 for H82 un pop PCZ120, PCZ104, CZ105, PCZ118, PCZ111, PCZ108, PCZ126, PCZ124, PCZ123, PCZ127, PCZ107, PCZ113, PCZ116, PCZ114 for H62

Change the PL501 1.5uH to common part

Change the PCZ47, PCZ48, PCZ65, PCV36, PCV249 from 33U_25V_NC_6.3X4.5 (SF000007200) to 33U_25V_M (SF000007700) Chnage the PRZ43 from 12.1K_0402_1% (SD034121280) to 12K_0402_1% (SD034120280)

/14

11

11/16

11/160 ohm to R-shortDesign Update

11/19

12/3solution changeDesign Update

A

06

07

08

Design Update solution change

B B

A A

solution changeDesign Update

5

87

83, 97

87, 93, 94

unpop PC1811 0.47U_0402_6.3V6K (SE124474K80)

reserve PDB2 for dead battery

Change PR1010, PRW9, PR1801, PR2501 from 0ohm to r-short

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

Issued Date

Compal Secret Data

2017/10/30 2018/10/30

Compal Secret Data

Deciphered Date

2

12/12

B

B12/18pop PCV149~PCV158, PCV162~PCV165, PCV258 (1U_0201_6.3V6M)

12/18 B

Compal Electronics, Inc.

Title

PIR

ze Document Number Re v

Size Document Number Re v

Si

Custom

EH5VF M/B LA-H501P

Date : Sheet o f

1

100 100Friday, February 22, 2019

1A

Acer Nitro AN515-54 Schematic

Specifications and Main Features

Frequently Asked Questions

User Manual