Acer Nitro AN515-52 Schematic

A

I

B

I

C

I

D

I

E

1

Compal

15

V

2

V

17

Vxl

*

3

Vxl

DH

/

DH

/

5

/

7

/

DH
DH

5

VF

7

VF

73

F

F

CoffeeLake

53

Intel

Nvidia

Confidential

MB

17

N

Schematic

H

P

-

G

0

/

G

1

Document

1

2

3

LA

4

Security

THIS

AND

DEPARTMENT

A

B

MAY

-

F

Rev

:

2018.02

Classification

Issued

Date

SHEETOFENGINEERING

TRADE

SECRET

EXCEPT

USED

BE

BY

INFORMATION

AS

OR

DISCLOSED

DRAWING

.

THIS

AUTHORIZEDBYCOMPAL

TO

ANY

951

lA

22

.

/

/

2017

18

12

IS

PROPRIETARY

NOT

MAY

ELECTRONICS

PARTY

PROPERTYOFCOMPAL

BE

TRANSFERED

WITHOUT

C

SHEET

THIRD

THE

P

Compal

,

INC

PRIOR

.

NEITFER

WRITTEN

Secret

Deciphered

FROM

THIS

ELECTRONICS

THE

CUSTODY

SHEET

CONSENT

Data

OF

Date

NOR

COMPAL

OF

THE

2018/09/01

,

INC

CONTAINS

.

AND

COMPETENT

THE

DIVISION

INFORMATIONITCONTAINS

,

ELECTRONICS

CONFIDENTIAL

INC

.

D

4

Cnmpnl

Title

Cover

Document

OF

R8D

Size

Sustorr

Date

:

Electronics

Sheet

Number

DH

M/B

5

VF

Thursday,February

LA

F

-

,

2018

22

591PR01

,

Sheet

I

E

Inc

.

Rev

1.0

67

of

1

BOM Structure Table

BOM Option Table

SATA HD D W RED RIVER

SATA HD D WO RE DRIVER
NV N17P -G0(1050 )
NV N17P -G1(1050 TI)
i5 CPU
i7 CPU

BOM Str ucture

VX15@

SATARD @
SATANR D@
G0@
G1@
i5@
i7@

+VCCIO
+VCC_SA
+1.8VSDGPU_AON
+1.8VSDGPU_MAIN

+1.8VGA_CORE
+1.35VSDGPU

X76730BOL51 SAMSUN G1280
X76730BOL52 HYNLX1 280
X76730BOL53 SAMSUN G2560
X76730BOL54 HYNIX2 560
X76730BOL55 MICRON 2560

I5QP89 PG1 4G 32HDMI

I78750 PG1 4G 32HDMI

+1.8VS

UQ2

+19VB -> +19V_CPU

LX1

RH92

RH94

+1.05VALW_PRIM

+1.05VALW_PCH

RH102

RH103

RH105

PCH

PCH

PCH

A

BIOS ver: V0 .02W1
EC : ve r: V002AT04

1 1

AC modeDH5VF_EVT Power Sequence

B

C

D

E

Plug in

+3VLP

EC_ON

+5VAL W

ON/OFF BTN#

+3VAL W

+1.05V ALW

EC_RSM RST#

PBTN_O UT#

PM_SLP _S4#

PM_SLP _S3#

2

3 3

SYSON

+1.05V _VCCST

+1.2V_ VDDQ

+2.5V S

SUSP#

+1.05V S_VCCST G

+5VS

+3VS

+1.8V S

EC_VCC ST_PG

SM_PG_ CTRL

+0.6VS _VTT

VR_ON

+VCC_S A

+VCC_C ORE

+VCC_G T

PCH_PW ROK

SYS_PW ROK

PLT_RS T#

330.8ms

→

333.3ms

→

→

→

2.439ms

92.03ms

94.88ms

29.19ms

→

→

174.6ms

20.1ms

← →

→
→

Power On

19.18ms

19.22ms

72.1us

→

275.9us

→

692.9us

→
→

910.1us

→

12.7ms

8.378us

→
→

→

412us

→
→

→
→

→

877.7us

630.4us

25.34ms

25.35ms

25.36ms

25.19ms

→
→

→
→

→
→

→

1.759ms

173.0ms

NA

12.42ms

150.3ms

152.3ms 318.7us

→

→

S3 S3 Resume

13.01us

55.47us

→

618.5us

→

8.679ms

→

347.6us

→

0us

→

0us 13.97ms

→

3.819ms

→

26.91us

51.25us

→

87.75us

→

NA

→

47.39us

→

61.95us

→

→

67.04ms

8.502us

→

906.0us

→

→

424.9us

→
→

→
→

→

656.1us

25.25ms

25.25ms

25.26ms

→
→

→
→

→
→

25.59ms

1.757ms

167.1ms

NA

12.18ms

150.6ms

151.8ms

Power Off

100.5us

152.8us

→

88.37us

→

367.6us

→
→

13us

→

→

686.0us

→

→

0us

→

2.034ms

→

27.06us

→

48.00us

→

112.0us

→

NA

47.83us

→

62.37us

→

2.266ms

68.53us

11.65ms

446.2us

293.7us

→

+3VLP

EC_ON

+5VAL W

ON/OFF BTN#

+3VAL W

+1.05V ALW

EC_RSM RST#

PBTN_O UT#

PM_SLP _S4#

PM_SLP _S3#

SYSON

+1.05V _VCCST

+1.2V_ VDDQ

+2.5V S

SUSP#

+1.05V S_VCCST G

+5VS

+3VS

+1.8V S

EC_VCC ST_PG

SM_PG_ CTRL

+0.6VS _VTT

VR_ON

+VCC_S A

+VCC_C ORE

+VCC_G T

PCH_PW ROK

SYS_PW ROK

PLT_RS T#

2

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS T HE PROPRIETARY PR OPERTY OF COMPAL ELECTRONICS, IN C. AND C ONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS T HE PROPRIETARY PR OPERTY OF COMPAL ELECTRONICS, IN C. AND C ONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS T HE PROPRIETARY PR OPERTY OF COMPAL ELECTRONICS, IN C. AND C ONTAINS CONFIDENTIAL
AND TRADE SECRET INFORM ATION. THIS SHEE T MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D

AND TRADE SECRET INFORM ATION. THIS SHEE T MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D

AND TRADE SECRET INFORM ATION. THIS SHEE T MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D
DEPARTMENT EXC EPT AS AUTHORIZE D BY COMPAL ELECT RONICS, INC. NEIT HER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXC EPT AS AUTHORIZE D BY COMPAL ELECT RONICS, INC. NEIT HER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXC EPT AS AUTHORIZE D BY COMPAL ELECT RONICS, INC. NEIT HER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

C

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2017/12/18 2018/09/01

2017/12/18 2018/09/01

2017/12/18 2018/09/01

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Power Sequence

Power Sequence

Power Sequence

Size

Size

Size

Document Number Re v

Document Number Re v

Document Number Re v

Custom

Custom

Custom

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

Date : Sheet of

Date : Sheet of

Date : Sheet of

E

5 67Thursday, February 22, 2018

5 67Thursday, February 22, 2018

5 67Thursday, February 22, 2018

1.0

1.0

1.0

5

PCH_SMBCLK

PCH_SMBD ATA

PCH_SML0CLK

D

Skylake-H

PCH

PCH_SML 0DATA

PCH_SML1CLK

PCH_SML 1DATA

499

499

2.2K

2.2K

2.2K

2.2K

+3VA LW_P CH _PRIM

(QH7)
2N7002D W

+3VA LW_P CH _PRIM

+3VA LW_P CH _PRIM

(RH189/RH19 0)
R-short

2.2K

2.2K

EC_SM B_CK1

EC_SMB_DA1

KB9022

EC_SM B_CK2

C C

EC_SMB_DA2

+3VL P_ EC

100 ohm

100 ohm

0 ohm

0 ohm

+3V S

EC_SMB_CK1-1

EC_SMB_DA1-1

EC_SMB_CK 1_CHGR

EC_SMB_D A1_CHGR

4

D_CK_SC LK

D_CK_SDATA

EC_SM B_CK2

EC_SMB_DA2

BATTERY

CONN

Charger

2.2K

2.2K

+3V S

SO-DIMM A & B

G-Sensor

+1.8 VSDG PU _MAIN

(QV2)
PJT138KA

(co-lay)

2N7002
R-Shor t

+3V S

(QF1)
2N7002D W

3

VGA_I2CS_SCL

VGA_I2CS_SDA

179F_SMB_CK2

179F_SMB_DA2

TMS_SMB_CLK

TMS_SM B_DATA

1.8K

1.8K

USB CC EJ179F

2.2K

2.2K

THERMAL SENSOR

+1.8 VSDG PU _AON

N17P-G0
N17P-G1

+3V S

2

1

2K

2K

I2CB_SCL

I2CB_SDA

+1.8 VSDG PU _AON

2K

2K

I2CC_SCL

I2CC_SDA

+1.8 VSDG PU _AON

D

B

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE P ROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. A ND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE P ROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. A ND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE P ROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. A ND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL E LECTRONICS, INC. N EITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL E LECTRONICS, INC. N EITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL E LECTRONICS, INC. N EITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2017/12/18 2018/09/01

2017/12/18 2018/09/01

2017/12/18 2018/09/01

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size

Size

Size

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

N17E-GDDR5_D

N17E-GDDR5_D

N17E-GDDR5_D

Document Number Re v

Document Number Re v

Document Number Re v

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

1

6 67Thursday, February 22, 2018

6 67Thursday, February 22, 2018

6 67Thursday, February 22, 2018

1.0

1.0

1.0

of

of

of

B

A

B

C

D

E

CO-LAY FOR VGA OUTPUT

1 2

GPU_ED P_TXP0<27>
GPU_ED P_TXN0<27>
GPU_ED P_TXP1<27>
GPU_ED P_TXN1<27>
GPU_ED P_TXP2<27>
GPU_ED P_TXN2<27>

1

GPU_ED P_TXP3<27>
GPU_ED P_TXN3<27>

GPU_ED P_AUXP<27>
GPU_ED P_AUXN<27>

RG183 0_0201 _5%@

1 2

RG184 0_0201 _5%@

1

RG185 0_0201 _5%@
RG186 0_0201 _5%

RG187 0_0201 _5%@
RG188 0_0201 _5%@

RG189 0_0201 _5%@
RG190 0_0201 _5%@

2

1 2

@

1

2

1 2

1 2
1 2

1 2

RG191 0_0201 _5%@

1 2

RG192 0_0201 _5%@

EDP_AU XP
EDP_AU XN

1

UC1D

K36

DDI1_TXP_0

K37

2 2

Coffee Lake-H CPU SKU

3

UC1

I5@

CFL-H 2.3 G BGA

SA0000BPJ40

UC1

I7@

CFL-H 2.2 G BGA

SA0000BPZ40

DDI1_TXN_0

J35

DDI1_TXP_1

J34

DDI1_TXN_1

H37

DDI1_TXP_2

H36

DDI1_TXN_2

J37

DDI1_TXP_3

J38

DDI1_TXN_3

D27

DDI1_AUXP

E27

DDI1_AUXN

H34

DDI2_TXP_0

H33

DDI2_TXN_0

F37

DDI2_TXP_1

G38

DDI2_TXN_1

F34

DDI2_TXP_2

F35

DDI2_TXN_2

E37

DDI2_TXP_3

E36

DDI2_TXN_3

F26

DDI2_AUXP

E26

DDI2_AUXN

C34

DDI3_TXP_0

D34

DDI3_TXN_0

B36

DDI3_TXP_1

B34

DDI3_TXN_1

F33

DDI3_TXP_2

E33

DDI3_TXN_2

C33

DDI3_TXP_3

B33

DDI3_TXN_3

A27

DDI3_AUXP

B27

DDI3_AUXN

CFL-H_B GA1440

CFL-H

EDP_TXP_0

EDP_TXN_0
EDP_TXP_1
EDP_TXN_1

EDP_TXP_2
EDP_TXN_2
EDP_TXP_3
EDP_TXN_3

EDP_AUXP

EDP_AUXN

EDP_DISP_UTIL

DISP_RCOMP

PROC_AUDIO_CLK

PROC_AUDIO_SDI

PROC_AUDIO_SDO

4 of 13

D29
E29
F28
E28

A29
B29
C28

B28

C26
B26

A33

D37

G27
G25
G29

EDP_TX P0
EDP_TX N0
EDP_TX P1
EDP_TX N1
EDP_TX P2
EDP_TX N2

EDP_TX P3

EDP_TX N3

EDP_AU XP
EDP_AU XN

DP_RCO MP

Trace Width/Space: 15 mil/ 20 mil
Max Trace Length: 600 mil

CPU_DISP A_SDI

RC1 24.9_04 02_1%

RC2 20_040 2_5%

1 2

2

follow CRB

1

EDP_TX P0 <33>
EDP_TX N0 <33>

EDP_TX P1 <33>
EDP_TX N1 <33>
EDP_TX P2 <33>
EDP_TX N2 <33>
EDP_TX P3 <33>
EDP_TX N3 <33>

EDP_AU XP <3 3>
EDP_AU XN <33>

+VCCIO

CPU_DISP A_BCLK_R
CPU_DISP A_SDO_R
CPU_DISP A_SDI_R

eDP

CPU_DISP A_BCLK_R <19>
CPU_DISP A_SDO_R <19>

CPU_DISP A_SDI_R <19>

Cannon Lake PCH SKU

UH1

QNDQ@

CNP-H_BG A874

SA0000BVP10

3

NV N17P SKU

4 4

UV1

G0@

N17P-G0 -A1

SA0000A0540

UV1

G1@

N17P-G1 -A1

SA0000A0660

A

Security Classification

Security Classification

Security Classification

2017/12 /18 2018/09 /01

2017/12 /18 2018/09 /01

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

B

2017/12 /18 2018/09 /01

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

CFL-H(1/8)DDI/eDP

CFL-H(1/8)DDI/eDP

CFL-H(1/8)DDI/eDP

Size Document Number Re v

Size Document Number Re v

Size Document Number R ev

Custom

Custom

Custom

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

Dat e: Sheet

Dat e: Sheet of

D

Dat e: Sheet of

7 67Thursday, Febru ary 22, 2018

o f

7 67Thursday, Febru ary 22, 2018

7 67Thursday, Febru ary 22, 2018

E

1.0

1.0

1.0

A

B

C

D

E

CHANNEL-A

Interleaved Memory

UC1A

1

2 2

3

DDR_A_ D[0..63]<23>

For ECC DIMM

DDR_A_ D0
DDR_A_ D1
DDR_A_ D2
DDR_A_ D3
DDR_A_ D4
DDR_A_ D5
DDR_A_ D6
DDR_A_ D7

DDR_A_ D8

DDR_A_ D9

DDR_A_ D10

DDR_A_ D11

DDR_A_ D12
DDR_A_ D13
DDR_A_ D14

DDR_A_ D15
DDR_A_ D16

DDR_A_ D17

DDR_A_ D18
DDR_A_ D19

DDR_A_ D20
DDR_A_ D21

DDR_A_ D22

DDR_A_ D23
DDR_A_ D24

DDR_A_ D25
DDR_A_ D26
DDR_A_ D27
DDR_A_ D28
DDR_A_ D29
DDR_A_ D30
DDR_A_ D31
DDR_A_ D32
DDR_A_ D33
DDR_A_ D34
DDR_A_ D35
DDR_A_ D36
DDR_A_ D37
DDR_A_ D38
DDR_A_ D39
DDR_A_ D40
DDR_A_ D41
DDR_A_ D42
DDR_A_ D43
DDR_A_ D44
DDR_A_ D45
DDR_A_ D46
DDR_A_ D47
DDR_A_ D48
DDR_A_ D49
DDR_A_ D50
DDR_A_ D51
DDR_A_ D52
DDR_A_ D53
DDR_A_ D54
DDR_A_ D55

DDR_A_ D56
DDR_A_ D57

DDR_A_ D58

DDR_A_ D59

DDR_A_ D60
DDR_A_ D61
DDR_A_ D62
DDR_A_ D63

DDR4(IL)/LP3-DDR4(NIL) LP3/DDR4

BR6

DDR0_DQ_0/DDR0_DQ_0

BT6

DDR0_DQ_1/DDR0_DQ_1

BP3

DDR0_DQ_2/DDR0_DQ_2

BR3

DDR0_DQ_3/DDR0_DQ_3

BN5

DDR0_DQ_4/DDR0_DQ_4

BP6

DDR0_DQ_5/DDR0_DQ_5

BP2

DDR0_DQ_6/DDR0_DQ_6

BN3

DDR0_DQ_7/DDR0_DQ_7

BL4

DDR0_DQ_8/DDR0_DQ_8

BL5

DDR0_DQ_9/DDR0_DQ_9

BL2

DDR0_DQ_10/DDR0_DQ_10

BM1

DDR0_DQ_11/DDR0_DQ_11

BK4

DDR0_DQ_12/DDR0_DQ_12

BK5

DDR0_DQ_13/DDR0_DQ_13

BK1

DDR0_DQ_14/DDR0_DQ_14

BK2

DDR0_DQ_15/DDR0_DQ_15

BG4

DDR0_DQ_16/DDR0_DQ_32

BG5

DDR0_DQ_17/DDR0_DQ_33

BF4

DDR0_DQ_18/DDR0_DQ_34

BF5

DDR0_DQ_19/DDR0_DQ_35

BG2

DDR0_DQ_20/DDR0_DQ_36

BG1

DDR0_DQ_21/DDR0_DQ_37

BF1

DDR0_DQ_22/DDR0_DQ_38

BF2

DDR0_DQ_23/DDR0_DQ_39

BD2

DDR0_DQ_24/DDR0_DQ_40

BD1

DDR0_DQ_25/DDR0_DQ_41

BC4

DDR0_DQ_26/DDR0_DQ_42

BC5

DDR0_DQ_27/DDR0_DQ_43

BD5

DDR0_DQ_28/DDR0_DQ_44

BD4

DDR0_DQ_29/DDR0_DQ_45

BC1

DDR0_DQ_30/DDR0_DQ_46

BC2

DDR0_DQ_31/DDR0_DQ_47

AB1

DDR0_DQ_32/DDR1_DQ_0

AB2

DDR0_DQ_33/DDR1_DQ_1

AA4

DDR0_DQ_34/DDR1_DQ_2

AA5

DDR0_DQ_35/DDR1_DQ_3

AB5

DDR0_DQ_36/DDR1_DQ_4

AB4

DDR0_DQ_37/DDR1_DQ_5

AA2

DDR0_DQ_38/DDR1_DQ_6

AA1

DDR0_DQ_39/DDR1_DQ_7

V5

DDR0_DQ_40/DDR1_DQ_8

V2

DDR0_DQ_41/DDR1_DQ_9

U1

DDR0_DQ_42/DDR1_DQ_10

U2

DDR0_DQ_43/DDR1_DQ_11

V1

DDR0_DQ_44/DDR1_DQ_12

V4

DDR0_DQ_45/DDR1_DQ_13

U5

DDR0_DQ_46/DDR1_DQ_14

U4

DDR0_DQ_47/DDR1_DQ_15

R2

DDR0_DQ_48/DDR1_DQ_32

P5

DDR0_DQ_49/DDR1_DQ_33

R4

DDR0_DQ_50/DDR1_DQ_34

P4

DDR0_DQ_51/DDR1_DQ_35

R5

DDR0_DQ_52/DDR1_DQ_36

P2

DDR0_DQ_53/DDR1_DQ_37

R1

DDR0_DQ_54/DDR1_DQ_38

P1

DDR0_DQ_55/DDR1_DQ_39

M4

DDR0_DQ_56/DDR1_DQ_40

M1

DDR0_DQ_57/DDR1_DQ_41

L4

DDR0_DQ_58/DDR1_DQ_42

L2

DDR0_DQ_59/DDR1_DQ_43

M5

DDR0_DQ_60/DDR1_DQ_44

M2

DDR0_DQ_61/DDR1_DQ_45

L5

DDR0_DQ_62/DDR1_DQ_46

L1

DDR0_DQ_63/DDR1_DQ_47

LP3/DDR4

BA2

NC/DDR0_ECC_0

BA1

NC/DDR0_ECC_1

AY4

NC/DDR0_ECC_2

AY5

NC/DDR0_ECC_3

BA5

NC/DDR0_ECC_4

BA4

NC/DDR0_ECC_5

AY1

NC/DDR0_ECC_6

AY2

NC/DDR0_ECC_7

CFL-H_B GA1440

CFL-H

DDR CHANNEL A

DDR0_CKP_0/DDR0_CKP_0
DDR0_CKN_0/DDR0_CKN_0
DDR0_CKP_1/DDR0_CKP_1
DDR0_CKN_1/DDR0_CKN_1

NC/DDR0_CKP_2
NC/DDR0_CKN_2
NC/DDR0_CKP_3
NC/DDR0_CKN_3

DDR0_CKE_0/DDR0_CKE_0
DDR0_CKE_1/DDR0_CKE_1
DDR0_CKE_2/DDR0_CKE_2
DDR0_CKE_3/DDR0_CKE_3

DDR0_CS#_0/DDR0_CS#_0
DDR0_CS#_1/DDR0_CS#_1

NC/DDR0_CS#_2
NC/DDR0_CS#_3

DDR0_ODT_0/DDR0_ODT_0

NC/DDR0_ODT_1
NC/DDR0_ODT_2
NC/DDR0_ODT_3

DDR0_CAB_4/DDR0_BA_0
DDR0_CAB_6/DDR0_BA_1

DDR0_CAA_5/DDR0_BG_0

DDR0_CAB_3/DDR0_MA_16
DDR0_CAB_2/DDR0_MA_14
DDR0_CAB_1/DDR0_MA_15

DDR0_CAB_9/DDR0_MA_0

DDR0_CAB_8/DDR0_MA_1
DDR0_CAB_5/DDR0_MA_2

NC/DDR0_MA_3

NC/DDR0_MA_4
DDR0_CAA_0/DDR0_MA_5
DDR0_CAA_2/DDR0_MA_6
DDR0_CAA_4/DDR0_MA_7
DDR0_CAA_3/DDR0_MA_8
DDR0_CAA_1/DDR0_MA_9

DDR0_CAB_7/DDR0_MA_10
DDR0_CAA_7/DDR0_MA_11
DDR0_CAA_6/DDR0_MA_12
DDR0_CAB_0/DDR0_MA_13

DDR0_CAA_9/DDR0_BG_1
DDR0_CAA_8/DDR0_ACT#

NC/DDR0_PAR

NC/DDR0_ALERT#

DDR4(IL)/LP3-DDR4(NIL)

DDR0_DQSN_0/DDR0_DQSN_0
DDR0_DQSN_1/DDR0_DQSN_1
DDR0_DQSN_2/DDR0_DQSN_4
DDR0_DQSN_3/DDR0_DQSN_5
DDR0_DQSN_4/DDR1_DQSN_0
DDR0_DQSN_5/DDR1_DQSN_1
DDR0_DQSN_6/DDR1_DQSN_4
DDR0_DQSN_7/DDR1_DQSN_5

DDR0_DQSP_0/DDR0_DQSP_0
DDR0_DQSP_1/DDR0_DQSP_1
DDR0_DQSP_2/DDR0_DQSP_4
DDR0_DQSP_3/DDR0_DQSP_5
DDR0_DQSP_4/DDR1_DQSP_0
DDR0_DQSP_5/DDR1_DQSP_1
DDR0_DQSP_6/DDR1_DQSP_4
DDR0_DQSP_7/DDR1_DQSP_5

DDR0_DQSP_8/DDR0_DQSP_8

DDR0_DQSN_8/DDR0_DQSN_8

1 OF 13

AG1
AG2
AK2
AK1
AL3
AK3
AL2
AL1

AT1
AT2
AT3
AT5

AD5
AE2
AD2
AE5

AD3
AE4
AE1
AD4

AH5
AH1
AU1

AH4
AG4
AD1

AH3

AP4
AN4

AP5
AP2
AP1
AP3
AN1
AN3
AT4
AH2
AN2
AU4
AE3
AU2
AU3

AG3
AU5

BR5
BL3
BG3
BD3
AA3
U3
P3
L3

BP5
BK3
BF3
BC3
AB3
V3
R3
M3

AY3
BA3

DDR_A_ CLK0
DDR_A_ CLK#0
DDR_A_ CLK1
DDR_A_ CLK#1

DDR_A_ CKE0
DDR_A_ CKE1

DDR_A_ CS#0
DDR_A_ CS#1

DDR_A_ ODT0
DDR_A_ ODT1

DDR_A_ BA0
DDR_A_ BA1
DDR_A_ BG0

DDR_A_ MA16_RAS#
DDR_A_ MA14_WE #
DDR_A_ MA15_CAS#

DDR_A_ MA0
DDR_A_ MA1
DDR_A_ MA2
DDR_A_ MA3
DDR_A_ MA4
DDR_A_ MA5
DDR_A_ MA6
DDR_A_ MA7
DDR_A_ MA8
DDR_A_ MA9
DDR_A_ MA10
DDR_A_ MA11
DDR_A_ MA12
DDR_A_ MA13
DDR_A_ BG1
DDR_A_ ACT#

DDR_A_ PAR
DDR_A_ ALERT#

DDR_A_ DQS#0
DDR_A_ DQS#1
DDR_A_ DQS#2
DDR_A_ DQS#3
DDR_A_ DQS#4
DDR_A_ DQS#5
DDR_A_ DQS#6
DDR_A_ DQS#7

DDR_A_ DQS0
DDR_A_ DQS1
DDR_A_ DQS2
DDR_A_ DQS3
DDR_A_ DQS4
DDR_A_ DQS5

DDR_A_ DQS6

DDR_A_ DQS7

DDR_A_ CLK0 <23>
DDR_A_ CLK#0 <23>
DDR_A_ CLK1 <23>
DDR_A_ CLK#1 <23>

DDR_A_ CKE0 <23>
DDR_A_ CKE1 <23>

DDR_A_ CS#0 <23>
DDR_A_ CS#1 <23>

DDR_A_ ODT0 <23>
DDR_A_ ODT1 <23>

DDR_A_ BA0 < 23>
DDR_A_ BA1 < 23>
DDR_A_ BG0 < 23>

DDR_A_ MA16_RAS# <23 >
DDR_A_ MA14_WE # <23>
DDR_A_ MA15_CAS# <23 >

DDR_A_ MA0 <23 >
DDR_A_ MA1 <23 >
DDR_A_ MA2 <23 >
DDR_A_ MA3 <23 >
DDR_A_ MA4 <23 >
DDR_A_ MA5 <23 >
DDR_A_ MA6 <23 >
DDR_A_ MA7 <23 >
DDR_A_ MA8 <23 >
DDR_A_ MA9 <23 >
DDR_A_ MA10 <2 3>
DDR_A_ MA11 <2 3>
DDR_A_ MA12 <2 3>
DDR_A_ MA13 <2 3>
DDR_A_ BG1 < 23>
DDR_A_ ACT# <23>

DDR_A_ PAR <23>
DDR_A_ ALERT# <23>

DDR_A_ DQS#0 <23>
DDR_A_ DQS#1 <23>
DDR_A_ DQS#2 <23>
DDR_A_ DQS#3 <23>
DDR_A_ DQS#4 <23>
DDR_A_ DQS#5 <23>
DDR_A_ DQS#6 <23>
DDR_A_ DQS#7 <23>

DDR_A_ DQS0 <23>
DDR_A_ DQS1 <23>
DDR_A_ DQS2 <23>
DDR_A_ DQS3 <23>
DDR_A_ DQS4 <23>
DDR_A_ DQS5 <23>
DDR_A_ DQS6 <23>
DDR_A_ DQS7 <23>

For ECC DIMM

1

3

4 4

Security Classification

Security Classification

Security Classification

2017/12 /18 2018/09 /01

2017/12 /18 2018/09 /01

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

A

B

2017/12 /18 2018/09 /01

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

CFL-H(2/8)DIMMA

CFL-H(2/8)DIMMA

CFL-H(2/8)DIMMA

Size Document Number R ev

Size Document Number R ev

Size Document Number R ev

Custom

Custom

Custom

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

Dat e: Sheet of

Dat e: Sheet of

D

Dat e: Sheet of

8 67Thursday, Febru ary 22, 2018

8 67Thursday, Febru ary 22, 2018

8 67Thursday, Febru ary 22, 2018

E

1.0

1.0

1.0

A

B

C

D

E

CHANNEL-B

Interleaved Memory

1

2 2

3

DDR_B_ D[0..63]<24>

For ECC DIMM

DDR_B_ D0
DDR_B_ D1
DDR_B_ D2
DDR_B_ D3

DDR_B_ D4
DDR_B_ D5
DDR_B_ D6

DDR_B_ D7
DDR_B_ D8
DDR_B_ D9
DDR_B_ D10
DDR_B_ D11
DDR_B_ D12
DDR_B_ D13
DDR_B_ D14
DDR_B_ D15
DDR_B_ D16
DDR_B_ D17
DDR_B_ D18

DDR_B_ D19

DDR_B_ D20

DDR_B_ D21
DDR_B_ D22
DDR_B_ D23
DDR_B_ D24
DDR_B_ D25
DDR_B_ D26
DDR_B_ D27
DDR_B_ D28
DDR_B_ D29
DDR_B_ D30
DDR_B_ D31
DDR_B_ D32
DDR_B_ D33
DDR_B_ D34
DDR_B_ D35
DDR_B_ D36
DDR_B_ D37
DDR_B_ D38
DDR_B_ D39

DDR_B_ D40
DDR_B_ D41
DDR_B_ D42
DDR_B_ D43
DDR_B_ D44
DDR_B_ D45
DDR_B_ D46
DDR_B_ D47
DDR_B_ D48
DDR_B_ D49
DDR_B_ D50
DDR_B_ D51
DDR_B_ D52
DDR_B_ D53
DDR_B_ D54
DDR_B_ D55
DDR_B_ D56
DDR_B_ D57
DDR_B_ D58
DDR_B_ D59
DDR_B_ D60
DDR_B_ D61
DDR_B_ D62
DDR_B_ D63

UC1B

DDR4(IL)/LP3-DDR4(NIL)

BT11

DDR1_DQ_0/DDR0_DQ_16

BR11

DDR1_DQ_1/DDR0_DQ_17

BT9

DDR1_DQ_2/DDR0_DQ_18

BR8

DDR1_DQ_3/DDR0_DQ_19

BP11

DDR1_DQ_4/DDR0_DQ_20

BN11

DDR1_DQ_5/DDR0_DQ_21

BP8

DDR1_DQ_6/DDR0_DQ_22

BN8

DDR1_DQ_7/DDR0_DQ_23

BL12

DDR1_DQ_8/DDR0_DQ_24

BL11

DDR1_DQ_9/DDR0_DQ_25

BL8

DDR1_DQ_10/DDR0_DQ_26

BJ8

DDR1_DQ_11/DDR0_DQ_27

BJ11

DDR1_DQ_12/DDR0_DQ_28

BJ10

DDR1_DQ_13/DDR0_DQ_29

BL7

DDR1_DQ_14/DDR0_DQ_30

BJ7

DDR1_DQ_15/DDR0_DQ_31

BG11

DDR1_DQ_16/DDR0_DQ_48

BG10

DDR1_DQ_17/DDR0_DQ_49

BG8

DDR1_DQ_18/DDR0_DQ_50

BF8

DDR1_DQ_19/DDR0_DQ_51

BF11

DDR1_DQ_20/DDR0_DQ_52

BF10

DDR1_DQ_21/DDR0_DQ_53

BG7

DDR1_DQ_22/DDR0_DQ_54

BF7

DDR1_DQ_23/DDR0_DQ_55

BB11

DDR1_DQ_24/DDR0_DQ_56

BC11

DDR1_DQ_25/DDR0_DQ_57

BB8

DDR1_DQ_26/DDR0_DQ_58

BC8

DDR1_DQ_27/DDR0_DQ_59

BC10

DDR1_DQ_28/DDR0_DQ_60

BB10

DDR1_DQ_29/DDR0_DQ_61

BC7

DDR1_DQ_30/DDR0_DQ_62

BB7

DDR1_DQ_31/DDR0_DQ_63

AA11

DDR1_DQ_32/DDR1_DQ_16

AA10

DDR1_DQ_33/DDR1_DQ_17

AC11

DDR1_DQ_34/DDR1_DQ_18

AC10

DDR1_DQ_35/DDR1_DQ_19

AA7

DDR1_DQ_36/DDR1_DQ_20

AA8

DDR1_DQ_37/DDR1_DQ_21

AC8

DDR1_DQ_38/DDR1_DQ_22

AC7

DDR1_DQ_39/DDR1_DQ_23

DDR4(IL)/LP3-DDR4(NIL)

W8

DDR1_DQ_40/DDR1_DQ_24

W7

DDR1_DQ_41/DDR1_DQ_25

V10

DDR1_DQ_42/DDR1_DQ_26

V11

DDR1_DQ_43/DDR1_DQ_27

W11

DDR1_DQ_44/DDR1_DQ_28

W10

DDR1_DQ_45/DDR1_DQ_29

V7

DDR1_DQ_46/DDR1_DQ_30

V8

DDR1_DQ_47/DDR1_DQ_31

R11

DDR1_DQ_48/DDR1_DQ_48

P11

DDR1_DQ_49/DDR1_DQ_49

P7

DDR1_DQ_50/DDR1_DQ_50

R8

DDR1_DQ_51/DDR1_DQ_51

R10

DDR1_DQ_52/DDR1_DQ_52

P10

DDR1_DQ_53/DDR1_DQ_53

R7

DDR1_DQ_54/DDR1_DQ_54

P8

DDR1_DQ_55/DDR1_DQ_55

L11

DDR1_DQ_56/DDR1_DQ_56

M11

DDR1_DQ_57/DDR1_DQ_57

L7

DDR1_DQ_58/DDR1_DQ_58

M8

DDR1_DQ_59/DDR1_DQ_59

L10

DDR1_DQ_60/DDR1_DQ_60

M10

DDR1_DQ_61/DDR1_DQ_61

M7

DDR1_DQ_62/DDR1_DQ_62

L8

DDR1_DQ_63/DDR1_DQ_63

LP3/DDR4

AW11

NC/DDR1_ECC_0

AY11

NC/DDR1_ECC_1

AY8

NC/DDR1_ECC_2

AW8

NC/DDR1_ECC_3

AY10

NC/DDR1_ECC_4

AW10

NC/DDR1_ECC_5

AY7

NC/DDR1_ECC_6

AW7

NC/DDR1_ECC_7

CFL-H

DDR CHANNEL B

DDR1_CKP_0/DDR1_CKP_0
DDR1_CKN_0/DDR1_CKN_0

DDR1_CKP_1/DDR1_CKP_1

DDR1_CKN_1/DDR1_CKN_1

DDR1_CKE_0/DDR1_CKE_0
DDR1_CKE_1/DDR1_CKE_1

DDR1_CKE_2/DDR1_CKE_2

DDR1_CKE_3/DDR1_CKE_3

DDR1_CS#_0/DDR1_CS#_0
DDR1_CS#_1/DDR1_CS#_1

DDR1_ODT_0/DDR1_ODT_0

DDR1_CAB_3/DDR1_MA_16
DDR1_CAB_2/DDR1_MA_14
DDR1_CAB_1/DDR1_MA_15

DDR1_CAB_4/DDR1_BA_0

DDR1_CAB_6/DDR1_BA_1

DDR1_CAA_5/DDR1_BG_0

DDR1_CAB_9/DDR1_MA_0
DDR1_CAB_8/DDR1_MA_1
DDR1_CAB_5/DDR1_MA_2

DDR1_CAA_0/DDR1_MA_5
DDR1_CAA_2/DDR1_MA_6
DDR1_CAA_4/DDR1_MA_7

DDR1_CAA_3/DDR1_MA_8

DDR1_CAA_1/DDR1_MA_9

DDR1_CAB_7/DDR1_MA_10
DDR1_CAA_7/DDR1_MA_11
DDR1_CAA_6/DDR1_MA_12
DDR1_CAB_0/DDR1_MA_13

DDR1_CAA_9/DDR1_BG_1

DDR1_CAA_8/DDR1_ACT#

DDR4(IL)/LP3-DDR4(NIL)

DDR1_DQSN_0/DDR0_DQSN_2

DDR1_DQSN_1/DDR0_DQSN_3
DDR1_DQSN_2/DDR0_DQSN_6
DDR1_DQSN_3/DDR0_DQSN_7
DDR1_DQSN_4/DDR1_DQSN_2

DDR1_DQSN_5/DDR1_DQSN_3

DDR1_DQSN_6/DDR1_DQSN_6
DDR1_DQSN_7/DDR1_DQSN_7

DDR1_DQSP_0/DDR0_DQSP_2
DDR1_DQSP_1/DDR0_DQSP_3
DDR1_DQSP_2/DDR0_DQSP_6
DDR1_DQSP_3/DDR0_DQSP_7
DDR1_DQSP_4/DDR1_DQSP_2
DDR1_DQSP_5/DDR1_DQSP_3
DDR1_DQSP_6/DDR1_DQSP_6
DDR1_DQSP_7/DDR1_DQSP_7

DDR1_DQSP_8/DDR1_DQSP_8
DDR1_DQSN_8/DDR1_DQSN_8

LP3/DDR4

NC/DDR1_CKP_2
NC/DDR1_CKN_2
NC/DDR1_CKP_3
NC/DDR1_CKN_3

NC/DDR1_CS#_2
NC/DDR1_CS#_3

NC/DDR1_ODT_1
NC/DDR1_ODT_2
NC/DDR1_ODT_3

NC/DDR1_MA_3
NC/DDR1_MA_4

NC/DDR1_PAR

NC/DDR1_ALERT#

AM9
AN9

AM7

AM8
AM11
AM10
AJ10
AJ11

AT8
AT10

AT7

AT11

AF11
AE7
AF10
AE10

AF7
AE8
AE9
AE11

AH10
AH11
AF8

AH8

AH9

AR9

AJ9
AK6
AK5
AL5
AL6
AM6
AN7
AN10

AN8

AR11

AH7
AN11
AR10
AF9
AR7

AT9

AJ7
AR8

BN9

BL9

BG9

BC9
AC9

W9

R9
M9

BP9

BJ9
BF9
BB9
AA9
V9
P9
L9

AW9
AY9

DDR_B_ CLK0
DDR_B_ CLK#0
DDR_B_ CLK1
DDR_B_ CLK#1

DDR_B_ CKE0
DDR_B_ CKE1

DDR_B_ CS#0
DDR_B_ CS#1

DDR_B_ ODT0

DDR_B_ ODT1

DDR_B_ MA16_RAS#
DDR_B_ MA14_WE #
DDR_B_ MA15_CAS#

DDR_B_ BA0
DDR_B_ BA1
DDR_B_ BG0

DDR_B_ MA0

DDR_B_ MA1
DDR_B_ MA2

DDR_B_ MA3

DDR_B_ MA4
DDR_B_ MA5
DDR_B_ MA6
DDR_B_ MA7

DDR_B_ MA8
DDR_B_ MA9
DDR_B_ MA10
DDR_B_ MA11
DDR_B_ MA12
DDR_B_ MA13
DDR_B_ BG1
DDR_B_ ACT#

DDR_B_ PAR
DDR_B_ ALERT#

DDR_B_ DQS#0

DDR_B_ DQS#1
DDR_B_ DQS#2
DDR_B_ DQS#3
DDR_B_ DQS#4
DDR_B_ DQS#5
DDR_B_ DQS#6
DDR_B_ DQS#7

DDR_B_ DQS0
DDR_B_ DQS1
DDR_B_ DQS2
DDR_B_ DQS3
DDR_B_ DQS4
DDR_B_ DQS5
DDR_B_ DQS6
DDR_B_ DQS7

DDR_B_ CLK0 <24>
DDR_B_ CLK#0 <24>
DDR_B_ CLK1 <24>

DDR_B_ CLK#1 <24>

DDR_B_ CKE0 <24>
DDR_B_ CKE1 <24>

DDR_B_ CS#0 <24>
DDR_B_ CS#1 <24>

DDR_B_ ODT0 <24>
DDR_B_ ODT1 <24>

DDR_B_ MA16_RAS# <24 >
DDR_B_ MA14_WE # <24>
DDR_B_ MA15_CAS# <24 >

DDR_B_ BA0 < 24>
DDR_B_ BA1 < 24>
DDR_B_ BG0 < 24>

DDR_B_ MA0 <24 >
DDR_B_ MA1 <24 >
DDR_B_ MA2 <24 >
DDR_B_ MA3 <24 >
DDR_B_ MA4 <24 >
DDR_B_ MA5 <24 >
DDR_B_ MA6 <24 >
DDR_B_ MA7 <24 >

DDR_B_ MA8 <24 >
DDR_B_ MA9 <24 >
DDR_B_ MA10 <2 4>
DDR_B_ MA11 <2 4>
DDR_B_ MA12 <2 4>
DDR_B_ MA13 <2 4>
DDR_B_ BG1 < 24>
DDR_B_ ACT# <24>

DDR_B_ PAR <24>
DDR_B_ ALERT# <24>

DDR_B_ DQS#0 <24>
DDR_B_ DQS#1 <24>
DDR_B_ DQS#2 <24>
DDR_B_ DQS#3 <24>
DDR_B_ DQS#4 <24>
DDR_B_ DQS#5 <24>
DDR_B_ DQS#6 <24>
DDR_B_ DQS#7 <24>

DDR_B_ DQS0 <24>
DDR_B_ DQS1 <24>
DDR_B_ DQS2 <24>
DDR_B_ DQS3 <24>
DDR_B_ DQS4 <24>
DDR_B_ DQS5 <24>
DDR_B_ DQS6 <24>
DDR_B_ DQS7 <24>

For ECC DIMM

1

3

1
1 2
1

2

2

B

RC3 121_04 02_1%
RC4 75_040 2_1%
RC5 100_04 02_1%

Trace Width/Space: 15 mil/ 25 mil

4 4

A

Max Trace Length: 500 mil

SM_RCO MP0
SM_RCO MP1
SM_RCO MP2

G1

DDR_RCOMP_0

H1

DDR_RCOMP_1

J2

DDR_RCOMP_2

CFL-H_B GA1440

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

2 OF 13

DDR_VREF_CA
DDR0_VREF_DQ
DDR1_VREF_DQ

Compal Secret Data

Compal Secret Data

2017/12 /18 2018/09 /01

2017/12 /18 2018/09 /01

2017/12 /18 2018/09 /01

C

Compal Secret Data

BN13
BP13
BR13

Deciphered Date

Deciphered Date

Deciphered Date

+0.6V_V REFCA

+0.6V_B _VREFDQ

+0.6V_V REFCA

+0.6V_B _VREFDQ

D

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

CFL-H(3/8)DIMMB

CFL-H(3/8)DIMMB

CFL-H(3/8)DIMMB

Size Document Number R ev

Size Document Number R ev

Size Document Number R ev

Custom

Custom

Custom

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

Dat e: Sheet of

Dat e: Sheet of

Dat e: Sheet

E

o f

9 67Thursday, Febru ary 22, 2018

9 67Thursday, Febru ary 22, 2018

9 67Thursday, Febru ary 22, 2018

1.0

1.0

1.0

A

PEG&DMI

B

C

D

E

1

2 2

3

To DGPU
PEG Lane Reversed

PEG_CR X_C_GTX_P1 5<25>
PEG_CR X_C_GTX_N1 5<25>

PEG_CR X_C_GTX_P1 4<25>
PEG_CR X_C_GTX_N1 4<25>

PEG_CR X_C_GTX_P1 3<25>
PEG_CR X_C_GTX_N1 3<25>

PEG_CR X_C_GTX_P1 2<25>
PEG_CR X_C_GTX_N1 2<25>

PEG_CR X_C_GTX_P1 1<25>
PEG_CR X_C_GTX_N1 1<25>

PEG_CR X_C_GTX_P1 0<25>
PEG_CR X_C_GTX_N1 0<25>

PEG_CR X_C_GTX_P9<25>
PEG_CR X_C_GTX_N9<25>

PEG_CR X_C_GTX_P8<25>
PEG_CR X_C_GTX_N8<25>

PEG_CR X_C_GTX_P7<25>

PEG_CR X_C_GTX_N7<25>

PEG_CR X_C_GTX_P6<25>
PEG_CR X_C_GTX_N6<25>

PEG_CR X_C_GTX_P5<25>
PEG_CR X_C_GTX_N5<25>

PEG_CR X_C_GTX_P4<25>
PEG_CR X_C_GTX_N4<25>

PEG_CR X_C_GTX_P3<25>
PEG_CR X_C_GTX_N3<25>

PEG_CR X_C_GTX_P2<25>
PEG_CR X_C_GTX_N2<25>

PEG_CR X_C_GTX_P1<25>
PEG_CR X_C_GTX_N1<25>

PEG_CR X_C_GTX_P0<25>
PEG_CR X_C_GTX_N0<25>

+VCCIO

To PCH

1 2

CC1 0.22U_0 201_6.3V6KVGA@

1 2

CC3 0.22U_0 201_6.3V6KVGA@

1

VGA@

VGA@

1

1 2

1 2

1 2

1 2
1

1 2
1 2

1 2

1 2

1 2
1 2

1 2

1 2

1

1 2

1 2

1 2

1 2

1 2

1
1 2

1 2

1 2

1
1

1
1 2

1 2

1 2

DMI_CRX_ PTX_P0<15>
DMI_CRX_ PTX_N0<15>

DMI_CRX_ PTX_P1<15>
DMI_CRX_ PTX_N1<15>

DMI_CRX_ PTX_P2<15>
DMI_CRX_ PTX_N2<15>

DMI_CRX_ PTX_P3<15>
DMI_CRX_ PTX_N3<15>

2

2

2

2

2
2

2

2

CC5 0.22U_0 201_6.3V6KVGA@
CC6 0.22U_0 201_6.3V6KVGA@

CC7 0.22U_0 201_6.3V6KVGA@

CC14 0.22U_0 201_6.3V6KVGA@

CC16 0.22U_0 201_6.3V6KVGA@
CC17 0.22U_0 201_6.3V6KVGA@

CC19 0.22U_0 201_6.3V6KVGA@
CC20 0.22U_0 201_6.3V6KVGA@

CC10 0.22U_0 201_6.3V6K
CC23 0.22U_0 201_6.3V6KVGA@

CC25 0.22U_0 201_6.3V6KVGA@
CC27 0.22U_0 201_6.3V6KVGA@

CC29 0.22U_0 201_6.3V6KVGA@

CC31 0.22U_0 201_6.3V6KVGA@

CC33 0.22U_0 201_6.3V6KVGA@

CC35 0.22U_0 201_6.3V6KVGA@

CC37 0.22U_0 201_6.3V6K

CC39 0.22U_0 201_6.3V6KVGA@

CC41 0.22U_0 201_6.3V6KVGA@

CC43 0.22U_0 201_6.3V6KVGA@

CC45 0.22U_0 201_6.3V6KVGA@
CC47 0.22U_0 201_6.3V6KVGA@

CC49 0.22U_0 201_6.3V6KVGA@

CC51 0.22U_0 201_6.3V6KVGA@

CC53 0.22U_0 201_6.3V6KVGA@
CC55 0.22U_0 201_6.3V6KVGA@

CC57 0.22U_0 201_6.3V6KVGA@
CC59 0.22U_0 201_6.3V6KVGA@

CC61 0.22U_0 201_6.3V6KVGA@

CC63 0.22U_0 201_6.3V6KVGA@

RC6 24.9_04 02_1%

PEG_CR X_GTX_P15
PEG_CR X_GTX_N15

PEG_CR X_GTX_P14
PEG_CR X_GTX_N14

PEG_CR X_GTX_P13
PEG_CR X_GTX_N13

PEG_CR X_GTX_P12
PEG_CR X_GTX_N12

PEG_CR X_GTX_P11
PEG_CR X_GTX_N11

PEG_CR X_GTX_P10
PEG_CR X_GTX_N10

PEG_CR X_GTX_P9
PEG_CR X_GTX_N9

PEG_CR X_GTX_P8
PEG_CR X_GTX_N8

PEG_CR X_GTX_P7
PEG_CR X_GTX_N7

PEG_CR X_GTX_P6
PEG_CR X_GTX_N6

PEG_CR X_GTX_P5
PEG_CR X_GTX_N5

PEG_CR X_GTX_P4
PEG_CR X_GTX_N4

PEG_CR X_GTX_P3
PEG_CR X_GTX_N3

PEG_CR X_GTX_P2
PEG_CR X_GTX_N2

PEG_CR X_GTX_P1
PEG_CR X_GTX_N1

PEG_CR X_GTX_P0

PEG_CR X_GTX_N0

PEG_RC OMP

Trace Width/Space: 15 mil/ 15 mil
Max Trace Length: 600 mil

DMI_CRX_ PTX_P0
DMI_CRX_ PTX_N0

DMI_CRX_ PTX_P1
DMI_CRX_ PTX_N1

DMI_CRX_ PTX_P2
DMI_CRX_ PTX_N2

DMI_CRX_ PTX_P3
DMI_CRX_ PTX_N3

E25

D25

E24
F24

E23

D23

E22
F22

E21

D21

E20

F20

E19

D19

E18
F18

D17

E17

F16
E16

D15

E15

F14
E14

D13

E13

F12

E12

D11

E11

F10
E10

G2

D8

E8

E6
F6

D5

E5

J8
J9

CFL-H_B GA1440

UC1C

PEG_RXP_0
PEG_RXN_0

PEG_RXP_1
PEG_RXN_1

PEG_RXP_2
PEG_RXN_2

PEG_RXP_3
PEG_RXN_3

PEG_RXP_4
PEG_RXN_4

PEG_RXP_5
PEG_RXN_5

PEG_RXP_6
PEG_RXN_6

PEG_RXP_7

PEG_RXN_7

PEG_RXP_8
PEG_RXN_8

PEG_RXP_9
PEG_RXN_9

PEG_RXP_10
PEG_RXN_10

PEG_RXP_11
PEG_RXN_11

PEG_RXP_12

PEG_RXN_12

PEG_RXP_13

PEG_RXN_13

PEG_RXP_14

PEG_RXN_14

PEG_RXP_15
PEG_RXN_15

PEG_RCOMP

DMI_RXP_0

DMI_RXN_0

DMI_RXP_1
DMI_RXN_1

DMI_RXP_2
DMI_RXN_2

DMI_RXP_3
DMI_RXN_3

CFL-H

PEG_TXP_10

PEG_TXN_10

PEG_TXP_11

PEG_TXN_11

PEG_TXP_12

PEG_TXN_12

PEG_TXP_13

PEG_TXN_13

PEG_TXP_14

PEG_TXN_14

PEG_TXP_15

PEG_TXN_15

3 OF 13

PEG_TXP_0

PEG_TXN_0

PEG_TXP_1

PEG_TXN_1

PEG_TXP_2

PEG_TXN_2

PEG_TXP_3

PEG_TXN_3

PEG_TXP_4

PEG_TXN_4

PEG_TXP_5

PEG_TXN_5

PEG_TXP_6

PEG_TXN_6

PEG_TXP_7

PEG_TXN_7

PEG_TXP_8

PEG_TXN_8

PEG_TXP_9

PEG_TXN_9

DMI_TXP_0
DMI_TXN_0

DMI_TXP_1
DMI_TXN_1

DMI_TXP_2
DMI_TXN_2

DMI_TXP_3
DMI_TXN_3

B25

A25

B24
C24

B23
A23

B22
C22

B21

A21

B20
C20

B19
A19

B18
C18

A17
B17

C16
B16

A15
B15

C14
B14

A13
B13

C12
B12

A11
B11

C10
B10

B8
A8

C6
B6

B5
A5

D4
B4

PEG_CT X_GRX_P15

PEG_CT X_GRX_N15

PEG_CT X_GRX_P14

PEG_CT X_GRX_N14

PEG_CT X_GRX_P13

PEG_CT X_GRX_N13

PEG_CT X_GRX_P12

PEG_CT X_GRX_N12

PEG_CT X_GRX_P11

PEG_CT X_GRX_N11

PEG_CT X_GRX_P10

PEG_CT X_GRX_N10

PEG_CT X_GRX_P9

PEG_CT X_GRX_N9

PEG_CT X_GRX_P8

PEG_CT X_GRX_N8

PEG_CT X_GRX_P7

PEG_CT X_GRX_N7

PEG_CT X_GRX_P6

PEG_CT X_GRX_N6

PEG_CT X_GRX_P5

PEG_CT X_GRX_N5

PEG_CT X_GRX_P4

PEG_CT X_GRX_N4

PEG_CT X_GRX_P3

PEG_CT X_GRX_N3

PEG_CT X_GRX_P2

PEG_CT X_GRX_N2

PEG_CT X_GRX_P1

PEG_CT X_GRX_N1

PEG_CT X_GRX_P0

PEG_CT X_GRX_N0

DMI_CTX_ PRX_P0
DMI_CTX_ PRX_N0

DMI_CTX_ PRX_P1
DMI_CTX_ PRX_N1

DMI_CTX_ PRX_P2
DMI_CTX_ PRX_N2

DMI_CTX_ PRX_P3
DMI_CTX_ PRX_N3

12

CC20.22U_0 201_6.3V6K VGA@

12

CC40.22U_0 201_6.3V6K VGA@

1

2

2

2

2

2

2

2

2

2

2

DMI_CTX_ PRX_P0 <15>
DMI_CTX_ PRX_N0 <15>

DMI_CTX_ PRX_P1 <15>
DMI_CTX_ PRX_N1 <15>

DMI_CTX_ PRX_P2 <15>
DMI_CTX_ PRX_N2 <15>

DMI_CTX_ PRX_P3 <15>
DMI_CTX_ PRX_N3 <15>

12

12

1

12

1

1

12

12

12

12
12

12

12

12

12

12

12

1
12

1
12

1

1

1
12

12

12

1
12

VGA@

VGA@

VGA@

VGA@
VGA@

CC110.22U_0 201_6.3V6K VGA@

CC120.22U_0 201_6.3V6K VGA@

CC130.22U_0 201_6.3V6K VGA@

CC150.22U_0 201_6.3V6K VGA@

CC80.22U_0 201_6.3V6K VGA@

CC180.22U_0 201_6.3V6K VGA@

CC90.22U_0 201_6.3V6K VGA@

CC210.22U_0 201_6.3V6K VGA@

CC220.22U_0 201_6.3V6K VGA@

CC240.22U_0 201_6.3V6K VGA@

CC260.22U_0 201_6.3V6K VGA@
CC280.22U_0 201_6.3V6K VGA@

CC300.22U_0 201_6.3V6K VGA@

CC320.22U_0 201_6.3V6K

CC340.22U_0 201_6.3V6K VGA@

CC360.22U_0 201_6.3V6K VGA@

CC380.22U_0 201_6.3V6K

CC400.22U_0 201_6.3V6K VGA@

CC420.22U_0 201_6.3V6K
CC440.22U_0 201_6.3V6K VGA@

CC460.22U_0 201_6.3V6K

CC480.22U_0 201_6.3V6K

CC500.22U_0 201_6.3V6K VGA@

CC520.22U_0 201_6.3V6K VGA@

CC540.22U_0 201_6.3V6K VGA@
CC560.22U_0 201_6.3V6K VGA@

CC580.22U_0 201_6.3V6K VGA@

CC600.22U_0 201_6.3V6K VGA@

CC620.22U_0 201_6.3V6K VGA@
CC640.22U_0 201_6.3V6K VGA@

PEG_CT X_C_GRX_P1 5 <25>

PEG_CT X_C_GRX_N1 5 <25>

PEG_CT X_C_GRX_P1 4 <25>
PEG_CT X_C_GRX_N1 4 <25>

PEG_CT X_C_GRX_P1 3 <25>
PEG_CT X_C_GRX_N1 3 <25>

PEG_CT X_C_GRX_P1 2 <25>
PEG_CT X_C_GRX_N1 2 <25>

PEG_CT X_C_GRX_P1 1 <25>
PEG_CT X_C_GRX_N1 1 <25>

PEG_CT X_C_GRX_P1 0 <25>
PEG_CT X_C_GRX_N1 0 <25>

PEG_CT X_C_GRX_P9 <25 >
PEG_CT X_C_GRX_N9 < 25>

PEG_CT X_C_GRX_P8 <25 >
PEG_CT X_C_GRX_N8 < 25>

PEG_CT X_C_GRX_P7 <25 >
PEG_CT X_C_GRX_N7 < 25>

PEG_CT X_C_GRX_P6 <25 >
PEG_CT X_C_GRX_N6 < 25>

PEG_CT X_C_GRX_P5 <25 >
PEG_CT X_C_GRX_N5 < 25>

PEG_CT X_C_GRX_P4 <25 >
PEG_CT X_C_GRX_N4 < 25>

PEG_CT X_C_GRX_P3 <25 >
PEG_CT X_C_GRX_N3 < 25>

PEG_CT X_C_GRX_P2 <25 >
PEG_CT X_C_GRX_N2 < 25>

PEG_CT X_C_GRX_P1 <25 >
PEG_CT X_C_GRX_N1 < 25>

PEG_CT X_C_GRX_P0 <25 >
PEG_CT X_C_GRX_N0 < 25>

To PCH

To DGPU
PEG Lane Reversed

1

3

4 4

Security Classification

Security Classification

Security Classification

2017/12 /18 2018/09 /01

2017/12 /18 2018/09 /01

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

A

B

2017/12 /18 2018/09 /01

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

PEG/DMI

PEG/DMI

PEG/DMI

Size Document Number R ev

Size Document Number R ev

Size Document Number R ev

Custom

Custom

Custom

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

Dat e: Sheet of

Dat e: Sheet of

D

Dat e: Sheet of

10 67Thursday, Febru ary 22, 2018

10 67Thursday, Febru ary 22, 2018

10 67Thursday, Febru ary 22, 2018

E

1.0

1.0

1.0

A

571391_CFL_H_PDG_Rev0p5

1. The total Length of Data and Clock (from CPU to each VR) must be equal (± 0.1 inch).

2. Route the Alert signal between the Clock and the Data signals.

1

3. Place those resistors close CPU side.

Sensitive

Sensitive

H_CPUP WRGD<19>
H_PLTR ST_CPU#<18>
H_PM_S YNC_R<18>

H_PECI<18,39>

PCH_TH ERMTRIP#_R< 18>

PROC_ SELE CT#

2 2

should be unconnected on CFL processor
EDS1.2 8/21

XEMC@

1 2

EMC@

1

XEMC@

1

EMC@

1 2

2

2

CC650.1U_0402_ 10V6K

CC661000P_ 0402_50V7K

CC670.1U_0402_ 10V6K

CC681000P_ 0402_50V7K

H_CPUP WRGD

H_PROC HOT#_R

H_THER MTRIP#

EC_VCC ST_PG

Near CPU side

follow 1050 Request

+1.05V_ VCCST

3

4 4

8/21

1

RH1 1K_040 2_5%

H_PROC HOT#<39,50>

EC_VCC ST_PG_R<39,47>

H_PM_D OWN_R<18 >

A

2

+1.05VS _VCCSTG

1

RC21
1K_040 2_5%

2

1 2

RC14 499_0 402_1%

+1.05V_ VCCST

1

RC22
1K_040 2_5%

2

1

RC15 60.4_04 02_1%

1 2

RC16 20_04 02_5%

1

RH2

@

13_040 2_5%

2

H_THER MTRIP#

2

H_PROC HOT#_R

EC_VCC ST_PG

H_PM_D OWN CPU_SV ID_ALERT#

PCH_CP U_PCIBCLK_P<16>
PCH_CP U_PCIBCLK_N<16>

PCH_CP U_24M_CLK_ P<16>
PCH_CP U_24M_CLK_ N<16>

PCH_CP U_BCLK_P<16>
PCH_CP U_BCLK_N<16>

CPU_SV ID_CLK<56,57>

RC17 0_040 2_5%@

B

1

SVID

B

2

DDR_PG _CTRL

PCH_CP U_BCLK_P
PCH_CP U_BCLK_N

PCH_CP U_PCIBCLK_P
PCH_CP U_PCIBCLK_N

PCH_CP U_24M_CLK_ P
PCH_CP U_24M_CLK_ N

CPU_SV ID_ALERT#
CPU_SV ID_CLK
CPU_SV ID_DAT

H_PROC HOT#_R

DDR_PG _CTRL

EC_VCC ST_PG

H_CPUP WRGD
H_PLTR ST_CPU#
H_PM_S YNC_R
H_PM_D OWN
H_PECI
H_THER MTRIP#

TC5TP@

TC6TP@

SKTOCC #

CATERR #

2

3

74AUP1 G07GW_T SSOP5

CPU_SVID_ALERT# _R<56,57>

CPU_SV ID_DAT<56,57>

Security Classification

Security Classification

Security Classification

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

NC1VCC

A

GND

Issued Date

Issued Date

Issued Date

B31
A32

D35
C36

E31
D31

BH31
BH32
BH29
BR30

BT13

H13

BT31
BP35

BM34

BP31
BT34

J31

BR33

BN1

BM30

AT13

AW13

AU13
AY13

UC3

5

4

Y

+1.05V_ VCCST

RC19

56_040 2_1%

C

CFL-H

UC1E

BN25

5 OF 13

CC69

1

CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8

CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15

CFG_17
CFG_16
CFG_19
CFG_18

BPM#_0
BPM#_1
BPM#_2
BPM#_3

PROC_TDO

PROC_TDI
PROC_TMS
PROC_TCK

PROC_TRST#
PROC_PREQ#
PROC_PRDY#

CFG_RCOMP

PU 330K follow CRB
8/21

Compal Secret Data

Compal Secret Data

Compal Secret Data

BN27
BN26
BN28
BR20
BM20
BT20
BP20
BR23
BR22
BT23
BT22
BM19
BR19
BP19
BT19

BN23
BP23
BP22
BN22

BR27
BT27
BM31
BT30

BT28
BL32
BP28
BR28

BP30
BL30
BP27

BT25

BCLKP
BCLKN

PCI_BCLKP
PCI_BCLKN

CLK24P
CLK24N

VIDALERT#
VIDSCK
VIDSOUT
PROCHOT#

DDR_VTT_CNTL

VCCST_PWRGD

PROCPWRGD
RESET#
PM_SYNC
PM_DOWN
PECI
THERMTRIP#

SKTOCC#
PROC_SELECT#

CATERR#

ZVM#
MSM#

RSVD1
RSVD2

CFL-H_B GA1440

+1.2V_V DDQ

2

0.1U_04 02_10V6K

SM_PG_ CTRL

1

1

RC20
100_04 02_1%

2

2

1 2

RC13 220_0 402_5%

2017/12 /18 2018/09 /01

2017/12 /18 2018/09 /01

2017/12 /18 2018/09 /01

C

CFG0

CFG2

CFG4
CFG5
CFG6
CFG7

XDP_BP M#0
XDP_BP M#1
XDP_BP M#2

XDP_BP M#3

CPU_XD P_TDO

CPU_XD P_TDI
CPU_XD P_TMS
CPU_XD P_TCK0

CPU_XD P_TRST#
XDP_PR EQ#
XDP_PR DY#

CFG_RC OMP

Trace Width/Space: 4 mil/ 12 mil
Max Trace Length: 600 mil

+3VS

1

RC23
330K_0 402_5%

2

CPU_SV ID_DAT

Deciphered Date

Deciphered Date

Deciphered Date

D

CFG0
CFG2
CFG4
CFG5
CFG6
CFG7

The CFG signals have a default valu e of '1' if not terminated on the boar d.

CFG[0]: Stall reset sequence after PCU PLL lock until de-asserted

1 = (Default) Normal Operation;

*

0 = Stall.

CFG[2]: PCI Express* Static x16 Lan e Numbering Reversal.

1 = Normal operation
0 = Lane numbers reversed.

*

CFG[4]: eDP enable:

1 = Disabled.
0 = Enabled.

*

CFG[6:5]: PCI Express* Bifurcation:

00 = 1 x8, 2 x4 PCI Express*
01 = reserved

TC1 TP@
TC2 TP@
TC3 TP@
TC4 TP@

CPU_XD P_TDO <1 9>
CPU_XDP_TDI <19>
CPU_XDP_TMS <19>
CPU_XDP_TCK 0 <19>

CPU_XDP_TRS T# <22>

TC19 TP @
TC20 TP @

RC18

2

1

49.9_04 02_1%

+1.05VS _VCCSTG

10 = 2 x8 PCI Express*
11 = 1 x16 PCI Express*

*

CFG[7]: PEG Training:

1 = (default) PEG Train immediately following RESET# de assertion.

*

0 = PEG Wait for BIOS for training.

*CFG Pin Use CMC debug on DDX03 R02 Schematic.

To be confirm

XDP_PR EQ#
XDP_PR DY#

2

CMC@

12

1

12

RC76 5 1_0402_5%CMC@

RC77 5 1_0402_5%CMC@

RC78 5 1_0402_5%

1 2

RC7 1K_040 2_5%@

1 2

RC8 1K_040 2_5%

1 2

RC9 1K_040 2_5%

1 2

RC10 1K_04 02_5%@

1 2

RC11 1K_04 02_5%@

1 2

RC12 1K_04 02_5%@

Place to CPU side

CPU_XD P_TMS

CPU_XD P_TDI

CPU_XD P_TDO

E

XDP_PREQ# <22>
XDP_PR DY# < 22>

Place to CPU side

CPU_XD P_TCK0

PCH_JT AG_TCK1

CPU_XD P_TRST#

PCH_JT AG_TCK1 <19>

11 67Thursday, Febru ary 22, 2018

11 67Thursday, Febru ary 22, 2018

11 67Thursday, Febru ary 22, 2018

E

1.0

1.0

1.0

o f

SM_PG_ CTRL <52>

D

RC79 5 1_0402_5%CMC@

RC80 5 1_0402_5%@

RC81 5 1_0402_5%@

12

12

2

1

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

CFL-H(5/8)CFG,SVID

CFL-H(5/8)CFG,SVID

CFL-H(5/8)CFG,SVID

Size Document Number R ev

Size Document Number R ev

Size Document Number R ev

Custom

Custom

Custom

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

Dat e: Sheet of

Dat e: Sheet of

Dat e: Sheet

1

3

A

B

C

D

E

GT
32000mA(Hexa Core GT2)

AT14
AT31
AT32
AT33
AT34
AT35
AT36
AT37

1

2 2

3

4 4

AT38
AU14
AU29
AU30
AU31
AU32
AU35
AU36
AU37
AU38
AV29
AV30
AV31
AV32
AV33
AV34
AV35
AV36

AW14
AW31
AW32
AW33
AW34
AW35
AW36
AW37
AW38

AY29
AY30
AY31
AY32
AY35
AY36
AY37
AY38
BA13
BA14
BA29
BA30
BA31
BA32
BA33
BA34
BA35
BA36
BB13
BB14
BB31
BB32
BB33
BB34
BB35
BB36
BB37
BB38
BC29
BC30
BC31
BC32
BC35
BC36

BC37
BC38
BD13
BD14

BD29
BD30
BD31

BD32

BD33
BD34
BP37
BP38
BR15
BR16
BR17

CFL-H

UC1K

VCCGT1
VCCGT2
VCCGT3
VCCGT4
VCCGT5
VCCGT6
VCCGT7
VCCGT8
VCCGT9
VCCGT10
VCCGT11
VCCGT12
VCCGT13
VCCGT14
VCCGT15
VCCGT16
VCCGT17
VCCGT18
VCCGT19
VCCGT20
VCCGT21
VCCGT22
VCCGT23
VCCGT24
VCCGT25
VCCGT26
VCCGT27
VCCGT28
VCCGT29
VCCGT30
VCCGT31
VCCGT32
VCCGT33
VCCGT34
VCCGT35
VCCGT36
VCCGT37
VCCGT38
VCCGT39
VCCGT40
VCCGT41
VCCGT42
VCCGT43
VCCGT44
VCCGT45
VCCGT46
VCCGT47
VCCGT48
VCCGT49
VCCGT50
VCCGT51
VCCGT52
VCCGT53
VCCGT54
VCCGT55
VCCGT56
VCCGT57
VCCGT58
VCCGT59
VCCGT60
VCCGT61
VCCGT62
VCCGT63
VCCGT64
VCCGT65
VCCGT66
VCCGT67
VCCGT68
VCCGT69
VCCGT70

VCCGT71
VCCGT72
VCCGT73

VCCGT74
VCCGT75
VCCGT76
VCCGT77
VCCGT78
VCCGT79
VCCGT159
VCCGT160
VCCGT161
VCCGT162
VCCGT163

11 OF 13

CFL-H_B GA1440

+VCC_G T+VCC_GT

BD35

VCCGT80

BD36

VCCGT81

BE31

VCCGT82

BE32

VCCGT83

BE33

VCCGT84

BE34

VCCGT85

BE35

VCCGT86

BE36

VCCGT87

BE37

VCCGT88

BE38

VCCGT89

BF13

VCCGT90

BF14

VCCGT91

BF29

VCCGT92

BF30

VCCGT93

BF31

VCCGT94

BF32

VCCGT95

BF35

VCCGT96

BF36

VCCGT97

BF37

VCCGT98

BF38

VCCGT99

BG29

VCCGT100

BG30

VCCGT101

BG31

VCCGT102

BG32

VCCGT103

BG33

VCCGT104

BG34

VCCGT105

BG35

VCCGT106

BG36

VCCGT107

BH33

VCCGT108

BH34

VCCGT109

BH35

VCCGT110

BH36

VCCGT111

BH37

VCCGT112

BH38

VCCGT113

BJ16

VCCGT114

BJ17

VCCGT115

BJ19

VCCGT116

BJ20

VCCGT117

BJ21

VCCGT118

BJ23

VCCGT119

BJ24

VCCGT120

BJ26

VCCGT121

BJ27

VCCGT122

BJ37

VCCGT123

BJ38

VCCGT124

BK16

VCCGT125

BK17

VCCGT126

BK19

VCCGT127

BK20

VCCGT128

BK21

VCCGT129

BK23

VCCGT130

BK24

VCCGT131

BK26

VCCGT132

BK27

VCCGT133

BL15

VCCGT134

BL16

VCCGT135

BL17

VCCGT136

BL23

VCCGT137

BL24

VCCGT138

BL25

VCCGT139

BL26

VCCGT140

BL27

VCCGT141

BL28

VCCGT142

BL36

VCCGT143

BL37

VCCGT144

BM15

VCCGT145

BM16

VCCGT146

BM17

VCCGT147

BM36

VCCGT148

BM37

VCCGT149

BN15

VCCGT150

BN16

VCCGT151

BN17

VCCGT152

BN36

VCCGT153

BN37

VCCGT154

BN38

VCCGT155

BP15

VCCGT156

BP16

VCCGT157

BP17

VCCGT158

BR37

VCCGT164

BT15

VCCGT165

BT16

VCCGT166

BT17

VCCGT167

BT37

VCCGT168

VSSGT_ SENSE

VSSGT_SENSE
VCCGT_SENSE

AH37

VCCGT_ SENSE

AH38

1. VccG T_SENSE / VssGT _SENSE Trace Length Match < 25 mils

2. M aintain 25-mil separa tion distance away from any other dyna mic signals.

+VCC_C ORE +VCC_C ORE +VCC_C ORE +VCC_C ORE

AA13
AA31
AA32
AA33
AA34

AA35
AA36
AA37
AA38
AB29
AB30
AB31
AB32
AB35
AB36
AB37

AB38
AC13
AC14

AC29
AC30
AC31
AC32
AC33
AC34

AC35

AC36

AD13
AD14

AD31
AD32
AD33
AD34
AD35
AD36

AD37
AD38

AE13

AE14

AE30

AE31

AE32

AE35

AE36

AE37

AE38

AF29

AF30

AF31

AF32

AF33

AF34

AF35

AF36

AF37

AF38
AG14

AG31

AG32

AG33

AG34
AG35
AG36

CFL-H_B GA1440

VSSGT_ SENSE <56>

VCCGT_ SENSE <56>

UC1I

VCC1
VCC2
VCC3
VCC4
VCC5

VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16

VCC17
VCC18
VCC19

VCC20
VCC21
VCC22
VCC23
VCC24
VCC25

VCC26

VCC27

VCC28
VCC29

VCC30
VCC31
VCC32
VCC33
VCC34
VCC35

VCC36

VCC37
VCC38

VCC39

VCC40
VCC41
VCC42
VCC43
VCC44
VCC45

VCC46
VCC47

VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57

VCC58

VCC59

VCC60

VCC61
VCC62
VCC63

CFL-H

AH13

VCC64

AH14

VCC65

AH29

VCC66

AH30

VCC67

AH31

VCC68

AH32

VCC69

AJ14

VCC70

AJ29

VCC71

AJ30

VCC72

AJ31

VCC73

AJ32

VCC74

AJ33

VCC75

AJ34

VCC76

AJ35

VCC77

AJ36

VCC78

AK31

VCC79

AK32

VCC80

AK33

VCC81

AK34

VCC82

AK35

VCC83

AK36

VCC84

AK37

VCC85

AK38

VCC86

AL13

VCC87

AL29

VCC88

AL30

VCC89

AL31

VCC90

AL32

VCC91

AL35

VCC92

AL36

VCC93

AL37

VCC94

AL38

VCC95

AM13

VCC96

AM14

VCC97

AM29

VCC98

AM30

VCC99

AM31

VCC100

AM32

VCC101

AM33

VCC102

AM34

VCC103

AM35

VCC104

AM36

VCC105

AN13

VCC106

AN14

VCC107

AN31

VCC108

AN32

VCC109

AN33

VCC110

AN34

VCC111

AN35

VCC112

AN36

VCC113

AN37

VCC114

AN38

VCC115

AP13

VCC116

AP30

VCC117

AP31

VCC118

AP32

VCC119

AP35

VCC120

AP36

VCC121

AP37

VCC122

AP38

VCC123

K13

VCC124

VCC_SENSE

9 OF 13

VSS_SENSE

1. Vc c_SENSE/ Vss_SENSE Trace Lengt h Matc h < 25 mi ls

2. M aintain 25-mil separa tion distance away from any other dyna mic signals.

AG37
AG38

128000mA(Hexa Core GT2)

VCCSEN SE
VSSSEN SE

VCCSEN SE <5 6>
VSSSEN SE <56>

K14

L13

L14
N13
N14

N30
N31
N32
N35
N36
N37
N38
P13

P14
P29

P30

P31
P32
P33

P34
P35
P36
R13
R31

R32
R33

R34

R35
R36

R37
R38
T29
T30
T31
T32

T35
T36

T37

T38

U29
U30
U31
U32
U33
U34

U35
U36
V13

V14
V31
V32
V33
V34
V35
V36
V37

V38

W13
W14
W29

W30
W31
W32

CFL-H_B GA1440

UC1J

VCC1
VCC2
VCC3
VCC4
VCC5

VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13

VCC14
VCC15

VCC16

VCC17
VCC18
VCC19

VCC20
VCC21
VCC22
VCC23
VCC24

VCC25

VCC26
VCC27

VCC28
VCC29

VCC30
VCC31
VCC32
VCC33
VCC34

VCC35
VCC36
VCC37
VCC38
VCC39

VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46

VCC47
VCC48
VCC49

VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56

VCC57
VCC58

VCC59

VCC60

VCC61
VCC62
VCC63

CFL-H

10 OF 13

VCC64
VCC65
VCC66
VCC67

VCC68
VCC69
VCC70
VCC71

VCC72
VCC73
VCC74
VCC75

W35
W36
W37
W38

Y29
Y30
Y31
Y32

Y33
Y34
Y35
Y36

1

3

Security Classification

Security Classification

Security Classification

2017/12 /18 2018/09 /01

2017/12 /18 2018/09 /01

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

A

B

2017/12 /18 2018/09 /01

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

CFL-H(6/8)VCC_CORE/GT

CFL-H(6/8)VCC_CORE/GT

CFL-H(6/8)VCC_CORE/GT

Size Document Number Re v

Size Document Number Re v

Size Document Number R ev

Custom

Custom

Custom

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

Dat e: Sheet

Dat e: Sheet

D

Dat e: Sheet of

12 67Thursday, Febru ary 22, 2018

12 67Thursday, Febru ary 22, 2018

o f

12 67Thursday, Febru ary 22, 2018

E

o f

1.0

1.0

1.0

A

+1.2V_VDDQ_CPU

+VCC_S A

+VCC_SA
Max: 11100mA

1

+VCC_IO
Max: 6400mA

2 2

+VCCIO

K29
K30
K31
K32
K33
K34
K35
L31
L32
L35
L36
L37

L38
M29
M30
M31
M32
M33
M34
M35
M36

AG12

G15
G17
G19
G21

H15

H16

H17

H19

H20

H21

H26

H27

J30

J15
J16
J17
J19
J20
J21
J26
J27

CFL-H_B GA1440

UC1L

VCCSA1
VCCSA2
VCCSA3
VCCSA4
VCCSA5
VCCSA6
VCCSA7
VCCSA8
VCCSA9
VCCSA10
VCCSA11
VCCSA12
VCCSA13
VCCSA14
VCCSA15
VCCSA16
VCCSA17
VCCSA18
VCCSA19
VCCSA20
VCCSA21
VCCSA22

VCCIO1
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
VCCIO8
VCCIO9
VCCIO10
VCCIO11
VCCIO12
VCCIO13
VCCIO14
VCCIO15
VCCIO16
VCCIO17
VCCIO18
VCCIO19
VCCIO20
VCCIO21

CFL-H

12 OF 13

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8

VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18
VDDQ19
VDDQ20
VDDQ21
VDDQ22
VDDQ23
VDDQ24
VDDQ25

VCCPLL_OC1
VCCPLL_OC2
VCCPLL_OC3

VCCST

VCCSTG2

VCCSTG1

VCCPLL1
VCCPLL2

VCCSA_SENSE
VSSSA_SENSE

VCCIO_SENSE

VSSIO_SENSE

Max: 3300mA

+1.2V_V DDQ_CPU

AA6
AE12
AF5
AF6
AG5
AG9
AJ12
AL11
AP6
AP7
AR12
AR6
AT12
AW6
AY6
J5
J6
K12
K6
L12
L6
R6
T6
W6
Y12

+1.2V_V CCPLL_OC

BH13
BJ13
G11

H30

H29

G30

H28
J28

M38
M37

H14
J14

B

+1.2V_V DDQ_CPU

JPC1

112

JPC2

112

+1.2V_V DDQ

2

2

VCCSA_ SENSE <57>

VSSSA_ SENSE <5 7>

VCCIO_SE NSE <55>

VSSIO_SE NSE < 55>

+1.2V_VDDQ_CPU

3.3A

@

JUMP_4 3X118

@

JUMP_4 3X118

+1.2V_VCCPLL_OC
Max: 130mA

+1.05V_ VCCST

Max: 60mA

Max: 20mA

Max: 150mA

VCCIO_SE NSE
VSSIO_SE NSE

1. VccG T_SENSE / VssGT _SENSE Trace Length Match < 25 mils

2. M aintain 25-mil separa tion distance away from any other dyna mic signals.

+1.05VS _VCCSTG

+1.05V_ VCCSFR

VCCSA_ SENSE
VSSSA_ SENSE

C

10U_0402_6.3V6M

1

CC70

2

10U_0603_6.3V6M

10U_0603_6.3V6M

1

2

571483_CFL_H_RVP_CRB_TDK_Rev0p5
+1.2V_VDDQ_CPU: 10uF * 12 22uF * 4

1

1

CC72

CC71

2

2

10U_0603_6.3V6M

CC73

10U_0603_6.3V6M

1

CC74

2

RC24 0_040 2_5%@

10U_0402_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

1

1

1

CC76

CC75

2

2

CC77

2

PLACE CAP BACKSIDE

+1.2V_V CCPLL_OC+1.2V_V DDQ

1 2

1

2

571483_CFL_H_RVP_CRB_TDK_Rev0p5
+1.2V_VCCPLL_OC: 1uF * 2

PLACE CAP BACKSIDE

+1.05V_ VCCST

1U_0201_6.3V6M

1

CC92

2

571483_CFL_H_RVP_CRB_TDK_Rev0p5
+1.05V_VCCST: 1uF * 1

10U_0603_6.3V6M

1

CC78

2

1U_0201_6.3V6M

1

CC86

2

RC25 0_040 2_5%@

D

10U_0603_6.3V6M

1

2

1U_0201_6.3V6M

CC87

1

1

1

CC80

CC79

2

2

+VCCIO

2

150mA

10U_0603_6.3V6M

10U_0603_6.3V6M

22U_0603_6.3V6M

1

CC82

CC81

2

10U_0603_6.3V6M

10U_0603_6.3V6M

1

1

CC88

2

2

571483_CFL_H_RVP_CRB_TDK_Rev0p5
+0.95VS_VCCIO: 10uF * 12 22uF * 4

+1.05V_ VCCSFR

1U_0201_6.3V6M

1

CC93

2

571483_CFL_H_RVP_CRB_TDK_Rev0p5
+1.05V_VCCSFR: 1uF * 1

22U_0603_6.3V6M

22U_0603_6.3V6M

1

1

2

1

CC89

2

1

CC84

CC83

2

2

10U_0402_6.3V6M

10U_0603_6.3V6M

@

1

CC91

CC90

2

E

22U_0603_6.3V6M

CC85

PLACE CAP BACKSIDE PLACE CAP BACKSIDE

1

3

4 4

Security Classification

Security Classification

Security Classification

2017/12 /18 2018/09 /01

2017/12 /18 2018/09 /01

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

A

B

2017/12 /18 2018/09 /01

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

+1.05VS _VCCSTG

1U_0201_6.3V6M

1

CC94

2

571483_CFL_H_RVP_CRB_TDK_Rev0p5
+1.05VS_VCCSTG: 1uF * 1

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

CFL-H(7/8)VCCSA/VCCIO/VDDQ

CFL-H(7/8)VCCSA/VCCIO/VDDQ

CFL-H(7/8)VCCSA/VCCIO/VDDQ

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

Dat e: Sheet

Dat e: Sheet of

Dat e: Sheet of

13 67Thursday, Febru ary 22, 2018

13 67Thursday, Febru ary 22, 2018

o f

13 67Thursday, Febru ary 22, 2018

E

1.0

1.0

1.0

3

A

B

C

D

E

CFL-H

UC1F

A10

VSS_1

A12

VSS_2

A16

VSS_3

A18

VSS_4

A20

VSS_5

A22

VSS_6

A24

VSS_7

A26

VSS_8

1

2 2

3

A28
A30

AA12
AA29
AA30
AB33
AB34

AB6
AC1

AC12

AC2

AC3
AC37
AC38

AC4

AC5

AC6
AD10
AD11
AD12
AD29
AD30

AD6

AD8

AD9
AE33
AE34

AE6

AF1
AF12
AF13
AF14

AF2

AF3

AF4
AG10

AG11

AG13
AG29
AG30

AG6

AG7

AG8
AH12
AH33
AH34
AH35
AH36

AH6

AJ1

AJ13

AJ2

AJ3
AJ37
AJ38

AJ4

AJ5

AJ6

Y10

Y11

Y13

Y14

Y37

Y38

AK29
AK30

A6
A9

W4
W5

Y7
Y8
Y9

VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43

VSS_44
VSS_45
VSS_46
VSS_47

VSS_48

VSS_49
VSS_50
VSS_51

VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80

6 OF 13

VSS_81

CFL-H_B GA1440

VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98

VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152

VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162

AK4
AL10
AL12
AL14
AL33
AL34
AL4
AL7
AL8
AL9
AM1
AM12
AM2
AM3
AM37
AM38
AM4
AM5
AN12
AN29
AN30
AN5
AN6
AP10
AP11
AP12
AP33
AP34
AP8
AP9
AR1
AR13
AR14
AR2
AR29
AR3
AR30
AR31
AR32
AR33
AR34
AR35
AR36
AR37
AR38
AR4
AR5
AT29
AT30
AT6
AU10
AU11
AU12
AU33
AU34

AU6
AU7

AU8
AU9
AV37
AV38
AW1
AW12
AW2
AW29
AW3
AW30
AW4
U6
V12

V29
V30
A14
AD7
V6
W1
W12
W2
W3
W33
W34

AW5
AY12
AY33
AY34

BA10
BA11
BA12
BA37
BA38

BA6
BA7
BA8
BA9
BB1

BB12

BB2

BB29

BB3

BB30

BB4
BB5

BB6
BC12
BC13
BC14
BC33
BC34

BC6
BD10
BD11
BD12
BD37

BD6

BD7

BD8

BD9

BE1

BE2
BE29

BE3
BE30

BE4

BE5

BE6

BF12
BF33
BF34

BF6
BG12
BG13
BG14
BG37
BG38

BG6

BH1
BH10
BH11
BH12
BH14

BH2

BH3

BH4

BH5

BH6

BH7

BH8

BH9

T33
T34

U37

U38
BJ12
BJ14

UC1G

VSS_163
VSS_164
VSS_165
VSS_166

B9

VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230

T2

VSS_231

T3

VSS_232
VSS_233
VSS_234

T4

VSS_235

T5

VSS_236

T7

VSS_237

T8

VSS_238

T9

VSS_239
VSS_240
VSS_241
VSS_242
VSS_243

CFL-H_B GA1440

CFL-H

7 OF 13

VSS_244
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
VSS_253
VSS_254
VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261

VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271

VSS_272

VSS_273

VSS_274

VSS_275

VSS_276
VSS_277
VSS_278
VSS_279

VSS_280
VSS_281
VSS_282

VSS_283
VSS_284

VSS_285
VSS_286

VSS_287

VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
VSS_314
VSS_315
VSS_316
VSS_317
VSS_318
VSS_319
VSS_320
VSS_321
VSS_322
VSS_323
VSS_324

BJ15
BJ18
BJ22
BJ25
BJ29
BJ30
BJ31
BJ32
BJ33
BJ34
BJ35
BJ36
BK13
BK14

BK15

BK18
BK22

BK25
BK29
BK6
BL13
BL14
BL18
BL19
BL20
BL21
BL22

BL29
BL33

BL35

BL38

BL6

BM11
BM12
BM13
BM14

BM18
BM2
BM21

BM22

BM23
BM24
BM25

BM26

BM27
BM28
BM29
BM3
BM33
BM35
BM38
BM5

BM6

BM7
BM8
BM9
BN12
BN14
BN18
BN19
BN2
BN20
BN21
BN24
BN29
BN30
BN31
BN34
P38
P6
R12
R29
AY14
BD38
R30
T1
T10
T11
T12
T13
T14

BN4

BN7
BP12
BP14
BP18
BP21
BP24
BP25
BP26
BP29
BP33
BP34

BR12
BR14
BR18
BR21
BR24

BR25
BR26
BR29
BR34

BR36

BR7

BT12
BT14
BT18
BT21
BT24
BT26
BT29
BT32

M14

BP7

BT5
C11
C13
C15

C17
C19
C21
C23
C25
C27
C29
C31
C37

D10
D12
D14
D16
D18
D20
D22
D24
D26
D28

D30
D33

E34
E35
E38

N33
N34

P12
P37

F11
F13

C5
C8
C9

D3

D6
D9

E4
E9
N3

N4
N5
N6
N7
N8
N9

M6

N1

CFL-H

UC1H

VSS_325
VSS_326
VSS_327
VSS_328
VSS_329
VSS_330
VSS_331
VSS_332
VSS_333
VSS_334
VSS_335
VSS_336
VSS_337
VSS_338
VSS_339
VSS_340
VSS_341
VSS_342
VSS_343
VSS_344

VSS_345
VSS_346
VSS_347

VSS_348
VSS_349

VSS_350

VSS_351
VSS_352
VSS_353
VSS_354
VSS_355
VSS_356
VSS_357
VSS_358
VSS_359

VSS_360

VSS_361

VSS_362
VSS_363
VSS_364
VSS_365
VSS_366
VSS_367
VSS_368
VSS_369
VSS_370
VSS_371
VSS_372
VSS_373
VSS_374
VSS_375
VSS_376
VSS_377
VSS_378
VSS_379
VSS_380
VSS_381
VSS_382
VSS_383
VSS_384
VSS_385
VSS_386
VSS_387
VSS_388
VSS_389
VSS_390
VSS_391
VSS_392
VSS_393
VSS_394
VSS_395
VSS_396
VSS_397
VSS_398
VSS_399
VSS_400
VSS_401
VSS_402

VSS_BR38
VSS_403
VSS_404

VSS_BT35

VSS_BT36

VSS_405
VSS_406
VSS_407

8 OF 13

VSS_408

CFL-H_B GA1440

VSS_409
VSS_410
VSS_411
VSS_412

VSS_413
VSS_414
VSS_415

VSS_416
VSS_417
VSS_418
VSS_419
VSS_420
VSS_421
VSS_422
VSS_423
VSS_424
VSS_425
VSS_426
VSS_427
VSS_428
VSS_429
VSS_430
VSS_431
VSS_432
VSS_433
VSS_434
VSS_435
VSS_436
VSS_437
VSS_438
VSS_439
VSS_440
VSS_441
VSS_442
VSS_443
VSS_444
VSS_445
VSS_446
VSS_447
VSS_448
VSS_449
VSS_450
VSS_451
VSS_452
VSS_453
VSS_454
VSS_455
VSS_456
VSS_457
VSS_458
VSS_459
VSS_460
VSS_461
VSS_462
VSS_463
VSS_464
VSS_465
VSS_466
VSS_467
VSS_468
VSS_469
VSS_470
VSS_471
VSS_472
VSS_473
VSS_474
VSS_475
VSS_476
VSS_477
VSS_478
VSS_479

VSS_A3

VSS_A34

VSS_A4
VSS_B3

VSS_B37

VSS_BT3

VSS_BT4

VSS_C2

VSS_D38

F15
F17
F19

F2
F21
F23
F25

F27
F29
F3

F31

F36
F4
F5
F8
F9
G10
G12
G14
G16
G18
G20
G22
G23
G24
G26
G28
G4
G5
G6
G8
G9
H11
H12
H18
H22
H25
H32
H35
J10
J18
J22
J25
J32
J33
J36
J4
J7
K1
K10
K11
K2
K3
K38
K4
K5
K7
K8
K9
L29
L30
L33
L34
M12
M13
N10
N11
N12
N2
BT8
BR9

A3
A34
A4
B3
B37
BR38
BT3
BT35
BT36
BT4
C2
D38

Impedance Spectrum Tool Trigger

PCH_TR IGOUT_R<22>
CPU_TR IGOUT_R<22>

1 2

RC26 30_04 02_5%

TC7TP@

IST_TRIG

TC8TP@

TC9TP@
TC10T P@

TC11T P@
TC12T P@

PCH_TR IGOUT_R
CPU_TR IGOUT

BR1

BT2

BN35

H24
BN33
BL34

N29

R14
AE29
AA14
AP29
AP14

A36

A37

H23

F30

E30

B30

C30

BR35
BR31
BH30

E2
E3
E1
D1

J24

J23

G3

J3

UC1M

RSVD_TP5
IST_TRIG
RSVD_TP4
RSVD_TP3

RSVD_TP1
RSVD_TP2

RSVD15

RSVD28
RSVD27
RSVD14
RSVD13

RSVD30
RSVD31
RSVD2
RSVD1
RSVD5
RSVD4
VSS_A36

VSS_A37

PROC_TRIGIN
PROC_TRIGOUT

RSVD24

RSVD23

RSVD7
RSVD21

RSVD26
RSVD29

RSVD19
RSVD18
RSVD9

CFL-H_B GA1440

CFL-H

13 OF 13

BK28

RSVD11

BJ28

RSVD10

BL31

RSVD12

AJ8

RSVD3

G13

RSVD25

C38

RSVD22

C1

RSVD20

BR2

RSVD17

BP1

RSVD16

B38

RSVD8

B2

RSVD6

Add for Corner NCTF testing

TC13 TP @
TC14 TP @
TC15 TP @
TC16 TP @
TC17 TP @
TC18 TP @

1

3

4 4

Security Classification

Security Classification

Security Classification

2017/12 /18 2018/09 /01

2017/12 /18 2018/09 /01

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

A

B

2017/12 /18 2018/09 /01

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

CFL-H(8/8)GND/RSVD

CFL-H(8/8)GND/RSVD

CFL-H(8/8)GND/RSVD

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

Dat e: Sheet

Dat e: Sheet of

D

Dat e: Sheet

14 67Thursday, Febru ary 22, 2018

o f

14 67Thursday, Febru ary 22, 2018

14 67Thursday, Febru ary 22, 2018

E

o f

1.0

1.0

1.0

A

DMI_CTX_ PRX_N0<10>

DMI_CTX_ PRX_P0<10>
DMI_CRX_ PTX_N0<10>
DMI_CRX_ PTX_P0<10>

DMI_CTX_ PRX_N1<10>

DMI_CTX_ PRX_P1<10>
DMI_CRX_ PTX_N1<10>
DMI_CRX_ PTX_P1<10>

DMI_CTX_ PRX_N2<10>

DMI_CTX_ PRX_P2<10>

1

2 2

3

DMI_CRX_ PTX_N2<10>

DMI_CRX_ PTX_P2<10>

DMI_CTX_ PRX_N3<10>

DMI_CTX_ PRX_P3<10>

DMI_CRX_ PTX_N3<10>

DMI_CRX_ PTX_P3<10>

B

DMI_CTX_ PRX_N0

DMI_CTX_ PRX_P0
DMI_CRX_ PTX_N0
DMI_CRX_ PTX_P0

DMI_CTX_ PRX_N1

DMI_CTX_ PRX_P1
DMI_CRX_ PTX_N1
DMI_CRX_ PTX_P1

DMI_CTX_ PRX_N2

DMI_CTX_ PRX_P2
DMI_CRX_ PTX_N2
DMI_CRX_ PTX_P2

DMI_CTX_ PRX_N3

DMI_CTX_ PRX_P3

DMI_CRX_ PTX_N3
DMI_CRX_ PTX_P3

UH1B

K34

DMI0_RXN

J35

DMI0_RXP

C33

DMI0_TXN

B33

DMI0_TXP

G33

DMI1_RXN

F34

DMI1_RXP

C32

DMI1_TXN

B32

DMI1_TXP

K32

DMI2_RXN

J32

DMI2_RXP

C31

DMI2_TXN

B31

DMI2_TXP

G30

DMI3_RXN

F30

DMI3_RXP

C29

DMI3_TXN

B29

DMI3_TXP

A25

RSVD

B25

RSVD

P24

RSVD

R24

RSVD

C26

RSVD

B26

RSVD

F26

RSVD

G26

RSVD

B27

RSVD

C27

RSVD

L26

RSVD

M26

RSVD

D29

RSVD

E28

RSVD

K29

RSVD

M29

RSVD

G17

PCIE1_RXN/USB31_7_RXN

F16

PCIE1_RXP/USB31_7_RXP

A17

PCIE1_TXN/USB31_7_TXN

B17

PCIE1_TXP/USB31_7_TXP

R21

PCIE2_RXN/USB31_8_RXN

P21

PCIE2_RXP/USB31_8_RXP

B18

PCIE2_TXN/USB31_8_TXN

C18

PCIE2_TXP/USB31_8_TXP

K18

PCIE3_RXN/USB31_9_RXN

J18

PCIE3_RXP/USB31_9_RXP

B19

PCIE3_TXN/USB31_9_TXN

C19

PCIE3_TXP/USB31_9_TXP

N18

PCIE4_RXN/USB31_10_RXN

R18

PCIE4_RXP/USB31_10_RXP

D20

PCIE4_TXN/USB31_10_TXN

C20

PCIE4_TXP/USB31_10_TXP

F20

PCIE5_RXN

G20

PCIE5_RXP

B21

PCIE5_TXN

A22

PCIE5_TXP

K21

PCIE6_RXN

J21

PCIE6_RXP

D21

PCIE6_TXN

C21

PCIE6_TXP

B23

PCIE7_TXP

C23

PCIE7_TXN

J24

PCIE7_RXP

L24

PCIE7_RXN

F24

PCIE8_RXN

G24

PCIE8_RXP

B24

PCIE8_TXN

C24

PCIE8_TXP

CNP-H_B GA874

C

CNP-H

GPP_E9/USB2_OC0#
GPP_E10/USB2_OC1#
GPP_E11/USB2_OC2#
GPP_E12/USB2_OC3#
GPP_F15/USB2_OC4#
GPP_F16/USB2_OC5#
GPP_F17/USB2_OC6#
GPP_F18/USB2_OC7#

USB2_VBUSSENSE

2 OF 13

USB2N_1
USB2P_1
USB2N_2

USB2P_2
USB2N_3
USB2P_3

USB2N_4
USB2P_4
USB2N_5
USB2P_5
USB2N_6
USB2P_6
USB2N_7
USB2P_7
USB2N_8
USB2P_8
USB2N_9

USB2P_9
USB2N_10
USB2P_10
USB2N_11
USB2P_11
USB2N_12
USB2P_12
USB2N_13
USB2P_13
USB2N_14
USB2P_14

USB2_COMP

RSVD1

USB2_ID

GPD7

PCIE24_TXP
PCIE24_TXN
PCIE24_RXP
PCIE24_RXN

PCIE23_TXP
PCIE23_TXN
PCIE23_RXP
PCIE23_RXN

PCIE22_TXP
PCIE22_TXN
PCIE22_RXP
PCIE22_RXN

PCIE21_TXP
PCIE21_TXN
PCIE21_RXP
PCIE21_RXN

Rev1.0

J3
J2

N13
N15
K4
K3

M10
L9
M1

L2

K7
K6
L4
L3
G4
G5
M6
N8
H3
H2
R10
P9
G1
G2
N3
N2
E5
F6

AH36
AL40
AJ44
AL41
AV47
AR35
AR37
AV43

F4
F3
U13
G3

BE41

G45
G46
Y41
Y40
G48
G49
W44
W43
H48
H47
U41
U40
F46
G47
R44
T43

D

USB20_ N1
USB20_ P1
USB20_ N2
USB20_ P2
USB20_ N3
USB20_ P3
USB20_ N4
USB20_ P4
USB20_ N5
USB20_ P5
USB20_ N6
USB20_ P6

USB20_ N8
USB20_ P8

USB20_ N14
USB20_ P14

USB_OC 0#
USB_OC 1#
USB_OC 2#
USB_OC 3#

USB2_R COMP
USB2_V BUS_SENSE

USB2_ID

GPD_7

The 30 HSIO lanes on PCH-H supports the following configurations:

1. Up to 24 PCIe* Lanes

— A maximum of 16 PCIe* Ports (or devices) can be enabled

When a GbE Port is enabled, the maximum number of PCIe* Ports (or



devices) that can be enabled reduces based off the following:
Max PCIe* Ports (or devices) = 16 - GbE (0 or 1)
— PCIe* Lanes 1-4 (PCIe* Controller #1), 5-8 (PCIe* Controller #2), 9-12 (PCIe*
Controller #3), 13-16 (PCIe* Controller #4), 17-20 (PCIe* Controller #5), and
21-24 (PCIe* Controller #6) can be individually configured

2. Up to 6 SATA Lanes
— A maximum of 6 SATA Ports (or devices) can be enabled
— SATA Lane 0 has the flexibility to be mapped to Flex I/O Lane 16 or 18
— SATA Lane 1 has the flexibility to be mapped to Flex I/O Lane 17 or 19

3. Up to 10 USB 3.1 Lanes
— A maximum of 10 USB 3.1 Ports (or devices) can be enabled

4. Up to 4 GbE Lanes
— A maximum of 1 GbE Port (or device) can be enabled

5. Supports up to 3 Remapped (IntelR Rapid Storage Technology) PCIe* storage
device s
— x2 and x4 PCIe* NVMe SSD
— x2 IntelR Optane? Memory Device
— See the “ PCI Express * (PCIe*)” chapt er for t he P CH PCI e* Controllers,configurations
, and lanes that can be used for IntelR Rapid Storage Technology PCIe* storage support

6. For unused SATA/PCIe* Combo Lanes, Flex I/O Lanes that can be configured as PCIe* or SATA,
the lanes must be statically assigned to SATA or PCIe* via the SATA/PCIe Combo Port Soft
Straps discussed in the SPI Programming Guide and
through the IntelR Flash Image Tool (FIT) tool.

USB20_ N1 <42>
USB20_ P1 <42>
USB20_ N2 <41>
USB20_ P2 <41>
USB20_ N3 <44>
USB20_ P3 <44>
USB20_ N4 <44>
USB20_ P4 <44>
USB20_ N5 <33>
USB20_ P5 <33>
USB20_ N6 <33>
USB20_ P6 <33>

USB20_ N8 <46>
USB20_ P8 <46>

USB20_ N14 <37 >
USB20_ P14 <37>

USB_OC 0# <40>

USB_OC 1# <42>

1 2

RH4 113_040 2_1%
RH5 0_0402_ 5%@

RH6 0_0402_ 5%@

1

1 2

2

USB3 MB

TYPE C

USB2 (SUB/B)

Cam er a

TS

FingerPrint

FOR CNVI follow 571906_CNL_PCH_TA_WW11.pdf

BT

USB_OC 0#
USB_OC 1#
USB_OC 2#
USB_OC 3#

STRAP

E

RPH1

10K_08 04_8P4R_5%

GPD_7

X'tal Input:
High: Differential
Low: Single ended

+3VALW _PCH_PR IM

18
27
36
45

+3VALW

1

RH3
10K_04 02_5%

2

1

RH7
10K_04 02_5%

@

2

1

3

4 4

Security Classification

Security Classification

Security Classification

2017/12 /18 2018/09 /01

2017/12 /18 2018/09 /01

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

A

B

2017/12 /18 2018/09 /01

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

PCH(1/8)DMI/PCIE/USB2

PCH(1/8)DMI/PCIE/USB2

PCH(1/8)DMI/PCIE/USB2

Size Document Number R ev

Size Document Number R ev

Size Document Number R ev

Custom

Custom

Custom

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

Dat e: Sheet of

Dat e: Sheet of

D

Dat e: Sheet of

15 67Thursday, Febru ary 22, 2018

15 67Thursday, Febru ary 22, 2018

15 67Thursday, Febru ary 22, 2018

E

1.0

1.0

1.0

A

B

C

D

E

PCH-H XTAL_IN/OUT POR is 24MHz for 571697_CNL_MOW_WW16_2017.pdf

RH8 1M_040 2_5%

YH1
24MHZ_ 18PF_XRCGB 24M000F2P5 1R0

1

2 2

3

4 4

3

33P_0402_50V8J

3

CH5

10P_0402_50V8J

1

32.768K HZ_9PF_X1A 0001410002 00

CH7

2

+3VS

For DDX03 R02

+1.8VAL W_PRIM

RH15 4.7K_0 402_5%

This signal has a weak internal pul l-down 20K.
0 = 38.4/19.2MHz XTAL frequency sel ected.
1 = 24MHz XTAL frequency selected. (DDX03)
Notes:

1. The internal pull-down is disabl ed after RSMRST#
de-asserts.

2. This signal is in the primary we ll.

+1.8VAL W_PRIM

RH21 4.7K_0 402_5%

The signal has a weak internal pull -down 20K
0 = VCCPSPI is connected to 3.3V ra il
1 = VCCPSPI is connected to 1.8V ra il
Note: If VCCPSPI is connected to 1. 8V rail, this pin

strap must be a ‘ 1’ fo r th e proper functionalit y
of the SPI (Flash) I/Os

+1.8VAL W_PRIM

RH22 10K_04 02_5%

RH23 10K_04 02_5%@

XTAL_2 4M_PCH_OUT

NC

2

XTAL_2 4M_PCH_IN

1

1

1 2

NC

4

1 2

RH12 10M_0402 _5%

YH2

1 2

Trace Space: 15 mil
Max Trace Length: 1000 mil

1 2

EMC@

RH11 33 _0402_1%

1 2

EMC@

RH9 33_ 0402_1%

18P_0402_50V8J

CH6

PCH_RT CX1

PCH_RT CX2

10P_0402_50V8J

1

CH8

2

use same part w C5MMH

RPH2

7

5

10K_08 04_8P4R_5%

XTAL Frequency Select

1 2

VCCPSPI Select

1

2

An external pull-up or pull-down is required.
0 = Integrated CNVi enable.
1 = Integrated CNVi disable.

Pulled down by CRF CNVi RGI_DT pin

LAN_CL KREQ#

18

VGA_CL KREQ#

2

WLA N_CLKREQ#

36

SSD_CL KREQ#

4

@

2

M.2 CNV Mode Select

12

1

A

CNV_BR I_PTX_DRX

GPP_J9

CNV_RG I_PTX_DRX

XTAL_2 4M_PCH_OUT _R

XTAL_2 4M_PCH_IN_R

VGA_CL KREQ# <25>

STRAP

STRAP

STRAP

PCH_CP U_24M_CLK_ P<11>
PCH_CP U_24M_CLK_ N<11>

PCH_CP U_BCLK_P<11>
PCH_CP U_BCLK_N<11> PCH_CP U_PCIBCLK_P <1 1>

1

XCLK_BIASREF (PDG)
Trace Width/Space: 15mil /15 mil
Max Trace Length: 1000 mil
8/24

RH10 60.4_0 402_1%

2

LAN_CL KREQ#<36>

WLA N_CLKREQ#<37>

SSD_CL KREQ#< 35>

remove no use srcclkreq

remove SD signal from PCH

remove CPU_C10_GATE#

CNV_BR I_PTX_DRX<37>
CNV_BR I_PRX_DTX<37>
CNV_RG I_PTX_DRX<37>
CNV_RG I_PRX_DTX<37>

+1.8VAL W_PRIM

1 2

RH181 20K_0 402_1%CNVI@

571391_CFL_H_PDG_Rev0p71
To avoid floating input at the I/O pin BRI_RSP and RGI_RSP it is recommen ded to add
a weak pull up resistor to the SoC pin with a recommended value of 20K oh m.

B

RH182 20K_0 402_1%CNVI@

2

1

remove TP as C5PRH

PCH_CP U_24M_CLK_ P
PCH_CP U_24M_CLK_ N

PCH_CP U_BCLK_P
PCH_CP U_BCLK_N

XTAL_2 4M_PCH_OUT _R
XTAL_2 4M_PCH_IN_R

XCLK_B IASREF

PCH_RT CX1
PCH_RT CX2

VGA_CL KREQ#
LAN_CL KREQ#
WLA N_CLKREQ#

SSD_CL KREQ#

AW13

BE9
BF8
BF9

BG8

BE8

BD8

AV13

AP3
AP2
AN4

AM7

AV6
AY3

AR13

AV7

AW3

CNV_BR I_PTX_DRX

CNV_BR I_PRX_DTX
CNV_RG I_PTX_DRX
CNV_RG I_PRX_DTX

GPP_J9

CNV_BR I_PRX_DTX

CNV_RG I_PRX_DTX

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

AT10

AV4
AY2
BA4
AV3

AW2

AU9

2017/12 /18 2018/09 /01

2017/12 /18 2018/09 /01

2017/12 /18 2018/09 /01

C

UH1G

BE33

GPP_A16/CLKOUT_48

D7

CLKOUT_CPUNSSC_P

C6

CLKOUT_CPUNSSC#

B8

CLKOUT_CPUBCLK_P

C8

CLKOUT_CPUBCLK#

U9

XTAL_OUT

U10

XTAL_IN

T3

XCLK_BIASREF

BA49

RTCX1

BA48

RTCX2

BF31

GPP_B5/SRCCLKREQ0#

BE31

GPP_B6/SRCCLKREQ1#

AR32

GPP_B7/SRCCLKREQ2#

BB30

GPP_B8/SRCCLKREQ3#

BA30

GPP_B9/SRCCLKREQ4#

AN29

GPP_B10/SRCCLKREQ5#

AE47

GPP_H0/SRCCLKREQ6#

AC48

GPP_H1/SRCCLKREQ7#

AE41

GPP_H2/SRCCLKREQ8#

AF48

GPP_H3/SRCCLKREQ9#

AC41

GPP_H4/SRCCLKREQ10#

AC39

GPP_H5/SRCCLKREQ11#

AE39

GPP_H6/SRCCLKREQ12#

AB48

GPP_H7/SRCCLKREQ13#

AC44

GPP_H8/SRCCLKREQ14#

AC43

GPP_H9/SRCCLKREQ15#

V2

CLKOUT_PCIE_N15

V3

CLKOUT_PCIE_P15

T2

CLKOUT_PCIE_N14

T1

CLKOUT_PCIE_P14

AA1

CLKOUT_PCIE_N13

Y2

CLKOUT_PCIE_P13

AC7

CLKOUT_PCIE_N12

AC6

CLKOUT_PCIE_P12

CNP-H_B GA874

UH1M

GPP_G0/SD_CMD
GPP_G1/SD_DATA0
GPP_G2/SD_DATA1
GPP_G3/SD_DATA2
GPP_G4/SD_DATA3
GPP_G5/SD_CD#
GPP_G6/SD_CLK
GPP_G7/SD_WP

GPP_I11/M2_SKT2_CFG0
GPP_I12/M2_SKT2_CFG1
GPP_I13/M2_SKT2_CFG2
GPP_I14/M2_SKT2_CFG3

GPP_J0/CNV_PA_BLANKING
GPP_J1/CPU_C10_GATE#
GPP_J11/A4WP_PRESENT
GPP_J10
GPP_J_2
GPP_J_3
GPP_J4/CNV_BRI_DT/UART0B_RTS#
GPP_J5/CNV_BRI_RSP/UART0B_RXD
GPP_J6/CNV_RGI_DT/UART0B_TXD
GPP_J7/CNV_RGI_RSP/UART0B_CTS#
GPP_J8/CNV_MFUART2_RXD
GPP_J9/CNV_MFUART2_TXD

CNP-H_B GA874

Compal Secret Data

Compal Secret Data

Compal Secret Data

CNP-H

CLKOUT_ITPXDP#

CLKOUT_ITPXDP_P

CLKOUT_CPUPCIBCLK#

CLKOUT_CPUPCIBCLK_P

CLKOUT_PCIE_N0
CLKOUT_PCIE_P0

CLKOUT_PCIE_N1
CLKOUT_PCIE_P1

CLKOUT_PCIE_N2
CLKOUT_PCIE_P2

CLKOUT_PCIE_N3
CLKOUT_PCIE_P3

CLKOUT_PCIE_N4
CLKOUT_PCIE_P4

CLKOUT_PCIE_N5
CLKOUT_PCIE_P5

CLKOUT_PCIE_N6
CLKOUT_PCIE_P6

CLKOUT_PCIE_N7
CLKOUT_PCIE_P7

CLKOUT_PCIE_N8
CLKOUT_PCIE_P8

CLKOUT_PCIE_N9
CLKOUT_PCIE_P9

CLKOUT_PCIE_N10
CLKOUT_PCIE_P10

CLKOUT_PCIE_N11
CLKOUT_PCIE_P11

7 OF 13

CNP-H

3.3V

1.8V

13 OF 13

Deciphered Date

Deciphered Date

Deciphered Date

Y3
Y4

B6
A6

AJ6
AJ7

AH9
AH10

AE14
AE15

AE6
AE7

AC2
AC3

AB2
AB3

W4
W3

W7
W6

AC14
AC15

U2
U3

AC9
AC11

AE9
AE11

CLKIN_XTAL

GPPJ_RCOMP_1P81
GPPJ_RCOMP_1P82
GPPJ_RCOMP_1P83

R6

Rev1.0

CNV_WR_CLKN
CNV_WR_CLKP

CNV_WR_D0N
CNV_WR_D0P
CNV_WR_D1N
CNV_WR_D1P

CNV_WT_CLKN
CNV_WT_CLKP

CNV_WT_D0N
CNV_WT_D0P
CNV_WT_D1N
CNV_WT_D1P

CNV_WT_RCOMP

PCIE_RCOMPN

PCIE_RCOMPP
SD_1P8_RCOMP
SD_3P3_RCOMP

RSVD2
RSVD3

RSVD1

Rev1.0

PCH_CP U_PCIBCLK_N
PCH_CP U_PCIBCLK_P

CLK_PE G_VGA#
CLK_PE G_VGA

CLK_PC IE_LAN#
CLK_PC IE_LAN

CLK_PC IE_WLAN#
CLK_PC IE_WLAN

CLK_PC IE_NGFF#
CLK_PC IE_NGFF

BD4
BE3

BB3
BB4
BA3
BA2

BC5
BB6

BE6
BD7
BG6
BF6
BA1

B12
A13
BE5
BE4
BD1
BE1
BE2

Y35
Y36

BC1
AL35

TP

D

TH2TP@
TH3TP@

REFCLK _CNV

1

RH14

10K_04 02_5%

2

CLK_CN V_PRX_DTX_ N
CLK_CN V_PRX_DTX_ P

CNV_PR X_DTX_N0
CNV_PR X_DTX_P0
CNV_PR X_DTX_N1
CNV_PR X_DTX_P1

CLK_CN V_PTX_DRX_ N

CLK_CN V_PTX_DRX_ P

CNV_PT X_DRX_N0
CNV_PT X_DRX_P0
CNV_PT X_DRX_N1
CNV_PT X_DRX_P1

CNV_W T_RCOMP

PCIE_RCO MPN
PCIE_RCO MPP

SD_RCO MP_1P8
SD_RCO MP_3P3

GPPJ_R COMP_1P8

RH16

RH17 100_0 402_1%

RH18 200_0 402_1%
RH19 200_0 402_1%

RH20 200_0 402_1%

#571483_CFL_H_RVP_CRB_TDK_Rev0p5
Recommend external test point

Title

Title

Title

Size Document Number R ev

Size Document Number R ev

Size Document Number R ev

Custom

Custom

Custom

Dat e: Sheet of

Dat e: Sheet of

Dat e: Sheet

PCH_CP U_PCIBCLK_N <11>

CLK_PEG_VGA# <25>

CLK_PEG_VGA <25>

CLK_PC IE_LAN# <36>

CLK_PC IE_LAN <36>

CLK_PC IE_WLAN# <37>

CLK_PC IE_WLAN < 37>

CLK_PC IE_NGFF# <35>
CLK_PC IE_NGFF <35>

REFCLK _CNV <37>

CNV_PR X_DTX_N0 < 37>
CNV_PR X_DTX_P0 <37 >
CNV_PR X_DTX_N1 < 37>
CNV_PR X_DTX_P1 <37 >

CNV_PT X_DRX_N0 <3 7>
CNV_PT X_DRX_P0 <37>
CNV_PT X_DRX_N1 <3 7>

2

1

1

1
1 2

1 2

TH4TP@

150_04 02_1%

2

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

PCH(2/8)CLK/CNVI/SD

PCH(2/8)CLK/CNVI/SD

PCH(2/8)CLK/CNVI/SD

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

CNV_PT X_DRX_P1 <37>

checked CRB

E

DGPU

GLAN

NGFF WL+BT(KEY E)

M2 SSD

CLK_CN V_PRX_DTX_ N <37>
CLK_CN V_PRX_DTX_ P <3 7>

CLK_CN V_PTX_DRX_ N <37>
CLK_CN V_PTX_DRX_ P <3 7>

o f

16 67Thursday, Febru ary 22, 2018

16 67Thursday, Febru ary 22, 2018

16 67Thursday, Febru ary 22, 2018

1.0

1.0

1.0

1

3

A

UH1E

no follow naming

can remove if no use DP
08/18

remove PCH DP SCLK/SDATA

DDP[B..F]CTRLDATA
This signal has a weak internal Pul l-down.
0 = Port B~D is not detected.
1 = Port B,C,D is detected. (Defau lt)
Notes:

1. The internal Pull-down is disabl ed after
PCH_PWROK de-asserts.

2. This signal is in the primary we ll.

* wait confirm CG7
PDG P348 quad mode support PH1K

+3VALW _SPI

+3VALW _PCH_PR IM

1 1

CRB PU 20k
#571182_CF L_PCH_EDS_ Rev1.0 re commend 100k

#571391_CFL_H_PDG_Rev0p71

RH25 1K_04 02_5%

RH26 1K_04 02_5%

RH27 1K_04 02_5%

RH29 100K_ 0402_5%

#571182_CNL_PCH_H_EDS_V1_Rev0.7
External pull-up is required. Recom mend 100K if pulled
up to 3.3V or 75K if pulled up to 1 .8V.
571007_CFL_MOW_Archive_WW22_2017
STUFF R on GPP_H15

PCH_SP I_CLK

1

2

12

12

12

RH195 100K_ 0201_5%

PCH_SP I_IO2

PCH_SP I_IO3

PCH_SP I_SI

GPP_H1 5

1

2

@

STRAP

HDMI_HPD _PCH<25 ,34>

EDP_HP D<25,33>

EC_PME #<36,39>

RH24 0_ 0402_5%

CRB connect GND

1 2

@

1 2

RH186 0_040 2_5%@

TH6 TP@

HDMI_HPD _PCH

EDP_HP D

EC_PME #_R

PCH_SP I_SI
PCH_SP I_SO
PCH_SP I_CS#0
PCH_SP I_CLK

PCH_SP I_IO2
PCH_SP I_IO3

AT6

GPP_I0/DDPB_HPD0/DISP_MISC0

AN10

GPP_I1/DDPC_HPD1/DISP_MISC1

AP9

GPP_I2/DDPD_HPD2/DISP_MISC2

AL15

GPP_I3/DDPF_HPD3/DISP_MISC3

AN6

GPP_I4/EDP_HPD/DISP_MISC4

CNP-H_B GA874

UH1A

BE36

GPP_A11/PME#/SD_VDD2_PWR_EN#

R15

RSVD2

R13

RSVD1

AL37

VSS

AN35

TP

AU41

SPI0_MOSI

BA45

SPI0_MISO

AY47

SPI0_CS0#

AW47

SPI0_CLK

AW48

SPI0_CS1#

AY48

SPI0_IO2

BA46

SPI0_IO3

AT40

SPI0_CS2#

BE19

GPP_D1/SPI1_CLK/SBK1_BK1

BF19

GPP_D0/SPI1_CS#/SBK0_BK0

BF18

GPP_D3/SPI1_MOSI/SBK3_BK3

BE18

GPP_D2/SPI1_MISO/SBK2_BK2

BC17

GPP_D22/SPI1_IO3

BD17

GPP_D21/SPI1_IO2

CNP-H_B GA874

CNP-H

5 OF 13

CNP-H

GPP_K15/GSXSRESET#

GPP_H18/SML4ALERT#

GPP_H15/SML3ALERT#

GPP_H12/SML2ALERT#

1 OF 13

GPP_I5/DDPB_CTRLCLK

GPP_I6/DDPB_CTRLDATA

GPP_I7/DDPC_CTRLCLK

GPP_I8/DDPC_CTRLDATA

GPP_I9/DDPD_CTRLCLK

GPP_I10/DDPD_CTRLDATA

GPP_F23/DDPF_CTRLDATA

GPP_F22/DDPF_CTRLCLK

GPP_F14/PS_ON#

GPP_K23/IMGCLKOUT1
GPP_K22/IMGCLKOUT0

GPP_H23/TIME_SYNC0

GPP_B13/PLTRST#

GPP_K16/GSXCLK

GPP_K12/GSXDOUT

GPP_K13/GSXSLOAD

GPP_K14/GSXDIN

GPP_E3/CPU_GP0
GPP_E7/CPU_GP1
GPP_B3/CPU_GP2
GPP_B4/CPU_GP3

GPP_H17/SML4DATA

GPP_H16/SML4CLK

GPP_H14/SML3DATA

GPP_H13/SML3CLK

GPP_H11/SML2DATA

GPP_H10/SML2CLK

INTRUDER#

Rev1.0

GPP_K21
GPP_K20

AL13
AR8
AN13
AL10
AL9
AR3
AN40
AT49

AP41

M45
L48
T45
T46
AJ47

Rev1.0

AV29

Y47
Y46
Y48
W46
AA45

AL47
AM45
BF32
BC33

AE44
AJ46
AE43
AC47
AD48
AF47
AB47
AD47
AE48

BB44

remove CIO_PLUG_EVENT#

PLT_RS T#

TP_INT#

TYPEC_1P 5A

GPP_H1 5

GPP_H1 2

SM_INTRU DER#

RVP: 330K
A 1 M pull-up is used on the custom er reference
board (CRB). This is needed to redu ce leakage
from Coin Cell Battery in G3 state.

PLT_RS T# <25,39 ,45>

GPIO Serial Expander (GSX) is the c apability
provided by the PCH to expand the G PIOs
on a platform that needs more GPIOs than the
ones provided by the PCH.

12

DH1
RB751V -40_SOD323-2

GPP_H1 2 < 20>

EC_TP_INT# <3 9,45>

TYPEC_1P 5A <4 0>

+RTCVC C

12

RH301M_0402_5 %

intel critical net recommend

1

RH198 100K_ 0201_5%

PLT_RS T#

1 2

CH9 100P_0 402_50V8J

XEMC@

TP_INT#

RH28 100K_ 0402_5%

2

+3VS

12

intel critical net recommend

SPI ROM ( 16MByte )

PCH_SP I_CS#0

PCH_SP I_IO2_0_R

UH2

1

/CS

2

DO(IO1)

3

/WP(IO2)

4

GND

W25 Q128FVSIQ_SO 8

P/N: SA00005VV20

PCH_SP I_CLK_0_R

@

1 2

RH33
0_0402 _5%

note : 1050 Use 8M rom

VCC

/HOLD(IO3)

CLK

DI(IO0)

+3VALW _SPI

CH10 0.1U_0201 _10V6K

8

PCH_SP I_IO3_0_RPCH_SP I_SO_0_R

7

PCH_SP I_CLK_0_R

6

PCH_SP I_SI_0_R

5

@

1 2

CH12
68P_04 02_50V8J

2

1

PCH_SP I_SI_0_R
PCH_SP I_SO_0_R

PCH_SP I_IO3_0_R
PCH_SP I_CLK_0_R

PCH_SP I_IO2_0_R

sch checklist 0.7
1 device 15 ohm / 2 device 33 ohm

PCH_SP I_CS#0

RH107 49.9_ 0402_1%
RH108 49.9_ 0402_1%
RH109 49.9_ 0402_1%
RH110 49.9_ 0402_1%
RH111 49.9_ 0402_1%

1

RH31 4.7 K_0402_5%

1 2
1 2
1
1 2
1

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

+3VALW _SPI

2

@

PCH_SP I_SI
PCH_SP I_SO

2

2

PCH_SP I_IO3
PCH_SP I_CLK

PCH_SP I_IO2

Compal Secret Data

Compal Secret Data

2017/12 /18 2018/09 /01

2017/12 /18 2018/09 /01

2017/12 /18 2018/09 /01

A

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

PCH PLTRST Buffer

PLT_RS T#

1 2

RH32 0_040 2_5%@

+3VS

1

B

2

A

1

2

CH11

0.1U_04 02_10V6K

5

UH3

P

4

Y

G

TC7SH0 8FU_SSOP5

3

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

PCH(3/8)DDC/SPI

PCH(3/8)DDC/SPI

PCH(3/8)DDC/SPI

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

Dat e: Sheet

Dat e: Sheet o f

Dat e: Sheet

PLT_RS T_BUF# <3 5,36,37>

1.0

1.0

1.0

17 67Thursday, Febru ary 22, 2018

17 67Thursday, Febru ary 22, 2018

o f

17 67Thursday, Febru ary 22, 2018

o f

A

USB3 MB

1

USB3 Type C

USB3 SUB

USB3 Type C

USB3 SUB

B

UH1F

USB3_P TX_DRX_N1<42>
USB3_P TX_DRX_P1<42>
USB3_P RX_DTX_N1<42>
USB3_P RX_DTX_P1<42>

USB3_P TX_DRX_N2<41>
USB3_P TX_DRX_P2<41>
USB3_P RX_DTX_N2<41>

USB3_P RX_DTX_P2<41>

USB3_P TX_DRX_N5<44>
USB3_P TX_DRX_P5<44>
USB3_P RX_DTX_N5<44>
USB3_P RX_DTX_P5<44>

USB3_P TX_DRX_P3<41>
USB3_P TX_DRX_N3<41>
USB3_P RX_DTX_P3<41>
USB3_P RX_DTX_N3<41>

USB3_P TX_DRX_P4<44>
USB3_P TX_DRX_N4<44>
USB3_P RX_DTX_P4<44>
USB3_P RX_DTX_N4<44>

F9

F7
D11
C11

C3
D4
B9
C9

C17
C16
G14

F14

C15

B15

J13

K13

G12

F11

C10

B10

C14

B14

J15

K16

CNP-H_B GA874

USB31_1_TXN
USB31_1_TXP
USB31_1_RXN
USB31_1_RXP

USB31_2_TXN
USB31_2_TXP
USB31_2_RXN
USB31_2_RXP

USB31_6_TXN
USB31_6_TXP
USB31_6_RXN
USB31_6_RXP
USB31_5_TXN
USB31_5_TXP
USB31_5_RXN
USB31_5_RXP

USB31_3_TXP
USB31_3_TXN
USB31_3_RXP
USB31_3_RXN

USB31_4_TXP
USB31_4_TXN
USB31_4_RXP
USB31_4_RXN

1.8V
(eSPI)

GPP_A7/PIRQA#/ESPI_ALERT0#

GPP_A14/SUS_STAT#/ESPI_RESET#

GPP_A9/CLKOUT_LPC0/ESPI_CLK

C

CNP-H

GPP_A1/LAD0/ESPI_IO0
GPP_A2/LAD1/ESPI_IO1
GPP_A3/LAD2/ESPI_IO2
GPP_A4/LAD3/ESPI_IO3

GPP_A5/LFRAME#/ESPI_CS0#

GPP_A6/SERIRQ/ESPI_CS1#

GPP_A0/RCIN#/ESPI_ALERT1#

GPP_A10/CLKOUT_LPC1

GPP_K19/SMI#
GPP_K18/NMI#

GPP_E6/SATA_DEVSLP2
GPP_E5/SATA_DEVSLP1
GPP_E4/SATA_DEVSLP0
GPP_F9/SATA_DEVSLP7
GPP_F8/SATA_DEVSLP6
GPP_F7/SATA_DEVSLP5
GPP_F6/SATA_DEVSLP4
GPP_F5/SATA_DEVSLP3

6 OF 13

Rev1.0

BB39
AW37
AV37
BA38

BE38
AW35
BA36
BE39
BF38

BB36
BB34

T48
T47

AH40
AH35
AL48
AP47
AN37
AN46
AR47
AP48

#571391_CFL_H_PDG_Rev0p5

eSPI clock and eSPI data mismatched: <500 mils.



eSPI clock and eSPI chip select mismatched: <500 mils.



eSPI signal maximum 9 Vias



* If DATA signals are entirely rout ed on MS, stuff the resistor with 15 Oh m.

LPC_AD 0

LPC_AD 1

LPC_AD 2
LPC_AD 3

LPC_FR AME#
TPM_SE RIRQ
LPC_PIRQ A#

ESPI_RST #

CLK_LP C
CLK_LP C_TPM

SSD_DE VSLP1

RH35 22_04 02_5%
RH36 22_04 02_5%

D

LPC_AD 0 <39,45 >
LPC_AD 1 <39,45 >
LPC_AD 2 <39,45 >
LPC_AD 3 <39,45 >

LPC_FR AME# <3 9,45>
TPM_SE RIRQ <39,4 5>

12

12

TPM@

SSD_DE VSLP1 < 35>

LPC Bus

LPC : +3.3V

ESPI_RST # <39>

CLK_LP C_R < 39>
CLK_LP C_TPM_R < 45>

1A modify

E

check straps

1

+3VS

2 2

For Intel CLINK

TH10 TP@
TH11 TP@
TH12 TP@

CL_CLK
CL_DAT A
CL_RST #

1A modify

PCIE_PTX _DRX_P11<35>

M.2 SSD PCIE L1

3

GLAN

PCIE_PTX _C_DRX_N14< 36>

PCIE_PTX _C_DRX_P14<36>

PCIE_PRX_DTX_N1 4<36>
PCIE_PRX_DTX_P1 4<36>

CH3 .1U_040 2_16V7K
CH4 .1U_040 2_16V7K

M.2 SSD PCIE L0

PCIE_PTX _DRX_N11<35>
PCIE_PRX _DTX_P11<35>
PCIE_PRX _DTX_N11<35>

DGPU_P RSNT#

12
12

PCIE_PTX _DRX_P12<35>
PCIE_PTX _DRX_N12<35>
PCIE_PRX _DTX_P12<35>
PCIE_PRX _DTX_N12<35>

PCIE_PTX _DRX_N14
PCIE_PTX _DRX_P14

PCIE_PRX _DTX_N14
PCIE_PRX _DTX_P14

1A modify

+3VALW _PCH_PR IM

1

RH43

10K_04 02_5%

4 4

UMA@

2

DGPU_P RSNT#

UH1C

AR2

CL_CLK

AT5

CL_DATA

AU4

CL_RST#

P48

GPP_K8

V47

GPP_K9

V48

GPP_K10

W47

GPP_K11

L47

GPP_K0

L46

GPP_K1

U48

GPP_K2

U47

GPP_K3

N48

GPP_K4

N47

GPP_K5

P47

GPP_K6

R46

GPP_K7

C36

PCIE11_TXP/SATA0A_TXP

B36

PCIE11_TXN/SATA0A_TXN

F39

PCIE11_RXP/SATA0A_RXP

G38

PCIE11_RXN/SATA0A_RXN

AR42

GPP_F10/SATA_SCLOCK

AR48

GPP_F11/SATA_SLOAD

AU47

GPP_F13/SATA_SDATAOUT0

AU46

GPP_F12/SATA_SDATAOUT1

C39

PCIE14_TXN/SATA1B_TXN

D39

PCIE14_TXP/SATA1B_TXP

D46

PCIE14_RXN/SATA1B_RXN

C47

PCIE14_RXP/SATA1B_RXP

B38

PCIE13_TXN/SATA0B_TXN

C38

PCIE13_TXP/SATA0B_TXP

C45

PCIE13_RXN/SATA0B_RXN

C46

PCIE13_RXP/SATA0B_RXP

E37

PCIE12_TXP/SATA1A_TXP

D38

PCIE12_TXN/SATA1A_TXN

J41

PCIE12_RXP/SATA_1A_RXP

H42

PCIE12_RXN/SATA1A_RXN

B44

PCIE20_TXP/SATA7_TXP

A44

PCIE20_TXN/SATA7_TXN

R37

PCIE20_RXP/SATA7_RXP

R35

PCIE20_RXN/SATA7_RXN

D43

PCIE19_TXP/SATA6_TXP

C44

PCIE19_TXN/SATA6_TXN

N42

PCIE19_RXP/SATA6_RXP

M44

PCIE19_RXN/SATA6_RXN

CNP-H_B GA874

CNP-H

PCIE9_RXN
PCIE9_RXP
PCIE9_TXN

PCIE9_TXP

PCIE10_RXN
PCIE10_RXP

PCIE10_TXN
PCIE10_TXP

PCIE15_RXN/SATA2_RXN

PCIE15_RXP/SATA2_RXP

PCIE_15_SATA_2_TXN

PCIE15_TXP/SATA2_TXP

PCIE16_RXN/SATA3_RXN

PCIE16_RXP/SATA3_RXP
PCIE16_TXN/SATA3_TXN

PCIE16_TXP/SATA3_TXP

PCIE17_RXN/SATA4_RXN

PCIE17_RXP/SATA4_RXP
PCIE17_TXN/SATA4_TXN

PCIE17_TXP/SATA4_TXP

PCIE18_RXN/SATA5_RXN

PCIE18_RXP/SATA5_RXP
PCIE18_TXN/SATA5_TXN

PCIE18_TXP/SATA5_TXP

GPP_E8/SATA_LED#

GPP_E0/SATAXPCIE0/SATAGP0
GPP_E1/SATAXPCIE1/SATAGP1
GPP_E2/SATAXPCIE2/SATAGP2

GPP_F0/SATAXPCIE3/SATAGP_3

GPP_F1/SATAXPCIE4/SATAGP4
GPP_F2/SATAXPCIE5/SATAGP5
GPP_F3/SATAXPCIE6/SATAGP6
GPP_F4/SATAXPCIE7/SATAGP7

GPP_F21/EDP_BKLTCTL

GPP_F20/EDP_BKLTEN

GPP_F19/EDP_VDDEN

THRMTRIP#

PECI

PM_SYNC

3 OF 13

PLTRST_CPU#

PM_DOWN

Rev1.0

G36
F36
C34
D34

K37
J37
C35
B35

F44
E45
B40
C40

L41
M40
B41
C41

K43
K44
A42
B42

P41
R40
C42
D42

AK48

AH41
AJ43
AK47
AN47

RH187 10K_0402 _5%PBA @

AM46
AM43
AM47
AM48

AU48
AV46
AV44

AD3
AF2
AF3
AG5
AE2

PCIE_PRX _DTX_N9
PCIE_PRX _DTX_P9
PCIE_PTX _DRX_N9
PCIE_PTX _DRX_P9

PCIE_PRX _DTX_N10

PCIE_PRX _DTX_P10
PCIE_PTX _DRX_N10
PCIE_PTX _DRX_P10

PCIE_PRX _DTX_N15
PCIE_PRX _DTX_P15
PCIE_PTX _DRX_N15
PCIE_PTX _DRX_P15

SATA_P RX_DTX_N4
SATA_P RX_DTX_P4
SATA_P TX_DRX_N4
SATA_P TX_DRX_P4

1A modify

1

SATA_G P5

PCH_BK L_PWM
ENBKL

PCH_EN VDD

PCH_TH ERMTRIP#
PCH_PE CI

H_PM_S YNC
H_PLTR ST_CPU#
H_PM_D OWN_R

1A modify

1 2
1

SATA_P RX_DTX_N4 < 43>

SATA_P RX_DTX_P4 <43 >
SATA_P TX_DRX_N4 < 43>

SATA_P TX_DRX_P4 <43 >

1A modify

2

TH13T P@

1 2

RH40 620_0 402_5%

RH41 13_04 02_5%

RH42 30_04 02_5%

1

@

1 2

2

PCIE_PRX _DTX_N9 < 35>
PCIE_PRX _DTX_P9 <35>
PCIE_PTX _DRX_N9 < 35>

PCIE_PTX _DRX_P9 <35 >

PCIE_PRX _DTX_N10 <35>
PCIE_PRX _DTX_P10 <35 >
PCIE_PTX _DRX_N10 <35>

PCIE_PTX _DRX_P10 <3 5>

PCIE_PRX_DTX_N1 5 <37>

CH1.1 U_0402_16V 7K

2

CH2.1 U_0402_16V 7K

SATA_G P1 <35>

PCH_BK L_PWM <25,33>
ENBKL <25,39>

PCH_EN VDD <25,33 >

PCIE_PRX_DTX_P1 5 <37>
PCIE_PTX _C_DRX_N15 <37>

PCIE_PTX _C_DRX_P15 <37>

#571391_CFL_H_PDG_Rev0p5.pdf

H_PECI
H_PM_S YNC_R

M.2 SSD PCIE L3

M.2 SSD PCIE L2

HDD

PCH_TH ERMTRIP#_R <11>
H_PECI <11,3 9>
H_PM_S YNC_R <11 >
H_PLTR ST_CPU# <11>
H_PM_D OWN_R <11>

TPM_SE RIRQ

LPC_PIRQ A#

NGFF
WL+BT(KEY E)

SATA_G P1

2

RH39 10K_0 402_5%

M.2 SSD PCIE/SATA select pin

H_PECI

2

10K_04 02_5%

1 2

10K_04 02_5%

1

XEMC@

2

1

1

RH37

RH38

+3VS

CH500.1U_0402_ 10V6K

3

RH44

10K_04 02_5%

1

VGA@

2

DIS,Optimus10

UMA

A

GPP_F1 3

DGPU_PRSNT#

Security Classification

Security Classification

Security Classification

2017/12 /18 2018/09 /01

2017/12 /18 2018/09 /01

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

B

2017/12 /18 2018/09 /01

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

PCIE/SATA/USB3/eSPI

PCIE/SATA/USB3/eSPI

PCIE/SATA/USB3/eSPI

Size Document Number R ev

Size Document Number R ev

Size Document Number R ev

Custom

Custom

Custom

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

Dat e: Sheet o f

Dat e: Sheet o f

D

Dat e: Sheet o f

18 67Thursday, Febru ary 22, 2018

18 67Thursday, Febru ary 22, 2018

18 67Thursday, Febru ary 22, 2018

E

1.0

1.0

1.0

A

1 2

ME_EN<39>

HDA_RS T#_R<38>
HDA_BIT_ CLK_R< 38>
HDA_SD OUT_R<38>
HDA_SYNC _R<38>

1

RPH7

1 8
2 7
3 6
4 5

33_080 4_8P4R_5%

@

RH45 0_ 0402_5%

HDA_RS T#

HDA_BIT_ CLK
HDA_SD OUT
HDA_SYNC

HDA_BIT_ CLK

12

RH196100K_ 0201_5%

HDA_RS T#

12

RH197100K_ 0201_5%

intel critical net recommend

del RF reserve cap on HDA

CPU_DISP A_SDO_R< 7>

CPU_DISP A_SDI_R<7>

FOR Jefferson Peak RESET pin is glitch free,it
is recommended that a pull-down resistor of 75K
ohm on GPP_D5(CNV_RF_RESET#)

+RTCVC C

1 2

RH50 20K_0 402_1%

1 2

2 2

3

+3VS

+3VALW _PCH_PR IM

4 4

CH18 1U_04 02_6.3V6K

1

RH52 20K_0 402_1%

1

CH19 1U_04 02_6.3V6K

1 2

JCMOS1 0_0603 _5%@

+3VALW _DSW

2

RH55 1K_04 02_5%

2

RH56 8.2K_0 402_5%

RH57 100K_ 0402_5%@

RH58 100K_ 0402_5%@

2

RH60 8.2K_0 402_5%

RH191 2.2K_ 0402_5%
RH192 2.2K_ 0402_5%

RPH11

5

2.2K_08 04_8P4R_5%

1

RH63 499_04 02_1%

1 2

RH64 499_04 02_1%

1

1

12

12

2

A

2

2

1

12
12

PCH_SM BCLK

18

PCH_SM BDATA

27

PCH_SM L1CLK

36

PCH_SM L1DATA

4

PCH_SM L0CLK

PCH_SM L0DATA

CPU_DISP A_BCLK_R<7>

PCH_SR TCRST#

CLR ME
Delay 18~25 ms

PCH_RT CRST#

ECLR CMOS
Delay 18~25 ms

WAK E#

PM_BAT LOW#

AC_PRE SENT_R

PBTN_O UT#_R

PM_CLK RUN#

D_CK_S CLK
D_CK_S DATA

2N7002 KDW_SOT 363-6

PCH_SM BCLK

HDA_SD IN0<38>

RH48

1 2

RH49

1 2

CLKREQ _CNV#<3 7>

CNV_RF _RESET#< 37>
PCH_DM IC_DATA0<38>
PCH_DM IC_CLK0<38>

TH22 TP@

TH24 TP@

PCH_RT CRST#<39>

PCH_PW ROK<39,47>
EC_RSM RST#<39>

PCH_SM BALERT#<20>

PCH_SM L0ALERT#<20>

PCH_SM L1ALERT#<20>

QH7B

2N7002 KDW_SOT 363-6

PCH_SM L1CLK

PCH_SM L1DATA

B

30_040 2_5%

30_040 2_5%

+3VS

5

G

3

4

S

D

QH7A

6 1

1

RH189 0_0 402_5%

1 2

RH190 0_0 402_5%

B

2

G

D

2

@

@

HDA_BIT_ CLK
HDA_SD IN0
HDA_SD OUT
HDA_SYNC

HDA_RS T#

CPU_DISP A_SDO
CPU_DISP A_SDI_R
CPU_DISP A_BCLK

CLKREQ _CNV#
CNV_RF _RESET#

PCH_RT CRST#

PCH_SR TCRST#

PCH_PW ROK
EC_RSM RST#

PCH_DP WROK

PCH_SM BALERT#
PCH_SM BCLK
PCH_SM BDATA

PCH_SM L0ALERT#
PCH_SM L0CLK
PCH_SM L0DATA
PCH_SM L1ALERT#
PCH_SM L1CLK
PCH_SM L1DATA

D_CK_S CLK

D_CK_S DATAPC H_SMBDATA

S

Security Classification

Security Classification

Security Classification

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

UH1D

BD11

HDA_BCLK/I2S0_SCLK

BE11

HDA_SDI0/I2S0_RXD

BF12

HDA_SDO/I2S0_TXD

BG13

HDA_SYNC/I2S0_SFRM

BE10

HDA_RST#/I2S1_SCLK

BF10

HDA_SDI1/I2S1_RXD

BE12

I2S1_TXD/SNDW2_DATA

BD12

I2S1_SFRM/SNDW2_CLK

AM2

HDACPU_SDO

AN3

HDACPU_SDI

AM3

HDACPU_SCLK

AV18

GPP_D8/I2S2_SCLK

AW18

GPP_D7/I2S2_RXD

BA17

GPP_D6/I2S2_TXD/MODEM_CLKREQ

BE16

GPP_D5/I2S2_SFRM/CNV_RF_RESET#

BF15

GPP_D20/DMIC_DATA0/SNDW4_DATA

BD16

GPP_D19/DMIC_CLK0/SNDW4_CLK

AV16

GPP_D18/DMIC_DATA1/SNDW3_DATA

AW15

GPP_D17/DMIC_CLK1/SNDW3_CLK

BE47

RTCRST#

BD46

SRTCRST#

AY42

PCH_PWROK

BA47

RSMRST#

AW41

DSW_PWROK

BE25

GPP_C2/SMBALERT#

BE26

GPP_C0/SMBCLK

BF26

GPP_C1/SMBDATA

BF24

GPP_C5/SML0ALERT#

BF25

GPP_C3/SML0CLK

BE24

GPP_C4/SML0DATA

BD33

GPP_B23/SML1ALERT#/PCHHOT#

BF27

GPP_C6/SML1CLK

BE27

GPP_C7/SML1DATA

CNP-H_B GA874

(DDR,G -Se nsor )

D_CK_S CLK < 23,24,43>

D_CK_S DATA <2 3,24,43>

EC_SMB _CK2 <25,3 9,40,44>

(EC, VGA)

EC_SMB _DA2 <25,3 9,40,44>

Issued Date

Issued Date

Issued Date

C

CNP-H

GPP_A12/BM_BUSY#/ISH_GP6/SX_EXIT_HOLDOFF#

GPP_B1/GSPI1_CS1#/TIME_SYNC1

1.8V

GPP_A13/SUSWARN#/SUSPWRDNACK

4 OF 13

Compal Secret Data

Compal Secret Data

2017/12 /18 2018/09 /01

2017/12 /18 2018/09 /01

2017/12 /18 2018/09 /01

C

Compal Secret Data

GPP_A8/CLKRUN#

GPD11/LANPHYPC

GPD9/SLP_WLAN#

DRAM_RESET#

GPP_B2/VRALERT#

GPP_B0/GSPI0_CS1#

GPP_K17/ADR_COMPLETE

GPP_B11/I2S_MCLK

GPD6/SLP_A#

GPP_B12/SLP_S0#

GPD4/SLP_S3#
GPD5/SLP_S4#

GPD10/SLP_S5#

GPD8/SUSCLK

GPD0/BATLOW#

GPP_A15/SUSACK#

GPD2/LAN_WAKE#
GPD1/ACPRESENT

GPD3/PWRBTN#

GPP_B14/SPKR

PCH_JTAG_TMS
PCH_JTAG_TDO

PCH_JTAG_TDI

PCH_JTAG_TCK

+3VALW _DSW

+3VALW _PCH_PR IM

POP on 1A version

0.1U_04 02_10V6K

Deciphered Date

Deciphered Date

Deciphered Date

SYS_PWROK

SYS_RESET#

CPUPWRGD

ITP_PMODE
PCH_JTAGX

RH183 10K _0402_5%

BF36
AV32

BF41

BD42

BB46

BE32
BF33

BE29

R47
AP29
AU3

BB47

WAKE#

BE40
BF40

SLP_LAN#

BC28

BF42
BE42
BC42

BE45
BF44
BE35

BC37

BG44
BG42
BD39

SLP_SUS#

BE46
AU2

AW29

AE3

AL3
AH4
AJ4
AH3
AH2

AJ3

Rev1.0

RPH8

18
2

7

36
45

10K_08 04_8P4R_5%

12

1 2

RH184100K_0 402_5% @

1 2

RH61100K_0 402_5% @

XEMC@

1

2

CH200.1U_0402_ 10V6K

XEMC@

2

1

CH21

XEMC@

2

1

CH220.1U_0402_ 10V6K

XEMC@

1 2

CH510.1U_0402_ 10V6K

From ESD Te am R equest

Near PCH side

D

DRAM_R ESET#

PM_CLK RUN#

LAN_DISA BLE_N

SLP_W LAN#

DRAM_R ESET#
PCH_VR ALERT#
TYPEC_3A
LAN_GP O

PCH_GP P_K17
PCH_GP P_B11

SYS_PW ROK

WAK E#

PM_SLP _A#
SLP_LA N#
PM_SLP _S0#
PM_SLP _S3#
PM_SLP _S4#
PM_SLP _S5#

SUSCLK
PM_BAT LOW#

SUSACK #_R

1 2

RH51 0_ 0402_5%

LAN_W AKE#
AC_PRE SENT_R
SLP_SU S#
PBTN_O UT#_R
SYS_RESE T#

PCH_SP KR

H_CPUP WRGD

XDP_ITP_ PMODE

CPU_XD P_TCK0
CPU_XD P_TMS
CPU_XD P_TDO
CPU_XD P_TDI
PCH_JT AG_TCK1

PCH_PW ROK
LAN_W AKE#
EC_RSM RST#

SYS_RESE T#

SYS_PW ROK

PCH_DP WROK

SYS_RESE T#

SYS_PW ROK

PCH_PW ROK

EC_RSM RST#

D

+1.2V_V DDQ

@

1 2

RH53 0_ 0402_5%

1 2

RH54 0_ 0402_5%

H_CPUP WRGD < 11>

EC_RSM RST#

PCH_VR ALERT#

Custom

Custom

Custom

Dat e: Sheet o f

Dat e: Sheet

Dat e: Sheet o f

E

2

RH46
470_04 02_1%

1

1 2

RH47 0_0402 _5%

1

2

CH13 1U_040 2_6.3V6K

PM_CLK RUN# <45>

TH14TP@

TH15TP@

TYPEC_3A <40>
LAN_GP O < 36>

TH19TP@

TH20TP@

SYS_PW ROK <39,47>

TH37TP@

TH21TP@

PM_SLP _S0# <39 >
PM_SLP _S3# <39 ,47>

PM_SLP _S4# <39 ,47>

TH23TP@

T207TP@

SUSPW RDNACK <39>

@

TP@

@

PCH_SP KR <2 0,38>

PBTN_O UT#

T208

T209

TP@

CPU_XD P_TCK0 <1 1>

CPU_XD P_TMS < 11>
CPU_XD P_TDO <1 1>

CPU_XD P_TDI < 11>

PCH_JT AG_TCK1 <11>

PM_SLP _S3#
PM_SLP _S4#

@

SUSCLK <35,37 >

AC_PRE SENT

--No Support Deep Sx

1 2

RH193 100K_ 0201_5%

1

RH194 100K_ 0201_5%

DDR_DR AMRST#_R <23,24>

AC_PRE SENT <3 9>

PBTN_O UT# < 39>

Connect CPU & PCH

2

intel critical net recommend

1

2

@

RH59 0_ 0402_5%

1

2

RH62 10K_0 402_5%@

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

PCH(5/8)PMU/HDA/SMBUS/DMIC

PCH(5/8)PMU/HDA/SMBUS/DMIC

PCH(5/8)PMU/HDA/SMBUS/DMIC

Size Document Number R ev

Size Document Number R ev

Size Document Number R ev

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

PCH_DP WROK

+3VALW _PCH_PR IM

E

o f

19 67Thursday, Febru ary 22, 2018

19 67Thursday, Febru ary 22, 2018

19 67Thursday, Febru ary 22, 2018

1.0

1.0

1.0

1

3

+3VALW _PCH_PR IM

Vinafix

1 8
2 7
3
4

+3VS

RH66 10K_04 02_5%@

1

2 2

3

4 4

RH68 49.9K_0 402_1%

RH69 49.9K_0 402_1%

RH70 49.9K_0 402_1%@

RH71 49.9K_0 402_1%@

RH72 10K_04 02_5%VGA@

RH73 10K_04 02_5%VGA@

+3VALW _PCH_PR IM

1 2

RH74 4.7K_0 402_5%@

This signal has a weak internal pul l-down.
0 = Master Attached Flash Sharing ( MAFS) enabled (Default)
1 = Slave Attached Flash Sharing (S AFS) enabled.
Notes:

1. This signal is in the primary we ll.

Warning: This strap must be configured to ‘ 0’ if the
eSPI or LPC strap is configured to ‘ 0’

+3VALW _PCH_PR IM

+3VS

A

RPH12

2.2K_08 04_8P4R_5%

1 2

1

RH112 4.7K_0 402_5%@

RH113 4.7K_0 402_5%@

RH114 150K _0402_1%

*

RH77 4.7K_0 402_5%@

The signal has a weak internal Pull -down.

0 = Disable “ No Reboot” mode. (Default)
1 = Enable “ No Reboot” mod e (PCH wil l disable th e
TCO Timer system reboot feature). This function is
useful when running ITP/XDP.
Notes:

1. The internal Pull-down is disabled after
PCH_PWROK is high.

2. This signal is in the primary well.

RH80 150K_ 0402_1%

This Signal has a weak internal Pul l-down.
0: SPI (Default)
1: LPC
Notes:

1. The internal Pull-down is disabl ed after PCH_PWROK is high.

2. This signal is in the primary we ll.

RH83 100K_ 0402_5%@

Top Swap Override

0 = Disable “ Top Swap” mode. (Default)
1 = Enable “ Top Swap” mode.
The internal Pull-down is disabled after PCH_PWROK is high.

I2C_1_SC L
I2C_1_SD A

I2C_0_SC L

6

I2C_0_SD A

5

12

12

12

12

12

2

1 2

SMBALERT# / GPP_C2 has a weak int ernal Pull-down.
0 = Disable Intel ME (TLS) (D efault)
1 = Enable Intel ME (TLS)

1

2

SML0ALERT# / GPP_C5 has a weak in ternal Pull-down.
0 = LPC is selected (for EC 9022).
1 = eSPI is selected

1 2

SML1ALERT# / GPP_B23 has an inter nal pull-down.
0 = Disable IntelR DCI-OOB (Default )
1 = Enable IntelR DCI-OOB

1

2

@

1 2

12

EC_SCI# GC6_FB _EN3V3 GC6_FB _EN

UART_2 _PRXD_DTXD

UART_2 _PTXD_DRXD

UART_2 _PRTS_DCTS

UART_2 _PCTS_DRTS

DGPU_P WR_EN

DGPU_H OLD_RST#

GPP_H1 2

GSPI0_MO SI

check needed?

CG11 connect to GPP_B15

GPP_H1 2 <1 7>

PCH_SM BALERT# <19>

PCH_SM L0ALERT# <19>

PCH_SM L1ALERT# <19>

GSPI1_MO SI

PCH_SP KR

GC6_FB _EN3V3<25>

STRAP

STRAP

STRAP

PCH_SP KR <1 9,38>

STRAP

B

<Touch PAD>

STRAP

GSPI1_MO SI

1 2

EC_SCI#

GSPI0_MO SI

EC_SCI#<39>

RH67 0_0402 _5%@

TS_EN<33,39>

check for remove (PCH or Both)

DGPU_A C_DETECT<39,50>

GPU_EVENT#<25>

DGPU_H OLD_RST#<25>

DGPU_P WR_EN<25,29>

UART_2 _PTXD_DRXD<37>

UART_2 _PRXD_DTXD<37>

I2C_1_SC L<4 5>

I2C_1_SD A<45>

pop for avoid floating

1.0 Modify

Reserved
Reserved
for 8 Layer

※

no t e : 00 /01 us ed f or 1050

EVT

10 used for 1060 EVT

TS_EN

DGPU_A C_DETECT

GPU_EV ENT#

DGPU_H OLD_RST#
DGPU_P WR_EN

UART_2 _PCTS_DRTS
UART_2 _PRTS_DCTS

UART_2 _PTXD_DRXD
UART_2 _PRXD_DTXD

I2C_1_SC L
I2C_1_SD A

I2C_0_SC L
I2C_0_SD A

VGA_ID1

VGA_ID2

C

UH1K

BA26

GPP_B22/GSPI1_MOSI

BD30

GPP_B21/GSPI1_MISO

AU26

GPP_B20/GSPI1_CLK

AW26

GPP_B19/GSPI1_CS0#

BE30

GPP_B18/GSPI0_MOSI

BD29

GPP_B17/GSPI0_MISO

BF29

GPP_B16/GSPI0_CLK

BB26

GPP_B15/GSPI0_CS0#

BB24

GPP_C9/UART0A_TXD

BE23

GPP_C8/UART0A_RXD

AP24

GPP_C11/UART0A_CTS#

BA24

GPP_C10/UART0A_RTS#

BD21

GPP_C15/UART1_CTS#/ISH_UART1_CTS#

AW24

GPP_C14/UART1_RTS#/ISH_UART1_RTS#

AP21

GPP_C13/UART1_TXD/ISH_UART1_TXD

AU24

GPP_C12/UART1_RXD/ISH_UART1_RXD

AV21

GPP_C23/UART2_CTS#

AW21

GPP_C22/UART2_RTS#

BE20

GPP_C21/UART2_TXD

BD20

GPP_C20/UART2_RXD

BE21

GPP_C19/I2C1_SCL

BF21

GPP_C18/I2C1_SDA

BC22

GPP_C17/I2C0_SCL

BF23

GPP_C16/I2C0_SDA

BE15

GPP_D4/ISH_I2C2_SDA/I2C3_SDA/SBK4_BK4

BE14

GPP_D23/ISH_I2C2_SCL/I2C3_SCL

CNP-H_B GA874

+1.8VAL W_PRIM

1 2

RH84 1K_040 2_5%@

1 2

RH85 10K_04 02_5%

1

RH86 1K_040 2_5%@

RH87 10K_04 02_5%

2

1 2

GPP_D10 GPP_D9

0

CNP-H

GPP_D9/ISH_SPI_CS#/GSPI2_CS0#

GPP_D11/ISH_SPI_MISO/GP_BSSB_CLK/GSPI2_MISO

GPP_D12/ISH_SPI_MOSI/GP_BSSB_DI/GSPI2_MOSI

GPP_D15/ISH_UART0_RTS#/GSPI2_CS1#/CNV_WFEN

GPP_D10/ISH_SPI_CLK/GSPI2_CLK

GPP_D16/ISH_UART0_CTS#/CNV_WCEN

GPP_D14/ISH_UART0_TXD/I2C2_SCL

GPP_D13/ISH_UART0_RXD/I2C2_SDA

GPP_A17/SD_VDD1_PWR_EN#/ISH_GP7

11 OF 13

PROJEC T_ID0

PROJEC T_ID1

Project ID

00
1
01
11

DH53F(1060 WO RD)Reserved
DH53F(1060 W RD)

*

DH5VF(1050 WO RD)

*

DH5VF(1050 W RD)

SCI capability is available on all GPIOs
PCH GPIOs that can be routed to gen erate SMI# or NMI:

GPP_B14, GPP_B20, GPP_B23



GPP_C[23:22]



GPP_D[4:0]



GPP_E[8:0]



GPP_I[3:0]



GPP_G[7:0] (support SMI# only).



The voltage of all GPIO pads in eac h GPP group is determined by the voltag e supplied to the group (either 3.3V o r 1.8V),
except for GPP_I and GPD group, (wh ich are 3.3V only), and GPP_J group (wh ich is 1.8V only).

All GPIOs have programmable interna l pull-up/pull-down resistors which are off by default.
The internal pull-up/pull-down for each GPIO can be enabled by BIOS progra mming.

D

GPP_H20/ISH_I2C0_SCL
GPP_H19/ISH_I2C0_SDA

GPP_H22/ISH_I2C1_SCL
GPP_H21/ISH_I2C1_SDA

GPP_A23/ISH_GP5
GPP_A22/ISH_GP4
GPP_A21/ISH_GP3
GPP_A20/ISH_GP2
GPP_A19/ISH_GP1
GPP_A18/ISH_GP0

Rev1.0

1 2

RH88 1K_040 2_5%

SATARD @

1

RH89 10K_04 02_5%S ATANRD@

1 2

RH90 1K_040 2_5%

1

RH91 10K_04 02_5%@

0 0
0
1
1 1

BA20
BB20
BB16
AN18

BF14
AR18
BF17
BE17

AG45
AH46

AH47
AH48

AV34
AW32
BA33
BE34
BD34
BF35
BD38

2

2

VGA_ID1
VGA_ID2
PROJEC T_ID0
PROJEC T_ID1

SUB_DE T

G_INT
CODEC_ ID

FOR 4 DMIC @256

CODEC_ ID

CODEC_ID / GPP_A19
0 = 2 DIMC @255 (Default)
1 = 4 DIMC @256

FOR 40 PIN SUB/B

SUB_DE T

+1.8VAL W_PRIM

Project_ID0Project_ID1

GPP_D11GPP_D12

1
0

1

RH188 1K_0 402_5%256@

1 2

RH185 1K_0 402_5%@

2

+3VS

2

1

2

@

1

E

GSEN@

RH78
10K_04 02_5%

G_INT

RH79

100K_0 402_5%

+3VALW _PCH_PR IM

+1.8VAL W_PRIM

G_INT < 43>

1

3

Security Classification

Security Classification

Security Classification

2017/12 /18 2018/09 /01

2017/12 /18 2018/09 /01

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

A

B

2017/12 /18 2018/09 /01

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

PCH(6/8)GPIO/I2C/UART/STRAP

PCH(6/8)GPIO/I2C/UART/STRAP

PCH(6/8)GPIO/I2C/UART/STRAP

Size Document Number R ev

Size Document Number R ev

Size Document Number R ev

Custom

Custom

Custom

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

Dat e: Sheet o f

Dat e: Sheet o f

D

Dat e: Sheet o f

20 67Thursday, Febru ary 22, 2018

20 67Thursday, Febru ary 22, 2018

20 67Thursday, Febru ary 22, 2018

E

1.0

1.0

1.0

A

B

C

D

E

GPIO Group Vol tag e

+1.05VALW

JPH1

@

2

112

JUMP_43X79

1

JPH2

@

2

112

JUMP_43X79

+1.05VALW_ PCH_PRIM

5.95A

1U_0402_6.3V6K

1

CH23

2

+1.05VALW_ VCCMPHY

6.6A

22U_0402_6.3V6M

1

CH25

2

HSIO for DMIU/USB3.1/PCIE=4162mA

+1.05VALW_ VCCMPHY

1U_0402_6.3V6K

1

CH26

2

+1.05VALW_ PCH

3-5MM FROM PACKAGE EDGE

1

RH94

pop for intel sensitive net (1.0)

+1.05VALW_ PCH

2 2

place near VCCDUSB
FOR W22/W23

1-5MM FROM PACKAGE EDGE
FOR VCCAPLL C1/C2

3 3

+1.05VALW_ PCH

0.1U_0402_10V6K

1

2

+1.05VALW_ PCH

1U_0402_6.3V6K

1

2

CH33

1

2

2

0_0603_5 %

CH29

1-3MM FROM PACKAGE EDGE
FOR VCCA_BCLK V19

1 2

RH102 0_0 402_5%

1P_0402_50V8

CH43

@

+1.05VALW_ PCH

+1.05VALW_ PCH +1.05V_VCCD SW

0.1U_0402_10V6K

1

CH30

2

1-3MM FROM PACKAGE
VCCPRIM_MPHY W31

1-3MM FROM PACKAGE EDGE

pop for intel sensitive net (1.0)

+1.05VALW_ PCH

0.1U_0402_10V6K

1

CH34

2

1-5MM FROM PACKAGE EDGE
FOR VCCAPLL B1/B2/B3

+1.05VALW_ VCCAZPLL

1P_0402_50V8

1

CH44

2

@

1U_0402_6.3V6K

1

2

+1.05VALW_ PCH

1U_0402_6.3V6K

1

2

CH31

CH35

+1.05V_VCCD SW

+1.05VALW_ VCCAZPLL

+1.05VALW_ VCCAMPHYPLL

+1.05VALW_ XTAL

+1.05VALW_ PCH_PRIM

5.95A

6.6A

0.0012A

0.2A

0.42A

0.109A

0.015A

0.213A

0.00428A

0.169A

0.0198A

0.0085A

0.021A

+3VALW +3VALW_PC H_PRIM

RH97 0_0805_ 5%

RH99 0_0402 _5%

1P_0402_50V8

1

CH41

2

@

AA22
AA23
AB20
AB22
AB23
AB27
AB28
AB30
AD20
AD23
AD27
AD28

AD30
AF23

AF27
AF30

U26
U29
V25
V27
V28
V30
V31

AD31

AE17

W22
W23

BG45
BG46

W31

D1
E1

C49

D49
E49

P2

P3
W19
W20

C1

C2

V19

B1

B2

B3

1 2

1 2

UH1H

VCCPRIM_1P051
VCCPRIM_1P052
VCCPRIM_1P053
VCCPRIM_1P054
VCCPRIM_1P055
VCCPRIM_1P056
VCCPRIM_1P057
VCCPRIM_1P058
VCCPRIM_1P059
VCCPRIM_1P0510
VCCPRIM_1P0511
VCCPRIM_1P0512

VCCPRIM_1P0513
VCCPRIM_1P0516

VCCPRIM_1P0517
VCCPRIM_1P0518

VCCPRIM_1P0523
VCCPRIM_1P0524
VCCPRIM_1P0525
VCCPRIM_1P0526
VCCPRIM_1P0527
VCCPRIM_1P0528
VCCPRIM_1P0529

VCCPRIM_1P0514

VCCPRIM_1P0515

VCCDUSB_1P051
VCCDUSB_1P052

VCCDSW_1P051
VCCDSW_1P052

VCCPRIM_MPHY_1P05

VCCPRIM_1P0521
VCCPRIM_1P0522

VCCAMPHYPLL_1P051
VCCAMPHYPLL_1P052

VCCAMPHYPLL_1P053

VCCA_XTAL_1P051
VCCA_XTAL_1P052
VCCA_SRC_1P051
VCCA_SRC_1P052

VCCAPLL_1P054

VCCAPLL_1P055
VCCA_BCLK_1P05

VCCAPLL_1P051
VCCAPLL_1P052
VCCAPLL_1P053

CNP-H_BGA87 4

+3VALW_H DA

12

RH1010_0402_5%

CH42

@

1-3MM FROM PACKAGE EDGE

0_0402_5 %

A

+1.05VALW_ VCCAMPHYPLL

22U_0402_6.3V6M

1

1

CH45

2

2

@

+1.05VALW_ XTAL

22U_0402_6.3V6M

1

CH49

2

@

1U_0402_6.3V6K

CH46

+RTCBATT

change to 10k

RH104 10K_0402 _5%

+CHGRTC

B

12

DH2

2

3

BAV70W_SOT 323-3

+RTCVCC

1

0.1U_0402_10V6K

1U_0402_6.3V6K

1

1

CH48

CH47

2

2

1 2

RH103 0_0402_5 %

LC filter colse to pin

4

1uF 1-3MM FROM PACKAGE EDGE

1 2

RH105

CNP-H

VCCPRIM_3P32

VCCPRIM_3P35

VCCPGPPG_3P3

VCCPRIM_3P33
VCCPRIM_3P34

VCCPGPPHK1
VCCPGPPHK2
VCCPGPPEF1
VCCPGPPEF2

VCCPGPPBC1
VCCPGPPBC2

VCCPRIM_3P31
VCCDSW_3P31
VCCDSW_3P32

VCCPRIM_1P83
VCCPRIM_1P84
VCCPRIM_1P85
VCCPRIM_1P86
VCCPRIM_1P87

VCCPRIM_1P81
VCCPRIM_1P82

VCCPRIM_1P0520
VCCPRIM_1P0519

VCCPRIM_1P241
VCCPRIM_1P242

VCCDPHY_1P241
VCCDPHY_1P242
VCCDPHY_1P243

VCCMPHY_SENSE
VSSMPHY_SENSE

8 OF 13

+3VALW_D SW

0.1U_0402_10V6K

1

CH40

2

1P_0402_50V8

1

2

reserve filter folloe CRB
8/21

+RTCBATT

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

AW9

BF47

DCPRTC1

BG47

DCPRTC2

V23

AN44

VCCSPI

BC49

VCCRTC1

BD49

VCCRTC2

AN21
AY8
BB7

AC35
AC36
AE35
AE36

AN24

VCCPGPPD

AN26
AP26

AN32

VCCPGPPA

AT44
BE48
BE49

BB14

VCCHDA

AG19
AG20
AN15
AR15
BB11

AF19
AF20

AG31
AF31
AK22
AK23

AJ22

AJ23

BG5

K47
K46

Rev1.0

+3VALW_PC H_PRIM +3VALW_SP I

RH98 0_0603 _5%

RH100 0_0603_5 %

change to 0_0603 (1.0)

JRTC1

1

1

2

2

3

GND

4

GND

ACES_50271 -0020N-001

CONN@

SP02000RO 00

2017/12/18 2018/09/01

2017/12/18 2018/09/01

2017/12/18 2018/09/01

0.182A

+VCCRTCE XT

0.095A

0.05A

0.145A

0.97A

0.262A

0.174A

0.14A

0.343A

0.101A

0.106A

0.113A

0.00767A

0.766A

0.882A

+1.8V_PHVLDO

0.193A

0.0895A

VCCMPHY_SEN SE
VSSMPHY_SENSE

1 2

1

2

Compal Secret Data

Compal Secret Data

Compal Secret Data

Internal LDO

+3VALW_PC H_PRIM

+1.8VALW_P RIM

+1.8V_PHVLDO

RH95 0_0402_ 5%@

TH27TP@
TH28TP@

+1.8VALW_P RIM+1.8VALW

Deciphered Date

Deciphered Date

Deciphered Date

D

+VCCRTCE XT

+3VALW_SP I

+RTCVCC

+1.8VALW_P RIM

+3VALW_D SW

1 2

+1.05VALW_ PCH

+1.05VALW_ PCH

+1.24V_VCCLD OSRAM_IN

+1.24V_PRIM_D PHY

+1.24V_PRIM_M AR

1-3MM FROM PACKAGE
FOR PGPPEF AE35/AE37

reserve for cnvi iss ue (1.0)

+1.8VALW_P RIM + 1.8VALW_PRIM

+3VALW_H DA

+1.8VALW_P RIM

Short pins AJ22,AJ23,AK22,AK23 together
at surface layer from PDG Rev0.71

0.1U_0402_10V6K

1

CH36

2

@

0.1U_0402_10V6K

1

CH52

2

near AG19/AG20

+VCCRTCE XT

0.1U_0402_10V6K

1

2

+1.8VALW_P RIM

4.7U_0402_6.3V6M

1

1

CH27

2

2

VCCPHVLDO_1P8
(External VRM mode RH172 unmount)

For DDX03 R02

+1.24V_PRIM_M AR

4.7U_0402_6.3V6M

1

CH32

2

+3VALW_PC H_PRIM+3VALW_PC H_PRIM

0.1U_0402_10V6K

1

2

1-3MM FROM PACKAGE
FOR PGPPHK AC35/AC36

10U_0603_6.3V6M

1

CH53

@

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

PCH(7/8)Power

PCH(7/8)Power

PCH(7/8)Power

Size Document Number R ev

Size Document Number R ev

Size Document Number R ev

Custom

Custom

Custom

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

Dat e: Sheet of

Dat e: Sheet of

Dat e: Sheet of

GPP A

GPP B
GPP C

GPP D

GPP E
GPP F

CH24

GPP G

GPP H
GPP K

GPP I

GPP J

GPD

1U_0402_6.3V6K

CH28

Close to BB11

+1.24V_VCCLD OSRAM_IN +1.24V_PRIM_DPHY

RH96 0_0402_5%@

RH174 for 571391_CFL_H_PDG_Rev0p71.pdf

CH39

@

1-3MM FROM PACKAGE
FOR VCCPRIM AY8/BB7

E

1 2

+3VALW_PC H_PRIM

1U_0402_6.3V6K

1

CH37

2

3.3 V

3.3 V

3.3 V

*

1.8 V

3.3 V

3.3 V

3.3 V

3.3V Only

1.8V Only

3.3V Only

0.1U_0402_10V6K

1

CH38

2

21 67Thursday, Febru ary 22, 2018

21 67Thursday, Febru ary 22, 2018

21 67Thursday, Febru ary 22, 2018

1.0

1.0

1.0

1

4