Acer Nitro AN515-52 Schematic

A

I

B

I

C

I

D

I

E

1

Compal

15

V

2

V

17

Vxl

*

3

Vxl

DH

/

DH

/

5

/

7

/

DH
DH

5

VF

7

VF

73

F

F

CoffeeLake

53

Intel

Nvidia

Confidential

MB

17

N

Schematic

H

P

-

G

0

/

G

1

Document

1

2

3

LA

4

Security

THIS

AND

DEPARTMENT

A

B

MAY

-

F

Rev

:

2018.02

Classification

Issued

Date

SHEETOFENGINEERING

TRADE

SECRET

EXCEPT

USED

BE

BY

INFORMATION

AS

OR

DISCLOSED

DRAWING

.

THIS

AUTHORIZEDBYCOMPAL

TO

ANY

951

lA

22

.

/

/

2017

18

12

IS

PROPRIETARY

NOT

MAY

ELECTRONICS

PARTY

PROPERTYOFCOMPAL

BE

TRANSFERED

WITHOUT

C

SHEET

THIRD

THE

P

Compal

,

INC

PRIOR

.

NEITFER

WRITTEN

Secret

Deciphered

FROM

THIS

ELECTRONICS

THE

CUSTODY

SHEET

CONSENT

Data

OF

Date

NOR

COMPAL

OF

THE

2018/09/01

,

INC

CONTAINS

.

AND

COMPETENT

THE

DIVISION

INFORMATIONITCONTAINS

,

ELECTRONICS

CONFIDENTIAL

INC

.

D

4

Cnmpnl

Title

Cover

Document

OF

R8D

Size

Sustorr

Date

:

Electronics

Sheet

Number

DH

M/B

5

VF

Thursday,February

LA

F

-

,

2018

22

591PR01

,

Sheet

I

E

Inc

.

Rev

1.0

67

of

1

BOM Structure Table

BOM Option Table

SATA HD D W RED RIVER

SATA HD D WO RE DRIVER
NV N17P -G0(1050 )
NV N17P -G1(1050 TI)
i5 CPU
i7 CPU

BOM Str ucture

VX15@

SATARD @
SATANR D@
G0@
G1@
i5@
i7@

+VCCIO
+VCC_SA
+1.8VSDGPU_AON
+1.8VSDGPU_MAIN

+1.8VGA_CORE
+1.35VSDGPU

X76730BOL51 SAMSUN G1280
X76730BOL52 HYNLX1 280
X76730BOL53 SAMSUN G2560
X76730BOL54 HYNIX2 560
X76730BOL55 MICRON 2560

I5QP89 PG1 4G 32HDMI

I78750 PG1 4G 32HDMI

+1.8VS

UQ2

+19VB -> +19V_CPU

LX1

RH92

RH94

+1.05VALW_PRIM

+1.05VALW_PCH

RH102

RH103

RH105

PCH

PCH

PCH

A

BIOS ver: V0 .02W1
EC : ve r: V002AT04

1 1

AC modeDH5VF_EVT Power Sequence

B

C

D

E

Plug in

+3VLP

EC_ON

+5VAL W

ON/OFF BTN#

+3VAL W

+1.05V ALW

EC_RSM RST#

PBTN_O UT#

PM_SLP _S4#

PM_SLP _S3#

2

3 3

SYSON

+1.05V _VCCST

+1.2V_ VDDQ

+2.5V S

SUSP#

+1.05V S_VCCST G

+5VS

+3VS

+1.8V S

EC_VCC ST_PG

SM_PG_ CTRL

+0.6VS _VTT

VR_ON

+VCC_S A

+VCC_C ORE

+VCC_G T

PCH_PW ROK

SYS_PW ROK

PLT_RS T#

330.8ms

→

333.3ms

→

→

→

2.439ms

92.03ms

94.88ms

29.19ms

→

→

174.6ms

20.1ms

← →

→
→

Power On

19.18ms

19.22ms

72.1us

→

275.9us

→

692.9us

→
→

910.1us

→

12.7ms

8.378us

→
→

→

412us

→
→

→
→

→

877.7us

630.4us

25.34ms

25.35ms

25.36ms

25.19ms

→
→

→
→

→
→

→

1.759ms

173.0ms

NA

12.42ms

150.3ms

152.3ms 318.7us

→

→

S3 S3 Resume

13.01us

55.47us

→

618.5us

→

8.679ms

→

347.6us

→

0us

→

0us 13.97ms

→

3.819ms

→

26.91us

51.25us

→

87.75us

→

NA

→

47.39us

→

61.95us

→

→

67.04ms

8.502us

→

906.0us

→

→

424.9us

→
→

→
→

→

656.1us

25.25ms

25.25ms

25.26ms

→
→

→
→

→
→

25.59ms

1.757ms

167.1ms

NA

12.18ms

150.6ms

151.8ms

Power Off

100.5us

152.8us

→

88.37us

→

367.6us

→
→

13us

→

→

686.0us

→

→

0us

→

2.034ms

→

27.06us

→

48.00us

→

112.0us

→

NA

47.83us

→

62.37us

→

2.266ms

68.53us

11.65ms

446.2us

293.7us

→

+3VLP

EC_ON

+5VAL W

ON/OFF BTN#

+3VAL W

+1.05V ALW

EC_RSM RST#

PBTN_O UT#

PM_SLP _S4#

PM_SLP _S3#

SYSON

+1.05V _VCCST

+1.2V_ VDDQ

+2.5V S

SUSP#

+1.05V S_VCCST G

+5VS

+3VS

+1.8V S

EC_VCC ST_PG

SM_PG_ CTRL

+0.6VS _VTT

VR_ON

+VCC_S A

+VCC_C ORE

+VCC_G T

PCH_PW ROK

SYS_PW ROK

PLT_RS T#

2

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS T HE PROPRIETARY PR OPERTY OF COMPAL ELECTRONICS, IN C. AND C ONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS T HE PROPRIETARY PR OPERTY OF COMPAL ELECTRONICS, IN C. AND C ONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS T HE PROPRIETARY PR OPERTY OF COMPAL ELECTRONICS, IN C. AND C ONTAINS CONFIDENTIAL
AND TRADE SECRET INFORM ATION. THIS SHEE T MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D

AND TRADE SECRET INFORM ATION. THIS SHEE T MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D

AND TRADE SECRET INFORM ATION. THIS SHEE T MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D
DEPARTMENT EXC EPT AS AUTHORIZE D BY COMPAL ELECT RONICS, INC. NEIT HER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXC EPT AS AUTHORIZE D BY COMPAL ELECT RONICS, INC. NEIT HER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXC EPT AS AUTHORIZE D BY COMPAL ELECT RONICS, INC. NEIT HER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

C

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2017/12/18 2018/09/01

2017/12/18 2018/09/01

2017/12/18 2018/09/01

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Power Sequence

Power Sequence

Power Sequence

Size

Size

Size

Document Number Re v

Document Number Re v

Document Number Re v

Custom

Custom

Custom

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

Date : Sheet of

Date : Sheet of

Date : Sheet of

E

5 67Thursday, February 22, 2018

5 67Thursday, February 22, 2018

5 67Thursday, February 22, 2018

1.0

1.0

1.0

5

PCH_SMBCLK

PCH_SMBD ATA

PCH_SML0CLK

D

Skylake-H

PCH

PCH_SML 0DATA

PCH_SML1CLK

PCH_SML 1DATA

499

499

2.2K

2.2K

2.2K

2.2K

+3VA LW_P CH _PRIM

(QH7)
2N7002D W

+3VA LW_P CH _PRIM

+3VA LW_P CH _PRIM

(RH189/RH19 0)
R-short

2.2K

2.2K

EC_SM B_CK1

EC_SMB_DA1

KB9022

EC_SM B_CK2

C C

EC_SMB_DA2

+3VL P_ EC

100 ohm

100 ohm

0 ohm

0 ohm

+3V S

EC_SMB_CK1-1

EC_SMB_DA1-1

EC_SMB_CK 1_CHGR

EC_SMB_D A1_CHGR

4

D_CK_SC LK

D_CK_SDATA

EC_SM B_CK2

EC_SMB_DA2

BATTERY

CONN

Charger

2.2K

2.2K

+3V S

SO-DIMM A & B

G-Sensor

+1.8 VSDG PU _MAIN

(QV2)
PJT138KA

(co-lay)

2N7002
R-Shor t

+3V S

(QF1)
2N7002D W

3

VGA_I2CS_SCL

VGA_I2CS_SDA

179F_SMB_CK2

179F_SMB_DA2

TMS_SMB_CLK

TMS_SM B_DATA

1.8K

1.8K

USB CC EJ179F

2.2K

2.2K

THERMAL SENSOR

+1.8 VSDG PU _AON

N17P-G0
N17P-G1

+3V S

2

1

2K

2K

I2CB_SCL

I2CB_SDA

+1.8 VSDG PU _AON

2K

2K

I2CC_SCL

I2CC_SDA

+1.8 VSDG PU _AON

D

B

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE P ROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. A ND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE P ROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. A ND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE P ROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. A ND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL E LECTRONICS, INC. N EITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL E LECTRONICS, INC. N EITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL E LECTRONICS, INC. N EITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2017/12/18 2018/09/01

2017/12/18 2018/09/01

2017/12/18 2018/09/01

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size

Size

Size

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

N17E-GDDR5_D

N17E-GDDR5_D

N17E-GDDR5_D

Document Number Re v

Document Number Re v

Document Number Re v

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

1

6 67Thursday, February 22, 2018

6 67Thursday, February 22, 2018

6 67Thursday, February 22, 2018

1.0

1.0

1.0

of

of

of

B

A

B

C

D

E

CO-LAY FOR VGA OUTPUT

1 2

GPU_ED P_TXP0<27>
GPU_ED P_TXN0<27>
GPU_ED P_TXP1<27>
GPU_ED P_TXN1<27>
GPU_ED P_TXP2<27>
GPU_ED P_TXN2<27>

1

GPU_ED P_TXP3<27>
GPU_ED P_TXN3<27>

GPU_ED P_AUXP<27>
GPU_ED P_AUXN<27>

RG183 0_0201 _5%@

1 2

RG184 0_0201 _5%@

1

RG185 0_0201 _5%@
RG186 0_0201 _5%

RG187 0_0201 _5%@
RG188 0_0201 _5%@

RG189 0_0201 _5%@
RG190 0_0201 _5%@

2

1 2

@

1

2

1 2

1 2
1 2

1 2

RG191 0_0201 _5%@

1 2

RG192 0_0201 _5%@

EDP_AU XP
EDP_AU XN

1

UC1D

K36

DDI1_TXP_0

K37

2 2

Coffee Lake-H CPU SKU

3

UC1

I5@

CFL-H 2.3 G BGA

SA0000BPJ40

UC1

I7@

CFL-H 2.2 G BGA

SA0000BPZ40

DDI1_TXN_0

J35

DDI1_TXP_1

J34

DDI1_TXN_1

H37

DDI1_TXP_2

H36

DDI1_TXN_2

J37

DDI1_TXP_3

J38

DDI1_TXN_3

D27

DDI1_AUXP

E27

DDI1_AUXN

H34

DDI2_TXP_0

H33

DDI2_TXN_0

F37

DDI2_TXP_1

G38

DDI2_TXN_1

F34

DDI2_TXP_2

F35

DDI2_TXN_2

E37

DDI2_TXP_3

E36

DDI2_TXN_3

F26

DDI2_AUXP

E26

DDI2_AUXN

C34

DDI3_TXP_0

D34

DDI3_TXN_0

B36

DDI3_TXP_1

B34

DDI3_TXN_1

F33

DDI3_TXP_2

E33

DDI3_TXN_2

C33

DDI3_TXP_3

B33

DDI3_TXN_3

A27

DDI3_AUXP

B27

DDI3_AUXN

CFL-H_B GA1440

CFL-H

EDP_TXP_0

EDP_TXN_0
EDP_TXP_1
EDP_TXN_1

EDP_TXP_2
EDP_TXN_2
EDP_TXP_3
EDP_TXN_3

EDP_AUXP

EDP_AUXN

EDP_DISP_UTIL

DISP_RCOMP

PROC_AUDIO_CLK

PROC_AUDIO_SDI

PROC_AUDIO_SDO

4 of 13

D29
E29
F28
E28

A29
B29
C28

B28

C26
B26

A33

D37

G27
G25
G29

EDP_TX P0
EDP_TX N0
EDP_TX P1
EDP_TX N1
EDP_TX P2
EDP_TX N2

EDP_TX P3

EDP_TX N3

EDP_AU XP
EDP_AU XN

DP_RCO MP

Trace Width/Space: 15 mil/ 20 mil
Max Trace Length: 600 mil

CPU_DISP A_SDI

RC1 24.9_04 02_1%

RC2 20_040 2_5%

1 2

2

follow CRB

1

EDP_TX P0 <33>
EDP_TX N0 <33>

EDP_TX P1 <33>
EDP_TX N1 <33>
EDP_TX P2 <33>
EDP_TX N2 <33>
EDP_TX P3 <33>
EDP_TX N3 <33>

EDP_AU XP <3 3>
EDP_AU XN <33>

+VCCIO

CPU_DISP A_BCLK_R
CPU_DISP A_SDO_R
CPU_DISP A_SDI_R

eDP

CPU_DISP A_BCLK_R <19>
CPU_DISP A_SDO_R <19>

CPU_DISP A_SDI_R <19>

Cannon Lake PCH SKU

UH1

QNDQ@

CNP-H_BG A874

SA0000BVP10

3

NV N17P SKU

4 4

UV1

G0@

N17P-G0 -A1

SA0000A0540

UV1

G1@

N17P-G1 -A1

SA0000A0660

A

Security Classification

Security Classification

Security Classification

2017/12 /18 2018/09 /01

2017/12 /18 2018/09 /01

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

B

2017/12 /18 2018/09 /01

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

CFL-H(1/8)DDI/eDP

CFL-H(1/8)DDI/eDP

CFL-H(1/8)DDI/eDP

Size Document Number Re v

Size Document Number Re v

Size Document Number R ev

Custom

Custom

Custom

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

Dat e: Sheet

Dat e: Sheet of

D

Dat e: Sheet of

7 67Thursday, Febru ary 22, 2018

o f

7 67Thursday, Febru ary 22, 2018

7 67Thursday, Febru ary 22, 2018

E

1.0

1.0

1.0

A

B

C

D

E

CHANNEL-A

Interleaved Memory

UC1A

1

2 2

3

DDR_A_ D[0..63]<23>

For ECC DIMM

DDR_A_ D0
DDR_A_ D1
DDR_A_ D2
DDR_A_ D3
DDR_A_ D4
DDR_A_ D5
DDR_A_ D6
DDR_A_ D7

DDR_A_ D8

DDR_A_ D9

DDR_A_ D10

DDR_A_ D11

DDR_A_ D12
DDR_A_ D13
DDR_A_ D14

DDR_A_ D15
DDR_A_ D16

DDR_A_ D17

DDR_A_ D18
DDR_A_ D19

DDR_A_ D20
DDR_A_ D21

DDR_A_ D22

DDR_A_ D23
DDR_A_ D24

DDR_A_ D25
DDR_A_ D26
DDR_A_ D27
DDR_A_ D28
DDR_A_ D29
DDR_A_ D30
DDR_A_ D31
DDR_A_ D32
DDR_A_ D33
DDR_A_ D34
DDR_A_ D35
DDR_A_ D36
DDR_A_ D37
DDR_A_ D38
DDR_A_ D39
DDR_A_ D40
DDR_A_ D41
DDR_A_ D42
DDR_A_ D43
DDR_A_ D44
DDR_A_ D45
DDR_A_ D46
DDR_A_ D47
DDR_A_ D48
DDR_A_ D49
DDR_A_ D50
DDR_A_ D51
DDR_A_ D52
DDR_A_ D53
DDR_A_ D54
DDR_A_ D55

DDR_A_ D56
DDR_A_ D57

DDR_A_ D58

DDR_A_ D59

DDR_A_ D60
DDR_A_ D61
DDR_A_ D62
DDR_A_ D63

DDR4(IL)/LP3-DDR4(NIL) LP3/DDR4

BR6

DDR0_DQ_0/DDR0_DQ_0

BT6

DDR0_DQ_1/DDR0_DQ_1

BP3

DDR0_DQ_2/DDR0_DQ_2

BR3

DDR0_DQ_3/DDR0_DQ_3

BN5

DDR0_DQ_4/DDR0_DQ_4

BP6

DDR0_DQ_5/DDR0_DQ_5

BP2

DDR0_DQ_6/DDR0_DQ_6

BN3

DDR0_DQ_7/DDR0_DQ_7

BL4

DDR0_DQ_8/DDR0_DQ_8

BL5

DDR0_DQ_9/DDR0_DQ_9

BL2

DDR0_DQ_10/DDR0_DQ_10

BM1

DDR0_DQ_11/DDR0_DQ_11

BK4

DDR0_DQ_12/DDR0_DQ_12

BK5

DDR0_DQ_13/DDR0_DQ_13

BK1

DDR0_DQ_14/DDR0_DQ_14

BK2

DDR0_DQ_15/DDR0_DQ_15

BG4

DDR0_DQ_16/DDR0_DQ_32

BG5

DDR0_DQ_17/DDR0_DQ_33

BF4

DDR0_DQ_18/DDR0_DQ_34

BF5

DDR0_DQ_19/DDR0_DQ_35

BG2

DDR0_DQ_20/DDR0_DQ_36

BG1

DDR0_DQ_21/DDR0_DQ_37

BF1

DDR0_DQ_22/DDR0_DQ_38

BF2

DDR0_DQ_23/DDR0_DQ_39

BD2

DDR0_DQ_24/DDR0_DQ_40

BD1

DDR0_DQ_25/DDR0_DQ_41

BC4

DDR0_DQ_26/DDR0_DQ_42

BC5

DDR0_DQ_27/DDR0_DQ_43

BD5

DDR0_DQ_28/DDR0_DQ_44

BD4

DDR0_DQ_29/DDR0_DQ_45

BC1

DDR0_DQ_30/DDR0_DQ_46

BC2

DDR0_DQ_31/DDR0_DQ_47

AB1

DDR0_DQ_32/DDR1_DQ_0

AB2

DDR0_DQ_33/DDR1_DQ_1

AA4

DDR0_DQ_34/DDR1_DQ_2

AA5

DDR0_DQ_35/DDR1_DQ_3

AB5

DDR0_DQ_36/DDR1_DQ_4

AB4

DDR0_DQ_37/DDR1_DQ_5

AA2

DDR0_DQ_38/DDR1_DQ_6

AA1

DDR0_DQ_39/DDR1_DQ_7

V5

DDR0_DQ_40/DDR1_DQ_8

V2

DDR0_DQ_41/DDR1_DQ_9

U1

DDR0_DQ_42/DDR1_DQ_10

U2

DDR0_DQ_43/DDR1_DQ_11

V1

DDR0_DQ_44/DDR1_DQ_12

V4

DDR0_DQ_45/DDR1_DQ_13

U5

DDR0_DQ_46/DDR1_DQ_14

U4

DDR0_DQ_47/DDR1_DQ_15

R2

DDR0_DQ_48/DDR1_DQ_32

P5

DDR0_DQ_49/DDR1_DQ_33

R4

DDR0_DQ_50/DDR1_DQ_34

P4

DDR0_DQ_51/DDR1_DQ_35

R5

DDR0_DQ_52/DDR1_DQ_36

P2

DDR0_DQ_53/DDR1_DQ_37

R1

DDR0_DQ_54/DDR1_DQ_38

P1

DDR0_DQ_55/DDR1_DQ_39

M4

DDR0_DQ_56/DDR1_DQ_40

M1

DDR0_DQ_57/DDR1_DQ_41

L4

DDR0_DQ_58/DDR1_DQ_42

L2

DDR0_DQ_59/DDR1_DQ_43

M5

DDR0_DQ_60/DDR1_DQ_44

M2

DDR0_DQ_61/DDR1_DQ_45

L5

DDR0_DQ_62/DDR1_DQ_46

L1

DDR0_DQ_63/DDR1_DQ_47

LP3/DDR4

BA2

NC/DDR0_ECC_0

BA1

NC/DDR0_ECC_1

AY4

NC/DDR0_ECC_2

AY5

NC/DDR0_ECC_3

BA5

NC/DDR0_ECC_4

BA4

NC/DDR0_ECC_5

AY1

NC/DDR0_ECC_6

AY2

NC/DDR0_ECC_7

CFL-H_B GA1440

CFL-H

DDR CHANNEL A

DDR0_CKP_0/DDR0_CKP_0
DDR0_CKN_0/DDR0_CKN_0
DDR0_CKP_1/DDR0_CKP_1
DDR0_CKN_1/DDR0_CKN_1

NC/DDR0_CKP_2
NC/DDR0_CKN_2
NC/DDR0_CKP_3
NC/DDR0_CKN_3

DDR0_CKE_0/DDR0_CKE_0
DDR0_CKE_1/DDR0_CKE_1
DDR0_CKE_2/DDR0_CKE_2
DDR0_CKE_3/DDR0_CKE_3

DDR0_CS#_0/DDR0_CS#_0
DDR0_CS#_1/DDR0_CS#_1

NC/DDR0_CS#_2
NC/DDR0_CS#_3

DDR0_ODT_0/DDR0_ODT_0

NC/DDR0_ODT_1
NC/DDR0_ODT_2
NC/DDR0_ODT_3

DDR0_CAB_4/DDR0_BA_0
DDR0_CAB_6/DDR0_BA_1

DDR0_CAA_5/DDR0_BG_0

DDR0_CAB_3/DDR0_MA_16
DDR0_CAB_2/DDR0_MA_14
DDR0_CAB_1/DDR0_MA_15

DDR0_CAB_9/DDR0_MA_0

DDR0_CAB_8/DDR0_MA_1
DDR0_CAB_5/DDR0_MA_2

NC/DDR0_MA_3

NC/DDR0_MA_4
DDR0_CAA_0/DDR0_MA_5
DDR0_CAA_2/DDR0_MA_6
DDR0_CAA_4/DDR0_MA_7
DDR0_CAA_3/DDR0_MA_8
DDR0_CAA_1/DDR0_MA_9

DDR0_CAB_7/DDR0_MA_10
DDR0_CAA_7/DDR0_MA_11
DDR0_CAA_6/DDR0_MA_12
DDR0_CAB_0/DDR0_MA_13

DDR0_CAA_9/DDR0_BG_1
DDR0_CAA_8/DDR0_ACT#

NC/DDR0_PAR

NC/DDR0_ALERT#

DDR4(IL)/LP3-DDR4(NIL)

DDR0_DQSN_0/DDR0_DQSN_0
DDR0_DQSN_1/DDR0_DQSN_1
DDR0_DQSN_2/DDR0_DQSN_4
DDR0_DQSN_3/DDR0_DQSN_5
DDR0_DQSN_4/DDR1_DQSN_0
DDR0_DQSN_5/DDR1_DQSN_1
DDR0_DQSN_6/DDR1_DQSN_4
DDR0_DQSN_7/DDR1_DQSN_5

DDR0_DQSP_0/DDR0_DQSP_0
DDR0_DQSP_1/DDR0_DQSP_1
DDR0_DQSP_2/DDR0_DQSP_4
DDR0_DQSP_3/DDR0_DQSP_5
DDR0_DQSP_4/DDR1_DQSP_0
DDR0_DQSP_5/DDR1_DQSP_1
DDR0_DQSP_6/DDR1_DQSP_4
DDR0_DQSP_7/DDR1_DQSP_5

DDR0_DQSP_8/DDR0_DQSP_8

DDR0_DQSN_8/DDR0_DQSN_8

1 OF 13

AG1
AG2
AK2
AK1
AL3
AK3
AL2
AL1

AT1
AT2
AT3
AT5

AD5
AE2
AD2
AE5

AD3
AE4
AE1
AD4

AH5
AH1
AU1

AH4
AG4
AD1

AH3

AP4
AN4

AP5
AP2
AP1
AP3
AN1
AN3
AT4
AH2
AN2
AU4
AE3
AU2
AU3

AG3
AU5

BR5
BL3
BG3
BD3
AA3
U3
P3
L3

BP5
BK3
BF3
BC3
AB3
V3
R3
M3

AY3
BA3

DDR_A_ CLK0
DDR_A_ CLK#0
DDR_A_ CLK1
DDR_A_ CLK#1

DDR_A_ CKE0
DDR_A_ CKE1

DDR_A_ CS#0
DDR_A_ CS#1

DDR_A_ ODT0
DDR_A_ ODT1

DDR_A_ BA0
DDR_A_ BA1
DDR_A_ BG0

DDR_A_ MA16_RAS#
DDR_A_ MA14_WE #
DDR_A_ MA15_CAS#

DDR_A_ MA0
DDR_A_ MA1
DDR_A_ MA2
DDR_A_ MA3
DDR_A_ MA4
DDR_A_ MA5
DDR_A_ MA6
DDR_A_ MA7
DDR_A_ MA8
DDR_A_ MA9
DDR_A_ MA10
DDR_A_ MA11
DDR_A_ MA12
DDR_A_ MA13
DDR_A_ BG1
DDR_A_ ACT#

DDR_A_ PAR
DDR_A_ ALERT#

DDR_A_ DQS#0
DDR_A_ DQS#1
DDR_A_ DQS#2
DDR_A_ DQS#3
DDR_A_ DQS#4
DDR_A_ DQS#5
DDR_A_ DQS#6
DDR_A_ DQS#7

DDR_A_ DQS0
DDR_A_ DQS1
DDR_A_ DQS2
DDR_A_ DQS3
DDR_A_ DQS4
DDR_A_ DQS5

DDR_A_ DQS6

DDR_A_ DQS7

DDR_A_ CLK0 <23>
DDR_A_ CLK#0 <23>
DDR_A_ CLK1 <23>
DDR_A_ CLK#1 <23>

DDR_A_ CKE0 <23>
DDR_A_ CKE1 <23>

DDR_A_ CS#0 <23>
DDR_A_ CS#1 <23>

DDR_A_ ODT0 <23>
DDR_A_ ODT1 <23>

DDR_A_ BA0 < 23>
DDR_A_ BA1 < 23>
DDR_A_ BG0 < 23>

DDR_A_ MA16_RAS# <23 >
DDR_A_ MA14_WE # <23>
DDR_A_ MA15_CAS# <23 >

DDR_A_ MA0 <23 >
DDR_A_ MA1 <23 >
DDR_A_ MA2 <23 >
DDR_A_ MA3 <23 >
DDR_A_ MA4 <23 >
DDR_A_ MA5 <23 >
DDR_A_ MA6 <23 >
DDR_A_ MA7 <23 >
DDR_A_ MA8 <23 >
DDR_A_ MA9 <23 >
DDR_A_ MA10 <2 3>
DDR_A_ MA11 <2 3>
DDR_A_ MA12 <2 3>
DDR_A_ MA13 <2 3>
DDR_A_ BG1 < 23>
DDR_A_ ACT# <23>

DDR_A_ PAR <23>
DDR_A_ ALERT# <23>

DDR_A_ DQS#0 <23>
DDR_A_ DQS#1 <23>
DDR_A_ DQS#2 <23>
DDR_A_ DQS#3 <23>
DDR_A_ DQS#4 <23>
DDR_A_ DQS#5 <23>
DDR_A_ DQS#6 <23>
DDR_A_ DQS#7 <23>

DDR_A_ DQS0 <23>
DDR_A_ DQS1 <23>
DDR_A_ DQS2 <23>
DDR_A_ DQS3 <23>
DDR_A_ DQS4 <23>
DDR_A_ DQS5 <23>
DDR_A_ DQS6 <23>
DDR_A_ DQS7 <23>

For ECC DIMM

1

3

4 4

Security Classification

Security Classification

Security Classification

2017/12 /18 2018/09 /01

2017/12 /18 2018/09 /01

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

A

B

2017/12 /18 2018/09 /01

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

CFL-H(2/8)DIMMA

CFL-H(2/8)DIMMA

CFL-H(2/8)DIMMA

Size Document Number R ev

Size Document Number R ev

Size Document Number R ev

Custom

Custom

Custom

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

Dat e: Sheet of

Dat e: Sheet of

D

Dat e: Sheet of

8 67Thursday, Febru ary 22, 2018

8 67Thursday, Febru ary 22, 2018

8 67Thursday, Febru ary 22, 2018

E

1.0

1.0

1.0

A

B

C

D

E

CHANNEL-B

Interleaved Memory

1

2 2

3

DDR_B_ D[0..63]<24>

For ECC DIMM

DDR_B_ D0
DDR_B_ D1
DDR_B_ D2
DDR_B_ D3

DDR_B_ D4
DDR_B_ D5
DDR_B_ D6

DDR_B_ D7
DDR_B_ D8
DDR_B_ D9
DDR_B_ D10
DDR_B_ D11
DDR_B_ D12
DDR_B_ D13
DDR_B_ D14
DDR_B_ D15
DDR_B_ D16
DDR_B_ D17
DDR_B_ D18

DDR_B_ D19

DDR_B_ D20

DDR_B_ D21
DDR_B_ D22
DDR_B_ D23
DDR_B_ D24
DDR_B_ D25
DDR_B_ D26
DDR_B_ D27
DDR_B_ D28
DDR_B_ D29
DDR_B_ D30
DDR_B_ D31
DDR_B_ D32
DDR_B_ D33
DDR_B_ D34
DDR_B_ D35
DDR_B_ D36
DDR_B_ D37
DDR_B_ D38
DDR_B_ D39

DDR_B_ D40
DDR_B_ D41
DDR_B_ D42
DDR_B_ D43
DDR_B_ D44
DDR_B_ D45
DDR_B_ D46
DDR_B_ D47
DDR_B_ D48
DDR_B_ D49
DDR_B_ D50
DDR_B_ D51
DDR_B_ D52
DDR_B_ D53
DDR_B_ D54
DDR_B_ D55
DDR_B_ D56
DDR_B_ D57
DDR_B_ D58
DDR_B_ D59
DDR_B_ D60
DDR_B_ D61
DDR_B_ D62
DDR_B_ D63

UC1B

DDR4(IL)/LP3-DDR4(NIL)

BT11

DDR1_DQ_0/DDR0_DQ_16

BR11

DDR1_DQ_1/DDR0_DQ_17

BT9

DDR1_DQ_2/DDR0_DQ_18

BR8

DDR1_DQ_3/DDR0_DQ_19

BP11

DDR1_DQ_4/DDR0_DQ_20

BN11

DDR1_DQ_5/DDR0_DQ_21

BP8

DDR1_DQ_6/DDR0_DQ_22

BN8

DDR1_DQ_7/DDR0_DQ_23

BL12

DDR1_DQ_8/DDR0_DQ_24

BL11

DDR1_DQ_9/DDR0_DQ_25

BL8

DDR1_DQ_10/DDR0_DQ_26

BJ8

DDR1_DQ_11/DDR0_DQ_27

BJ11

DDR1_DQ_12/DDR0_DQ_28

BJ10

DDR1_DQ_13/DDR0_DQ_29

BL7

DDR1_DQ_14/DDR0_DQ_30

BJ7

DDR1_DQ_15/DDR0_DQ_31

BG11

DDR1_DQ_16/DDR0_DQ_48

BG10

DDR1_DQ_17/DDR0_DQ_49

BG8

DDR1_DQ_18/DDR0_DQ_50

BF8

DDR1_DQ_19/DDR0_DQ_51

BF11

DDR1_DQ_20/DDR0_DQ_52

BF10

DDR1_DQ_21/DDR0_DQ_53

BG7

DDR1_DQ_22/DDR0_DQ_54

BF7

DDR1_DQ_23/DDR0_DQ_55

BB11

DDR1_DQ_24/DDR0_DQ_56

BC11

DDR1_DQ_25/DDR0_DQ_57

BB8

DDR1_DQ_26/DDR0_DQ_58

BC8

DDR1_DQ_27/DDR0_DQ_59

BC10

DDR1_DQ_28/DDR0_DQ_60

BB10

DDR1_DQ_29/DDR0_DQ_61

BC7

DDR1_DQ_30/DDR0_DQ_62

BB7

DDR1_DQ_31/DDR0_DQ_63

AA11

DDR1_DQ_32/DDR1_DQ_16

AA10

DDR1_DQ_33/DDR1_DQ_17

AC11

DDR1_DQ_34/DDR1_DQ_18

AC10

DDR1_DQ_35/DDR1_DQ_19

AA7

DDR1_DQ_36/DDR1_DQ_20

AA8

DDR1_DQ_37/DDR1_DQ_21

AC8

DDR1_DQ_38/DDR1_DQ_22

AC7

DDR1_DQ_39/DDR1_DQ_23

DDR4(IL)/LP3-DDR4(NIL)

W8

DDR1_DQ_40/DDR1_DQ_24

W7

DDR1_DQ_41/DDR1_DQ_25

V10

DDR1_DQ_42/DDR1_DQ_26

V11

DDR1_DQ_43/DDR1_DQ_27

W11

DDR1_DQ_44/DDR1_DQ_28

W10

DDR1_DQ_45/DDR1_DQ_29

V7

DDR1_DQ_46/DDR1_DQ_30

V8

DDR1_DQ_47/DDR1_DQ_31

R11

DDR1_DQ_48/DDR1_DQ_48

P11

DDR1_DQ_49/DDR1_DQ_49

P7

DDR1_DQ_50/DDR1_DQ_50

R8

DDR1_DQ_51/DDR1_DQ_51

R10

DDR1_DQ_52/DDR1_DQ_52

P10

DDR1_DQ_53/DDR1_DQ_53

R7

DDR1_DQ_54/DDR1_DQ_54

P8

DDR1_DQ_55/DDR1_DQ_55

L11

DDR1_DQ_56/DDR1_DQ_56

M11

DDR1_DQ_57/DDR1_DQ_57

L7

DDR1_DQ_58/DDR1_DQ_58

M8

DDR1_DQ_59/DDR1_DQ_59

L10

DDR1_DQ_60/DDR1_DQ_60

M10

DDR1_DQ_61/DDR1_DQ_61

M7

DDR1_DQ_62/DDR1_DQ_62

L8

DDR1_DQ_63/DDR1_DQ_63

LP3/DDR4

AW11

NC/DDR1_ECC_0

AY11

NC/DDR1_ECC_1

AY8

NC/DDR1_ECC_2

AW8

NC/DDR1_ECC_3

AY10

NC/DDR1_ECC_4

AW10

NC/DDR1_ECC_5

AY7

NC/DDR1_ECC_6

AW7

NC/DDR1_ECC_7

CFL-H

DDR CHANNEL B

DDR1_CKP_0/DDR1_CKP_0
DDR1_CKN_0/DDR1_CKN_0

DDR1_CKP_1/DDR1_CKP_1

DDR1_CKN_1/DDR1_CKN_1

DDR1_CKE_0/DDR1_CKE_0
DDR1_CKE_1/DDR1_CKE_1

DDR1_CKE_2/DDR1_CKE_2

DDR1_CKE_3/DDR1_CKE_3

DDR1_CS#_0/DDR1_CS#_0
DDR1_CS#_1/DDR1_CS#_1

DDR1_ODT_0/DDR1_ODT_0

DDR1_CAB_3/DDR1_MA_16
DDR1_CAB_2/DDR1_MA_14
DDR1_CAB_1/DDR1_MA_15

DDR1_CAB_4/DDR1_BA_0

DDR1_CAB_6/DDR1_BA_1

DDR1_CAA_5/DDR1_BG_0

DDR1_CAB_9/DDR1_MA_0
DDR1_CAB_8/DDR1_MA_1
DDR1_CAB_5/DDR1_MA_2

DDR1_CAA_0/DDR1_MA_5
DDR1_CAA_2/DDR1_MA_6
DDR1_CAA_4/DDR1_MA_7

DDR1_CAA_3/DDR1_MA_8

DDR1_CAA_1/DDR1_MA_9

DDR1_CAB_7/DDR1_MA_10
DDR1_CAA_7/DDR1_MA_11
DDR1_CAA_6/DDR1_MA_12
DDR1_CAB_0/DDR1_MA_13

DDR1_CAA_9/DDR1_BG_1

DDR1_CAA_8/DDR1_ACT#

DDR4(IL)/LP3-DDR4(NIL)

DDR1_DQSN_0/DDR0_DQSN_2

DDR1_DQSN_1/DDR0_DQSN_3
DDR1_DQSN_2/DDR0_DQSN_6
DDR1_DQSN_3/DDR0_DQSN_7
DDR1_DQSN_4/DDR1_DQSN_2

DDR1_DQSN_5/DDR1_DQSN_3

DDR1_DQSN_6/DDR1_DQSN_6
DDR1_DQSN_7/DDR1_DQSN_7

DDR1_DQSP_0/DDR0_DQSP_2
DDR1_DQSP_1/DDR0_DQSP_3
DDR1_DQSP_2/DDR0_DQSP_6
DDR1_DQSP_3/DDR0_DQSP_7
DDR1_DQSP_4/DDR1_DQSP_2
DDR1_DQSP_5/DDR1_DQSP_3
DDR1_DQSP_6/DDR1_DQSP_6
DDR1_DQSP_7/DDR1_DQSP_7

DDR1_DQSP_8/DDR1_DQSP_8
DDR1_DQSN_8/DDR1_DQSN_8

LP3/DDR4

NC/DDR1_CKP_2
NC/DDR1_CKN_2
NC/DDR1_CKP_3
NC/DDR1_CKN_3

NC/DDR1_CS#_2
NC/DDR1_CS#_3

NC/DDR1_ODT_1
NC/DDR1_ODT_2
NC/DDR1_ODT_3

NC/DDR1_MA_3
NC/DDR1_MA_4

NC/DDR1_PAR

NC/DDR1_ALERT#

AM9
AN9

AM7

AM8
AM11
AM10
AJ10
AJ11

AT8
AT10

AT7

AT11

AF11
AE7
AF10
AE10

AF7
AE8
AE9
AE11

AH10
AH11
AF8

AH8

AH9

AR9

AJ9
AK6
AK5
AL5
AL6
AM6
AN7
AN10

AN8

AR11

AH7
AN11
AR10
AF9
AR7

AT9

AJ7
AR8

BN9

BL9

BG9

BC9
AC9

W9

R9
M9

BP9

BJ9
BF9
BB9
AA9
V9
P9
L9

AW9
AY9

DDR_B_ CLK0
DDR_B_ CLK#0
DDR_B_ CLK1
DDR_B_ CLK#1

DDR_B_ CKE0
DDR_B_ CKE1

DDR_B_ CS#0
DDR_B_ CS#1

DDR_B_ ODT0

DDR_B_ ODT1

DDR_B_ MA16_RAS#
DDR_B_ MA14_WE #
DDR_B_ MA15_CAS#

DDR_B_ BA0
DDR_B_ BA1
DDR_B_ BG0

DDR_B_ MA0

DDR_B_ MA1
DDR_B_ MA2

DDR_B_ MA3

DDR_B_ MA4
DDR_B_ MA5
DDR_B_ MA6
DDR_B_ MA7

DDR_B_ MA8
DDR_B_ MA9
DDR_B_ MA10
DDR_B_ MA11
DDR_B_ MA12
DDR_B_ MA13
DDR_B_ BG1
DDR_B_ ACT#

DDR_B_ PAR
DDR_B_ ALERT#

DDR_B_ DQS#0

DDR_B_ DQS#1
DDR_B_ DQS#2
DDR_B_ DQS#3
DDR_B_ DQS#4
DDR_B_ DQS#5
DDR_B_ DQS#6
DDR_B_ DQS#7

DDR_B_ DQS0
DDR_B_ DQS1
DDR_B_ DQS2
DDR_B_ DQS3
DDR_B_ DQS4
DDR_B_ DQS5
DDR_B_ DQS6
DDR_B_ DQS7

DDR_B_ CLK0 <24>
DDR_B_ CLK#0 <24>
DDR_B_ CLK1 <24>

DDR_B_ CLK#1 <24>

DDR_B_ CKE0 <24>
DDR_B_ CKE1 <24>

DDR_B_ CS#0 <24>
DDR_B_ CS#1 <24>

DDR_B_ ODT0 <24>
DDR_B_ ODT1 <24>

DDR_B_ MA16_RAS# <24 >
DDR_B_ MA14_WE # <24>
DDR_B_ MA15_CAS# <24 >

DDR_B_ BA0 < 24>
DDR_B_ BA1 < 24>
DDR_B_ BG0 < 24>

DDR_B_ MA0 <24 >
DDR_B_ MA1 <24 >
DDR_B_ MA2 <24 >
DDR_B_ MA3 <24 >
DDR_B_ MA4 <24 >
DDR_B_ MA5 <24 >
DDR_B_ MA6 <24 >
DDR_B_ MA7 <24 >

DDR_B_ MA8 <24 >
DDR_B_ MA9 <24 >
DDR_B_ MA10 <2 4>
DDR_B_ MA11 <2 4>
DDR_B_ MA12 <2 4>
DDR_B_ MA13 <2 4>
DDR_B_ BG1 < 24>
DDR_B_ ACT# <24>

DDR_B_ PAR <24>
DDR_B_ ALERT# <24>

DDR_B_ DQS#0 <24>
DDR_B_ DQS#1 <24>
DDR_B_ DQS#2 <24>
DDR_B_ DQS#3 <24>
DDR_B_ DQS#4 <24>
DDR_B_ DQS#5 <24>
DDR_B_ DQS#6 <24>
DDR_B_ DQS#7 <24>

DDR_B_ DQS0 <24>
DDR_B_ DQS1 <24>
DDR_B_ DQS2 <24>
DDR_B_ DQS3 <24>
DDR_B_ DQS4 <24>
DDR_B_ DQS5 <24>
DDR_B_ DQS6 <24>
DDR_B_ DQS7 <24>

For ECC DIMM

1

3

1
1 2
1

2

2

B

RC3 121_04 02_1%
RC4 75_040 2_1%
RC5 100_04 02_1%

Trace Width/Space: 15 mil/ 25 mil

4 4

A

Max Trace Length: 500 mil

SM_RCO MP0
SM_RCO MP1
SM_RCO MP2

G1

DDR_RCOMP_0

H1

DDR_RCOMP_1

J2

DDR_RCOMP_2

CFL-H_B GA1440

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

2 OF 13

DDR_VREF_CA
DDR0_VREF_DQ
DDR1_VREF_DQ

Compal Secret Data

Compal Secret Data

2017/12 /18 2018/09 /01

2017/12 /18 2018/09 /01

2017/12 /18 2018/09 /01

C

Compal Secret Data

BN13
BP13
BR13

Deciphered Date

Deciphered Date

Deciphered Date

+0.6V_V REFCA

+0.6V_B _VREFDQ

+0.6V_V REFCA

+0.6V_B _VREFDQ

D

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

CFL-H(3/8)DIMMB

CFL-H(3/8)DIMMB

CFL-H(3/8)DIMMB

Size Document Number R ev

Size Document Number R ev

Size Document Number R ev

Custom

Custom

Custom

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

Dat e: Sheet of

Dat e: Sheet of

Dat e: Sheet

E

o f

9 67Thursday, Febru ary 22, 2018

9 67Thursday, Febru ary 22, 2018

9 67Thursday, Febru ary 22, 2018

1.0

1.0

1.0

A

PEG&DMI

B

C

D

E

1

2 2

3

To DGPU
PEG Lane Reversed

PEG_CR X_C_GTX_P1 5<25>
PEG_CR X_C_GTX_N1 5<25>

PEG_CR X_C_GTX_P1 4<25>
PEG_CR X_C_GTX_N1 4<25>

PEG_CR X_C_GTX_P1 3<25>
PEG_CR X_C_GTX_N1 3<25>

PEG_CR X_C_GTX_P1 2<25>
PEG_CR X_C_GTX_N1 2<25>

PEG_CR X_C_GTX_P1 1<25>
PEG_CR X_C_GTX_N1 1<25>

PEG_CR X_C_GTX_P1 0<25>
PEG_CR X_C_GTX_N1 0<25>

PEG_CR X_C_GTX_P9<25>
PEG_CR X_C_GTX_N9<25>

PEG_CR X_C_GTX_P8<25>
PEG_CR X_C_GTX_N8<25>

PEG_CR X_C_GTX_P7<25>

PEG_CR X_C_GTX_N7<25>

PEG_CR X_C_GTX_P6<25>
PEG_CR X_C_GTX_N6<25>

PEG_CR X_C_GTX_P5<25>
PEG_CR X_C_GTX_N5<25>

PEG_CR X_C_GTX_P4<25>
PEG_CR X_C_GTX_N4<25>

PEG_CR X_C_GTX_P3<25>
PEG_CR X_C_GTX_N3<25>

PEG_CR X_C_GTX_P2<25>
PEG_CR X_C_GTX_N2<25>

PEG_CR X_C_GTX_P1<25>
PEG_CR X_C_GTX_N1<25>

PEG_CR X_C_GTX_P0<25>
PEG_CR X_C_GTX_N0<25>

+VCCIO

To PCH

1 2

CC1 0.22U_0 201_6.3V6KVGA@

1 2

CC3 0.22U_0 201_6.3V6KVGA@

1

VGA@

VGA@

1

1 2

1 2

1 2

1 2
1

1 2
1 2

1 2

1 2

1 2
1 2

1 2

1 2

1

1 2

1 2

1 2

1 2

1 2

1
1 2

1 2

1 2

1
1

1
1 2

1 2

1 2

DMI_CRX_ PTX_P0<15>
DMI_CRX_ PTX_N0<15>

DMI_CRX_ PTX_P1<15>
DMI_CRX_ PTX_N1<15>

DMI_CRX_ PTX_P2<15>
DMI_CRX_ PTX_N2<15>

DMI_CRX_ PTX_P3<15>
DMI_CRX_ PTX_N3<15>

2

2

2

2

2
2

2

2

CC5 0.22U_0 201_6.3V6KVGA@
CC6 0.22U_0 201_6.3V6KVGA@

CC7 0.22U_0 201_6.3V6KVGA@

CC14 0.22U_0 201_6.3V6KVGA@

CC16 0.22U_0 201_6.3V6KVGA@
CC17 0.22U_0 201_6.3V6KVGA@

CC19 0.22U_0 201_6.3V6KVGA@
CC20 0.22U_0 201_6.3V6KVGA@

CC10 0.22U_0 201_6.3V6K
CC23 0.22U_0 201_6.3V6KVGA@

CC25 0.22U_0 201_6.3V6KVGA@
CC27 0.22U_0 201_6.3V6KVGA@

CC29 0.22U_0 201_6.3V6KVGA@

CC31 0.22U_0 201_6.3V6KVGA@

CC33 0.22U_0 201_6.3V6KVGA@

CC35 0.22U_0 201_6.3V6KVGA@

CC37 0.22U_0 201_6.3V6K

CC39 0.22U_0 201_6.3V6KVGA@

CC41 0.22U_0 201_6.3V6KVGA@

CC43 0.22U_0 201_6.3V6KVGA@

CC45 0.22U_0 201_6.3V6KVGA@
CC47 0.22U_0 201_6.3V6KVGA@

CC49 0.22U_0 201_6.3V6KVGA@

CC51 0.22U_0 201_6.3V6KVGA@

CC53 0.22U_0 201_6.3V6KVGA@
CC55 0.22U_0 201_6.3V6KVGA@

CC57 0.22U_0 201_6.3V6KVGA@
CC59 0.22U_0 201_6.3V6KVGA@

CC61 0.22U_0 201_6.3V6KVGA@

CC63 0.22U_0 201_6.3V6KVGA@

RC6 24.9_04 02_1%

PEG_CR X_GTX_P15
PEG_CR X_GTX_N15

PEG_CR X_GTX_P14
PEG_CR X_GTX_N14

PEG_CR X_GTX_P13
PEG_CR X_GTX_N13

PEG_CR X_GTX_P12
PEG_CR X_GTX_N12

PEG_CR X_GTX_P11
PEG_CR X_GTX_N11

PEG_CR X_GTX_P10
PEG_CR X_GTX_N10

PEG_CR X_GTX_P9
PEG_CR X_GTX_N9

PEG_CR X_GTX_P8
PEG_CR X_GTX_N8

PEG_CR X_GTX_P7
PEG_CR X_GTX_N7

PEG_CR X_GTX_P6
PEG_CR X_GTX_N6

PEG_CR X_GTX_P5
PEG_CR X_GTX_N5

PEG_CR X_GTX_P4
PEG_CR X_GTX_N4

PEG_CR X_GTX_P3
PEG_CR X_GTX_N3

PEG_CR X_GTX_P2
PEG_CR X_GTX_N2

PEG_CR X_GTX_P1
PEG_CR X_GTX_N1

PEG_CR X_GTX_P0

PEG_CR X_GTX_N0

PEG_RC OMP

Trace Width/Space: 15 mil/ 15 mil
Max Trace Length: 600 mil

DMI_CRX_ PTX_P0
DMI_CRX_ PTX_N0

DMI_CRX_ PTX_P1
DMI_CRX_ PTX_N1

DMI_CRX_ PTX_P2
DMI_CRX_ PTX_N2

DMI_CRX_ PTX_P3
DMI_CRX_ PTX_N3

E25

D25

E24
F24

E23

D23

E22
F22

E21

D21

E20

F20

E19

D19

E18
F18

D17

E17

F16
E16

D15

E15

F14
E14

D13

E13

F12

E12

D11

E11

F10
E10

G2

D8

E8

E6
F6

D5

E5

J8
J9

CFL-H_B GA1440

UC1C

PEG_RXP_0
PEG_RXN_0

PEG_RXP_1
PEG_RXN_1

PEG_RXP_2
PEG_RXN_2

PEG_RXP_3
PEG_RXN_3

PEG_RXP_4
PEG_RXN_4

PEG_RXP_5
PEG_RXN_5

PEG_RXP_6
PEG_RXN_6

PEG_RXP_7

PEG_RXN_7

PEG_RXP_8
PEG_RXN_8

PEG_RXP_9
PEG_RXN_9

PEG_RXP_10
PEG_RXN_10

PEG_RXP_11
PEG_RXN_11

PEG_RXP_12

PEG_RXN_12

PEG_RXP_13

PEG_RXN_13

PEG_RXP_14

PEG_RXN_14

PEG_RXP_15
PEG_RXN_15

PEG_RCOMP

DMI_RXP_0

DMI_RXN_0

DMI_RXP_1
DMI_RXN_1

DMI_RXP_2
DMI_RXN_2

DMI_RXP_3
DMI_RXN_3

CFL-H

PEG_TXP_10

PEG_TXN_10

PEG_TXP_11

PEG_TXN_11

PEG_TXP_12

PEG_TXN_12

PEG_TXP_13

PEG_TXN_13

PEG_TXP_14

PEG_TXN_14

PEG_TXP_15

PEG_TXN_15

3 OF 13

PEG_TXP_0

PEG_TXN_0

PEG_TXP_1

PEG_TXN_1

PEG_TXP_2

PEG_TXN_2

PEG_TXP_3

PEG_TXN_3

PEG_TXP_4

PEG_TXN_4

PEG_TXP_5

PEG_TXN_5

PEG_TXP_6

PEG_TXN_6

PEG_TXP_7

PEG_TXN_7

PEG_TXP_8

PEG_TXN_8

PEG_TXP_9

PEG_TXN_9

DMI_TXP_0
DMI_TXN_0

DMI_TXP_1
DMI_TXN_1

DMI_TXP_2
DMI_TXN_2

DMI_TXP_3
DMI_TXN_3

B25

A25

B24
C24

B23
A23

B22
C22

B21

A21

B20
C20

B19
A19

B18
C18

A17
B17

C16
B16

A15
B15

C14
B14

A13
B13

C12
B12

A11
B11

C10
B10

B8
A8

C6
B6

B5
A5

D4
B4

PEG_CT X_GRX_P15

PEG_CT X_GRX_N15

PEG_CT X_GRX_P14

PEG_CT X_GRX_N14

PEG_CT X_GRX_P13

PEG_CT X_GRX_N13

PEG_CT X_GRX_P12

PEG_CT X_GRX_N12

PEG_CT X_GRX_P11

PEG_CT X_GRX_N11

PEG_CT X_GRX_P10

PEG_CT X_GRX_N10

PEG_CT X_GRX_P9

PEG_CT X_GRX_N9

PEG_CT X_GRX_P8

PEG_CT X_GRX_N8

PEG_CT X_GRX_P7

PEG_CT X_GRX_N7

PEG_CT X_GRX_P6

PEG_CT X_GRX_N6

PEG_CT X_GRX_P5

PEG_CT X_GRX_N5

PEG_CT X_GRX_P4

PEG_CT X_GRX_N4

PEG_CT X_GRX_P3

PEG_CT X_GRX_N3

PEG_CT X_GRX_P2

PEG_CT X_GRX_N2

PEG_CT X_GRX_P1

PEG_CT X_GRX_N1

PEG_CT X_GRX_P0

PEG_CT X_GRX_N0

DMI_CTX_ PRX_P0
DMI_CTX_ PRX_N0

DMI_CTX_ PRX_P1
DMI_CTX_ PRX_N1

DMI_CTX_ PRX_P2
DMI_CTX_ PRX_N2

DMI_CTX_ PRX_P3
DMI_CTX_ PRX_N3

12

CC20.22U_0 201_6.3V6K VGA@

12

CC40.22U_0 201_6.3V6K VGA@

1

2

2

2

2

2

2

2

2

2

2

DMI_CTX_ PRX_P0 <15>
DMI_CTX_ PRX_N0 <15>

DMI_CTX_ PRX_P1 <15>
DMI_CTX_ PRX_N1 <15>

DMI_CTX_ PRX_P2 <15>
DMI_CTX_ PRX_N2 <15>

DMI_CTX_ PRX_P3 <15>
DMI_CTX_ PRX_N3 <15>

12

12

1

12

1

1

12

12

12

12
12

12

12

12

12

12

12

1
12

1
12

1

1

1
12

12

12

1
12

VGA@

VGA@

VGA@

VGA@
VGA@

CC110.22U_0 201_6.3V6K VGA@

CC120.22U_0 201_6.3V6K VGA@

CC130.22U_0 201_6.3V6K VGA@

CC150.22U_0 201_6.3V6K VGA@

CC80.22U_0 201_6.3V6K VGA@

CC180.22U_0 201_6.3V6K VGA@

CC90.22U_0 201_6.3V6K VGA@

CC210.22U_0 201_6.3V6K VGA@

CC220.22U_0 201_6.3V6K VGA@

CC240.22U_0 201_6.3V6K VGA@

CC260.22U_0 201_6.3V6K VGA@
CC280.22U_0 201_6.3V6K VGA@

CC300.22U_0 201_6.3V6K VGA@

CC320.22U_0 201_6.3V6K

CC340.22U_0 201_6.3V6K VGA@

CC360.22U_0 201_6.3V6K VGA@

CC380.22U_0 201_6.3V6K

CC400.22U_0 201_6.3V6K VGA@

CC420.22U_0 201_6.3V6K
CC440.22U_0 201_6.3V6K VGA@

CC460.22U_0 201_6.3V6K

CC480.22U_0 201_6.3V6K

CC500.22U_0 201_6.3V6K VGA@

CC520.22U_0 201_6.3V6K VGA@

CC540.22U_0 201_6.3V6K VGA@
CC560.22U_0 201_6.3V6K VGA@

CC580.22U_0 201_6.3V6K VGA@

CC600.22U_0 201_6.3V6K VGA@

CC620.22U_0 201_6.3V6K VGA@
CC640.22U_0 201_6.3V6K VGA@

PEG_CT X_C_GRX_P1 5 <25>

PEG_CT X_C_GRX_N1 5 <25>

PEG_CT X_C_GRX_P1 4 <25>
PEG_CT X_C_GRX_N1 4 <25>

PEG_CT X_C_GRX_P1 3 <25>
PEG_CT X_C_GRX_N1 3 <25>

PEG_CT X_C_GRX_P1 2 <25>
PEG_CT X_C_GRX_N1 2 <25>

PEG_CT X_C_GRX_P1 1 <25>
PEG_CT X_C_GRX_N1 1 <25>

PEG_CT X_C_GRX_P1 0 <25>
PEG_CT X_C_GRX_N1 0 <25>

PEG_CT X_C_GRX_P9 <25 >
PEG_CT X_C_GRX_N9 < 25>

PEG_CT X_C_GRX_P8 <25 >
PEG_CT X_C_GRX_N8 < 25>

PEG_CT X_C_GRX_P7 <25 >
PEG_CT X_C_GRX_N7 < 25>

PEG_CT X_C_GRX_P6 <25 >
PEG_CT X_C_GRX_N6 < 25>

PEG_CT X_C_GRX_P5 <25 >
PEG_CT X_C_GRX_N5 < 25>

PEG_CT X_C_GRX_P4 <25 >
PEG_CT X_C_GRX_N4 < 25>

PEG_CT X_C_GRX_P3 <25 >
PEG_CT X_C_GRX_N3 < 25>

PEG_CT X_C_GRX_P2 <25 >
PEG_CT X_C_GRX_N2 < 25>

PEG_CT X_C_GRX_P1 <25 >
PEG_CT X_C_GRX_N1 < 25>

PEG_CT X_C_GRX_P0 <25 >
PEG_CT X_C_GRX_N0 < 25>

To PCH

To DGPU
PEG Lane Reversed

1

3

4 4

Security Classification

Security Classification

Security Classification

2017/12 /18 2018/09 /01

2017/12 /18 2018/09 /01

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

A

B

2017/12 /18 2018/09 /01

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

PEG/DMI

PEG/DMI

PEG/DMI

Size Document Number R ev

Size Document Number R ev

Size Document Number R ev

Custom

Custom

Custom

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

Dat e: Sheet of

Dat e: Sheet of

D

Dat e: Sheet of

10 67Thursday, Febru ary 22, 2018

10 67Thursday, Febru ary 22, 2018

10 67Thursday, Febru ary 22, 2018

E

1.0

1.0

1.0

A

571391_CFL_H_PDG_Rev0p5

1. The total Length of Data and Clock (from CPU to each VR) must be equal (± 0.1 inch).

2. Route the Alert signal between the Clock and the Data signals.

1

3. Place those resistors close CPU side.

Sensitive

Sensitive

H_CPUP WRGD<19>
H_PLTR ST_CPU#<18>
H_PM_S YNC_R<18>

H_PECI<18,39>

PCH_TH ERMTRIP#_R< 18>

PROC_ SELE CT#

2 2

should be unconnected on CFL processor
EDS1.2 8/21

XEMC@

1 2

EMC@

1

XEMC@

1

EMC@

1 2

2

2

CC650.1U_0402_ 10V6K

CC661000P_ 0402_50V7K

CC670.1U_0402_ 10V6K

CC681000P_ 0402_50V7K

H_CPUP WRGD

H_PROC HOT#_R

H_THER MTRIP#

EC_VCC ST_PG

Near CPU side

follow 1050 Request

+1.05V_ VCCST

3

4 4

8/21

1

RH1 1K_040 2_5%

H_PROC HOT#<39,50>

EC_VCC ST_PG_R<39,47>

H_PM_D OWN_R<18 >

A

2

+1.05VS _VCCSTG

1

RC21
1K_040 2_5%

2

1 2

RC14 499_0 402_1%

+1.05V_ VCCST

1

RC22
1K_040 2_5%

2

1

RC15 60.4_04 02_1%

1 2

RC16 20_04 02_5%

1

RH2

@

13_040 2_5%

2

H_THER MTRIP#

2

H_PROC HOT#_R

EC_VCC ST_PG

H_PM_D OWN CPU_SV ID_ALERT#

PCH_CP U_PCIBCLK_P<16>
PCH_CP U_PCIBCLK_N<16>

PCH_CP U_24M_CLK_ P<16>
PCH_CP U_24M_CLK_ N<16>

PCH_CP U_BCLK_P<16>
PCH_CP U_BCLK_N<16>

CPU_SV ID_CLK<56,57>

RC17 0_040 2_5%@

B

1

SVID

B

2

DDR_PG _CTRL

PCH_CP U_BCLK_P
PCH_CP U_BCLK_N

PCH_CP U_PCIBCLK_P
PCH_CP U_PCIBCLK_N

PCH_CP U_24M_CLK_ P
PCH_CP U_24M_CLK_ N

CPU_SV ID_ALERT#
CPU_SV ID_CLK
CPU_SV ID_DAT

H_PROC HOT#_R

DDR_PG _CTRL

EC_VCC ST_PG

H_CPUP WRGD
H_PLTR ST_CPU#
H_PM_S YNC_R
H_PM_D OWN
H_PECI
H_THER MTRIP#

TC5TP@

TC6TP@

SKTOCC #

CATERR #

2

3

74AUP1 G07GW_T SSOP5

CPU_SVID_ALERT# _R<56,57>

CPU_SV ID_DAT<56,57>

Security Classification

Security Classification

Security Classification

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

NC1VCC

A

GND

Issued Date

Issued Date

Issued Date

B31
A32

D35
C36

E31
D31

BH31
BH32
BH29
BR30

BT13

H13

BT31
BP35

BM34

BP31
BT34

J31

BR33

BN1

BM30

AT13

AW13

AU13
AY13

UC3

5

4

Y

+1.05V_ VCCST

RC19

56_040 2_1%

C

CFL-H

UC1E

BN25

5 OF 13

CC69

1

CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8

CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15

CFG_17
CFG_16
CFG_19
CFG_18

BPM#_0
BPM#_1
BPM#_2
BPM#_3

PROC_TDO

PROC_TDI
PROC_TMS
PROC_TCK

PROC_TRST#
PROC_PREQ#
PROC_PRDY#

CFG_RCOMP

PU 330K follow CRB
8/21

Compal Secret Data

Compal Secret Data

Compal Secret Data

BN27
BN26
BN28
BR20
BM20
BT20
BP20
BR23
BR22
BT23
BT22
BM19
BR19
BP19
BT19

BN23
BP23
BP22
BN22

BR27
BT27
BM31
BT30

BT28
BL32
BP28
BR28

BP30
BL30
BP27

BT25

BCLKP
BCLKN

PCI_BCLKP
PCI_BCLKN

CLK24P
CLK24N

VIDALERT#
VIDSCK
VIDSOUT
PROCHOT#

DDR_VTT_CNTL

VCCST_PWRGD

PROCPWRGD
RESET#
PM_SYNC
PM_DOWN
PECI
THERMTRIP#

SKTOCC#
PROC_SELECT#

CATERR#

ZVM#
MSM#

RSVD1
RSVD2

CFL-H_B GA1440

+1.2V_V DDQ

2

0.1U_04 02_10V6K

SM_PG_ CTRL

1

1

RC20
100_04 02_1%

2

2

1 2

RC13 220_0 402_5%

2017/12 /18 2018/09 /01

2017/12 /18 2018/09 /01

2017/12 /18 2018/09 /01

C

CFG0

CFG2

CFG4
CFG5
CFG6
CFG7

XDP_BP M#0
XDP_BP M#1
XDP_BP M#2

XDP_BP M#3

CPU_XD P_TDO

CPU_XD P_TDI
CPU_XD P_TMS
CPU_XD P_TCK0

CPU_XD P_TRST#
XDP_PR EQ#
XDP_PR DY#

CFG_RC OMP

Trace Width/Space: 4 mil/ 12 mil
Max Trace Length: 600 mil

+3VS

1

RC23
330K_0 402_5%

2

CPU_SV ID_DAT

Deciphered Date

Deciphered Date

Deciphered Date

D

CFG0
CFG2
CFG4
CFG5
CFG6
CFG7

The CFG signals have a default valu e of '1' if not terminated on the boar d.

CFG[0]: Stall reset sequence after PCU PLL lock until de-asserted

1 = (Default) Normal Operation;

*

0 = Stall.

CFG[2]: PCI Express* Static x16 Lan e Numbering Reversal.

1 = Normal operation
0 = Lane numbers reversed.

*

CFG[4]: eDP enable:

1 = Disabled.
0 = Enabled.

*

CFG[6:5]: PCI Express* Bifurcation:

00 = 1 x8, 2 x4 PCI Express*
01 = reserved

TC1 TP@
TC2 TP@
TC3 TP@
TC4 TP@

CPU_XD P_TDO <1 9>
CPU_XDP_TDI <19>
CPU_XDP_TMS <19>
CPU_XDP_TCK 0 <19>

CPU_XDP_TRS T# <22>

TC19 TP @
TC20 TP @

RC18

2

1

49.9_04 02_1%

+1.05VS _VCCSTG

10 = 2 x8 PCI Express*
11 = 1 x16 PCI Express*

*

CFG[7]: PEG Training:

1 = (default) PEG Train immediately following RESET# de assertion.

*

0 = PEG Wait for BIOS for training.

*CFG Pin Use CMC debug on DDX03 R02 Schematic.

To be confirm

XDP_PR EQ#
XDP_PR DY#

2

CMC@

12

1

12

RC76 5 1_0402_5%CMC@

RC77 5 1_0402_5%CMC@

RC78 5 1_0402_5%

1 2

RC7 1K_040 2_5%@

1 2

RC8 1K_040 2_5%

1 2

RC9 1K_040 2_5%

1 2

RC10 1K_04 02_5%@

1 2

RC11 1K_04 02_5%@

1 2

RC12 1K_04 02_5%@

Place to CPU side

CPU_XD P_TMS

CPU_XD P_TDI

CPU_XD P_TDO

E

XDP_PREQ# <22>
XDP_PR DY# < 22>

Place to CPU side

CPU_XD P_TCK0

PCH_JT AG_TCK1

CPU_XD P_TRST#

PCH_JT AG_TCK1 <19>

11 67Thursday, Febru ary 22, 2018

11 67Thursday, Febru ary 22, 2018

11 67Thursday, Febru ary 22, 2018

E

1.0

1.0

1.0

o f

SM_PG_ CTRL <52>

D

RC79 5 1_0402_5%CMC@

RC80 5 1_0402_5%@

RC81 5 1_0402_5%@

12

12

2

1

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

CFL-H(5/8)CFG,SVID

CFL-H(5/8)CFG,SVID

CFL-H(5/8)CFG,SVID

Size Document Number R ev

Size Document Number R ev

Size Document Number R ev

Custom

Custom

Custom

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

Dat e: Sheet of

Dat e: Sheet of

Dat e: Sheet

1

3

A

B

C

D

E

GT
32000mA(Hexa Core GT2)

AT14
AT31
AT32
AT33
AT34
AT35
AT36
AT37

1

2 2

3

4 4

AT38
AU14
AU29
AU30
AU31
AU32
AU35
AU36
AU37
AU38
AV29
AV30
AV31
AV32
AV33
AV34
AV35
AV36

AW14
AW31
AW32
AW33
AW34
AW35
AW36
AW37
AW38

AY29
AY30
AY31
AY32
AY35
AY36
AY37
AY38
BA13
BA14
BA29
BA30
BA31
BA32
BA33
BA34
BA35
BA36
BB13
BB14
BB31
BB32
BB33
BB34
BB35
BB36
BB37
BB38
BC29
BC30
BC31
BC32
BC35
BC36

BC37
BC38
BD13
BD14

BD29
BD30
BD31

BD32

BD33
BD34
BP37
BP38
BR15
BR16
BR17

CFL-H

UC1K

VCCGT1
VCCGT2
VCCGT3
VCCGT4
VCCGT5
VCCGT6
VCCGT7
VCCGT8
VCCGT9
VCCGT10
VCCGT11
VCCGT12
VCCGT13
VCCGT14
VCCGT15
VCCGT16
VCCGT17
VCCGT18
VCCGT19
VCCGT20
VCCGT21
VCCGT22
VCCGT23
VCCGT24
VCCGT25
VCCGT26
VCCGT27
VCCGT28
VCCGT29
VCCGT30
VCCGT31
VCCGT32
VCCGT33
VCCGT34
VCCGT35
VCCGT36
VCCGT37
VCCGT38
VCCGT39
VCCGT40
VCCGT41
VCCGT42
VCCGT43
VCCGT44
VCCGT45
VCCGT46
VCCGT47
VCCGT48
VCCGT49
VCCGT50
VCCGT51
VCCGT52
VCCGT53
VCCGT54
VCCGT55
VCCGT56
VCCGT57
VCCGT58
VCCGT59
VCCGT60
VCCGT61
VCCGT62
VCCGT63
VCCGT64
VCCGT65
VCCGT66
VCCGT67
VCCGT68
VCCGT69
VCCGT70

VCCGT71
VCCGT72
VCCGT73

VCCGT74
VCCGT75
VCCGT76
VCCGT77
VCCGT78
VCCGT79
VCCGT159
VCCGT160
VCCGT161
VCCGT162
VCCGT163

11 OF 13

CFL-H_B GA1440

+VCC_G T+VCC_GT

BD35

VCCGT80

BD36

VCCGT81

BE31

VCCGT82

BE32

VCCGT83

BE33

VCCGT84

BE34

VCCGT85

BE35

VCCGT86

BE36

VCCGT87

BE37

VCCGT88

BE38

VCCGT89

BF13

VCCGT90

BF14

VCCGT91

BF29

VCCGT92

BF30

VCCGT93

BF31

VCCGT94

BF32

VCCGT95

BF35

VCCGT96

BF36

VCCGT97

BF37

VCCGT98

BF38

VCCGT99

BG29

VCCGT100

BG30

VCCGT101

BG31

VCCGT102

BG32

VCCGT103

BG33

VCCGT104

BG34

VCCGT105

BG35

VCCGT106

BG36

VCCGT107

BH33

VCCGT108

BH34

VCCGT109

BH35

VCCGT110

BH36

VCCGT111

BH37

VCCGT112

BH38

VCCGT113

BJ16

VCCGT114

BJ17

VCCGT115

BJ19

VCCGT116

BJ20

VCCGT117

BJ21

VCCGT118

BJ23

VCCGT119

BJ24

VCCGT120

BJ26

VCCGT121

BJ27

VCCGT122

BJ37

VCCGT123

BJ38

VCCGT124

BK16

VCCGT125

BK17

VCCGT126

BK19

VCCGT127

BK20

VCCGT128

BK21

VCCGT129

BK23

VCCGT130

BK24

VCCGT131

BK26

VCCGT132

BK27

VCCGT133

BL15

VCCGT134

BL16

VCCGT135

BL17

VCCGT136

BL23

VCCGT137

BL24

VCCGT138

BL25

VCCGT139

BL26

VCCGT140

BL27

VCCGT141

BL28

VCCGT142

BL36

VCCGT143

BL37

VCCGT144

BM15

VCCGT145

BM16

VCCGT146

BM17

VCCGT147

BM36

VCCGT148

BM37

VCCGT149

BN15

VCCGT150

BN16

VCCGT151

BN17

VCCGT152

BN36

VCCGT153

BN37

VCCGT154

BN38

VCCGT155

BP15

VCCGT156

BP16

VCCGT157

BP17

VCCGT158

BR37

VCCGT164

BT15

VCCGT165

BT16

VCCGT166

BT17

VCCGT167

BT37

VCCGT168

VSSGT_ SENSE

VSSGT_SENSE
VCCGT_SENSE

AH37

VCCGT_ SENSE

AH38

1. VccG T_SENSE / VssGT _SENSE Trace Length Match < 25 mils

2. M aintain 25-mil separa tion distance away from any other dyna mic signals.

+VCC_C ORE +VCC_C ORE +VCC_C ORE +VCC_C ORE

AA13
AA31
AA32
AA33
AA34

AA35
AA36
AA37
AA38
AB29
AB30
AB31
AB32
AB35
AB36
AB37

AB38
AC13
AC14

AC29
AC30
AC31
AC32
AC33
AC34

AC35

AC36

AD13
AD14

AD31
AD32
AD33
AD34
AD35
AD36

AD37
AD38

AE13

AE14

AE30

AE31

AE32

AE35

AE36

AE37

AE38

AF29

AF30

AF31

AF32

AF33

AF34

AF35

AF36

AF37

AF38
AG14

AG31

AG32

AG33

AG34
AG35
AG36

CFL-H_B GA1440

VSSGT_ SENSE <56>

VCCGT_ SENSE <56>

UC1I

VCC1
VCC2
VCC3
VCC4
VCC5

VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16

VCC17
VCC18
VCC19

VCC20
VCC21
VCC22
VCC23
VCC24
VCC25

VCC26

VCC27

VCC28
VCC29

VCC30
VCC31
VCC32
VCC33
VCC34
VCC35

VCC36

VCC37
VCC38

VCC39

VCC40
VCC41
VCC42
VCC43
VCC44
VCC45

VCC46
VCC47

VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57

VCC58

VCC59

VCC60

VCC61
VCC62
VCC63

CFL-H

AH13

VCC64

AH14

VCC65

AH29

VCC66

AH30

VCC67

AH31

VCC68

AH32

VCC69

AJ14

VCC70

AJ29

VCC71

AJ30

VCC72

AJ31

VCC73

AJ32

VCC74

AJ33

VCC75

AJ34

VCC76

AJ35

VCC77

AJ36

VCC78

AK31

VCC79

AK32

VCC80

AK33

VCC81

AK34

VCC82

AK35

VCC83

AK36

VCC84

AK37

VCC85

AK38

VCC86

AL13

VCC87

AL29

VCC88

AL30

VCC89

AL31

VCC90

AL32

VCC91

AL35

VCC92

AL36

VCC93

AL37

VCC94

AL38

VCC95

AM13

VCC96

AM14

VCC97

AM29

VCC98

AM30

VCC99

AM31

VCC100

AM32

VCC101

AM33

VCC102

AM34

VCC103

AM35

VCC104

AM36

VCC105

AN13

VCC106

AN14

VCC107

AN31

VCC108

AN32

VCC109

AN33

VCC110

AN34

VCC111

AN35

VCC112

AN36

VCC113

AN37

VCC114

AN38

VCC115

AP13

VCC116

AP30

VCC117

AP31

VCC118

AP32

VCC119

AP35

VCC120

AP36

VCC121

AP37

VCC122

AP38

VCC123

K13

VCC124

VCC_SENSE

9 OF 13

VSS_SENSE

1. Vc c_SENSE/ Vss_SENSE Trace Lengt h Matc h < 25 mi ls

2. M aintain 25-mil separa tion distance away from any other dyna mic signals.

AG37
AG38

128000mA(Hexa Core GT2)

VCCSEN SE
VSSSEN SE

VCCSEN SE <5 6>
VSSSEN SE <56>

K14

L13

L14
N13
N14

N30
N31
N32
N35
N36
N37
N38
P13

P14
P29

P30

P31
P32
P33

P34
P35
P36
R13
R31

R32
R33

R34

R35
R36

R37
R38
T29
T30
T31
T32

T35
T36

T37

T38

U29
U30
U31
U32
U33
U34

U35
U36
V13

V14
V31
V32
V33
V34
V35
V36
V37

V38

W13
W14
W29

W30
W31
W32

CFL-H_B GA1440

UC1J

VCC1
VCC2
VCC3
VCC4
VCC5

VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13

VCC14
VCC15

VCC16

VCC17
VCC18
VCC19

VCC20
VCC21
VCC22
VCC23
VCC24

VCC25

VCC26
VCC27

VCC28
VCC29

VCC30
VCC31
VCC32
VCC33
VCC34

VCC35
VCC36
VCC37
VCC38
VCC39

VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46

VCC47
VCC48
VCC49

VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56

VCC57
VCC58

VCC59

VCC60

VCC61
VCC62
VCC63

CFL-H

10 OF 13

VCC64
VCC65
VCC66
VCC67

VCC68
VCC69
VCC70
VCC71

VCC72
VCC73
VCC74
VCC75

W35
W36
W37
W38

Y29
Y30
Y31
Y32

Y33
Y34
Y35
Y36

1

3

Security Classification

Security Classification

Security Classification

2017/12 /18 2018/09 /01

2017/12 /18 2018/09 /01

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

A

B

2017/12 /18 2018/09 /01

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

CFL-H(6/8)VCC_CORE/GT

CFL-H(6/8)VCC_CORE/GT

CFL-H(6/8)VCC_CORE/GT

Size Document Number Re v

Size Document Number Re v

Size Document Number R ev

Custom

Custom

Custom

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

Dat e: Sheet

Dat e: Sheet

D

Dat e: Sheet of

12 67Thursday, Febru ary 22, 2018

12 67Thursday, Febru ary 22, 2018

o f

12 67Thursday, Febru ary 22, 2018

E

o f

1.0

1.0

1.0

A

+1.2V_VDDQ_CPU

+VCC_S A

+VCC_SA
Max: 11100mA

1

+VCC_IO
Max: 6400mA

2 2

+VCCIO

K29
K30
K31
K32
K33
K34
K35
L31
L32
L35
L36
L37

L38
M29
M30
M31
M32
M33
M34
M35
M36

AG12

G15
G17
G19
G21

H15

H16

H17

H19

H20

H21

H26

H27

J30

J15
J16
J17
J19
J20
J21
J26
J27

CFL-H_B GA1440

UC1L

VCCSA1
VCCSA2
VCCSA3
VCCSA4
VCCSA5
VCCSA6
VCCSA7
VCCSA8
VCCSA9
VCCSA10
VCCSA11
VCCSA12
VCCSA13
VCCSA14
VCCSA15
VCCSA16
VCCSA17
VCCSA18
VCCSA19
VCCSA20
VCCSA21
VCCSA22

VCCIO1
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
VCCIO8
VCCIO9
VCCIO10
VCCIO11
VCCIO12
VCCIO13
VCCIO14
VCCIO15
VCCIO16
VCCIO17
VCCIO18
VCCIO19
VCCIO20
VCCIO21

CFL-H

12 OF 13

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8

VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18
VDDQ19
VDDQ20
VDDQ21
VDDQ22
VDDQ23
VDDQ24
VDDQ25

VCCPLL_OC1
VCCPLL_OC2
VCCPLL_OC3

VCCST

VCCSTG2

VCCSTG1

VCCPLL1
VCCPLL2

VCCSA_SENSE
VSSSA_SENSE

VCCIO_SENSE

VSSIO_SENSE

Max: 3300mA

+1.2V_V DDQ_CPU

AA6
AE12
AF5
AF6
AG5
AG9
AJ12
AL11
AP6
AP7
AR12
AR6
AT12
AW6
AY6
J5
J6
K12
K6
L12
L6
R6
T6
W6
Y12

+1.2V_V CCPLL_OC

BH13
BJ13
G11

H30

H29

G30

H28
J28

M38
M37

H14
J14

B

+1.2V_V DDQ_CPU

JPC1

112

JPC2

112

+1.2V_V DDQ

2

2

VCCSA_ SENSE <57>

VSSSA_ SENSE <5 7>

VCCIO_SE NSE <55>

VSSIO_SE NSE < 55>

+1.2V_VDDQ_CPU

3.3A

@

JUMP_4 3X118

@

JUMP_4 3X118

+1.2V_VCCPLL_OC
Max: 130mA

+1.05V_ VCCST

Max: 60mA

Max: 20mA

Max: 150mA

VCCIO_SE NSE
VSSIO_SE NSE

1. VccG T_SENSE / VssGT _SENSE Trace Length Match < 25 mils

2. M aintain 25-mil separa tion distance away from any other dyna mic signals.

+1.05VS _VCCSTG

+1.05V_ VCCSFR

VCCSA_ SENSE
VSSSA_ SENSE

C

10U_0402_6.3V6M

1

CC70

2

10U_0603_6.3V6M

10U_0603_6.3V6M

1

2

571483_CFL_H_RVP_CRB_TDK_Rev0p5
+1.2V_VDDQ_CPU: 10uF * 12 22uF * 4

1

1

CC72

CC71

2

2

10U_0603_6.3V6M

CC73

10U_0603_6.3V6M

1

CC74

2

RC24 0_040 2_5%@

10U_0402_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

1

1

1

CC76

CC75

2

2

CC77

2

PLACE CAP BACKSIDE

+1.2V_V CCPLL_OC+1.2V_V DDQ

1 2

1

2

571483_CFL_H_RVP_CRB_TDK_Rev0p5
+1.2V_VCCPLL_OC: 1uF * 2

PLACE CAP BACKSIDE

+1.05V_ VCCST

1U_0201_6.3V6M

1

CC92

2

571483_CFL_H_RVP_CRB_TDK_Rev0p5
+1.05V_VCCST: 1uF * 1

10U_0603_6.3V6M

1

CC78

2

1U_0201_6.3V6M

1

CC86

2

RC25 0_040 2_5%@

D

10U_0603_6.3V6M

1

2

1U_0201_6.3V6M

CC87

1

1

1

CC80

CC79

2

2

+VCCIO

2

150mA

10U_0603_6.3V6M

10U_0603_6.3V6M

22U_0603_6.3V6M

1

CC82

CC81

2

10U_0603_6.3V6M

10U_0603_6.3V6M

1

1

CC88

2

2

571483_CFL_H_RVP_CRB_TDK_Rev0p5
+0.95VS_VCCIO: 10uF * 12 22uF * 4

+1.05V_ VCCSFR

1U_0201_6.3V6M

1

CC93

2

571483_CFL_H_RVP_CRB_TDK_Rev0p5
+1.05V_VCCSFR: 1uF * 1

22U_0603_6.3V6M

22U_0603_6.3V6M

1

1

2

1

CC89

2

1

CC84

CC83

2

2

10U_0402_6.3V6M

10U_0603_6.3V6M

@

1

CC91

CC90

2

E

22U_0603_6.3V6M

CC85

PLACE CAP BACKSIDE PLACE CAP BACKSIDE

1

3

4 4

Security Classification

Security Classification

Security Classification

2017/12 /18 2018/09 /01

2017/12 /18 2018/09 /01

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

A

B

2017/12 /18 2018/09 /01

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

+1.05VS _VCCSTG

1U_0201_6.3V6M

1

CC94

2

571483_CFL_H_RVP_CRB_TDK_Rev0p5
+1.05VS_VCCSTG: 1uF * 1

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

CFL-H(7/8)VCCSA/VCCIO/VDDQ

CFL-H(7/8)VCCSA/VCCIO/VDDQ

CFL-H(7/8)VCCSA/VCCIO/VDDQ

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

Dat e: Sheet

Dat e: Sheet of

Dat e: Sheet of

13 67Thursday, Febru ary 22, 2018

13 67Thursday, Febru ary 22, 2018

o f

13 67Thursday, Febru ary 22, 2018

E

1.0

1.0

1.0

3

A

B

C

D

E

CFL-H

UC1F

A10

VSS_1

A12

VSS_2

A16

VSS_3

A18

VSS_4

A20

VSS_5

A22

VSS_6

A24

VSS_7

A26

VSS_8

1

2 2

3

A28
A30

AA12
AA29
AA30
AB33
AB34

AB6
AC1

AC12

AC2

AC3
AC37
AC38

AC4

AC5

AC6
AD10
AD11
AD12
AD29
AD30

AD6

AD8

AD9
AE33
AE34

AE6

AF1
AF12
AF13
AF14

AF2

AF3

AF4
AG10

AG11

AG13
AG29
AG30

AG6

AG7

AG8
AH12
AH33
AH34
AH35
AH36

AH6

AJ1

AJ13

AJ2

AJ3
AJ37
AJ38

AJ4

AJ5

AJ6

Y10

Y11

Y13

Y14

Y37

Y38

AK29
AK30

A6
A9

W4
W5

Y7
Y8
Y9

VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43

VSS_44
VSS_45
VSS_46
VSS_47

VSS_48

VSS_49
VSS_50
VSS_51

VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80

6 OF 13

VSS_81

CFL-H_B GA1440

VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98

VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152

VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162

AK4
AL10
AL12
AL14
AL33
AL34
AL4
AL7
AL8
AL9
AM1
AM12
AM2
AM3
AM37
AM38
AM4
AM5
AN12
AN29
AN30
AN5
AN6
AP10
AP11
AP12
AP33
AP34
AP8
AP9
AR1
AR13
AR14
AR2
AR29
AR3
AR30
AR31
AR32
AR33
AR34
AR35
AR36
AR37
AR38
AR4
AR5
AT29
AT30
AT6
AU10
AU11
AU12
AU33
AU34

AU6
AU7

AU8
AU9
AV37
AV38
AW1
AW12
AW2
AW29
AW3
AW30
AW4
U6
V12

V29
V30
A14
AD7
V6
W1
W12
W2
W3
W33
W34

AW5
AY12
AY33
AY34

BA10
BA11
BA12
BA37
BA38

BA6
BA7
BA8
BA9
BB1

BB12

BB2

BB29

BB3

BB30

BB4
BB5

BB6
BC12
BC13
BC14
BC33
BC34

BC6
BD10
BD11
BD12
BD37

BD6

BD7

BD8

BD9

BE1

BE2
BE29

BE3
BE30

BE4

BE5

BE6

BF12
BF33
BF34

BF6
BG12
BG13
BG14
BG37
BG38

BG6

BH1
BH10
BH11
BH12
BH14

BH2

BH3

BH4

BH5

BH6

BH7

BH8

BH9

T33
T34

U37

U38
BJ12
BJ14

UC1G

VSS_163
VSS_164
VSS_165
VSS_166

B9

VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230

T2

VSS_231

T3

VSS_232
VSS_233
VSS_234

T4

VSS_235

T5

VSS_236

T7

VSS_237

T8

VSS_238

T9

VSS_239
VSS_240
VSS_241
VSS_242
VSS_243

CFL-H_B GA1440

CFL-H

7 OF 13

VSS_244
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
VSS_253
VSS_254
VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261

VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271

VSS_272

VSS_273

VSS_274

VSS_275

VSS_276
VSS_277
VSS_278
VSS_279

VSS_280
VSS_281
VSS_282

VSS_283
VSS_284

VSS_285
VSS_286

VSS_287

VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
VSS_314
VSS_315
VSS_316
VSS_317
VSS_318
VSS_319
VSS_320
VSS_321
VSS_322
VSS_323
VSS_324

BJ15
BJ18
BJ22
BJ25
BJ29
BJ30
BJ31
BJ32
BJ33
BJ34
BJ35
BJ36
BK13
BK14

BK15

BK18
BK22

BK25
BK29
BK6
BL13
BL14
BL18
BL19
BL20
BL21
BL22

BL29
BL33

BL35

BL38

BL6

BM11
BM12
BM13
BM14

BM18
BM2
BM21

BM22

BM23
BM24
BM25

BM26

BM27
BM28
BM29
BM3
BM33
BM35
BM38
BM5

BM6

BM7
BM8
BM9
BN12
BN14
BN18
BN19
BN2
BN20
BN21
BN24
BN29
BN30
BN31
BN34
P38
P6
R12
R29
AY14
BD38
R30
T1
T10
T11
T12
T13
T14

BN4

BN7
BP12
BP14
BP18
BP21
BP24
BP25
BP26
BP29
BP33
BP34

BR12
BR14
BR18
BR21
BR24

BR25
BR26
BR29
BR34

BR36

BR7

BT12
BT14
BT18
BT21
BT24
BT26
BT29
BT32

M14

BP7

BT5
C11
C13
C15

C17
C19
C21
C23
C25
C27
C29
C31
C37

D10
D12
D14
D16
D18
D20
D22
D24
D26
D28

D30
D33

E34
E35
E38

N33
N34

P12
P37

F11
F13

C5
C8
C9

D3

D6
D9

E4
E9
N3

N4
N5
N6
N7
N8
N9

M6

N1

CFL-H

UC1H

VSS_325
VSS_326
VSS_327
VSS_328
VSS_329
VSS_330
VSS_331
VSS_332
VSS_333
VSS_334
VSS_335
VSS_336
VSS_337
VSS_338
VSS_339
VSS_340
VSS_341
VSS_342
VSS_343
VSS_344

VSS_345
VSS_346
VSS_347

VSS_348
VSS_349

VSS_350

VSS_351
VSS_352
VSS_353
VSS_354
VSS_355
VSS_356
VSS_357
VSS_358
VSS_359

VSS_360

VSS_361

VSS_362
VSS_363
VSS_364
VSS_365
VSS_366
VSS_367
VSS_368
VSS_369
VSS_370
VSS_371
VSS_372
VSS_373
VSS_374
VSS_375
VSS_376
VSS_377
VSS_378
VSS_379
VSS_380
VSS_381
VSS_382
VSS_383
VSS_384
VSS_385
VSS_386
VSS_387
VSS_388
VSS_389
VSS_390
VSS_391
VSS_392
VSS_393
VSS_394
VSS_395
VSS_396
VSS_397
VSS_398
VSS_399
VSS_400
VSS_401
VSS_402

VSS_BR38
VSS_403
VSS_404

VSS_BT35

VSS_BT36

VSS_405
VSS_406
VSS_407

8 OF 13

VSS_408

CFL-H_B GA1440

VSS_409
VSS_410
VSS_411
VSS_412

VSS_413
VSS_414
VSS_415

VSS_416
VSS_417
VSS_418
VSS_419
VSS_420
VSS_421
VSS_422
VSS_423
VSS_424
VSS_425
VSS_426
VSS_427
VSS_428
VSS_429
VSS_430
VSS_431
VSS_432
VSS_433
VSS_434
VSS_435
VSS_436
VSS_437
VSS_438
VSS_439
VSS_440
VSS_441
VSS_442
VSS_443
VSS_444
VSS_445
VSS_446
VSS_447
VSS_448
VSS_449
VSS_450
VSS_451
VSS_452
VSS_453
VSS_454
VSS_455
VSS_456
VSS_457
VSS_458
VSS_459
VSS_460
VSS_461
VSS_462
VSS_463
VSS_464
VSS_465
VSS_466
VSS_467
VSS_468
VSS_469
VSS_470
VSS_471
VSS_472
VSS_473
VSS_474
VSS_475
VSS_476
VSS_477
VSS_478
VSS_479

VSS_A3

VSS_A34

VSS_A4
VSS_B3

VSS_B37

VSS_BT3

VSS_BT4

VSS_C2

VSS_D38

F15
F17
F19

F2
F21
F23
F25

F27
F29
F3

F31

F36
F4
F5
F8
F9
G10
G12
G14
G16
G18
G20
G22
G23
G24
G26
G28
G4
G5
G6
G8
G9
H11
H12
H18
H22
H25
H32
H35
J10
J18
J22
J25
J32
J33
J36
J4
J7
K1
K10
K11
K2
K3
K38
K4
K5
K7
K8
K9
L29
L30
L33
L34
M12
M13
N10
N11
N12
N2
BT8
BR9

A3
A34
A4
B3
B37
BR38
BT3
BT35
BT36
BT4
C2
D38

Impedance Spectrum Tool Trigger

PCH_TR IGOUT_R<22>
CPU_TR IGOUT_R<22>

1 2

RC26 30_04 02_5%

TC7TP@

IST_TRIG

TC8TP@

TC9TP@
TC10T P@

TC11T P@
TC12T P@

PCH_TR IGOUT_R
CPU_TR IGOUT

BR1

BT2

BN35

H24
BN33
BL34

N29

R14
AE29
AA14
AP29
AP14

A36

A37

H23

F30

E30

B30

C30

BR35
BR31
BH30

E2
E3
E1
D1

J24

J23

G3

J3

UC1M

RSVD_TP5
IST_TRIG
RSVD_TP4
RSVD_TP3

RSVD_TP1
RSVD_TP2

RSVD15

RSVD28
RSVD27
RSVD14
RSVD13

RSVD30
RSVD31
RSVD2
RSVD1
RSVD5
RSVD4
VSS_A36

VSS_A37

PROC_TRIGIN
PROC_TRIGOUT

RSVD24

RSVD23

RSVD7
RSVD21

RSVD26
RSVD29

RSVD19
RSVD18
RSVD9

CFL-H_B GA1440

CFL-H

13 OF 13

BK28

RSVD11

BJ28

RSVD10

BL31

RSVD12

AJ8

RSVD3

G13

RSVD25

C38

RSVD22

C1

RSVD20

BR2

RSVD17

BP1

RSVD16

B38

RSVD8

B2

RSVD6

Add for Corner NCTF testing

TC13 TP @
TC14 TP @
TC15 TP @
TC16 TP @
TC17 TP @
TC18 TP @

1

3

4 4

Security Classification

Security Classification

Security Classification

2017/12 /18 2018/09 /01

2017/12 /18 2018/09 /01

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

A

B

2017/12 /18 2018/09 /01

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

CFL-H(8/8)GND/RSVD

CFL-H(8/8)GND/RSVD

CFL-H(8/8)GND/RSVD

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

Dat e: Sheet

Dat e: Sheet of

D

Dat e: Sheet

14 67Thursday, Febru ary 22, 2018

o f

14 67Thursday, Febru ary 22, 2018

14 67Thursday, Febru ary 22, 2018

E

o f

1.0

1.0

1.0

A

DMI_CTX_ PRX_N0<10>

DMI_CTX_ PRX_P0<10>
DMI_CRX_ PTX_N0<10>
DMI_CRX_ PTX_P0<10>

DMI_CTX_ PRX_N1<10>

DMI_CTX_ PRX_P1<10>
DMI_CRX_ PTX_N1<10>
DMI_CRX_ PTX_P1<10>

DMI_CTX_ PRX_N2<10>

DMI_CTX_ PRX_P2<10>

1

2 2

3

DMI_CRX_ PTX_N2<10>

DMI_CRX_ PTX_P2<10>

DMI_CTX_ PRX_N3<10>

DMI_CTX_ PRX_P3<10>

DMI_CRX_ PTX_N3<10>

DMI_CRX_ PTX_P3<10>

B

DMI_CTX_ PRX_N0

DMI_CTX_ PRX_P0
DMI_CRX_ PTX_N0
DMI_CRX_ PTX_P0

DMI_CTX_ PRX_N1

DMI_CTX_ PRX_P1
DMI_CRX_ PTX_N1
DMI_CRX_ PTX_P1

DMI_CTX_ PRX_N2

DMI_CTX_ PRX_P2
DMI_CRX_ PTX_N2
DMI_CRX_ PTX_P2

DMI_CTX_ PRX_N3

DMI_CTX_ PRX_P3

DMI_CRX_ PTX_N3
DMI_CRX_ PTX_P3

UH1B

K34

DMI0_RXN

J35

DMI0_RXP

C33

DMI0_TXN

B33

DMI0_TXP

G33

DMI1_RXN

F34

DMI1_RXP

C32

DMI1_TXN

B32

DMI1_TXP

K32

DMI2_RXN

J32

DMI2_RXP

C31

DMI2_TXN

B31

DMI2_TXP

G30

DMI3_RXN

F30

DMI3_RXP

C29

DMI3_TXN

B29

DMI3_TXP

A25

RSVD

B25

RSVD

P24

RSVD

R24

RSVD

C26

RSVD

B26

RSVD

F26

RSVD

G26

RSVD

B27

RSVD

C27

RSVD

L26

RSVD

M26

RSVD

D29

RSVD

E28

RSVD

K29

RSVD

M29

RSVD

G17

PCIE1_RXN/USB31_7_RXN

F16

PCIE1_RXP/USB31_7_RXP

A17

PCIE1_TXN/USB31_7_TXN

B17

PCIE1_TXP/USB31_7_TXP

R21

PCIE2_RXN/USB31_8_RXN

P21

PCIE2_RXP/USB31_8_RXP

B18

PCIE2_TXN/USB31_8_TXN

C18

PCIE2_TXP/USB31_8_TXP

K18

PCIE3_RXN/USB31_9_RXN

J18

PCIE3_RXP/USB31_9_RXP

B19

PCIE3_TXN/USB31_9_TXN

C19

PCIE3_TXP/USB31_9_TXP

N18

PCIE4_RXN/USB31_10_RXN

R18

PCIE4_RXP/USB31_10_RXP

D20

PCIE4_TXN/USB31_10_TXN

C20

PCIE4_TXP/USB31_10_TXP

F20

PCIE5_RXN

G20

PCIE5_RXP

B21

PCIE5_TXN

A22

PCIE5_TXP

K21

PCIE6_RXN

J21

PCIE6_RXP

D21

PCIE6_TXN

C21

PCIE6_TXP

B23

PCIE7_TXP

C23

PCIE7_TXN

J24

PCIE7_RXP

L24

PCIE7_RXN

F24

PCIE8_RXN

G24

PCIE8_RXP

B24

PCIE8_TXN

C24

PCIE8_TXP

CNP-H_B GA874

C

CNP-H

GPP_E9/USB2_OC0#
GPP_E10/USB2_OC1#
GPP_E11/USB2_OC2#
GPP_E12/USB2_OC3#
GPP_F15/USB2_OC4#
GPP_F16/USB2_OC5#
GPP_F17/USB2_OC6#
GPP_F18/USB2_OC7#

USB2_VBUSSENSE

2 OF 13

USB2N_1
USB2P_1
USB2N_2

USB2P_2
USB2N_3
USB2P_3

USB2N_4
USB2P_4
USB2N_5
USB2P_5
USB2N_6
USB2P_6
USB2N_7
USB2P_7
USB2N_8
USB2P_8
USB2N_9

USB2P_9
USB2N_10
USB2P_10
USB2N_11
USB2P_11
USB2N_12
USB2P_12
USB2N_13
USB2P_13
USB2N_14
USB2P_14

USB2_COMP

RSVD1

USB2_ID

GPD7

PCIE24_TXP
PCIE24_TXN
PCIE24_RXP
PCIE24_RXN

PCIE23_TXP
PCIE23_TXN
PCIE23_RXP
PCIE23_RXN

PCIE22_TXP
PCIE22_TXN
PCIE22_RXP
PCIE22_RXN

PCIE21_TXP
PCIE21_TXN
PCIE21_RXP
PCIE21_RXN

Rev1.0

J3
J2

N13
N15
K4
K3

M10
L9
M1

L2

K7
K6
L4
L3
G4
G5
M6
N8
H3
H2
R10
P9
G1
G2
N3
N2
E5
F6

AH36
AL40
AJ44
AL41
AV47
AR35
AR37
AV43

F4
F3
U13
G3

BE41

G45
G46
Y41
Y40
G48
G49
W44
W43
H48
H47
U41
U40
F46
G47
R44
T43

D

USB20_ N1
USB20_ P1
USB20_ N2
USB20_ P2
USB20_ N3
USB20_ P3
USB20_ N4
USB20_ P4
USB20_ N5
USB20_ P5
USB20_ N6
USB20_ P6

USB20_ N8
USB20_ P8

USB20_ N14
USB20_ P14

USB_OC 0#
USB_OC 1#
USB_OC 2#
USB_OC 3#

USB2_R COMP
USB2_V BUS_SENSE

USB2_ID

GPD_7

The 30 HSIO lanes on PCH-H supports the following configurations:

1. Up to 24 PCIe* Lanes

— A maximum of 16 PCIe* Ports (or devices) can be enabled

When a GbE Port is enabled, the maximum number of PCIe* Ports (or



devices) that can be enabled reduces based off the following:
Max PCIe* Ports (or devices) = 16 - GbE (0 or 1)
— PCIe* Lanes 1-4 (PCIe* Controller #1), 5-8 (PCIe* Controller #2), 9-12 (PCIe*
Controller #3), 13-16 (PCIe* Controller #4), 17-20 (PCIe* Controller #5), and
21-24 (PCIe* Controller #6) can be individually configured

2. Up to 6 SATA Lanes
— A maximum of 6 SATA Ports (or devices) can be enabled
— SATA Lane 0 has the flexibility to be mapped to Flex I/O Lane 16 or 18
— SATA Lane 1 has the flexibility to be mapped to Flex I/O Lane 17 or 19

3. Up to 10 USB 3.1 Lanes
— A maximum of 10 USB 3.1 Ports (or devices) can be enabled

4. Up to 4 GbE Lanes
— A maximum of 1 GbE Port (or device) can be enabled

5. Supports up to 3 Remapped (IntelR Rapid Storage Technology) PCIe* storage
device s
— x2 and x4 PCIe* NVMe SSD
— x2 IntelR Optane? Memory Device
— See the “ PCI Express * (PCIe*)” chapt er for t he P CH PCI e* Controllers,configurations
, and lanes that can be used for IntelR Rapid Storage Technology PCIe* storage support

6. For unused SATA/PCIe* Combo Lanes, Flex I/O Lanes that can be configured as PCIe* or SATA,
the lanes must be statically assigned to SATA or PCIe* via the SATA/PCIe Combo Port Soft
Straps discussed in the SPI Programming Guide and
through the IntelR Flash Image Tool (FIT) tool.

USB20_ N1 <42>
USB20_ P1 <42>
USB20_ N2 <41>
USB20_ P2 <41>
USB20_ N3 <44>
USB20_ P3 <44>
USB20_ N4 <44>
USB20_ P4 <44>
USB20_ N5 <33>
USB20_ P5 <33>
USB20_ N6 <33>
USB20_ P6 <33>

USB20_ N8 <46>
USB20_ P8 <46>

USB20_ N14 <37 >
USB20_ P14 <37>

USB_OC 0# <40>

USB_OC 1# <42>

1 2

RH4 113_040 2_1%
RH5 0_0402_ 5%@

RH6 0_0402_ 5%@

1

1 2

2

USB3 MB

TYPE C

USB2 (SUB/B)

Cam er a

TS

FingerPrint

FOR CNVI follow 571906_CNL_PCH_TA_WW11.pdf

BT

USB_OC 0#
USB_OC 1#
USB_OC 2#
USB_OC 3#

STRAP

E

RPH1

10K_08 04_8P4R_5%

GPD_7

X'tal Input:
High: Differential
Low: Single ended

+3VALW _PCH_PR IM

18
27
36
45

+3VALW

1

RH3
10K_04 02_5%

2

1

RH7
10K_04 02_5%

@

2

1

3

4 4

Security Classification

Security Classification

Security Classification

2017/12 /18 2018/09 /01

2017/12 /18 2018/09 /01

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

A

B

2017/12 /18 2018/09 /01

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

PCH(1/8)DMI/PCIE/USB2

PCH(1/8)DMI/PCIE/USB2

PCH(1/8)DMI/PCIE/USB2

Size Document Number R ev

Size Document Number R ev

Size Document Number R ev

Custom

Custom

Custom

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

Dat e: Sheet of

Dat e: Sheet of

D

Dat e: Sheet of

15 67Thursday, Febru ary 22, 2018

15 67Thursday, Febru ary 22, 2018

15 67Thursday, Febru ary 22, 2018

E

1.0

1.0

1.0

A

B

C

D

E

PCH-H XTAL_IN/OUT POR is 24MHz for 571697_CNL_MOW_WW16_2017.pdf

RH8 1M_040 2_5%

YH1
24MHZ_ 18PF_XRCGB 24M000F2P5 1R0

1

2 2

3

4 4

3

33P_0402_50V8J

3

CH5

10P_0402_50V8J

1

32.768K HZ_9PF_X1A 0001410002 00

CH7

2

+3VS

For DDX03 R02

+1.8VAL W_PRIM

RH15 4.7K_0 402_5%

This signal has a weak internal pul l-down 20K.
0 = 38.4/19.2MHz XTAL frequency sel ected.
1 = 24MHz XTAL frequency selected. (DDX03)
Notes:

1. The internal pull-down is disabl ed after RSMRST#
de-asserts.

2. This signal is in the primary we ll.

+1.8VAL W_PRIM

RH21 4.7K_0 402_5%

The signal has a weak internal pull -down 20K
0 = VCCPSPI is connected to 3.3V ra il
1 = VCCPSPI is connected to 1.8V ra il
Note: If VCCPSPI is connected to 1. 8V rail, this pin

strap must be a ‘ 1’ fo r th e proper functionalit y
of the SPI (Flash) I/Os

+1.8VAL W_PRIM

RH22 10K_04 02_5%

RH23 10K_04 02_5%@

XTAL_2 4M_PCH_OUT

NC

2

XTAL_2 4M_PCH_IN

1

1

1 2

NC

4

1 2

RH12 10M_0402 _5%

YH2

1 2

Trace Space: 15 mil
Max Trace Length: 1000 mil

1 2

EMC@

RH11 33 _0402_1%

1 2

EMC@

RH9 33_ 0402_1%

18P_0402_50V8J

CH6

PCH_RT CX1

PCH_RT CX2

10P_0402_50V8J

1

CH8

2

use same part w C5MMH

RPH2

7

5

10K_08 04_8P4R_5%

XTAL Frequency Select

1 2

VCCPSPI Select

1

2

An external pull-up or pull-down is required.
0 = Integrated CNVi enable.
1 = Integrated CNVi disable.

Pulled down by CRF CNVi RGI_DT pin

LAN_CL KREQ#

18

VGA_CL KREQ#

2

WLA N_CLKREQ#

36

SSD_CL KREQ#

4

@

2

M.2 CNV Mode Select

12

1

A

CNV_BR I_PTX_DRX

GPP_J9

CNV_RG I_PTX_DRX

XTAL_2 4M_PCH_OUT _R

XTAL_2 4M_PCH_IN_R

VGA_CL KREQ# <25>

STRAP

STRAP

STRAP

PCH_CP U_24M_CLK_ P<11>
PCH_CP U_24M_CLK_ N<11>

PCH_CP U_BCLK_P<11>
PCH_CP U_BCLK_N<11> PCH_CP U_PCIBCLK_P <1 1>

1

XCLK_BIASREF (PDG)
Trace Width/Space: 15mil /15 mil
Max Trace Length: 1000 mil
8/24

RH10 60.4_0 402_1%

2

LAN_CL KREQ#<36>

WLA N_CLKREQ#<37>

SSD_CL KREQ#< 35>

remove no use srcclkreq

remove SD signal from PCH

remove CPU_C10_GATE#

CNV_BR I_PTX_DRX<37>
CNV_BR I_PRX_DTX<37>
CNV_RG I_PTX_DRX<37>
CNV_RG I_PRX_DTX<37>

+1.8VAL W_PRIM

1 2

RH181 20K_0 402_1%CNVI@

571391_CFL_H_PDG_Rev0p71
To avoid floating input at the I/O pin BRI_RSP and RGI_RSP it is recommen ded to add
a weak pull up resistor to the SoC pin with a recommended value of 20K oh m.

B

RH182 20K_0 402_1%CNVI@

2

1

remove TP as C5PRH

PCH_CP U_24M_CLK_ P
PCH_CP U_24M_CLK_ N

PCH_CP U_BCLK_P
PCH_CP U_BCLK_N

XTAL_2 4M_PCH_OUT _R
XTAL_2 4M_PCH_IN_R

XCLK_B IASREF

PCH_RT CX1
PCH_RT CX2

VGA_CL KREQ#
LAN_CL KREQ#
WLA N_CLKREQ#

SSD_CL KREQ#

AW13

BE9
BF8
BF9

BG8

BE8

BD8

AV13

AP3
AP2
AN4

AM7

AV6
AY3

AR13

AV7

AW3

CNV_BR I_PTX_DRX

CNV_BR I_PRX_DTX
CNV_RG I_PTX_DRX
CNV_RG I_PRX_DTX

GPP_J9

CNV_BR I_PRX_DTX

CNV_RG I_PRX_DTX

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

AT10

AV4
AY2
BA4
AV3

AW2

AU9

2017/12 /18 2018/09 /01

2017/12 /18 2018/09 /01

2017/12 /18 2018/09 /01

C

UH1G

BE33

GPP_A16/CLKOUT_48

D7

CLKOUT_CPUNSSC_P

C6

CLKOUT_CPUNSSC#

B8

CLKOUT_CPUBCLK_P

C8

CLKOUT_CPUBCLK#

U9

XTAL_OUT

U10

XTAL_IN

T3

XCLK_BIASREF

BA49

RTCX1

BA48

RTCX2

BF31

GPP_B5/SRCCLKREQ0#

BE31

GPP_B6/SRCCLKREQ1#

AR32

GPP_B7/SRCCLKREQ2#

BB30

GPP_B8/SRCCLKREQ3#

BA30

GPP_B9/SRCCLKREQ4#

AN29

GPP_B10/SRCCLKREQ5#

AE47

GPP_H0/SRCCLKREQ6#

AC48

GPP_H1/SRCCLKREQ7#

AE41

GPP_H2/SRCCLKREQ8#

AF48

GPP_H3/SRCCLKREQ9#

AC41

GPP_H4/SRCCLKREQ10#

AC39

GPP_H5/SRCCLKREQ11#

AE39

GPP_H6/SRCCLKREQ12#

AB48

GPP_H7/SRCCLKREQ13#

AC44

GPP_H8/SRCCLKREQ14#

AC43

GPP_H9/SRCCLKREQ15#

V2

CLKOUT_PCIE_N15

V3

CLKOUT_PCIE_P15

T2

CLKOUT_PCIE_N14

T1

CLKOUT_PCIE_P14

AA1

CLKOUT_PCIE_N13

Y2

CLKOUT_PCIE_P13

AC7

CLKOUT_PCIE_N12

AC6

CLKOUT_PCIE_P12

CNP-H_B GA874

UH1M

GPP_G0/SD_CMD
GPP_G1/SD_DATA0
GPP_G2/SD_DATA1
GPP_G3/SD_DATA2
GPP_G4/SD_DATA3
GPP_G5/SD_CD#
GPP_G6/SD_CLK
GPP_G7/SD_WP

GPP_I11/M2_SKT2_CFG0
GPP_I12/M2_SKT2_CFG1
GPP_I13/M2_SKT2_CFG2
GPP_I14/M2_SKT2_CFG3

GPP_J0/CNV_PA_BLANKING
GPP_J1/CPU_C10_GATE#
GPP_J11/A4WP_PRESENT
GPP_J10
GPP_J_2
GPP_J_3
GPP_J4/CNV_BRI_DT/UART0B_RTS#
GPP_J5/CNV_BRI_RSP/UART0B_RXD
GPP_J6/CNV_RGI_DT/UART0B_TXD
GPP_J7/CNV_RGI_RSP/UART0B_CTS#
GPP_J8/CNV_MFUART2_RXD
GPP_J9/CNV_MFUART2_TXD

CNP-H_B GA874

Compal Secret Data

Compal Secret Data

Compal Secret Data

CNP-H

CLKOUT_ITPXDP#

CLKOUT_ITPXDP_P

CLKOUT_CPUPCIBCLK#

CLKOUT_CPUPCIBCLK_P

CLKOUT_PCIE_N0
CLKOUT_PCIE_P0

CLKOUT_PCIE_N1
CLKOUT_PCIE_P1

CLKOUT_PCIE_N2
CLKOUT_PCIE_P2

CLKOUT_PCIE_N3
CLKOUT_PCIE_P3

CLKOUT_PCIE_N4
CLKOUT_PCIE_P4

CLKOUT_PCIE_N5
CLKOUT_PCIE_P5

CLKOUT_PCIE_N6
CLKOUT_PCIE_P6

CLKOUT_PCIE_N7
CLKOUT_PCIE_P7

CLKOUT_PCIE_N8
CLKOUT_PCIE_P8

CLKOUT_PCIE_N9
CLKOUT_PCIE_P9

CLKOUT_PCIE_N10
CLKOUT_PCIE_P10

CLKOUT_PCIE_N11
CLKOUT_PCIE_P11

7 OF 13

CNP-H

3.3V

1.8V

13 OF 13

Deciphered Date

Deciphered Date

Deciphered Date

Y3
Y4

B6
A6

AJ6
AJ7

AH9
AH10

AE14
AE15

AE6
AE7

AC2
AC3

AB2
AB3

W4
W3

W7
W6

AC14
AC15

U2
U3

AC9
AC11

AE9
AE11

CLKIN_XTAL

GPPJ_RCOMP_1P81
GPPJ_RCOMP_1P82
GPPJ_RCOMP_1P83

R6

Rev1.0

CNV_WR_CLKN
CNV_WR_CLKP

CNV_WR_D0N
CNV_WR_D0P
CNV_WR_D1N
CNV_WR_D1P

CNV_WT_CLKN
CNV_WT_CLKP

CNV_WT_D0N
CNV_WT_D0P
CNV_WT_D1N
CNV_WT_D1P

CNV_WT_RCOMP

PCIE_RCOMPN

PCIE_RCOMPP
SD_1P8_RCOMP
SD_3P3_RCOMP

RSVD2
RSVD3

RSVD1

Rev1.0

PCH_CP U_PCIBCLK_N
PCH_CP U_PCIBCLK_P

CLK_PE G_VGA#
CLK_PE G_VGA

CLK_PC IE_LAN#
CLK_PC IE_LAN

CLK_PC IE_WLAN#
CLK_PC IE_WLAN

CLK_PC IE_NGFF#
CLK_PC IE_NGFF

BD4
BE3

BB3
BB4
BA3
BA2

BC5
BB6

BE6
BD7
BG6
BF6
BA1

B12
A13
BE5
BE4
BD1
BE1
BE2

Y35
Y36

BC1
AL35

TP

D

TH2TP@
TH3TP@

REFCLK _CNV

1

RH14

10K_04 02_5%

2

CLK_CN V_PRX_DTX_ N
CLK_CN V_PRX_DTX_ P

CNV_PR X_DTX_N0
CNV_PR X_DTX_P0
CNV_PR X_DTX_N1
CNV_PR X_DTX_P1

CLK_CN V_PTX_DRX_ N

CLK_CN V_PTX_DRX_ P

CNV_PT X_DRX_N0
CNV_PT X_DRX_P0
CNV_PT X_DRX_N1
CNV_PT X_DRX_P1

CNV_W T_RCOMP

PCIE_RCO MPN
PCIE_RCO MPP

SD_RCO MP_1P8
SD_RCO MP_3P3

GPPJ_R COMP_1P8

RH16

RH17 100_0 402_1%

RH18 200_0 402_1%
RH19 200_0 402_1%

RH20 200_0 402_1%

#571483_CFL_H_RVP_CRB_TDK_Rev0p5
Recommend external test point

Title

Title

Title

Size Document Number R ev

Size Document Number R ev

Size Document Number R ev

Custom

Custom

Custom

Dat e: Sheet of

Dat e: Sheet of

Dat e: Sheet

PCH_CP U_PCIBCLK_N <11>

CLK_PEG_VGA# <25>

CLK_PEG_VGA <25>

CLK_PC IE_LAN# <36>

CLK_PC IE_LAN <36>

CLK_PC IE_WLAN# <37>

CLK_PC IE_WLAN < 37>

CLK_PC IE_NGFF# <35>
CLK_PC IE_NGFF <35>

REFCLK _CNV <37>

CNV_PR X_DTX_N0 < 37>
CNV_PR X_DTX_P0 <37 >
CNV_PR X_DTX_N1 < 37>
CNV_PR X_DTX_P1 <37 >

CNV_PT X_DRX_N0 <3 7>
CNV_PT X_DRX_P0 <37>
CNV_PT X_DRX_N1 <3 7>

2

1

1

1
1 2

1 2

TH4TP@

150_04 02_1%

2

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

PCH(2/8)CLK/CNVI/SD

PCH(2/8)CLK/CNVI/SD

PCH(2/8)CLK/CNVI/SD

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

CNV_PT X_DRX_P1 <37>

checked CRB

E

DGPU

GLAN

NGFF WL+BT(KEY E)

M2 SSD

CLK_CN V_PRX_DTX_ N <37>
CLK_CN V_PRX_DTX_ P <3 7>

CLK_CN V_PTX_DRX_ N <37>
CLK_CN V_PTX_DRX_ P <3 7>

o f

16 67Thursday, Febru ary 22, 2018

16 67Thursday, Febru ary 22, 2018

16 67Thursday, Febru ary 22, 2018

1.0

1.0

1.0

1

3

A

UH1E

no follow naming

can remove if no use DP
08/18

remove PCH DP SCLK/SDATA

DDP[B..F]CTRLDATA
This signal has a weak internal Pul l-down.
0 = Port B~D is not detected.
1 = Port B,C,D is detected. (Defau lt)
Notes:

1. The internal Pull-down is disabl ed after
PCH_PWROK de-asserts.

2. This signal is in the primary we ll.

* wait confirm CG7
PDG P348 quad mode support PH1K

+3VALW _SPI

+3VALW _PCH_PR IM

1 1

CRB PU 20k
#571182_CF L_PCH_EDS_ Rev1.0 re commend 100k

#571391_CFL_H_PDG_Rev0p71

RH25 1K_04 02_5%

RH26 1K_04 02_5%

RH27 1K_04 02_5%

RH29 100K_ 0402_5%

#571182_CNL_PCH_H_EDS_V1_Rev0.7
External pull-up is required. Recom mend 100K if pulled
up to 3.3V or 75K if pulled up to 1 .8V.
571007_CFL_MOW_Archive_WW22_2017
STUFF R on GPP_H15

PCH_SP I_CLK

1

2

12

12

12

RH195 100K_ 0201_5%

PCH_SP I_IO2

PCH_SP I_IO3

PCH_SP I_SI

GPP_H1 5

1

2

@

STRAP

HDMI_HPD _PCH<25 ,34>

EDP_HP D<25,33>

EC_PME #<36,39>

RH24 0_ 0402_5%

CRB connect GND

1 2

@

1 2

RH186 0_040 2_5%@

TH6 TP@

HDMI_HPD _PCH

EDP_HP D

EC_PME #_R

PCH_SP I_SI
PCH_SP I_SO
PCH_SP I_CS#0
PCH_SP I_CLK

PCH_SP I_IO2
PCH_SP I_IO3

AT6

GPP_I0/DDPB_HPD0/DISP_MISC0

AN10

GPP_I1/DDPC_HPD1/DISP_MISC1

AP9

GPP_I2/DDPD_HPD2/DISP_MISC2

AL15

GPP_I3/DDPF_HPD3/DISP_MISC3

AN6

GPP_I4/EDP_HPD/DISP_MISC4

CNP-H_B GA874

UH1A

BE36

GPP_A11/PME#/SD_VDD2_PWR_EN#

R15

RSVD2

R13

RSVD1

AL37

VSS

AN35

TP

AU41

SPI0_MOSI

BA45

SPI0_MISO

AY47

SPI0_CS0#

AW47

SPI0_CLK

AW48

SPI0_CS1#

AY48

SPI0_IO2

BA46

SPI0_IO3

AT40

SPI0_CS2#

BE19

GPP_D1/SPI1_CLK/SBK1_BK1

BF19

GPP_D0/SPI1_CS#/SBK0_BK0

BF18

GPP_D3/SPI1_MOSI/SBK3_BK3

BE18

GPP_D2/SPI1_MISO/SBK2_BK2

BC17

GPP_D22/SPI1_IO3

BD17

GPP_D21/SPI1_IO2

CNP-H_B GA874

CNP-H

5 OF 13

CNP-H

GPP_K15/GSXSRESET#

GPP_H18/SML4ALERT#

GPP_H15/SML3ALERT#

GPP_H12/SML2ALERT#

1 OF 13

GPP_I5/DDPB_CTRLCLK

GPP_I6/DDPB_CTRLDATA

GPP_I7/DDPC_CTRLCLK

GPP_I8/DDPC_CTRLDATA

GPP_I9/DDPD_CTRLCLK

GPP_I10/DDPD_CTRLDATA

GPP_F23/DDPF_CTRLDATA

GPP_F22/DDPF_CTRLCLK

GPP_F14/PS_ON#

GPP_K23/IMGCLKOUT1
GPP_K22/IMGCLKOUT0

GPP_H23/TIME_SYNC0

GPP_B13/PLTRST#

GPP_K16/GSXCLK

GPP_K12/GSXDOUT

GPP_K13/GSXSLOAD

GPP_K14/GSXDIN

GPP_E3/CPU_GP0
GPP_E7/CPU_GP1
GPP_B3/CPU_GP2
GPP_B4/CPU_GP3

GPP_H17/SML4DATA

GPP_H16/SML4CLK

GPP_H14/SML3DATA

GPP_H13/SML3CLK

GPP_H11/SML2DATA

GPP_H10/SML2CLK

INTRUDER#

Rev1.0

GPP_K21
GPP_K20

AL13
AR8
AN13
AL10
AL9
AR3
AN40
AT49

AP41

M45
L48
T45
T46
AJ47

Rev1.0

AV29

Y47
Y46
Y48
W46
AA45

AL47
AM45
BF32
BC33

AE44
AJ46
AE43
AC47
AD48
AF47
AB47
AD47
AE48

BB44

remove CIO_PLUG_EVENT#

PLT_RS T#

TP_INT#

TYPEC_1P 5A

GPP_H1 5

GPP_H1 2

SM_INTRU DER#

RVP: 330K
A 1 M pull-up is used on the custom er reference
board (CRB). This is needed to redu ce leakage
from Coin Cell Battery in G3 state.

PLT_RS T# <25,39 ,45>

GPIO Serial Expander (GSX) is the c apability
provided by the PCH to expand the G PIOs
on a platform that needs more GPIOs than the
ones provided by the PCH.

12

DH1
RB751V -40_SOD323-2

GPP_H1 2 < 20>

EC_TP_INT# <3 9,45>

TYPEC_1P 5A <4 0>

+RTCVC C

12

RH301M_0402_5 %

intel critical net recommend

1

RH198 100K_ 0201_5%

PLT_RS T#

1 2

CH9 100P_0 402_50V8J

XEMC@

TP_INT#

RH28 100K_ 0402_5%

2

+3VS

12

intel critical net recommend

SPI ROM ( 16MByte )

PCH_SP I_CS#0

PCH_SP I_IO2_0_R

UH2

1

/CS

2

DO(IO1)

3

/WP(IO2)

4

GND

W25 Q128FVSIQ_SO 8

P/N: SA00005VV20

PCH_SP I_CLK_0_R

@

1 2

RH33
0_0402 _5%

note : 1050 Use 8M rom

VCC

/HOLD(IO3)

CLK

DI(IO0)

+3VALW _SPI

CH10 0.1U_0201 _10V6K

8

PCH_SP I_IO3_0_RPCH_SP I_SO_0_R

7

PCH_SP I_CLK_0_R

6

PCH_SP I_SI_0_R

5

@

1 2

CH12
68P_04 02_50V8J

2

1

PCH_SP I_SI_0_R
PCH_SP I_SO_0_R

PCH_SP I_IO3_0_R
PCH_SP I_CLK_0_R

PCH_SP I_IO2_0_R

sch checklist 0.7
1 device 15 ohm / 2 device 33 ohm

PCH_SP I_CS#0

RH107 49.9_ 0402_1%
RH108 49.9_ 0402_1%
RH109 49.9_ 0402_1%
RH110 49.9_ 0402_1%
RH111 49.9_ 0402_1%

1

RH31 4.7 K_0402_5%

1 2
1 2
1
1 2
1

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

+3VALW _SPI

2

@

PCH_SP I_SI
PCH_SP I_SO

2

2

PCH_SP I_IO3
PCH_SP I_CLK

PCH_SP I_IO2

Compal Secret Data

Compal Secret Data

2017/12 /18 2018/09 /01

2017/12 /18 2018/09 /01

2017/12 /18 2018/09 /01

A

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

PCH PLTRST Buffer

PLT_RS T#

1 2

RH32 0_040 2_5%@

+3VS

1

B

2

A

1

2

CH11

0.1U_04 02_10V6K

5

UH3

P

4

Y

G

TC7SH0 8FU_SSOP5

3

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

PCH(3/8)DDC/SPI

PCH(3/8)DDC/SPI

PCH(3/8)DDC/SPI

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

Dat e: Sheet

Dat e: Sheet o f

Dat e: Sheet

PLT_RS T_BUF# <3 5,36,37>

1.0

1.0

1.0

17 67Thursday, Febru ary 22, 2018

17 67Thursday, Febru ary 22, 2018

o f

17 67Thursday, Febru ary 22, 2018

o f

A

USB3 MB

1

USB3 Type C

USB3 SUB

USB3 Type C

USB3 SUB

B

UH1F

USB3_P TX_DRX_N1<42>
USB3_P TX_DRX_P1<42>
USB3_P RX_DTX_N1<42>
USB3_P RX_DTX_P1<42>

USB3_P TX_DRX_N2<41>
USB3_P TX_DRX_P2<41>
USB3_P RX_DTX_N2<41>

USB3_P RX_DTX_P2<41>

USB3_P TX_DRX_N5<44>
USB3_P TX_DRX_P5<44>
USB3_P RX_DTX_N5<44>
USB3_P RX_DTX_P5<44>

USB3_P TX_DRX_P3<41>
USB3_P TX_DRX_N3<41>
USB3_P RX_DTX_P3<41>
USB3_P RX_DTX_N3<41>

USB3_P TX_DRX_P4<44>
USB3_P TX_DRX_N4<44>
USB3_P RX_DTX_P4<44>
USB3_P RX_DTX_N4<44>

F9

F7
D11
C11

C3
D4
B9
C9

C17
C16
G14

F14

C15

B15

J13

K13

G12

F11

C10

B10

C14

B14

J15

K16

CNP-H_B GA874

USB31_1_TXN
USB31_1_TXP
USB31_1_RXN
USB31_1_RXP

USB31_2_TXN
USB31_2_TXP
USB31_2_RXN
USB31_2_RXP

USB31_6_TXN
USB31_6_TXP
USB31_6_RXN
USB31_6_RXP
USB31_5_TXN
USB31_5_TXP
USB31_5_RXN
USB31_5_RXP

USB31_3_TXP
USB31_3_TXN
USB31_3_RXP
USB31_3_RXN

USB31_4_TXP
USB31_4_TXN
USB31_4_RXP
USB31_4_RXN

1.8V
(eSPI)

GPP_A7/PIRQA#/ESPI_ALERT0#

GPP_A14/SUS_STAT#/ESPI_RESET#

GPP_A9/CLKOUT_LPC0/ESPI_CLK

C

CNP-H

GPP_A1/LAD0/ESPI_IO0
GPP_A2/LAD1/ESPI_IO1
GPP_A3/LAD2/ESPI_IO2
GPP_A4/LAD3/ESPI_IO3

GPP_A5/LFRAME#/ESPI_CS0#

GPP_A6/SERIRQ/ESPI_CS1#

GPP_A0/RCIN#/ESPI_ALERT1#

GPP_A10/CLKOUT_LPC1

GPP_K19/SMI#
GPP_K18/NMI#

GPP_E6/SATA_DEVSLP2
GPP_E5/SATA_DEVSLP1
GPP_E4/SATA_DEVSLP0
GPP_F9/SATA_DEVSLP7
GPP_F8/SATA_DEVSLP6
GPP_F7/SATA_DEVSLP5
GPP_F6/SATA_DEVSLP4
GPP_F5/SATA_DEVSLP3

6 OF 13

Rev1.0

BB39
AW37
AV37
BA38

BE38
AW35
BA36
BE39
BF38

BB36
BB34

T48
T47

AH40
AH35
AL48
AP47
AN37
AN46
AR47
AP48

#571391_CFL_H_PDG_Rev0p5

eSPI clock and eSPI data mismatched: <500 mils.



eSPI clock and eSPI chip select mismatched: <500 mils.



eSPI signal maximum 9 Vias



* If DATA signals are entirely rout ed on MS, stuff the resistor with 15 Oh m.

LPC_AD 0

LPC_AD 1

LPC_AD 2
LPC_AD 3

LPC_FR AME#
TPM_SE RIRQ
LPC_PIRQ A#

ESPI_RST #

CLK_LP C
CLK_LP C_TPM

SSD_DE VSLP1

RH35 22_04 02_5%
RH36 22_04 02_5%

D

LPC_AD 0 <39,45 >
LPC_AD 1 <39,45 >
LPC_AD 2 <39,45 >
LPC_AD 3 <39,45 >

LPC_FR AME# <3 9,45>
TPM_SE RIRQ <39,4 5>

12

12

TPM@

SSD_DE VSLP1 < 35>

LPC Bus

LPC : +3.3V

ESPI_RST # <39>

CLK_LP C_R < 39>
CLK_LP C_TPM_R < 45>

1A modify

E

check straps

1

+3VS

2 2

For Intel CLINK

TH10 TP@
TH11 TP@
TH12 TP@

CL_CLK
CL_DAT A
CL_RST #

1A modify

PCIE_PTX _DRX_P11<35>

M.2 SSD PCIE L1

3

GLAN

PCIE_PTX _C_DRX_N14< 36>

PCIE_PTX _C_DRX_P14<36>

PCIE_PRX_DTX_N1 4<36>
PCIE_PRX_DTX_P1 4<36>

CH3 .1U_040 2_16V7K
CH4 .1U_040 2_16V7K

M.2 SSD PCIE L0

PCIE_PTX _DRX_N11<35>
PCIE_PRX _DTX_P11<35>
PCIE_PRX _DTX_N11<35>

DGPU_P RSNT#

12
12

PCIE_PTX _DRX_P12<35>
PCIE_PTX _DRX_N12<35>
PCIE_PRX _DTX_P12<35>
PCIE_PRX _DTX_N12<35>

PCIE_PTX _DRX_N14
PCIE_PTX _DRX_P14

PCIE_PRX _DTX_N14
PCIE_PRX _DTX_P14

1A modify

+3VALW _PCH_PR IM

1

RH43

10K_04 02_5%

4 4

UMA@

2

DGPU_P RSNT#

UH1C

AR2

CL_CLK

AT5

CL_DATA

AU4

CL_RST#

P48

GPP_K8

V47

GPP_K9

V48

GPP_K10

W47

GPP_K11

L47

GPP_K0

L46

GPP_K1

U48

GPP_K2

U47

GPP_K3

N48

GPP_K4

N47

GPP_K5

P47

GPP_K6

R46

GPP_K7

C36

PCIE11_TXP/SATA0A_TXP

B36

PCIE11_TXN/SATA0A_TXN

F39

PCIE11_RXP/SATA0A_RXP

G38

PCIE11_RXN/SATA0A_RXN

AR42

GPP_F10/SATA_SCLOCK

AR48

GPP_F11/SATA_SLOAD

AU47

GPP_F13/SATA_SDATAOUT0

AU46

GPP_F12/SATA_SDATAOUT1

C39

PCIE14_TXN/SATA1B_TXN

D39

PCIE14_TXP/SATA1B_TXP

D46

PCIE14_RXN/SATA1B_RXN

C47

PCIE14_RXP/SATA1B_RXP

B38

PCIE13_TXN/SATA0B_TXN

C38

PCIE13_TXP/SATA0B_TXP

C45

PCIE13_RXN/SATA0B_RXN

C46

PCIE13_RXP/SATA0B_RXP

E37

PCIE12_TXP/SATA1A_TXP

D38

PCIE12_TXN/SATA1A_TXN

J41

PCIE12_RXP/SATA_1A_RXP

H42

PCIE12_RXN/SATA1A_RXN

B44

PCIE20_TXP/SATA7_TXP

A44

PCIE20_TXN/SATA7_TXN

R37

PCIE20_RXP/SATA7_RXP

R35

PCIE20_RXN/SATA7_RXN

D43

PCIE19_TXP/SATA6_TXP

C44

PCIE19_TXN/SATA6_TXN

N42

PCIE19_RXP/SATA6_RXP

M44

PCIE19_RXN/SATA6_RXN

CNP-H_B GA874

CNP-H

PCIE9_RXN
PCIE9_RXP
PCIE9_TXN

PCIE9_TXP

PCIE10_RXN
PCIE10_RXP

PCIE10_TXN
PCIE10_TXP

PCIE15_RXN/SATA2_RXN

PCIE15_RXP/SATA2_RXP

PCIE_15_SATA_2_TXN

PCIE15_TXP/SATA2_TXP

PCIE16_RXN/SATA3_RXN

PCIE16_RXP/SATA3_RXP
PCIE16_TXN/SATA3_TXN

PCIE16_TXP/SATA3_TXP

PCIE17_RXN/SATA4_RXN

PCIE17_RXP/SATA4_RXP
PCIE17_TXN/SATA4_TXN

PCIE17_TXP/SATA4_TXP

PCIE18_RXN/SATA5_RXN

PCIE18_RXP/SATA5_RXP
PCIE18_TXN/SATA5_TXN

PCIE18_TXP/SATA5_TXP

GPP_E8/SATA_LED#

GPP_E0/SATAXPCIE0/SATAGP0
GPP_E1/SATAXPCIE1/SATAGP1
GPP_E2/SATAXPCIE2/SATAGP2

GPP_F0/SATAXPCIE3/SATAGP_3

GPP_F1/SATAXPCIE4/SATAGP4
GPP_F2/SATAXPCIE5/SATAGP5
GPP_F3/SATAXPCIE6/SATAGP6
GPP_F4/SATAXPCIE7/SATAGP7

GPP_F21/EDP_BKLTCTL

GPP_F20/EDP_BKLTEN

GPP_F19/EDP_VDDEN

THRMTRIP#

PECI

PM_SYNC

3 OF 13

PLTRST_CPU#

PM_DOWN

Rev1.0

G36
F36
C34
D34

K37
J37
C35
B35

F44
E45
B40
C40

L41
M40
B41
C41

K43
K44
A42
B42

P41
R40
C42
D42

AK48

AH41
AJ43
AK47
AN47

RH187 10K_0402 _5%PBA @

AM46
AM43
AM47
AM48

AU48
AV46
AV44

AD3
AF2
AF3
AG5
AE2

PCIE_PRX _DTX_N9
PCIE_PRX _DTX_P9
PCIE_PTX _DRX_N9
PCIE_PTX _DRX_P9

PCIE_PRX _DTX_N10

PCIE_PRX _DTX_P10
PCIE_PTX _DRX_N10
PCIE_PTX _DRX_P10

PCIE_PRX _DTX_N15
PCIE_PRX _DTX_P15
PCIE_PTX _DRX_N15
PCIE_PTX _DRX_P15

SATA_P RX_DTX_N4
SATA_P RX_DTX_P4
SATA_P TX_DRX_N4
SATA_P TX_DRX_P4

1A modify

1

SATA_G P5

PCH_BK L_PWM
ENBKL

PCH_EN VDD

PCH_TH ERMTRIP#
PCH_PE CI

H_PM_S YNC
H_PLTR ST_CPU#
H_PM_D OWN_R

1A modify

1 2
1

SATA_P RX_DTX_N4 < 43>

SATA_P RX_DTX_P4 <43 >
SATA_P TX_DRX_N4 < 43>

SATA_P TX_DRX_P4 <43 >

1A modify

2

TH13T P@

1 2

RH40 620_0 402_5%

RH41 13_04 02_5%

RH42 30_04 02_5%

1

@

1 2

2

PCIE_PRX _DTX_N9 < 35>
PCIE_PRX _DTX_P9 <35>
PCIE_PTX _DRX_N9 < 35>

PCIE_PTX _DRX_P9 <35 >

PCIE_PRX _DTX_N10 <35>
PCIE_PRX _DTX_P10 <35 >
PCIE_PTX _DRX_N10 <35>

PCIE_PTX _DRX_P10 <3 5>

PCIE_PRX_DTX_N1 5 <37>

CH1.1 U_0402_16V 7K

2

CH2.1 U_0402_16V 7K

SATA_G P1 <35>

PCH_BK L_PWM <25,33>
ENBKL <25,39>

PCH_EN VDD <25,33 >

PCIE_PRX_DTX_P1 5 <37>
PCIE_PTX _C_DRX_N15 <37>

PCIE_PTX _C_DRX_P15 <37>

#571391_CFL_H_PDG_Rev0p5.pdf

H_PECI
H_PM_S YNC_R

M.2 SSD PCIE L3

M.2 SSD PCIE L2

HDD

PCH_TH ERMTRIP#_R <11>
H_PECI <11,3 9>
H_PM_S YNC_R <11 >
H_PLTR ST_CPU# <11>
H_PM_D OWN_R <11>

TPM_SE RIRQ

LPC_PIRQ A#

NGFF
WL+BT(KEY E)

SATA_G P1

2

RH39 10K_0 402_5%

M.2 SSD PCIE/SATA select pin

H_PECI

2

10K_04 02_5%

1 2

10K_04 02_5%

1

XEMC@

2

1

1

RH37

RH38

+3VS

CH500.1U_0402_ 10V6K

3

RH44

10K_04 02_5%

1

VGA@

2

DIS,Optimus10

UMA

A

GPP_F1 3

DGPU_PRSNT#

Security Classification

Security Classification

Security Classification

2017/12 /18 2018/09 /01

2017/12 /18 2018/09 /01

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

B

2017/12 /18 2018/09 /01

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

PCIE/SATA/USB3/eSPI

PCIE/SATA/USB3/eSPI

PCIE/SATA/USB3/eSPI

Size Document Number R ev

Size Document Number R ev

Size Document Number R ev

Custom

Custom

Custom

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

Dat e: Sheet o f

Dat e: Sheet o f

D

Dat e: Sheet o f

18 67Thursday, Febru ary 22, 2018

18 67Thursday, Febru ary 22, 2018

18 67Thursday, Febru ary 22, 2018

E

1.0

1.0

1.0

A

1 2

ME_EN<39>

HDA_RS T#_R<38>
HDA_BIT_ CLK_R< 38>
HDA_SD OUT_R<38>
HDA_SYNC _R<38>

1

RPH7

1 8
2 7
3 6
4 5

33_080 4_8P4R_5%

@

RH45 0_ 0402_5%

HDA_RS T#

HDA_BIT_ CLK
HDA_SD OUT
HDA_SYNC

HDA_BIT_ CLK

12

RH196100K_ 0201_5%

HDA_RS T#

12

RH197100K_ 0201_5%

intel critical net recommend

del RF reserve cap on HDA

CPU_DISP A_SDO_R< 7>

CPU_DISP A_SDI_R<7>

FOR Jefferson Peak RESET pin is glitch free,it
is recommended that a pull-down resistor of 75K
ohm on GPP_D5(CNV_RF_RESET#)

+RTCVC C

1 2

RH50 20K_0 402_1%

1 2

2 2

3

+3VS

+3VALW _PCH_PR IM

4 4

CH18 1U_04 02_6.3V6K

1

RH52 20K_0 402_1%

1

CH19 1U_04 02_6.3V6K

1 2

JCMOS1 0_0603 _5%@

+3VALW _DSW

2

RH55 1K_04 02_5%

2

RH56 8.2K_0 402_5%

RH57 100K_ 0402_5%@

RH58 100K_ 0402_5%@

2

RH60 8.2K_0 402_5%

RH191 2.2K_ 0402_5%
RH192 2.2K_ 0402_5%

RPH11

5

2.2K_08 04_8P4R_5%

1

RH63 499_04 02_1%

1 2

RH64 499_04 02_1%

1

1

12

12

2

A

2

2

1

12
12

PCH_SM BCLK

18

PCH_SM BDATA

27

PCH_SM L1CLK

36

PCH_SM L1DATA

4

PCH_SM L0CLK

PCH_SM L0DATA

CPU_DISP A_BCLK_R<7>

PCH_SR TCRST#

CLR ME
Delay 18~25 ms

PCH_RT CRST#

ECLR CMOS
Delay 18~25 ms

WAK E#

PM_BAT LOW#

AC_PRE SENT_R

PBTN_O UT#_R

PM_CLK RUN#

D_CK_S CLK
D_CK_S DATA

2N7002 KDW_SOT 363-6

PCH_SM BCLK

HDA_SD IN0<38>

RH48

1 2

RH49

1 2

CLKREQ _CNV#<3 7>

CNV_RF _RESET#< 37>
PCH_DM IC_DATA0<38>
PCH_DM IC_CLK0<38>

TH22 TP@

TH24 TP@

PCH_RT CRST#<39>

PCH_PW ROK<39,47>
EC_RSM RST#<39>

PCH_SM BALERT#<20>

PCH_SM L0ALERT#<20>

PCH_SM L1ALERT#<20>

QH7B

2N7002 KDW_SOT 363-6

PCH_SM L1CLK

PCH_SM L1DATA

B

30_040 2_5%

30_040 2_5%

+3VS

5

G

3

4

S

D

QH7A

6 1

1

RH189 0_0 402_5%

1 2

RH190 0_0 402_5%

B

2

G

D

2

@

@

HDA_BIT_ CLK
HDA_SD IN0
HDA_SD OUT
HDA_SYNC

HDA_RS T#

CPU_DISP A_SDO
CPU_DISP A_SDI_R
CPU_DISP A_BCLK

CLKREQ _CNV#
CNV_RF _RESET#

PCH_RT CRST#

PCH_SR TCRST#

PCH_PW ROK
EC_RSM RST#

PCH_DP WROK

PCH_SM BALERT#
PCH_SM BCLK
PCH_SM BDATA

PCH_SM L0ALERT#
PCH_SM L0CLK
PCH_SM L0DATA
PCH_SM L1ALERT#
PCH_SM L1CLK
PCH_SM L1DATA

D_CK_S CLK

D_CK_S DATAPC H_SMBDATA

S

Security Classification

Security Classification

Security Classification

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

UH1D

BD11

HDA_BCLK/I2S0_SCLK

BE11

HDA_SDI0/I2S0_RXD

BF12

HDA_SDO/I2S0_TXD

BG13

HDA_SYNC/I2S0_SFRM

BE10

HDA_RST#/I2S1_SCLK

BF10

HDA_SDI1/I2S1_RXD

BE12

I2S1_TXD/SNDW2_DATA

BD12

I2S1_SFRM/SNDW2_CLK

AM2

HDACPU_SDO

AN3

HDACPU_SDI

AM3

HDACPU_SCLK

AV18

GPP_D8/I2S2_SCLK

AW18

GPP_D7/I2S2_RXD

BA17

GPP_D6/I2S2_TXD/MODEM_CLKREQ

BE16

GPP_D5/I2S2_SFRM/CNV_RF_RESET#

BF15

GPP_D20/DMIC_DATA0/SNDW4_DATA

BD16

GPP_D19/DMIC_CLK0/SNDW4_CLK

AV16

GPP_D18/DMIC_DATA1/SNDW3_DATA

AW15

GPP_D17/DMIC_CLK1/SNDW3_CLK

BE47

RTCRST#

BD46

SRTCRST#

AY42

PCH_PWROK

BA47

RSMRST#

AW41

DSW_PWROK

BE25

GPP_C2/SMBALERT#

BE26

GPP_C0/SMBCLK

BF26

GPP_C1/SMBDATA

BF24

GPP_C5/SML0ALERT#

BF25

GPP_C3/SML0CLK

BE24

GPP_C4/SML0DATA

BD33

GPP_B23/SML1ALERT#/PCHHOT#

BF27

GPP_C6/SML1CLK

BE27

GPP_C7/SML1DATA

CNP-H_B GA874

(DDR,G -Se nsor )

D_CK_S CLK < 23,24,43>

D_CK_S DATA <2 3,24,43>

EC_SMB _CK2 <25,3 9,40,44>

(EC, VGA)

EC_SMB _DA2 <25,3 9,40,44>

Issued Date

Issued Date

Issued Date

C

CNP-H

GPP_A12/BM_BUSY#/ISH_GP6/SX_EXIT_HOLDOFF#

GPP_B1/GSPI1_CS1#/TIME_SYNC1

1.8V

GPP_A13/SUSWARN#/SUSPWRDNACK

4 OF 13

Compal Secret Data

Compal Secret Data

2017/12 /18 2018/09 /01

2017/12 /18 2018/09 /01

2017/12 /18 2018/09 /01

C

Compal Secret Data

GPP_A8/CLKRUN#

GPD11/LANPHYPC

GPD9/SLP_WLAN#

DRAM_RESET#

GPP_B2/VRALERT#

GPP_B0/GSPI0_CS1#

GPP_K17/ADR_COMPLETE

GPP_B11/I2S_MCLK

GPD6/SLP_A#

GPP_B12/SLP_S0#

GPD4/SLP_S3#
GPD5/SLP_S4#

GPD10/SLP_S5#

GPD8/SUSCLK

GPD0/BATLOW#

GPP_A15/SUSACK#

GPD2/LAN_WAKE#
GPD1/ACPRESENT

GPD3/PWRBTN#

GPP_B14/SPKR

PCH_JTAG_TMS
PCH_JTAG_TDO

PCH_JTAG_TDI

PCH_JTAG_TCK

+3VALW _DSW

+3VALW _PCH_PR IM

POP on 1A version

0.1U_04 02_10V6K

Deciphered Date

Deciphered Date

Deciphered Date

SYS_PWROK

SYS_RESET#

CPUPWRGD

ITP_PMODE
PCH_JTAGX

RH183 10K _0402_5%

BF36
AV32

BF41

BD42

BB46

BE32
BF33

BE29

R47
AP29
AU3

BB47

WAKE#

BE40
BF40

SLP_LAN#

BC28

BF42
BE42
BC42

BE45
BF44
BE35

BC37

BG44
BG42
BD39

SLP_SUS#

BE46
AU2

AW29

AE3

AL3
AH4
AJ4
AH3
AH2

AJ3

Rev1.0

RPH8

18
2

7

36
45

10K_08 04_8P4R_5%

12

1 2

RH184100K_0 402_5% @

1 2

RH61100K_0 402_5% @

XEMC@

1

2

CH200.1U_0402_ 10V6K

XEMC@

2

1

CH21

XEMC@

2

1

CH220.1U_0402_ 10V6K

XEMC@

1 2

CH510.1U_0402_ 10V6K

From ESD Te am R equest

Near PCH side

D

DRAM_R ESET#

PM_CLK RUN#

LAN_DISA BLE_N

SLP_W LAN#

DRAM_R ESET#
PCH_VR ALERT#
TYPEC_3A
LAN_GP O

PCH_GP P_K17
PCH_GP P_B11

SYS_PW ROK

WAK E#

PM_SLP _A#
SLP_LA N#
PM_SLP _S0#
PM_SLP _S3#
PM_SLP _S4#
PM_SLP _S5#

SUSCLK
PM_BAT LOW#

SUSACK #_R

1 2

RH51 0_ 0402_5%

LAN_W AKE#
AC_PRE SENT_R
SLP_SU S#
PBTN_O UT#_R
SYS_RESE T#

PCH_SP KR

H_CPUP WRGD

XDP_ITP_ PMODE

CPU_XD P_TCK0
CPU_XD P_TMS
CPU_XD P_TDO
CPU_XD P_TDI
PCH_JT AG_TCK1

PCH_PW ROK
LAN_W AKE#
EC_RSM RST#

SYS_RESE T#

SYS_PW ROK

PCH_DP WROK

SYS_RESE T#

SYS_PW ROK

PCH_PW ROK

EC_RSM RST#

D

+1.2V_V DDQ

@

1 2

RH53 0_ 0402_5%

1 2

RH54 0_ 0402_5%

H_CPUP WRGD < 11>

EC_RSM RST#

PCH_VR ALERT#

Custom

Custom

Custom

Dat e: Sheet o f

Dat e: Sheet

Dat e: Sheet o f

E

2

RH46
470_04 02_1%

1

1 2

RH47 0_0402 _5%

1

2

CH13 1U_040 2_6.3V6K

PM_CLK RUN# <45>

TH14TP@

TH15TP@

TYPEC_3A <40>
LAN_GP O < 36>

TH19TP@

TH20TP@

SYS_PW ROK <39,47>

TH37TP@

TH21TP@

PM_SLP _S0# <39 >
PM_SLP _S3# <39 ,47>

PM_SLP _S4# <39 ,47>

TH23TP@

T207TP@

SUSPW RDNACK <39>

@

TP@

@

PCH_SP KR <2 0,38>

PBTN_O UT#

T208

T209

TP@

CPU_XD P_TCK0 <1 1>

CPU_XD P_TMS < 11>
CPU_XD P_TDO <1 1>

CPU_XD P_TDI < 11>

PCH_JT AG_TCK1 <11>

PM_SLP _S3#
PM_SLP _S4#

@

SUSCLK <35,37 >

AC_PRE SENT

--No Support Deep Sx

1 2

RH193 100K_ 0201_5%

1

RH194 100K_ 0201_5%

DDR_DR AMRST#_R <23,24>

AC_PRE SENT <3 9>

PBTN_O UT# < 39>

Connect CPU & PCH

2

intel critical net recommend

1

2

@

RH59 0_ 0402_5%

1

2

RH62 10K_0 402_5%@

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

PCH(5/8)PMU/HDA/SMBUS/DMIC

PCH(5/8)PMU/HDA/SMBUS/DMIC

PCH(5/8)PMU/HDA/SMBUS/DMIC

Size Document Number R ev

Size Document Number R ev

Size Document Number R ev

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

PCH_DP WROK

+3VALW _PCH_PR IM

E

o f

19 67Thursday, Febru ary 22, 2018

19 67Thursday, Febru ary 22, 2018

19 67Thursday, Febru ary 22, 2018

1.0

1.0

1.0

1

3

+3VALW _PCH_PR IM

Vinafix

1 8
2 7
3
4

+3VS

RH66 10K_04 02_5%@

1

2 2

3

4 4

RH68 49.9K_0 402_1%

RH69 49.9K_0 402_1%

RH70 49.9K_0 402_1%@

RH71 49.9K_0 402_1%@

RH72 10K_04 02_5%VGA@

RH73 10K_04 02_5%VGA@

+3VALW _PCH_PR IM

1 2

RH74 4.7K_0 402_5%@

This signal has a weak internal pul l-down.
0 = Master Attached Flash Sharing ( MAFS) enabled (Default)
1 = Slave Attached Flash Sharing (S AFS) enabled.
Notes:

1. This signal is in the primary we ll.

Warning: This strap must be configured to ‘ 0’ if the
eSPI or LPC strap is configured to ‘ 0’

+3VALW _PCH_PR IM

+3VS

A

RPH12

2.2K_08 04_8P4R_5%

1 2

1

RH112 4.7K_0 402_5%@

RH113 4.7K_0 402_5%@

RH114 150K _0402_1%

*

RH77 4.7K_0 402_5%@

The signal has a weak internal Pull -down.

0 = Disable “ No Reboot” mode. (Default)
1 = Enable “ No Reboot” mod e (PCH wil l disable th e
TCO Timer system reboot feature). This function is
useful when running ITP/XDP.
Notes:

1. The internal Pull-down is disabled after
PCH_PWROK is high.

2. This signal is in the primary well.

RH80 150K_ 0402_1%

This Signal has a weak internal Pul l-down.
0: SPI (Default)
1: LPC
Notes:

1. The internal Pull-down is disabl ed after PCH_PWROK is high.

2. This signal is in the primary we ll.

RH83 100K_ 0402_5%@

Top Swap Override

0 = Disable “ Top Swap” mode. (Default)
1 = Enable “ Top Swap” mode.
The internal Pull-down is disabled after PCH_PWROK is high.

I2C_1_SC L
I2C_1_SD A

I2C_0_SC L

6

I2C_0_SD A

5

12

12

12

12

12

2

1 2

SMBALERT# / GPP_C2 has a weak int ernal Pull-down.
0 = Disable Intel ME (TLS) (D efault)
1 = Enable Intel ME (TLS)

1

2

SML0ALERT# / GPP_C5 has a weak in ternal Pull-down.
0 = LPC is selected (for EC 9022).
1 = eSPI is selected

1 2

SML1ALERT# / GPP_B23 has an inter nal pull-down.
0 = Disable IntelR DCI-OOB (Default )
1 = Enable IntelR DCI-OOB

1

2

@

1 2

12

EC_SCI# GC6_FB _EN3V3 GC6_FB _EN

UART_2 _PRXD_DTXD

UART_2 _PTXD_DRXD

UART_2 _PRTS_DCTS

UART_2 _PCTS_DRTS

DGPU_P WR_EN

DGPU_H OLD_RST#

GPP_H1 2

GSPI0_MO SI

check needed?

CG11 connect to GPP_B15

GPP_H1 2 <1 7>

PCH_SM BALERT# <19>

PCH_SM L0ALERT# <19>

PCH_SM L1ALERT# <19>

GSPI1_MO SI

PCH_SP KR

GC6_FB _EN3V3<25>

STRAP

STRAP

STRAP

PCH_SP KR <1 9,38>

STRAP

B

<Touch PAD>

STRAP

GSPI1_MO SI

1 2

EC_SCI#

GSPI0_MO SI

EC_SCI#<39>

RH67 0_0402 _5%@

TS_EN<33,39>

check for remove (PCH or Both)

DGPU_A C_DETECT<39,50>

GPU_EVENT#<25>

DGPU_H OLD_RST#<25>

DGPU_P WR_EN<25,29>

UART_2 _PTXD_DRXD<37>

UART_2 _PRXD_DTXD<37>

I2C_1_SC L<4 5>

I2C_1_SD A<45>

pop for avoid floating

1.0 Modify

Reserved
Reserved
for 8 Layer

※

no t e : 00 /01 us ed f or 1050

EVT

10 used for 1060 EVT

TS_EN

DGPU_A C_DETECT

GPU_EV ENT#

DGPU_H OLD_RST#
DGPU_P WR_EN

UART_2 _PCTS_DRTS
UART_2 _PRTS_DCTS

UART_2 _PTXD_DRXD
UART_2 _PRXD_DTXD

I2C_1_SC L
I2C_1_SD A

I2C_0_SC L
I2C_0_SD A

VGA_ID1

VGA_ID2

C

UH1K

BA26

GPP_B22/GSPI1_MOSI

BD30

GPP_B21/GSPI1_MISO

AU26

GPP_B20/GSPI1_CLK

AW26

GPP_B19/GSPI1_CS0#

BE30

GPP_B18/GSPI0_MOSI

BD29

GPP_B17/GSPI0_MISO

BF29

GPP_B16/GSPI0_CLK

BB26

GPP_B15/GSPI0_CS0#

BB24

GPP_C9/UART0A_TXD

BE23

GPP_C8/UART0A_RXD

AP24

GPP_C11/UART0A_CTS#

BA24

GPP_C10/UART0A_RTS#

BD21

GPP_C15/UART1_CTS#/ISH_UART1_CTS#

AW24

GPP_C14/UART1_RTS#/ISH_UART1_RTS#

AP21

GPP_C13/UART1_TXD/ISH_UART1_TXD

AU24

GPP_C12/UART1_RXD/ISH_UART1_RXD

AV21

GPP_C23/UART2_CTS#

AW21

GPP_C22/UART2_RTS#

BE20

GPP_C21/UART2_TXD

BD20

GPP_C20/UART2_RXD

BE21

GPP_C19/I2C1_SCL

BF21

GPP_C18/I2C1_SDA

BC22

GPP_C17/I2C0_SCL

BF23

GPP_C16/I2C0_SDA

BE15

GPP_D4/ISH_I2C2_SDA/I2C3_SDA/SBK4_BK4

BE14

GPP_D23/ISH_I2C2_SCL/I2C3_SCL

CNP-H_B GA874

+1.8VAL W_PRIM

1 2

RH84 1K_040 2_5%@

1 2

RH85 10K_04 02_5%

1

RH86 1K_040 2_5%@

RH87 10K_04 02_5%

2

1 2

GPP_D10 GPP_D9

0

CNP-H

GPP_D9/ISH_SPI_CS#/GSPI2_CS0#

GPP_D11/ISH_SPI_MISO/GP_BSSB_CLK/GSPI2_MISO

GPP_D12/ISH_SPI_MOSI/GP_BSSB_DI/GSPI2_MOSI

GPP_D15/ISH_UART0_RTS#/GSPI2_CS1#/CNV_WFEN

GPP_D10/ISH_SPI_CLK/GSPI2_CLK

GPP_D16/ISH_UART0_CTS#/CNV_WCEN

GPP_D14/ISH_UART0_TXD/I2C2_SCL

GPP_D13/ISH_UART0_RXD/I2C2_SDA

GPP_A17/SD_VDD1_PWR_EN#/ISH_GP7

11 OF 13

PROJEC T_ID0

PROJEC T_ID1

Project ID

00
1
01
11

DH53F(1060 WO RD)Reserved
DH53F(1060 W RD)

*

DH5VF(1050 WO RD)

*

DH5VF(1050 W RD)

SCI capability is available on all GPIOs
PCH GPIOs that can be routed to gen erate SMI# or NMI:

GPP_B14, GPP_B20, GPP_B23



GPP_C[23:22]



GPP_D[4:0]



GPP_E[8:0]



GPP_I[3:0]



GPP_G[7:0] (support SMI# only).



The voltage of all GPIO pads in eac h GPP group is determined by the voltag e supplied to the group (either 3.3V o r 1.8V),
except for GPP_I and GPD group, (wh ich are 3.3V only), and GPP_J group (wh ich is 1.8V only).

All GPIOs have programmable interna l pull-up/pull-down resistors which are off by default.
The internal pull-up/pull-down for each GPIO can be enabled by BIOS progra mming.

D

GPP_H20/ISH_I2C0_SCL
GPP_H19/ISH_I2C0_SDA

GPP_H22/ISH_I2C1_SCL
GPP_H21/ISH_I2C1_SDA

GPP_A23/ISH_GP5
GPP_A22/ISH_GP4
GPP_A21/ISH_GP3
GPP_A20/ISH_GP2
GPP_A19/ISH_GP1
GPP_A18/ISH_GP0

Rev1.0

1 2

RH88 1K_040 2_5%

SATARD @

1

RH89 10K_04 02_5%S ATANRD@

1 2

RH90 1K_040 2_5%

1

RH91 10K_04 02_5%@

0 0
0
1
1 1

BA20
BB20
BB16
AN18

BF14
AR18
BF17
BE17

AG45
AH46

AH47
AH48

AV34
AW32
BA33
BE34
BD34
BF35
BD38

2

2

VGA_ID1
VGA_ID2
PROJEC T_ID0
PROJEC T_ID1

SUB_DE T

G_INT
CODEC_ ID

FOR 4 DMIC @256

CODEC_ ID

CODEC_ID / GPP_A19
0 = 2 DIMC @255 (Default)
1 = 4 DIMC @256

FOR 40 PIN SUB/B

SUB_DE T

+1.8VAL W_PRIM

Project_ID0Project_ID1

GPP_D11GPP_D12

1
0

1

RH188 1K_0 402_5%256@

1 2

RH185 1K_0 402_5%@

2

+3VS

2

1

2

@

1

E

GSEN@

RH78
10K_04 02_5%

G_INT

RH79

100K_0 402_5%

+3VALW _PCH_PR IM

+1.8VAL W_PRIM

G_INT < 43>

1

3

Security Classification

Security Classification

Security Classification

2017/12 /18 2018/09 /01

2017/12 /18 2018/09 /01

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

A

B

2017/12 /18 2018/09 /01

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

PCH(6/8)GPIO/I2C/UART/STRAP

PCH(6/8)GPIO/I2C/UART/STRAP

PCH(6/8)GPIO/I2C/UART/STRAP

Size Document Number R ev

Size Document Number R ev

Size Document Number R ev

Custom

Custom

Custom

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

Dat e: Sheet o f

Dat e: Sheet o f

D

Dat e: Sheet o f

20 67Thursday, Febru ary 22, 2018

20 67Thursday, Febru ary 22, 2018

20 67Thursday, Febru ary 22, 2018

E

1.0

1.0

1.0

A

B

C

D

E

GPIO Group Vol tag e

+1.05VALW

JPH1

@

2

112

JUMP_43X79

1

JPH2

@

2

112

JUMP_43X79

+1.05VALW_ PCH_PRIM

5.95A

1U_0402_6.3V6K

1

CH23

2

+1.05VALW_ VCCMPHY

6.6A

22U_0402_6.3V6M

1

CH25

2

HSIO for DMIU/USB3.1/PCIE=4162mA

+1.05VALW_ VCCMPHY

1U_0402_6.3V6K

1

CH26

2

+1.05VALW_ PCH

3-5MM FROM PACKAGE EDGE

1

RH94

pop for intel sensitive net (1.0)

+1.05VALW_ PCH

2 2

place near VCCDUSB
FOR W22/W23

1-5MM FROM PACKAGE EDGE
FOR VCCAPLL C1/C2

3 3

+1.05VALW_ PCH

0.1U_0402_10V6K

1

2

+1.05VALW_ PCH

1U_0402_6.3V6K

1

2

CH33

1

2

2

0_0603_5 %

CH29

1-3MM FROM PACKAGE EDGE
FOR VCCA_BCLK V19

1 2

RH102 0_0 402_5%

1P_0402_50V8

CH43

@

+1.05VALW_ PCH

+1.05VALW_ PCH +1.05V_VCCD SW

0.1U_0402_10V6K

1

CH30

2

1-3MM FROM PACKAGE
VCCPRIM_MPHY W31

1-3MM FROM PACKAGE EDGE

pop for intel sensitive net (1.0)

+1.05VALW_ PCH

0.1U_0402_10V6K

1

CH34

2

1-5MM FROM PACKAGE EDGE
FOR VCCAPLL B1/B2/B3

+1.05VALW_ VCCAZPLL

1P_0402_50V8

1

CH44

2

@

1U_0402_6.3V6K

1

2

+1.05VALW_ PCH

1U_0402_6.3V6K

1

2

CH31

CH35

+1.05V_VCCD SW

+1.05VALW_ VCCAZPLL

+1.05VALW_ VCCAMPHYPLL

+1.05VALW_ XTAL

+1.05VALW_ PCH_PRIM

5.95A

6.6A

0.0012A

0.2A

0.42A

0.109A

0.015A

0.213A

0.00428A

0.169A

0.0198A

0.0085A

0.021A

+3VALW +3VALW_PC H_PRIM

RH97 0_0805_ 5%

RH99 0_0402 _5%

1P_0402_50V8

1

CH41

2

@

AA22
AA23
AB20
AB22
AB23
AB27
AB28
AB30
AD20
AD23
AD27
AD28

AD30
AF23

AF27
AF30

U26
U29
V25
V27
V28
V30
V31

AD31

AE17

W22
W23

BG45
BG46

W31

D1
E1

C49

D49
E49

P2

P3
W19
W20

C1

C2

V19

B1

B2

B3

1 2

1 2

UH1H

VCCPRIM_1P051
VCCPRIM_1P052
VCCPRIM_1P053
VCCPRIM_1P054
VCCPRIM_1P055
VCCPRIM_1P056
VCCPRIM_1P057
VCCPRIM_1P058
VCCPRIM_1P059
VCCPRIM_1P0510
VCCPRIM_1P0511
VCCPRIM_1P0512

VCCPRIM_1P0513
VCCPRIM_1P0516

VCCPRIM_1P0517
VCCPRIM_1P0518

VCCPRIM_1P0523
VCCPRIM_1P0524
VCCPRIM_1P0525
VCCPRIM_1P0526
VCCPRIM_1P0527
VCCPRIM_1P0528
VCCPRIM_1P0529

VCCPRIM_1P0514

VCCPRIM_1P0515

VCCDUSB_1P051
VCCDUSB_1P052

VCCDSW_1P051
VCCDSW_1P052

VCCPRIM_MPHY_1P05

VCCPRIM_1P0521
VCCPRIM_1P0522

VCCAMPHYPLL_1P051
VCCAMPHYPLL_1P052

VCCAMPHYPLL_1P053

VCCA_XTAL_1P051
VCCA_XTAL_1P052
VCCA_SRC_1P051
VCCA_SRC_1P052

VCCAPLL_1P054

VCCAPLL_1P055
VCCA_BCLK_1P05

VCCAPLL_1P051
VCCAPLL_1P052
VCCAPLL_1P053

CNP-H_BGA87 4

+3VALW_H DA

12

RH1010_0402_5%

CH42

@

1-3MM FROM PACKAGE EDGE

0_0402_5 %

A

+1.05VALW_ VCCAMPHYPLL

22U_0402_6.3V6M

1

1

CH45

2

2

@

+1.05VALW_ XTAL

22U_0402_6.3V6M

1

CH49

2

@

1U_0402_6.3V6K

CH46

+RTCBATT

change to 10k

RH104 10K_0402 _5%

+CHGRTC

B

12

DH2

2

3

BAV70W_SOT 323-3

+RTCVCC

1

0.1U_0402_10V6K

1U_0402_6.3V6K

1

1

CH48

CH47

2

2

1 2

RH103 0_0402_5 %

LC filter colse to pin

4

1uF 1-3MM FROM PACKAGE EDGE

1 2

RH105

CNP-H

VCCPRIM_3P32

VCCPRIM_3P35

VCCPGPPG_3P3

VCCPRIM_3P33
VCCPRIM_3P34

VCCPGPPHK1
VCCPGPPHK2
VCCPGPPEF1
VCCPGPPEF2

VCCPGPPBC1
VCCPGPPBC2

VCCPRIM_3P31
VCCDSW_3P31
VCCDSW_3P32

VCCPRIM_1P83
VCCPRIM_1P84
VCCPRIM_1P85
VCCPRIM_1P86
VCCPRIM_1P87

VCCPRIM_1P81
VCCPRIM_1P82

VCCPRIM_1P0520
VCCPRIM_1P0519

VCCPRIM_1P241
VCCPRIM_1P242

VCCDPHY_1P241
VCCDPHY_1P242
VCCDPHY_1P243

VCCMPHY_SENSE
VSSMPHY_SENSE

8 OF 13

+3VALW_D SW

0.1U_0402_10V6K

1

CH40

2

1P_0402_50V8

1

2

reserve filter folloe CRB
8/21

+RTCBATT

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

AW9

BF47

DCPRTC1

BG47

DCPRTC2

V23

AN44

VCCSPI

BC49

VCCRTC1

BD49

VCCRTC2

AN21
AY8
BB7

AC35
AC36
AE35
AE36

AN24

VCCPGPPD

AN26
AP26

AN32

VCCPGPPA

AT44
BE48
BE49

BB14

VCCHDA

AG19
AG20
AN15
AR15
BB11

AF19
AF20

AG31
AF31
AK22
AK23

AJ22

AJ23

BG5

K47
K46

Rev1.0

+3VALW_PC H_PRIM +3VALW_SP I

RH98 0_0603 _5%

RH100 0_0603_5 %

change to 0_0603 (1.0)

JRTC1

1

1

2

2

3

GND

4

GND

ACES_50271 -0020N-001

CONN@

SP02000RO 00

2017/12/18 2018/09/01

2017/12/18 2018/09/01

2017/12/18 2018/09/01

0.182A

+VCCRTCE XT

0.095A

0.05A

0.145A

0.97A

0.262A

0.174A

0.14A

0.343A

0.101A

0.106A

0.113A

0.00767A

0.766A

0.882A

+1.8V_PHVLDO

0.193A

0.0895A

VCCMPHY_SEN SE
VSSMPHY_SENSE

1 2

1

2

Compal Secret Data

Compal Secret Data

Compal Secret Data

Internal LDO

+3VALW_PC H_PRIM

+1.8VALW_P RIM

+1.8V_PHVLDO

RH95 0_0402_ 5%@

TH27TP@
TH28TP@

+1.8VALW_P RIM+1.8VALW

Deciphered Date

Deciphered Date

Deciphered Date

D

+VCCRTCE XT

+3VALW_SP I

+RTCVCC

+1.8VALW_P RIM

+3VALW_D SW

1 2

+1.05VALW_ PCH

+1.05VALW_ PCH

+1.24V_VCCLD OSRAM_IN

+1.24V_PRIM_D PHY

+1.24V_PRIM_M AR

1-3MM FROM PACKAGE
FOR PGPPEF AE35/AE37

reserve for cnvi iss ue (1.0)

+1.8VALW_P RIM + 1.8VALW_PRIM

+3VALW_H DA

+1.8VALW_P RIM

Short pins AJ22,AJ23,AK22,AK23 together
at surface layer from PDG Rev0.71

0.1U_0402_10V6K

1

CH36

2

@

0.1U_0402_10V6K

1

CH52

2

near AG19/AG20

+VCCRTCE XT

0.1U_0402_10V6K

1

2

+1.8VALW_P RIM

4.7U_0402_6.3V6M

1

1

CH27

2

2

VCCPHVLDO_1P8
(External VRM mode RH172 unmount)

For DDX03 R02

+1.24V_PRIM_M AR

4.7U_0402_6.3V6M

1

CH32

2

+3VALW_PC H_PRIM+3VALW_PC H_PRIM

0.1U_0402_10V6K

1

2

1-3MM FROM PACKAGE
FOR PGPPHK AC35/AC36

10U_0603_6.3V6M

1

CH53

@

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

PCH(7/8)Power

PCH(7/8)Power

PCH(7/8)Power

Size Document Number R ev

Size Document Number R ev

Size Document Number R ev

Custom

Custom

Custom

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

Dat e: Sheet of

Dat e: Sheet of

Dat e: Sheet of

GPP A

GPP B
GPP C

GPP D

GPP E
GPP F

CH24

GPP G

GPP H
GPP K

GPP I

GPP J

GPD

1U_0402_6.3V6K

CH28

Close to BB11

+1.24V_VCCLD OSRAM_IN +1.24V_PRIM_DPHY

RH96 0_0402_5%@

RH174 for 571391_CFL_H_PDG_Rev0p71.pdf

CH39

@

1-3MM FROM PACKAGE
FOR VCCPRIM AY8/BB7

E

1 2

+3VALW_PC H_PRIM

1U_0402_6.3V6K

1

CH37

2

3.3 V

3.3 V

3.3 V

*

1.8 V

3.3 V

3.3 V

3.3 V

3.3V Only

1.8V Only

3.3V Only

0.1U_0402_10V6K

1

CH38

2

21 67Thursday, Febru ary 22, 2018

21 67Thursday, Febru ary 22, 2018

21 67Thursday, Febru ary 22, 2018

1.0

1.0

1.0

1

4

A

B

C

D

E

CNP-H

CNP-H

UH1I

A2

VSS

1

2 2

3

A28

A33
A37

A45
A46
A47

A48

AA19
AA20
AA25
AA27
AA28
AA30

AA31

AA49

AA5
AB19
AB25
AB31
AC12
AC17
AC33
AC38

AC4
AC46

AD1
AD19

AD2
AD22
AD25
AD49
AE12
AE33
AE38

AE4
AE46

AF22
AF25

AF28

AG1
AG22
AG23
AG25
AG27
AG28
AG30
AG49
AH12
AH17
AH33
AH38

AJ19
AJ20
AJ25
AJ27
AJ28
AJ30

AJ31
AK19
AK20
AK25
AK27
AK28
AK30
AK31

AK4

AK46

A3

A4

A5
A8

VSS

VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS

VSS

9 OF 13

VSS

CNP-H_B GA874

VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS

VSS
VSS

VSS
VSS

VSS
VSS
VSS
VSS
VSS
VSS

VSS

VSS
VSS
VSS
VSS

VSS
VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS

VSS

VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS

VSS
VSS
VSS
VSS
VSS
VSS

Rev1.0

AL12
AL17
AL21
AL24
AL26
AL29
AL33

AL38
AM1

AM18
AM32
AM49
AN12
AN16
AN34

AN38

AP4

AP46
AR12
AR16

AR34
AR38
AT1
AT16
AT18
AT21

AT24

AT26
AT29
AT32
AT34

AT45
AV11

AV39
AW10
AW4
AW40
AW46
B47
B48
B49
BA12

BA14
BA44

BA5
BA6
BB41
BB43
BB9
BC10
BC13
BC15
BC19

BC24
BC26

BC31
BC35
BC40
BC45
BC8
BD43
BE44
BF1
BF2

BF3
BF48

BF49
BG17
BG2
BG22
BG25
BG28

BG3
BG33
BG37

BG4
BG48

C12

C25

C30

C48

D12

D16

D17

D30

D33

E10
E13
E15
E17
E19
E22
E24
E26
E31
E33
E35
E40
E42

F41
F43
F47

G44

J10
J26
J29

J40
J46
J47
J48

K11

K39
M16
M18
M21

C4

C5

D8

E8

G6

H8

J4

J9

UH1L

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

12 OF 13

VSS

CNP-H_B GA874

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

Rev1.0

M24
M32
M34
M49
M5
N12
N16
N34
N35
N37
N38
P26
P29
P4
P46
R12
R16
R26
R29
R3
R34
R38
R4
T17
T18
T32
T4
T49
T5
T7
U12
U15
U17
U21
U24
U33
U38
V20
V22
V4
V46
W25
W27
W28
W30
Y10
Y12
Y17
Y33
Y38
Y9

CNP-H

UH1J

RSVD7
RSVD8
RSVD6
RSVD5

RSVD3
RSVD4

RSVD2
RSVD1

PREQ#

PRDY#

CPU_TRST#

TRIGGER_OUT

TRIGGER_IN

10 OF 13

CNP-H_B GA874

Rev1.0

Y14
Y15
U37
U35

N32
R32

AH15
AH14

AL2
AM5
AM4
AK3
AK2

XDP_PR EQ#
XDP_PR DY#
CPU_XD P_TRST#
PCH_TR IGOUT
CPU_TR IGOUT_R

1 2

RH106 30_04 02_5%

PCH_TR IGOUT_R

XDP_PR EQ# < 11>
XDP_PR DY# < 11>
CPU_XD P_TRST# <11 >

PCH_TR IGOUT_R <14 >
CPU_TR IGOUT_R <14 >

1

3

4 4

Security Classification

Security Classification

Security Classification

2017/12 /18 2018/09 /01

2017/12 /18 2018/09 /01

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

A

B

2017/12 /18 2018/09 /01

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

PCH(8/8)GND/RSVD

PCH(8/8)GND/RSVD

PCH(8/8)GND/RSVD

Size Document Number Re v

Size Document Number R ev

Size Document Number R ev

Custom

Custom

Custom

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

Dat e: Sheet o f

Dat e: Sheet

D

Dat e: Sheet

E

o f

22 67Thursday, Febru ary 22, 2018

o f

22 67Thursday, Febru ary 22, 2018

22 67Thursday, Febru ary 22, 2018

1.0

1.0

1.0

5

4

3

2

1

CHANNEL-A

BOT

REVERSE TYPE

Interleaved Memory

TOP: JDIMM1 CONN Non-ECC DIMM

D

12

@

1

2

RD4
0_0402_5 %

RD3
0_0402_5 %

12

@

1

2

RD1
0_0402_5 %

RD6
0_0402_5 %

PLACE ALL THE BELOW RESISTORS CLOSE TO SODIMM

SPD ADDRESS FOR CHANNEL A :
WRITE ADDRESS: 0XA0
READ ADDRESS: 0XA1
SA0 = 0; SA1 = 0; SA2 = 0.
DDR4 POR OPERATING SPEED: 1867 MT/S

C C

STRETCH GOAL IS 2133 MT/S

Layout Note:
Place near JDIMM1.257,259

+2.5V

10U_0603_6.3V6M

10U_0603_6.3V6M

1

1

CD3

2

2

Layout Note:
PLACE THE CAP near JDIMM1. 164

B B

+0.6V_DDR_ VREFCA

2

CD11

0.1U_0402 _10V6K

1

10uF* 2
1uF*2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

CD5

2

CD6

2

2.2uF *1

0.1uF *1

2

CD12

2.2U_0402 _6.3V6M

1

CD4

+3VS+ 3VS+3VS

1

RD5

@

0_0402_5 %

2

SA2_CHA_DIM1SA1_CHA_DIM1SA0_CHA_DIM1

1

RD2
0_0402_5 %

2

PLACE NEAR TO PIN

Layout Note:
Place near JDIMM1.258

+0.6VS_VTT

10U_0603_6.3V6M

1

2

10uF* 2
1uF*1

1U_0402_6.3V6K

10U_0603_6.3V6M

1

1

CD7

CD9

CD8

2

2

+1.2V_VDDQ

+3VS

0.1U_0402_10V6K

2.2U_0402_6.3V6M

+0.6V_DDR_ VREFCA

2

2

CD2

CD1

1

1

Part Number:SP07001FYH0
Part Value:S SOCKET FOX_AS0A826-H4RB-7H 260P DDR4

DDR_A_D[0..1 5]< 8>

DDR_A_D[16 ..31]<8>

DDR_A_D[32 ..47]<8>

DDR_A_D[48 ..63]<8>

JDIMM1B

REVERSE

111

VDD1

112

VDD2

117

VDD3

118

VDD4

123

VDD5

124

VDD6

129

VDD7

130

VDD8

135

VDD9

136

VDD10

255

VDDSPD

164

VREFCA

1

VSS

2

VSS

5

VSS

6

VSS

9

VSS

10

VSS

14

VSS

15

VSS

18

VSS

19

VSS

22

VSS

23

VSS

26

VSS

27

VSS

30

VSS

31

VSS

35

VSS

36

VSS

39

VSS

40

VSS

43

VSS

44

VSS

47

VSS

48

VSS

51

VSS

52

VSS

56

VSS

57

VSS

60

VSS

61

VSS

64

VSS

65

VSS

68

VSS

69

VSS

72

VSS

73

VSS

77

VSS

78

VSS

81

VSS

82

VSS

85

VSS

86

VSS

89

VSS

90

VSS

93

VSS

94

VSS

98

VSS

262

GND

LOTES_ADDR 0206-P001A

CONN@

VDD11
VDD12
VDD13
VDD14
VDD15
VDD16

VDD17
VDD18
VDD19

VPP1
VPP2

GND

141
142
147
148
153
154

159
160
163

258

VTT

257
259

99

VSS

102

VSS

103

VSS

106

VSS

107

VSS

167

VSS

168

VSS

171

VSS

172

VSS

175

VSS

176

VSS

180

VSS

181

VSS

184

VSS

185

VSS

188

VSS

189

VSS

192

VSS

193

VSS

196

VSS

197

VSS

201

VSS

202

VSS

205

VSS

206

VSS

209

VSS

210

VSS

213

VSS

214

VSS

217

VSS

218

VSS

222

VSS

223

VSS

226

VSS

227

VSS

230

VSS

231

VSS

234

VSS

235

VSS

238

VSS

239

VSS

243

VSS

244

VSS

247

VSS

248

VSS

251

VSS

252

VSS

261

+1.2V_VDDQ

+0.6VS_VTT

+2.5V

+1.2V_VDDQ

DDR_DRAM RST#_R

RD7 240_0402_1 %

2

@

1

+1.2V_VDDQ

(4 mm)

DDR_A_CLK 0<8>
DDR_A_CLK #0<8>
DDR_A_CLK 1<8>
DDR_A_CLK #1<8>

DDR_A_CKE 0<8>
DDR_A_CKE 1<8>

DDR_A_CS# 0<8>
DDR_A_CS# 1<8>

DDR_A_ODT 0<8>
DDR_A_ODT 1<8>

DDR_A_BG0<8>
DDR_A_BG1<8>
DDR_A_BA0<8>
DDR_A_BA1<8>

DDR_A_MA0<8>
DDR_A_MA1<8>
DDR_A_MA2<8>
DDR_A_MA3<8>

DDR_A_MA4<8>

DDR_A_MA5<8>
DDR_A_MA6<8>
DDR_A_MA7<8>
DDR_A_MA8<8>
DDR_A_MA9<8>
DDR_A_MA10<8 >
DDR_A_MA11<8 >
DDR_A_MA12<8 >
DDR_A_MA13<8 >
DDR_A_MA14_ WE#<8>
DDR_A_MA15_ CAS#< 8>
DDR_A_MA16_ RAS#< 8>

DDR_A_ACT#<8>

DDR_A_PAR<8>
DDR_A_ALERT #<8>

12

DDR_DRAM RST#_R<19,24>

D_CK_SDAT A<19 ,24,43>
D_CK_SCL K<19 ,24,43>

For ECC DIMM

+1.2V_VDDQ

0.1U_0402_10V6K

CD10

PLACE NEAR TO SODIMM

DDR_A_CLK 0

DDR_A_CLK #0
DDR_A_CLK 1
DDR_A_CLK #1

DDR_A_CKE 0
DDR_A_CKE 1

DDR_A_CS# 0
DDR_A_CS# 1

DDR_A_ODT 0
DDR_A_ODT 1

DDR_A_BG0
DDR_A_BG1
DDR_A_BA0
DDR_A_BA1

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3

DDR_A_MA4

DDR_A_MA5
DDR_A_MA6
DDR_A_MA7

DDR_A_MA8

DDR_A_MA9

DDR_A_MA10
DDR_A_MA11
DDR_A_MA12

DDR_A_MA13
DDR_A_MA14_ WE#

DDR_A_MA15_ CAS#

DDR_A_MA16_ RAS#

DDR_A_ACT#

DDR_A_PAR
DDR_A_ALERT #
DIMM1_CHA_EVEN T#
DDR_DRAM RST#_R

SA2_CHA_DIM1
SA1_CHA_DIM1
SA0_CHA_DIM1

JDIMM1A

REVERSE

137

CK0(T)

139

CK0#(C)

138

CK1(T)

140

CK1#(C)

109

CKE0

110

CKE1

149

S0#

157

S1#

162

S2#/C0

165

S3#/C1

155

ODT0

161

ODT1

115

BG0

113

BG1

150

BA0

145

BA1

144

A0

133

A1

132

A2

131

A3

128

A4

126

A5

127

A6

122

A7

125

A8

121

A9

146

A10_AP

120

A11

119

A12

158

A13

151

A14_WE#

156

A15_CAS#

152

A16_RAS#

114

ACT#

143

PARITY

116

ALERT#

134

EVENT#

108

RESET#

254

SDA

253

SCL

166

SA2

260

SA1

256

SA0

92

CB0_NC

91

CB1_NC

101

CB2_NC

105

CB3_NC

88

CB4_NC

87

CB5_NC

100

CB6_NC

104

CB7_NC

97

DQS8(T)

95

DQS8#(C)

12

DM0#/DBI0#

33

DM1#/DBI1#

54

DM2#/DBI2#

75

DM3#/DBI3#

178

DM4#/DBI4#

199

DM5#/DBI5#

220

DM6#/DBI6#

241

DM7#/DBI7#

96

DM8#/DBI8#

LOTES_ADDR 0206-P001A

CONN@

DQS0(T)

DQS0#(C)

DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

DQS1(T)

DQS1#(C)

DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23

DQS2(T)

DQS2#(C)

DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

DQS3(T)

DQS3#(C)

DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39

DQS4(T)

DQS4#(C)

DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47

DQS5(T)

DQS5#(C)

DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55

DQS6(T)

DQS6#(C)

DQ56
DQ57
DQ58
DQ59

DQ60

DQ61

DQ62
DQ63

DQS7(T)

DQS7#(C)

DDR_A_D0

8

DQ0

DDR_A_D1

7

DQ1

DDR_A_D2

20

DQ2

DDR_A_D3

21

DQ3

DDR_A_D4

4

DQ4

DDR_A_D5

3

DQ5

DDR_A_D6

16

DQ6

DDR_A_D7

17

DQ7

DDR_A_DQS0

13

DDR_A_DQS# 0

11

DDR_A_D8

28

DQ8

DDR_A_D9

29

DQ9

DDR_A_D10

41

DDR_A_D11

42

DDR_A_D12

24

DDR_A_D13

25

DDR_A_D14

38

DDR_A_D15

37

DDR_A_DQS1

34

DDR_A_DQS# 1

32

DDR_A_D16

50

DDR_A_D17

49

DDR_A_D18

62

DDR_A_D19

63

DDR_A_D20

46

DDR_A_D21

45

DDR_A_D22

58

DDR_A_D23

59

DDR_A_DQS2

55

DDR_A_DQS# 2

53

DDR_A_D24

70

DDR_A_D25

71

DDR_A_D26

83

DDR_A_D27

84

DDR_A_D28

66

DDR_A_D29

67

DDR_A_D30

79

DDR_A_D31

80

DDR_A_DQS3

76

DDR_A_DQS# 3

74

DDR_A_D32

174

DDR_A_D33

173

DDR_A_D34

187

DDR_A_D35

186

DDR_A_D36

170

DDR_A_D37

169

DDR_A_D38

183

DDR_A_D39

182

DDR_A_DQS4

179

DDR_A_DQS# 4

177

DDR_A_D40

195

DDR_A_D41

194

DDR_A_D42

207

DDR_A_D43

208

DDR_A_D44

191

DDR_A_D45

190

DDR_A_D46

203

DDR_A_D47

204

DDR_A_DQS5

200

DDR_A_DQS# 5

198

DDR_A_D48

216

DDR_A_D49

215

DDR_A_D50

228

DDR_A_D51

229

DDR_A_D52

211

DDR_A_D53

212

DDR_A_D54

224

DDR_A_D55

225

DDR_A_DQS6

221

DDR_A_DQS# 6

219

DDR_A_D56

237

DDR_A_D57

236

DDR_A_D58

249

DDR_A_D59

250

DDR_A_D60

232

DDR_A_D61

233

DDR_A_D62

245

DDR_A_D63

246

DDR_A_DQS7

242

DDR_A_DQS# 7

240

DDR_A_DQS0 <8>

DDR_A_DQS# 0 <8>

DDR_A_DQS1 <8>

DDR_A_DQS# 1 <8>

DDR_A_DQS2 <8>

DDR_A_DQS# 2 <8>

DDR_A_DQS3 <8>

DDR_A_DQS# 3 <8>

DDR_A_DQS4 <8>

DDR_A_DQS# 4 <8>

DDR_A_DQS5 <8>

DDR_A_DQS# 5 <8>

DDR_A_DQS6 <8>

DDR_A_DQS# 6 <8>

DDR_A_DQS7 <8>

DDR_A_DQS# 7 <8>

D

DIMM Side

Layout Note:
Place near JDIMM1

10uF* 6
1uF*8

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

CD16

CD17

1

1

A

2

1

2

2

330uF *1

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

CD19

CD18

CD20

1

2

5

CD21

1

2

1

1

2

2

+1.2V_VDDQ+1.2V_VDDQ

10U_0603_6.3V6M

10U_0603_6.3V6M

CD22

1

2

@

@

1U_0402_6.3V6K

CD23

1

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

CD24

CD25

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

CD26

2

1U_0402_6.3V6K

1

CD27

2

4

1U_0402_6.3V6K

1

1

CD28

CD29

CD30

2

2

+1.2V_VDDQ

1U_0402_6.3V6K

1

2

1

+

2

CD32
330U_D2 _2V_Y

CD31

2

@

CD13

0.1U_0402 _10V6K

1

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

1

2

1

+0.6V_DDR_ VREFCA

RD8
1K_0402_ 1%

RD10
1K_0402_ 1%

2017/12/18 2018/09/01

2017/12/18 2018/09/01

2017/12/18 2018/09/01

2

CD14

0.1U_0402 _10V6K

1

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

1

RD9

2_0402_1 %

2

CPU Side

+0.6V_VREFCA

2

1

CD15

0.022U_04 02_16V7K

2

2

RD11

24.9_0402 _1%

1

VREF traces should be at least 20 mils
wide with 20 mils spacing to other
signal s

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number R ev

Size Document Number R ev

Size Document Number R ev

Dat e: Sheet of

Dat e: Sheet of

Dat e: Sheet of

Compal Electronics, Inc.

DDRIV_CHA: DIMM0

DDRIV_CHA: DIMM0

DDRIV_CHA: DIMM0

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

1

23 67Thursday, Febru ary 22, 2018

23 67Thursday, Febru ary 22, 2018

23 67Thursday, Febru ary 22, 2018

A

1.0

1.0

1.0

5

4

3

2

1

CHANNEL-B

TOP: JDIMM3 CONN

D

@

1

2

1

2

RD12

0_0402_5 %

RD15
0_0402_5 %

Non-ECC DIMM

1

RD13

0_0402_5 %

2

1

RD16

@

0_0402_5 %

2

+3VS+ 3VS+3VS

1

@

2

1

2

RD14

0_0402_5 %

SA2_CHB_D IM3SA1_CHB_D IM3SA0_CHB _DIM3

RD17
0_0402_5 %

PLACE ALL THE BELOW RESISTORS CLOSE TO SODIMM

SPD ADDRESS FOR CHANNEL B :
WRITE ADDRESS: 0XA4
READ ADDRESS: 0XA3
SA0 = 0; SA1 = 1; SA2 = 0.
DDR4 POR OPERATING SPEED: 1867 MT/S
STRETCH GOAL IS 2133 MT/S

C C

Layout Note:
Place near JDIMM3.257,259

10uF* 2
1uF*2

10U_0603_6.3V6M

1

2

Layout Note:
PLACE THE CAP WITHIN 200 MILS
FROM THE JDIMM3

B B

+0.6V_DDRB _VREFCA

A

1U_0402_6.3V6K

10U_0603_6.3V6M

1

1

CD35

2

2

CD42

0.1U_0402 _10V6K

1

Layout Note:
Place near JDIMM3

1

2

1

CD37

CD36

2

2

2

1

10U_0603_6.3V6M

10U_0603_6.3V6M

CD47

CD46

1

1

2

2

1U_0402_6.3V6K

CD38

2.2uF *1

0.1uF *1

CD43

2.2U_0402 _6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

CD49

CD48

1

2

10uF* 6
1uF*8
330uF *1

10U_0603_6.3V6M

CD50

1

2

Layout Note:
Place near JDIMM3.258

+0.6VS_VTT+2.5V

10U_0603_6.3V6M

1

2

10U_0603_6.3V6M

1

2

10U_0603_6.3V6M

10U_0603_6.3V6M

CD52

CD53

1

1

2

2

@

@

10uF* 2
1uF*1

10U_0603_6.3V6M

1U_0402_6.3V6K

1

1

CD40

CD39

CD41

2

2

+1.2V_VDDQ+1.2V_VDDQ

1U_0402_6.3V6K

CD54

1U_0402_6.3V6K

1

1

CD56

CD57

2

2

Interleaved Memory

+3VS

0.1U_0402_10V6K

2

CD33

1

PLACE NEAR TO PIN

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

CD58

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

CD59

CD60

2

2

+1.2V_VDDQ

2.2U_0402_6.3V6M

+0.6V_DDRB _VREFCA

2

CD34

1

1U_0402_6.3V6K

1

CD62

CD61

2

DDR_B_D [0..15]< 9>

DDR_B_D [16..31]<9>

DDR_B_D [32..47]<9>

DDR_B_D [48..63]<9>

111
112
117
118
123
124
129
130
135
136

255

164

10
14
15
18
19
22
23
26
27
30
31
35
36
39
40
43
44
47
48
51
52
56
57
60
61
64
65

68

69
72
73
77
78
81
82
85
86
89
90
93
94
98

262

Part Number:SP07001CEA0
Part Value:S SOCKET FOX_AS0A826-H4SB-7H 260P DDR4

1U_0402_6.3V6K

1

CD63

2

JDIMM2B

RESERVE

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10

VDDSPD

VREFCA

1

VSS

2

VSS

5

VSS

6

VSS

9

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

GND

LOTES_ADDR 0070-P009A

CONN@

VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
VDD19

VPP1
VPP2

GND

141
142
147
148
153
154
159
160
163

258

VTT

257
259

99

VSS

102

VSS

103

VSS

106

VSS

107

VSS

167

VSS

168

VSS

171

VSS

172

VSS

175

VSS

176

VSS

180

VSS

181

VSS

184

VSS

185

VSS

188

VSS

189

VSS

192

VSS

193

VSS

196

VSS

197

VSS

201

VSS

202

VSS

205

VSS

206

VSS

209

VSS

210

VSS

213

VSS

214

VSS

217

VSS

218

VSS

222

VSS

223

VSS

226

VSS

227

VSS

230

VSS

231

VSS

234

VSS

235

VSS

238

VSS

239

VSS

243

VSS

244

VSS

247

VSS

248

VSS

251

VSS

252

VSS

261

+1.2V_VDDQ

+0.6VS_VTT

+2.5V

+1.2V_VDDQ

+1.2V_VDDQ

+1.2V_VDDQ

@

2

CD44

0.1U_0402 _10V6K

1

2

CD51

0.1U_0402 _10V6K

1

2

1

2

1

RD19
1K_0402_ 1%

RD21
1K_0402_ 1%

DDR_B_C LK0< 9>
DDR_B_C LK#0<9>

DDR_B_C LK#1<9>

DDR_B_C KE0<9>

DDR_B_C KE1<9>

DDR_B_C S#0< 9>
DDR_B_C S#1< 9>

DDR_B_OD T0<9>

DDR_B_OD T1<9>

DDR_B_BG 0<9>
DDR_B_BG 1<9>
DDR_B_BA0< 9>
DDR_B_BA1< 9>

DDR_B_MA0<9>
DDR_B_MA1<9>
DDR_B_MA2<9>

DDR_B_MA3<9>
DDR_B_MA4<9>
DDR_B_MA5<9>
DDR_B_MA6<9>
DDR_B_MA7<9>
DDR_B_MA8<9>
DDR_B_MA9<9>
DDR_B_MA1 0<9>
DDR_B_MA1 1<9>
DDR_B_MA1 2<9>
DDR_B_MA1 3<9>

DDR_B_MA1 4_WE#<9>
DDR_B_MA1 5_CAS#< 9>
DDR_B_MA1 6_RAS#< 9>

DDR_B_ACT #<9>

DDR_B_PAR<9>

DDR_B_ALE RT#<9>

2

RD18

240_0402 _1%

DDR_DRAM RST#_R<19,23>

DIMM Side

+0.6V_DDRB _VREFCA

STD

DDR_B_C LK1< 9>

1

D_CK_SDAT A<19 ,23,43>
D_CK_SCL K<19 ,23,43>

For ECC DIMM

1

RD20

2_0402_1 %

2

CD45

0.1U_0402 _10V6K

1

DIMM3_CHB_ EVENT#
DDR_DRAM RST#_R

2

(4 mm)BOT

DDR_B_C LK0
DDR_B_C LK#0
DDR_B_C LK1
DDR_B_C LK#1

DDR_B_C KE0
DDR_B_C KE1

DDR_B_C S#0
DDR_B_C S#1

DDR_B_OD T0
DDR_B_OD T1

DDR_B_BG 0
DDR_B_BG 1
DDR_B_BA0
DDR_B_BA1

DDR_B_MA0

DDR_B_MA1

DDR_B_MA2
DDR_B_MA3

DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7

DDR_B_MA8
DDR_B_MA9

DDR_B_MA1 0

DDR_B_MA1 1
DDR_B_MA1 2
DDR_B_MA1 3
DDR_B_MA1 4_WE#
DDR_B_MA1 5_CAS#
DDR_B_MA1 6_RAS#

DDR_B_ACT #

DDR_B_PAR
DDR_B_ALE RT#

SA2_CHB_D IM3
SA1_CHB_D IM3
SA0_CHB_D IM3

CPU Side

1

CD55

0.022U_04 02_16V7K

2

2

RD22

24.9_0402 _1%

1

JDIMM2A

RESERVE

137

CK0(T)

139

CK0#(C)

138

CK1(T)

140

CK1#(C)

109

CKE0

110

CKE1

149

S0#

157

S1#

162

S2#/C0

165

S3#/C1

155

ODT0

161

ODT1

115

BG0

113

BG1

150

BA0

145

BA1

144

A0

133

A1

132

A2

131

A3

128

A4

126

A5

127

A6

122

A7

125

A8

121

A9

146

A10_AP

120

A11

119

A12

158

A13

151

A14_WE#

156

A15_CAS#

152

A16_RAS#

114

ACT#

143

PARITY

116

ALERT#

134

EVENT#

108

RESET#

254

SDA

253

SCL

166

SA2

260

SA1

256

SA0

92

CB0_NC

91

CB1_NC

101

CB2_NC

105

CB3_NC

88

CB4_NC

87

CB5_NC

100

CB6_NC

104

CB7_NC

97

DQS8(T)

95

DQS8#(C)

12

DM0#/DBI0#

33

DM1#/DBI1#

54

DM2#/DBI2#

75

DM3#/DBI3#

178

DM4#/DBI4#

199

DM5#/DBI5#

220

DM6#/DBI6#

241

DM7#/DBI7#

96

DM8#/DBI8#

LOTES_ADDR 0070-P009A

CONN@

+0.6V_B_VREFD Q

VREF traces should be at least 20 mils
wide with 20 mils spacing to other
signal s

DQS0(T)

DQS0#(C)

DQS1(T)

DQS1#(C)

DQS2(T)

DQS2#(C)

DQS3(T)

DQS3#(C)

DQS4(T)

DQS4#(C)

DQS5(T)

DQS5#(C)

DQS6(T)

DQS6#(C)

DQS7(T)

DQS7#(C)

DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23

DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39

DQ40

DQ41
DQ42
DQ43

DQ44
DQ45
DQ46
DQ47

DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55

DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

DDR_B_D 0

8

DQ0

DDR_B_D 1

7

DQ1

DDR_B_D 2

20

DQ2

DDR_B_D 3

21

DQ3

DDR_B_D 4

4

DQ4

DDR_B_D 5

3

DQ5

DDR_B_D 6

16

DQ6

DDR_B_D 7

17

DQ7

DQ8
DQ9

13
11

28
29

41
42
24
25
38
37

34
32

50
49
62
63
46
45
58
59

55
53

70
71
83
84
66
67
79
80

76
74

174
173
187
186
170
169
183

182
179
177

195
194
207
208

191
190
203
204

200
198

216
215
228
229
211
212

224
225
221
219

237
236
249
250
232
233
245
246
242
240

DDR_B_D QS0
DDR_B_D QS#0

DDR_B_D 8
DDR_B_D 9
DDR_B_D 11
DDR_B_D 15
DDR_B_D 14
DDR_B_D 10
DDR_B_D 12
DDR_B_D 13

DDR_B_D QS1
DDR_B_D QS#1

DDR_B_D 16
DDR_B_D 17
DDR_B_D 19

DDR_B_D 20

DDR_B_D 22
DDR_B_D 18
DDR_B_D 23
DDR_B_D 21

DDR_B_D QS2
DDR_B_D QS#2

DDR_B_D 30

DDR_B_D 25

DDR_B_D 26

DDR_B_D 24

DDR_B_D 28
DDR_B_D 27

DDR_B_D 29

DDR_B_D 31

DDR_B_D QS3
DDR_B_D QS#3

DDR_B_D 34
DDR_B_D 35
DDR_B_D 36
DDR_B_D 32
DDR_B_D 39
DDR_B_D 38
DDR_B_D 37
DDR_B_D 33

DDR_B_D QS4
DDR_B_D QS#4

DDR_B_D 40
DDR_B_D 41
DDR_B_D 42
DDR_B_D 43
DDR_B_D 44
DDR_B_D 45
DDR_B_D 46
DDR_B_D 47

DDR_B_D QS5
DDR_B_D QS#5

DDR_B_D 48
DDR_B_D 52
DDR_B_D 50
DDR_B_D 55
DDR_B_D 51
DDR_B_D 54
DDR_B_D 49
DDR_B_D 53

DDR_B_D QS6
DDR_B_D QS#6

DDR_B_D 61

DDR_B_D 57

DDR_B_D 60
DDR_B_D 56
DDR_B_D 62
DDR_B_D 59

DDR_B_D 63

DDR_B_D 58

DDR_B_D QS7
DDR_B_D QS#7

DDR_B_D QS0 <9>

DDR_B_D QS#0 <9>

DDR_B_D QS1 <9>

DDR_B_D QS#1 <9>

DDR_B_D QS2 <9>

DDR_B_D QS#2 <9>

DDR_B_D QS3 <9>

DDR_B_D QS#3 <9>

DDR_B_D QS4 <9>

DDR_B_D QS#4 <9>

DDR_B_D QS5 <9>

DDR_B_D QS#5 <9>

DDR_B_D QS6 <9>

DDR_B_D QS#6 <9>

DDR_B_D QS7 <9>

DDR_B_D QS#7 <9>

D

A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2017/12/18 2018/09/01

2017/12/18 2018/09/01

2017/12/18 2018/09/01

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number R ev

Size Document Number R ev

Size Document Number R ev

Dat e: Sheet of

Dat e: Sheet of

2

Dat e: Sheet

Compal Electronics, Inc.

DDRIV_CHB: DIMM0

DDRIV_CHB: DIMM0

DDRIV_CHB: DIMM0

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

1

24 67Thursday, Febru ary 22, 2018

24 67Thursday, Febru ary 22, 2018

24 67Thursday, Febru ary 22, 2018

1.0

1.0

1.0

of

A

UV1A

2

PEX_TREMP

1.35VS_DGPU_PG<59>

1

2

AN12
AM12
AN14
AM14
AP14
AP15
AN15
AM15
AN17
AM17
AP17
AP18
AN18
AM18
AN20
AM20
AP20
AP21
AN21
AM21
AN23
AM23
AP23
AP24
AN24
AM24
AN26
AM26
AP26
AP27
AN27
AM27

AK14
AJ14
AH14
AG14
AK15
AJ15

AL16
AK16

AK17

AJ17
AH17
AG17
AK18
AJ18
AL19
AK19
AK20
AJ20
AH20
AG20
AK21
AJ21
AL22
AK22

AK23

AJ23
AH23
AG23
AK24
AJ24
AL25
AK25

AJ11

AL13
AK13
AK12

AJ12
AP29

1VS_DGPU_PG

GC6_FB_EN3V3

1VS_DGPU_PG<60>

GC6_FB_EN3V3 < 20>

+1.8VSDGPU_AON

UV2
NL17SZ08DFT2G_SC70-5

5

VGA@

IN B

VCC
OUT Y

IN A

GND

3

GP107-ES-A1_BGA908

@

NL17SZ08DFT2G_SC70-5

4

PEG_CTX_C_GRX_P0<10>
PEG_CTX_C_GRX_N0< 10>
PEG_CTX_C_GRX_P1<10>
PEG_CTX_C_GRX_N1< 10>
PEG_CTX_C_GRX_P2<10>
PEG_CTX_C_GRX_N2< 10>
PEG_CTX_C_GRX_P3<10>
PEG_CTX_C_GRX_N3< 10>
PEG_CTX_C_GRX_P4<10>
PEG_CTX_C_GRX_N4< 10>
PEG_CTX_C_GRX_P5<10>

CLK_PEG_VGA<16>
CLK_PEG_VGA#<16>

RV111

10K_0402_5%

VGA@

2

QV8B

VGA@

+3VS

1

2
6

D

G

S

1

PEG_CTX_C_GRX_N5< 10>
PEG_CTX_C_GRX_P6<10>
PEG_CTX_C_GRX_N6< 10>
PEG_CTX_C_GRX_P7<10>
PEG_CTX_C_GRX_N7< 10>
PEG_CTX_C_GRX_P8<10>
PEG_CTX_C_GRX_N8< 10>
PEG_CTX_C_GRX_P9<10>
PEG_CTX_C_GRX_N9< 10>
PEG_CTX_C_GRX_P10<10>
PEG_CTX_C_GRX_N10<10>
PEG_CTX_C_GRX_P11<10>
PEG_CTX_C_GRX_N11<10>
PEG_CTX_C_GRX_P12<10>
PEG_CTX_C_GRX_N12<10>
PEG_CTX_C_GRX_P13<10>
PEG_CTX_C_GRX_N13<10>
PEG_CTX_C_GRX_P14<10>
PEG_CTX_C_GRX_N14<10>
PEG_CTX_C_GRX_P15<10>
PEG_CTX_C_GRX_N15<10>

PEG_CRX_C_GTX_P0<10>
PEG_CRX_C_GTX_N0< 10>
PEG_CRX_C_GTX_P1<10>
PEG_CRX_C_GTX_N1< 10>
PEG_CRX_C_GTX_P2<10>
PEG_CRX_C_GTX_N2< 10>
PEG_CRX_C_GTX_P3<10>
PEG_CRX_C_GTX_N3< 10>
PEG_CRX_C_GTX_P4<10>
PEG_CRX_C_GTX_N4< 10>
PEG_CRX_C_GTX_P5<10>
PEG_CRX_C_GTX_N5< 10>
PEG_CRX_C_GTX_P6<10>
PEG_CRX_C_GTX_N6< 10>
PEG_CRX_C_GTX_P7<10>
PEG_CRX_C_GTX_N7< 10>
PEG_CRX_C_GTX_P8<10>
PEG_CRX_C_GTX_N8< 10>
PEG_CRX_C_GTX_P9<10>
PEG_CRX_C_GTX_N9< 10>
PEG_CRX_C_GTX_P10<10>
PEG_CRX_C_GTX_N10<10>
PEG_CRX_C_GTX_P11<10>
PEG_CRX_C_GTX_N11<10>
PEG_CRX_C_GTX_P12<10>
PEG_CRX_C_GTX_N12<10>
PEG_CRX_C_GTX_P13<10>
PEG_CRX_C_GTX_N13<10>
PEG_CRX_C_GTX_P14<10>
PEG_CRX_C_GTX_N14<10>
PEG_CRX_C_GTX_P15<10>
PEG_CRX_C_GTX_N15<10>

RV7 10K_0402_5%VGA@

PLTRST_VGA#_1V8

RV113

4.7K_0402_5%

VGA@

G

5

QV8A

VGA@

DGPU_HOLD_RST#

A

DGPU_CLKREQ#

1 2

1

RV10

VGA@

2.49K_0402_1%

1

2

GC6_FB_EN3V3

3

D

S

PJT138KA 2N SOT363-6

4

PLT_RST#

1 1

2

+1.8VSDGPU_AON

3 3

GC6 2.0 function

GC6_FB_EN1V8

PJT138KA 2N SOT363-6

4 4

PLT_RST#<17>

DGPU_HOLD_RST#<20>

Part 1 of 7

PEX_RX0
PEX_RX0_N
PEX_RX1
PEX_RX1_N
PEX_RX2
PEX_RX2_N
PEX_RX3
PEX_RX3_N
PEX_RX4
PEX_RX4_N
PEX_RX5
PEX_RX5_N
PEX_RX6
PEX_RX6_N
PEX_RX7
PEX_RX7_N
PEX_RX8
PEX_RX8_N
PEX_RX9
PEX_RX9_N
PEX_RX10
PEX_RX10_N
PEX_RX11
PEX_RX11_N

PEX_RX12

PEX_RX12_N
PEX_RX13
PEX_RX13_N
PEX_RX14
PEX_RX14_N
PEX_RX15
PEX_RX15_N

PEX_TX0
PEX_TX0_N
PEX_TX1
PEX_TX1_N
PEX_TX2
PEX_TX2_N
PEX_TX3

PEX_TX3_N

PEX_TX4
PEX_TX4_N

PEX_TX5
PEX_TX5_N
PEX_TX6
PEX_TX6_N
PEX_TX7
PEX_TX7_N
PEX_TX8
PEX_TX8_N
PEX_TX9
PEX_TX9_N
PEX_TX10
PEX_TX10_N
PEX_TX11
PEX_TX11_N
PEX_TX12
PEX_TX12_N

PEX_TX13

PEX_TX13_N
PEX_TX14
PEX_TX14_N
PEX_TX15
PEX_TX15_N

NC

PEX_REFCLK
PEX_REFCLK_N
PEX_CLKREQ_N

PEX_RST_N
PEX_TERMP

RV16 100K_0402_5%VGA@

CV200 0 .1U_0201_10V6K

+1.8VSDGPU_AON

UV11

VGA@

1

IN B

2

IN A

DV3

2

3

BAV70W_SOT323-3

+1.8VSDGPU_AON

1

2

1

2

1

PCI EXPRESS

5

VCC
OUT Y

GND

3

1

VGA@

RV100
10K_0402_5%

@

2

@

GPIO

CLK

XTAL_OUTBUFF

PLTRST_VGA#_1V8

I2CB_SCL
I2CB_SDA

I2CC_SCL
I2CC_SDA

I2C

I2CS_SCL
I2CS_SDA

XS_PLLVDD

SP_PLLVDD

VID_PLLVDD

XTAL_OUT

XTAL_SSIN

+1.8VSDGPU_AON

2

1

4

1

2

P6

GPIO0

M3

GPIO1

L6

GPIO2

P5

GPIO3

P7

GPIO4

L7

GPIO5

M7

GPIO6

N8

GPIO7

L3

GPIO8

M2

GPIO9

L1

GPIO10

M5

GPIO11

N3

GPIO12

M4

GPIO13

N4

GPIO14

P2

GPIO15

R8

GPIO16

M6

GPIO17

R1

GPIO18

P3

GPIO19

P4

GPIO20

P1

GPIO21

P8

GPIO22

T8

GPIO23

L2

GPIO24

R4

GPIO25

R5

GPIO26

U3

GPIO27

AK9

NC

AL10

NC

AL9

NC

AM9

NC

AN9

NC

AG10

NC

AP8

NC

AK26

NC

AJ26

NC

AP9

TS_VREF

R7
R6

R2
R3

T4
T3

AD8

AE8

AD7

H3

XTAL_IN

H2

J4
H1

RV83
10K_0402_5%

@

ALL_GPWRGD

1

VGA@

CV226

0.1U_0201_10V6K

2

1.35VSDGPU_PW R_EN <29>

RV12
100K_0402_1%

VGA@

B

DGPU_VID
GC6_FB_EN1V8
GPU_EVENT#_1

1.8VSDGPU_MAIN_EN
FRM_LCK#
DGPU_PSI

GPU_INV_PWM

VRAM_VDD_CTL
VGA_ALERT
VRAM_VREF_CTL

DGPU_ENVDD

ACIN_BUF

GPU_ENBKL

SYS_PEX_RST_MON#

DGPU_EDP_HPD#

GPU_PEX_RST_HOLD#

HDMI_HPD_GPU#

unused pin PH 2K to 1V8AON

1 2

RV86 2K_0402_5%VGA@

1 2

RV85 2K_0402_5%VGA@

1 2

RV5 2K_040 2_5%VGA@

1 2

RV6 2K_040 2_5%VGA@

VGA_I2CS_SCL

VGA_I2CS_SDA

+GPU_PLLVDD

XTALIN
XTALOUT

10K_0402_5%

XTAL_OUTBUFF

1

XTAL_SSIN

1 2

B

DGPU_VID <61>

DGPU_PSI <61>

VRAM_VDD_CTL <59>

VRAM_VREF_CTL <30,31 >

0.1U_0201_10V6K

1

CV5

VGA@

2

Near
AD7

RV9

2

VGA@
VGA@

RV11

10K_0402_5%

1.8VSDGPU_MAIN_EN <29>

12

DV2

RB751S40T1G_SOD523-2

VGA@

+1.8VSDGPU_AON

+GPU_PLLVDD

0.1U_0201_10V6K

0.1U_0201_10V6K

1

1

CV3

CV6

VGA@

VGA@

2

2

Near

Near

AD8

AE8

VGA@

12

DV8

RB751S40T1G_SOD523-2

DGPU_AC_DETECT <39,50>

4.7U_0402_6.3V6M

1

CV42

VGA@

2

GC6_FB_EN1V8

QV6B

PJT138KA 2N SOT363-6

LV1
TAI-TECH HCB1608KF-330T30

22U_0603_6.3V6M

1

CV4

VGA@

2

Near
GPU

@

C

GPU_EVENT# <20>

VGA_OVERT#<27>

+1.8VSDGPU_MAIN

VGA@

1 2

SM010 00JX00

HDMI_HPD_PCH<17,34>

1.8VSDGPU_MAIN_EN

+1.8VSDGPU_AON

1

RV102
10K_0402_5%

@

2

6

D

G

2

S

1

PLTRST_VGA#_1V8

GC6_FB_EN1V8#

2

CV224

0.1U_0201_10V6K

1

@

1.A Modify

2

1

Thermal shutdown protection

C

0.1U_0201_10V6K

HDMI_HPD_PCH

PLTRST_VGA#_1V8

NL17SZ08DFT2G_SC70-5

PJT138KA 2N SOT363-6

+1.8VSDGPU_AON

CV199

0.1U_0201_10V6K

@

5

1

IN B

VCC

2

IN A

GND

3

PLTRST_VGA#_1V8

+1.8VSDGPU_MAIN

NL17SZ08DFT2G_SC70-5

VGA_ALERT

DGPU_CLKREQ#

+1.8VSDGPU_MAIN

VGA_OVERT#

QV1B

PJT138KA 2N SOT363-6

VGA@

+1.8VSDGPU_AON

VGA@

CG340

12

1

IN B

2

IN A

VGA@

UG28

+3VS

G

2

QV7B

VGA@

GPU_OVERT#

UV9

@

NL17SZ08DFT2G_SC70-5

4

OUT Y

2

@

CV227

0.1U_0201_10V6K

1

D

+1.8VSDGPU_AON

1

2

UV12

@

VGA_GATE

2

S

QV5B
PJT138KA 2N SOT363-6

ALL_GPWRGD

5

S

QV5A
PJT138KA 2N SOT363-6

1

RV131
100K_0201_5%

VGA@

2

6

D

G

2

S

1

5

IN B

IN A

G

D

G

D

61

34

VGA@

VGA@

VCC

GND

3

OUT Y

PCH side

5

VGA_GATE

4

GPU_ALERT <39>

VGA_CLKREQ# <16>

3

D

G

QV1A

S

PJT138KA 2N SOT363-6

VGA@

4

1

CV201

0.01U_0402_16V7K

2

@

PU at EC side

GPU_OVERT# <39>

XTALOUT

VRAM_VREF_CTL
GC6_FB_EN1V8

1.8VSDGPU_MAIN_EN

SYS_PEX_RST_MON#

VGA_I2CS_SDA

VGA_I2CS_SCL

DGPU_PSI

GPU_PEX_RST_HOLD#

VGA_I2CS_SCL

VGA_I2CS_SDA

XTALOUT_R

12

RV80
0_0402_5%

VGA@

VGA@

CV1

VGA_OVERT#
VGA_ALERT
FRM_LCK#
ACIN_BUF

GPU_EVENT#_1

RV1 10 K_0402_5%VGA@

RV2 1 .8K_0402_1%VGA@

RV3 1. 8K_0402_1%VGA@
RV4 10 K_0402_5%VGA@

RV82 10K_0402_5%VGA@

VGA@

VGA@

1

2

15P_0402_50V8J

S

S

RESERVE FOR DIS eDP

+1.8VSDGPU_AON

1

VGA@

RG180

10K_0402_5%

2

5

VCC
OUT Y

GND

3

1

RV106
10K_0402_5%

VGA@

2

6

D

S

1

5

G

QV7A

VGA@

5

3

D

S

4

1

D

4

2

G

S

3

1

RV108
10K_0402_5%

VGA@

2

1.8VSDGPU_MAIN

3

D

G

S

4

PJT138KA 2N SOT363-6

1 2

DV7

RB751S40T1G_SOD523-2

QV6A
PJT138KA 2N SOT363-6

@

HDMI_HPD_GPU#

VGA@

QG5
MESS138W-G_S OT323-3

1.0 Modify

VGA@

1

2

NL17SZ08DFT2G_SC70-5

VGA@

remove DV6/RV104

+1.8VSDGPU_AON

+3VS

5

IN B

GPUCORE_EN

VCC

4

OUT Y

IN A

GND

UV10

3

DV4

RB751S40T1G_SOD523-2

2

RV105

6.2K_0402_1%

VGA@

1.0 Modify

VGA@

DV5

RB751S40T1G_SOD523-2

RV103 24.9K_0402_1%

VGA@

VGA_CORE_PG <61>

marge NVVDD remove VGA_CORE_S_PG

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS T HE PROPRIETARY PR OPERTY OF COMPAL ELECTRONICS, IN C. AND C ONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS T HE PROPRIETARY PR OPERTY OF COMPAL ELECTRONICS, IN C. AND C ONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS T HE PROPRIETARY PR OPERTY OF COMPAL ELECTRONICS, IN C. AND C ONTAINS CONFIDENTIAL
AND TRADE SECRET INFORM ATION. THIS SHEE T MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D

AND TRADE SECRET INFORM ATION. THIS SHEE T MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D

AND TRADE SECRET INFORM ATION. THIS SHEE T MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D
DEPARTMENT EXC EPT AS AUTHORIZE D BY COMPAL ELECT RONICS, INC. NEIT HER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXC EPT AS AUTHORIZE D BY COMPAL ELECT RONICS, INC. NEIT HER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXC EPT AS AUTHORIZE D BY COMPAL ELECT RONICS, INC. NEIT HER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2017/12/18 2018/09/01

2017/12/18 2018/09/01

2017/12/18 2018/09/01

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

VGA@

1 2

1

GPU_INV_PWM

GPU_ENBKL

DGPU_ENVDD

RG193 1 0K_0402_5%@

12

1

2

CV197

0.1U_0201_10V6K

1

VGA@

2

2

CV196

0.22U_0402_16V7K

1

VGA@

+1.8VSDGPU_AON

RVP1

10K_0804_8P4R_5%

18
27
36
45

VGA@

RVP2

10K_0804_8P4R_5%

1

8

2

7

3

6

45

VGA@

12

1 2

1 2

12

1

2

+1.8VSDGPU_MAIN

5

QV2A

G

PJT138KA 2N SOT363-6

34

D

+1.8VSDGPU_MAIN

2

QV2B

G

PJT138KA 2N SOT363-6

61

D

1

EC_SMB_CK2 <19,39,40,44>

EC_SMB_DA2 <19,39,40,44>

27MHZ_10PF_XRCGB27M000F2P 18R0
XV1

1

VGA@

3

3

NC

NC

2

4

CV2

Crystals must have a max ESR of 80 ohm

@

+1.8VSDGPU_AON

1 2

DGPU_EDP_HPD#

MESS138W-G_S OT323-3

for PEX_VDD dis-charge

Enable: Vh:1.5V
Vl:0.7V

VDDS delay

1.33ms

RG194

10K_0402_5%

5

G

@

34

QV9A

S

D

PJT138KA 2N SOT363-6

+1.8VSDGPU_AON

2

@

G

61

QV9B

D

S

PJT138KA 2N SOT363-6

1

D

@

QG6

S

3

GPUCORE_EN <29>

VGA_CORE_EN < 29,61>DGPU_P WR_EN <20>

1.0VSDGPU_EN <60>

rename from VGA_CORE_S_EN

Title

Title

Title

Size

Size

Size

Custom

Custom

Custom

Date : Sheet of

Date : Sheet

Date : Sheet

E

XTALIN

1

VGA@

2

12P_0402_50V8J

@

+3VS

GPU_INV_PWM
GPU_ENBKL
DGPU_ENVDD

1

2

1

@

RG195
10K_0402_5%

2

1 2

RV135 0_0402_5%@

2

G

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Document Number Re v

Document Number Re v

Document Number Re v

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

E

RVP3

1
2
3 6
4 5

100K_0804_8P4R_5%

PCH_BKL_PW M <18, 33>

ENBKL < 18,39>

CLOSE UX1

PCH_ENVDD <18,33>

EDP_HPD <17,33>

N17P PEG 1/7

N17P PEG 1/7

N17P PEG 1/7

8
7

of

of

25 67Thursda y, February 22, 2018

25 67Thursda y, February 22, 2018

25 67Thursda y, February 22, 2018

1.0

1.0

1.0

2

A

AG28

AF29

AG29

AF28

AD30

AD29
AC29

AD28

AJ29

AK29

AJ30
AK28
AM29
AM31
AN29
AM30
AN31
AN32
AP30
AP32
AM33

AL31
AK33
AK32
AD34
AD32
AC30
AD33

AF31
AG34
AG32
AG33

AD31

AL29
AM32

AF34

AE31
AK30
AN33

AF33

AF30
AK31
AM34

AF32

L28
M29
L29
M28

N31
P29
R29
P28
J28
H29
J29
H28

G29
E31

E32

F30

C34

D32
B33
C33
F33
F32

H33

H32
P34

P32
P31
P33

L31

L34

L32

L33

P30
F31
F34
M32

M31

G31
E33
M33

M30
H30
E34
M34

UV1B

FBA_D0
FBA_D1
FBA_D2
FBA_D3

FBA_D4
FBA_D5
FBA_D6
FBA_D7
FBA_D8
FBA_D9
FBA_D10
FBA_D11
FBA_D12

FBA_D13

FBA_D14

FBA_D15

FBA_D16

FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21

FBA_D22

FBA_D23
FBA_D24
FBA_D25

FBA_D26
FBA_D27

FBA_D28

FBA_D29

FBA_D30

FBA_D31
FBA_D32
FBA_D33
FBA_D34
FBA_D35

FBA_D36

FBA_D37

FBA_D38

FBA_D39
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63

FBA_DQM0
FBA_DQM1
FBA_DQM2
FBA_DQM3
FBA_DQM4
FBA_DQM5
FBA_DQM6
FBA_DQM7

FBA_DQS_WP0

FBA_DQS_WP1
FBA_DQS_WP2
FBA_DQS_WP3
FBA_DQS_WP4
FBA_DQS_WP5
FBA_DQS_WP6
FBA_DQS_WP7

FBA_DQS_RN0
FBA_DQS_RN1
FBA_DQS_RN2
FBA_DQS_RN3
FBA_DQS_RN4
FBA_DQS_RN5
FBA_DQS_RN6
FBA_DQS_RN7

Part 2 of 7

MEMORY INTERFACE

FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8

FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13

FBA_CMD14

FBA_CMD15

FBA_CMD16

FBA_CMD17
FBA_CMD18
FBA_CMD19

FBA_CMD20

FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
FBA_CMD29

FBA_CMD30

FBA_CMD31
FBA_CMD32
FBA_CMD33
FBA_CMD34
FBA_CMD35

FBA_CLK0

FBA_CLK0_N

FBA_CLK1

FBA_CLK1_N

A

FBA_WCK01

FBA_WCK01_N

FBA_WCK23

FBA_WCK23_N

FBA_WCK45

FBA_WCK45_N

FBA_WCK67

FBA_WCK67_N

FBA_WCKB01

FBA_WCKB01_N

FBA_WCKB23

FBA_WCKB23_N

FBA_WCKB45

FBA_WCKB45_N

FBA_WCKB67

FBA_WCKB67_N

BUFRST_N

FB_REFPLL_AVDD

FBA_PLL_AVDD

GPCPLL_AVDD

FBA_D[63..0]<30 >

1

2 2

FBA_DBI[7..0]<3 0>

FBA_EDC[7..0]<30>

3 3

FBA_D0

FBA_D1

FBA_D2

FBA_D3
FBA_D4
FBA_D5
FBA_D6
FBA_D7
FBA_D8

FBA_D9

FBA_D10
FBA_D11
FBA_D12

FBA_D13

FBA_D14

FBA_D15

FBA_D16
FBA_D17

FBA_D18

FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26

FBA_D27

FBA_D28
FBA_D29
FBA_D30
FBA_D31
FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37

FBA_D38
FBA_D39

FBA_D40

FBA_D41

FBA_D42
FBA_D43

FBA_D44
FBA_D45

FBA_D46
FBA_D47

FBA_D48

FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_D56
FBA_D57

FBA_D58

FBA_D59

FBA_D60
FBA_D61
FBA_D62
FBA_D63

FBA_DBI0
FBA_DBI1
FBA_DBI2
FBA_DBI3
FBA_DBI4
FBA_DBI5
FBA_DBI6
FBA_DBI7

FBA_EDC0
FBA_EDC1
FBA_EDC2
FBA_EDC3
FBA_EDC4
FBA_EDC5
FBA_EDC6
FBA_EDC7

U30
T31
U29
R34
R33
U32
U33
U28
V28
V29
V30
U34
U31
V34

V33

Y32

AA31

AA29
AA28
AC34

AC33

AA32
AA33
Y28
Y29
W31
Y30
AA34
Y31
Y34

Y33

V31
R28
AC28
R32
AC32

R30
R31
AB31
AC31

K31
L30
H34
J34
AG30
AG31
AJ34
AK34

J30
J31
J32
J33
AH31
AJ31
AJ32
AJ33

E1

K27

U27

H26

B

FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
FBA_CMD29
FBA_CMD30

FBA_CMD31

FBA_DEBUG0
FBA_DEBUG1

GPU_BUFRST #

+FB_PLLAVDD

+GPU_PLLVD D

FBA_CMD[31..0] <30> FBB_D[63..0]<31 >

TV1@
TV3@

FBA_CLKA0 <3 0>
FBA_CLKA0# < 30>
FBA_CLKA1 <3 0>
FBA_CLKA1# < 30>

FBA_WCK0 1 <30>
FBA_WCK0 1# <30>
FBA_WCK2 3 <30>
FBA_WCK2 3# <30>
FBA_WCK4 5 <30>
FBA_WCK4 5# <30>
FBA_WCK6 7 <30>
FBA_WCK6 7# <30>

@

TV9

CV11

VGA@

LV3
TAI-TECH HCB 1608KF-330T30

22U_0603_6.3V6M

1

2

0.1U_0201_10V6K

1

CV9

CV10

VGA@

VGA@

2

Near U27 Near

K27

0.1U_0201_10V6K

1

2

+1.8VSDGPU_ MAIN

VGA@

1 2

SM01000JX00

C

UV1C

FBB_D0

G9

FBB_D1

E9

FBB_D2

G8

FBB_D3

F9

FBB_D4

F11

FBB_D5

G11

FBB_D6

F12

FBB_D7

G12

FBB_D8

G6

FBB_D9

F5

FBB_D10

E6

FBB_D11

F6

FBB_D12

F4

FBB_D13

G4

FBB_D14

E2

FBB_D15

F3

FBB_D16

C2

FBB_D17

D4

FBB_D18

D3

FBB_D19

C1

FBB_D20

B3

FBB_D21

C4

FBB_D22

B5

FBB_D23

C5

FBB_D24

A11

FBB_D25

C11

FBB_D26

D11

FBB_D27

B11

FBB_D28

D8

FBB_D29

A8

FBB_D30

C8

FBB_D31

B8

FBB_D32

F24

FBB_D33

G23

FBB_D34

E24

FBB_D35

G24

FBB_D36

D21

FBB_D37

E21

FBB_D38

G21

FBB_D39

F21

FBB_D40

G27

FBB_D41

D27

FBB_D42

G26

FBB_D43

E27

FBB_D44

E29

FBB_D45

F29

FBB_D46

E30

FBB_D47

D30

FBB_D48

A32

FBB_D49

C31

FBB_D50

C32

FBB_D51

B32

FBB_D52

D29

FBB_D53

A29

FBB_D54

C29

FBB_D55

B29

FBB_D56

B21

FBB_D57

C23

FBB_D58

A21

FBB_D59

C21

FBB_D60

B24

FBB_D61

C24

FBB_D62

B26

FBB_D63

FBB_DBI[7..0]<3 1>

FBB_EDC[7..0]<31>

FBB_DBI0
FBB_DBI1
FBB_DBI2
FBB_DBI3
FBB_DBI4
FBB_DBI5
FBB_DBI6
FBB_DBI7

FBB_EDC0
FBB_EDC1
FBB_EDC2
FBB_EDC3
FBB_EDC4
FBB_EDC5
FBB_EDC6
FBB_EDC7

C26

E11

E3
A3

C9
F23
F27
C30
A24

D10

D5

C3

B9
E23
E28
B30
A23

D9

E4

B2

A9
D22
D28
A30
B23

FBB_D0
FBB_D1
FBB_D2
FBB_D3
FBB_D4
FBB_D5
FBB_D6
FBB_D7
FBB_D8
FBB_D9
FBB_D10
FBB_D11
FBB_D12
FBB_D13
FBB_D14
FBB_D15
FBB_D16
FBB_D17
FBB_D18
FBB_D19
FBB_D20
FBB_D21
FBB_D22
FBB_D23
FBB_D24
FBB_D25
FBB_D26
FBB_D27
FBB_D28
FBB_D29
FBB_D30
FBB_D31
FBB_D32
FBB_D33
FBB_D34
FBB_D35
FBB_D36
FBB_D37
FBB_D38
FBB_D39
FBB_D40
FBB_D41
FBB_D42
FBB_D43
FBB_D44
FBB_D45
FBB_D46
FBB_D47
FBB_D48
FBB_D49
FBB_D50
FBB_D51
FBB_D52

FBB_D53
FBB_D54
FBB_D55

FBB_D56
FBB_D57
FBB_D58
FBB_D59
FBB_D60
FBB_D61
FBB_D62
FBB_D63

FBB_DQM0
FBB_DQM1
FBB_DQM2
FBB_DQM3
FBB_DQM4

FBB_DQM5
FBB_DQM6
FBB_DQM7

FBB_DQS_WP0
FBB_DQS_WP1
FBB_DQS_WP2
FBB_DQS_WP3
FBB_DQS_WP4
FBB_DQS_WP5
FBB_DQS_WP6
FBB_DQS_WP7

FBB_DQS_RN0
FBB_DQS_RN1
FBB_DQS_RN2
FBB_DQS_RN3
FBB_DQS_RN4
FBB_DQS_RN5
FBB_DQS_RN6
FBB_DQS_RN7

Part 3 of 7

MEMORY INTERFACE B

FBB_CLK0_N

FBB_CLK1_N

FBB_WCK01

FBB_WCK01_N

FBB_WCK23

FBB_WCK23_N

FBB_WCK45

FBB_WCK45_N

FBB_WCK67

FBB_WCK67_N

FBB_WCKB01

FBB_WCKB01_N

FBB_WCKB23

FBB_WCKB23_N

FBB_WCKB45

FBB_WCKB45_N

FBB_WCKB67

FBB_WCKB67_N

FBB_PLL_AVDD

D

FBB_CMD0
FBB_CMD1
FBB_CMD2
FBB_CMD3
FBB_CMD4
FBB_CMD5
FBB_CMD6
FBB_CMD7
FBB_CMD8

FBB_CMD9
FBB_CMD10
FBB_CMD11
FBB_CMD12
FBB_CMD13
FBB_CMD14
FBB_CMD15
FBB_CMD16
FBB_CMD17
FBB_CMD18
FBB_CMD19
FBB_CMD20
FBB_CMD21
FBB_CMD22
FBB_CMD23
FBB_CMD24
FBB_CMD25
FBB_CMD26
FBB_CMD27
FBB_CMD28
FBB_CMD29
FBB_CMD30
FBB_CMD31
FBB_CMD32

FBB_CMD33

FBB_CMD34
FBB_CMD35

FBB_CLK0

FBB_CLK1

E

GDDR5 Mode H Mapping

FBB_CMD0

D13

FBB_CMD1

E14

FBB_CMD2

F14

FBB_CMD3

A12

FBB_CMD4

B12

FBB_CMD5

C14

FBB_CMD6

B14

FBB_CMD7

G15

FBB_CMD8

F15

FBB_CMD9

E15

FBB_CMD10

D15

FBB_CMD11

A14

FBB_CMD12

D14

FBB_CMD13

A15

FBB_CMD14

B15

FBB_CMD15

C17

FBB_CMD16

D18

FBB_CMD17

E18

FBB_CMD18

F18

FBB_CMD19

A20

FBB_CMD20

B20

FBB_CMD21

C18

FBB_CMD22

B18

FBB_CMD23

G18

FBB_CMD24

G17

FBB_CMD25

F17

FBB_CMD26

D16

FBB_CMD27

A18

FBB_CMD28

D17

FBB_CMD29

A17

FBB_CMD30

B17

FBB_CMD31

E17
G14

G20

FBB_DEBUG0

C12

FBB_DEBUG1

C20

FBB_CMD[31 ..0] <31>

TV2@

TV4@

Add res s

CMD0

CMD1

CMD2

CMD3

CMD4

CMD5

CMD6

CMD7

CMD8

CMD9

CMD10

CMD11

CMD12

CMD13

CMD14

CMD15

CMD16

CMD17

CMD18

CMD19

CMD20

D12
E12
E20
F20

F8
E8
A5
A6

D24

D25
B27
C27

D6
D7

C6
B6
F26
E26
A26
A27

H17

CV12

VGA@

Near
H17

0.1U_0201_10V6K

1

2

FBB_CLKA0 <3 1>
FBB_CLKA0# < 31>
FBB_CLKA1 <3 1>
FBB_CLKA1# < 31>

FBB_WCK 01 <31>
FBB_WCK 01# <31>
FBB_WCK 23 <31>
FBB_WCK 23# <31>
FBB_WCK 45 <31>
FBB_WCK 45# <31>
FBB_WCK 67 <31>
FBB_WCK 67# <31>

+FB_PLLAVDD

0.1U_0201_10V6K

1

CV7

VGA@

2

CMD21

CMD22

CMD23

CMD24

CMD25

CMD26

CMD27

CMD28

CMD29

CMD30

CMD31

DATA Bus

0..31 32..6 3

CS#

A3_BA 3

A2_BA 0

A4_BA 2

A5_BA 1

WE#

A7_A8

A6_A1 1

ABI#

A12_R FU

A0_A1 0

A1_A9

RAS#

RST#

CKE#

CAS#

CS#

A3_BA 3

A2_BA 0

A4_BA 2

A5_BA 1

WE#

A7_A8

A6_A1 1

ABI#

A12_R FU

A0_A1 0

A1_A9

RAS#

RST#

CKE#

CAS#

1

GP107-ES-A1_ BGA908

@

4

A

+GPU_PLLVD D

CV195

0.1U_0201_10V6K

CV124

0.1U_0201_10V6K

CV194

0.1U_0201_10V6K

1

VGA@

2

Near
H26

1

1

VGA@

VGA@

2

2

FBA_CMD14

RV87 10K_040 2_5%

FBA_CMD30

RV88 10K_040 2_5%

FBA_CMD13

RV89 10K_040 2_5%

FBA_CMD29

RV90 10K_040 2_5%

B

+1.35VSDGPU

12

VGA@

12

VGA@

12

VGA@

1

2

VGA@

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

GP107-ES-A1_ BGA908

@

+1.35VSDGPU

FBB_CMD14

CKE

FBB_CMD30

signal

FBB_CMD13

RST

FBB_CMD29

signal

Compal Secret Data

Compal Secret Data

2017/12/18 2018/09/01

2017/12/18 2018/09/01

2017/12/18 2018/09/01

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

12

VGA@

RV91 10K_040 2_5%

1

2

VGA@

RV92 10K_040 2_5%

1

2

VGA@

RV93 10K_040 2_5%

12

VGA@

RV94 10K_040 2_5%

D

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number R ev

Size Document Number R ev

Size Document Number R ev

Custom

Custom

Custom

Dat e: Sheet of

Dat e: Sheet of

Dat e: Sheet of

Compal Electronics, Inc.

N17P VRAM 2/7

N17P VRAM 2/7

N17P VRAM 2/7

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

E

26 67Thursday, Febru ary 22, 2018

26 67Thursday, Febru ary 22, 2018

26 67Thursday, Febru ary 22, 2018

4

1.0

1.0

1.0

A

B

C

D

E

UV1D

AL6

IFPA_L0

AK6

IFPA_L0_N

AN5

IFPA_L1

AM5

IFPA_L1_N

AP3

IFPA_L2

AN3

IFPA_L2_N

AM6

IFPA_L3

AN6

1

GPU_DP2_P 0<34>
GPU_DP2_N 0<34>
GPU_DP2_P 1<34>

HDMI

2.0

eDP

2 2

3 3

GPU_DP2_N 1<34>
GPU_DP2_P 2<34>
GPU_DP2_N 2<34>

GPU_DP2_P 3<34>

GPU_DP2_N 3<34>

GPU_EDP_T XP0<7>
GPU_EDP_T XN0<7>

GPU_EDP_T XP1<7>
GPU_EDP_T XN1<7>
GPU_EDP_T XP2<7>
GPU_EDP_T XN2<7>

GPU_EDP_T XP3<7>
GPU_EDP_T XN3<7>

GPU_DP2_C TRL_CLK<34>
GPU_DP2_C TRL_DAT<34>

GPU_EDP_AU XP<7>

GPU_EDP_AU XN<7>

IFPA_L3_N

AN8

IFPB_L0

AM8

IFPB_L0_N

AM7

IFPB_L1

AL7

IFPB_L1_N

AP6

IFPB_L2

AP5

IFPB_L2_N

AJ9

IFPB_L3

AH9

IFPB_L3_N

AK1

IFPC_L0

AJ1

IFPC_L0_N

AJ3

IFPC_L1

AJ2

IFPC_L1_N

AH3

IFPC_L2

AH4

IFPC_L2_N

AG5

IFPC_L3

AG4

IFPC_L3_N

AM1

IFPD_L0

AM2

IFPD_L0_N

AM3

IFPD_L1

AM4

IFPD_L1_N

AL3

IFPD_L2

AL4

IFPD_L2_N

AK4

IFPD_L3

AK5

IFPD_L3_N

AD2

IFPE_L0

AD3

IFPE_L0_N

AD1

IFPE_L1

AC1

IFPE_L1_N

AC2

IFPE_L2

AC3

IFPE_L2_N

AC4

IFPE_L3

AC5

IFPE_L3_N

AE3

IFPF_L0

AE4

IFPF_L0_N

AF4

IFPF_L1

AF5

IFPF_L1_N

AD4

IFPF_L2

AD5

IFPF_L2_N

AG1

IFPF_L3

AF1

IFPF_L3_N

AJ6

IFPA_AUX_SCL

AH6

IFPA_AUX_SDA_N

AK8

IFPB_AUX_SCL

AL8

IFPB_AUX_SCL_N

AG3

IFPC_AUX_SCL

AG2

IFPC_AUX_SDA_N

AK3

IFPD_AUX_SCL

AK2

IFPD_AUX_SDA_N

AB3

IFPE_AUX_SCL

AB4

IFPE_AUX_SDA_N

AF3

IFPF_AUX_SCL

AF2

IFPF_AUX_SDA_N

GP107-ES-A1_ BGA908

@

Part 4 of 7

LVDS/TMDS

NC

FB_VREF

VDD_SENSE

GND_SENSE

TES T

NVJTAG_SEL

JTAG_TCK

JTAG_TDI
JTAG_TDO
JTAG_TMS

JTAG_TRST_N

SERIAL

ROM_CS_N

ROM_SCLK

ROM_SI

ROM_SO

GENERAL

STRAP0
STRAP1
STRAP2
STRAP3
STRAP4

STRAP5

THERMDP
THERMDN

OVERT

MULTI LEVEL
STRAPS

strap3strap 2strap1strap0 strap5

2

RV29
100K_040 2_5%

X76@

1

2

RV37
100K_040 2_5%

@

1

strap4

For N17x

2

RV30
100K_040 2_5%

@

1

2

RV38
100K_040 2_5%

X76@

1

2

RV78
100K_040 2_5%

@

1

2

RV79
100K_040 2_5%

X76@

1

2

RV31
100K_040 2_5%

X76@

1

2

RV39
100K_040 2_5%

@

1

2

RV32
100K_040 2_5%

X76@

1

2

RV40
100K_040 2_5%

@

1

2

RV33
100K_040 2_5%

X76@

1

ROM_SI
ROM_SO
ROM_SCLK

2

RV41
100K_040 2_5%

@

1

STRAP0
STRAP1

STRAP2
STRAP3

STRAP4

STRAP5

+1.8VSDGPU_ AON

2

RV26
100K_040 2_5%

@

1

2

RV34
100K_040 2_5%

@

1

2

RV27
100K_040 2_5%

@

1

2

RV35
100K_040 2_5%

@

1

2

RV28
100K_040 2_5%

@

1

2

RV36
100K_040 2_5%

@

1

AC6

NC

AJ28

NC

AJ4

NC

AJ5

NC

AL11

NC

C15

NC

D19

NC

D20

NC

D23

NC

D26

NC

V32

NC

H31

VCCSENSE_VGA

L4

L5

AK11

AM10
AM11
AP12
AP11
AN11

H6
H4

H5

H7

M1

J2
J7
J6
J5
J3

J1

K3
K4

VSSSENSE_VGA

TESTMODE

ROM_SCLK
ROM_SI
ROM_SO

VGA_OVERT#

STRAP0
STRAP1

STRAP2

STRAP3
STRAP4
STRAP5

JTAG_TCK_VGA
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_RST

1 2

RV42 10K_0 402_5%VGA@

1

RV43 10K_0402_5%VGA@

VGA_OVERT# <25>

TV5@
TV6@
TV7@
TV8@

VCCSENSE_VGA <61>

VSSSENSE_VGA <61>

2

1

SMB_ATL_ADDR

LOW

High

DEVID_SEL

LOW

High

VGA_DEVICE

LOW

High

PCIE_CFG

LOW

High

Orig. Device ID

Support G-Sync GPUID

Single GPU

Dual GPU

3D Device

VGA Device

Normal signal swing

Reduce the signal amplitude

4

*

*

*

*

4

HDMI audio output

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2017/12/18 2018/09/01

2017/12/18 2018/09/01

2017/12/18 2018/09/01

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number R ev

Size Document Number R ev

Size Document Number R ev

Custom

Custom

Custom

Dat e: Sheet of

Dat e: Sheet

D

Dat e: Sheet

Compal Electronics, Inc.

N17P STRAP 3/7

N17P STRAP 3/7

N17P STRAP 3/7

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

E

1.0

1.0

27 67Thursday, Febru ary 22, 2018

27 67Thursday, Febru ary 22, 2018

27 67Thursday, Febru ary 22, 2018

1.0

of

of

A

+1.35VSDGPU

CHA
/6*1uF+2*1 0uF

CV18

VGA@

1

2 2

CHB
/6*1uF+2*1 0uF

CV126

VGA@

GPU
/5*22uF+2 *10uF

CV37

VGA@

CV217

@

1

1

2

1

2

1

2

1

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

10U_0603_6.3V6M

10U_0603_6.3V6M

CV19

VGA@

CV127

VGA@

CV38

VGA@

CV218

@

CV20

VGA@

2

1

1U_0402_6.3V6K

CV128

VGA@

2

1

10U_0603_6.3V6M

CV202

VGA@

2

1

10U_0603_6.3V6M

CV219

@

2

1

1U_0402_6.3V6K

CV21

VGA@

2

1

1U_0402_6.3V6K

CV129

VGA@

2

1

22U_0603_6.3V6M

CV36

VGA@

2

Place close to
GPU

1

22U_0603_6.3V6M

CV220

@

2

Under
GPU

1

1

2

1

2

1

2

1

2

1

1U_0402_6.3V6K

CV22

VGA@

2

1

1U_0402_6.3V6K

CV130

VGA@

2

1

22U_0603_6.3V6M

CV39

VGA@

2

1

22U_0603_6.3V6M

CV221

@

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

22U_0603_6.3V6M

22U_0603_6.3V6M

CV23

VGA@

CV131

VGA@

CV40

VGA@

CV222

@

CV24

VGA@

2

1

1U_0402_6.3V6K

CV132

VGA@

2

1

22U_0603_6.3V6M

CV41

VGA@

2

1

22U_0603_6.3V6M

CV223

@

2

near GPU for NV up date spec 1210

FB_VDDQ_SEN SE<59>

+1.35VSDGPU

3 3

1

RV47 40.2_ 0402_1%

VGA@

1 2

RV48 40.2_ 0402_1%VGA@

1

VGA@

RV49 60.4_0 402_1%

1

10U_0603_6.3V6M

CV26

VGA@

2

1

10U_0603_6.3V6M

CV133

VGA@

2

1

22U_0603_6.3V6M

2

1

22U_0603_6.3V6M

2

FB_VDDQ_SEN SE

2

2

B

1

2

1

2

+1.35VSDGPU

TV10@

10U_0603_6.3V6M

10U_0603_6.3V6M

2

RV45

@

0_0402_5 %

1

FB_GND_SEN SE

FB_CAL_PD_ VDDQ

FB_CAL_PU_ GND

FB_CAL_TER M_GND

AA27
AA30
AB27
AB33
AC27
AD27
AE27
AF27

AG27

UV1E

B13
B19
E13
E19

H10

H11
H12
H13
H14
H18
H19
H20
H21
H22
H23
H24

H8
H9

L27

M27

N27
P27
R27
T27
T30
T33
Y27

B16
E16
H15
H16

V27
W27
W30
W33

F1

F2

J27

H27

H25

@

Part 5 of 7

FBVDDQ_0
FBVDDQ_1
FBVDDQ_2
FBVDDQ_3
FBVDDQ_4
FBVDDQ_5
FBVDDQ_6
FBVDDQ_7
FBVDDQ_8
FBVDDQ_9
FBVDDQ_11
FBVDDQ_12
FBVDDQ_14

FBVDDQ_15

FBVDDQ_16
FBVDDQ_17
FBVDDQ_18
FBVDDQ_19
FBVDDQ_22
FBVDDQ_23
FBVDDQ_24
FBVDDQ_25
FBVDDQ_26
FBVDDQ_27
FBVDDQ_28
FBVDDQ_29
FBVDDQ_30
FBVDDQ_31
FBVDDQ_32
FBVDDQ_33
FBVDDQ_34
FBVDDQ_35
FBVDDQ_36
FBVDDQ_37
FBVDDQ_38
FBVDDQ_43

FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ

FB_VDDQ_SENSE

PROBE_FB_GND

FB_CAL_PD_VDDQ

FB_CAL_PU_GND

FB_CAL_TERM_GND

GP107-ES-A1_ BGA908

PEX_PLL_HVDD

POWER

IFPAB_PLLVDD

IFPCD_PLLVDD

IFPEF_PLLVDD

PEX_DVDD
PEX_DVDD
PEX_DVDD
PEX_DVDD
PEX_DVDD
PEX_DVDD

PEX_HVDD
PEX_HVDD
PEX_HVDD
PEX_HVDD

PEX_HVDD
PEX_HVDD
PEX_HVDD
PEX_HVDD
PEX_HVDD
PEX_HVDD
PEX_HVDD
PEX_HVDD
PEX_HVDD
PEX_HVDD

1V8_AON
1V8_AON

VDD18
VDD18

IFPAB_RSET

IFPCD_RSET

IFPEF_RSET

IFP_IOVDD
IFP_IOVDD
IFP_IOVDD
IFP_IOVDD
IFP_IOVDD
IFP_IOVDD

C

1*22uF+1*10uF+2*4 .7uF+4*1u F

AG19
AG21
AG22
AG24
AH21
AH25

AG13
AG15
AG16
AG18

AG25
AH15
AH18
AH26
AH27
AJ27
AK27
AL27
AM28

AN28

AH12

CV43

AG12

VGA@

NC

AG26

NC

AG7

NC

AN2

NC

J8
K8
L8
M8

AH8
AJ8

AF7
AF8

RG38 1K_0402_1%

AB8
AD6

RG182 1K_0402_ 1%

AG8
AG9
AG6
AF6
AC7
AC8

CV134

VGA@

0.1U_0201_10V6K

1

2

12

12

1

1U_0402_6.3V6K

CV13

VGA@

2

1*22uF+2*10uF+2*4 .7uF+4*1u F

CV137

VGA@

+1.8VSDGPU_ MAIN

Near
GPU

CV135

VGA@

Under
GPU

3*4.7uF+3*1uF+6* 0.1uF

Under
GPU

1

2

1

2

D

Near
GPU

4.7U_0402_6.3V6M

CV16

VGA@

Near
GPU

4.7U_0402_6.3V6M

1

2

+1.8VSDGPU_ AON

4.7U_0402_6.3V6M

0.1U_0201_10V6K

CV53

VGA@

0.1U_0201_10V6K

1

2

1

1U_0402_6.3V6K

CV205

VGA@

2

4.7U_0402_6.3V6M

1

CV28

VGA@

2

4.7U_0402_6.3V6M

1

CV30

CV32

VGA@

VGA@

2

2*4.7uF+1*1uF+2* 0.1uF

0.1U_0201_10V6K

1

CV54

VGA@

2

+GPU_PLLVD D

Under GPU
1 per ball

4.7U_0402_6.3V6M

1

CV204

VGA@

2

1

10U_0603_6.3V6M

2

1

2

1

1U_0402_6.3V6K

2

Near
GPU

4.7U_0402_6.3V6M

1

CV203

VGA@

2

1

1U_0402_6.3V6K

1U_0402_6.3V6K

CV33

CV14

VGA@

VGA@

2

Under
GPU

1U_0402_6.3V6K

1U_0402_6.3V6K

CV136

VGA@

1U_0402_6.3V6K

1

1

CV25

VGA@

2

2

1

1

1U_0402_6.3V6K

CV29

VGA@

2

2

1U_0402_6.3V6K

1

CV15

CV17

VGA@

VGA@

2

2*4.7uF+1*1uF+2* 0.1uF

0.1U_0201_10V6K

0.1U_0201_10V6K

1

CV49

VGA@

2

CV214

VGA@

1

1

CV51

VGA@

2

Near
GPU

Under
GPU

1

1U_0402_6.3V6K

CV213

VGA@

2

2

CV215

VGA@

1

1U_0402_6.3V6K

CV50

VGA@

2

1

CV52

VGA@

2

0.1U_0201_10V6K

1

CV216

VGA@

2

1

1U_0402_6.3V6K

CV212

VGA@

2

+1.0VSDGPU

1

22U_0603_6.3V6M
CV34

VGA@

2

+1.8VSDGPU_ MAIN

22U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

1

4.7U_0402_6.3V6M

2

4.7U_0402_6.3V6M

1

2

1

CV31

VGA@

2

+1.8VSDGPU_ MAIN

+1.0VSDGPU

CV27

VGA@

CV55

VGA@

1

2

E

1

Near
GPU

0.1U_0201_10V6K

0.1U_0201_10V6K

1

CV210

VGA@

4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2017/12/18 2018/09/01

2017/12/18 2018/09/01

2017/12/18 2018/09/01

1

CV211

CV209

VGA@

2

VGA@

2

Under GPU 1
per ball

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

0.1U_0201_10V6K

0.1U_0201_10V6K

1

1

CV208

CV207

VGA@

VGA@

2

2

0.1U_0201_10V6K

0.1U_0201_10V6K

1

1

CV206

VGA@

2

2

4

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number R ev

Size Document Number R ev

Size Document Number R ev

Custom

Custom

Custom

Dat e: Sheet of

Dat e: Sheet of

Dat e: Sheet of

Compal Electronics, Inc.

N17P POWER 4/7

N17P POWER 4/7

N17P POWER 4/7

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

E

1.0

1.0

28 67Thursday, Febru ary 22, 2018

28 67Thursday, Febru ary 22, 2018

28 67Thursday, Febru ary 22, 2018

1.0

A

N17P VDDS
1uF*5/4.7uF*5 (under GPU)
330uF*1/2 2uF*3/10 uF*2/4.7 uF*2

+VGA_CORE

1

2 2

3 3

+1.8VSDGPU_ AON

RG179

1.8VSDGPU_MAIN_E N<25 >

4

For Power down sequence

DGPU_PW R_EN<20>

1

@

10K_0402 _5%

0.1U_0201 _10V6K

2

+1.8V_AON/+1.8V_MAIN

DVT

+1.8VALW

1V8_AON_EN

+5VALW

+1.8VALW + 1.8VSDGPU_MAIN

1

CG337

VGA@

2

+1.8VALW

22U_0603_6.3V6M

CG339

1

VGA@

2

DV1

12

RB751S40 T1G_SOD523-2

VGA@

2

1

RV22

49.9K_040 2_5%

VGA@

1.0 Modify

A

UV1G

AA14

VDD_1

AA21

VDD_4

AB13

VDD_6

AB15

VDD_7

AB17

VDD_8

AB18

VDD_9

AB20

VDD_10

AB22

VDD_11

AC12

VDD_12

AC16

VDD_14

AC19

VDD_15

AC23

VDD_17

M12

VDD_18

M16

VDD_20

M19

VDD_21

M23

VDD_23

N13

VDD_24

N15

VDD_25

N17

VDD_26

N18

VDD_27

N20

VDD_28

N22

VDD_29

P14

VDD_31

P21

VDD_34

R13

VDD_36

R15

VDD_37

R17

VDD_38

R18

VDD_39

R20

VDD_40

R22

VDD_41

T12

VDD_42

T16

VDD_44

T19

VDD_45

T23

VDD_47

U13

VDD_48

U15

VDD_49

U18

VDD_51

U20

VDD_52

U22

VDD_53

V13

VDD_54

V15

VDD_55

V17

VDD_56

V20

VDD_58

V22

VDD_59

W12

VDD_60

W16

VDD_62

W19

VDD_63

W23

VDD_65

Y13

VDD_66

Y15

VDD_67

Y17

VDD_68

Y18

VDD_69

Y20

VDD_70

Y22

VDD_71

GP107-ES-A1_ BGA908

@

UG27

1

VIN1

2

VIN1

3

ON1

4

VBIAS

5

ON2

6

VIN2

7

VIN2

EM5209VF_D FN14_2X3

VGA@

1V8_AON_EN

1

CV35

0.1U_0201 _10V6K

2

VGA@

VOUT1
VOUT1

GND

VOUT2
VOUT2

GPAD

CT1

CT2

Part 7 of 7

14
13

12

11

10

9
8

15

B

VDDS
VDDS
VDDS
VDDS
VDDS
VDDS
VDDS
VDDS
VDDS
VDDS
VDDS
VDDS
VDDS
VDDS
VDDS
VDDS
VDDS
VDDS

VDDS_SENSE
GNDS_SENSE

XVDD

XVDD

XVDD

XVDD

XVDD
XVDD
XVDD
XVDD
XVDD
XVDD

POWER

XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD

XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD

XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD

CG335 220P_0402_ 50V8J

2

1

VGA@

CG336 220P_0402_ 50V8J

1 2

VGA@

VGA@

B

P23
P19
AA12
AA16
AA19
AA23
AC14
AC21
M14
M21
P12
P16
W21
W14
V18
U17
T21
T14

U1

NVVDD & NVVDDS merge

U2

confirm NV nc or not

U4
U5

U6
U7

U8
V1

V2

V3
V4
V5
V6
V7
V8
W2
W3
W4
W5
W7
W8

Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8

AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8

10U_0603_6.3V6M

CG338

1

2

+VGA_CORE

+VGA_CORE

+1.8VSDGPU_ AON

10U_0603_6.3V6M

1

VGA@

2

GPUCORE_E N<25>

C

+1.35VSDGPU

+5VS

2

RV115

100K_040 2_5%

VGA@

1

3

D

VGA@

5

G

5

G

S

4

QV11B
2N7002KD W_SOT363- 6

VGA@

+5VS

2

RV117

100K_040 2_5%

VGA@

1

3

D

5

G

S

4

QV10B
2N7002KD W_SOT363- 6

VGA@

+5VS

2

R214

1

GPUCORE_E N#

3

D

S

4

remove NVDDS discharge

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

1.35VSDGPU_ PWR_EN<25,59>

VGA_CORE_EN<25,61>

CG334

100K_040 2_5%

GPUCORE_E N

Q17B
2N7002KD W_SOT363- 6

VGA@

+1.35VSDGPU _R

1.35VSDGPU_ PWR_EN#

2N7002KD W_SOT363- 6

VGA@

RV118
20_0402_ 5%

+VGA_CORE_R

NVVDD_EN#

2N7002KD W_SOT363- 6

+1.0VSDGPU

2

VGA@

R39
20_0402_ 5%

1

6

D

2

Q17A

G

2N7002KD W_SOT363- 6

S

1

2

VGA@

RV116
20_0402_ 5%

1

6

D

2

G

S

1

QV11A

VGA@

+VGA_CORE

2

1

6

D

2

G

S

1

QV10A

VGA@

VGA@

Compal Secret Data

Compal Secret Data

2017/12/18 2018/09/01

2017/12/18 2018/09/01

2017/12/18 2018/09/01

Compal Secret Data

D

Deciphered Date

Deciphered Date

Deciphered Date

D

UV1F

A2

GND_0

AA17

GND_1

AA18

GND_2

AA20

GND_3

AA22

GND_4

AB12

GND_5

AB14

GND_6

AB16

GND_7

AB19

GND_8

AB2

GND_9

AB21

GND_10

A33

GND_11

AB23

GND_12

AB28

GND_13

AB30

GND_14

AB32

GND_15

AB5

GND_16

AB7

GND_17

AC13

GND_18

AC15

GND_19

AC17

GND_20

AC18

GND_21

AA13

GND_22

AC20

GND_23

AC22

GND_24

AE2

GND_25

AE28

GND_26

AE30

GND_27

AE32

GND_28

AE33

GND_29

AE5

GND_30

AE7

GND_31

AH10

GND_32

AA15

GND_33

AH13

GND_34

AH16

GND_35

AH19

GND_36

AH2

GND_37

AH22

GND_38

AH24

GND_39

AH28

GND_40

AH29

GND_41

AH30

GND_42

AH32

GND_43

AH33

GND_44

AH5

GND_45

AH7

GND_46

AJ7

GND_47

AK10

GND_48

AK7

GND_49

AL12

GND_50

AL14

GND_51

AL15

GND_52

AL17

GND_53

AL18

GND_54

AL2

GND_55

AL20

GND_56

AL21

GND_57

AL23

GND_58

AL24

GND_59

AL26

GND_60

AL28

GND_61

AL30

GND_62

AL32

GND_63

AL33

GND_64

AL5

GND_65

AM13

GND_66

AM16

GND_67

AM19

GND_68

AM22

GND_69

AM25

GND_70

AN1

GND_71

AN10

GND_72

AN13

GND_73

AN16

GND_74

AN19

GND_75

AN22

GND_76

AN25

GND_77

AN30

GND_78

AN34

GND_79

AN4

GND_80

AN7

GND_81

AP2

GND_82

AP33

GND_83

B1

GND_84

B10

GND_85

B22

GND_86

B25

GND_87

B28

GND_88

B31

GND_89

B34

GND_90

B4

GND_91

B7

GND_92

C10

GND_93

C13

GND_94

C19

GND_95

C22

GND_96

C25

GND_97

C28

GND_98

C7

GND_99

GP107-ES-A1_ BGA908

@

E

Part 6 of 7

GND

Size Document Number R ev

Size Document Number R ev

Size Document Number R ev

Custom

Custom

Custom

Dat e: Sheet of

Dat e: Sheet

Dat e: Sheet of

D2

GND_100

D31

GND_101

D33

GND_102

E10

GND_103

E22

GND_104

E25

GND_105

E5

GND_106

E7

GND_107

F28

GND_108

F7

GND_109

G10

GND_110

G13

GND_111

G16

GND_112

G19

GND_113

G2

GND_114

G22

GND_115

G25

GND_116

G28

GND_117

G3

GND_118

G30

GND_119

G32

GND_120

G33

GND_121

G5

GND_122

G7

GND_123

K2

GND_124

K28

GND_125

K30

GND_126

K32

GND_127

K33

GND_128

K5

GND_129

K7

GND_130

M13

GND_131

M15

GND_132

M17

GND_133

M18

GND_134

M20

GND_135

M22

GND_136

N12

GND_137

N14

GND_138

N16

GND_139

N19

GND_140

N2

GND_141

N21

GND_142

N23

GND_143

N28

GND_144

N30

GND_145

N32

GND_146

N33

GND_147

N5

GND_148

N7

GND_149

P13

GND_150

P15

GND_151

P17

GND_152

P18

GND_153

P20

GND_154

P22

GND_155

R12

GND_156

R14

GND_157

R16

GND_158

R19

GND_159

R21

GND_160

R23

GND_161

T13

GND_162

T15

GND_163

T17

GND_164

T18

GND_165

T2

GND_166

T20

GND_167

T22

GND_168

AG11

GND_169

T28

GND_170

T32

GND_171

T5

GND_172

T7

GND_173

U12

GND_174

U14

GND_175

U16

GND_176

U19

GND_177

U21

GND_178

U23

GND_179

V12

GND_180

V14

GND_181

V16

GND_182

V19

GND_183

V21

GND_184

V23

GND_185

W13

GND_186

W15

GND_187

W17

GND_188

W18

GND_189

W20

GND_190

W22

GND_191

W28

GND_192

Y12

GND_193

Y14

GND_194

Y16

GND_195

Y19

GND_196

Y21

GND_197

Y23

GND_198

AH11

GND_199

C16

GND_OPT

W32

GND_OPT

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Compal Electronics, Inc.

N17P POWER & GND 5/7

N17P POWER & GND 5/7

N17P POWER & GND 5/7

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

E

1.0

1.0

29 67Thursday, Febru ary 22, 2018

29 67Thursday, Febru ary 22, 2018

29 67Thursday, Febru ary 22, 2018

1.0

of

1

4

A

B

C

D

E

MF=1

FBA_D[63:0]<26 >

FBA_CMD6<26>
FBA_CMD11<26>
FBA_CMD10<26>
FBA_CMD7<26>
FBA_CMD9<26>

FBA_CMD2<26>

1

FBA_CMD4<26>
FBA_CMD3<26>
FBA_CMD1<26>

FBA_CMD8<26>
FBA_CMD12<26>
FBA_CMD0<26>
FBA_CMD15<26>
FBA_CMD5<26>

FBA_CLKA0< 26>
FBA_CLKA0#<26>
FBA_CMD14<26>

FBA_DBI0<2 6>
FBA_DBI1<2 6>
FBA_DBI2<2 6>
FBA_DBI3<2 6>

FBA_CMD13<26>

FBA_WCK0 1<26>
FBA_WCK0 1#<26>

FBA_WCK2 3<26>
FBA_WCK2 3#<26>

2 2

+1.35VSDGPU

1

1U_0402_6.3V6K

CV58

CV59

VGA@

VGA@

2

1

1U_0402_6.3V6K

CV141

CV142

VGA@

VGA@

3 3

CV161

VGA@

4

2

10U_0402_6.3V6M

1

CV85

CV84

VGA@

VGA@

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

CV160

VGA@

2

2

CV158

VGA@

1

VGA@

RV57
1K_0402_ 5%

2

1

1U_0402_6.3V6K

CV67

VGA@

2

1

1U_0402_6.3V6K

CV140

VGA@

2

1

10U_0402_6.3V6M

CV70

VGA@

2

1U_0402_6.3V6K

1

CV162

VGA@

2

FBA0_ZQ1

1

VGA@

RV58
121_0402 _1%

2

1

1U_0402_6.3V6K

CV56

VGA@

2

Close to
VRAM

1

1U_0402_6.3V6K

CV73

VGA@

2

Close to
VRAM

1

22U_0603_6.3V6M

CV71

VGA@

2

Around
VRAM

1U_0402_6.3V6K

1

CV163

VGA@

2

x32
only

1

1

1U_0402_6.3V6K

CV57

VGA@

2

2

10U_0603_6.3V6M

1

1

CV74

VGA@

2

2

1

1

22U_0603_6.3V6M

CV72

VGA@

2

2

1U_0402_6.3V6K

1

1

CV164

VGA@

2

2

UV4B

K4

A8/A7

H5

A9/A1

H4

A10/A0

K5

A11/A6

J5

A12/RFU#J5/NC#J5

H11

BA0/A2

K10

BA1/A5

K11

BA2/A4

H10

BA3/A3

J4

ABI#

G3

RAS#

G12

CS#

L3

CAS#

L12

WE#

J12

CK

J11

CK#

J3

CKE#

D2

DBI0#

D13

DBI1#

P13

DBI2#

P2

DBI3#

J2

RESET#

J10

SEN

J13

ZQ

J1

MF

D4

WCK01

D5

WCK01#

P4

WCK23

P5

WCK23#

1

X76@

VGA@

H5GC2H24 BFR-T2C_FBGA170

RV59
1K_0402_ 5%

2

1U_0402_6.3V6K

CV60

VGA@

10U_0402_6.3V6M

CV75

VGA@

22U_0603_6.3V6M

CV138

VGA@

1U_0402_6.3V6K

CV159

VGA@

MF=0

1

1U_0402_6.3V6K

2

10U_0603_6.3V6M

1

2

1

22U_0603_6.3V6M

2

1U_0402_6.3V6K

1

2

CV68

VGA@

CV76

VGA@

CV139

VGA@

CV165

VGA@

FBA1_VREFC

CV88

VGA@

2 OF 2

DQ0

DQ1

DQ2
DQ3

DQ4
DQ5
DQ6
DQ7
DQ8
DQ9

DQ10

DQ11

DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21

DQ22

DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30

DQ31

EDC0
EDC1
EDC2
EDC3

+1.35VSDGPU

1

820P_0402_50V7K

2

FBA_D56

A4

FBA_D57

A2

FBA_D58

B4

FBA_D59

B2

FBA_D60

E4

FBA_D61

E2

FBA_D62

F4

FBA_D63

F2

FBA_D48

A11

FBA_D49

A13

FBA_D50

B11

FBA_D51

B13

FBA_D52

E11

FBA_D53

E13

FBA_D54

F11

FBA_D55

F13

FBA_D40

U11

FBA_D41

U13

FBA_D42

T11

FBA_D43

T13

FBA_D44

N11

FBA_D45

N13

FBA_D46

M11

FBA_D47

M13

FBA_D32

U4

FBA_D33

U2

FBA_D34

T4

FBA_D35

T2

FBA_D36

N4

FBA_D37

N2

FBA_D38

M4

FBA_D39

M2

C2
C13
R13
R2

UV5A

C5

VDD

C10

VDD

D11

VDD

G1

VDD

G4

VDD

G11

VDD

G14

VDD

L1

VDD

L4

VDD

L11

VDD

L14

VDD

P11

VDD

R5

VDD

R10

VDD

B1

VDDQ

B3

VDDQ

B12

VDDQ

B14

VDDQ

D1

VDDQ

D3

VDDQ

D12

VDDQ

D14

VDDQ

E5

VDDQ

E10

VDDQ

F1

VDDQ

F3

VDDQ

F12

VDDQ

F14

VDDQ

G2

VDDQ

G13

VDDQ

H3

VDDQ

H12

VDDQ

K3

VDDQ

K12

VDDQ

L2

VDDQ

L13

VDDQ

M1

VDDQ

M3

VDDQ

M12

VDDQ

M14

VDDQ

N5

VDDQ

N10

VDDQ

P1

VDDQ

P3

VDDQ

P12

VDDQ

P14

VDDQ

T1

VDDQ

T3

VDDQ

T12

VDDQ

T14

VDDQ

J14

VREFC

A10

VREFD

U10

VREFD

X76@

H5GC2H24 BFR-T2C_FBGA170

1 OF 2

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

VSSQ

VSSQ

VPP/NC#A5
VPP/NC#U5

VSS

VSS
VSS
VSS
VSS
VSS

VSS

VSS

VSS

VSS
VSS

VSS
VSS
VSS

FBA_EDC7 < 26>
FBA_EDC6 < 26>
FBA_EDC5 < 26>

B5
B10
D10
G5
G10
H1

H14

K1

K14

L5
L10
P10

T5
T10

A1
A3
A12
A14
C1
C3
C4
C11
C12
C14
E1
E3
E12
E14
F5
F10
H2
H13
K2
K13
M5
M10
N1
N3
N12
N14
R1
R3
R4
R11
R12

R14

U1
U3

U12
U14

A5
U5

2 OF 2

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

EDC0
EDC1
EDC2
EDC3

1

1U_0402_6.3V6K

2

1

10U_0402_6.3V6M

2

1

22U_0603_6.3V6M

2

FBA0_VREFC

1U_0402_6.3V6K

1

CV89

VGA@

2

A4
A2
B4
B2
E4
E2
F4
F2
A11
A13
B11
B13
E11
E13
F11
F13
U11
U13
T11
T13
N11
N13
M11
M13
U4
U2
T4
T2
N4
N2
M4
M2

C2
C13
R13
R2

+1.35VSDGPU

1

820P_0402_50V7K

2

FBA_D0
FBA_D1
FBA_D2
FBA_D3
FBA_D4
FBA_D5
FBA_D6
FBA_D7
FBA_D8
FBA_D9
FBA_D10
FBA_D11
FBA_D12
FBA_D13

FBA_D14

FBA_D15

FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21

FBA_D22

FBA_D23

FBA_D24
FBA_D25
FBA_D26
FBA_D27

FBA_D28

FBA_D29
FBA_D30
FBA_D31

UV4A

C5

VDD

C10

VDD

D11

VDD

G1

VDD

G4

VDD

G11

VDD

G14

VDD

L1

VDD

L4

VDD

L11

VDD

L14

VDD

P11

VDD

R5

VDD

R10

VDD

B1

VDDQ

B3

VDDQ

B12

VDDQ

B14

VDDQ

D1

VDDQ

D3

VDDQ

D12

VDDQ

D14

VDDQ

E5

VDDQ

E10

VDDQ

F1

VDDQ

F3

VDDQ

F12

VDDQ

F14

VDDQ

G2

VDDQ

G13

VDDQ

H3

VDDQ

H12

VDDQ

K3

VDDQ

K12

VDDQ

L2

VDDQ

L13

VDDQ

M1

VDDQ

M3

VDDQ

M12

VDDQ

M14

VDDQ

N5

VDDQ

N10

VDDQ

P1

VDDQ

P3

VDDQ

P12

VDDQ

P14

VDDQ

T1

VDDQ

T3

VDDQ

T12

VDDQ

T14

VDDQ

J14

VREFC

A10

VREFD

U10

VREFD

X76@

H5GC2H24 BFR-T2C_FBGA170

FBA_VREFC_R

1

D

VRAM_VREF_CTL<25>

MESS138W -G_SOT323-3

FBA_EDC0 < 26>
FBA_EDC1 < 26>
FBA_EDC2 < 26>

FBA_EDC3 < 26> FBA_EDC4 < 26>

1 OF 2

B5

VSS

B10

VSS

D10

VSS

G5

VSS

G10

VSS

H1

VSS

H14

VSS

K1

VSS

K14

VSS

L5

VSS

L10

VSS

P10

VSS

T5

VSS

T10

VSS

A1

VSSQ

A3

VSSQ

A12

VSSQ

A14

VSSQ

C1

VSSQ

C3

VSSQ

C4

VSSQ

C11

VSSQ

C12

VSSQ

C14

VSSQ

E1

VSSQ

E3

VSSQ

E12

VSSQ

E14

VSSQ

F5

VSSQ

F10

VSSQ

H2

VSSQ

H13

VSSQ

K2

VSSQ

K13

VSSQ

M5

VSSQ

M10

VSSQ

N1

VSSQ

N3

VSSQ

N12

VSSQ

N14

VSSQ

R1

VSSQ

R3

VSSQ

R4

VSSQ

R11

VSSQ

R12

VSSQ

R14

VSSQ

U1

VSSQ

U3

VSSQ

U12

VSSQ

U14

VSSQ

A5

VPP/NC#A5

U5

VPP/NC#U5

2

VGA@

1.0 Modify

FBA_CLKA0

40.2_0402 _1%

FBA_CLKA1

40.2_0402 _1%

G

QV3

RV63

VGA@

0.01U_0402_16V7K

RV96

VGA@

0.01U_0402_16V7K

(3GHz and
up)

S

3

1

2

1

2

FBA_CLKA0#

1

RV95

40.2_0402 _1%

VGA@

2

1

VGA@

CV190

2

FBA_CLKA1#

1

RV62

40.2_0402 _1%

VGA@

2

1

VGA@

CV191

2

RV51
931_0402 _1%

1

VGA@

RV54
931_0402 _1%

1 2

VGA@

+1.35VSDGPU

1

RV50
549_0402 _1%

VGA@

2

2

1

RV52

1.33K_040 2_1%

VGA@

2

+1.35VSDGPU

1

RV53
549_0402 _1%

VGA@

2

1

RV56

1.33K_040 2_1%

VGA@

2

FBA0_VREFC

FBA1_VREFC

+1.35VSDGPU

CV166

VGA@

1

2

CV61

VGA@

CV77

VGA@

CV86

VGA@

1U_0402_6.3V6K

CV168

VGA@

FBA_CMD26<26>
FBA_CMD23<26>
FBA_CMD22<26>
FBA_CMD27<26>
FBA_CMD25<26>

FBA_CMD19<26>
FBA_CMD17<26>
FBA_CMD18<26>
FBA_CMD20<26>

FBA_CMD24<26>
FBA_CMD31<26>
FBA_CMD21<26>
FBA_CMD28<26>
FBA_CMD16<26>

FBA_CLKA1< 26>
FBA_CLKA1#<26>
FBA_CMD30<26>

FBA_DBI7<2 6>
FBA_DBI6<2 6>
FBA_DBI5<2 6>
FBA_DBI4<2 6>

FBA_CMD29<26>

+1.35VSDGPU

FBA_WCK6 7<26>
FBA_WCK6 7#<26>

FBA_WCK4 5<26>
FBA_WCK4 5#<26>

1

1

1U_0402_6.3V6K

1U_0402_6.3V6K

CV63

CV62

VGA@

VGA@

2

2

1

1

1U_0402_6.3V6K

1U_0402_6.3V6K

CV78

CV79

VGA@

VGA@

2

2

10U_0603_6.3V6M

10U_0603_6.3V6M

1

1

CV143

CV87

VGA@

VGA@

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

2

CV167

VGA@

CV170

VGA@

2

1

2

Close to
VRAM

1

2

Close to
VRAM

1

2

1U_0402_6.3V6K

1U_0402_6.3V6K

22U_0603_6.3V6M

Around
VRAM

RV55

VGA@

1K_0402_ 5%

1

VGA@

RV60

1K_0402_ 5%

1

1U_0402_6.3V6K

CV65

CV64

VGA@

VGA@

2

1

10U_0402_6.3V6M

CV81

CV80

VGA@

VGA@

2

1

22U_0603_6.3V6M

CV145

CV144

VGA@

VGA@

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

CV172

CV169

VGA@

VGA@

2

2

x32
only

FBA1_ZQ3

2

1

1

2

2

1

1

1U_0402_6.3V6K

CV66

VGA@

2

2

1

1

10U_0402_6.3V6M

CV82

VGA@

2

2

1

1

22U_0603_6.3V6M

CV147

VGA@

2

2

1U_0402_6.3V6K

1

CV171

VGA@

2

VGA@

RV61
121_0402 _1%

1U_0402_6.3V6K

CV69

VGA@

10U_0603_6.3V6M

CV83

VGA@

22U_0603_6.3V6M

CV146

VGA@

1U_0402_6.3V6K

1

CV173

VGA@

2

UV5B

K4

A8/A7

H5

A9/A1

H4

A10/A0

K5

A11/A6

J5

A12/RFU#J5/NC#J5

H11

BA0/A2

K10

BA1/A5

K11

BA2/A4

H10

BA3/A3

J4

ABI#

G3

RAS#

G12

CS#

L3

CAS#

L12

WE#

J12

CK

J11

CK#

J3

CKE#

D2

DBI0#

D13

DBI1#

P13

DBI2#

P2

DBI3#

J2

RESET#

J10

SEN

J13

ZQ

J1

MF

D4

WCK01

D5

WCK01#

P4

WCK23

P5

WCK23#

X76@

H5GC2H24 BFR-T2C_FBGA170

1

1U_0402_6.3V6K

2

10U_0603_6.3V6M

1

2

1

22U_0603_6.3V6M

2

1U_0402_6.3V6K

1

2

1

4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2017/12/18 2018/09/01

2017/12/18 2018/09/01

2017/12/18 2018/09/01

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number R ev

Size Document Number R ev

Size Document Number R ev

Custom

Custom

Custom

Dat e: Sheet

Dat e: Sheet

D

Dat e: Sheet

Compal Electronics, Inc.

N17P GDDR5 CHA 6/7

N17P GDDR5 CHA 6/7

N17P GDDR5 CHA 6/7

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

E

1.0

1.0

1.0

of

30 67Thursday, Febru ary 22, 2018

30 67Thursday, Febru ary 22, 2018

of

30 67Thursday, Febru ary 22, 2018

of

A

B

C

D

E

MF=1

RV65
931_0402 _1%

1 2

VGA@

RV68
931_0402 _1%

1

VGA@

+1.35VSDGPU

1

RV64
549_0402 _1%

VGA@

2

1

RV66

1.33K_040 2_1%

VGA@

2

+1.35VSDGPU

1

RV67
549_0402 _1%

VGA@

2

2

1

RV70

1.33K_040 2_1%

VGA@

2

+1.35VSDGPU

CV182

VGA@

FBB0_VREFC

FBB1_VREFC

CV90

VGA@

CV104

VGA@

CV118

VGA@

1

2

FBB_CMD26<26>
FBB_CMD23<26>
FBB_CMD22<26>
FBB_CMD27<26>
FBB_CMD25<26>

FBB_CMD19<26>
FBB_CMD17<26>
FBB_CMD18<26>
FBB_CMD20<26>

FBB_CMD24<26>

FBB_CMD31<26>
FBB_CMD21<26>
FBB_CMD28<26>
FBB_CMD16<26>

FBB_CLKA1< 26>

FBB_CLKA1#<26>

FBB_CMD30<26>

FBB_DBI7<2 6>
FBB_DBI6<2 6>
FBB_DBI5<2 6>
FBB_DBI4<2 6>

FBB_CMD29<26>

FBB_WCK 67<26>
FBB_WCK 67#<26>

FBB_WCK 45<26>
FBB_WCK 45#<26>

1

1U_0402_6.3V6K

CV94

VGA@

2

1

1U_0402_6.3V6K

CV105

VGA@

2

10U_0603_6.3V6M

1

CV119

VGA@

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

CV184

VGA@

2

CV183

VGA@

1

1

1U_0402_6.3V6K

CV96

VGA@

2

2

1

1

1U_0402_6.3V6K

CV106

VGA@

2

2

10U_0603_6.3V6M

1

1

CV153

VGA@

2

2

1U_0402_6.3V6K

1

CV185

VGA@

2

+1.35VSDGPU

1U_0402_6.3V6K

CV97

VGA@

Close to
VRAM

1U_0402_6.3V6K

CV174

VGA@

Close to
VRAM

22U_0603_6.3V6M

CV155

VGA@

Around
VRAM

1U_0402_6.3V6K

1

2

CV186

VGA@

x32
only

RV69
1K_0402_ 5%

1

1K_0402_ 5%

1

1U_0402_6.3V6K

2

1

10U_0402_6.3V6M

2

1

22U_0603_6.3V6M

2

2

VGA@

1

1

VGA@

RV71

CV91

VGA@

CV108

VGA@

CV154

VGA@

1U_0402_6.3V6K

1

CV188

VGA@

2

2

2

1

1

1U_0402_6.3V6K

CV95

VGA@

2

2

10U_0603_6.3V6M

1

1

CV109

VGA@

2

2

1

1

22U_0603_6.3V6M

CV156

VGA@

2

2

1U_0402_6.3V6K

1

CV187

VGA@

2

FBB_D[63:0]<26 >

FBB_CMD6<26>
FBB_CMD11<26>
FBB_CMD10<26>
FBB_CMD7<26>
FBB_CMD9<26>

1

FBB_CMD2<26>
FBB_CMD4<26>
FBB_CMD3<26>
FBB_CMD1<26>

FBB_CMD8<26>
FBB_CMD12<26>
FBB_CMD0<26>
FBB_CMD15<26>
FBB_CMD5<26>

FBB_CLKA0< 26>
FBB_CLKA0#<26>
FBB_CMD14<26>

FBB_DBI0<2 6>
FBB_DBI1<2 6>
FBB_DBI2<2 6>
FBB_DBI3<2 6>

FBB_CMD13<26>

FBB_WCK 01<26>
FBB_WCK 01#<26>

FBB_WCK 23<26>
FBB_WCK 23#<26>

2 2

+1.35VSDGPU

1

1U_0402_6.3V6K
CV99

VGA@

2

1

1U_0402_6.3V6K
CV111

VGA@

2

3 3

10U_0603_6.3V6M

1

CV120

VGA@

2

1U_0402_6.3V6K

1

CV107

VGA@

4

1

CV176

VGA@

2

2

CV100

VGA@

CV112

VGA@

CV121

VGA@

1U_0402_6.3V6K

CV175

VGA@

1

2

1

1U_0402_6.3V6K

CV101

VGA@

2

1

1U_0402_6.3V6K

CV113

VGA@

2

10U_0603_6.3V6M

1

CV148

VGA@

2

1U_0402_6.3V6K

1

2

VGA@

RV73
1K_0402_ 5%

1

1U_0402_6.3V6K

2

Close to
VRAM

1

1U_0402_6.3V6K

CV114

2

Close to
VRAM

1

22U_0603_6.3V6M

2

Around
VRAM

1

CV177

VGA@

2

CV92

VGA@

VGA@

CV149

VGA@

1U_0402_6.3V6K

FBB0_ZQ1

1

VGA@

RV74
121_0402 _1%

2

1

2

1

2

1

2

CV178

VGA@

x32
only

1U_0402_6.3V6K

10U_0603_6.3V6M

22U_0603_6.3V6M

CV115

1

2

CV93

VGA@

VGA@

CV150

VGA@

1U_0402_6.3V6K

CV180

VGA@

1

VGA@

RV75
1K_0402_ 5%

2

1

1U_0402_6.3V6K

2

10U_0603_6.3V6M

1

2

1

22U_0603_6.3V6M

2

1

2

UV6B

K4

A8/A7

H5

A9/A1

H4

A10/A0

K5

A11/A6

J5

A12/RFU#J5/NC#J5

H11

BA0/A2

K10

BA1/A5

K11

BA2/A4

H10

BA3/A3

J4

ABI#

G3

RAS#

G12

CS#

L3

CAS#

L12

WE#

J12

CK

J11

CK#

J3

CKE#

D2

DBI0#

D13

DBI1#

P13

DBI2#

P2

DBI3#

J2

RESET#

J10

SEN

J13

ZQ

J1

MF

D4

WCK01

D5

WCK01#

P4

WCK23

P5

WCK23#

X76@

H5GC2H24 BFR-T2C_FBGA170

1

1U_0402_6.3V6K

CV102

VGA@

2

1

10U_0402_6.3V6M
CV116

VGA@

2

1

22U_0603_6.3V6M
CV152

VGA@

2

1U_0402_6.3V6K

1

CV179

VGA@

2

MF=0

CV103

VGA@

CV117

VGA@

CV151

VGA@

1U_0402_6.3V6K

CV181

VGA@

2 OF 2

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

EDC0
EDC1
EDC2
EDC3

1

1U_0402_6.3V6K

2

1

10U_0402_6.3V6M

2

1

22U_0603_6.3V6M

2

1U_0402_6.3V6K

1

FBB0_VREFC

2

CV123

VGA@

A4
A2
B4
B2
E4
E2
F4
F2
A11
A13
B11
B13
E11
E13
F11
F13
U11
U13
T11
T13
N11
N13
M11
M13
U4
U2
T4
T2
N4
N2
M4

M2

C2
C13
R13
R2

+1.35VSDGPU

1

820P_0402_50V7K

2

FBB_D0
FBB_D1

FBB_D2
FBB_D3
FBB_D4
FBB_D5
FBB_D6
FBB_D7
FBB_D8
FBB_D9

FBB_D10
FBB_D11
FBB_D12
FBB_D13
FBB_D14
FBB_D15

FBB_D16
FBB_D17
FBB_D18
FBB_D19

FBB_D20
FBB_D21

FBB_D22

FBB_D23

FBB_D24
FBB_D25
FBB_D26

FBB_D27

FBB_D28
FBB_D29
FBB_D30
FBB_D31

UV6A

C5

VDD

C10

VDD

D11

VDD

G1

VDD

G4

VDD

G11

VDD

G14

VDD

L1

VDD

L4

VDD

L11

VDD

L14

VDD

P11

VDD

R5

VDD

R10

VDD

B1

VDDQ

B3

VDDQ

B12

VDDQ

B14

VDDQ

D1

VDDQ

D3

VDDQ

D12

VDDQ

D14

VDDQ

E5

VDDQ

E10

VDDQ

F1

VDDQ

F3

VDDQ

F12

VDDQ

F14

VDDQ

G2

VDDQ

G13

VDDQ

H3

VDDQ

H12

VDDQ

K3

VDDQ

K12

VDDQ

L2

VDDQ

L13

VDDQ

M1

VDDQ

M3

VDDQ

M12

VDDQ

M14

VDDQ

N5

VDDQ

N10

VDDQ

P1

VDDQ

P3

VDDQ

P12

VDDQ

P14

VDDQ

T1

VDDQ

T3

VDDQ

T12

VDDQ

T14

VDDQ

J14

A10
U10

VPP/NC#A5

VREFC

VPP/NC#U5

VREFD
VREFD

X76@

H5GC2H24 BFR-T2C_FBGA170

VRAM_VREF_CTL<25>

FBB_EDC0 < 26>
FBB_EDC1 < 26>
FBB_EDC2 < 26>
FBB_EDC3 < 26>

1 OF 2

B5

VSS

B10

VSS

D10

VSS

G5

VSS

G10

VSS

H1

VSS

H14

VSS

K1

VSS

K14

VSS

L5

VSS

L10

VSS

P10

VSS

T5

VSS

T10

VSS

A1

VSSQ

A3

VSSQ

A12

VSSQ

A14

VSSQ

C1

VSSQ

C3

VSSQ

C4

VSSQ

C11

VSSQ

C12

VSSQ

C14

VSSQ

E1

VSSQ

E3

VSSQ

E12

VSSQ

E14

VSSQ

F5

VSSQ

F10

VSSQ

H2

VSSQ

H13

VSSQ

K2

VSSQ

K13

VSSQ

M5

VSSQ

M10

VSSQ

N1

VSSQ

N3

VSSQ

N12

VSSQ

N14

VSSQ

R1

VSSQ

R3

VSSQ

R4

VSSQ

R11

VSSQ

R12

VSSQ

R14

VSSQ

U1

VSSQ

U3

VSSQ

U12

VSSQ

U14

VSSQ

A5
U5

MESS138W -G_SOT323-3

VGA@

1.0 Modify

40.2_0402 _1%

40.2_0402 _1%

2

G

QV4

RV76

VGA@

RV97

VGA@

(3GHz and
up)

FBB_VREFC_R

1

D

S

3

1

2

0.01U_0402_16V7K

1

2

VGA@

1

2

0.01U_0402_16V7K

1

2

VGA@

FBB_CLKA0#FBB_ CLKA0

1

RV77

40.2_0402 _1%

VGA@

2

CV193

FBB_CLKA1#FBB_ CLKA1

1

RV98

40.2_0402 _1%

VGA@

2

CV192

FBB1_ZQ3

VGA@

RV72
121_0402 _1%

1U_0402_6.3V6K

CV98

VGA@

10U_0402_6.3V6M

CV110

VGA@

22U_0603_6.3V6M

CV157

VGA@

1U_0402_6.3V6K

1

CV189

VGA@

2

UV7B

K4

A8/A7

H5

A9/A1

H4

A10/A0

K5

A11/A6

J5

A12/RFU#J5/NC#J5

H11

BA0/A2

K10

BA1/A5

K11

BA2/A4

H10

BA3/A3

J4

ABI#

G3

RAS#

G12

CS#

L3

CAS#

L12

WE#

J12

CK

J11

CK#

J3

CKE#

D2

DBI0#

D13

DBI1#

P13

DBI2#

P2

DBI3#

J2

RESET#

J10

SEN

J13

ZQ

J1

MF

D4

WCK01

D5

WCK01#

P4

WCK23

P5

WCK23#

X76@

H5GC2H24 BFR-T2C_FBGA170

1

1U_0402_6.3V6K

2

10U_0603_6.3V6M

1

2

1

22U_0603_6.3V6M

2

1U_0402_6.3V6K

1

2

+1.35VSDGPU

FBB1_VREFC

CV122

VGA@

2 OF 2

DQ0
DQ1

DQ2

DQ3
DQ4
DQ5
DQ6
DQ7
DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

EDC0
EDC1
EDC2
EDC3

1

820P_0402_50V7K

2

FBB_D56

A4

FBB_D57

A2

FBB_D58

B4

FBB_D59

B2

FBB_D60

E4

FBB_D61

E2

FBB_D62

F4

FBB_D63

F2

FBB_D48

A11

FBB_D49

A13

FBB_D50

B11

FBB_D51

B13

FBB_D52

E11

FBB_D53

E13

FBB_D54

F11

FBB_D55

F13

FBB_D40

U11

FBB_D41

U13

FBB_D42

T11

FBB_D43

T13

FBB_D44

N11

FBB_D45

N13

FBB_D46

M11

FBB_D47

M13

FBB_D32

U4

FBB_D33

U2

FBB_D34

T4

FBB_D35

T2

FBB_D36

N4

FBB_D37

N2

FBB_D38

M4

FBB_D39

M2

C2
C13
R13
R2

UV7A

C5

VDD

C10

VDD

D11

VDD

G1

VDD

G4

VDD

G11

VDD

G14

VDD

L1

VDD

L4

VDD

L11

VDD

L14

VDD

P11

VDD

R5

VDD

R10

VDD

B1

VDDQ

B3

VDDQ

B12

VDDQ

B14

VDDQ

D1

VDDQ

D3

VDDQ

D12

VDDQ

D14

VDDQ

E5

VDDQ

E10

VDDQ

F1

VDDQ

F3

VDDQ

F12

VDDQ

F14

VDDQ

G2

VDDQ

G13

VDDQ

H3

VDDQ

H12

VDDQ

K3

VDDQ

K12

VDDQ

L2

VDDQ

L13

VDDQ

M1

VDDQ

M3

VDDQ

M12

VDDQ

M14

VDDQ

N5

VDDQ

N10

VDDQ

P1

VDDQ

P3

VDDQ

P12

VDDQ

P14

VDDQ

T1

VDDQ

T3

VDDQ

T12

VDDQ

T14

VDDQ

J14

A10
U10

VPP/NC#A5

VREFC

VPP/NC#U5

VREFD
VREFD

X76@

H5GC2H24 BFR-T2C_FBGA170

1 OF 2

VSS
VSS
VSS
VSS
VSS

VSS

VSS

VSS

VSS
VSS

VSS
VSS
VSS

VSS

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

VSSQ

VSSQ

VSSQ

FBB_EDC7 < 26>
FBB_EDC6 < 26>
FBB_EDC5 < 26>
FBB_EDC4 < 26>

B5
B10
D10
G5
G10

H1

H14

K1

K14
L5
L10

P10
T5

T10

A1
A3
A12
A14
C1
C3
C4
C11
C12
C14
E1
E3
E12
E14
F5
F10
H2
H13
K2
K13
M5
M10
N1
N3
N12
N14
R1
R3
R4
R11

R12

R14
U1

U3
U12

U14

A5
U5

1

4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2017/12/18 2018/09/01

2017/12/18 2018/09/01

2017/12/18 2018/09/01

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number R ev

Size Document Number R ev

Size Document Number R ev

Custom

Custom

Custom

Dat e: Sheet

Dat e: Sheet

D

Dat e: Sheet

Compal Electronics, Inc.

N17P GDDR5 CHB 7/7

N17P GDDR5 CHB 7/7

N17P GDDR5 CHB 7/7

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

E

1.0

1.0

1.0

of

31 67Thursday, Febru ary 22, 2018

31 67Thursday, Febru ary 22, 2018

of

31 67Thursday, Febru ary 22, 2018

of

A

remove GPAK circuit for improve HDMI layout (1.0)

B

C

D

E

1

2 2

3

1

3

4 4

Security Classification

Security Classification

Security Classification

2017/12 /18 2018/09 /01

2017/12 /18 2018/09 /01

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

A

B

2017/12 /18 2018/09 /01

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

Dat e: Sheet o f

Dat e: Sheet o f

D

Dat e: Sheet o f

Compal Electronics, Inc.

N17P G-Pak sequence 8/8

N17P G-Pak sequence 8/8

N17P G-Pak sequence 8/8

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

E

1.0

1.0

1.0

32 67Thursday, Febru ary 22, 2018

32 67Thursday, Febru ary 22, 2018

32 67Thursday, Febru ary 22, 2018

A

LCD POWER CIRCUIT

1

RX1
100K_0 402_5%

2

EDP_HPD<17,25>

UX1

5

4

SY6288C2 0AAC_SOT23 -5

PCH_BK L_PWM

BKOFF#

+5VS

CX2

1U_0402_6.3V6K

1

2 2

3

1

2

PCH_EN VDD<18,25>

PCH_BK L_PWM< 18,25>

BKOFF#<39>

Camera

USB20_ N5<15 >

USB20_ P5<1 5>

CO-LAY FOR VGA OUTPUT

+3VS

4 4

B

1

OUT

IN

EN

2

GND

3

OC

RX3
0_0402 _5%

1 2

@

RX10 100 K_0402_5%

CX9 220P_ 0402_50V7K

CX10 220 P_0402_50V 7K

RX5 10K_ 0402_5%@

USB Touch Screen

+3VS

1 2

RX6 0_06 03_5%@

1 2

RX7 0_06 03_5%

USB20_ N5

USB20_ P5

1 2

RG196 100K_0 201_5%@

1 2

RG197 100K_0 201_5%@

1 2

RG198 100K_0 201_5%@

1

RG199 100K_0 201_5%@

1

2

1 2

@

XEMC@

1 2

XEMC@

1 2

1 2

1 2

RX8 0_04 02_5%@

1 2

RX9 0_04 02_5%@

2

W=60mils

1

CX3

10U_06 03_6.3V6M

2

EDP_HP D_R

RX4
100K_0 402_5%

+TS_PW R

1

2

EDP_AU XN_C
EDP_AU XP_C

EDP_AU XN
EDP_AU XP

W=60mils W=60mils

CX4

0.1U_02 01_10V6K

@

USB20_ N5_CAMERA

USB20_ P5_CAMERA

C

SM01000EJ00 3000ma
220 ohm @10 0mh z

DCR 0.04

LX1

EMC@

HCB201 2KF-221T30_ 0805

1 2

68P_04 02_50V8J

EDP_AUXN<7>

EDP_AUXP<7>

EDP_TXP0<7>

EDP_TXN0<7>

EDP_TXP1<7>

EDP_TXN1<7>

EDP_TXP2<7>

EDP_TXN2<7>

EDP_TXP3<7>

EDP_TXN3<7>

XEMC@

CX5

+INVPW R_B++19VB_ CPU+LCDVD D+3VS

1

1

2

EDP_AU XN
EDP_AU XP

EDP_TX P0
EDP_TX N0

EDP_TX P1
EDP_TX N1

EDP_TX P2
EDP_TX N2

EDP_TX P3
EDP_TX N3

Touch
Scree n

For
Camera

CX6
1000P_ 0402_50V7K

EMC@

2

CX20 0.1U_0201_10 V6K
CX19 0.1U_0201_10 V6K

CX11 0.1U_0201_10 V6K
CX12 0.1U_0201_10 V6K

CX13 0.1U_0201_10 V6K

CX14 0.1U_0201_10 V6K

CX15 0.1U_0201_10 V6K
CX16 0.1U_0201_10 V6K

CX17 0.1U_0201_10 V6K
CX18 0.1U_0201_10 V6K

1 2
1 2

1
1 2

1

1

1
1 2

1
1 2

D

E

Place closed to

0.1U_0201_10V6K

+LCDVD D

1

@

CX8

0.1U_02 01_10V6K

2

1

CX1

10U_06 03_6.3V6M

2

CX7

JEDP1

+3VS

1

2

LED PANEL Conn.

+INVPW R_B+

+LCDVD D

2

2
2

2

2

USB20_ P6<1 5>

USB20_ N6<15 >

+TS_PW R

TS_EN<20,39>

+3VS

DMIC_CLK _R<3 8>
DMIC_DAT A_R<38>

DMIC_CLK _R

DMIC_DAT A_R

2

3

DX1
YSLC05CH _SOT23-3

XEMC@

1

W=60mils

PCH_BK L_PWM
BKOFF#

EDP_HP D_R

EDP_AU XN_C
EDP_AU XP_C

EDP_TX P0_C
EDP_TX N0_C

EDP_TX P1_C

EDP_TX N1_C

EDP_TX P2_C
EDP_TX N2_C

EDP_TX P3_C
EDP_TX N3_C

USB20_ P6
USB20_ N6

TS_EN

USB20_ N5_CAMERA
USB20_ P5_CAMERA

DMIC_CLK _R
DMIC_DAT A_R

JEDP1

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

21

22

22

23

23

24

24

25

25

26

26

27

27

28

28

29

29

30

30

31

31

32

32

33

33

34

34

35

35

36

36

G1

37

G2

37

38

38

G3

39

G4

39

40

40

G5

ACES_5 0398-04041-0 01

CONN@

SP010013I00

41
42
43
44
45

1

3

Security Classification

Security Classification

Security Classification

2017/12 /18 2018/09 /01

2017/12 /18 2018/09 /01

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

A

B

2017/12 /18 2018/09 /01

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number R ev

Size Document Number R ev

Size Document Number R ev

Custom

Custom

Custom

Dat e: Sheet o f

Dat e: Sheet o f

D

Dat e: Sheet o f

Compal Electronics, Inc.

eDP CONN.

eDP CONN.

eDP CONN.

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

E

1.0

1.0

1.0

33 67Thursday, Febru ary 22, 2018

33 67Thursday, Febru ary 22, 2018

33 67Thursday, Febru ary 22, 2018

A

1 2

GPU_DP 2_P3<27>

1

2 2

3

HDMI_HPD _PCH<17 ,25>

GPU_DP 2_N3<27>

GPU_DP 2_P2<27>
GPU_DP 2_N2<27>

GPU_DP 2_P1<27>
GPU_DP 2_N1<27>

GPU_DP 2_P0<27>
GPU_DP 2_N0<27>

HDMI_CLK P HDMI_R_C LKP

CY26

XEMC@

3.3P_04 02_50V8

HDMI_CLK N

HDMI_TX_ P0 HD MI_R_TX_P0

HDMI_TX_ N0 HDMI_R_T X_N0

HDMI_TX_ P1 HD MI_R_TX_P1

HDMI_TX_ N1

HDMI_TX_ P2 HD MI_R_TX_P2

HDMI_TX_ N2

2

RY24

1M_040 2_5%

1

CY22 .1U_0 402_16V7K
CY24 .1U_0 402_16V7K

CY16 .1U_0 402_16V7K
CY17 .1U_0 402_16V7K

CY18 .1U_0 402_16V7K
CY19 .1U_0 402_16V7K

CY20 .1U_0 402_16V7K
CY21 .1U_0 402_16V7K

1 2

RY15 6.04_ 0402_1%

2

1

1 2

RY14 6.04_ 0402_1%

1

RY16 6.04_ 0402_1%

1

RY17

1 2

RY18

1 2

RY19 6.04_ 0402_1%

1 2

RY20 6.04_ 0402_1%

1 2

RY22

+3VS+3VS

2

G

QY2A

2N7002 KDW_SOT 363-6

S

6

1

D

1

1 2
1 2

1 2
1 2

1 2
1 2

2

RY11 design guide rev2.0 use 20K pull down.

1

+1.8VSD GPU_AON

5

QY1A

4 4

GPU_DP 2_CTRL_CLK< 27>

GPU_DP 2_CTRL_DAT<27 >

PJT138 KA_SOT363-6

G

3

4

S

D

PJT138 KA_SOT363-6

QY1B

2

G

61

S

D

3ohm/10pF

A

2

2

2

6.04_04 02_1%

6.04_04 02_1%

6.04_04 02_1%

HDMI_HPD

RY11

100K_0 402_5%

HDMI_CTR L_CLK

HDMI_CTR L_DAT

B

Issued Date

Issued Date

Issued Date

HDMI_CLK N
HDMI_CLK P

HDMI_TX_ N0
HDMI_TX_ P0

HDMI_TX_ N1

HDMI_TX_ P1
HDMI_TX_ N2
HDMI_TX_ P2

HDMI_CLK P
HDMI_CLK N

HDMI_TX_ P0
HDMI_TX_ N0

HDMI_TX_ P1
HDMI_TX_ N1

HDMI_TX_ P2
HDMI_TX_ N2

HDMI_R_C LKN

HDMI_R_T X_N1

HDMI_R_T X_N2

Security Classification

Security Classification

Security Classification

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

B

C

RPY2

RPY3

HDMI_GND

5

7

5

+3VS

G

DY2

1

1

2

2

4

4

5

5

3

3

8

L05ESD L5V0NA-4 SLP 2510P8

XEMC@

DY3

1

1

2

2

4

4

5

5

3

3

8

L05ESD L5V0NA-4 SLP 2510P8

XEMC@

DY1

6

I/O4

5

VDD

4

I/O3

AZC099 -04S.R7G_SOT 23-6

XEMC@

3

D

S

4

1 8
2 7
3 6
4

499_08 04_8P4R_1%

1 8
2
3 6
4 5

499_08 04_8P4R_1%

HDMI_R_C LKN HDMI_R_C LKN

HDMI_R_C LKP H DMI_R_CLKP

HDMI_R_T X_N0 HDMI_R_T X_N0

HDMI_R_T X_P0

HDMI_R_T X_N1

HDMI_R_T X_P1 HDMI_R_T X_P1

HDMI_R_T X_N2

HDMI_R_T X_P2 HDMI_R_T X_P2

HDMI_HPD

HDMI_CTR L_CLK

QY2B
2N7002 KDW_SOT 363-6

9

10

8

9

7

7

HDMI_R_T X_P0

6

6

HDMI_R_T X_N1

9

10

8

9

HDMI_R_T X_N2

7

7

6

6

HDMI_CTR L_DAT

3

I/O2

2

GND

1

I/O1

D

+HDMI_5V _OUT

P/N: SC300002900, S DIO(BR) AZC199-04S.R7G SOT23-6 ESD

Compal Secret Data

Compal Secret Data

2017/12 /18 2018/09 /01

2017/12 /18 2018/09 /01

2017/12 /18 2018/09 /01

C

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

E

+5VS +HDM I_5V_OUT

W=40mils

UY2

3

1

AP2330 W-7_SC59 -3

+HDMI_5V _OUT

Size Document Number R ev

Size Document Number R ev

Size Document Number R ev

Custom

Custom

Custom

Dat e: Sheet o f

Dat e: Sheet o f

Dat e: Sheet o f

OUT

IN

HDMI_CTR L_DAT
HDMI_CTR L_CLK
GPU_DP 2_CTRL_CLK
GPU_DP 2_CTRL_DAT

HDMI_HPD

HDMI_CTR L_DAT
HDMI_CTR L_CLK

HDMI_R_C LKN

HDMI_R_C LKP
HDMI_R_T X_N0

HDMI_R_T X_P0
HDMI_R_T X_N1

HDMI_R_T X_P1
HDMI_R_T X_N2

HDMI_R_T X_P2

Title

Title

Title

2

GND

ZZZ2

HDMI_ROYAL TY

ROYALTY HDM I W/LOGO+HD CP

RO0000 003HM

45@

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

1

CY23

0.1U_02 01_10V6K

2

+HDMI_5V _OUT

RPY1

18
2

7

36
45

2.2K_08 04_8P4R_5%

HDMI connector

JHDMI1

19

HP_DET

18

+5V

17

DDC/CEC_GND

16

SDA

15

SCL

14

Reserved

13

CEC

12

CK-

11

CK_shield

10

CK+

9

D0-

8

D0_shield

7

D0+

6

D1-

5

D1_shield

4

D1+

3
2
1

CCM_C1 00042GR019 M298ZL

CONN@

HDMI CONN.

HDMI CONN.

HDMI CONN.

GND

D2-

GND

D2_shield

GND

D2+

GND

DC232003500

E

+1.8VSD GPU_AON

20
21
22
23

34 67Thursday, Febru ary 22, 2018

34 67Thursday, Febru ary 22, 2018

34 67Thursday, Febru ary 22, 2018

1.0

1.0

1.0

1

3

5

+3VS_S SD_NGFF+3VS

RM1
0_1206 _5%

1 2

@

CM1

D

1A modify

PCIE_PRX _DTX_N9<18>
PCIE_PRX _DTX_P9<18>

PCIE_PTX _DRX_N9< 18>

PCIE_PTX _DRX_P9<18>

PCIE_PRX _DTX_N10<18 >
PCIE_PRX _DTX_P10< 18>

PCIE_PTX _DRX_N10<18>
PCIE_PTX _DRX_P10< 18>

PCIE_PRX _DTX_N11<18 >
PCIE_PRX _DTX_P11< 18>

PCIE_PTX _DRX_N11<18>
PCIE_PTX _DRX_P11< 18>

PCIE_PRX _DTX_P12< 18>

C C

PCIE_PRX _DTX_N12<18 >

PCIE_PTX _DRX_N12<18>

PCIE_PTX _DRX_P12< 18>

CLK_PC IE_NGFF#<16>
CLK_PC IE_NGFF<16>

4

10U_0603_6.3V6M

1

2

0.1U_0201_10V6K

2

CM2

1

1 2

CM6 0.22U_0402_ 16V7K

1

2

CM4 0.22U_0402_ 16V7K

1 2

CM5 0.22U_0402_ 16V7K

1 2

CM7 0.22U_0402_ 16V7K

1 2

CM8 0.22U_0402_ 16V7K

1 2

CM9 0.22U_0402_ 16V7K

1 2

CM10 0.2 2U_0402_16 V7K

1 2

CM11 0.2 2U_0402_16 V7K

1

+

CM3
150U_6 .3V_M_D2

SGA00009000

2

PCIE_PRX _DTX_N9
PCIE_PRX _DTX_P9

PCIE_PTX _C_DRX_N9
PCIE_PTX _C_DRX_P9

PCIE_PRX _DTX_N10
PCIE_PRX _DTX_P10

PCIE_PTX _C_DRX_N10
PCIE_PTX _C_DRX_P10

PCIE_PRX _DTX_N11
PCIE_PRX _DTX_P11

PCIE_PTX _C_DRX_N11
PCIE_PTX _C_DRX_P11

PCIE_PRX _DTX_P12
PCIE_PRX _DTX_N12

PCIE_PTX _C_DRX_N12

PCIE_PTX _C_DRX_P12

JSSD1

1

GND

3

GND

5

PERn3

7

PERp3

9

GND

11

PETn3

13

PETp3

15

GND

17

PERn2

19

PERp2

21

GND

23

PETn2

25

PETp2

27

GND

29

PERn1

31

PERp1

33

GND

35

PETn1

37

PETp1

39

GND

41

PERn0/SATA-B+

43

PERp0/SATA-B-

45

GND

47

PETn0/SATA-A-

49

PETp0/SATA-A+

51

GND

53

REFCLKN

55

REFCLKP

57

GND

3

M.2 SSD

3P3VAUX
3P3VAUX

DAS/DSS#

3P3VAUX
3P3VAUX
3P3VAUX
3P3VAUX

DEVSLP

PERST#

CLKREQ#

PEWake#

2
4
6

NC

8

NC

10
12
14
16
18
20

NC

22

NC

24

NC

26

NC

28

NC

30

NC

32

NC

34

NC

36

NC

38
40

NC

42

NC

44

NC

46

NC

48

NC

50
52
54
56

NC

58

NC

+3VS_S SD_NGFF

SSD_RS T#_R
SSD_CL KREQ#_R

2

SSD_RS T#_R

EMC@

2

CM16 100P_0402 _50V8J

Place close to JSSD pin 50

ESD request to reserve.

1 2

RM2 0_0402_5%@

1 2

RM4

1 2

RM6 0_0402_5%@

1 2

RM7 0_0402_5%@

0_0402 _5%@

1

1

SSD_DE VSLP1 < 18>

PLT_RS T_BUF# <1 7,36,37>
SSD_CL KREQ# <16>

D

59

SSD_DE T#

+3VS_S SD_NGFF

2

RM9

Pull high at PCH side

RM10

1 2

D

S

1

3

@

0_0402 _5%

2

G

B

SATA_G P1<18 >

BSS138 W-7-F_SOT 323-3

QM1

@

@

10K_04 02_5%

1

SSD_DE T#

SSD_DE T#

NC

61

PEDET(NC-PCIE/GND-SATA)

63

GND

65

GND

67

GND

BELLW _80159-32 21

CONN@

SP070018L00

SUSCLK(32kHz)

3P3VAUX
3P3VAUX
3P3VAUX

GND1
GND2

SUSCLK _SSD

60
62
64
66

68
69

+3VS_S SD_NGFF

1 2

RM8 0_0402_5%@

SSD_RS T#_R

SSD_CL KREQ#_R

SUSCLK <19,37 >

1

2

@

RM20 10K_04 02_5%

RM21 10K_04 02_5%

12

@

reserve for Optane Memory

+3VS

+3VS

SATA Device 0
PCIE Device 1

A A

Security Classification

Security Classification

Security Classification

2017/12 /18 2018/09 /01

2017/12 /18 2018/09 /01

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

5

4

2017/12 /18 2018/09 /01

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number R ev

Custom

Custom

Custom

Dat e: Sheet

Dat e: Sheet

2

Dat e: Sheet

Compal Electronics, Inc.

mSATA-SSD

mSATA-SSD

mSATA-SSD

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

35 67Thursday, Febru ary 22, 2018

35 67Thursday, Febru ary 22, 2018

35 67Thursday, Febru ary 22, 2018

1

1.0

1.0

1.0

o f

o f

o f

B

A

B

C

D

E

LAN-RTL8411B

LDO mode

W=60 mil

+REGOUT

1

2

PLT_RST _BUF#< 17,35,37>

LAN_CLKRE Q#<16 >

PCIE_PRX_DTX_ P14<18>

PCIE_PRX_DTX_ N14<18>
PCIE_PTX_C_D RX_P14< 18>
PCIE_PTX_C_D RX_N14<18 >

1

2

3

LAN_PWR _EN <39>

+3V_LAN+3VALW

60mil

1

60mil

2

CL14

1U_0402_ 6.3V6K

1

RL2
0_0805_5 %

1 2

@

UL1

5

IN

4

EN

SY6288C20AAC_ SOT23-5

LAN_PWR _EN

OUT

GND

OC

From EC

High active.
EN threshold voltage min:1.2V
typ:1.6V max:2.0V
Current limit threshold 1.5~2.8A

+3V_LAN Rising time must >0.5ms and <100ms

+3VS

1

SWR mode

1 2

1 2

RL15
1K_0402_ 5%

2

2

RL18
15K_0402 _5%

1

ISOLATEB

ENSWRE G ENSWRE G

2 2

+3V_LAN

RL11 0_0402_5%SWR@

RL13 0_0402_5%LDO@

RL1 0_0 603_5%L DO@

LL1

2.2UH_HPC 252012NF-2R 2M_20%

Using for Switch mode

CL1

0.1U_0201_10V6K

The trace length from
Lx to PIN48 (REGOUT)

LDO@

and from C to Lx must
< 200mils.

11/27: P/N change to SH00000RT00
( S COIL 2.2UH +-20%

HPC252012NF-2R2M 1.3A)

+3V_LAN

EC_PME#<1 7,39>

reserve EC_PME# pull high 100K to +3VALW_EC

CL15 .1U _0402_16V7K

CL17 .1U _0402_16V7K

LDO mode

+3V_LAN

1 2

RL12 10K_0402_ 5%@

YL1

3 3

10P_0402 _50V8J

CL18

25MHZ_20 PF_XRCGB25M000F2 P18R0

3

XTLI

3

1

2

1

NC

NC

2

4

GPO

XTLO_R

1

1

18P_0402 _50V8J
CL19

2

for disable PHY
reserve 0 ohm

P/N: SJ10000UP00 (S CRYSTAL 25MHZ 10PF XRCGB25M000F2P34R0)

TL1

LAN_TERMAL

LAN_MIDI0+

LAN_MIDI1+

LAN_MIDI1-

LAN_MIDI2+
LAN_MIDI2-

LAN_MIDI3+

CL25

4

0.1U_0201 _10V6K

1
2
3

4
5
6

7
8
9

10
11
12

1

GST5009-E

SP050006 B10

2

Place close to TCT pin

TCT1
TD1+
TD1-

TCT2
TD2+
TD2-

TCT3
TD3+
TD3-

TCT4
TD4+
TD4-

MCT1

MX1+
MX1-

MCT2

MX2+
MX2-

MCT3

MX3+
MX3-

MCT4

MX4+
MX4-

24
23
22

21
20
19

18
17
16

15
14
13

4

5

2

36

7

RJ45_MIDI0+
RJ45_MIDI0-LAN_MIDI0-

RJ45_MIDI1+
RJ45_MIDI1-

RJ45_MIDI2+
RJ45_MIDI2-

RJ45_MIDI3+
RJ45_MIDI3-LAN_MIDI3-

1

RPL1
75_0804_ 8P4R_1%

8

RJ45_GND

12

SWR@

IDC=1200mA

1 2

1 2

RL5 10K_ 0402_5%

XTLO_R

LAN_GPO<19>

RL3 0_0402_5%@

CLK_PCIE_LAN<16>
CLK_PCIE_LAN #<16>

1 2

1 2

RL16

2.49K_040 2_1%

RJ45_MIDI3-

RJ45_MIDI3+

RJ45_MIDI1-

RJ45_MIDI2-

RJ45_MIDI2+

RJ45_MIDI1+

RJ45_MIDI0-

RJ45_MIDI0+

RL14

1 2

330_0402 _5%

+3V_LAN

+LAN_VDD

12

12

RL17 0_0 402_5%

4.7U_0402_6.3V6M

0.1U_0201_10V6K

CL2

1

1

SWR@

2

2

ISOLATEB

LAN_PME#

CLK_PCIE_LAN
CLK_PCIE_LAN #

PLT_RST _BUF#
LAN_CLKRE Q#

PCIE_PRX_C_D TX_P14
PCIE_PRX_C_D TX_N14

LAN_MIDI0+
LAN_MIDI0­LAN_MIDI1+
LAN_MIDI1­LAN_MIDI2+
LAN_MIDI2­LAN_MIDI3+
LAN_MIDI3-

XTLI
XTLO

+REGOUT

LAN_RST

T45

@

1 2

@

T46@

T47@

LAN Connector

JRJ45

8

PR4-

7

PR4+

6

PR2-

5

PR3-

4

PR3+

3

PR2+

2

PR1-

1

PR1+

SINGA_2RJ1660 -000111F

CONN@

DC234009H00

CL28

SWR@

31
39

23
24

30

29

25
26
21
22

1
2
4
5
6
7
9

10

44
45

36

35
34
46

47

41
38

GPO

37
40

12

GND

11

GND

10

GND

9

GND

0.1U_0201_10V6K

0.1U_0201_10V6K

1

2

UL2

Power Manahement/Isolation

ISOLATEBPIN
LANWAKEB

PCI-Express

REFCLK_P
REFCLK_N

PERSTBPIN

CLKREQBPIN

HSOP
HSON
HSIP
HSIN

Transceiver Interface

MDIP0
MDIN0
MDIP1
MDIN1
MDIP2
MDIN2
MDIP3
MDIN3

CKXTAL1
CKXTAL2

Regulator and Reference

REG_OUT

VDDREG
ENSWREG_H
AVDD10

RSET

LED0
LED1/GPO
LED3

LED_CR

RTL8411 B-CGT_QFN48_6 X6

LANGND

0.1U_0201_10V6K

CL4

CL3

1

2

Clock

LEDs

LANGND

CL5

1

2

W=60 mil

300mA

0.1U_0201_10V6K
CL6

1

2

Card Reader

CL26
10P_0402 _50V8J

3

Place near P in 20Place ne ar Pin 3,8,33,46

SD_D0/MS_D1

SD_CLK/MS_D0

SD_CMD/MS_D2

SD_D3/MS_D3

SD_D2/MS_CLK

SD_WP/MS_BS

SD_CD#

MS_CD#

AVDD33
AVDD33
DVDD33

DVDD33

DVDD10
AVDD10
AVDD10

EVDD10

Card_3V3

DV33/18

1

2

2

MESC5V02BD03_SOT23-3

EMC@

1

0.1U_0201_10V6K

1

2

SD_D1

E_Pad

RJ45_GND

DL1

+LAN_VDD

CL7

1U_0402_6.3V6K

CL8

1

2

+3V_LAN

1

2

W=60 mil

1.4A

0.1U_0201_10V6K

CL9

Using for Switch mode

The trace length
from C to
PIN 34,3 5(V DDR EG)
must < 200mils.

PVT modify 01/06
R2534, R2537, R2539, R2535, R2536
change to R-short

15

14

16

17
18
19
28

42
43

48
11
12

32

33
3
8

20

13

27

49

RL6 0_0 402_5%@

SD_D1

RL7 0_0 402_5%@

SD_CLK SD_CLK_R

RL4 10_ 0402_1%

SD_CMD SD_CMD _R

RL8 0_0 402_5%@
RL9 0_0 402_5%@

RL10 0_0402_5 %@

SD_WP

SD_CD#

140 0mA

300 mA

800 mA

+VDD33_18

0.1U_0201_10V6K

CL20

1

2

1
1 2

1 2
1

1 2

1

+3V_LAN

+LAN_VDD

@

2

2

2

Card Uninsert

+CARD_3V3

4.7U_0402_6.3V6M

CL21

1

1

2

2

Place near P in 27

SD Write protect inverter circuit

@

RL21 0_0402_5%

+3VS

2

RL20

40mil40mil

@

JPL1
JUMP_43X11 8

100K_040 2_5%

1

SD_WP#

Connector side

2

G

CL10

4.7U_0402_6.3V6M

1

SWR@

2

Card insert

CL22

0.1U_0201 _10V6K

12

IC side

SD_WP

1

D

QL1
L2N7002W T1G_SC-70 -3

S

SB00001GE00

3

0.1U_0201_10V6K

CL11

1

2

Place near Pin 11,32,48

SD_D0_RSD_D0

SD_D1_R

SD_D3_RSD_D3

SD_D2_RSD_D2

close to pin17

Write protect
(Lock)

SD_WPSD_WP#

0.1U_0201_10V6K

0.1U_0201_10V6K

CL13

CL12

1

1

2

2

2

CL16
5P_0402_ 50V8C

1

XEMC@

Protect cotact

Write Enable
(Unlock)

Open Open
Open

+CARD_3V3

Close

Close to Card Reader C ONN

0.1U_0201_10V6K

4.7U_0402_6.3V6M
CL24

CL23

1

1

2

2

SD_CLK_R

Card contact

Open
Close

Card Reader Connector

JSD1

6

SD_CMD_R
SD_CLK_R

SD_D0_R
SD_D1_R
SD_D2_R
SD_D3_R

SD_WP#
SD_CD#

Close to JREAD1 for EMI

VDD

3

CMD

7

CLK

5

VSS1

8

VSS2

9

DAT0

10

DAT1

1

DAT2

2

CD/DAT3

11

W/P

4

CD

TAITW_PSD ATQ09GLBS1NN4H 1

CONN@

SP011611110

RL19

XEMC@

0_0402_5 %

1 2

CL27

XEMC@

10P_0402 _50V8J

1 2

GND
GND

12
13

1

4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2017/12/18 2018/09/01

2017/12/18 2018/09/01

2017/12/18 2018/09/01

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number R ev

Size Document Number R ev

Size Document Number R ev

Custom

Custom

Custom

Dat e: Sheet

Dat e: Sheet of

D

Dat e: Sheet of

Compal Electronics, Inc.

LAN RTL8411H

LAN RTL8411H

LAN RTL8411H

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

E

1.0

1.0

36 67Thursday, Febru ary 22, 2018

36 67Thursday, Febru ary 22, 2018

36 67Thursday, Febru ary 22, 2018

1.0

of

A

https:/ /Dr-Bios.com

Wireless LAN

B

C

D

E

+3VALW +3VS_W LAN

CM15

1U_0402_6.3V6K

1

1

2 2

@

2

+3VALW

RM44 0_0805_5%@

+3VS

RM11 0_0805_5%NIOAC@

60mil

WLA N_ON< 39>

1

1 2

2

4.7U_04 02_6.3V6M

+3VS_W LAN

CM12

5

4

1

2

NGFF WL+BT (KEY E)

3

W=60mils

UM1

IN

EN

SY6288C2 0AAC_SOT23 -5

IOAC@

1

2

1

OUT

2

GND

3

OC

CM13

@

0.1U_02 01_10V6K

0.1U_02 01_10V6K

CNV_PR X_DTX_N1<1 6>

CNV_PR X_DTX_P1<16>

CNV_PR X_DTX_N0<1 6>
CNV_PR X_DTX_P0<16>

CLK_CN V_PRX_DTX_ N<16>

CLK_CN V_PRX_DTX_ P<16>

CNV_PT X_DRX_N1<1 6>
CNV_PT X_DRX_P1<16>

CNV_PT X_DRX_N0<1 6>
CNV_PT X_DRX_P0<16>

CLK_CN V_PTX_DRX_ N<16>
CLK_CN V_PTX_DRX_ P<16>

(link to PICE Po rt 3)

(From PCH C LKOUT2)

PCIE CLK

CM14

PCIE X1

reserve for cnvi issue (1.0)

@

1

1

CM19

4.7U_04 02_6.3V6M

2

2

USB2 Port.14

1 2

RM22

(For BT)

+3VS_W LAN

1 2

RM23 0_0201_5%

1 2

RM24 0_0201_5%

1 2

RM25 0_0201_5%

1 2

RM26 0_0201_5%

1

RM27 0_0201_5%

PCIE_PTX _C_DRX_P15<18>

PCIE_PRX _DTX_P15< 18>

PCIE_PRX _DTX_N15<18 >

CLK_PC IE_WLAN<16>

CLK_PC IE_WLAN#<16>

WLA N_CLKREQ#<16>

1 2

RM28 0_0201_5%

1

RM29 0_0201_5%

1 2

RM30 0_0201_5%

1 2

RM31 0_0201_5%

1

RM32 0_0201_5%

1

RM33 0_0201_5%

RM16 10 K_0402_5%

UART_2 _PRXD_R_DT XD
UART_2 _PTXD_R_DR XD

Co-layout with CNVi

1 2

RM42 0_0402_5%UART@

1

RM43 0_0402_5%UART@

2

PH +3VS at SOC side,
for win7 USB3 debug

UART_2 _PRXD_DTXD <20>

UART_2 _PTXD_DRXD <20>

reserve 1000p for cnvi issue (1.0)

2
4
6
8
10
12
14
16
18
20
22

24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66

68

+3VS_W LAN

CNV_RF _RESET#_R

CLKREQ _CNV#_R

UART_2 _PRXD_R_DT XD

UART_2 _PTXD_R_DR XD
CNV_RG I_PRX_R_DTX
CNV_BR I_PTX_R_DRX

E51TXD _P80DATA_R
E51RXD _P80CLK_R

SUSCLK _R

WL_ RST#_R
BT_ON
WL_ OFF#

REFCLK _CNV_R

T52@

T53@

RM40 0_0201_5%

1 2

RM34 0_0201_5%

1 2

RM35

1 2

RM36 0_0402_5%CNVI@

1 2

RM37

1 2

RM38 0_0201_5%

1

RM39 0_0201_5%

RM12 0_0402_5%@

RM13 0_0402_5%@

1

RM14 0_0402_5%@

1 2

RM15 0_0402_5%@

1 2

E51TXD _P80DATA_R

CNVI@

2

12

12

2

XEMC@

1

CM17

0.1U_02 01_10V6K

For ESD req reserve L C filter

2

close PCH

1

2

JNGFF1

KEY E

1

USB20_ P14<1 5>

USB20_ N14<15>

0_0201 _5%

2

WLA N_PME#<39>

2

2
2

WLA N_PME#

12

USB20_ P14
USB20_ N14

CNV_PR X_R_DTX_N1
CNV_PR X_R_DTX_P1

CNV_PR X_R_DTX_N0
CNV_PR X_R_DTX_P0

CLK_CN V_PRX_R_DT X_N
CLK_CN V_PRX_R_DT X_P

PCIE_PTX _C_DRX_P15
PCIE_PTX _C_DRX_N15

PCIE_PRX _DTX_P15
PCIE_PRX _DTX_N15

CLK_PC IE_WLAN
CLK_PC IE_WLAN#

WLA N_CLKREQ#
WLA N_PME#

CNV_PT X_R_DRX_N1
CNV_PT X_R_DRX_P1

CNV_PT X_R_DRX_N0
CNV_PT X_R_DRX_P0

CLK_CN V_PTX_R_DR X_N
CLK_CN V_PTX_R_DR X_P

GND_1

3

USB_D+

5

USB_D-

7

GND_7

9

SDIO_CLK

11

SDIO_CMD

13

SDIO_DAT0

15

SDIO_DAT1

17

SDIO_DAT2

19

SDIO_DAT3

21

SDIO_WAKE

23

SDIO_RST

25

GND_33

27

PET_RX_P0

29

PET_RX_N0

31

GND_39

33

PER_TX_P0

35

PER_TX_N0

37

GND_45

39

REFCLK_P0

41

REFCLK_N0

43

GND_51

45

CLKREQ0#

47

PEWAKE0#

49

GND_57

51

RSVD/PCIE_RX_P1

53

RSVD/PCIE_RX_N1

55

GND_63

57

RSVD/PCIE_TX_P1

59

RSVD/PCIE_TX_N1

61

GND_69

63

RSVD_71

65

RSVD_73

67

GND_75

69

GND2

BELLW _80152-32 21

CONN@

SP070013E00

3.3VAUX_2

3.3VAUX_4
LED1#

PCM_CLK

PCM_SYNC

PCM_OUT

PCM_IN

LED2#

GND_18

UART_WAKE

UART_TX

UART_RX
UART_RTS
UART_CTS
CLink_RST

CLink_DATA

CLink_CLK

COEX3
COEX2
COEX1

SUSCLK(32KHz)

PERST0#

W_DISABLE2#
W_DISABLE1#

I2C_DAT
I2C_CLK

I2C_IRQ
RSVD_64
RSVD_66
RSVD_68
RSVD_70

3.3VAUX_72

3.3VAUX_74

GND1

@

1 2

CM18 10 00P_0402_5 0V7K

CNVI@

1

2

RM41

75K_04 02_1%

0_0201 _5%

0_0402 _5%

E51TXD _P80DATA <39>PCIE_PTX _C_DRX_N15< 18>
E51RXD _P80CLK < 39>

SUSCLK <19,35>
PLT_RS T_BUF# <1 7,35,36>
BT_ON <3 9>
WL_ OFF# <39 >

REFCLK _CNV <16>

For CNVi Feature

RM19
100K_0 402_5%

CNV_RF _RESET# <19 >

CLKREQ _CNV# <19>

CNV_BR I_PRX_DTX <16>

CNV_RG I_PTX_DRX <16>
CNV_RG I_PRX_DTX <16>

CNV_BR I_PTX_DRX <16>

1

3

reserve for BT_ON OD pull high (1.0)

BT_ON

4 4

Security Classification

Security Classification

A

Security Classification

2017/12 /18 2018/09 /01

2017/12 /18 2018/09 /01

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

B

2017/12 /18 2018/09 /01

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

1 2

@

RM458.2K_ 0402_5%

Title

Title

Title

M.2 Key E (WLAN)

M.2 Key E (WLAN)

M.2 Key E (WLAN)

Size Document Number R ev

Size Document Number R ev

Size Document Number R ev

Custom

Custom

Custom

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

Dat e: Sheet o f

Dat e: Sheet o f

Dat e: Sheet

+3VS_W LAN

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

E

o f

37 67Thursday, Febru ary 22, 2018

37 67Thursday, Febru ary 22, 2018

37 67Thursday, Febru ary 22, 2018

1.0

1.0

1.0

A

HD Audio Codec

1

Reserved for RF

2 2

+3VS

RA13 100K_0 402_1%

+3VS_DVDD

+1.8VS

3 3

+3VALW

+5VALW

SENSE_A

12

HDA_RST#_ R<19>

HP_PLUG#<44>

1 2

255@

RA36 0_0402 _5%

1 2

256@

RA37 0_0402 _5%

1 2

255@

RA16 0_0402 _5%

1 2

256@

RA35 0_0402 _5%

+VDDA

2

XEMC@

GNDA

3V_1.8V_PVDD

3V_5V_STB

1

2000mA 600ohm@1 00MHz
DCR 0.1

LA1

FBMA-L11-201 209601LMA20T _2P

1 2

PN : SM01000EE00

+3VS

1 2

RA2 0_ 0402_5%

+3VS

1 2

RA4 0_ 0402_5%

DMIC_CLK

CA2710P _0402_50V8J

+MICBIAS

40mil

EC_MUTE#<39>

1 2

255@

RA42 0_0402 _5%

Close codec

RA12 200 K_0402_1%

RA17 20K_ 0402_5%@

12

12

1

CA15
1U_0402_ 6.3V6K

2

GNDA

RA19

GND

@

@

RESETB

2

CA1

10U_0402_6.3V6M

1

2

near Pin9

near Pin1

LINE1_L

LINE1_R

RING2
SLEEVE

DMIC_DATA
DMIC_CLK

MONO_IN

CA19

10U_0402 _6.3V6M

1

2

SENSE_A

3V_1.8V_PVDD

3V_5V_STB

1 2

1

0_0402_5 %@

40mil

CA2

0.1U_0201_10V6K

1 2

CA7 0.1 U_0201_10V6K

1 2

CA8 10 U_0603_6.3V6M

20mil

1

2

for ALC256 co-lay

RA22

22K_0402 _5%

RA27

22K_0402 _5%

12

12

BEEP#<39>

4

PCH_SPKR<19 ,20>

XEMC@

BEEP#_R

CA26

100P_0402_50V8J

1

2

2

RA24

4.7K_0402 _5%

1

CA25

255@

1U_0402_ 6.3V6K

1 2

MONO_IN

GND

A

B

CA3

0.1U_0201_10V6K

1

2

near Pin46near Pin41

+3VS_DVDDIO

+3VS_DVDD

CA10

0.1U_0201_10V6K

10U_0603_6.3V6M

CA9

1

2

UA1

22

LINE1-L(PORT-C-L)

21

LINE1-R(PORT-C-R)

24

LINE2-L(PORT-E-L)

23

LINE2-R(PORT-E-R)

31

LINE1-VREFO-L

30

LINE1-VREFO-R

17

MIC2-L(PORT-F-L) /RING

18

MIC2-R(PORT-F-R) /SLEEVE

2

GPIO0/DMIC-DATA

3

GPIO1/DMIC-CLK

47

PDB

11

RESETB

12

PCBEEP

13

HP/LINE1 JD(JD1)

14

MIC2/LINE2 JD(JD2)

15

SPDIFO/FRONT JD(JD3)/GPIO3

37

CBP

35

CBN

36

CPVDD

20

VD33 STB

19

MIC CAP

4

DC DET

49

Thermal PAD

ALC255-CG_ MQFN48_6X6

SA00008270 0

RA25 0_0 402_5%@

RA29 0_0 402_5%@

RA31 0_0 402_5%@

RA33 0_0 402_5%@

B

1

DVDD

1 2

1 2

1 2

1

+5VS_PVDD

+5VS_AVDD

41

46

9

PVDD1

PVDD2

DVDD-IO

2

+1.8VS_VDDA

40

26

AVDD2

AVDD1

HPOUT-L(PORT-I-L)

HPOUT-R(PORT-I-R)

SPDIF-OUT/GPIO2

20mil

CA4

0.1U_0201_10V6K

1

2

GNDA

near Pin26

GNDA

SPK-OUT-L-

SPK-OUT-L+

SPK-OUT-R+

SPK-OUT-R-

SYNC

BCLK

SDATA-OUT

SDATA-IN

MONO-OUT

MIC2-VREFO

LDO3-CAP
LDO2-CAP
LDO1-CAP

VREF

CPVEE

AVSS1
AVSS2

RA26

RA30 0_0 402_5%@

RA32

RA34

0.1U_0201_10V6K

1

2

1

2

Place ne ar Pin40

43
42

45
44

32
33

10
6
5
8

48

16

29

7
39
27

28

34

25
38

1

1 2

1 2

1 2

GNDAGN D GND GNDA

RA1

@

0_0603_5 %

1 2

10U_0402_6.3V6M

CA6

CA5

1

2

down size for female gaming(1.0)

1 2

RA3 0_ 0402_5%

CA12

10U_0402_6.3V6M

CA11

0.1U_0201_10V6K

1

2

SPKL­SPKL+

SPKR+

SPKR-

HP_LEFT
HP_RIGHT

HDA_SYNC_R
HDA_BIT_CLK _R

HDA_SDOUT _R

HDA_SDIN0_AUD IO

1 2

256@

RA45 0_0402 _5%

1 2

+MIC2_VREFO

CA14 10U_0402_6 .3V6M

CA16 10U_0603_6 .3V6M
CA17 10U_0402_6 .3V6M

10mil

CODEC_VREF

CPVEE

GNDA

@

RA14 100K_ 0402_5%

CA18 10U_0402_6 .3V6M@

CA20 2.2U_0402_6 .3V6M

CA21 0.1U_0201_1 0V6K@

CA22

1U_0402_6.3V6K

1

2

2

0_0402_5 %@

0_0402_5 %@

0_0402_5 %

C

D

DMIC3 Conn. (support on 256)

+VDDA

@

+5VS

JPA1

1 2

JUMP_43X39

(output = 300 mA)

+1.8VS

+VDDA

@

DA4

6

+3VS

I/O4

5

VDD

4

I/O3

AZC099-04S.R 7G_SOT23-6

XEMC@

40mil

Int. Speaker Conn.

SPKR+

HDA_BIT_CLK _R

1 2

RA10 33_0402_ 5%

1U_0402_ 6.3V6K

256@

1 2

CA28

1 2

1 2
1 2

1

1 2

1 2

2

2

RA5
0_0402_5 %

1

XEMC@

2

CA13
22P_0402 _50V8J

1

XEMC@

DMIC_DATA34

BEEP#_R

HDA_SYNC_R <19>
HDA_BIT_CLK _R <19>
HDA_SDOUT _R <19>
HDA_SDIN0 <19>

single net

GND

down size for female gaming(1.0)

GNDA

GNDA

I2C for Co-lay ALC256

+3VS_DVDD

1

1

256@

RA41

3.3K_0402 _5%

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

256@

RA44

3.3K_0402 _5%

2

2

MONO_IN

RESETB

Compal Secret Data

Compal Secret Data

2017/12/18 2018/09/01

2017/12/18 2018/09/01

2017/12/18 2018/09/01

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

SPKR-

SPKL+

SPKL-

GND GND

Digital MIC

MIC BOM upload by Audio Team

PCH_DMIC_D ATA0<19>

PCH_DMIC_C LK0<19>

Headphone Out

+MICBIAS

D

DMIC_CLK

I/O2

GND

I/O1

1 2

LA2

1

LA3 HCB1608 KF-121T30_06 03EM C@

1 2

LA4 HCB1608 KF-121T30_06 03EM C@

1 2

LA5 HCB1608 KF-121T30_06 03EM C@

JPA2

@

1

1

JUMP_43X79

JPA3

@

112

JUMP_43X79

+MIC2_VREFO

DA3

1

BAT54A-7-F_SOT 23-3

SCSBAT54100

LA7

2

1

BLM15PX221 SN1D_2P256@

SM01000Q5 00

DMIC_CLK34

3

2

GND

DMIC_DATA34

1

40mil

HCB1608K F-121T30_060 3EMC @

2

2

2

2

DMIC_DATA

2

PCH_DMIC_D ATA0

PCH_DMIC_C LK0

RA7 0_0 402_5%

@

RA8 33_ 0402_5%

2

@

RA9 33_ 0402_5%

DMIC_CLK

HP_RIGHT HPOUT _R_1

LINE1_L

LINE1_R

2

LA6 BLM15PX221S N1D_2PEMC@

SM01000Q5 00

change PN to SM01000Q500

1 2

RA15 2.2K_0402_5%

1 2

RA18 2.2K_0402_5%

1 2

RA20 0_060 3_5%@

1 2

RA21 0_060 3_5%@

1 2

CA23 4.7U_0402_6.3 V6M

1

CA24 4.7U_0402_6.3 V6M

2

3

RA23

4.7K_0402 _5%

2

RA28

4.7K_0402 _5%

Title

Title

Title

Size Document Number R ev

Size Document Number R ev

Size Document Number R ev

Custom

Custom

Custom

Dat e: Sheet

Dat e: Sheet of

Dat e: Sheet of

E

+3VS

GND

ACES_50278 -00401-001

SP02000RR00

GND

TO eDP cable

SLEEVE

RING2

E

1
2
3
4
5
6

ACES_50273 -0040N-001

JSPK1

1

1

2

2

3

3

4

4

5

G1

6

G2

CONN@

DMIC_DATA_R <33>

DMIC_CLK_R <33>

DMIC_DATA34
DMIC_CLK34

SPK_R+
SPK_R-

SPK_L+
SPK_L-

DMIC_DATA_R

1

12

1

DMIC_CLK_R

1

TO IO/B

HPOUT_L_ 1HP_LEFT

2

12

1

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

HD Audio Codec ALC255

HD Audio Codec ALC255

HD Audio Codec ALC255

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

JDMIC1

1
2
3
4
G5
G6

SP02000T I00

SLEEVE <44>

RING2 <44>

HPOUT_L_ 1 <4 4>

HPOUT_R_ 1 <44>

38 67Thursday, Febru ary 22, 2018

38 67Thursday, Febru ary 22, 2018

38 67Thursday, Febru ary 22, 2018

of

1.0

1.0

1.0

1

4

A

B

C

D

E

Board ID

+3VLP

JPB1

2

112

JUMP_43X39

@

+3VLP_EC

1

1 2

RB4 47K_0402_ 5%@

For turn off internal LPC module of KB9032

XEMC@

1 2

CB5 10 0P_0402_50V8J

2

1

CB6 10 0P_0402_50V8J

XEMC@

12

CB7
22P_0402 _50V8J

+3VLP_EC

1 2

RB10 2.2K_ 0402_5%

2 2

1 2

RB11 2.2K_ 0402_5%

SPOK_3V

SPOK_5V

1 2

RB72 0_0 402_5%

1 2

RB73 0_0 402_5%@

XEMC@

RB6

33_0402_ 5%

12

EC_PME#

PLT_RST #

AC_IN

CLK_LPC_ R

EC_SMB_C K1
EC_SMB_D A1

SPOK_3V5V

For Power consumption
Measurement

SUSPWR DNACK<19>
CHG_CTL 3<4 2>

For abnormal shutdown

EC_VCCST_ PG_R

2

VCOUT1_PR OCHOT

2

RB19

@

0_0402_5 %

1

@

QB1B

3

D

2N7002KD W_SOT363- 6

S

4

EC_RSMRS T#SPOK_3V5V

PCH_PW ROK

5

G

PU at CPU side

GPU_OVERT#<25>

FAN_SPEED1<46>
FAN_SPEED2<46>

E51TXD_P8 0DATA<37>

E51RXD_P80 CLK<37>

PWR_SU SP_LED#<44>

1 2

DB2 RB7 51V-40_SOD323- 2

1 2

DB3 RB7 51V-40_SOD323- 2

1

3 3

VCOUT1_PR OCHOT VCOUT1_PROCH OT

DB4 RB7 51V-40_SOD323- 2

DGPU_AC_DE TECT SW_PROCH OT#

2N7002KD W_SOT363- 6

@

QB1A

6

D

2

G

S

1

0.1U_0201_10V6K

0.1U_0201_10V6K

CB1

CB2

1

1

2

2

ESPI Bus Pin : 1~5.7.8.10.12.14
LPC Bus Pin : 3~5.7.8.10.12.13

SUSPWR DNACK
CHG_CTL 3

TPM_SERIRQ<18,45>
LPC_FRAME#<1 8,45>

LPC_AD3<18 ,45>
LPC_AD2<18 ,45>
LPC_AD1<18 ,45>
LPC_AD0<18 ,45>

CLK_LPC_ R<18 >
PLT_RST #<17>
EC_RST#<46 >

EC_SCI#<20>

WLAN_ON<37>

KSI[0..7]<45>

KSO[0..17]<45>

EC_SMB_C K1<49,50>

EC_SMB_D A1<49,50>

EC_SMB_C K2<19 ,25,40,44>

EC_SMB_D A2<19 ,25,40,44>

PM_SLP_S3 #<1 9,47>

ESPI_RST#<18>

SPOK_3V<51,54>

TP_EN<45>

TS_EN<20,3 3>
WL_OFF#<37>
AC_PRESENT<19 >

PCH_PW ROK<19,47>

NUM_LED#<4 5>

PBTN_OUT #<1 9>

PM_SLP_S4 #<1 9,47>

TPM_SERIRQ

LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

CLK_LPC_ R
PLT_RST #

EC_RST#

EC_SCI#

WLAN_ON

KSI0

KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0

KSO1
KSO2
KSO3

KSO4
KSO5
KSO6

KSO7
KSO8

KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15

KSO16
KSO17

EC_SMB_C K1
EC_SMB_D A1

PM_SLP_S3 #
ESPI_RST#
SPOK_3V
TP_EN
TS_EN
WL_OFF#
AC_PRESENT

GPU_OVERT#

FAN_SPEED1

FAN_SPEED2

E51TXD_P8 0DATA

E51RXD_P80 CLK

PWR_SU SP_LED#

NUM_LED#

PBTN_OUT #
PM_SLP_S4 #

CO-LAY with KB9032QA (SA000080J00)

remove C NVI detect pin on EC(1.0)

2

4

A

VCCCORE_VR_ PWRGD<56>

VCCSA_VR_PW RGD< 57>

RB78 0_0402 _5%@

RB77 1K_040 2_5%@

1

12

check VR_PW RGD IS
AND BY CORE_PWRGD & SA_PWRGD

B

VR_PWRGD

+3VLP_EC

UB1

1

GATEA20/GPIO00

2

KBRST#/GPIO01

3

SERIRQ

4

LPC_FRAME#

5

LPC_AD3

7

LPC_AD2

8

LPC_AD1

10

LPC_AD0

12

CLK_PCI_EC

13

PCIRST#/GPIO05

37

EC_RST#

20

EC_SCI#/GPIO0E

38

CLKRUN#/GPIO1D

55

KSI0/GPIO30

56

KSI1/GPIO31

57

KSI2/GPIO32

58

KSI3/GPIO33

59

KSI4/GPIO34

60

KSI5/GPIO35

61

KSI6/GPIO36

62

KSI7/GPIO37

39

KSO0/GPIO20

40

KSO1/GPIO21

41

KSO2/GPIO22

42

KSO3/GPIO23

43

KSO4/GPIO24

44

KSO5/GPIO25

45

KSO6/GPIO26

46

KSO7/GPIO27

47

KSO8/GPIO28

48

KSO9/GPIO29

49

KSO10/GPIO2A

50

KSO11/GPIO2B

51

KSO12/GPIO2C

52

KSO13/GPIO2D

53

KSO14/GPIO2E

54

KSO15/GPIO2F

81

KSO16/GPIO48

82

KSO17/GPIO49

77

EC_SMB_CLK1/GPIO44

78

EC_SMB_DAT1/GPIO45

79

EC_SMB_CLK2/GPIO46

80

EC_SMB_DAT2/GPIO47

6

PM_SLP_S3#/GPIO04

14

GPIO07

15

GPIO08

16

GPIO0A

17

GPIO0B

18

GPIO0C

19

AC_PRESENT/GPIO0D

25

PWM2/GPIO11

28

FAN_SPEED1/GPIO14

29

FANFB1/GPIO15

30

EC_TX/GPIO16

31

EC_RX/GPIO17

32

PCH_PWROK/GPIO18

34

SUSP_LED#/GPIO19

36

NUM_LED#/GPIO1A

122

PBTN_OUT#/GPIO5D

123

PM_SLP_S4#/GPIO5E

2

RB2

@

0_0402_5 %

1

+3VLP_LPC

LPC & MISC

Int. K/B
Matrix

LB1
FBMA-L11-160 808-800LMT_ 0603

1 2

9

125

111

96

33

22

67

VCC

VCC

VCC

VCC

VCC0

VCC_LPC

EC_VCCST_PG/GPIO0F

PWM Output

VCIN1_BATT_TEMP/AD0/GPIO38

VCIN1_BATT_DROP/AD1/GPIO39

AD Input

DA Output

EN_DFAN1/DA1/GPIO3D

EC_MUTE#/PSCLK1/GPIO4A

USB_EN#/PSDAT1/GPIO4B

PS2 Interface

SPI Device Interface

SPI Flash ROM

EC_CIR_RX/AD6/GPIO40

SYS_PWROK/AD7/GPIO41

BATT_CHG_LED#/GPIO52

GPIO

BATT_LOW_LED#/GPIO55

SM Bus

EC_RSMRST#/GPXIOA03

VCIN1_ADP_PROCHOT/GPXIOA05

VCOUT1_PROCHOT#/GPXIOA06

VCOUT0_MAIN_PWR_ON/GPXIOA07

GPO

GPIO

PCH_PWR_EN/GPXIOA10

PWR_VCCST_PG/GPXIOA11

VCIN1_AC_IN/GPXIOD01

GPI

GND

GND

GND

GND

GND

35

11

94

24

69

113

ECAGND

2015/1/9 acer require:
reserved protact circuit when
adaptor 107% happen

+3VLP_ECA

+3VLP_ECA

1

CB3

0.1U_0201 _10V6K

2

ECAGND

ECAGND <49>

AVCC

BEEP#/GPIO10

EC_FAN_PWM/GPIO12

AC_OFF/GPIO13

ADP_I/AD2/GPIO3A

AD_BID/AD3/GPIO3B

AD4/GPIO42
AD5/GPIO43

DA0/GPIO3C

DA2/GPIO3E

DA3/GPIO3F

PSCLK2/GPIO4C
PSDAT2/GPIO4D
TP_CLK/GPIO4E

TP_DATA/GPIO4F

ENKBL/GPXIOA00

WOL_EN/GPXIOA01

ME_EN/GPXIOA02

VCIN0_PH1/GPXIOD00

MISO/GPIO5B
MOSI/GPIO5C

SPICLK/GPIO58

SPICS#/GPIO5A

GPIO50

CAPS_LED#/GPIO53

PWR_LED#/GPIO54

SYSON/GPIO56

VR_ON/GPIO57

DPWROK_EC/GPIO59

GPXIOA04

BKOFF#/GPXIOA08

GPXIOA09

EC_ON/GPXIOD02
ON/OFF#/GPXIOD03
LID_SW#/GPXIOD04

SUSP#/GPXIOD05

GPXIOD06

PECI/GPXIOD07

V18R/VCC_IO2

AGND

KB9022QD_ LQFP128_14X14

20mil

1 2

CB9

100P_040 2_50V8J

LB2

FBMA-L11-160 808-800LMT_ 0603

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

21
23
26
27

63

64
65
66

75
76

68
70
71
72

83
84
85
86
87
88

97
98
99
109

119
120
126
128

73
74

89
90
91
92
93
95
121
127

100
101
102
103
104
105
106
107
108

110
112
114
115
116
117
118

124

BATT_TEMP

12

EC_VCCST_ PG_R

BEEP#
FAN_PWM1

FAN_PWM2

BATT_TEMP
CHG_CTL 1

ADP_I
AD_BID

WLAN_PM E#
EC_PME#

LAN_PWR _EN
EC_TP_INT #
VR_PWRGD
KBL_EN

EC_MUTE#
USB_EN
EC_TYPEC_ EN#
CHG_EN

TP_CLK

TP_DATA

ENBKL
TP_PWR _EN

ME_EN
VCIN0_PH

SPOK_5V
BT_ON
EC_CLR_ CMOS
FP_PWR_ EN

GPU_ALERT
SYS_PWROK _R

BATT_BLUE _LED#
CAPS_LED#

PWR_LE D#

BATT_AMB_LE D#

SYSON

VR_ON
CHG_ILMSEL

EC_RSMRS T#

DGPU_AC_DE TECT

VCIN1_ADP_PROC HOT
VCOUT1_PR OCHOT

MAINPWON
BKOFF#

THERMAL_ALE RT#
3V_EN_R
PM_SLP_S0 #

AC_IN

EC_ONPCH_PW ROK

ON/OFFBTN#
LID_SW#

SUSP#

SW_PROC HOT#

EC_PECI

2017/12/18 2018/09/01

2017/12/18 2018/09/01

2017/12/18 2018/09/01

EC_VCCST_ PG_R <11,47 >
BEEP# <38>

FAN_PWM1 <46 >
FAN_PWM2 <46 >

BATT_TEMP <49 ,50>

CHG_CTL 1 < 42>
ADP_I <49,50>

WLAN_PM E# < 37>
EC_PME# <17,36>

LAN_PWR _EN <36>

EC_TP_INT # <17 ,45>

KBL_EN <45>

EC_MUTE# <38>
USB_EN <44>

EC_TYPEC_ EN# <40>
CHG_EN <42 >
TP_CLK <45>
TP_DATA <45>

ENBKL <18,25>
TP_PWR _EN <45>

ME_EN <19>

VCIN0_PH <49>

SPOK_5V <51>
BT_ON <37>

FP_PWR_ EN <46>

GPU_ALERT <25>

BATT_4S <5 0>

BATT_BLUE _LED# <44>

CAPS_LED# <4 5>
PWR_LE D# <44>
BATT_AMB_LE D# <44>

SYSON <47,52,5 4>

VR_ON <47,55,56,5 7>

CHG_ILMSEL < 42>

EC_RSMRS T# < 19>
DGPU_AC_DE TECT <20 ,25,50>
VCIN1_ADP_PROC HOT < 49>

MAINPWON < 46,49,51>

BKOFF# <33>

THERMAL_ALE RT# <44>

PM_SLP_S0 # <19>

AC_IN <50>

EC_ON <51>

ON/OFFBTN# <45>
LID_SW# <44>
SUSP# <47,50,52,55>

1 2

RB16 33_0402_1%

+3VLP_EC

Compal Secret Data

Compal Secret Data

Compal Secret Data

add for 4C Batt (1.0)

H_PECI <11,18 >

Deciphered Date

Deciphered Date

Deciphered Date

D

near SOC

CB8

.1U_0402_ 16V7K

XEMC@

H_PROCHOT #<11,50>

RB3

VX15@

240K_040 2_1%

SD000001B80

change board ID to 1A

Analog Board ID definition,
Please see page 3.

EC_CLR_ CMOS

RB26

10K_0402 _5%

SYS_PWROK _R

GPU_ALERT

GPU_OVERT#

EC Internal PU

LID_SW#

DB1
RB751V-40_ SOD323-2

MAINPWON

1

3V_EN_R

2

Title

Title

Title

Size Document Number R ev

Size Document Number R ev

Size Document Number R ev

Custom

Custom

Custom

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

Dat e: Sheet of

Dat e: Sheet of

Dat e: Sheet of

+3VLP_EC

2

RB1

100K_040 2_1%

20K_0402 _1%

1

2

RB7

RB9 10K_0402 _5%VGA@

RB12 10K_0 402_5%VGA@

RB13 100K_ 0402_1%

RB3

V15@

2

G

1

@

1 2

1 2

1 2

Ra

1

AD_BID

2

Rb

1

1

D

QB6

L2N7002W T1G_SC-70 -3

S

SB00001GE00

3

2

0_0402_5 %

1

CB4

@

0.1U_0201 _10V6K

2

PCH_RTC RST# <19>

SYS_PWROK <19,4 7>

+3VS

+3VLP_EC

For Thermal Portect Shutdown

1 2

RB14

1 2

1K_0402_ 5%

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

EC ENE-KB9012A4/KB9022

EC ENE-KB9012A4/KB9022

EC ENE-KB9012A4/KB9022

3V_EN

RB15
1M_0402_ 5%

RB74

@

0_0402_5 %

1 2

RB17

@

0_0402_5 %

1 2

RB18

@

0_0402_5 %

1

E

SW_PROC HOT#H_PROCHOT #

2

1

FOLLOW TD

VR2_HOT#

VR_HOT#

3V_EN <51>

2

39 67Thursday, Febru ary 22, 2018

39 67Thursday, Febru ary 22, 2018

39 67Thursday, Febru ary 22, 2018

VR2_HOT# <57>

VR_HOT# <56>

1.0

1.0

1.0

1

4

5

+5VALW

0.1U_04 02_10V6K

RS156 100 K_0402_5%TYPEC@

RS155 1K_ 0402_5%TYPEC@

+3VALW

D

1 2

2.2U_04 02_6.3V6M

12

@

CS124

12

CS90

TYPEC@

6

5

4

1

2

US2

OUT

IN

SET

GND

EN(/EN)

FLAG

G527AT P1U_TSOT23 -6

TYPEC@

SA00006Y700

20 mils

1

2

3

4

+5V_CC

TYPEC@

1

CS101

0.1U_02 01_10V6K

2

3

2

+3.3V_C C +3.3V_C C

1

RS103

10K_04 02_5%

TYPEC@

RS104

@

2

1

2

CUR_MO DE0 CU R_MODE1

10K_04 02_5%

1

2

RS105
10K_04 02_5%

TYPEC@

1

2

RS106
10K_04 02_5%

@

1

D

0.2A OCP for VCONN!

Initial Current mode selection

+3VALW +3.3V_C C

1 2

RS1 0_06 03_5%

1.0 Modify

CUR_MODE0 CUR_MODE 1 MODE

H

L

H

L

H

H

Default Current

Medium current

High current

+USB3_ VCCC

12

C C

Scaled input
for detection of VBUS DC levels

RS101
39K_04 02_1%

TYPEC@

VBUS_D C

1

RS102

3.01K_0 402_1%

TYPEC@

2

179F_S MB_DA2
179F_S MB_CK2

VBUS_D C
CUR_MO DE0
CUR_MO DE1

US3

TYPEC@

1

GPIO2(INT#)

2

CUR_DR

3

SI0(SDA)

4

SI1(SCL)

7

VBUS_DC

14

CUR_MODE0

15

CUR_MODE1

6

GND

EJ179F _QFN16_4X4

VCONN

VDD33

VDD18

CC1
CC2

CC_EN

CC_SEL

TYPC_CONN_DET

EPAD

10

9

8

17

11
12

16
5
13

+5V_CC

+3.3V_C C

+1.8V_C C

VBUS_E N_179

2

1

CS91 2.2U_ 0402_6.3V6M

TYPEC@

1 2

CS92 1U_0 402_6.3V6K

TYPEC@

CC1_VC ONN <41>
CC2_VC ONN <41>

1

TYPEC@

RS116
10K_04 02_5%

2

1.0 Modify

Remove INT#,
platform doesn't monitor it

CC_SEL
report CC1 or CC2 is connection

CC_EN

B

power path control "low active"

150U_D2_6.3VM_R17M

EC need change to low active

PU on SOC side

EC_SMB _CK2< 19,25,39,44>

+3.3V_C C

S

2N7002 KDW_SOT 363-6

2

G

G

5

QS1B

@

34

D

4.7K_04 02_5%

RS108

@

+3.3V_C C

1

1

2

2

@

RS107

4.7K_04 02_5%

179F_S MB_CK2

+5VALW

1

@

RS111

100K_0 402_5%

2

EC_TYPEC _EN#<39 >

EC need change t o low act i v e

A A

EC_SMB _DA2< 19,25,39,44>

5

S

61

D

2N7002 KDW_SOT 363-6

QS1A

@

2

RS114 0_0 402_5%@

2

RS115 0_0 402_5%@

179F_S MB_DA2

Security Classification

Security Classification

1

1

4

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

1

CS95

+

TYPEC@

2

VBUS_E N_179

2

G

2017/12 /18 2018/09 /01

2017/12 /18 2018/09 /01

2017/12 /18 2018/09 /01

3

+5VALW

CS96

0.1U_0402_10V6K

1

TYPEC@

2

footprint : G518

6

PN : SA0000BD N00(SILERGY SY686 1B1)

D

2N7002 KDW_SOT 363-6
QS3A

@

S

1

US11

TYPEC@

6

IN

OUT

5

RSET

SET

GND

4

FLAG

EN

SY6861B1 ABC_TSOT23 -6

D

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

1

2

3

3

S

QS3B

4

2N7002 KDW_SOT 363-6

+USB3_ VCCC

1 2

@

RS112
0_0402 _5%

5

G

pop for intel sensitive net
(1.0)

@

2

RSET

6.2K_04 02_5%

TYPEC@

2N7002 KDW_SOT 363-6

CS97

0.1U_0402_25V6

1

@

2

1

CS100

0.1U_02 01_10V6K

2

RS113

1

2

RS109

8.2K_04 02_5%

TYPEC@

QS4A

TYPEC@

1

2

6

D

1

1

RS110

4.3K_04 02_5%

TYPEC@

2
3

D

5

G

S

QS4B

TYPEC@

4

2N7002 KDW_SOT 363-6

2

G

S

G518 M OS Current Limi t

1

2

GPP_B 1

(TYPEC_3A)

22U_0805_25V6M

GPP_B 4

(TYPEC_1P5A)

L L

L

H

*H

CS98

CS99

22U_0805_25V6M

1

@

@

2

USB_OC 0# <15>

RSET(kΩ ) MODE

H

L

H

limit point

6.2

3.53

2.54

1.94

0.9A

1.5A

2A

3A

Initial Current mode selection

VBUS_EN _179 EC_TY PEC_EN#

L

L

H

H

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

Dat e: Sheet

Dat e: Sheet

Dat e: Sheet

Compal Electronics, Inc.

CC+USB TYPE C

CC+USB TYPE C

CC+USB TYPE C

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

H

L

H

L

1

TYPEC_3A <19>

TYPEC_1P 5A <1 7>

checked bios

1.09A

1.92A

2.67A

3.5A

V BUS

0

0

0

1

40

40

40

o f

o f

o f

1.0

1.0

1.0

67Thursday, Febru ary 22, 2018

67Thursday, Febru ary 22, 2018

67Thursday, Febru ary 22, 2018

B

5

4

3

2

1

USB3.0 (Port 3)

D

USB3_P TX_DRX_P2<18>

USB3_P TX_DRX_N2<18>

USB3_P RX_DTX_P2<18>

USB3_P RX_DTX_N2<18>

Change to 0201 for placement.

1

RS64 0_0 201_5%@

1 2

RS65 0_0 201_5%@

2

USB3_P TX_L_DRX_P 2

USB3_P TX_L_DRX_N 2

USB3_P RX_DTX_P2

USB3_P RX_DTX_N2

USB3.0 (Port 4)

EMC@

USB3_P TX_L_DRX_P 3

USB3_P TX_L_DRX_N 3

USB3_P RX_DTX_P3

USB3_P RX_DTX_N3

1

1

4

4

1 2

USB3_P TX_DRX_P3<18>

USB3_P TX_DRX_N3<18>

USB3_P RX_DTX_P3<18>

USB3_P RX_DTX_N3<18>

C C

USB20_ P2<1 5>

USB20_ N2<15>

RS82 0_0 201_5%@

RS83 0_0 201_5%@

USB20_ P2

USB20_ N2

1 2

2

3

DLM0NS N900HY2D_4P

2

3

LS10

USB20_ P2_L

USB20_ N2_L

1A modify

1 2

CS58 0.22U _0402_16V7 K

1

2

CS59 0.22U _0402_16V7 K

1 2

RS74 0_0 201_5%@

1 2

RS76 0_0 201_5%@

1A modify

1 2

CS60 0.22U _0402_16V7 K

1 2

CS61 0.22U _0402_16V7 K

1 2

RS84 0_0 201_5%@

1 2

RS85 0_0 201_5%@

USB3_P TX_C_DRX_P 2

USB3_P TX_C_DRX_N 2

USB3_P RX_L_DTX_P 2

USB3_P RX_L_DTX_N 2

USB3_P TX_C_DRX_P 3

USB3_P TX_C_DRX_N 3

USB3_P RX_L_DTX_P 3

USB3_P RX_L_DTX_N 3

For ESD request

DS3

USB3_P TX_L_DRX_P 2

USB3_P TX_L_DRX_N 2

CC1_VC ONN CC1_VCON N

TBTA_S BU1 TBTA_S BU1

USB3_P TX_L_DRX_P 3 USB3_PTX _L_DRX_P3 USB3_P RX_L_DTX_P 2USB3 _PRX_L_DTX _P2

EMC@

1

2

4

5

3

TVW DF1004AD0_ DFN9

SC300003Z00

DS4

EMC@

1

2

4

5

3

TVW DF1004AD0_ DFN9

USB3_P TX_L_DRX_P 2

9

USB3_P TX_L_DRX_N 2

8

7

6

9

8

USB3_P TX_L_DRX_N 3USB3_P TX_L_DRX_N 3

7

6

USB20_ P2_L USB2 0_P2_L

USB20_ N2_L USB20_ N2_L

USB3_P RX_L_DTX_N 3

USB3_P RX_L_DTX_P 3

CC2_VC ONN

SC300003Z00

DS6

EMC@

1

2

4

5

3

TVW DF1004AD0_ DFN9

SC300003Z00

DS5

EMC@

1

2

4

5

3

TVW DF1004AD0_ DFN9

SC300003Z00

9

8

USB3_P RX_L_DTX_N 3

7

USB3_P RX_L_DTX_P 3

6

CC2_VC ONN

9

TBTA_S BU2TBTA_S BU2

8

USB3_P RX_L_DTX_N 2USB3_P RX_L_DTX_N 2

7

6

SM070005U00

add topology for intel ECN_Update (1.0)

USB3_P RX_L_DTX_P 2

USB3_P RX_L_DTX_N 2 USB3_P RX_C_DTX_N 2

B

USB3_P RX_L_DTX_P 3

USB3_P RX_L_DTX_N 3

1 2

CS102 0.3 3U_0402_10 V6K

1 2

CS103 0.3 3U_0402_10 V6K

RS119
220K_0 402_5%

1 2

CS104 0.3 3U_0402_10 V6K

1

CS105 0.3 3U_0402_10 V6K

2

RS121
220K_0 402_5%

USB3_P RX_C_DTX_P 2

1

1

RS120
220K_0 402_5%

2

2

USB3_P RX_C_DTX_P 3

USB3_P RX_C_DTX_N 3

1

1

RS122
220K_0 402_5%

2

2

CS13

10U_08 05_25V6K

USB3_P TX_C_DRX_P 2
USB3_P TX_C_DRX_N 2

1

2

2

1

CC1_VC ONN<40>

3

DS19

EMC@

MESC5V 02BD03_SOT 23-3

0.1U_04 02_25V6

2

USB20_ P2_L
USB20_ N2_L USB20_ P2_L

TBTA_S BU1

USB3_P RX_C_DTX_N 3
USB3_P RX_C_DTX_P 3

+USB3_ VCCC +USB3_ VCCC

JTYPEC1

A1

GND

A2

SSTXP1

A3

1

CS840.1U_040 2_25V6

12

CS86

SSTXN1

A4

VBUS

A5

CC1

A6

DP1

A7

DN1

A8

SBU1

A9

VBUS

A10

SSRXN2

A11

SSRXP2

A12

GND

1

GND

2

GND

3

GND

4

GND

LOTES_ AUSB0249-P0 01A

CONN@

GND

SSRXP1

SSRXN1

VBUS

SBU2

DN2
DP2

CC2

VBUS

SSTXN2

SSTXP2

GND

GND
GND
GND
GND

B12

B11

B10

B9

B8

B7
B6

B5

B4

B3

B2

B1

5
6
7
8

USB3_P RX_C_DTX_P 2
USB3_P RX_C_DTX_N 2

1 2

CS87 0.1U_0 402_25V6

TBTA_S BU2

USB20_ N2_L

CC2_VC ONN <40>

2

1

CS85 0.1U_0 402_25V6

USB3_P TX_C_DRX_N 3
USB3_P TX_C_DRX_P 3

Follow intel #575549 for ESD/EOS protection.

A A

CC1_VCONN & CC2_VCONN need 20miil trace width.

Security Classification

Security Classification

Security Classification

2017/12 /18 2018/09 /01

2017/12 /18 2018/09 /01

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

5

4

2017/12 /18 2018/09 /01

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number R ev

Size Document Number R ev

Size Document Number R ev

Custom

Custom

Custom

Dat e: Sheet o f

Dat e: Sheet o f

2

Dat e: Sheet o f

Compal Electronics, Inc.

CC+USB TYPE C

CC+USB TYPE C

CC+USB TYPE C

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

41

41

41

1

1.0

1.0

1.0

67Thursday, Febru ary 22, 2018

67Thursday, Febru ary 22, 2018

67Thursday, Febru ary 22, 2018

D

B

A

USB3.0 /2.0 CMC

B

C

D

E

USB3_P TX_C_DRX_P 1

USB3_P TX_DRX_P1<18>

1

USB3_P TX_DRX_N1<18>

USB3_P RX_DTX_P1<18>

USB3_P RX_DTX_N1<18>

1 2

CS2 .1U_ 0402_16V7K

USB3_P TX_C_DRX_N 1

1 2

CS3 .1U_ 0402_16V7K

USB3_P RX_DTX_P1

USB3_P RX_DTX_N1

1 2

RS90 0_04 02_5%@

1 2

RS91 0_04 02_5%@

1 2

RS86 0_04 02_5%@

1

RS89 0_04 02_5%@

2

USB3_P RX_L_DTX_P 1

USB3_P RX_L_DTX_N 1

ESD request

DS1

USB3_P TX_L_DRX_P 1

USB3_P TX_L_DRX_N 1

USB3_P RX_L_DTX_P 1

USB3_P RX_L_DTX_N 1

2 2

EMC@

1

2

4

5

3

TVW DF1004AD0_ DFN9

USB3_P TX_L_DRX_P 1

9

USB3_P TX_L_DRX_N 1

8

USB3_P RX_L_DTX_P 1

7

USB3_P RX_L_DTX_N 1

6

USB3_P TX_L_DRX_P 1

USB3_P TX_L_DRX_N 1

+USB3_ VCCA

U2DP1

U2DN1

DS2

EMC@

6

I/O4

5

VDD

4

I/O3

AZC099 -04S.R7G_SOT 23-6

I/O2

GND

I/O1

3

2

1

2

3

U2DN1_ L

U2DP1_ L

DLM0NS N900HY2D_4P

2

3

LS1

EMC@

1

4

SM070005U00

U2DP1_ L

1

U2DN1_ L

4

+USB3_ VCCA

W=100 mil s

2

1

EMC@

+

2

CS6
.1U_040 2_16V7K

1

U2DN1_ L
U2DP1_ L

USB3.0 Conn.

JUSB1

1

VBUS

2

D-

3

D+

4

GND

5

SSRX-

6

SSRX+

7

GND

8

SSTX-

9

SSTX+

ACON_T ARB5-9V1391

CONN@

DC23300NH00

GND
GND
GND
GND

10
11
12
13

150U_D 2_6.3VM_R17 M

CS5

SGA000 09000

USB3_P RX_L_DTX_N 1
USB3_P RX_L_DTX_P 1

USB3_P TX_L_DRX_N 1
USB3_P TX_L_DRX_P 1

SC300003Z00

USB Host Charger

3

+5VALW

CHG@

1

@

1 2

2

RS14 10K_ 0402_5%

RS15 10K_ 0402_5%

CHG_CT L2

CHG_ILMS EL

+5VALW

RS8 0_12 06_5%@

USB_OC 1#<15>

USB_OC 1#

CS8

0.1U_02 01_10V6K

1

2

@

0904 vendor recommend

1 2

RS11

0_0402 _5%

@

22U_0603_6.3V6M

1

CS9

@

12

CHG@

2

USB20_ N1<15>

USB20_ P1<1 5>

CHG_ILMSEL<39>

CHG_EN<39>

CHG_CTL1<39>

CHG_CTL3<39>

.1U_0402_16V7K

1

2

CHG_ILMS EL

CHG_EN

CHG_CT L1
CHG_CT L2
CHG_CT L3

CS7

+5VALW _CHG

US12

CHG@

1

VIN

2

DM_OUT

3

DP_OUT

13

FAULT#

4

ILIM_SEL

5

EN

6

CTL1

7

CTL2

8

CTL3

SLGC55 544CVTR_TQ FN16_3X3

DM_IN

ILIM_L

ILIM_HI

Thermal Pad

VOUT

DP_IN

GND

22.1K_0402_1%

1

RS12

CHG@

2

+USB3_ VCCA

U2DP1
U2DN1

0831 Reserve ILIM_L R as vendor recommend

1

39K_0402_1%

RS13

@

2

12

10
11

15
16

9

NC

14
17

1

3

0911 Rerserve PU, vendor suggest to EC control
if future need support SDP2

ILM R vaule
Ios(mA)=50250/R(Kohm)
ILIM_Hi=2273 mA
ILIM_L=1288mA(reserve )

4 4

USB Host Charger Truth Table

CHG_EN

0

1

1

1

CTL1

CTL2 CTL3 ILIM_SEL

0 1 10

0

0 1 1 1

1 111

A

101

MODE

SDP1-OFF

SDP1

DCP
Au to

CDP

Current Limit
Setti ng

ILIM_H

ILIM_H

ILIM_H

ILIM_H

Note

Port power off

Data Lines Connected

Data Lines Disconnected

Data Lines Connected

B

Security Classification

Security Classification

Security Classification

2017/12 /18 2018/09 /01

2017/12 /18 2018/09 /01

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

2017/12 /18 2018/09 /01

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number R ev

Size Document Number R ev

Custom

Custom

Custom

Dat e: Sheet

Dat e: Sheet

Dat e: Sheet o f

Compal Electronics, Inc.

USB3.0 Conn/USB Charger

USB3.0 Conn/USB Charger

USB3.0 Conn/USB Charger

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

E

o f

o f

42 67Thursday, Febru ary 22, 2018

42 67Thursday, Febru ary 22, 2018

42 67Thursday, Febru ary 22, 2018

1.0

1.0

1.0

A

B

SATA Re-Driver and cable HDD Conn.

C

D

E

co-lay w/o re-driver

1 2

RO24

0_0402 _5% SATANRD@

1

1

SATA_P TX_DRX_P4<18>

SATA_P TX_DRX_N4<18>

SATA_P RX_DTX_N4<18>
SATA_P RX_DTX_P4<18>

+3VS

1 2

RO6 4.7K_0402 _5%@

1 2

RO8 4.7K_0402 _5%

2 2

3

4 4

@

1 2

RO10 4.7K_040 2_5%@

1 2

RO11 4.7K_040 2_5%@

1 2

RO12 4.7K_040 2_5%@

1

RO13 4.7K_040 2_5%@

1 2

RO14 4.7K_040 2_5%@

1 2

RO15 4.7K_040 2_5%@

1 2

RO16 4.7K_040 2_5%@

1 2

RO17 4.7K_040 2_5%@

1 2

RO18 4.7K_040 2_5%SAT ARD@

1 2

SATARD @

RO19 4.7K_040 2_5%

1 2

RO20 4.7K_040 2_5%SAT ARD@

RO23

0_0402 _5% SATANRD@

CO4 0.01U_0 402_16V7K

2

CO5 0.01U_0 402_16V7K

2

CO8 0.01U_0 402_16V7K

CO9 0.01U_0 402_16V7K

1 2

RO22

0_0402 _5% SATANRD@

1 2

RO21

0_0402 _5% SATANRD@

2

A

SATA_P TX_C_DRX_P 4_NRD

SATA_P TX_C_DRX_N 4_NRD

2

SATARD @
SATARD @

SATA_P TX_C_DRX_P 4

12

SATA_P TX_C_DRX_N 4

1

SATA_P RX_C_DTX_N 4

1

SATA_P RX_C_DTX_P 4 RDSATA _PRX_DTX_P 4

12

SATARD @

SATARD @

SATA_P RX_C_DTX_N 4_NRD

SATA_P RX_C_DTX_P 4_NRD

A_DE

B_DE

B_EQ1

A_EQ1

A_EQ2

B_EQ2

DEW

A_DE

B_DE

B_EQ1

A_EQ1

A_EQ2

B_EQ2

+3VS

0.01U_0 402_16V7K

RO7

4.99K_0 402_1%

+3VS

CO1

1

2

SATARD @

SATARD @

1 2

4.7K_04 02_5%

20

1

A_INP

2

A_INN

3

GND1

4

B_OUTN

5

B_OUTP

21

GND2

6

12

RO9

@

USE 8527 re-driver
SA000 07JU 10

B

A_EQ1

B_EQ1

A_EQ2

DEW

18

VDD2

A_EQ1

B_EQ1

A_EQ2

REXT

EN

A_DE

B_DE

9

7

8

A_DE

B_DE

PS8527 CTQFN20GTR 2A_TQFN20_ 4X4

SATARD @

DEW

15

A_OUTP

14

A_OUTN

13

B_EQ2

12

B_INN

11

B_INP

VDD1

10

0.1U_0201_10V6K

SATARD@

+3VS

CO10

1

2

RDSATA _PTX_DRX_P 4

RDSATA _PTX_DRX_N 4

B_EQ2

RDSATA _PRX_DTX_N 4

@

JPO1

2

112

JUMP_4 3X79

JPO2

@

2

112

JUMP_4 3X79

GND GND

+3VS + 5VS_HDD

1

CO11

0.1U_02 01_10V6K

2

@

RDSATA _PRX_DTX_P 4

RDSATA _PRX_DTX_N 4

RDSATA _PTX_DRX_N 4

RDSATA _PTX_DRX_P 4

SATA_P RX_C_DTX_P 4_NRD

SATA_P RX_C_DTX_N 4_NRD

SATA_P TX_C_DRX_N 4_NRD

SATA_P TX_C_DRX_P 4_NRD

10U_0603_6.3V6M

1

2

CO7 0.01U_040 2_16V7K

CO6 0.01U_040 2_16V7K

CO3 0.01U_040 2_16V7K

CO2 0.01U_040 2_16V7K

CO16 0.01U_040 2_16V7K

CO14 0.01U_040 2_16V7K

CO17 0.01U_040 2_16V7K

CO18 0.01U_040 2_16V7K

UO1

16

19

17

+5VS

100mils

CO12

1

CO13

0.1U_02 01_10V6K

2

@

1 2

@

RO5 0_0402_5 %

1 2

SATARD @

1 2

SATARD @

1 2

SATARD @

1

2

SATARD @

1

2

SATANR D@

1 2

SATANR D@

1

2

SATANR D@

1 2

SATANR D@

RO4

1 2

0_0805 _5%

+5VS_H DD

G_INT2_R

JHDD_P 8

RDSATA_PRX_ C_DTX_P4
RDSATA_PRX_ C_DTX_N4

RDSATA_PTX_ C_DRX_N4
RDSATA_PTX_ C_DRX_P4

+3VS

+5VS_H DD

G_INT2_RG_INT2

JHDD_P 8

RDSATA_PRX_ C_DTX_P4
RDSATA_PRX_ C_DTX_N4

RDSATA_PTX_ C_DRX_N4
RDSATA_PTX_ C_DRX_P4

FFC Type

JHDD1

14

GND

13

GND

12

12

11

11

10

10

9

9

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

ACES_5 1625-01201-0 01

CONN@

SP010028W00

Cable Type

JHDD2

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

G1

22

G2

23

G3

24

G4

ACES_5 0406-02071-0 01

CONN@

SP010016L00

co-lay w/o re-driver

+3VS

1

RZ1
10K_04 02_5%

GSEN@

2

D_CK_S CLK<19,23,24 >

D_CK_S DATA<19,23,24>

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

2017/12 /18 2018/09 /01

2017/12 /18 2018/09 /01

2017/12 /18 2018/09 /01

C

RZ2 10 K_0402_5%@

+3VS

RZ3 10 K_0402_5%GSEN @

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

1
1

2

UZ1

8

CS

4

SCLSPC

6

SDA/SDI/SDO

7

SDO/SA0

16

ADC1

15

ADC2

13

ADC3

2

NC

3

NC

LIS3DHTR _LGA16_3X3

GSEN@

LIS 3DH
SA0 ->0 , Addre ss is 0011 00 0 (0x3 0h)
SA0 ->1 , Addre ss is 0011 00 1 (0x3 2h)

D

G-Sensor

Vdd_IO

Vdd

INT1
INT2

RES

GND
GND

Title

Title

Title

Size Document Number R ev

Size Document Number R ev

Size Document Number R ev

Custom

Custom

Custom

Dat e: Sheet o f

Dat e: Sheet o f

Dat e: Sheet o f

+3VS

GSEN@

1

14

G_INT

11

G_INT2

9

10

5
12

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

HDD/ Re-Driver/ G-sensor

HDD/ Re-Driver/ G-sensor

HDD/ Re-Driver/ G-sensor

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

1

2

CZ1

CZ2

INT1/2 all High Active

1 2

0.1U_02 01_10V6K

G_INT <20>

10U_06 03_6.3V6M

GSEN@

E

1.0

1.0

1.0

43 67Thursday, Febru ary 22, 2018

43 67Thursday, Febru ary 22, 2018

43 67Thursday, Febru ary 22, 2018

1

3

A

B

C

D

E

JIO2

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

21

22

22

23

23

24

24

25

25

26

26

27

GND

28

GND

ACES_5 1522-02601-0 01

CONN@

SP01001AO00

HPOUT_ L_1<38 >
HPOUT_ R_1<38 >
SLEEVE<38>
RING2<38 >

HP_PLU G#<38>

BATT_A MB_LED#<39>

BATT_B LUE_LED#<39>

PWR _SUSP_LED#<39>

PWR _LED#<39>

USB_EN<39>

+5VALW

USB3_P RX_DTX_N4<18>
USB3_P RX_DTX_P4<18>

USB3_P TX_DRX_N4<18>
USB3_P TX_DRX_P4<18>

USB3_P RX_DTX_N5<18>
USB3_P RX_DTX_P5<18>

USB3_P TX_DRX_N5<18>
USB3_P TX_DRX_P5<18>

GNDA

HPOUT_ L_1
HPOUT_ R_1

SLEEVE
RING2

HP_PLU G#

SUB_PIN7

USB20_ L_P3
USB20_ L_N3

USB20_ L_P4

USB20_ L_N4

BATT_AMB_LE D#
BATT_BLUE_L ED#
PWR_SU SP_LED#
PWR _LED#

USB_EN

To USB/B FPC BTB CONN

USB20_ P3<1 5>

USB20_ N3<15>

1

USB20_ P4<1 5>

USB20_ N4<15>

USB20_ P3

USB20_ N3

USB20_ P4

USB20_ N4

DLM0NS N900HY2D_4P

2

2

3

3

LS11

EMC@

SM070005U00

DLM0NS N900HY2D_4P

1

1

4

4

LS12

EMC@

USB20_ L_P3

1

1

USB20_ L_N3

4

4

USB20_ L_P4

2

2

USB20_ L_N4

3

3

+5VALW

SM070005U00

2 2

GNDA

HPOUT_ L_1

HPOUT_ R_1
SLEEVE

RING2
HP_PLU G#

SUB_PIN7

USB20_ L_P3
USB20_ L_N3

USB20_ L_P4
USB20_ L_N4

BATT_AMB_LE D#
BATT_BLUE_L ED#
PWR_SU SP_LED#
PWR _LED#

USB_EN

USB3_P RX_DTX_N4
USB3_P RX_DTX_P4

USB3_P TX_DRX_N4

USB3_P TX_DRX_P4

USB3_P RX_DTX_N5
USB3_P RX_DTX_P5

USB3_P TX_DRX_N5
USB3_P TX_DRX_P5

pop for 40 pin SUB/B

+3VALW

1

R227 0_0402 _5%@

1

R228 0_0402 _5%

2

2

SUB_PIN7

JIO3

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

21

22

22

23

23

24

24

25

25

26

26

27

27

28

28

29

29

30

30

31

31

32

32

33

33

34

34

35

35

36

36

37
38
39
40

G1

37

G2

38

G3

39

G4

40

G5

ACES_5 0398-04041-0 01

CONN@

SP010013I00

To Hall sensor/B

+3VLP

JHS1

1

LID_SW#< 39>

41
42
43
44
45

LID_SW #

1

2

2

3

3

4

4

5

GND

6

GND

ACES_5 1524-0040N-0 01

CONN@

SP010022M00

1

THERMAL SENSOR

3

+3VS

+3VS +3 VS

1

1

2.2K_04 02_5%

2

G

D

RF10

TMS@

S

5

TMS@

G

2N7002 KDW_SOT 363-6

EC_SMB _CK2< 19,25,39,40>

EC_SMB _DA2< 19,25,39,40>

4 4

A

QF1B

3

D

TMS@

2N7002 KDW_SOT 363-6

QF1A

4

S

6 1

2

2

RF9

2.2K_04 02_5%

TMS@

TMS_SM B_CLK

TMS_SM B_DATA

B

1 2

CF11 2200P_ 0402_50V7K

+3VS

RF6 10 K_0402_5%TM S@

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

TMS@

TMS@

1 2

0.1U_0201_10V6K

1

2

CF4

H_THER MDA

H_THER MDC

CPU_TH ERM#

Thermal sensor SMBus address

-->100-1_100xb : 0x4C
(x=0)Write Address(0x98h)
(x=1)Read Address(0x99h)

SA0000 67P00

UF1

1

VDD

2

3

NCT771 8W_MSOP 8

TMS@

2017/12 /18 2018/09 /01

2017/12 /18 2018/09 /01

2017/12 /18 2018/09 /01

C

SCLK

D+

SDATA

ALERT#

D-

THERM#4GND

Compal Secret Data

Compal Secret Data

Compal Secret Data

TMS_SM B_CLK

8

TMS_SM B_DATA

7

THERMA L_ALERT#

6

5

Deciphered Date

Deciphered Date

Deciphered Date

+3VS

1

RF8
10K_04 02_5%

2

D

TMS@

THERMA L_ALERT# < 39>

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number R ev

Size Document Number R ev

Size Document Number R ev

Custom

Custom

Custom

Dat e: Sheet o f

Dat e: Sheet o f

Dat e: Sheet

Compal Electronics, Inc.

FUN/B & LED/B

FUN/B & LED/B

FUN/B & LED/B

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

E

44 67Thursday, Febru ary 22, 2018

44 67Thursday, Febru ary 22, 2018

44 67Thursday, Febru ary 22, 2018

o f

1.0

1.0

1.0

3

ON/OFF BTN

1

ON/OFFBTN#<39>

Test Only

BOT

A

R17

+3VLP

100K_040 2_5%

SW1

@

EVQPLDA15_4P

1

2

B

KB Conn.

KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6

KSO7

KSO8

KSO9
KSO10
KSO11
KSO12

KSO13
KSO14

KSO15
KSO16

KSO17

KSI0

KSI1

KSI2

KSI3

KSI4

KSI5

KSI6

KSI7

JKB1

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

21

22

22

23

23

24

24

25

25

26

26

27

27

GND

28

28

GND

29

29

30

30

31

31

32

32

ACES_50596 -03201-P01

CONN@

33
34

CAPS_LED#<39 >

+5VS

NUM_LED#<3 9>

12

ON/OFFBTN#

3

4

5

6

1 2

RK1 1K_0402_ 5%

1 2

RK3 0_0402_5 %@

1 2

RK4 0_0402_5 %@

1 2

RK2 1K_0402_ 5%

PVT modify

ON/OFFBTN#

C

KSI[0..7]

KSO[0..17]

ON/OFFBTN#

KSO0
KSO1

KSO2
KSO3
KSO4

KSO5

KSO6
KSO7
KSO8

KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17

KSI0

KSI1

KSI2

KSI3

KSI4

KSI5

KSI6

KSI7

ACES_85201 -2805

SP01000GO00

KSI[0..7] <39>

KSO[0..17] <39>

30

GND2

29

GND1

28

28

27

27

26

26

25

25

24

24

23

23

22

22

21

21

20

20

19

19

18

18

17

17

16

16

15

15

14

14

13

13

12

12

11

11

10

10

9

9

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

CONN@

JKB2

KB
BackLight

+5VS

KBL_EN<39>

1 2

R18 0_0402_5%

D

JBL1

U4

5

IN

4

@

EN

SY6288C20AAC_ SOT23-5

OUT

GND

OC

0.1U_0201 _10V6K

+5VS_BL

1

2

3

1

C32

@

2

1

1

2

2

3

3

4

4

5

GND

6

GND

ACES_51524 -0040N-001

CONN@

SP010022M00

E

1

TPM

2 2

+3VALW +3VALW _TPM +3VS +3VS_TPM

1 2

R19 0_0 603_5%

3 3

SERIRQ PH 10K to +3VS at PCH side

10U_0603_6.3V6M

0.1U_0201_10V6K

C33

C34

1

1

R210_0402_5%

2

LPC_AD0

LPC_AD1
LPC_AD2

LPC_AD3

near

TPM@

pin1

SELECTION

AEh(write) ,
AFh(read)

TPM_BADD

CLK_LPC_ TPM_R

LPC_FRAME#

PLT_RST #

TPM_SERIRQ

PM_CLKRU N#

2

TPM@

BADD

1

*

1 2

@

LPC_AD0<18 ,39>
LPC_AD1<18 ,39>
LPC_AD2<18 ,39>
LPC_AD3<18 ,39>

CLK_LPC_ TPM_R<18>

LPC_FRAME#<1 8,39>

PLT_RST #<17>
TPM_SERIRQ<18,39>
PM_CLKRU N#<19>

P/N:SA00008ELC0 (S IC NPCT650ABBYX QFN 32P TPM2.0 FW 1.3.1.0)

CLKRUN# PH 10K to +3VS at PCH s ide

LPCPD# had interna l PH

CLK_LPC_ TPM_R

R22 33_ 0402_5%

1 2

R20 0_0 603_5%

U5

TPM@

29

XOR_OUT/SDA/GPIO0

30

SCL/GPIO1

3

GPX/GPIO2

6

GPIO3/BADD

24

LAD0/MISO

21

LAD1/MOSI

18

LAD2/SPI_IRQ#

15

LAD3

19

LCLK/SCLK

20

LFRAME#/SCS#

17

LRESET#/SPI_RST#/SRESET#

27

SERIRQ

13

CLKRUN#/GPIO4/SINT#

28

LPCPD#

4

PP

5

TEST

NPCT650 LA0YX_QFN32_5X5

XEMC@

1 2

1

2

TPM@

VSB

VDD1
VDD2
VDD3

NC1
NC2
NC3
NC4
NC5
NC6
NC7

GND1
GND2
GND3
GND4

PGND

Reserved

XEMC@

1 2

C39 22P_0402_5 0V8J

1

2

2

TPM@

near
pin8,14 ,22

1

8
14
22

2
7
10
11
25
26
31

9
16
23
32
33
12

C36

0.1U_0201_10V6K

10U_0603_6.3V6M

C35

1

C37

0.1U_0201_10V6K

1

2

TPM@

+3VALW_T PM

C38

0.1U_0201_10V6K

TPM@

+3VS_TPM

Touch Pad

4.7U_0402_6.3V6M

TP_PWR_EN follow SYSON behavior

2N7002KD W_SOT363- 6

I2C_1_SCL<20>

I2C_1_SDA<2 0>

CK2

1

1

2

3

2

TP_PWR_EN<39>

+3V_PTP +3V_PTP

2

QK1A

6

D

1 2

@

RK12 0_040 2_5%

2N7002KD W_SOT363- 6

RK13

UK1

OUT

GND

OC

SY6288C20AAC_ SOT23-5

G

1

S

QK1B

1

IN

EN

2.2K_0402 _5%

5

G

3 4

D

2

5

4

0_0402_5 %@

+3V_PTP

+3VALW+3V_PTP

+3V_PTP

2

CK3

1U_0402_ 6.3V6K

1

1

1

RK8

S

RK9

2.2K_0402 _5%

2

2

I2C_1_SCL_ R

I2C_1_SDA_R

2

RK7
10K_0402 _5%

1

EC_TP_INT #

+3VALW

+3VS

EC_TP_INT#<17,39>

@

RK50_0402_5%

2

@

RK60_0402_5%

CK1

@

0.1U_0201 _10V6K

2

EC PS2

PCH I2C

TP_EN<39 >

12

1

1

TP_CLK
TP_DATA

I2C_1_SDA_R
I2C_1_SCL_ R

EC_TP_INT #
TP_EN

RK10

4.7K_0402 _5%

TP_CLK
TP_DATA

+3V_PTP

1

2

10

1

RK11

4.7K_0402 _5%

2

1
2

3
4
5
6
7
8
9

JTP1

1
2

3
4
5
6
7
8
GND
GND

ACES_51524 -00801-001

CONN@

SP01001A910

TP_CLK <39>
TP_DATA <39>

4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2017/12/18 2018/09/01

2017/12/18 2018/09/01

2017/12/18 2018/09/01

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number R ev

Size Document Number R ev

Size Document Number R ev

Custom

Custom

Custom

Dat e: Sheet

Dat e: Sheet of

D

Dat e: Sheet of

Compal Electronics, Inc.

KB & TP & TPM Connector

KB & TP & TPM Connector

KB & TP & TPM Connector

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

E

45 67Thursday, Febru ary 22, 2018

45 67Thursday, Febru ary 22, 2018

45 67Thursday, Febru ary 22, 2018

of

4

1.0

1.0

1.0

+5VS

RF4 0_0603_5%

RF7 0_0603_5%

1

1000P_04 02_50V7K

FAN_SPEED1<39>

FAN_SPEED2<39>

CF6

2

@

@

+3VS

1

RF3
10K_0402 _5%

2

1

CF7
1000P_04 02_50V7K

XEMC@

2

+3VS

1

RF5
10K_0402 _5%

2

1

CF10
1000P_04 02_50V7K

XEMC@

2

1

CF5
10U_0603 _6.3V6M

2

FAN_PWM1<39>

FAN_PWM2<39>

Reset Circuit

BI_GATE PH to +RTCVCC at PWR
side

BI_GATE<49>

change PN to SN10000CV00

BI_GATE

Reset Button

SW3

BI_GATE BI_GATE

1 2

3 4

SKRPABE010_ 4P

SN10000CV00

1 2

@

1 2

@

Q1B

5

G

+VCC_FAN1

+VCC_FAN2

2

CF13

4.7U_0603 _10V6K

1

+VCC_FAN1

FAN_PWM1

1

CF12

4.7U_0603 _10V6K

2

+VCC_FAN2

FAN_PWM2

+3VLP

2

1

1

3

D

2

2N7002KD W_SOT363- 6

S

4

40mil

FAN Conn

JFAN1

1

1

2

2

3

3

4

4

5

G1

6

G2

ACES_50278 -00401-001

CONN@

SP02000RR00

JFAN2

1

1

2

2

3

3

4

4

5

G1

6

G2

ACES_50278 -00401-001

CONN@

SP02000RR00

R25
10K_0402 _5%

Q1A

BI_GATE#

2

G

C40

0.1U_0201 _10V6K

BI SW

SW2

3

4

ATE-2-V-TR_4 P

H : 3.8mm

Release : Battery Off
Push : Battery ON

1 2

@

R23 0_0402_5%

1

@

R24 0_0402_5%

61

D

2N7002KD W_SOT363- 6

S

@

1

2

Screw
Hole

H23

H27

@

H_2P7x2P0N

1

+FP_VCC

@

H24

@

H_3P2

H_3P2

1

1

H28

@

H29

@

H_2P7x2P0N

H_2P0N

1

1

1

FP@

CK5

4.7U_0402 _6.3V6M

2

DK1

FPEMC@

6

I/O4

+FP_VCC

PIN

5

VDD

4

I/O3

AZC099-04S.R 7G_SOT23-6

ETU 801 FA577 E-120 0

+FP_VCC (5 V) +FP _VCC (3 V)

1

USB P

2

USB N

3

GND

4

NC

5

NC

6
7
8

FD1

@

1

FIDUCIAL_C40M8 0

FD3

@

1

FIDUCIAL_C40M8 0

3

I/O2

2

GND

1

I/O1

D+
D­GND
NC
NC
NC
NC

FIDUCIAL_C40M8 0

FIDUCIAL_C40M8 0

USB20_P8_ L

USB20_N8 _L

FD2

@

1

FD4

@

1

H2

@

H_3P0

@

H_6P0

@

H3

@

H1

H_3P0

H_2P5

1

1

H14

H15

@

H_3P7

1

H5

@

H4

@

H_3P0

1

H21

@

H_3P7

1

H7

@

H_3P0

H_4P0

@

H_3P7

1

1

H22

H12

@

H_3P7

1

1

1

1

@

H_6P4

H8

@

H_3P7

H9

@

H6

@

H_4P0

H_4P0

1

1

H13

1

@

H_3P7

1

H26

@

H25

H_3P7

1

1

Finger Print

+3VALW

FP@

1 2

RK14 0_040 2_5%

+5VALW

1 2

RK15 0_040 2_5%@

1U_0402_ 6.3V6K

FP_PWR_EN<39>

MAINPWON <39,51>

2

EC_RST# <39>

BI_S <49>

USB20_N8<15>

USB20_P8<15>

USB20_P8_ L

USB20_N8 _L

2

FP@

CK4

1

FP_PWR_ EN

1 2

@

RK16 0_0402 _5%

1 2

@

RK17 0_0402 _5%

+FP_VCC

JFP1

8

8

7

7

G2

6

6

G1

5

5

4

4

3

3

2

2

1

1

ACES_51522 -00801-001

CONN@

SP01001AE00

UK2

5

IN

4

EN

SY6288C20AAC_ SOT23-5

FP@

USB20_N8 _L

USB20_P8_ L

10
9

OUT

GND

1

2

3

OC

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2017/12/18 2018/09/01

2017/12/18 2018/09/01

2017/12/18 2018/09/01

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number R ev

Size Document Number R ev

Size Document Number R ev

Custom

Custom

Custom

Dat e: Sheet of

Dat e: Sheet

Dat e: Sheet of

Compal Electronics, Inc.

FAN & FP & Screw Hole

FAN & FP & Screw Hole

FAN & FP & Screw Hole

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

46 67Thursday, Febru ary 22, 2018

46 67Thursday, Febru ary 22, 2018

of

46 67Thursday, Febru ary 22, 2018

1.0

1.0

1.0

A

B

C

D

E

System DC inferface

@

1 2

CQ2 0.1U_020 1_10V6K

SUSP#

1

2 2

SUSP#<39,52,55>

1 2

RQ1 0_ 0402_5%

RQ2 0_ 0402_5%

2N7002KD W_SOT363- 6

10K_0402 _5%

12

@

1 2

CQ4 0.1U_02 01_10V6K

2

@

1

Place CQ7 close UQ1 pin 1&2
Place CQ8 close UQ1 pin 6&7

R27

@

100K_040 2_5%

SUSP

Q7A

2

G

@

1

R32

@

2

+5VALW +5VS

5VS_ON

+5VALW

3VS_ON

+3VALW

2

CQ7
1U_0402_ 6.3V6K

2

1

6

D

S

1

@

+0.6VS_VTT+5VALW

2

R28

@

100K_040 2_5%

1

discha rge
trace 20 mils

3

D

Q7B

S

2N7002KD W_SOT363- 6

4

1

G

CQ8
1U_0402_ 6.3V6K

5

SUSP

@

UQ1

1

VIN1

2

VIN1

3

ON1

4

VBIAS

5

ON2

6

VIN2

7

VIN2

EM5209VF_D FN14_2X3

SYSON<39,52,54>

14

VOUT1

13

VOUT1

1

12

CT1

CQ1 1000P_0 402_50V7K

11

GND

1 2

10

CT2

CQ3 1000P_0 402_50V7K

9

VOUT2

8

VOUT2

15

GPAD

SYSON

2N7002KD W_SOT363- 6

+5VS_OUT

2

+3VS_OUT

100K_040 2_5%

SYSON#

5

+3VS_OUT

2

1

R30

Q8B

G

@

JPQ2

@

112

JUMP_43X11 8

JPQ1

@

1

1

JUMP_43X11 8

CQ5

0.1U_0201 _10V6K

+1.2V_VDDQ+ 5VALW

2

@

@

1

3

D

S

4

2

2

+3VS

2

+5VS_OUT+3VALW +5VALW

2

CQ6

0.1U_0201 _10V6K

1

2

R29
100K_040 2_5%

1

discha rge
trace 20 mils

6

D

Q8A

2

SYSON#

G

S

2N7002KD W_SOT363- 6

1

@

For Power ON/Off Sequence

PM_SLP_S3

+3VALW

1

R37

100K_040 2_5%

2

Q11A

6

PM_SLP_S3 #<1 9,39>

PM_SLP_S4 #< 19,39>

2N7002KD W_SOT363- 6

2N7002KD W_SOT363- 6

2

G

R38

100K_040 2_5%

Q13A

2

G

S

1

D

+3VALW

S

1

2

6

D

1

PM_SLP_S4

P/N: SB00000EO00 footprint use SB00000ZU00

2

G

S

1

G

5

S

4

5

G

S

G

2

S

5

G

S

5

G

S

Q10A
2N7002KD W_SOT363- 6

6

D

EC_VCCST_ PG_R <11,39 >

MOW14, For tCPU28 200us(max)
SLP_S3# to VCCST_PWRGD deassertion

Q10B
2N7002KD W_SOT363- 6

3

D

Q11B
2N7002KD W_SOT363- 6

D

Q12A
2N7002KD W_SOT363- 6

D

Q12B
2N7002KD W_SOT363- 6

D

Q13B
2N7002KD W_SOT363- 6

D

VR_ON <39,55,56,5 7>

MOW14, For tPLT17 200us(max)
SLP_S3# to IMVP VR_ON deassertion

34

SUSP#

MOW14, For tPLT18 200us(max)
SLP_S3# to VCCIO VR disable

@

61

SYS_PWROK <19,3 9>

@

34

PCH_PW ROK <19,39>

34

SYSON

MOW14, For tPLT15 200us(max)
SLP_S4# to VDDQ ramp down

1

+1.05VALW TO +1.05V_VCCST /+1.8VALW TO +1.8VS +1.05VALW TO +1.05VS_VCCSTG

+1.05VALW

@

1 2

3 3

4

CQ15 0.1U _0201_10V6K

SYSON

RQ4 0_ 0402_5%

SUSP#

RQ8 0_ 0402_5%

CQ20 0.1U _0201_10V6K

+1.05VALW

2

1

1

2

@

2

1

2

CQ11
1U_0402_ 6.3V6K

1

Place CQ11 close UQ2 pin 1&2
Place CQ24 close UQ2 pin 6&7

EN_1.0V_VCCS TU

+5VALW

EN_1.8VS

+1.8VALW

+1.8VALW

2

CQ24
1U_0402_ 6.3V6K

1

A

UQ2

1

VOUT1

VIN1

2

VOUT1

VIN1

3

ON1

4

VBIAS

5

ON2

6

VIN2

VOUT2

7

VOUT2

VIN2

EM5209VF_D FN14_2X3

+1.05V_VCCST _OUT

14
13

12

1 2

CT1

CQ14 1000P_0402_ 50V7K

11

GND

1 2

10

CT2

CQ16 1000P_0402_ 50V7K

+1.8VS_OUT

9
8

15

GPAD

+1.05V_VCCST _OUT+1.05VALW

RQ5

RQ9 0_ 0603_5%

2

CQ9

0.1U_0201 _10V6K

1

B

1 2

1 2

+1.8VS_OUT

0_0603_5 %

2

CQ22

0.1U_0201 _10V6K

1

+1.05V_VCCST

+1.8VS

2

CQ12

1U_0402_ 6.3V6K

Issued Date

Issued Date

Issued Date

12

SUSP#

RQ3 0_ 0402_5%

Security Classification

Security Classification

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

1

+5VALW +1.05VS_VCCS TG

EN_1.0V_VCCS TG

1

@

CQ13

0.1U_0201 _10V6K

2

2017/12/18 2018/09/01

2017/12/18 2018/09/01

2017/12/18 2018/09/01

UC4

1

VIN1

2

VIN2

7

VIN thermal

3

VBIAS

4

ON

AOZ1334DI-01_D FN8-7_3X3

+1.0VS_VCCSTG: 60mA
R ON = 4.4m ohm
VDROP= 11mV
Delay time: 9.3us

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

VOUT

D

GND

6

5

+1.05VS_VCCS TG_OUT

1 2

RQ6 0_ 0603_5%

2

CQ10

0.1U_0201 _10V6K

1

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number R ev

Size Document Number R ev

Size Document Number R ev

Custom

Custom

Custom

Dat e: Sheet

Dat e: Sheet of

Dat e: Sheet of

Compal Electronics, Inc.

DC Interface

DC Interface

DC Interface

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

E

47 67Thursday, Febru ary 22, 2018

47 67Thursday, Febru ary 22, 2018

47 67Thursday, Febru ary 22, 2018

1.0

1.0

1.0

of

4

A

B

C

D

E

1 1

20160216 3PIN'+' 3PIN'-'

@

ACES_5029 9-00601-001

1

1

2

2

3

3

4

G7
G8

PJP101

4

5

5

6

6

7
8

2 2

4.7_1206_ 5%

EMI@

PC103

0.1U_0603 _25V7K

@

0_0402_5 %

1 2

PR102

PR101

1

1

2

1

2

PC102
100P_0402_50V8J

2

+3VLP

3

EMI@

FBMA-L11-201 209-800LMA5 0T

1 2

PL102

EMI@

FBMA-L11-201 209-800LMA5 0T

1 2

EMI@

EMI@

1000P_0402_50V7K

+CHGRTC

+19V_VIN+19V_ADPIN

1

PC104

2

SM01000P200 to comm part
SM01000U600

1

PR103

4.7_1206_ 5%

2

1

2

PC105

EMI@

0.1U_0603 _25V7K

PL101

change PL101PL102 from

3

4 4

A

Security Classification

Security Classification

Security Classification

2016/07/18 2017/06/14

2016/07/18 2017/06/14

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERT Y OF COMPAL ELEC TRONICS, INC. AN D CONTAINS CONFIDENT IAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERT Y OF COMPAL ELEC TRONICS, INC. AN D CONTAINS CONFIDENT IAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERT Y OF COMPAL ELEC TRONICS, INC. AN D CONTAINS CONFIDENT IAL

AND T RADE SECRET INFORMATION. THIS SHEET MAY N OT BE T RANSFERED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND T RADE SECRET INFORMATION. THIS SHEET MAY N OT BE T RANSFERED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND T RADE SECRET INFORMATION. THIS SHEET MAY N OT BE T RANSFERED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SH EET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SH EET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SH EET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY T HIRD PARTY WITHOUT PRIOR WR ITTEN C ONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY T HIRD PARTY WITHOUT PRIOR WR ITTEN C ONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY T HIRD PARTY WITHOUT PRIOR WR ITTEN C ONSENT OF COMPAL ELECTRONICS, INC.

B

2016/07/18 2017/06/14

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

C

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

DCIN

DCIN

DCIN

Size

Size

Size

Document N umber Re v

Document N umber Re v

Document N umber Re v

Custom

Custom

Custom

Dat e: Sheet

Dat e: Sheet

Dat e: Sheet o f

D

C5MMH M/B LAE911P

C5MMH M/B LAE911P

C5MMH M/B LAE911P

0.1

0.1

0.1

o f

o f

48 67Thursday, February 22, 2018

48 67Thursday, February 22, 2018

48 67Thursday, February 22, 2018

E

A

B

C

D

E

+3VLP

1 1

PR207 100_0402_1%

1 2

PR205 100_0402_1%

1

+12.6V_BATT+

FBMA-L11-201209-800LM A50T

FBMA-L11-201209-800LM A50T

1

PC201

EMI@

1000P_0402_50V7K

2

2

PR202

200K_0402_1%

1 2

1

PR203 1K_0402_1%

PL201

EMI@

1 2

PL202

EMI@

1 2

2

+3VLP

BI_GATE<46>

1

2

BATT_TEMP <39,50>

+12.6V_BATT

PC202

EMI@

0.01U_0402_25V7K

+RTCVCC

1

2

PR212
100K_0402_5%

2

G

EC_SMB_DA1 <39,50>

EC_SMB_CK1 <39,50>

2016/09/26
Change thePQ201 from
SB00000QO00 to SB00001GD00,

1

D

PQ201
LBSS139LT1G 1N SOT-23-3

S

3

1

2

PR217
0_0402_5%

BI_S <46>

<45 ,47 >

MAINPWON<39,51>

PR206

10K_0402_1%

1 2

MAINPWON

1

PR213

@

100K_0402_1%

2

ADP_I <39>

Battery Bot Side

PIN1 GND
PIN2 GND
PIN3 SMD
PIN4 SMC
PIN5 TEMP
PIN6 BI
PIN7 Batt+
PIN8 Batt+
PIN9 GND
PIN10 GND
SP0 20017H00

2

CVI LU_ CI 99 08 M2 HR 0- NH

3

MB:Battery Con Put BOT Side

PJP201

@

1

1

2

2

EC_SMB_DA1-1

3

3

EC_SMB_CK1-1

4

4

BATT_TS

5

5

BATT_B/I

6

6

7

7

8

8

9

GND

10

GND

CVILU_CI9908M2HR 0-NH

VCIN1_ADP_PROCHOT <39>

1

PC205

@

0.1U_0603_25V7K

2

PU201

@

1

TMSNS1

VCC

2

RHYST1

GND

3

OT1

TMSNS2

4

RHYST2

OT2

G718TM1U_SOT23-8

21.5K_0402_1%

8

7

6

5

@

10K_0402_1%

(Common Part)
SL20000 2H00

@

PR218

PR215

1

2

12

1

2

PH3 Near VGA.

When PR204=16.9K

For KB9022
OTP

89'C, 1V 56'C, 2VVCIN0_P H(V)

PH202(o hm) 7.3092K 26.1 1K

+3VLP_ECA

1

PR204

18.7K_0402_1%

2

@

26.7K_0402_1%

2

PR216

@

14K_0402_1%

100K_0402_1%_NCP15W F104F03RC

@

PH203

RecoveryActive

VCIN0_PH <39>

PR214

1

2

1

1

2

(Common Part)
SL20000 2H00

100K_0402_1%_NCP15W F104F03RC

@

PH202

2

3

PR208

10K_0402_1%

1

2

100K_0402_1%_NCP15W F104F03RC

T202@

T201@

PH201

1

2

PC203 must close to EC pin

2

PC203

@

0.1U_0402_25V6

1

PH201 is Common Part SL200002H00

ECAGND <39>

T202 T201 must close to PH201

ADP_I=2 0*I (ad apter)*0 .01

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

I(ada pter)=ad apt er( W)*95%/1 9

Compal Secret Data

Compal Secret Data

2016/07/18 2017/06/14

2016/07/18 2017/06/14

2016/07/18 2017/06/14

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

BATTERY CONN/OTP

BATTERY CONN/OTP

BATTERY CONN/OTP

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

C5MMH M/B LA-E911P

C5MMH M/B LA-E911P

C5MMH M/B LA-E911P

Date : Sheet o f

Date : Sheet o f

Date : Sheet o f

E

49 67Thursday, February 22, 2018

49 67Thursday, February 22, 2018

49 67Thursday, February 22, 2018

0.1

0.1

0.1

5

4

3

2

1

Module model information

ISL9 5520_ Hybr id_Bo ost_ V2.md d

Protection for rev erse i nput

Vgs = 20V
Vds = 60V

D

1 2

PR301

1M_0402_1%

Need check the SOA for inrush

+19V_VIN

C C

0x3CH <BIT9> PSYS current gain
Rs1 = 10mΩ an d Rs2 = 5m Ω o r Rs 1 = 10mΩ and R s2 = 10mΩ
BIT0 = 1.1 4uA/W
BIT1 = 0.285uA/W
===== ==== ===== ===== ==== ===== ===== ==== ===== ===== ==== ===== =
Rs1 = 20mΩ and Rs2 = 10mΩ o r Rs1 = 20m Ω a nd Rs2 = 20mΩ
BIT0 = 2.2 8uA/W
BIT1 = 0.5 7uA/W

Ipsys = KPSYS x ( VAD P x IAD P + VBA T x IBAT )
R_Psys = 1.2V / Ipsys
KPSYS = 1.14uA/W
adapter wattag e = 45W
Battery wattag e = 40Wh
Ipsys = 1.14 x (45+40) = 96.9uA
R_Psys = 1.2V / 96.9uA = 12.3K-ohm.
===== ==== ===== ===== ==== ===== ===== ====
adapter wattag e = 65W
Battery wattag e = 40Wh
Ipsys = 1.14 x (65+40) = 119.7uA
R_Psys = 1.2V / 96.9uA = 10K-o hm.

**Design Notes**
For 45W/65W /90W system, 2S/3S/4S battery

B

Maximum Charging current 3.5A
Maximum Battery discharge power 55W
#Register Setting

1. 0X3DH bit10 set 0 (default 1) to enable turbo boost function

2. Disable turbo when AC only
#Circuit Design

1. ACLIM and CCLIM are devider voltage control.

2. Use 7X7 choke and 3X3 H/L side MOSFET
Charge current 3A
Power loss : 1.79W (H/S=0.227W,L/S=1.2738W,Choke=0.297W)
Power density : 0.61 (23X16)
#Protect function

1. ACOVP : VCC voltage > 24V

2. SMBus timeout : 0X3DH bit15 set 0 (default 0) to enable 175s(default).

3. ACOC : OX3CH bit4 set1 release adapter limit function (default:Enable).

4. CHGOCP : based on charge current setting

5. BATOVP : 4.6V/Cell

6. BATLOWV : No.

7. TSHUT : 150C

A A

  

DGPU_AC_DETECT<20,25,39>

@VGA@

PQ314

RUM001L02_VMT3

H_PROCHOT#

2

AC_IN<39>

1

3

5

Range :2V~ 3.5V
20*49 .9/( 392+4 9.9)= 2.55 V

VDD_CHG

1

PR311

2

100K_0402_1%

1

PR313

2

158K_0402_1%

+3VS

12

@VGA@

@VGA@

PR341

PR340

5

@VGA@

PQ313B

G

10K_0402_1%

3

D

S

4

2

G

10K_0402_1%

2N7002KDW_SOT363-6

AC_IN

Id = 250mA

1 2

PR302

3M_0402_5%

PQ310

EMB04N03H_EDFN5X6-8-5

5

4

1

PR306
499K_0402_1%

2

1

1

PR310

2

2

66.5K_0402_1%

ACIN_CHG BST_CHG_R

EC_SMB_DA1<39,49>

EC_SMB_CK1<39,49>

H_PROCHOT#<11,39>

ADP_I<39>

PC316

0.1U_0402_25V6

Close to
EC.

1

AC_IN

L2N7002WT1G_SC70-3

2

6

D

@VGA@

S

PQ313A

1

2N7002KDW_SOT363-6

1

D

2

PQ301

G

L2N7002WT1G_SC70-3

S

3

+19V_P1

1
2
3

PC322

@

1 2

1000P_0402_25V

1

2

PR307 4.02K_0402_1%

PC301

2200P_0402_50V7K

support Turbo b oost : 2200P
no support Turbo boost : 0.1u

PR314 0_0402_5%@

PR316 0_0402_5%@

PR317 0_0402_5%@

PR318 1K_0402_1%

PR321 1K_0402_1%

1

1

PC317

0.1U_0402_25V6

Follow ad apter a nd

2

2

battery w attage in
Vsys c urrent source.
Base on CPU Core VR design.
The resistor is pop on CPU V R schematic.

VDD=5V

@

PR331

76.8K_0402_1%

1 2

@

PQ309

1

D

2

G

S

3

AON7380_DFN3X3-8-5

1
2
3

1

2

PR308 4.02K_0402_1%

1 2

1 2

1

2

1 2

1 2

Close t o EC.

VDD_CHG

1

1

PR329
200K_0402_1%

PR328

2

2

200K_0402_1%

OCCP setting

1

1

PR337

135W@

75K_0402_1%

2

PR336

2

232K_0402_1%

Battery current limimed by CCLIm ~ 3.89A.
Adapter current limimed by ACLIm ~ 4.33A.
(PR779 and PQ741 are for change ACLI m when AC in)

(Rs1 = 10mΩ and Rs2 = 5mΩ o r Rs 1 = 20m Ω and R s2 = 10mΩ).
CC_LIM = VccLIM / 64 x Rs2
=== ==== === === === ==== === === === ==== === === === ==== === === === ==== ==
(Rs1 = 10mΩ and Rs2 = 10mΩ o r Rs 1 = 20m Ω and R s2 = 20mΩ ).
CC_LIM = VccLIM / 32 x Rs2
=== ==== === === === ==== === === === ==== === === === ==== === === === ==== ==
AC_LIM = Vac_LIM / 32 x Rs1

4

PQ311

+19V_P2 +19VB_CHG

5

4

CMSRC_CHG

ASGATE_CHG

PU301

1

ACIN

2

PR322

0_0402_5%

ACLIM_CHG

1

2

PR335

ACOK

3

SDA

4

SCL

5

PROCHOT#

6

AMON

7

BMON

8

NC

CCLIM_CHG

PROG_CHG

1

2

150K_0402_1%

ICClimit : 7.73A
Delta I : 1.44A
1C charge current :6.48A

EC_SMB_DA1_R

EC_SMB_CK1_R

AMON_ISL95520

BMON_ISL95520

@

Hybrid boost power mode
Cell = 4s

max Power loss 0.22W for 90W;0.12W for 65W system;0.05W for 45W
CSR rating: 1W
VCSIP-VCSIN spec < 81mV

PR303

PR304

0_0402_5%

@

AGND

33

COMP_CHG

1

2

PC320

@

1

2

CSIP_CHG_R

1

2

CSIP_CHG

CSIN_CHG

32

CSIP

PROG

9

PR332

560P_0402_50V7K

0.005_1206_1%

PC306

2

1

0.1U_0402_25V6

31

30

CSIN

ASGATE

COMP

CCLIM

10

11

FSET_CHG

1

2

100_0402_1%

1

PC321

2

0.015U_0402_25V7K

4

3

CSIN_CHG_R

1

PR305

2_0402_5%

2

1

2

PC307 0.22U_0603_25V7K

OPCP_CHG

OPCN_CHG

28

29

27

QPCP

OPCN

CMSRC

FSET

CSON

BATGONE

12

14

13

1

PR325
10K_0402_1%

2

1

2

PR333 0_0402_5%

@

BATGO NE(B ATT_T EMP)
logic high: above 2.4V
logic low: u nder 0.8V

PL704

EMI@

FBMA-L11-201209-800LMA50T

2

1

PJP1

@

2

1

2

1

JUMP_43X118

Co-lay jump and ISN choke.

PR309

100_0402_1%

1 2

BGATE_CHG

VBAT_CHG

25

26

VBAT

BGATE

BOOT

UGATE

PHASE

LGATE

VDDP

VDD

DCIN

NTC

ACLIM

CSOP

16

15

ISL88739AHRZ-T_QFN32_4X4

CSOP_CHG

24

23

22

21

20

19

18

17

BST_CHG

UG_CHG

LX_CHG

LG_CHG

VDDP_CHG

VDD_CHG

PR323

1

100K_0402_1%

2

PC318

PR312

1 2

0_0603_5%

PR324 10_1206_5%

1 2

2

VF = 0.38V

1

1U_0603_25V6

1

2

PR333=0 ohm, Fs=50 0KHZ ~ +/- 15%

CSON_CHG

BATT_TEMP <39,49>

3

EMI@

1

1

2

2

PC302

PC305

PC303

10U_0805_25V6K

10U_0805_25V6K

+12.6V_BATT

PC309

0.47U_0402_16V4Z

1 2

1

2

PR319 4.7_0402_5%

PC313
1U_0201_6.3V6K

PD1

3

1

2

S SCH DIO BAS40CW SOT-323

1 2

PR330 2_0402_5%

1

PC319

0.1U_0402_25V6

2

1

2

@

PR334 0_0402_5%

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CON FIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

EMI@

1

2

PC304

0.1U_0402_25V6

1

PC314
1U_0201_6.3V6K

2

+19VB

EMI@

1

1

2

2

PC324

0.1U_0402_25V6

2200P_0402_25V7K

PQ312

AON7380_DFN3X3-8-5

5

4

@

1 2

0.1U_0402_25V7K

PQ305

5

Choke 4.7uH SH00000YC00 (Common Part)
(Size:6.6 x 7.3 x 3 mm)
(DCR:28m ~33m)

AON7506_DFN33-8-5

1

2

1

AON7506_DFN33-8-5

2

PL301

4.7UH_PCMB063T-4R7MS_8A_20%

1 2

PR320

4.7_1206_5%

EMI@

PC315

EMI@

680P_0402_50V7K

+19V_VIN

4

1

2

3

PQ306

5

4

1

3

2

+12.6V_BATT

CSOP_CHG_R

CSON_CHG_R

Compal Secret Data

Compal Secret Data

2016/07/18 2017/06/14

2016/07/18 2017/06/14

2016/07/18 2017/06/14

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

1
2
3

PC308

+17.4V_BATT_CHG

PR315

0.01_1206_1%

1

2

Support max charge 3.5A
Power loss: 0.245W
CSR rating: 1W
VCSPP-VCSON spec < 81mV

4

3

PC310

+12.6V_BATT

1

1

1

2

2

2

PC311

PC312

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

For 4S per cell 4 .35V battery

PR339

4S_BATT@

100K_0402_1%

BATT_4S<39>

1 2

4S_BATT@

PQ316

SUSP#<39,52,55>

Title

Title

Title

Size

Size

Size

Date: Sheet

Date: Sheet

Date: Sheet of

2

G

L2N7002WT1G_SC70-3

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

PWR_CHARGER

PWR_CHARGER

PWR_CHARGER

Document Number R ev

Document Number R ev

Document Number R ev

ACIN_CHG

1

PR338

4S_BATT@

2M_0402_1%

2

1

4S_BATT@

PQ315
LTC015EUBFS8TL_UMT3F

2

3

1

D

S

3

0.1

0.1

0.1

of

of

50 67Thursday, February 22, 2018

50 67Thursday, February 22, 2018

1

50 67Thursday, February 22, 2018

D

B

A

PL401

@EMI@

FBMA-L11-201209-800LM A50T

1 1

+19VB

1 2

PJ403

@

112

JUMP_43X79

2

1

PC406

2

EMI@

0.1U_0402_25V6

+19VB_3V

1

1

PC403

PC404

2

2

2200P_0402_50V7K

EMI@

0.1U_0402_25V6

@EMI@

+3VALWP

PR406

100K_0402_5%

SPOK_3V<39,54>

PL403

2

3

+19VB

SPOK_5V<39>

EC_ON<39>

MAINPWON<39,46,49>

@EMI@

FBMA-L11-201209-800LM A50T

1 2

PJ404

@

112

JUMP_43X79

+3VLP

1

PR414

100K_0402_5%

@

0_0402_5%

1

2

2.2K_0402_5%

1 2

PR411

PR410

2

+19VB_5V

2

PC431

1

1

PC414

2

2

EMI@

0.1U_0402_25V6

10U_0805_25V6K

5V_EN

1

1

PC428

PR412

2

1M_0402_1%

2

4.7U_0402_6.3V6M

B

PU401
SY8286BRAC_QFN20_3X3

1

1

2

2

PC432

@

PC415

LX_3V

PC405

10U_0805_25V6K

10U_0805_25V6K

1

2

SPOK_3V

ENLDO_3V5V

3V_EN<39>

+19VB_5V BST_5V

1

1

PC416

2

2

10U_0603_25V6M

2200P_0402_50V7K

EMI@

@

0_0402_5%

SPOK_5V

PC417

0.1U_0402_25V6

@EMI@

PR413

6

LX

7

GND

8

GND

9

PG

10

NC

1

2

ENLDO_3V5V

LX_5V

SPOK_5V_R

1

2

5

IN

EN2

11

10

5V_EN

BST_3V

2

1

3

4

IN

IN

IN

EN1

OUT

FF

12

15

14

13

PC402
1000P_0402_25V8J

3V_FB

PU402
SY8288CRAC_QFN20_3X3

4

5

IN

6

LX

7

GND

8

GND

9

PG

NC

EN2

12

11

BS

20

LX

19

LX

18

GND

17

LDO

16

NC

21

GND

NC

3.3V LDO 150mA~300mA

1 2

3

2

1

IN

IN

IN

FF

EN1

OUT

15

14

13

1

2

1000P_0402_25V8J

5V_FB

C

EN1 and EN2 dont't floating

PR401

@

0_0603_5%

1 2

1

2

1K_0402_5%

1 2

BS

LX

LX

GND

VCC

NC

GND

LDO

PC427

4.7U_0402_6.3V6M

PC413

1 2

PC401

0.1U_0603_25V7K

1 2

+3VLP

PC411

4.7U_0402_6.3V6M

PR403

PR408

@

0_0603_5%

1 2

20

LX_5V

19

18

PC419 4.7U_0402_6.3V6M

1 2

17

16

21

VL

5V LDO 150mA~300mA

PR407

1K_0402_5%

1 2

Choke 1.5uH SH000016800 (Common Part)
(Size:4.9 x 5.2 x 3 mm)
(DCR:20 m~25 m)

LX_3V

1.5UH_PCMB053T-1R 5MS_6A_20%

1

@EMI@

PR405

4.7_1206_5%

2

3V_SN

1

2

PC418

0.1U_0603_25V7K

1 2

ENLDO_3V5V

PL402

1 2

@EMI@

PC412
680P_0402_50V7K

1

2

5V_SN

1

2

D

PR402
499K_0402_1%

1 2

1

PR404

2

150K_0402_1%

+19VB

1

1

1

2

2

2

PC407

PC408

@

22U_0603_6.3V6M

22U_0603_6.3V6M

1

1

2

2

PC410

PC409

@

22U_0603_6.3V6M

22U_0603_6.3V6M

Vout is 3.234V~3.366V

Choke 1.5uH SH000016700 (Common Part)
(Size:7.3 x 6.6 x 3 mm)
(DCR:14 m~15 m)

PL404

1 2

1.5UH_9A_20%_7X7X3_M

@EMI@

PR409

4.7_1206_5%

@EMI@

PC426
680P_0402_50V7K

1

1

2

1

2

2

PC421

PC420

22U_0603_6.3V6M

22U_0603_6.3V6M

Vout is 4.998V~5.202V

1

2

PC429

22U_0603_6.3V6M

1

2

PC422

@

22U_0603_6.3V6M

+3VALWP

E

+3VALWP

PC430

22U_0603_6.3V6M

+5VALWP

1

1

2

2

PC423

22U_0603_6.3V6M

PC425

PC424

@

22U_0603_6.3V6M

22U_0603_6.3V6M

PJ401

@

112

JUMP_43X118

PJ402

@

112

JUMP_43X118

2

2

+3VALW

+5VALW+5VALWP

2

3

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2016/07/18 2017/06/14

2016/07/18 2017/06/14

2016/07/18 2017/06/14

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

3.3VALWP/5VALWP

3.3VALWP/5VALWP

3.3VALWP/5VALWP

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

C5MMH M/B LAE911P

C5MMH M/B LAE911P

C5MMH M/B LAE911P

Date : Sheet o f

Date : Sheet

D

Date : Sheet o f

51 67Thursday, February 22, 2018

51 67Thursday, February 22, 2018

51 67Thursday, February 22, 2018

E

0.1

0.1

0.1

of

A

B

C

D

E

1

PJ503

@

JUMP_4 3X79

2

112

PL501

@EMI@

+19VB

FBMA-L1 1-201209-800 LMA50T

1 2

+19VB_ 1.2VP

change PL501 from
SM01000C000 to comm
part SM01000P200

2 2

Choke 1uH SH00000YE00 (Common Part)
(Size:6.86 x 6.47 x 3 mm)
(DCR:6.2m~7.2m Ohm)

1UH_PC MC063T-1R0M N_11A_20%

+1.2VP

PC52322U_0603_6.3V6M

3

PC52122U_0603_6.3V6M

PC52222U_0603_6.3V6M

1

1

2

2

PC52522U_0603_6.3V6M

PC52022U_0603_6.3V6M

PC52422U_0603_6.3V6M

1

2

1

1

1

2

2

2

+19VB_1.2VP

1

1

PC510

2

1 2

PC502

2

0.1U_0402_25V6

EMI@

@EMI@

PL502

@EMI@

@EMI@

680P_0 402_50V7K

H/S AON7408 Rds(on) :typ:27m Ohm, max:34m Ohm
Idsm(TA=25)=7.5A, Idsm(TA=70)=5.5A

L/S SI7716 Rds(on) :typ:13.5m Ohm, max:16.5m Ohm
Idsm(TA=25)=16A, Idsm(TA=70)=9.5A

Choke: 7x7x3
Rdc=6.2mohm(Typ), 7.2mohm(Max)

Switching Frequency: 530kHz
Ipeak=7A, Imax=4.9A

1

PC503

2

0.1U_0402_25V6

EMI@

PR504

4.7_120 6_5%

PC518

1

2

2200P_0402_50V7K

PC504

LX_1.2V P

1

2
1

2

12

PC505

10U_0805_25V6K

10U_0805_25V6K

5

PQ503

3

1

2

AON740 8L 1N DFN

5

PQ502

3

1

2

AON750 6_DFN33-8-5

0.1U_06 03_25V7K

4

4

1

PC506

2

+5VALW +1.2VP

VFB=0.607V, Vout=1.214V

BST_1.2 VP_R

PR505

5.1_060 3_5%

1

PC517

1U_020 1_6.3V6K

2

IOCP

PR503

16.5K_0 402_1%

1 2

1

2

+5VALW

PR502

2.2_060 3_5%

1 2

LG_1.2V P

CS_1.2V P

PC509

1U_020 1_6.3V6K

2

1

VDD_1.2 VP

PR511

2.2_040 2_1%

+19VB_ 1.2VP

SYSON<39,47,54>

SUSP#<39, 47,50,55>

1

2

Frequ enc y

470K_0 402_1%

SM_PG_CTRL<11>

Mode Level +0.675VSP VTTREF_1.35V

4 4

S5 L off off
S3 L off on
S0 H on on

Note: S3 - sleep ; S5 - power off

A

B

Security Classification

Security Classification

Security Classification

2016/07 /18 2017/06 /14

2016/07 /18 2017/06 /14

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

2016/07 /18 2017/06 /14

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Pin19 need pull separate from +1.35VP.
If you have +1.35V and +0.675V sequence question,
you can change from +1.35VP to +1.35VS.

BST_1.2 VP

UG_1.2V P

LX_1.2V P

PU501

15

LGATE

14

PGND

13

CS

12

VDDP

11

VDD

PR507

1 2

@

0_0402 _5%

1 2

0.1U_04 02_10V7K

@

0_0402 _5%

1 2

@

0_0402 _5%

1 2

Deciphered Date

Deciphered Date

Deciphered Date

17

16

PHASE

RT8207 PGQW_W QFN20_3X 3

PGOOD

9

10

TON_1.2VP

PR501

PC501

@

PR509

PR510

0.1U_04 02_10V7K

19

18

UGATE

TON

8

EN_1.2VP

1

2

20

21

VTT

BOOT

S5

PAD

VTTGND

VTTSNS

GND

VTTREF

VDDQ

FB

6

FB_1.2VP

1

2

3

4

5

VTTREF _1.2VP

6.19K_0 402_1%

1

1

PR508
10K_04 02_1%

2

PR506

VLDOIN

S3

7

EN_0.6VSP

+1.2VP

1

PC519

@

2

+0.6VSP

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

Dat e: Sheet

Dat e: Sheet o f

D

Dat e: Sheet

0.6Volt +/- 5%
TDC 0.7A
Peak Current 1A

+1.2VP

+0.6VSP

1

1

PC508

PC507

2

2

10U_0603_6.3V6M

10U_0603_6.3V6M

1

PC516

0.033U_ 0402_16V7K

2

2

+1.2VP

Vout=0.75V* (1+Rup/Rdown)
=0.75*(1+(6.19/10))
=1.214V 1.2%

Vout=0.75V* (1+Rup/Rdown)
=0.75*(1+(8.2/10))
=1.365V 1.1%

PJ501

@

JUMP_4 3X118

2

112

PJ502

@

JUMP_4 3X39

2

112

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

DDR4

DDR4

DDR4

C5MMH M/B LAE911P

C5MMH M/B LAE911P

C5MMH M/B LAE911P

+1.2V_VDDQ

+0.6VS_VTT

E

0.1

0.1

0.1

o f

o f

52 67Thursday, Febru ary 22, 2018

52 67Thursday, Febru ary 22, 2018

52 67Thursday, Febru ary 22, 2018

1

3

A

+19VB_1VALW

PL601

1

+19VB

LDO_3V

1

PR607

@

0_0402_5%

2

ILMT_1VALW

1

PR609

@

0_0402_5%

2

The current limit is set to 6A, 8A or 12A when this pin
is pull low, floating or pull high

2 2

@EMI@

FBMA-L11-201209-800LMA50T

1 2

2

112

PJ602

@

JUMP_43X39

change PL601
SM01000C0 00 to comm
part SM01000P200

1

PC604

PC607

2

0.1U_0402_25V6

EMI@

EMI@

2200P_0402_50V7K

1M_0402_1%

1

2

1

1

PC606

PC605

2

2

0.1U_0402_25V6
10U_0805_25V6K

@EMI@

EN_1VALW

ILMT_1VALW

+3VALW

EN_1VALW

1

12

PR601

2

B

EN pin don't floating
If have pull down resistor at HW side, pls delete PR702

+19VB_1VALW

PC601

@

0.22U_0402_10V6K

1

2

PR611

0_0402_5%

1 2

PR603

@

10K_0402_1%

1 2

PU601

2

IN

3

IN

4

IN

5

IN

7

GND

8

GND

18

GND

11

EN

13

ILMT

15

BYP

SY8288RAC_QFN20_3X3

PC614
1U_0402_6.3V6K

PG

BS

LX

LX

LX

FB

VCC

NC

NC

NC

PAD

+1.8_PG <54>

+3VALW

9

1

LX_1VALW

6

19

20

FB_1VALW

14

LDO_3V

17

10

12

16

21

PR606

@

0_0603_5%

1

1

PC613

2.2U_0402_6.3V6M

2

Pin 7 BYP is for CS.
Common NB can delete +3VALW and PC15

C

PR605

@EMI@

4.7_1206_5%

2

Choke 1uH SH00000YE00 (Common Part)
(Size:6.86 x 6.47 x 3 mm)
(DCR:6.2m~7.2m Ohm)

1 2

PC603

0.1U_0603_25V7K

BST_1VALW_RBST_1VALW

1 2

1UH_11A_20%_7X7X3_M

1 2

FB = 0.6V

D

PC602

@EMI@

680P_0402_50V7K

SNUB_1VALW

1 2

PL602

1

1

Rup

PR608

2

1

PR610

Rdo wn

20K_0402_1%

2

Vout=0.6V * (1+R up/Rdown)
=0.6*(1+(15.4/20))
Vout=1.06 2V

1

PC608

2

2

15.4K_0402_1%

330P_0402_50V7K

E

PJ601

@

JUMP_43X118

2

+1.05VALWP

1

PC610

PC609

2

22U_0603_6.3V6M

1

1

PC611

2

2

22U_0603_6.3V6M

22U_0603_6.3V6M

112

1

+

PC612

PC615

2

@

22U_0603_6.3V6M

220U_B2_4VM_R35M

+1.05VALW

+1.05VALWP

1

3

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE P ROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. A ND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE P ROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. A ND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE P ROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. A ND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL E LECTRONICS, INC. N EITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL E LECTRONICS, INC. N EITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL E LECTRONICS, INC. N EITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2016/07/18 2017/06/14

2016/07/18 2017/06/14

2016/07/18 2017/06/14

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

1V

1V

1V

Size

Size

Size

Document Number Re v

Document Number Re v

Document Number Re v

C

C

C

C5MMH M/B LAE911P

C5MMH M/B LAE911P

C5MMH M/B LAE911P

Date: Sheet

Date: Sheet

Date: Sheet o f

E

53 67Thursday, February 22, 2018

53 67Thursday, February 22, 2018

53 67Thursday, February 22, 2018

0.1

0.1

0.1

of

of

3

A

1

+3VALW

+3VALW

2 2

B

PR7126

100K_0402_5%

+1.8_PG<53>

PJ7108

@

2

112

JUMP_43X79

PC7127

22U_0603_6.3V6M

12

VIN_1.8V

1

2

PU7105

PGND

1

FB

SGND

2

PG

3

IN

4

NC

PGND

SY8003ADFC_DFN8_2X2

FB=0.6V

Note:Il oad(ma x)=3A

C

PR7123

@

0_0402_5%

EN_1.8V

1

PC7118

PR7122

PR7121

10K_0402_1%

2

1

1

2

PC7123

2

20.5K_0402_1%

PC7119

68P_0402_50V8J

22U_0603_6.3V6M

Vout=0.6V * (1+R up/Rdown)
Vout =0.6 V*(1 +2 0. 5/1 0)
=1.8 3V (x1.017 )

1

2

PL7103

1 2

Rup

FB_1.8V

Rdo wn

1

@

0.1U_0402_16V7K

2

1

2

1

2

PR7124

1M_0402_1%

9
8

7

EN

6

LX

5

Choke 1uH SH00000YG00 (Common Part)
(Size:3.8 x 3.8 x 1.9 mm)
(DCR:20 m~25m)

LX_1.8V

1UH_2.8A_30%_4X4X2_F

1

PR7125

2

4.7_0603_5%

@EMI@

1

2

PC7124

680P_0402_50V7K

@EMI@

1

2

1

2

PC7125

22U_0603_6.3V6M

SPOK_3V <39,51>

PC7126

@

D

+1.8VALWP

22U_0603_6.3V6M

PJ7107

@

JUMP_43X79

2

+1.8VALWP +1.8VALW

112

E

1

+3VALW

PJ7105
JUMP_43X79

@

1

2

VIN_2.5V

PR7113

1M_0402_5%

+5VALW

1

PC7210

1U_0402_6.3V6K

2

PU7102

G9661MF11U_SO8

4
3
2
1

+2.5VP +2.5V

FB=0.8V

VPP
VIN
VEN
POK

5

NC

6

VO

7

ADJ

8

GND

GND

9

C

Note:Il oad(ma x)=3A

1

PR7115

21.5K_0402_1%

FB_2.5V

PR7116

10K_0402_1%

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE P ROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. A ND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE P ROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. A ND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE P ROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. A ND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL E LECTRONICS, INC. N EITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL E LECTRONICS, INC. N EITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL E LECTRONICS, INC. N EITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

Rup

2

1

Rdo wn Vout =0.8V* (1+Rup/Rdown)

2

1

2

PC7109

2

PC7110

22U_0603_6.3V6M

@

0.01U_0402_25V7K

Vout=0.8V * (1+(21.5/10)) = 2.52V (x1. 008)

2016/07/18 2017/06/14

2016/07/18 2017/06/14

2016/07/18 2017/06/14

1

2

PC7111

22U_0603_6.3V6M

Compal Secret Data

Compal Secret Data

Compal Secret Data

+2.5VP

Deciphered Date

Deciphered Date

Deciphered Date

D

2

2

1

1

VIN_2.5V

4.7U_0402_6.3V6M

@

PR7110

3

4 4

A

SYSON<39,47,52>

0_0402_5%

1 2

B

PC7108

1

2

EN_2.5V

1

2

PC7107

@

0.1U_0402_16V7K

PJ7103

@

JUMP_43X79

1

1

2

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

1.5VS/2.5V

1.5VS/2.5V

1.5VS/2.5V

Size

Size

Size

Document Number R ev

Document Number R ev

Document Number R ev

C

C

C

C5MMH M/B LAE911P

C5MMH M/B LAE911P

C5MMH M/B LAE911P

Date: Sheet of

Date: Sheet

Date: Sheet

E

54 67Thursday, February 22, 2018

54 67Thursday, February 22, 2018

54 67Thursday, February 22, 2018

0.1

0.1

0.1

of

of

3

5

PL7201

EMI@

D

+19VB

FBMA-L11-201209-800LMA50T

1 2

PJ7202

@

2

112

JUMP_43X39

+VCCIOP_B+

1

1

2

PC7217

PC7207

2200P_0402_50V7K

@EMI@

EMI@

2

0.1U_0402_25V6

1

2

PC7208

10U_0805_25V6K

+VCCIOP_EN

+VCCIOP_ILMT

+3VALW

PC7209

1U_0402_6.3V6K

+VCCIOP_LDO_3V

C C

1

PR7213

@

0_0402_5%

2

+VCCIOP_ILMT

1

@

PR7217
0_0402_5%

2

4

PU7201

2

IN

3

IN

4

IN

5

IN

7

GND

8

GND

18

GND

11

EN

13

ILMT

15

12

BYP

SY8288RAC_QFN20_3X3

Pin 7 BYP is for CS.
Common NB can delete +3VALW and PC15

VR_ON<39,47,56,57>

SUSP#<39,47, 50,52>

check delay time with HW

VR_ON

SUSP#

9

PG

+VCCIOP_BST +VCCIOP_BST_R

1

BS

6

LX

19

LX

20

LX

+VCCIOP_FB

14

FB

+VCCIOP_LDO_3V

17

VCC

PAD

NC

NC

NC

10

12

16

21

0_0402_5%

1

1K_0402_5%

1

1

2

PR7207

@

2

PR7208

2

PR7201

1M_0402_5%

PR7202

0_0603_5%

1 2

+VCCIOP_LX

PC7218

2.2U_0402_6.3V6M

+VCCIOP_EN

1

PC7201

2

0.1U_0402_25V6

1

2

3

PC7202

0.1U_0603_25V7K

1 2

FB = 0.6V

PR7203

EMI@

4.7_1206_5%

SNB_+VCCIOP

1

2

Choke 0.68uH SH00000Z300 (Common Part)
(Size:4.85 x 4.7 x 2.8 mm)
(DCR:11 m~12m)

PL7202

0.68UH_7.9A_20%_5X5X3_M

1 2

PR7214

@

Rdo wn

1K_0402_1%

PR7215

20.5K_0402_1%

EMI@

680P_0402_50V7K

1 2

1

2

PC7219

@

2

330P_0402_50V7K

1

Rup

1 2

PR7218

12K_0402_1%

1

2

PC7203

1

PR7212

2

VCCIO_SENSE_R

1

2

10_0402_1%

2

PJ7201

@

2

+VCCIOP

112

JUMP_43X118

1

+VCCIO

Real Voltage=0.95V

+VCCIOP

1

1

1

1

1

2

2

PC7206

22U_0603_6.3V6M

PR7209

@

0_0402_5%

1 2

PR7210

@

0_0402_5%

1 2

PC7211

2

22U_0603_6.3V6M

PC7212

22U_0603_6.3V6M

VCCIO_SENSE

VSSIO_SENSE

2

PC7204

PC7205

@

22U_0603_6.3V6M

22U_0603_6.3V6M

Note :Ilo ad( max )= 5. 5A

2

IOCP =7A~ 8A (typ)

PC7214

22U_0603_6.3V6M

Vout=0.6V * (1+R up/Rdown)
=0.6* (1+(12k/20.5k))
=0 .951V --- ( x1.001)

VCCIO_SENSE <13>

VSSIO_SENSE <13>

D

B

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE P ROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. A ND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE P ROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. A ND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE P ROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. A ND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL E LECTRONICS, INC. N EITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL E LECTRONICS, INC. N EITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL E LECTRONICS, INC. N EITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2016/07/18 2017/06/14

2016/07/18 2017/06/14

2016/07/18 2017/06/14

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size

Size

Size

Date: Sheet of

Date: Sheet of

Date: Sheet

Compal Electronics, Inc.

C5MMH M/B LAE911P

C5MMH M/B LAE911P

C5MMH M/B LAE911P

Document Number R ev

Document Number R ev

Document Number R ev

1.0VS_VCCIO

1.0VS_VCCIO

1.0VS_VCCIO

1

55 67Thursday, February 22, 2018

55 67Thursday, February 22, 2018

55 67Thursday, February 22, 2018

0.1C

0.1C

0.1C

of

B

5

+19VB_CPU+19 VB_CPU

Fs=400k, LL =1.8m for Core

Fs=400k, LL =2.1m for GT

SET1 ICC MAX=128A, OCP=120%, DVIDT=35.7mV.

D D

SET2 Ram p=133%, DV IDW=9us, Q RT=25mV, QR W=44%

SET3 Zero L L disable, VR address Core=0, GT=1.

SETA1 IC CMAX=32A, OCP=120%, DVIDT=60mV.

SETA2 Ra mp=133%, D VIDW=9us, QRT=25mV, Q RW=44%

Core offset function disable, GT offset
function di sable, PSY S disable.

1

2

PR8132

3.01K_0402_1%

1

PR8137

@

2

24.9_0402_1%

1

2

PR8145

1.02K_0402_1%

1

PR8153

@

@

0_0402_5%

C C

2

VCCSENSE<12>

+VCC_CORE

B

ENABLE
Upper Thres hold > 0.8V
Lower Thres hold < 0.3V

0.22U_04 02_25 V6K

+VREF

1

1

PR8134

10K_0402_1%

2

2

PR8135

PR8133

13.3K_0402_1%

13.3K_0402_1%

12

1

PR8143

PR8140

PR8138

0_0402_5%

2

2K_0402_1%

26.7K_0402_1%

1

1

PR8148

PR8147

402_0402_1%

768_0402_1%

3.4K_0402_1%

2

2

PR8146

1

1

PR8155

PR8154

PR8156

412_0402_1%

0_0402_5%

@

0_0402_5%

2

2

RTCPU_V SEN

@

PR8165

0_0402 _5%

12

PR8168

100_04 02_1%

12

VCCGT_SENSE<12 >

+VCC_GT

Reserved for RF Team Request

@RF@

PC8142

2.2P_04 02_50 V8C

1 2

SCLK_C PU

PR8189 49.9_040 2_1%

ALERT_ CPU

PR8190 0_0402 _5%@

SDIO_C PU

PR8191 10_040 2_1%

1

2

1

2

1

2

1

2

1

1

1 2

2

PR8107

2

2.2_0402_1%

1

PR8116
402K_0 402_1 %

2

1

2

PR8136

5.1K_0402_1%

1

PR8141

2

8.2K_0402_1%

RTCPU_S ET1
RTCPU_S ET2
RTCPU_S ET3
RTCPU_S ETA1
RTCPU_S ETA2

1

PR8149

2

3.16K_0402_1%

1

PR8157

300_0402_1%

2

PR8166

10K_04 02_1%

12

PC8126

330P_0 402_5 0V8J

12

RTCPU_V SENA

PR8175

@

0_0402 _5%

12

PR8178

100_04 02_1%

12

+1.05V_VCCST

PR8186

1

2

100_0402_1%

2

2

1

1

PC8109

1

12

PR8108

PC8110

2

2.2_0402_1%

0.22U_0402_25V6K

1

PR8117
442K_0 402_1 %

2

RTCPU_T ONSETR TCPU_T ONSETA

PR8167

23.2K_0 402_1 %

12

PC8127

82P_04 02_50 V8J

12

PR8177

10K_04 02_1%

12

PC8137

270P_0 402_5 0V7K

12

confirm with power sequence,
it need behind +5VS.

PR96and PR98 pull high resistor are pop at the end of VR
SVID.
Other VR is unpop.

PR8187

@

PC8143

PR8188

1

1

1

2

2

2

100_0402_1%

0.1U_0402_25V6

45.3_0402_1%

1

PR8109

2

8.66K_0402_1%

1

RTCPU_TSEN_R

PR8118

2

2

57.6K_0402_1%

PH8103

1

220K_0402_5%_B25/50 4700K

RTCPU_TSEN

PR8139 0_0402_5 %@

12

PR8142 0_0402_5 %@

12

RTCPU_T ONSET

RTCPU_T ONSETA

RTCPU_P S4

RTCPU_S ET1

RTCPU_S ET2

RTCPU_S ET3

RTCPU_S ETA1

RTCPU_S ETA2

RTCPU_V SENA

RTCPU_V SENA

RTCPU_V SEN

RTCPU_V SEN

RTCPU_C OMP

RTCPU_F B

+19VB_ CPU

1

RTCPU_D VD

2

PR8169

510K_0402_1%

1

1

2

2

PR8172

100K_0402_1%

PR8176

16.9K_0 402_1 %

1

2

PC8138

68P_04 02_50 V8J

12

CPU_SVID_CLK <11,57>

CPU_SVID_ALERT#_R <11,57>

CPU_SVID_DAT <11,57>

1

PR8119

2

57.6K_0402_1%

56

44

55

43

49

14

15

17

18

19

33

12

11

10

@

0_0402 _5%

PC8134

0.1U_040 2_50V 7K

+19VB_CPU

PC8154

PC8153

PC8151

PC8152

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

1

1

1

2

2

2

PC8158

PR8196

0.1U_060 3_25V 7K

2.2_060 3_1%

EN5

EN5

1

PC8161
1U_0201 _6.3V6 K

2

1 2

BOOST_ VCCGT 1_R

PU8106

4

BOOT

UGATE

5

PWM

PHASE

1

EN

PGND

8

VCC

LGATE

GND

RT9610 CGQW _WDF N8_2X2

1

3

2

6

7
9

BOOST_ VCCGT 1

RTCPU_P WMA1

PR8200

5.1_040 2_1%

2

1

+5VALW

A A

PR8204

@

0_0402 _5%

RTCPU_P S4

2

1

1

2

2

VCCGT_ UG1

VCCGT_ LG1

10U_0805_25V6K

VCCGT_ PHASE1

PC8156

PC8155

EMI@

EMI@

2200P_0402_50V7K

0.1U_0402_25V6

1

1

2

2

4

90A for ICCMAX=2.2V 76A for ICCMAX=2.2V

+VREF

1

PR8102

8.45K_0 402_1 %

1

2

1

PR8104

PH8102

2

7.5K_0402_1%

PR8113

1.8K_0402_1%

+VREF

42

1

TSEN

TSENA

NC

28

1

2

100K_0 402_1 %_B25 /50 425 0K

2

NTC1N

1

2

1

2

PC8111

0.47U_0402_16V4Z

12

PR8127

1_0402_1%

20

21

IMON

VREF

RT3607CE

COMPA

FBA

PGOOD

34

35

54

RTCPU_FBA

RTCPU_COMPA

RTCPU_VCC

VCCCORE_VR_PWRGD

1

2

PR8180

100K_0402_1%

22

PR8110

8.66K_0402_1%

PH8104

220K_0402_5%_B25/50 4700K

57

NC

NC

TONSET

TONSETA

PS4

SET1

SET2

SET3

SETA1

SETA2

VSENA

VSEN

COMP

FB

PR8170

1

2

RTCPU_TSENA_R

2

1

RTCPU_TSENA

GND

DVD

45

IMONA

PR8124

100K_0402_1%

GND

PR8173

1

2

RTCPU_IBIAS

31

IBIAS

RTCPU_VCC

10_0603_1%

+5VALW

VCC

29

1

2

+VREF

1

PR8105

2

4.02K_0402_1%

NTCGT1N

1

+1.05V_VCCST

PR8114

2

5.76K_0402_1%

PR8126
100_04 02_1%

1

2

1

PR8128 0_0402_5%

@

26

24

23

25

16

NC

VDIO

VCLK

VR_HOT

ISENA3P

ISENA3N

ISENA2N

40

41

36

RTCPU_VCC

1

PC8136

2.2U_040 2_6.3V 6M

2

VCCCORE_VR_PWRGD <39>

+3VALW

H/S AON6380 Rds(on) :typ:8.2mOhm, max:10.5mOhm
Idsm(TA=25)=22A, Idsm(TA=70)=17.5A

L/S AON6314 Rds(on) :typ:2.8mOhm, max:3.5mOhm
Idsm(TA=25)=37A, Idsm(TA=70)=30A

Ta=70=>Id=17 .5A

2

S2

4

5

D1

S2

S2

3

AON6962 _DFN5X 6D-8-7

Rdson=8.2~10.5 mohm

VCCGT_ PHASE1

1

2

SNUB_VCC GT1

1

2

PQ8105

1

G1

7

D2/S1

G2

6

confirm with power sequence,
it need behind +5VS.

1

PR8103

30.1_04 02_1%

2

NTCGT1PNTC1P

1

PH8101

10K_04 02_1% _B25/5 0 3370 K

2

1

PR8122

@

1K_040 2_1%

2

2

RTCPU_E N

VSSGT_ SENSE_ R

VSSSENS E_R

PU8101
RT3607 CEGQW _WQ FN56_6 X6

32

27

13

EN

RGND

ALERT

RGNDA

PWM1

PWM2

PWM3

PWM4

ISEN1P

ISEN1N

ISEN2P

ISEN2N

ISEN3P

ISEN3N

ISEN4P

ISEN4N

PWMA1

PWMA2

PWMA3

ISENA1P

ISENA2P

ISENA1N

38

39

37

AISPGT 1

PR8171

680_04 02_1%

RTCPU_ISENA1N

Ta=70=>Id=3 0A
Rdson=2.8~3.5 mohm

0.15UH_MMD0 6CZER 15MG_3 7A_20 %

@EMI@

PR8201

4.7_120 6_5%

1

PR8203

PR8202

182_04 02_1%

2
1

182_0402_1%

@EMI@

PC8162
680P_0 402_5 0V7K

VR_HOT# <39>

SCLK_C PU
SDIO_C PU
ALERT_ CPU

52

51

53

50

30

NC

5

4

6

7

2

3

9

8

47

46

48

12

PL8107

134

2

0.47U_04 02_6.3 V6K

2

RTCPU_P WM1

RTCPU_P WM2

RTCPU_P WM3

RTCPU_P WM4

AISP1

RTCPU_I SEN1N

AISP2

RTCPU_I SEN2N

AISP3

RTCPU_I SEN3N

AISP4

RTCPU_I SEN4N

RTCPU_P WMA1

AVGT1

PC8163

1

PR8205

@

0_0402 _5%

1

1

2

PC8115
1U_0201 _6.3V6 K

PR8150

680_04 02_1%

1

PR8152

680_04 02_1%

1 2

PR8159

680_04 02_1%

1

PR8162

680_04 02_1%

1 2

PR8106

100_04 02_1%

1 2

PR8111

@

0_0402 _5%

1

PR8115

100_04 02_1%

1 2

PR8120

@

0_0402 _5%

1 2

PR8130

0_0402 _5%

1

2

2

3

2

VSSGT_SENSE <12>

+5VALW

VSSSENSE <12>

2

AVcore1

AVcore2

AVcore3

AVcore4

RTCPU_P S4

VR_ON <39,47,55,57>

+5VALW

RTCPU_P S4

PR8112

5.1_040 2_1%

1 2

PR8129

@

0_0402 _5%

1 2

PR8151

5.1_040 2_1%

1 2

PR8163

@

0_0402 _5%

1

2

+19VB_CPU

BOOST_ VCC1

EN1

+19VB_CPU

EN2

EN1

1

PC8112
1U_0201 _6.3V6 K

2

EN2

1

PC8123
1U_0201 _6.3V6 K

2

PR8101

2.2_060 3_1%

BOOST_ VCC1_ R

1 2

PU8102

4

BOOT

UGATE

5

PHASE

PWM

1

EN

8

VCC

LGATE

RT9610 CGQW _WDF N8_2X2

PR8144

2.2_060 3_1%

BOOST_ VCC2_ RBOOST_VC C2

1 2

PU8103

4

BOOT

UGATE

5

PWM

PHASE

1

EN

8

VCC

LGATE

RT9610 CGQW _WDF N8_2X2

1

2

PGND

GND

1

2

PGND

GND

PC8104

10U_0805_25V6K

1

2

PC8101

0.1U_060 3_25V 7K

1 2

VCC_UG1

3

2

6

VCC_LG 1

7
9

PC8119

10U_0805_25V6K

1

2

PC8122

0.1U_060 3_25V 7K

1 2

VCC_UG2

3

2

6

VCC_LG 2

7
9

PC8105

PC8120

PC8107

PC8106

EMI@

EMI@

2200P_0402_50V7K

10U_0805_25V6K

0.1U_0402_25V6

1

1

2

2

VCC_PHA SE1

PC8117

PC8121

EMI@

EMI@

10U_0805_25V6K

2200P_0402_50V7K

0.1U_0402_25V6

1

1

2

2

VCC_PHA SE2

+19VB_CPU

1

2

VCC_UG3

VCC_LG 3

PC8131

PC8133

PC8132

EMI@

EMI@

10U_0805_25V6K

2200P_0402_50V7K

0.1U_0402_25V6

1

1

2

2

PQ8103

VCC_PHA SE3

+5VALW

RTCPU_P S4

PR8179

5.1_040 2_1%

1

PR8184

@

0_0402 _5%

1

2

2

BOOST_ VCC3

EN3

EN3

1

PC8139
1U_0201 _6.3V6 K

2

PR8174

2.2_060 3_1%

BOOST_ VCC3_ R

1 2

PU8104

4

BOOT

UGATE

5

PWM

PHASE

1

EN

8

VCC

LGATE

RT9610 CGQW _WDF N8_2X2

1

2

PGND

GND

PC8130

10U_0805_25V6K

PC8135

0.1U_060 3_25V 7K

1 2

3

2

6

7
9

+19VB_CPU

PC8148

PC8147

PC8146

10U_0805_25V6K

1

2

PR8192

PC8150

2.2_060 3_1%

0.1U_060 3_25V 7K

BOOST_ VCC4_ RBOOST_VC C4

2

1

1 2

PU8105

3

4

BOOT

UGATE

5

2

PWM

PHASE

6

PR8193

5.1_040 2_1%

1 2

+5VALW

PR8198

+VCC_GT

2

2

AVGT1AISP GT1

RTCPU_P S4

@

0_0402 _5%

1

1

EN4

EN

PGND

8

7

VCC

LGATE

9

PC8157
1U_0201 _6.3V6 K

GND

RT9610 CGQW _WDF N8_2X2

1

2

2

EN4

1

2

VCC_UG4

VCC_LG 4

PC8149

EMI@

EMI@

0.1U_0402_25V6

10U_0805_25V6K

2200P_0402_50V7K

1

1

@

2

2

PQ8104

VCC_PHA SE4

PQ8102

2

+19VB_CPU

33U_D1_25VM_R6M

33U_D1_25VM_R6M

100U_25V_NC_6.3X6

@

@

1

1

1

+

2

Ta=70=>Id=17 .5A
Rdson=8.2~10.5 mohm

PQ8101

2

1

D1

G1

7

D2/S1

S2

G2

S2

4S25

6

3

AON6962 _DFN5X 6D-8-7

Ta=70=>Id=3 0A
Rdson=2.8~3.5 mohm

Ta=70=>Id=17 .5A

S2

5

2

D1

S2

S2

4

5

2

D1

S2

S2

5

4

2

D1

S2

S2

4

3

AON6962 _DFN5X 6D-8-7

S2

3

AON6962 _DFN5X 6D-8-7

S2

3

AON6962 _DFN5X 6D-8-7

Rdson=8.2~10.5 mohm

VCC_PHA SE2

Ta=70=>Id=3 0A
Rdson=2.8~3.5 mohm

Ta=70=>Id=17 .5A
Rdson=8.2~10.5 mohm

VCC_PHA SE3

VCC_PHA SE4

1

G1

7

D2/S1

G2

6

1

G1

7

D2/S1

G2

6

1

G1

7

D2/S1

G2

6

PC8118

PC8116

PC8108

+

+

2

2

VCC_PHA SE1

1

@EMI@

PR8121

4.7_120 6_5%

2

SNUB_VCC 1

1

@EMI@

PC8114

2

680P_0 402_5 0V7K

1

@EMI@

PR8158

4.7_120 6_5%

2

SNUB_VCC 2

1

@EMI@

PC8125

2

680P_0 402_5 0V7K

1

@EMI@

PR8181

4.7_120 6_5%

2

SNUB_VCC 3

1

@EMI@

PC8141

2

680P_0 402_5 0V7K

Ta=70=>Id=3 0A
Rdson=2.8~3.5 mohm

Ta=70=>Id=17 .5A
Rdson=8.2~10.5 mohm

1

@EMI@

PR8194

4.7_120 6_5%

2

SNUB_VCC 4

12

@EMI@

PC8160
680P_0 402_5 0V7K

Ta=70=>Id=3 0A
Rdson=2.8~3.5 mohm

PL8103

EMI@

FBMA-L11 -20120 9-800L MA50T

1 2

PL8102

EMI@

FBMA-L11 -20120 9-800L MA50T

1 2

Choke 0. 15uH SH000 00X700
(Size:6.59 x 6.6 x 3. 0 mm)
(DCR:0.9m +-7%)

PL8101

0.15UH_MMD0 6CZER 15MG_3 7A_20 %

134

2

1

PR8125

PC8113

PR8123

0.47U_04 02_6.3 V6K

200_04 02_1%

2

1 2

1 2

200_0402_1%

@

PR8131

0_0402 _5%

1 2

AVcore1AISP1

PL8306

0.15UH_MMD0 6CZER 15MG_3 7A_20 %

134

2

1

PR8161

PC8124

PR8160

0.47U_04 02_6.3 V6K

200_04 02_1%

2

2

1

1 2

200_0402_1%

PR8164

@

0_0402 _5%

1 2

AVcore2AISP2

PL8305

0.15UH_MMD0 6CZER 15MG_3 7A_20 %

1

4

2

3

1

PR8183

PC8140

PR8182

0.47U_04 02_6.3 V6K

200_04 02_1%

2

1 2

2

1

200_0402_1%

PR8185

@

0_0402 _5%

1 2

AISP3

AVcore3

PL8106

0.15UH_MMD0 6CZER 15MG_3 7A_20 %

1

342

1

PC8159

PR8197

PR8195

0.47U_04 02_6.3 V6K

200_04 02_1%

2

200_0402_1%

1 2

1

@

0_0402 _5%

1 2

PR8199

2

AVcore4AISP4

+19VB

+VCC_CORE

1

B

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

Compal Secret Data

Compal Secret Data

Compal Secret Data

2016/07/18 2017/06/14

2016/07/18 2017/06/14

2016/07/18 2017/06/14

Deciphered Date

Deciphered Date

Deciphered Date

Title

Title

Title

RT3607CE

RT3607CE

RT3607CE

Size

Size

Size

Document Numbe r R ev

Document Numbe r R ev

Document Numbe r R ev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet

Date: Sheet of

1

56 67Thursday, Feb ruary 22, 201 8

56 67Thursday, Feb ruary 22, 201 8

56 67Thursday, Feb ruary 22, 201 8

0.1

0.1

0.1

of

5

4

3

2

1

+1.05V_VCCST

PC8302

1

2

1

2

IMON_VCCSA

18

IMON

VCC

PC8318

2.2U_0603_10V6K

0.47U_0402_6.3V6K

1

2

1

2

VREF_VCCSA

17

PR8307

1_0402_1%

VREF

PVCC

12

1

2

1

@

1K_0402_5%

2

3

VRHOT#

PC8317

1U_0201_6.3V6K

Confirm HW side.

D D

VREF_VCCSA

1

PR8305

2

30.9K_0402_1%

1

PR8309

1

14K_0402_1%

2

2

10K_0402_1%

0.22U_0402_25V6K

12

VCCSA_VR_PWRGD<39>

PR8315

7.32K_0402_1%

PR8318

2K_0402_1%

PC8309

1 2

PSYS_VCCSA

SET1_VCCSA
SET2_VCCSA
SET3_VCCSA

VSEN_VCCSA

COMP_VCCSA

FB_VCCSA

RGND_VCCSA

1

2

1

2

PR8319

PR8325

PR8328

PR8333

22K_0402_1%

300_0402_1%

20K_0402_1%

300_0402_1%

PR8344

1

1

PR8320

22.6K_0402_1%

2

2

1

1

PR8326

@

0_0402_5%

2

2

1

1

PR8329

7.68K_0402_1%

2

2

1

1

PR8334

2

2

2.2K_0402_1%

47.5K_0402_1%

12

PC8314

100P_0402_50V8J

1 2

PR8312

PR8345

Confirm HW side.
Don't do uble p ull hig h.

VREF_VCCSA

1

3.6K_0402_1%

PR8317

PC8312

10K_0402_1%

1

2

12

PR8343

PR8324

PR8327

PR8332

2

1

120_0402_1%

2

1

1.78K_0402_1%

2
1

2

100_0402_1%

300_0402_1%

1

SET1 connect to 5V is into test mode.

C

VCCSA_SENSE<13>

B B

VSSSA_SENSE<13>

The output is 1.05V.

Local sense, for debug only.
Trace is form output cap that is near choke.

PR8335

100_0402_1%

PR8339

@

0_0402_5%

2

PR8346

@

0_0402_5%

12

1

12

+VCC_SA

PR8341

@

0_0402_5%

12

@

0.1U_0402_25V6

1

2

PR8347

100_0402_1%

PC8313

12

1

2

1

2

PR8342

@

0_0402_5%

2

330P_0402_50V8J

PC8315

@

0.1U_0402_25V6

PC8316

@

0.1U_0402_25V6

Local sense, for debug only.

VCCSENSE and VSSSENSE need have
a 100ohm at HW Si de

Don't do uble p ull hig h.

VR_HOT# 90 degreeC
ALERT# 87.3 degreeC

PH8302

100K_0402_1%_B25/50 425 0K

1 2

PR8314

PR8313

200_0402_1%

48.7K_0402_1%

TSEN_VCCSA_R

2

1

2

Vboot= 0V

+19VB_CPU

PR8322

1

2.2_0805_1%

2

13

VIN

19

PSYS

28

SET1

27

SET2

26

SET3

25

VSEN

23

COMP

24

FB

22

RGND

PR8348

100K_0402_5%

+3VALW

VR2_HOT#<39>

1

PR8310

59K_0402_1%

PR8316

2.4K_0402_1%

TSEN_VCCSA

16

TSEN

VR_READY

1

7

+VCC_VCCSA

1

1

1

2

2

PR8349

2

22_0402_1%

+5VALW

PR902 and PR904 pull high resistor are pop at the end of VR SVID.
Other VR is unpop.

SVID_ALERT# pull high resistor is at HW side.

PR8302

VCLK_VCCSA

SDIO_VCCSA

ALERT#_VCCSA

6

4

5

VDIO

VCLK

ALERT#

DRVEN

15

+5VALW

45.3_0402_1%

PR8306

49.9_0402_1%

1 2

PR8308

@

0_0402_5%

1 2

PR8311

10_0402_1%

1 2

1

@

0.1U_0402_25V6

2

VCCSA_VR_EN

2

EN

ISEN1N

21

1

2

PC8319

0.1U_0402_25V6

+1.05V_VCCST

PR8303

PC8306

PWM

LGATE

PHASE

UGATE

BOOT

GND

ISEN1P

20

AISP1_VCCSA

AVcore1_VCCSA

1

1

PR8304

PC8303

100_0402_1%

0.1U_0402_25V6

2

2

PR8321

EN: high > 0.7V, Low < 0.3V

0_0402_5%

1 2

BOOST_VCCSA

PU8301

RT3601EAGQW_W QFN28_4X4

14

LG_VCCSA

11

LX_VCCSA

10

UG_VCCSA

9

BOOST_VCCSA

8

29

1

2

VR_ON < 39,47,55,56>

PR8301

2.2_0603_5%

1 2

confirm with power sequence,
it need behind +5VS.

CPU_SVID_CLK <11,56>

CPU_SVID_ALERT#_R <11,56>

CPU_SVID_DAT <11,56>

1

2

PC8301

0.22U_0402_16V7K

AONH36334_DFN3X3A8-10

UG_VCCSA

PQ8301

LG_VCCSA

BOOST_VCCSA_R

LX_VCCSA

Choke

+19VB_CPU

Size and DCR

IMON

1

1

1

1

2

2

PC8305

PC8304

10U_0805_25V6K

10U_0805_25V6K

PC8308

2

PC8307

2

EMI@

0.1U_0402_25V6

2200P_0402_50V7K

@EMI@

COMP

ISEN

PR813

PR841

PR832

PR833

PR828

PR830

PR831

7x7x4

0.67m +-5%

68.1K

0

10K

40.2K

604

243

10K

7x7x3

0.9m +-5%

73.2K

1.1K

37.4K

665

549

1K

1K(3650K)PH802 10K(3370K)

3

2

4

1

D1

D1

D1

G1

9

D1

D2/S1

G2

S2

S2

8

6

7

LX_VCCSA

10

S2

5

AISP1_R

1

1

PR8331

PR8330

576_0603_1%

2

4.7_1206_5%

2

@EMI@

PR8336

255_0402_1%

1 2

SNUB_VCCSA

1

PC8311

@EMI@

2

680P_0402_50V7K

10K_0402_1%_B25/50 3370 K

AISP1_VCCSA

PL8301

0.24UH_22A_20%_ 7X7X3_ M

1

2

PC8310

0.47U_0402_6.3V6K

1

2

PR8337

10K_0402_1%

AVcore1_NTC

1 2

AVcore1_NTC_R

2

1

PH8301

For NTC trace routing only.

4

3

PR8340

@

0_0201_5%

1

+VCC_SA

2

AVcore1_VCCSA

C

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS T HE PROPRIETARY PR OPERTY OF COMPAL ELECTRONICS, IN C. AND C ONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS T HE PROPRIETARY PR OPERTY OF COMPAL ELECTRONICS, IN C. AND C ONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS T HE PROPRIETARY PR OPERTY OF COMPAL ELECTRONICS, IN C. AND C ONTAINS CONFIDENTIAL

AND TRADE SECRET INFORM ATION. THIS SHEE T MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D

AND TRADE SECRET INFORM ATION. THIS SHEE T MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D

AND TRADE SECRET INFORM ATION. THIS SHEE T MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D

DEPARTMENT EXC EPT AS AUTHORIZE D BY COMPAL ELECT RONICS, INC. NEIT HER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXC EPT AS AUTHORIZE D BY COMPAL ELECT RONICS, INC. NEIT HER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXC EPT AS AUTHORIZE D BY COMPAL ELECT RONICS, INC. NEIT HER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2016/07/18 2017/06/14

2016/07/18 2017/06/14

2016/07/18 2017/06/14

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Title

Title

Title

Size

Size

Size

Custom

Custom

Custom

Date : Sheet of

Date : Sheet of

Date : Sheet of

RT3601EA VCC_SA

RT3601EA VCC_SA

RT3601EA VCC_SA

Document Number Re v

Document Number Re v

Document Number Re v

57 67Thursda y, February 22, 2018

57 67Thursda y, February 22, 2018

1

57 67Thursda y, February 22, 2018

0.1

0.1

0.1

5

4

+VCC_CORE +VCC_GT

3

2

1

1

+

PC9002

2

+VCC_CORE +VCC_GT

D

12

PC9009

1

2

PC9039

1

2

PC9067

C C

1

2

PC9093

1

PC9114

2

1

1

+

+

PC9003

PC9004

2

2

220U_D2_2V_Y

220U_D2_2V_Y

1

1

2

2

PC9010

22U_0603_6.3V6M

22U_0603_6.3V6M

1

1

2

2

PC9040

22U_0603_6.3V6M

22U_0603_6.3V6M

1

1

2

2

PC9068

22U_0603_6.3V6M

22U_0603_6.3V6M

1

1

2

2

PC9094

22U_0603_6.3V6M

22U_0603_6.3V6M

1

1

PC9115

2

2

1U_0201_6.3V6M

1U_0201_6.3V6M

1

1

2

PC9154

220U_D2_2V_Y

1

2

PC9011

22U_0603_6.3V6M

1

2

PC9041

22U_0603_6.3V6M

1

2

PC9069

22U_0603_6.3V6M

1

2

PC9095

22U_0603_6.3V6M

1

PC9116

2

1U_0201_6.3V6M

1

1

1

2

2

PC9150

PC9156

22U_0603_6.3V6M

22U_0603_6.3V6M

1

1

2

2

PC9013

PC9012

22U_0603_6.3V6M

22U_0603_6.3V6M

1

1

2

PC9042

PC9070

2

PC9043

22U_0603_6.3V6M

22U_0603_6.3V6M

1

1

2

2

PC9071

22U_0603_6.3V6M

22U_0603_6.3V6M

2

2

PC9155

PC9153

22U_0603_6.3V6M

22U_0603_6.3V6M

1

1

2

2

PC9014

PC9015

22U_0603_6.3V6M

22U_0603_6.3V6M

1

1

2

2

PC9045

PC9044

22U_0603_6.3V6M

22U_0603_6.3V6M

1

1

2

2

PC9073

PC9072

22U_0603_6.3V6M

22U_0603_6.3V6M

1

2

PC9097

PC9096

@

@

22U_0603_6.3V6M

22U_0603_6.3V6M

1

1

1

PC9118

PC9117

1U_0201_6.3V6M

PC9119

2

2

1U_0201_6.3V6M

1

PC9120

2

2

1U_0201_6.3V6M

1U_0201_6.3V6M

1

1

2

2

PC9151

PC9152

22U_0603_6.3V6M

PC9016

22U_0603_6.3V6M

PC9046

22U_0603_6.3V6M

PC9074

22U_0603_6.3V6M

PC9121

1U_0201_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

1

1

2

2

PC9018

PC9017

22U_0603_6.3V6M

22U_0603_6.3V6M

1

1

2

2

PC9047

PC9048

22U_0603_6.3V6M

22U_0603_6.3V6M

1

1

2

2

PC9075

PC9076

22U_0603_6.3V6M

22U_0603_6.3V6M

1

1

PC9122

PC9123

2

2

1U_0201_6.3V6M

1U_0201_6.3V6M

1

1

2

2

PC9020

PC9019

22U_0603_6.3V6M

22U_0603_6.3V6M

1

1

2

2

PC9050

PC9049

22U_0603_6.3V6M

22U_0603_6.3V6M

1

1

PC9078

PC9077

2

2

1

2

1U_0201_6.3V6M

1U_0201_6.3V6M

1

PC9099

PC9098

2

1U_0201_6.3V6M

1U_0201_6.3V6M

1

+

2

1

1

2

2

PC9021

22U_0603_6.3V6M

1

1

2

2

PC9051

22U_0603_6.3V6M

1

1

PC9079

2

2

1U_0201_6.3V6M

1

1

PC9100

2

2

@

1U_0201_6.3V6M

1

2

PC9007

PC9022

PC9052

PC9080

PC9101

@

PC9162

220U_D2_2V_Y

1

1

2

2

PC9023

22U_0603_6.3V6M

22U_0603_6.3V6M

1

1

2

2

PC9053

22U_0603_6.3V6M

22U_0603_6.3V6M

1

1

PC9081

2

2

1U_0201_6.3V6M

1U_0201_6.3V6M

1

1

PC9102

2

2

@

1U_0201_6.3V6M

1U_0201_6.3V6M

1

1

2

PC9158

22U_0603_6.3V6M

1

2

PC9024

22U_0603_6.3V6M

1

2

PC9054

22U_0603_6.3V6M

1

PC9082

2

1U_0201_6.3V6M

1

PC9103

2

@

1U_0201_6.3V6M

1

1

2

2

PC9157

22U_0603_6.3V6M

1

2

PC9025

22U_0603_6.3V6M

1

2

PC9055

22U_0603_6.3V6M

1

PC9083

2

1U_0201_6.3V6M

1

PC9104

2

@

1U_0201_6.3V6M

2

PC9160

PC9163

@

22U_0603_6.3V6M

22U_0603_6.3V6M

1

1

2

2

PC9027

PC9026

22U_0603_6.3V6M

22U_0603_6.3V6M

1

1

2

PC9056

PC9084

PC9105

@

2

PC9057

22U_0603_6.3V6M

22U_0603_6.3V6M

1

1

PC9085

2

2

1U_0201_6.3V6M

1U_0201_6.3V6M

1

1

PC9106

2

2

@

1U_0201_6.3V6M

1U_0201_6.3V6M

1

1

2

2

PC9161

PC9159

@

22U_0603_6.3V6M

22U_0603_6.3V6M

PC9028

22U_0603_6.3V6M

PC9058

22U_0603_6.3V6M

PC9086

1U_0201_6.3V6M

PC9107

@

1U_0201_6.3V6M

1

1

2

PC9164

22U_0603_6.3V6M

1

2

2

PC9165

PC9166

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

+VCC_SA

1

1

1

2

PC9087

1

2

PC9108

@

1

1

2

PC9088

22U_0603_6.3V6M

1

2

PC9109

22U_0603_6.3V6M

2

2

PC9090

PC9089

22U_0603_6.3V6M

22U_0603_6.3V6M

1

1

2

2

PC9110

PC9111

@

22U_0603_6.3V6M

22U_0603_6.3V6M

1

2

2

PC9091

PC9092

22U_0603_6.3V6M

22U_0603_6.3V6M

1

2

22U_0603_6.3V6M

22U_0603_6.3V6M

1

2

PC9113

PC9112

22U_0603_6.3V6M

22U_0603_6.3V6M

D

1

1

B B

PC9124

2

1

PC9139

2

A

1

PC9125

PC9126

2

2

1U_0201_6.3V6M

1U_0201_6.3V6M

1

1

PC9140

PC9141

2

2

1U_0201_6.3V6M

1U_0201_6.3V6M

5

1

1

PC9128

PC9127

2

2

1U_0201_6.3V6M

1U_0201_6.3V6M

1

1

PC9143

PC9142

2

2

1U_0201_6.3V6M

@

1U_0201_6.3V6M

1

1

PC9129

PC9130

2

2

1U_0201_6.3V6M

1U_0201_6.3V6M

1

1

PC9144

PC9145

2

2

@

@

1U_0201_6.3V6M

1U_0201_6.3V6M

1

1

PC9131

2

1U_0201_6.3V6M

1

PC9146

2

@

1U_0201_6.3V6M

1

1

1

PC9133

PC9132

2

2

1U_0201_6.3V6M

1

2

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1

PC9148

PC9147

2

@

@

1U_0201_6.3V6M

1U_0201_6.3V6M

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2016/07/18 2017/06/14

2016/07/18 2017/06/14

2016/07/18 2017/06/14

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

1

PC9134

2

1

PC9135

PC9136

2

2

@

@

1U_0201_6.3V6M

1U_0201_6.3V6M

Title

Title

Title

Size Document Number R ev

Size Document Number R ev

Size Document Number R ev

Dat e: Sheet of

Dat e: Sheet of

Dat e: Sheet

1

PC9137

PC9138

2

2

@

@

1U_0201_6.3V6M

1U_0201_6.3V6M

C5MMH M/B LAE911P

C5MMH M/B LAE911P

C5MMH M/B LAE911P

1U_0201_6.3V6M

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

0.1Custom

0.1Custom

58 67Thursday, Febru ary 22, 2018

58 67Thursday, Febru ary 22, 2018

1

58 67Thursday, Febru ary 22, 2018

0.1Custom

of

A

A

1 1

1K_040 2_1%

1.35VSD GPU_PWR _EN<29>

2 2

VRAM_V DD_CTL<2 5>

VGA@

10K_04 02_1%

3 3

1 2

1

PR1309

PR1311

0_0402 _5%

@VGA@

2

Change the output voltage from 1.35V to 1.5V

PR1303

1.35VS_DGPU_P G<25>

VGA@

+3VS

IOCP

PR1301

1

2

1

2

1

2

G

3

PC1309

@VGA@

0.1U_0402_16V7K

VGA@

69.8K_0 402_1%

1 2

1

2

PR1310

VGA@

90.9K_0 402_1%

D

VGA@

PQ1302
L2N700 2WT1G_S C70-3

S

VGA@

12

@VGA@

1M_040 2_1%
PR1304

Rrf=470K ->290KHz
Rrf=200K ->340KHz
Rrf=100K ->380KHz

1

2

PR1312

1 2

10K_04 02_5%

ILMT_1.35 VSDGPUP

1.35VS_ DGPU_EN

PC1306

VGA@

0.1U_0402_16V7K

Frequ enc y

B

1

VGA@

PR1306

200K_0 402_1%

2

1.35VS_ DGPU_FB1.35 VS_DGPU_FB

1

VGA@

PR1308
20K_04 02_1%

2

PU1301

VGA@

RT8237 EZQW(2)_W DFN10_3 X3

1

PGOOD

2

CS

3

EN

4

FB

5

RF

VGA@

680P_0 402_50V7K

BOOT

UGATE

PHASE

LGATE

1 2

10

9

8

7

VCC

6

11

TP

PC1313

VGA@

18.7K_0 402_1%

VFB=0.704 V
Vout=0.704V* (1+Rup/Rdown)

Vout=0.704V* (1+(18.7/20))=1.36 0.97%

Vout=0.704V* (1+(18.7/(20//93.1)))=1.5 0.03%
Vout=0.704V* (1+(18.7/(20//90.9)))=1.524 1.62%
Vout=0.704V* (1+(18.7/(20//88.7)))=1.548 3.23%

Rds on 2.8 / 3.5mohm
Rlimt=69.8K

C

TYP MAX
H/S_AON6428 Rds(on) = 11.3m Ohm , 14.5m Ohm
L/S_AON6794 Rds(on) = 2.8m Ohm , 3.5m Ohm

VGA@

AON638 0 1N DFN5X6-8

PC1305

BST_1.3 5VSDGPUP

HGATE_ 1.35VSDGPUP

LX_1.35 VSDGPUP

LGATE_ 1.35VSDGPUP

PR1315

VGA@

49.9_04 02_1%

1 2

PR1307

12

VGA@

0_0603 _5%

1

PR1302

2

1

VGA@

PC1307
1U_040 2_6.3V6K

2

VGA@

0.1U_06 03_25V7K

1 2

+5VALW

VGA@

AON631 4 1N DFN5X6-8

PQ1301

PQ1303

D

VGA_EM I@

FBMA-L1 1-201209-800 LMA50T

1 2

+19VB_ 1.35VSDGPUP

1

1

5

4

1

2

3

5

4

1

2

3

Choke 0.82uH SH00000FH00/SH00000YJ00
(Size:6.95 x 6.6 x 2.8 mm)
(DCR:6.7m~8m Ohm)

1

SNB_1.35VSDGPUP

2

1

2

2

PC1302

2200P_0402_50V7K

VGA_EMI@

VGA@

0.82UH P CMC063T-R82 MN 13A_20%

1 2

PR1305

4.7_120 6_5%

VGA_EM I@

PC1308
680P_0 402_50V7K

VGA_EM I@

PC1303

0.1U_0402_25V6

@VGA_EMI@

PL1302

1

2

PC1304

10U_0805_25V6K

VGA@

100_04 02_1%

VGA@

1

2

10U_0805_25V6K

PR1314

+1.35VSDGPUP +1.35VSDGPU

1

2

2

PC1310

PC1312

0.1U_0402_25V6

VGA@

VGA_EMI@

1

+

1

2

1 2

2

PR1313 0_04 02_5%@VGA@

PJ1302

@

112

JUMP_4 3X118

PJ1303

@

112

JUMP_4 3X118

PC1301

VGA@

112

PJ1301

@

JUMP_4 3X79

220U_D2 SX_2VY_R9M

2

2

E

+19VB

PL1301

2

+1.35VSDGPUP

1

+

PC1311

2

VGA@

220U_D2 SX_2VY_R9M

FB_VDD Q_SENSE <28 >

4

Security Classification

Security Classification

Security Classification

2016/07 /18 2017/06 /14

2016/07 /18 2017/06 /14

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

2016/07 /18 2017/06 /14

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

VRAM

VRAM

VRAM

Size Document Number Re v

Size Document Number Re v

Size Document Number R ev

A3

A3

A3

C5MMH M/B LAE911P

C5MMH M/B LAE911P

C5MMH M/B LAE911P

Dat e: Sheet o f

Dat e: Sheet o f

Dat e: Sheet o f

59 67Thursday, Febru ary 22, 2018

59 67Thursday, Febru ary 22, 2018

59 67Thursday, Febru ary 22, 2018

4

0.1

0.1

0.1

A

1

VGA@

0_0402_5%

1.0VSDGPU_EN<25>

2 2

1 2

B

PC1402

VGA@

22U_0603_6.3V6M

1

2

PJ1402

@

JUMP_43X79

+3VS

EN_1.0VSDGPUP

PR1404

VGA@

1M_0402_1%

112

VGA@

1 2

4.7K_0402_5%

1

2

+3VALW

1VS_DGPU_PG<25>

PR1406

Not e:
When design Vin=5 V, please stuff snubber
to pr event Vin damage

PR1401

2

1

VGA@

0.1U_0402_16V7K

2

VIN_1.0VSDGPUP

PC1404

PU1401

VGA@

SY8032ABC_SOT23-6

4

IN

5

PG

GND

FB6EN

LX

3

2

1

LX_1.0VSDGPUP

C

Choke 1uH SH00000YG00 (Common Part)
(Size:3.8 x 3.8 x 1.9 mm)
(DCR:20 m~25m)

VGA@

PL1401

1UH_2.8A_30%_4X4X2_F

1

2

PR1403

13.7K_0402_1%

FB_1.0VSDGPUP

Rdo wn

PR1405

20K_0402_1%

Rup

VGA@

VGA@

1

PC1401

VGA@

68P_0402_50V8J

2

1

2

1

VGA_EMI@

PR1402

4.7_0603_5%

2

SNUB_1.0VSDGPUP

1

VGA_EMI@

PC1405
680P_0402_50V7K

2

D

PJ1401

@

JUMP_43X79

2

+1.0VSDGPUP +1.0VSDGPU

112

+1.0VSDGPUP

1

1

2

2

PC1406

@VGA@

1

1

2

PC1403

22U_0603_6.3V6M

22U_0603_6.3V6M

VGA@

VFB= 0. 6V
Vout=0.6V * (1+R up/Rdown)

2

PC1407

=0.6V* ( 1+13.7/20)

22U_0603_6.3V6M

Vout =1. 01 1V

VGA@

E

1

3

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE P ROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. A ND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE P ROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. A ND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE P ROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. A ND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL E LECTRONICS, INC. N EITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL E LECTRONICS, INC. N EITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL E LECTRONICS, INC. N EITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2016/07/18 2017/06/14

2016/07/18 2017/06/14

2016/07/18 2017/06/14

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

1.05VSDGPU

1.05VSDGPU

1.05VSDGPU

Size

Size

Size

Document Number R ev

Document Number R ev

Document Number R ev

C

C

C

C5MMH M/B LAE911P

C5MMH M/B LAE911P

C5MMH M/B LAE911P

Date: Sheet

Date: Sheet

Date: Sheet of

E

60 67Thursday, February 22, 2018

60 67Thursday, February 22, 2018

60 67Thursday, February 22, 2018

0.1

0.1

0.1

of

of

3

5

PR1207 for OCP setting

D

Close to PU1201

0_0402_5%

1

PR1263

10K_0402_5%

PR1232

@

0_0402_5%

1 2

PR1233 0_0402_5%@

12

@

PR1237 0_0402_5%

PR1220

1 2

PR1222
100_0402_5%

PR1224
0_0402_5%

1

PR1228
100_0402_5%

2

PR1235 0_0402_5%@

1

12

1 2

2

PR1243 100K_0402_5%

+5VS

PR1247 100K_0402_5%

6

PQ1201A

1

DMN53D0LDW-7 2N SOT 363-6

100K_0402_5%

1

5

PR1238

3

PR1230

PQ1201B

4

DMN53D0LDW-7 2N SOT 363-6

2

2

12

FBRTN

12

2

+3VS

VGA_CORE_PG<25>

VCCSENSE_VGA<27>

+VGA_CORE

VSSSENSE_VGA<27>

C C

+3VALW

VGA_CORE_EN<25,29>

+3VS

+1.8VS

DGPU_PSI <25>

B

0.01U_0402_16V7K

PR1262
0_0402_5%@

12

12

1

2

24.9K_0402_1%

GPU_TP1

GPU_TP2

GPU_LPC

NVVDD1_ENP

@

0.1U_0402_25V6

4

PC1201

0.1U_0402_25V6

1 2

PR1201

10K_0402_5%

2

PC1203

1 2

PR1218

1 2

0_0402_5%

@

PC1212

1

2

12

PR1223
1K_0402_1%

GPU_PSI

PWMVI D 的 RC BOM
請 根 據 GPU 's conf ig

設 定

DGPU_VID<25>

PR1214

0_0402_5%

1 2

PC1206

0.015U_0402_16V7K

2

PR1221

0_0402_5%

1

FBRTN

@

1 2

PC1217

12

1 2

PC1208

@

0.1U_0402_25V6

25

26

27

28

29

30

31

32

33

PR1240

0_0402_5%

+19VB_NVVDD

1

PR1206

2

91K_0402_1%

1

0.1U_0402_25V6@

1 2

12

PR1215

0_0402_5%

2

12

PR1216

2.4K_0402_1%

1

EAP

COMP

24

23

EAP

COMP

FB

FBRTN

TP1

TP2

UP9511QQKI_WQFN32_4X4

LPC

EN

PIN 30 LOW 動 作 .

PSI

PGOOD

GND

REFADJ

VID

1

2

REFADJ

R1

GPU_VID

1

PR1236

2

1

2

PC1215

4700P_0402_50V7K

PR1217
0_0402_5%

VINMON

SS

22

21

SS

PU1201

REFIN

4

3

6.19K_0402_1%

PR1241

2

4.32K_0402_1%

R2

PR1258

20.5K_0402_1%

C

2

PR1205

0_0402_5%

@

1

1

PR1207

2

10.7K_0402_1%

GPU_PROG3

20

19

IMON

PROG3

VINMON

PWM4

FSW

VREF

6

5

GPU_FSW

2

PR1234

1

33K_0402_5%

R3

1

R4

R5

12

2

PC1202

@

1

0.1U_0402_25V6

GPU_PROG1

GPU_PROG2

18

17

PROG1

PROG2

16

CSPSUM

15

CSNSUM

14

ISEN1

13

ISEN2

12

ISEN3

11

ISEN4

10

5VCC

9

PWM1

PWM3

PWM2

7

8

PWM2

Fsw=300kHz

REFIN

1

PR1249

2

16.5K_0402_1%

1

PR1256

2

309_0402_1%

FBRTN

PC1216

3

NVVDD_ISUMP2 <62>NVVDD_ISUMP1<62>

1

2

CSPSUM

ISEN1

ISEN2

5VCC

PWM1

PR1239

2

0_0402_5%

PR1245

12

0_0402_5%

2

1

0.01U_0402_16V

1

PR1202

2

20K_0402_1%

NTC_La NTC_Lb

@

@

PR1208

1

2

1 2

0_0402_5%

1 2

PR1212 0_0402_5%@

1

2

PC1204 0.1U_0402_25V6@

1 2

PC1205 0.1U_0402_25V6@

1 2

PC1207 0.1U_0402_10V6K

PR1219 1K_0402_1%

CSNSUM

PR1225 2. 2K_0402_1%

PR1226 2. 2K_0402_1%

100K_0402_5%

5VCC

1

2

GPU_PWM1 <62>

1

GPU_PWM2 <62>

layo ut 上 :

PR1203

請 將 T ota l DC R sens in g 的c ompo n en t

20K_0402_1%

放 靠 近C ont rol le r .

PR1209

0_0402_5%

12

12

12

PR1264

PR1231 2. 2_0603_1%

1U_0402_6.3V6K

PC1214

PR1210 1_0402_1%

PR1211 1_0402_1%

NTC_La

PH1201

@

1 2

470K_0402_5%_B25/50 4700K

Close to PL1301

1

PC1209

0.1U_0402_10V6K

2

layou t 上 : 請 將 RS E N 1 ~ 4
放 靠 近 C o n t r o l l e r.

GPU_PH1

GPU_PH2

12

5VCC

+5VS

12

12

12

NTC_Lb

請 教 A U TO

P H A S E 的 設 定

2

PR1242

1

GPU_PROG1

2

PR1251

1

2

NVVDD_ISUMN1 <62>

NVVDD_ISUMN2 <62>

For N 17P-G1, TDP 50W

NVV DD1
TDC = 4 5+13=58A
Peak Current = 106+18=124A
OCP = 1 48A

+5VS

2

1

43K_0402_5%

GPU_PROG2

2

1

8.2K_0402_5%

2

PR1246

1

@

36K_0402_5%

GPU_PROG3

2

PR1252

1

8.2K_0402_5%

Cold Boot = 4-phase
Warm Boot = 4-phase

PR1244

51K_0402_5%

PR1255

0_0402_5%

@

@

1

2

PR1248

1

10K_0402_5%

GPU_LPC

2

PR1257

0_0402_5%

1

D

B

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE P ROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. A ND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE P ROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. A ND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE P ROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. A ND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL E LECTRONICS, INC. N EITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL E LECTRONICS, INC. N EITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL E LECTRONICS, INC. N EITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2016/07/18 2017/06/14

2016/07/18 2017/06/14

2016/07/18 2017/06/14

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size

Size

Size

Date: Sheet

Date: Sheet of

Date: Sheet

Compal Electronics, Inc.

PWR_VGA_UP9511P

PWR_VGA_UP9511P

PWR_VGA_UP9511P

Document Number R ev

Document Number R ev

Document Number R ev

C5MMH M/B LAE911P

C5MMH M/B LAE911P

C5MMH M/B LAE911P

1

61 67Thursday, February 22, 2018

61 67Thursday, February 22, 2018

61 67Thursday, February 22, 2018

1.0

1.0

1.0

of

of

1

+19VB

A

GPU_PWM1<61>

+19VB_NVVDD

B B

+5VS

2

PR1502

0_0402_5%

@

1

+5VS

2

1U_0402_6.3V6K

1

PR1505

0_0402_5%

1

@

2

1

1

PC1505

PC1504

2

2

0.1U_0402_25V6

EMI@

2200P_0402_50V7K

@EMI@

PL1502

EMI@

FBMA-L11-201209-800LMA50T

1 2

PL1503

EMI@

FBMA-L11-201209-800LMA50T

1 2

PR1504
1K_0402_1%

PC1502

1

12

2

PC1506

10U_0603_25V6M

PC1508

PC1507

10U_0603_25V6M

10U_0603_25V6M

@

12

PR1501

1 2

0_0402_5%

1

2

PC1509

@

+19VB_NVVDD

0.1U_0402_50V7K

1

2

10U_0603_25V6M

PC1501

1 2

2

PU1501

1

PWM

2

ZCD_EN #

3

VCIN

4

CGND

5

BOOT

6

NC

7

PHASE

8

VIN

9

VIN

10

PGND

11

SW

12

SW

13

SW

14

SW

SIC632CDT1GE3_POWERPAK31_5X5

1

1

2

2

PC1510

PC1511

10U_0603_25V6M

10U_0603_25V6M

CGND

DSBL#

THW n

VDRV

PGND

28
27

GL

26
25
24
23
22

GL

21

SW

20

SW

19

SW

18

SW

17

SW

16

SW

15

SW

3

PR1503

10K_0402_1%

1 2

PR1506

2.2_0603_1%

PC1503

1U_0603_16V7

1

2

+5VS

12

1

EMI@

PR1507

4.7_1206_5%

2

GPU_SNB1

1

EMI@

PC1512
680P_0402_50V7K

2

4

VGA_CO RE
Vboot= 0.8V
TDC=58 A
Peak Current=124A
OCP=14 8A
FSW=30 0kHz
Dr.MOS SIC632 TYP MAX
H/S Rds(on) = 4.8mohm ,5.76mohm
L/S Rds(on) = 1.3mohm ,1.56mohm

Choke 0.22uH SH00000QZ00

GPU_PH1

0.22UH_MMD-10DZ-R22MES1L__35A_20%

GPU_PH1

NVVDD_ISUMP1<61>

NVVDD_ISUMN1<61>

PL1501

1

2

4

3

5

+VGA_CORE

A

+5VS

2

PR1508

0_0402_5%

@

1

C

D D

GPU_PWM2<61>

+19VB_NVVDD

+5VS

PC1513

1U_0402_6.3V6K

1

PR1511

0_0402_5%

1 2

@

2

1

1

PC1517

PC1516

2

2

0.1U_0402_25V6

@EMI@

1

PC1518

EMI@

10U_0805_25VAK

2200P_0402_50V7K

PR1510
1K_0402_1%

12

PR1513

2

1

1

1

2

1

2

2

PC1519

PC1520

10U_0603_25V6M

10U_0805_25VAK

0_0402_5%

1

2

PC1521

10U_0603_25V6M

PC1514

1 2

0.1U_0402_50V7K

2

PU1502

1

PWM

2

ZCD_EN #

3

VCIN

4

CGND

5

BOOT

6

NC

7

PHASE

8

VIN

9

VIN

10

PGND

11

SW

12

SW

13

SW

14

SW

SIC632CDT1GE3_POWERPAK31_5X5

28

CGND

27

GL

26

DSBL#

25

THW n

24

VDRV

23

PGND

22

GL

21

SW

20

SW

19

SW

18

SW

17

SW

16

SW

15

SW

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

3

+5VS

PR1509

2

10K_0402_1%

PR1512

2.2_0603_1%

12

PC1515

1U_0603_16V7

1

2

1

2

GPU_SNB2

1

2

Compal Secret Data

Compal Secret Data

2016/07/18 2017/06/14

2016/07/18 2017/06/14

2016/07/18 2017/06/14

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

EMI@

PR1514

4.7_1206_5%

EMI@

PC1522
680P_0402_50V7K

GPU_PH2

NVVDD_ISUMP2<61>

NVVDD_ISUMN2<61>

0.22UH_MMD-10DZ-R22MES1L__35A_20%

GPU_PH2

4

1

2

PL1504

4

3

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date : Sheet

Date : Sheet

Date : Sheet

Compal Electronics, Inc.

PWR_+NVVDD1

PWR_+NVVDD1

PWR_+NVVDD1

C5MMH M/B LAE911P

C5MMH M/B LAE911P

C5MMH M/B LAE911P

5

+VGA_CORE

62 67Thursday, February 22, 2018

62 67Thursday, February 22, 2018

o f

o f

o f

62 67Thursday, February 22, 2018

1.0

1.0

1.0

C

5

4

3

2

1

+VGA_C ORE +VGA_C ORE

+VGA_CORE
560uF_OS X 2
220uF_D2 X 3(+1@)

PC1708

1U_0402_6.3V6K

PC1709

PC1704

PC1702

1U_0402_6.3V6K

PC1701

1U_0402_6.3V6K

1

D

C C

1

2

2

VGA@

VGA@

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M
PC1716

PC1715

1

1

2

2

VGA@

@VGA@

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

PC1729

1

2

1

2

PC1730

1

2

VGA@

VGA@

10U_0603_6.3V6M

10U_0603_6.3V6M

PC1745

PC1744

1

2

VGA@

VGA@

1U_0402_6.3V6K

PC1703

1U_0402_6.3V6K

1

12

2

VGA@

4.7U_0402_6.3V6M
PC1717

1

1

2

2

VGA@

4.7U_0402_6.3V6M
PC1731

1

1

2

2

VGA@

10U_0603_6.3V6M

PC1746

1

1

2

2

VGA@

PC1705

1U_0402_6.3V6K

1

1

2

2

VGA@

VGA@

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

PC1718

PC1719

1

1

2

2

VGA@

VGA@

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

PC1732

PC1733

1

1

2

2

VGA@

VGA@

10U_0603_6.3V6M

10U_0603_6.3V6M

PC1769

PC1770

1

1

2

2

VGA@

VGA@

PC1707

1U_0402_6.3V6K

PC1706

1U_0402_6.3V6K

1

2

VGA@

VGA@

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M
PC1721

PC1720

1

2

VGA@

VGA@

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M
PC1735

PC1734

1

2

VGA@

VGA@

10U_0603_6.3V6M

22U_0603_6.3V6M

PC1775

PC1747

12

VGA@

VGA@

1U_0402_6.3V6K

1

1

2

2

VGA@

VGA@

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M
PC1722

1

1

2

2

VGA@

4.7U_0402_6.3V6M
PC1736

1

1

2

2

VGA@

22U_0603_6.3V6M

PC1748

1

1

2

2

@VGA@

PC1724

PC1723

1

2

@VGA@

@VGA@

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M
PC1738

PC1737

1

2

@VGA@

@VGA@

22U_0603_6.3V6M

PC1749

VGA@

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

PC1751

PC1750

1

1

2

2

VGA@

VGA@

22uF_0805 X 0(+3@)
22uF_0603 X 27(+8@)
10uF_0603X 16

4.7uF_0402 X 20(+7@)
1uF_0402 X 14

22U_0603_6.3V6M

@VGA@

PC1710

1

2

10U_0603_6.3V6M

VGA@

PC1725

1

2

4.7U_0402_6.3V6M

VGA@

PC1739

1

2

VGA@

1U_0402_6.3V6K

PC1752

1

2

22U_0603_6.3V6M

22U_0603_6.3V6M

VGA@

@VGA@

PC1712

PC1711

1

1

2

2

22U_0603_6.3V6M

10U_0603_6.3V6M

VGA@

VGA@

PC1766

PC1726

1

1

2

2

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

VGA@

@VGA@

PC1740

PC1741

1

1

2

2

VGA@

VGA@

1U_0402_6.3V6K

1U_0402_6.3V6K

PC1753

1

2

PC1754

1

2

22U_0603_6.3V6M

22U_0603_6.3V6M

VGA@

VGA@

PC1714

PC1713

1

1

2

2

22U_0603_6.3V6M

22U_0603_6.3V6M

@VGA@

@VGA@

PC1767

1

2

1

2

1

2

PC1768

1

2

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

VGA@

@VGA@

PC1743

PC1742

1

2

VGA@

VGA@

1U_0402_6.3V6K

1U_0402_6.3V6K

PC1756

PC1755

1

2

D

22U_0603_6.3V6M

22U_0805_6.3V6M

PC1757

1

B

A A

2

@VGA@

1

PC1781

2

VGA@

22U_0603_6.3V6M

1

PC1787

2

22U_0603_6.3V6M

VGA@

5

22U_0603_6.3V6M

PC1758

1

2

1

2

1

2

PC1759

1

2

VGA@

VGA@

1

PC1782

PC1783

2

VGA@

22U_0603_6.3V6M

VGA@

22U_0603_6.3V6M

1

PC1789

PC1788

2

22U_0603_6.3V6M

VGA@

22U_0603_6.3V6M

VGA@

22U_0603_6.3V6M

22U_0805_6.3V6M

PC1760

1

2

@VGA@

1

PC1784

2

VGA@

22U_0603_6.3V6M

1

PC1790

2

22U_0603_6.3V6M

VGA@

22U_0805_6.3V6M

PC1761

1

2

1

2

1

2

PC1762

1

2

@VGA@

@VGA@

1

PC1785

PC1786

2

22U_0603_6.3V6M

VGA@

VGA@

22U_0603_6.3V6M

1

PC1791

PC1792

2

VGA@

22U_0603_6.3V6M

22U_0603_6.3V6M

@VGA@

22U_0603_6.3V6M

22U_0603_6.3V6M

PC1764

PC1763

1

1

2

2

VGA@

VGA@

1

1

PC1798

PC1797

2

2

22U_0603_6.3V6M

VGA@

VGA@

22U_0603_6.3V6M

1

1

PC1794

PC1793

2

2

22U_0603_6.3V6M

VGA@

22U_0603_6.3V6M

@VGA@

10U_0603_6.3V6M

22U_0603_6.3V6M

PC1765

1

2

VGA@

1

+

PC1771

2

VGA@

220U_D2 SX_2VY_R9M

1

PC1795

2

VGA@

22U_0603_6.3V6M

4

10U_0603_6.3V6M

PC1778

1

2

1

+

2

1

2

PC1779

1

10U_0603_6.3V6M

2

VGA@

VGA@

1

+

PC1773

PC1772

2

560U_2.5V_M

VGA@

VGA@

220U_D2 SX_2VY_R9M

10U_0603_6.3V6M

PC1780

1

PC1796

2

22U_0603_6.3V6M

VGA@

VGA@

Security Classification

Security Classification

Security Classification

2016/07 /18 2017/06 /14

2016/07 /18 2017/06 /14

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

2016/07 /18 2017/06 /14

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

10U_0603_6.3V6M

VGA@

PC1727

1

1

2

2

1

1

+

+

PC1776

PC1777

2

2

VGA@

@VGA@

220U_D2 SX_2VY_R9M

Deciphered Date

Deciphered Date

Deciphered Date

VGA@

PC1728

220U_D2 SX_2VY_R9M

10U_0603_6.3V6M

10U_0603_6.3V6M

VGA@

PC1799

1

2

1

+

PC1774

2

560U_2.5V_M

VGA@

10U_0603_6.3V6M

VGA@

VGA@

PC17991

1

2

PC17992

1

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Dat e: Sheet o f

Dat e: Sheet o f

2

Dat e: Sheet

Compal Electronics, Inc.

VGA DECOUPLING

VGA DECOUPLING

VGA DECOUPLING

C5MMH M/B LAE911P

C5MMH M/B LAE911P

C5MMH M/B LAE911P

0.1

0.1

0.1

o f

63 67Thursday, Febru ary 22, 2018

63 67Thursday, Febru ary 22, 2018

63 67Thursday, Febru ary 22, 2018

1

B

5

4

3

2

1

Version change list (P.I.R. List) Page 1 of 1 for PWR

Item

01

Design Update

02

D D

C

B

A A

Design Update

03

Design Update

04

Design Update

05

Design Update

06

Design Update Solution Change

07

Design Update Down size for MLCC

08

Design Update Down size for EMI MLCC

09

Design Update Down size for MLCC

10

Design Update Solution Change

11

   Down size for Jump

12

Design Update

13

Design Update Solution Change

14

Design Update CPU transient test result

15

Design Update Power sequence

16

Design Update Solution Change

17

Design Update Solution Change

18

Design Update Solution Change

Reason for change

Solution Change

Solution Change

Solution Change

Down size for SNB MLCC

Solution Change

5

Rev. PG#

Change the PQ310 from AON6366E (SB00001D800) to EMB04N03H (SB00001C500).

0.2

0.2

0.2

50

53

54

0.2 63

0.2

5 0 5 9 62

0.2

59

0.2 59

0.2 48

0.2 63

0.2 56

0.2 53

0.2

5 6 5 7

0.2 58

0.2

5 6 5 7 58

0.2

5 9 6 0

0.2

0.2

0.2

61 11/08

5 2 5 6 57 Change the PC8317PC509 P C517 fr om 1 U_0402_1 0V6K ( SE0000 0QL 10) to 1 U_0201 _6. 3V6K ( SE00000YB00).

5 0 5 6 Change the PR340P Q31 4 PQ31 3A PQ313B PR32 7 PQ3 07 PQ30 8 fro m p op to un-po p.

4

Change the PQ311P Q31 2 fro m AON6366E ( SB00001 D800) to AON7380 ( SB00001 G M00).
Change the PC302PC303 PC310 PC31 1 PC 312 f rom 1 0U_0603_ 25V ( SE00 000X2 00) to 10U_0805_ 25 V ( SE00 000QK00).
Delete the PC323 10U_0603_25V (SE00000X200).

Change the PR603 (10K_0402_1%, SD034100280) from pop to un-pop. 10/13

Change the PR7126 (100K_0402_5%, SD028100380) from un-pop to pop.

Change the PR7126.2 net from +3VS to +3VALW.

Change the PC1748PC1 761PC1710 PC1 712P C1767 PC 1768 ( 22U_0603_6 . 3V, SE0 0000M000) from po p to un-pop.Solution Change 10/13

Change the PC315PC1 308 PC1512P C1 5 22

from 680P_50V_K_X7R_0603 (SE025681K80) to 680P_50V_K_X7R_0402 (SE074681K80).
Change the PQ1302 from 2N7002KW (SB000009Q80) to L2N7002WT1G (SB00000ST00).

Change the PC1307 from 1U_6.3V_M_X5R_0603 (SE107105M80) to 1U_6.3V_K_X5R_0402 (SE000000K80).

Change the PC102 from 100P_50V_J_NPO_0603 (SE024101J80) to 100P_50V_J_NPO_0402 (SE071101J80).

Change the PC104 from 1000P_50V_K_X7R_0603 (SE025102K80) to 1000P_50V_K_X7R_0402 (SE074102K80).

Change the PC1747P C1759 PC1 749 P C1 758 P C1764 P C1 766 P C1713

from 22U_6.3V_M_X5R_0805(SE000000I10) to 22U_6.3V_M_X5R_0603 (SE00000M000).
Change the PH8103P H8104 fro m 150K_5 %_0402_B25/50_4500K ( SL200002K00) t o 220K_5 %_0402_B25/ 50_4700K ( SL200002I00).

Change the PR8109P R811 0 fro m 8. 87K_0402_1 % ( SD0348871 80) to 8. 66K_0402_1 % ( SD0348661 80).
Change the PR8118PR811 9 fro m 93. 1K_0402_1 % ( SD034931 280) to 57. 6K_0402_1 % ( SD034576280).

Change the PJ602 from 43X79 to 43X39. 10/23

Change the PC8113P C81 24 PC8140 PC8159PC8 1 63

from 0.47U_16V_Z_Y5V_0402 (SE000002F80) to 0.47U_6.3V_K_X5R_0402 (SE124474K80).
Change the PC8310 from 0.47U_25V_K_X5R_0402 (SE00000WA00) to 0.47U_6.3V_K_X5R_0402 (SE124474K80).

Add the location PC9164PC91 65 P C9166 and pop, 22U_6. 3V _M_X5R_0603 ( SE0000 0M000).

Change the PR8114 from 6.81K_0402_1% (SD034681180) to 5.76K_0402_1% (SD034576180).
Change the PR8113 from 2.49K_0402_1% (SD034249180) to 1.8K_0402_1% (SD00000R580).
Change the PR8117 from 560K_0402_1% (SD034560380) to 442K_0402_1% (SD034442300).
Change the PR8116 from 510K_0402_1% (SD00000RK80) to 402K_0402_1% (SD034402380).
Change the PR8141 from 100_0402_1% (SD034100080) to 8.2K_0402_1% (SD000004100).
Change the PR8149 from 1.05K_0402_1% (SD00000J480) to 3.16K_0402_1% (SD000006580).
Change the PR8176 from 20K_0402_1% (SD034200280) to 16.9K_0402_1% (SD034169280).
Change the PR8310 from 63.4K_0402_1% (SD03463K280) to 59K_0402_1% (SD034590280).
Change the PR8319 from 24.9K_0402_1% (SD034249280) to 22K_0402_1% (SD034220280).
Change the PR8325 from 0_0402_5% (SD028000080) to 300_0402_1% (SD034300080).
Change the PR8328 from 22K_0402_1% (SD034220280) to 20K_0402_1% (SD034200280).
Change the PR8333 from 680_0402_1% (SD034680080) to 300_0402_1% (SD034300080).
Change the PC8312 from 270P_0402_50V7K (SE074271K80) to 330P_0402_50V8J (SE000006I80).
Change the PR8331 from 470_0603_1% (SD014470080) to 576_0603_1% (SD014576080).
Change the PR8336 from 42.2_0402_1% (SD00000ZN00) to 255_0402_1% (SD034255080).
Change the PR8134 from 121K_0402_1% (SD034121380) to 13.3K_0402_1% (SD034133280).
Change the PR8138 from 49.9K_0402_1% (SD034499280) to 26.7K_0402_1% (SD034267280).
Change the PR8147 from 3.32K_0402_1% (SD034332180) to 768_0402_1% (SD00000TT80).
Change the PC9110P C91 08 fro m 22 U_0603_6. 3V6 M ( SE00000 M000) to un- pop.
Change the PC9112P C911 3 fro m un- pop to 22 U_0603_6. 3V6 M ( SE00000 M000).
Change the PC8126 from 330P_0402_25V8J (SE00000FD80) to 330P_0402_50V8J (SE000006I80).
Change the PR8173 from 0_0603_5% (SD013000080) to 10_0603_1% (SD014100A80).
Change the PC8137 from 330P_0402_25V8J (SE00000FD80) to 270P_0402_50V7K (SE074271K80).
Change the PC9159P C91 60 fro m 22 U_0603_6. 3V6 M ( SE00000 M000) to un- pop.
Change the PC9057PC9058 fro m un-pop to 22 U_0603_6. 3V6 M ( SE00000 M000).

Change the PR1303 from 10K_0402_1% (SD034100280) to 1K_0402_1% (SD034100180).
Change the PR1401 from 10K_0402_5% (SD028100280) to 4.7K_0402_5% (SD028470180).

Change the PU1201 from UP9511P (SA00009SW00) to UP9511Q (SA0000BK300).
Change the PR1243P R1 247 fro m 1 0K_0402_5 % ( SD0281 00280) to 1 00K_0402_5 % ( SD0281 00380).

Change the PC8112PC811 5 P C8123 PC8139PC8157 PC8161 fr om 1 U_0402_25V6K ( SE000010V00) t o 1 U_0201 _6. 3V6K ( SE00000YB00).

Change the PR326 from un-pop to 0_0603_5% (SD013000080)
Change the PR310 from 51.1K_0402_1% (SD034511280) to 52.3K_0402_1% (SD034523280)
Change the PC8147 from
10U_0805_25V_X5R
(SE00000QK00) to un-pop

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

Modify List Date PhaseFixed Issue

Compal Secret Data

Compal Secret Data

2016/01/29 2017/06/14

2016/01/29 2017/06/14

2016/01/29 2017/06/14

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

10/13

A2

A2

10/13

A2

A2

10/13

10/13

10/13

10/13

10/13

10/23

A2

A2

A2

A2

A2

A2

A2

10/25

10/26

10/27

11/02

A2

A2

A2

A2

A2

11/08

11/14

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

PIR

PIR

PIR

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

DH53F M/B LA-E951P

DH53F M/B LA-E951P

DH53F M/B LA-E951P

Date : Sheet o f

Date : Sheet o f

Date : Sheet o f

1

A2

A2

64 67Thursday, February 22, 2018

64 67Thursday, February 22, 2018

64 67Thursday, February 22, 2018

0.1

0.1

0.1

C

B

5

4

3

2

1

Version change list (P.I.R. List) Page 2 of 2 for PWR

Item

19

Design Update

20

Design Update Solution Change

D D

21

Design Update Solution Change

22

Design Update Solution Change

23

Design Update SW2 un-pop

24

Design Update Solution Change

25

Design Update Solution Change

26

Design Update 4S_BATT

27

Design Update Solution Change

28

Design Update

29

C

Design Update Power sequence

30

Design Update 3valw interfere

31

Design Update Solution Change 01/12

Reason for change

Solution Change

ACIN_CHG 1.0

Rev. PG#

1.0

1.0

1.0

1.0

1.0

1.0

1.0

1.0

1.0

50

5 0 5 5
5 6 5 7

50

56

49

50

56

50

50

50

1.0

1.0

1.A

60

5 5 5 9

55

Change the PR304P R31 4 PR316 P R322 PR334PR81 11 PR8120PR8128P R81 39 P R81 42 PR8143P R81 53 PR 8 1 5 4
PR8155P R81 65 P R81 70 PR8175 P R81 9 0 P R81 29 PR81 63PR8184P R81 98 P R8204 P R8308 P R83 2 6  PR83 39 
PR8341P R8342 PR8346 PR317 PR 333 f r o m 0_040 2_5%( SD0280000 80) to R- shor t.

Change the PC305P C324 fro m 0. 1 U_0402_25V7K( SE00000 W210) to 0. 1 U_0402_25V6 ( SE00000G880).

Change the PC8101P C81 22 PC8135 PC8150PC8158 fr om 0. 1 U_0603_50V7K( SE0251 04K80)

to 0.1U 25V K X7R 0603 (SE042104K80).
Change the PR217 from un-pop to 0_0402_5%(SD028000080).

Change the PR326PR7202 fro m 0_0603_5 %( SD01 3000080) t o R-s hort. 12/18

Add PC8116P C811 8, 33U_D1 _25V M_R6 M ( SGA0000A400), and un-pop.

Delete location PR326P R327 PQ307 PQ308
Add location PR338->2M_0402_1% (SD034200480)PR339->1 00K_0402_1 % ( SD0341 00380)
Add location PQ315->LTC015EUBFS8TL(SB000011K00)P Q31 6-> 2 N7002K W 1 N SOT323- 3 ( SB00000ST00)

Change the PC309 from 0.22U_0603_25V(SE000005Z80) to 0.47U_0402_16V(SE000002F80).

Change the PR306 from 392K_0402_1%(SD034392380) to 499K_0402_1%(SD034499380).
Change the PR310 from 52.3K_0402_1%(SD034523280) to 66.5K_0402_1%(SD034665280).

Change the PR1406 from 10K_0402_1%(SD034100280) to 0_0402_5%(SD028000080).

Change the Jump PJ7202P J1 301 fro m short to open.
Change the bead PL7201PL1301 fro m un- pop to pop 0805_5A ( S M01000U600).
Change the PR7203 from un-pop to pop 4.7_1206_5% (SD001470B80)

Change the PC7203 from un-pop to pop 680pF_0402_50V (SE074681K80)

Change the PR7202 from R-short to 0_0603_5%(SD013000080).

Modify List Date PhaseFixed Issue

12/15Change the PC313PC31 4 fro m 1 U_1 6V_X5R_0402( SE00000 OU00) to 1 U_6. 3V_X5R_0201 ( SE00000YB00).

12/15

12/18

12/18

12/18

C

C

C

C

C

C

12/19

12/20

12/21

12/25

12/27

01/10

C

C

C

C

C

C

C

C

B

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2016/01/29 2017/06/14

2016/01/29 2017/06/14

2016/01/29 2017/06/14

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

PIR

PIR

PIR

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

C5MMH M/B LA-E911P

C5MMH M/B LA-E911P

C5MMH M/B LA-E911P

Date : Sheet o f

Date : Sheet o f

2

Date : Sheet o f

1

65 67Thursday, February 22, 2018

65 67Thursday, February 22, 2018

65 67Thursday, February 22, 2018

0.1

0.1

0.1

B

A

Version change list (P.I.R. List)

B

C

D

E

Page 1 of 1 for HW

Item Page PhaseSolution DescriptionTitle

1

1 1

2

3

39

37

4

Design Update power source optimization

Design Update

Design Update 10/19

5

41,42

6

7

2 2

8

9

10

11

44

39

38

43

25

Design Update

Design Update

Design Update

Design Update

Design Update

Date

9/27

9/27

10/24

10/25

10/26

10/26

Issue Description

CNVI power request10/17Design Update

0 ohm part count reduce

for cost, change 10uF_0402 to 0603

CNVI device detact issue

for reserve 4 dmic

SATA HDD redriver EQ tuning

NV vga sequence tuning11/02

DGPU1.8V power source change to 1.8VALW

Change board ID to DVT (V15_ID1/VX15_ID11)version upgrade

Add RM44 for +3VALW to +3VS_WLAN

RH186/RH47/RH103/RH105/RH97/RH98/RH99/RH100/
RD3/RD6/RD2/RD15/RD13/RD17/RM22/RM23/RM24/
RM25/RM26/RM27/RM28/RM29/RM30/RM31/RM32/
RM33/RM34/RM35/RM38/RM39/RM40/RS1/RS8/RS16/
R19/R20/RQ5/RQ9/RQ6

LS1/LS10 change footprint to "MURAT_DLM0NSN900HY2D_4P"USB common voltage footprint updateDesign Update 10/19

CV75, Cv83, CV86, Cc88, CV87, Cv83, Cv73, Cv82,Cv108, Cv119, Cv118, Cv110,
Cv120, Cv121, Cv114, Cv115 , CC75, Cc73, Cc80, CC74,CC76, CC78, CC79, CX1
CX3, CA6, CA8, CA9, CA16, CA17, CC71, CC72, CC81, CC89, CC90,

add L11/ L12 for USB2.0 CMCUSB CMC move to M/BDesign Update

add PU 100K RB78 for CNVI card detect
reserved RB79 PD 0ohm for CNVI card detect
EC add PIN89 GPIO50 as CNVI_DET#
add PIN 19 CNVI_DET#

Change JDMIC1 to 4pin : SP02000TI00

UNPOP RO17 for redriver EQ11/02

change RV105 to 8.2K (vga_core_en)
RV12 change to 100k_1% (1.35VSDGPU_PWR_EN)
RV113 change to 4.7k_5%
PR1303 change to 1k
PR1401 change to 4.7k

A229

Rev.

0.2

0.2A2

0.2A2

0.2A2

0.2A2

0.2A2

0.2A2

0.2A2

0.2A2

0.2A2

0.2A2

12

3 3

13

14

15

16

17

18

4 4

19

20

43

45

40

18

46

39

40

11/06Design Update add CO14/CO16~18/RO21~24 for no re-driver.

co-lay no HDD re-driver circuit

Design Update 11/13 for factory request, don't include SW1 in bom unpop SW1 and control by SMT memo

Design Update 11/13

Design Update 11/13 fine tune crystal frequency

0 OHM change to R-short change RC17/RH5/RH6/RH94/RH96/RV125/RM2/RB19/RB76/RO4

peci issue, can't get system temperature UNPOP RH41

Design Update

12/14Design Update PVT

12/14 PVT

Design Update 12/14

Design Update 12/16

Design Update 12/18

A

change typeC VCONN sol to G527

B

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET O F ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET O F ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET O F ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTODY O F THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTODY O F THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTODY O F THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, I NC. NEITHER THIS SHE ET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, I NC. NEITHER THIS SHE ET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, I NC. NEITHER THIS SHE ET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT O F COMPAL EL ECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT O F COMPAL EL ECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT O F COMPAL EL ECTRONICS, INC.

C

unpop QS1/RS107/RS108 POP RS114/RS115replace level shift by 0 ohm on Type-C circuit

24Mhz Keep 33 18 /1M
25Mhz Keep 10 18 /330
27Mhz CV1 change to 15PF (15 12 /0)

32.768Khz change CH7/CH8 to 10PF (10 10 /10M)

/RS114/RS115 to R-short

unpop SW2(BI SW)

channge board ID to ver1.0 (V series 15k/ vx series 200k) PVT

add RS116 on VBUS_EN_179
change US2 to SA00006Y700, add RS156/RS155/CS101/CS124

Compal Secret Data

Compal Secret Data

2017/12/18 2018/09/01

2017/12/18 2018/09/01

2017/12/18 2018/09/01

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

0.2A2

0.2A2

A2 0.2

A2 0.2

1.0

1.0

PVT

1.0

1.0

PVT

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

PIR-HW1

PIR-HW1

PIR-HW1

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

Dat e: Shee t o f

Dat e: Shee t o f

D

Dat e: Shee t o f

E

1.0

1.0

1.0

66 6 7Thursday, February 22, 2018

66 6 7Thursday, February 22, 2018

66 6 7Thursday, February 22, 2018

1.0

A

Version change list (P.I.R. List)

B

C

D

E

Page 1 of 1 for HW

Item Page PhaseSolution DescriptionTitle

21

22

1 1

23

24

25

26

27

28

2 2

29

30

31

32

33

37

25

21

45

37

21 add CH52 0.1U on +1.8VALW_PRIM

37

21

38

32

18, 35

18

32

7

19

Design Update 12/18 BT lost issue reserve RM45 for pull up BT_ON to +3VS_WLAN PVT

Design Update

Design Update

Design Update 12/21 intel ECN_Update

Design Update

Design Update

Design Update

Design Update

Design Update 01/11 improve optone layout for HM370

Design Update 01/11 HDD port change to SATA0B

Design Update 01/11 JTYPEC1.A2/A3/B2/B3 change to NET NAME

Design Update

Design Update

Date

12/20

12/20

12/22

12/26

12/26

12/26

02/22

02/22

Issue Description

vga sequence tuning change RV105 to 6.2k / RV103 to 24.9k PVT

intel sensitive net

CNVI lost issue

pop CH29 & CH34

Change RS64,RS65,RS74,RS76,RS82~RS85 to 0201 size.

Add CS102~CS105,RS119~RS122.

reserve CM18 on CNV_RF_RESET#

PVT

PVT

PVT

reserve CM19 4.7uF on +3VS_WLAN

CNVI lost issue

reserve CH53_10uF on +1.8VALW_PRIM

PVT

change RH100 R-short to 0_0603

charmeleon down z-high on wi-fi card area

improve HDMI layout

change CA6/CA17 to 0402 package PVT

remove GPAK circuit for improve HDMI layout
del U18/CV225/RV126/RV125/CG341/CG342

change PCIE port from 17-20 to 12-9
change from SSD_DEVSLP4 to SSD_DEVSLP1
change from SATA_GP4 to SATA_GP1

PVT

PVT

PVT

PVT 1A

UC1/UH1/UV1/ change to MP part numberchange PN for MP chip

PVT 1A

PVT memo improve POP RH183 Remove CQ7/CQ8 PVT 1A

Rev.

1.0

1.0

1.0

1.0

1.0

1.0

1.0

1.0

1A

1A

3 3

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET O F ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET O F ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET O F ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTODY O F THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTODY O F THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTODY O F THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, I NC. NEITHER THIS SHE ET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, I NC. NEITHER THIS SHE ET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, I NC. NEITHER THIS SHE ET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT O F COMPAL EL ECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT O F COMPAL EL ECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT O F COMPAL EL ECTRONICS, INC.

C

2017/12/18 2018/09/01

2017/12/18 2018/09/01

2017/12/18 2018/09/01

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

PIR-HW1

PIR-HW1

PIR-HW1

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

DH5VF M/B LA-F591PR01

Dat e: Shee t o f

Dat e: Shee t o f

D

Dat e: Shee t o f

E

67 6 7Thursday, February 22, 2018

67 6 7Thursday, February 22, 2018

67 6 7Thursday, February 22, 2018

1.0

1.0

1.0