Acer Nitro 5 AN517-52 Schematic
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
Compal Confidential
MB Schematic Document
2020.02.11
Rev:1.0
LA-J871P
FH51M
Title
Size Document Number R e v
Date: Sheet o f
Security Classification
Compal Secret Data
THIS SHEET OF ENGINE ERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, IN C. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFO RMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTODY OF THE COMP ETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHEET NOR THE INFORM ATION IT CONTAINS
MAY BE USED BY OR DIS CLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELEC TRONICS, INC.
Issued Date
Deciphered Date
1.0
Cover Sheet
Custom
1 112Tuesday, F ebruary 11, 2020
2019/09/20 2020/09/20
Compal Electronics, Inc.
FH51M M/B LA-J871P
Title
Size Document Number R e v
Date: Sheet o f
Security Classification
Compal Secret Data
THIS SHEET OF ENGINE ERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, IN C. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFO RMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTODY OF THE COMP ETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHEET NOR THE INFORM ATION IT CONTAINS
MAY BE USED BY OR DIS CLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELEC TRONICS, INC.
Issued Date
Deciphered Date
1.0
Cover Sheet
Custom
1 112Tuesday, F ebruary 11, 2020
2019/09/20 2020/09/20
Compal Electronics, Inc.
FH51M M/B LA-J871P
Title
Size Document Number R e v
Date: Sheet o f
Security Classification
Compal Secret Data
THIS SHEET OF ENGINE ERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, IN C. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFO RMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTODY OF THE COMP ETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHEET NOR THE INFORM ATION IT CONTAINS
MAY BE USED BY OR DIS CLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELEC TRONICS, INC.
Issued Date
Deciphered Date
1.0
Cover Sheet
Custom
1 112Tuesday, F ebruary 11, 2020
2019/09/20 2020/09/20
Compal Electronics, Inc.
FH51M M/B LA-J871P
www.laptoprepairsecrets.com
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
Cof f eeLake H Pr ocess or
BGA1440 (42X28)
(CFL-H & CML-H _ 8+2)
Cannonlake PCH - H
FCBGA874 (25X24)
CFL-H : HM370
CML-H : HM470
Memory BUS
LPC/eSPI BUS
Int.KBD
Interleaved (DDR4 2400/2666)
SPI
P.23
SPI ROM 16M
TPM
X4 DMI
PEG x16
8GT/s
P.27-37
N18P-G61/G62
- DDR4 So-DIMM 260 pin
- Channel A
- BANK 0,1,2,3
- Address : 0XA0/1
- DDR4 So-DIMM 260 pin
- Channel B
- BANK 4,5,6,7
- Address : 0XA3/4
P.24
P.6-13
P.14-21
- SOP8
- Size : 16M
P.16
- KSI/KSO
- W/BL or 4 Zone RGB
P.66
P.63
EC KB9022
P.58
I2C/PS2
HDA Codec
- ALC295
P.56
HD Audio
Audio Jack
- On IO/B
Int. DMIC
- On CCD Module
Int. Speaker
- ON IO/B > L
- ON M/B > R
- GEN2
- On M/B
- Port 1
P.71
USB3.1 - JUSB 1
- Port 5
P.38
DDC Camera
- W/USB Charger
(SLGC55544)
- PCIE 2.0 5GT/s
- Port 14
LAN(GbE) JRJ45
- E2600
- SATA 3.0
- Port 13
(SATA 0B)
P.67
HDD - JHDD1
P.68
SSD - JSSD1 (PCIE)
- PCIE 2.0 5GT/s
- PCIE Port 21-24
P.68
SSD - JSSD2 (PCIE/SATA)
- PCIE 2.0 5GT/s
- PCIE Port 9-12
- SATA @ Port 12
P.69
- PCIE 2.0 5GT/s
- PCIE Port 17-20
- SATA @ Port 17
- PCIE1.0 2.5GT/s
- PCIE Port 15
P.52
WIFI - JNGFF1
- USB2 Port 4
- GEN2
- USB3.1 Port 5
- USB2.0 Port 3
USB3.1 - JUSB 2
- USB3.1 GEN2
- USB3.1 Port3&4
P.42-43
Type C - JTYPEC1
- CPU eDP
P.38
eDP - JEDP1
DDI
Finger print
- USB2 Port 8
Tuch Screen
- USB2 Port 6
- PCH I2C2
P.66 P.38
HW Circuit DC/DC
Power Circuit DC/DC
P.82-111
P.78
Power On/Of f CKT.
P.63
RTC CKT. (JRTC1)
P.20
Sub Board
HS/B (JHS1)
TURBO/B (JTURBO1)
IO/B (JIO1/JIO2)
P.77
P.66
P.73
- MAX-Q
- GDDR6 4G
Extend IC
- I2C
- KC3810
P.59
- VGA Port C
P.40
HDMI - JHDMI1
P.39
mDP - JDP1
- VGA Port E
- SOP8
- Size : 1M
P.29
VBIOS ROM
- RTS5441E
USB3 Re-driver
USB3.1 - JUSB 3
USB3 Re-driver
- PS8713 - PS8713
- GEN2
- USB3.1 Port 2
- USB2.0 Port 2
IO_B
P.73
SSD - JSSD3 (PCIE/SATA)
EMR - JEMR1
- PCH I2C0
P.64
Touch Pad
- EC PS2
- PCH I2C1
P.63
Fan Control*2
page 77
- NPCT750
I2C
Title
Size Document Number R ev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
FH51M M/B LA-J871P
1.0
Block Diagrams
Custom
2 112Tuesday, February 11, 2020
2019/09/20 2020/09/20
Compal Electronics, Inc.
Title
Size Document Number R ev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
FH51M M/B LA-J871P
1.0
Block Diagrams
Custom
2 112Tuesday, February 11, 2020
2019/09/20 2020/09/20
Compal Electronics, Inc.
Title
Size Document Number R ev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
FH51M M/B LA-J871P
1.0
Block Diagrams
Custom
2 112Tuesday, February 11, 2020
2019/09/20 2020/09/20
Compal Electronics, Inc.
www.laptoprepairsecrets.com
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
Vcc
3.3V +/- 5%
100K +/- 1%
Ra
Board ID
Rb
Vmin
0
1
2
0
0.423 V 0.430 V 0.438 V
Vtyp Vmax
15K +/- 1%
0.000 V 0.300 V
12K +/- 1% 0.347 V 0.345 V 0.360 V
EC AD
0x00 - 0x13
0x14 - 0x1E
0x1F - 0x25
3
4
5
6
7
20K +/- 1%
27K +/- 1%
33K +/- 1%
43K +/- 1%
56K +/- 1%
0x26 - 0x300.541 V 0.550 V 0.559 V
0x31 - 0x3A0.691 V 0.702 V 0.713 V
0x3B - 0x450.807 V 0.819 V 0.831 V
0x46 - 0x540.978 V 0.992 V 1.006 V
0x55 - 0x641.169 V 1.185 V 1.200 V
EC Board ID Table for AD channel
8
9
10
11
12
13
14
15
16
17
18
19
75K +/- 1%
100K +/- 1%
130K +/- 1%
160K +/- 1%
200K +/- 1%
240K +/- 1%
270K +/- 1%
330K +/- 1%
430K +/- 1%
560K +/- 1%
750K +/- 1%
NC
1.398 V
1.634 V
1.849 V
2.015 V
2.185 V
2.316 V
2.395 V
2.521 V
2.667 V
2.791 V
2.905 V
3.000 V
1.414 V
1.650 V
1.865 V
2.031 V
2.200 V
2.329 V
2.408 V
2.533 V
2.677 V
2.800 V
2.912 V
3.000 V
1.430 V
1.667 V
1.881 V
2.046 V
2.215 V
2.343 V
2.421 V
2.544 V
2.687 V
2.808 V
2.919 V
0x65 - 0x76
0x77 - 0x87
0x88 - 0x96
0x97 - 0xA4
0xA5 - 0xAF
0xB0 - 0xB7
0xB8 - 0xBF
0xC0 - 0xC9
0xCA - 0xD4
0xD5 - 0xDD
0xDE - 0xF0
0xF1 - 0xFF
0x16
0x9E
Address(7 bit)
Device
Write Read
Address(8bit)
BUS
EC_SMB_CK1
(+3VLP)
PCH_SML1CLK
(+3VALW)
EC_SMB_CK2
(+3VS)
PCH_SMBCLK
(+3VS)
BQ24780 (Charger IC)
N18P-G0/N17P-G0-K1 (VGA)
BATTERY PACK
0x12
TM-P3393-003 (Touch Pad)I2C_1 (+3VS)
I2C_0 (+3VS)
Thermal Sensor (NCT7718W) 1001_100xb 1001_1001b 1001_1000b
EC_SMB_CK3
(+3VALW)
LED driver 0xC0
CONN@
Connector
Item (X43 / X76) BOM Structure
Unpop @
Item (X43 / X76) BOM Structure
BOM StructureDescript i on43 Level
PCH 0x90
Thermal Sensor (G781) 1001_101xb
KC3810
0xC0
1001_1011b 1001_1010b
XXXXXX (EMR)
DIMM1
DIMM2
UMA Only(Reserved)
UMA@
H62 CPU(Reserved) H62@
H82 CPU(POP) H82@
eDP-TS USB TS_USB@
eDP-TS I2C TS_I2C@
eDP-TS USB NONTS_I2C@
mDP
DP@
For Acer IOAC IOAC@
No Acer IOAC
Intel CNVi
FOR UART BT module
FOR UART debug
NIOAC@
CNVI@
UART_BT@
UART@
Extend GPIO
Finger Print
FinerPrint(with PBA)
KB LED driver
KC3810@
FP@
PBA@
LED14P@
EMR 1.8V WC18V@
EMR 3.3V WC33V@
Thermal sensor
TMS@
TPM pop TPM@
TPM non-pop NTPM@
EMI requirement EMI@
XEMI@
ESD@
FP ESD requirement FPESD@
EMI require reserve
ESD requirement
XESD@ESD require reserve
Item (X4E) BOM Structure
V
V
V
V
V
V
V
V
V
V
V
PCB PCB@
V
431AMBBOL02 FH51M PG61QS 4G
PCB@/H82@/SATANRD@/CMLi5@/CMLPCH@/VGA@/N18P@/VGAG61@/TS_USB@/NONTS_I2C@/DP@/IOAC@/CNVI@/FP@/PBA@/KBLED@/LED14P@/WC18V@/TMS/@TPM@
Item (X76) BOM Structure
OVRM-uPI
uPI_X76@
ON_X76@OVRM-ON
VRAM-SAMSUNG X76SAM@
VRAM-MICRON
X76MIC@
X76869BOL01 - MICRON
X76869BOL02 - SAMSUNG
X76869BOL03 - ON OVRM
X76869BOL04 - UPI OVRM
X4EAMBBOL01 PG6162 FOR EE
X4EP4MBOL01 PG6162 IO FOR EE
SSD3@SSD3 pop
V
Remove KBLED@
+1.8VS power rail for GPU(AON rails)
+1.8VSDGPU_AON
+0.6VS_VTT DDR +0.6VS power rail for DDR terminator .
+3VS
+5VALW
+3VALW System +3VALW always on power rail
+3VLP
+19VB to +3VLP power rail for suspend power
DDR4 +1.2V power rail+1.2V_VDDQ
+1.0VSDGPU
+1.0VS power rail for GPU
System +3V power rail
+5V Always power rail
+5VS System +5V power rail
+VCC_CORE
+19V_VIN
+19VB
Adapter power supply
AC or battery power rail for power circuit.
Core voltage for CPU
Power Plane
Description
+VCC_GT
Sliced graphics power rail
+12.6V_BATT Battery power supply
STATE
SIGNAL
S3 (Suspend to RAM)
S4 (Suspend to Disk)
S5 (Soft OFF)
ONONONONOFF
OFF
OFF
OFF
OFFLOW LOW LOW
LOWLOW
LOW HIGH
HIGH
HIGH
S0 (Full ON) ON ON ONHIGH HIGH HIGH
SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS
+1.05VALW +1.05V Always power rail
+1.8VS power rail for GPU GC6+1.8VSDGPU_MAIN
+3VALW_DSW +3VALW power for PCH DSW rails
+VCC_SA
System Agent power rail
+RTCVCC
+VCCIO
+1.05V_VCCST
RTC Battery Power
CPU IO +0.95VS power rail
Sustain voltage for processor in Standby modes
+NVVDD1
Core voltage for VGA (merge core & core_s)
+1.35VSDGPU +1.35VS power rail for GPU
+1.8VALW System +1.8VALW always on power rail
+1.05VS_VCCSTG +1.05VALW_PRIM Gated version of VCCST
N/A
ON
N/A
N/A
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
S0 S3
N/A
N/A
N/A
ON
ON
ON
ONON
ON
ON
ON
OFF
ON
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
ONS4ON
N/A
N/A
N/A
ON
ON
ON
ON
ON
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
ON
S5
ON
N/A
N/A
N/A
ON
ON
ON*
ON
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
ON
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
ON*
SD034120280
SD034150280
SD034200280
SD034270280
SD034330280
SD034430280
SD034560280
SD034750280
SD034100380
SD034130380
SD034160380
SD034200380
SD000001B80
SD00000G280
SD034330380
SD00000WM80
SD034560380
SD00000AL80
50 Rev0.2
50 Rev1.0+RGB
50 Rev0.2+RGB
50 Rev1.0
60 Rev0.1
60 Rev0.2
60 Rev1.0
60 Rev0.2+RGB
60 Rev1.0+RGB
50 Rev0.3
50 Rev0.3+RGB
60 Rev0.3
60 Rev0.3+RGB
50 Rev0.1
10
11
12
16
17
13
14
15
18
19
2
1
0
Board ID
7
6
5
4
3
PCB Revision
8
9
*PCB Version
*Key board type
CFL i5QS CPU CFLi5QS@
CFLi5@CFL i5 CPU
CFL QS PCH CFLPCHQS@
CML PCH CMLPCH@
CML i5 CPU
CML i7 CPU
CMLi5@
CMLi7@
CML i9 CPU
CML i5QS CPU CMLi5QS@
CMLi9QS@CML i9QS CPU
CML i7QS CPU CMLi7QS@
CML QS PCH
PVT
PVT W/RGB
PVT@
PVTRGB@
dGPU circuit VGA@
N17P GPU N17P@
N18P GPU N18P@
V
V
N18P-G61 VGAG61@
N18P-G62 MP2 VGAG62@
Title
Size Document Number R ev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
1.0
Notes List
Custom
3 112Tuesday, February 11, 2020
2019/09/20 2020/09/20
Compal Electronics, Inc.
FH51M M/B LA-J871P
Title
Size Document Number R ev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
1.0
Notes List
Custom
3 112Tuesday, February 11, 2020
2019/09/20 2020/09/20
Compal Electronics, Inc.
FH51M M/B LA-J871P
Title
Size Document Number R ev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
1.0
Notes List
Custom
3 112Tuesday, February 11, 2020
2019/09/20 2020/09/20
Compal Electronics, Inc.
FH51M M/B LA-J871P
www.laptoprepairsecrets.com
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DC_IN
PL101,2,3
PJP101
+19V_VIN
PUB1
+12.6V_BATT
+19VB
PL201,2
+12.6V_BATT+
AC CONN.
BATTERY
PJP201
IMVP8
CHARGER
+VCC_CORE
PLZ1,2,3,4
EN:DRVON
PRA3
EN:DRVON
+VCC_SA
PLA1
+19VB
+19VB
EN:3V_EN
PU301
+3VALW
PJ302
+3VLP
EN:SYSON
PUM1
+19VB
+1.2V_VDDQ
PJM2
EN:+1.8_PG
PU1101
+19VB
+1.05VALW
PJ1101
PU501
PJ502
+19VB
+5VALW
US12
+USB3_VCCC
+FP_VCC
UQ1
UL1
UM1
R19
RH99
RH101
UK1
+3VS
JPQ1
+3VALW_TPM
+3V_LAN
+3VS_WLAN
+3VALW_DSW
+3V_PTP
+3VALW_HDA
JPH1
RH94
UQ2
+1.05VALW_PRI M
UC4
+1.05VALW_PCH
+1.05V_VCCST
RH102
+1.05VS_VCCS TG
RH105
RH103
UV45
UO1
R20
+LCDVDD
UX1
RC24
+1.2V_VCCPLL_ OC
RF4
RF7
UY2
+HDMI_5V_OUT
EC,LID
CPU
CPU
CPU
SATA Re-driver
TPM
TPM
PANEL
PCH
LAN
WLAN CARD Conn.
PCH
PCH
TP Conn.
PCH
CPU
PCH
FAN1 Conn.
HDMI Conn.
+0.6VS_VTT
PJM3
PUV1
PUV2,3
+19VB
PUH1 PJH1
+19VB
+VCCIO
CPU
EN:SUSP#
PU2501 PJ2502
+2.5V
JDIMM2
DDR4 Conn.
JDIMM1
+3VS_TPM
U5
JNGFF1
UL2
JTP1
+USB_VCCA
USB3.0 Conn.
JTYPEC1
JHDMI1
JHDD1
+5VS_HDD
UA1
JBL1
JPA1
RO4
U4
+5VS_BL
+VDDA
HDD Conn.
KB BackLight Conn.
CODEC
FAN2 Conn.
JEDP1
U5
GPU
EN:DRVON
PLG1
+19VB
CPU
+VCC_GT
PUZ2,3,4,5
PRG5
RA2
RA4
CODEC
CODEC
+3VS_DVDDIO
+3VS_DVDD
CPU,Memory
+VCC_FAN1
+VCC_FAN2
RX7 JEDP1
+TS_PWR
Touch Screen
+1.35VSDGPU
+NVVDD1
GPU
GPU
+INVPWR_B+
+19VB →+19VB_CPU
LX1
PANEL
EN:SM_PG_CTR L
EN:1.35VSDGPU _EN
+3VALWP
+1.2VP
+0.6VSP
+1.05VALWP
+1.0VS_VCCIOP
+5VALWP
NVVDD_B+
PLV2,3
PUW1
PLW1
+19VB
JIO1
US11
UK2
+2.5VP
UM2
PU1002 PJ1003
+1.0VSDGPUP
+1.0VSDGPU
GPU
+FP_VCC
FP Conn.
UK2
RS127
+5VALW_MUX
IO/B Conn.
PU1801 PJ1801
+19VB
+1.8VALW
EN:SPOK_3V
+1.8VALWP
UQ2
+1.8VS
RA3
CODEC
+1.8VS_VDDA
UG27
EN:DGPU_PWR_E N
+1.8VSDGPU_AO N
+1.8VSDGPU_MA IN
GPU
RH100
+1.8VALW _PR IM
PCH
GPU_B+
+19VB_CPU
+19VB_CPU
+19VB_CPU
RQ5
RQ9
UV48
+FP_FUSE_GPU
GPU
US3
CC logic/U3 MUX
+USB_VCCB
USB3.0 Conn.
US13
UE5
+5V_LEDPWR
KB BackLight Conn.
JBL2
JPQ2UQ1
+5VS
FP Conn.
JFP1
Type-C Conn.
JIO1
JFP1
UM2
+3VS_SSD1
RM54
+3VS_SSD2
RM55
JSSD1
SSD Conn.
JSSD2
SSD Conn.
JUSB1
JUSB2
JFAN1
JFAN1
+3VSDGPU
+3VS
+3VS_WLAN
JNGFF1RM11
WLAN CARD Conn.
+5VALW
+1.05VALW_VCC AZPLL
+1.05VALW_VCC AMPHYPLL
+1.05VALW_XTA L
Title
Size Document Number R e v
Date: Sheet o f
Security Classifi cation
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
1.0
Power Map
Custom
4 112Tuesday, February 11, 2020
2019/09/20 2020/09/20
Compal Electronics, Inc.
FH51M M/B LA-J871P
Title
Size Document Number R e v
Date: Sheet o f
Security Classifi cation
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
1.0
Power Map
Custom
4 112Tuesday, February 11, 2020
2019/09/20 2020/09/20
Compal Electronics, Inc.
FH51M M/B LA-J871P
Title
Size Document Number R e v
Date: Sheet o f
Security Classifi cation
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
1.0
Power Map
Custom
4 112Tuesday, February 11, 2020
2019/09/20 2020/09/20
Compal Electronics, Inc.
FH51M M/B LA-J871P
www.laptoprepairsecrets.com
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
+3VS
+2.5VS
+1.8VS
+1.05VS_VCCST G
877.7us
8.378us
12.7ms
630.4us
+5VS
412us
25.34ms
EC_VCCST_PG
+VCC_SA
25.35ms
25.36ms
25.19ms
1.759ms
173.0ms
NA
12.42ms
150.3ms
13.01us
55.47us
618.5us
8.679ms
→
347.6us
0us
3.819ms
51.25us
87.75us
NA
26.91us
47.39us
61.95us
25.25ms
67.04ms
100.5us
906.0us
EC_ON
656.1us
424.9us
25.25ms
25.26ms
25.59ms
167.1ms
NA
1.757ms
12.18ms
150.6ms
152.8us
88.37us
367.6us
2.266ms
13us
68.53us
686.0us
11.65ms
446.2us
0us
0us 13.97ms
2.034ms
27.06us
48.00us
112.0us
NA
47.83us
62.37us
BIOS ver: V 0.02W1
EC: ver: V 002AT04
333.3ms
92.03ms
94.88ms
S3 S3 Resume
72.1us
8.502us
2.439ms
SYSON
+1.05V_VCCST
+1.05VALW
+1.2V_VDDQ
SM_PG_CTRL
+0.6VS_VTT
+VCC_GT
SYS_PWROK
330.8ms
29.19ms
→
← →
19.18ms
152.3ms 318.7us
+3VS
+2.5VS
+1.8VS
+1.05VS_VCCST G
+5VS
EC_VCCST_PG
+VCC_SA
EC_ON
SYSON
+1.05V_VCCST
+1.05VALW
+1.2V_VDDQ
SM_PG_CTRL
+0.6VS_VTT
+VCC_GT
SYS_PWROK
PLT_RST#
PCH_PWROK
SUSP#
VR_ON
PBTN_OUT#
EC_RSMRST#
PM_SLP_S4#
PM_SLP_S3#
+VCC_CORE
ON/OFFBTN#
+3VALW
+5VALW
+3VLP
151.8ms
293.7us
PLT_RST#
PCH_PWROK
SUSP#
VR_ON
PBTN_OUT#
EC_RSMRST#
19.22ms
PM_SLP_S4#
PM_SLP_S3#
Power On
AC modeDH5VF_EVT P ower Sequence
+VCC_CORE
Power Off
174.6ms
ON/OFFBTN#
→
→
+3VALW
+5VALW
20.1ms
Plug in
+3VLP
275.9us
692.9us
910.1us
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
Title
Size
Document Number R e v
Date: Sheet o f
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
FH51M M/B LA-J871P
1.0
Power Sequence
Custom
5 1 12Tuesday, February 11, 2020
2019/09/20 2020/09/20
Compal Electronics, Inc.
Title
Size
Document Number R e v
Date: Sheet o f
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
FH51M M/B LA-J871P
1.0
Power Sequence
Custom
5 1 12Tuesday, February 11, 2020
2019/09/20 2020/09/20
Compal Electronics, Inc.
Title
Size
Document Number R e v
Date: Sheet o f
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
FH51M M/B LA-J871P
1.0
Power Sequence
Custom
5 1 12Tuesday, February 11, 2020
2019/09/20 2020/09/20
Compal Electronics, Inc.
www.laptoprepairsecrets.com
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
eDP
Trace Width/Space: 15 mil/ 20 mil
Max Trace Length: 600 mil
20191024
- SDI 20 ohm close to CPU
- BCLK/SDO 30 ohm close to PCH
Coffee Lake-H
- Re-fresh R0 stepping
Comet Lake-H
EDP_TXN0
EDP_TXP0
EDP_TXN1
EDP_AUXN
EDP_AUXP
DP_RCOMP
CPU_DISPA_BC LK_R
CPU_DISPA_SD I
CPU_DISPA_SD O_R
CPU_DISPA_SD I_R
EDP_TXP1
EDP_TXN2
EDP_TXP2
EDP_TXN3
EDP_TXP3
EDP_TXP0 <38>
EDP_TXN0 <3 8>
EDP_TXP1 <38>
EDP_TXN1 <3 8>
EDP_AUXP <3 8>
EDP_AUXN <3 8>
CPU_DISPA_BC LK_R <18>
CPU_DISPA_SD O_R <18>
CPU_DISPA_S DI_R <1 8>
EDP_TXN2 <3 8>
EDP_TXP2 <38>
EDP_TXN3 <3 8>
EDP_TXP3 <38>
+VCCIO
Title
Size Document Number R e v
Date: Sheet o f
Security Classification
Compal Secret Data
THIS SHEET OF ENGINE ERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, IN C. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFO RMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTODY OF THE COMP ETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHEET NOR THE INFORM ATION IT CONTAINS
MAY BE USED BY OR DIS CLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELEC TRONICS, INC.
Issued Date
Deciphered Date
FH51M M/B LA-J871P
1.0
CFL-H(1/8)DDI/eDP
Custom
6 112Tuesday, Feb ruary 11, 2020
2019/09/20 2020/09/20
Compal Electronics, Inc.
Title
Size Document Number R e v
Date: Sheet o f
Security Classification
Compal Secret Data
THIS SHEET OF ENGINE ERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, IN C. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFO RMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTODY OF THE COMP ETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHEET NOR THE INFORM ATION IT CONTAINS
MAY BE USED BY OR DIS CLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELEC TRONICS, INC.
Issued Date
Deciphered Date
FH51M M/B LA-J871P
1.0
CFL-H(1/8)DDI/eDP
Custom
6 112Tuesday, Feb ruary 11, 2020
2019/09/20 2020/09/20
Compal Electronics, Inc.
Title
Size Document Number R e v
Date: Sheet o f
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEE RING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET IN FORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AU THORIZED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHEET NOR THE INFORMA TION IT CONTAINS
MAY BE USED BY OR DISC LOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELEC TRONICS, INC.
Issued Date
Deciphered Date
FH51M M/B LA-J871P
1.0
CFL-H(1/8)DDI/eDP
Custom
6 112Tuesday, Feb ruary 11, 2020
2019/09/20 2020/09/20
Compal Electronics, Inc.
UH1
S IC FH82HM470 SRJAU A0 FCBGA PCH-H
CMLPCH@
SA0000DDP80
RC1 24.9_040 2_1%
1 2
UC1
S IC CL8070104399007 QTJ0 R0 2.8G S
CMLi9QS@
SA0000D3G10
RC2 20_0402_5 %
12
UC1
S IC CL8070104398806 QTJ1 R0 2.1G 1440 S
CMLi5QS@
SA0000D3I10
UC1
S IC CL8068404121905 QRR5 U0 2.4G FCBGA
CFLi5QS@
SA0000COG00
UC1
S IC CL8070104398908 QTJ2 R0 2.4G 1440 S
CMLi7QS@
SA0000D3N10
UH1
S IC FHHM370 QNYF B0 BGA 874P PCH-
CFLPCHQS@
SA0000BPF10
4 of 13
CFL-H
UC1D
CFL-H_BGA1 440
@
DDI1_TXP_0
K36
DDI1_TXN_0
K37
DDI1_TXP_1
J35
DDI1_TXN_1
J34
DDI1_TXP_2
H37
DDI1_TXN_2
H36
DDI1_TXP_3
J37
DDI1_TXN_3
J38
DDI1_AUXP
D27
DDI1_AUXN
E27
DDI2_TXP_0
H34
DDI2_TXN_0
H33
DDI2_TXP_1
F37
DDI2_TXN_1
G38
DDI2_TXP_2
F34
DDI2_TXN_2
F35
DDI2_TXP_3
E37
DDI2_TXN_3
E36
DDI2_AUXP
F26
DDI2_AUXN
E26
DDI3_TXP_0
C34
DDI3_TXN_0
D34
DDI3_TXP_1
B36
DDI3_TXN_1
B34
DDI3_TXP_2
F33
DDI3_TXN_2
E33
DDI3_TXP_3
C33
DDI3_TXN_3
B33
DDI3_AUXP
A27
DDI3_AUXN
B27
EDP_TXP_0
D29
EDP_TXN_0
E29
EDP_TXP_1
F28
EDP_TXN_1
E28
EDP_TXP_2
A29
EDP_TXN_2
B29
EDP_TXP_3
C28
EDP_TXN_3
B28
EDP_AUXP
C26
EDP_AUXN
B26
EDP_DISP_UTIL
A33
PROC_AUDIO_CLK
G27
DISP_RCOMP
D37
PROC_AUDIO_SDI
G25
PROC_AUDIO_SDO
G29
UC5
S IC CL8068404121905 SRF6X U0 2.4G
CFLi5@
SA0000COG40
UC6
S IC CL8070104399510 SRH84 R1 2.5G
CMLi5@
SA0000DCP40
UC8
S IC CL8070104399510 SRH84 R1 2.5G
CMLi7@
SA0000DCP40
www.laptoprepairsecrets.com
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
For ECC DIMM
Interleaved Memory
CHANNEL-A
For ECC DIMM
DDR_A_D48
DDR_A_D62
DDR_A_D58
DDR_A_D63
DDR_A_D30
DDR_A_D18
DDR_A_D22
DDR_A_D19
DDR_A_D42
DDR_A_D40
DDR_A_D34
DDR_A_D41
DDR_A_D44
DDR_A_D16
DDR_A_D17
DDR_A_D20
DDR_A_D21
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D43
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D7
DDR_A_D15
DDR_A_D11
DDR_A_D6
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_CLK0
DDR_A_CLK#0
DDR_A_CLK#1
DDR_A_CLK1
DDR_A_CKE1
DDR_A_CKE0
DDR_A_CS#1
DDR_A_CS#0
DDR_A_ODT0
DDR_A_ODT1
DDR_A_BG0
DDR_A_BA1
DDR_A_BA0
DDR_A_MA16_ RAS#
DDR_A_MA14_ WE#
DDR_A_MA15_ CAS#
DDR_A_MA12
DDR_A_MA11
DDR_A_ACT#
DDR_A_BG1
DDR_A_MA5
DDR_A_MA9
DDR_A_MA6
DDR_A_MA8
DDR_A_MA7
DDR_A_MA13
DDR_A_MA2
DDR_A_MA10
DDR_A_MA1
DDR_A_MA0
DDR_A_MA3
DDR_A_MA4
DDR_A_PAR
DDR_A_ALERT #
DDR_A_DQS# 4
DDR_A_DQS# 6
DDR_A_DQS# 5
DDR_A_DQS# 7
DDR_A_DQS# 2
DDR_A_DQS# 3
DDR_A_DQS# 0
DDR_A_DQS# 1
DDR_A_DQS5
DDR_A_DQS0
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS1
DDR_A_DQS4
DDR_A_DQS6
DDR_A_DQS7
DDR_A_D[0..63 ]<23>
DDR_A_CLK# 0 <23>
DDR_A_CLK0 <23 >
DDR_A_CLK# 1 <23>
DDR_A_CLK1 <23 >
DDR_A_CKE0 < 23>
DDR_A_CKE1 < 23>
DDR_A_ODT0 <23>
DDR_A_CS#1 <23 >
DDR_A_CS#0 <23 >
DDR_A_ODT1 <23>
DDR_A_BG0 <23>
DDR_A_BA0 <23>
DDR_A_BA1 <23>
DDR_A_MA1 6_RAS# <23 >
DDR_A_MA1 4_WE# <23>
DDR_A_MA1 5_CAS# <23 >
DDR_A_MA5 <23>
DDR_A_MA9 <23>
DDR_A_MA6 <23>
DDR_A_MA8 <23>
DDR_A_MA7 <23>
DDR_A_MA1 2 < 23>
DDR_A_MA1 1 < 23>
DDR_A_ACT# <23>
DDR_A_BG1 <23>
DDR_A_MA2 <23>
DDR_A_MA1 0 < 23>
DDR_A_MA1 <23>
DDR_A_MA0 <23>
DDR_A_MA1 3 < 23>
DDR_A_MA3 <23>
DDR_A_MA4 <23>
DDR_A_PAR <23>
DDR_A_ALE RT# <23>
DDR_A_DQS# 4 <23>
DDR_A_DQS# 6 <23>
DDR_A_DQS# 5 <23>
DDR_A_DQS# 7 <23>
DDR_A_DQS# 2 <23>
DDR_A_DQS# 3 <23>
DDR_A_DQS# 0 <23>
DDR_A_DQS# 1 <23>
DDR_A_DQS1 < 23>
DDR_A_DQS3 < 23>
DDR_A_DQS2 < 23>
DDR_A_DQS0 < 23>
DDR_A_DQS5 < 23>
DDR_A_DQS4 < 23>
DDR_A_DQS7 < 23>
DDR_A_DQS6 < 23>
Title
Size Document Number R e v
Date: Sheet o f
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEE RING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET IN FORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AU THORIZED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHEET NOR THE INFORMA TION IT CONTAINS
MAY BE USED BY OR DISC LOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELEC TRONICS, INC.
Issued Date
Deciphered Date
FH51M M/B LA-J871P
1.0
CFL-H(2/8)DIMMA
Custom
7 112Tuesday, Feb ruary 11, 2020
2019/09/20 2020/09/20
Compal Electronics, Inc.
Title
Size Document Number R e v
Date: Sheet o f
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEE RING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET IN FORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AU THORIZED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHEET NOR THE INFORMA TION IT CONTAINS
MAY BE USED BY OR DISC LOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELEC TRONICS, INC.
Issued Date
Deciphered Date
FH51M M/B LA-J871P
1.0
CFL-H(2/8)DIMMA
Custom
7 112Tuesday, Feb ruary 11, 2020
2019/09/20 2020/09/20
Compal Electronics, Inc.
Title
Size Document Number R e v
Date: Sheet o f
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEE RING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET IN FORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AU THORIZED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHEET NOR THE INFORMA TION IT CONTAINS
MAY BE USED BY OR DISC LOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELEC TRONICS, INC.
Issued Date
Deciphered Date
FH51M M/B LA-J871P
1.0
CFL-H(2/8)DIMMA
Custom
7 112Tuesday, Feb ruary 11, 2020
2019/09/20 2020/09/20
Compal Electronics, Inc.
1 OF 13
DDR CHANNEL A
CFL-H
DDR4(IL)/LP3-DDR4(NIL) LP3/DDR4
LP3/DDR4
DDR4(IL)/LP3-DDR4(NIL)
UC1A
CFL-H_BGA1 440
@
DDR0_DQSN_7/DDR1_DQSN_5
L3
DDR0_DQSN_0/DDR0_DQSN_0
BR5
DDR0_DQ_9/DDR0_DQ_9
BL5
DDR0_DQ_13/DDR0_DQ_13
BK5
DDR0_DQ_17/DDR0_DQ_33
BG5
NC/DDR0_ECC_2
AY4
NC/DDR0_ALERT#
AU5
DDR0_CKN_0/DDR0_CKN_0
AG2
DDR0_CS#_0/DDR0_CS#_0
AD5
DDR0_CAB_1/DDR0_MA_15
AD1
DDR0_DQ_40/DDR1_DQ_8
V5
DDR0_DQ_61/DDR1_DQ_45
M2
DDR0_DQ_5/DDR0_DQ_5
BP6
DDR0_DQSP_2/DDR0_DQSP_4
BF3
NC/DDR0_ECC_3
AY5
DDR0_CKE_3/DDR0_CKE_3
AT5
DDR0_CKE_0/DDR0_CKE_0
AT1
NC/DDR0_CKN_2
AK3
DDR0_ODT_0/DDR0_ODT_0
AD3
NC/DDR0_CS#_2
AD2
DDR0_DQ_38/DDR1_DQ_6
AA2
DDR0_DQSN_5/DDR1_DQSN_1
U3
DDR0_DQ_52/DDR1_DQ_36
R5
DDR0_DQSP_7/DDR1_DQSP_5
M3
DDR0_DQ_1/DDR0_DQ_1
BT6
DDR0_DQSP_0/DDR0_DQSP_0
BP5
DDR0_DQ_31/DDR0_DQ_47
BC2
NC/DDR0_ECC_4
BA5
NC/DDR0_CKN_3
AL1
NC/DDR0_CS#_3
AE5
DDR0_DQ_34/DDR1_DQ_2
AA4
DDR0_DQ_55/DDR1_DQ_39
P1
DDR0_DQ_57/DDR1_DQ_41
M1
NC/DDR0_ECC_5
BA4
DDR0_DQSN_8/DDR0_DQSN_8
BA3
DDR0_CAA_6/DDR0_MA_12
AU4
DDR0_CAA_8/DDR0_ACT#
AU3
DDR0_CAA_4/DDR0_MA_7
AN1
NC/DDR0_CKP_2
AL3
DDR0_CAB_6/DDR0_BA_1
AH1
DDR0_CKP_0/DDR0_CKP_0
AG1
DDR0_DQSP_5/DDR1_DQSP_1
V3
DDR0_DQ_44/DDR1_DQ_12
V1
DDR0_DQ_48/DDR1_DQ_32
R2
DDR0_DQ_22/DDR0_DQ_38
BF1
DDR0_DQ_24/DDR0_DQ_40
BD2
NC/DDR0_ECC_6
AY1
DDR0_CAA_9/DDR0_BG_1
AU2
NC/DDR0_CKP_3
AL2
DDR0_CAB_2/DDR0_MA_14
AG4
DDR0_DQ_47/DDR1_DQ_15
U4
DDR0_DQ_11/DDR0_DQ_11
BM1
DDR0_DQ_8/DDR0_DQ_8
BL4
DDR0_DQ_14/DDR0_DQ_14
BK1
DDR0_DQSN_3/DDR0_DQSN_5
BD3
DDR0_DQ_27/DDR0_DQ_43
BC5
DDR0_DQSP_8/DDR0_DQSP_8
AY3
NC/DDR0_ECC_7
AY2
DDR0_CAA_1/DDR0_MA_9
AT4
DDR0_CS#_1/DDR0_CS#_1
AE2
DDR0_DQ_37/DDR1_DQ_5
AB4
DDR0_DQ_4/DDR0_DQ_4
BN5
DDR0_DQ_18/DDR0_DQ_34
BF4
DDR0_CAA_0/DDR0_MA_5
AP1
DDR0_CKN_1/DDR0_CKN_1
AK1
DDR0_DQ_62/DDR1_DQ_46
L5
DDR0_DQ_0/DDR0_DQ_0
BR6
DDR0_DQSN_1/DDR0_DQSN_1
BL3
DDR0_DQSP_3/DDR0_DQSP_5
BC3
DDR0_CKE_1/DDR0_CKE_1
AT2
NC/DDR0_MA_3
AP5
DDR0_CAA_7/DDR0_MA_11
AN2
DDR0_CAB_7/DDR0_MA_10
AH2
DDR0_DQ_33/DDR1_DQ_1
AB2
DDR0_DQ_50/DDR1_DQ_34
R4
DDR0_DQ_53/DDR1_DQ_37
P2
DDR0_CAA_5/DDR0_BG_0
AU1
NC/DDR0_MA_4
AP2
DDR0_CAB_9/DDR0_MA_0
AH3
NC/DDR0_ODT_1
AE4
DDR0_DQ_58/DDR1_DQ_42
L4
DDR0_DQ_7/DDR0_DQ_7
BN3
DDR0_DQSP_1/DDR0_DQSP_1
BK3
DDR0_DQ_20/DDR0_DQ_36
BG2
DDR0_DQ_23/DDR0_DQ_39
BF2
DDR0_CKP_1/DDR0_CKP_1
AK2
NC/DDR0_ODT_2
AE1
DDR0_DQ_45/DDR1_DQ_13
V4
DDR0_DQ_42/DDR1_DQ_10
U1
DDR0_DQ_49/DDR1_DQ_33
P5
DDR0_DQ_3/DDR0_DQ_3
BR3
DDR0_DQ_28/DDR0_DQ_44
BD5
DDR0_DQ_25/DDR0_DQ_41
BD1
DDR0_CAA_3/DDR0_MA_8
AN3
DDR0_CAB_3/DDR0_MA_16
AH4
DDR0_CAB_0/DDR0_MA_13
AE3
NC/DDR0_ODT_3
AD4
DDR0_DQ_36/DDR1_DQ_4
AB5
DDR0_DQSN_6/DDR1_DQSN_4
P3
DDR0_DQ_12/DDR0_DQ_12
BK4
DDR0_DQ_15/DDR0_DQ_15
BK2
DDR0_DQ_16/DDR0_DQ_32
BG4
DDR0_DQ_19/DDR0_DQ_35
BF5
DDR0_DQ_32/DDR1_DQ_0
AB1
DDR0_DQSP_6/DDR1_DQSP_4
R3
DDR0_DQ_60/DDR1_DQ_44
M5
DDR0_CKE_2/DDR0_CKE_2
AT3
DDR0_DQSN_4/DDR1_DQSN_0
AA3
DDR0_DQ_41/DDR1_DQ_9
V2
DDR0_DQ_51/DDR1_DQ_35
P4
DDR0_DQ_63/DDR1_DQ_47
L1
DDR0_CAA_2/DDR0_MA_6
AP3
DDR0_CAB_4/DDR0_BA_0
AH5
DDR0_DQ_39/DDR1_DQ_7
AA1
DDR0_DQ_54/DDR1_DQ_38
R1
DDR0_DQ_6/DDR0_DQ_6
BP2
DDR0_DQ_30/DDR0_DQ_46
BC1
DDR0_DQSP_4/DDR1_DQSP_0
AB3
DDR0_DQ_35/DDR1_DQ_3
AA5
DDR0_DQ_43/DDR1_DQ_11
U2
DDR0_DQ_56/DDR1_DQ_40
M4
DDR0_DQ_59/DDR1_DQ_43
L2
DDR0_DQ_2/DDR0_DQ_2
BP3
DDR0_DQ_21/DDR0_DQ_37
BG1
NC/DDR0_ECC_0
BA2
DDR0_CAB_8/DDR0_MA_1
AP4
DDR0_CAB_5/DDR0_MA_2
AN4
DDR0_DQ_46/DDR1_DQ_14
U5
DDR0_DQ_10/DDR0_DQ_10
BL2
DDR0_DQSN_2/DDR0_DQSN_4
BG3
DDR0_DQ_29/DDR0_DQ_45
BD4
DDR0_DQ_26/DDR0_DQ_42
BC4
NC/DDR0_ECC_1
BA1
NC/DDR0_PAR
AG3
www.laptoprepairsecrets.com
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
CHANNEL-B Interleaved Memory
For ECC DIMMFor ECC DIMM
Trace Width/Space: 15 mil/ 25 mil
Max Trace Length: 500 mil
DDR_B_MA12
DDR_B_MA9
DDR_B_MA5
DDR_B_BG 1
DDR_B_ACT #
DDR_B_MA11
DDR_B_MA13
DDR_B_MA7
DDR_B_MA8
DDR_B_MA6
DDR_B_MA1
DDR_B_MA10
DDR_B_MA2
DDR_B_MA4
DDR_B_MA3
DDR_B_MA0
DDR_B_PAR
DDR_B_ALER T#
DDR_B_DQS#0
DDR_B_DQS0
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS#5
DDR_B_DQS5
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_DQS#7
DDR_B_DQS7
SM_RCOMP2
SM_RCOMP1
SM_RCOMP0
+0.6V_B_V REFDQ
+0.6V_VREF CA
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D1 7
DDR_B_D1 8
DDR_B_D1 9
DDR_B_D2 0
DDR_B_D2 1
DDR_B_D2 2
DDR_B_D2 3
DDR_B_D2 4
DDR_B_D2 5
DDR_B_D2 6
DDR_B_D2 7
DDR_B_D2 8
DDR_B_D2 9
DDR_B_D3 0
DDR_B_D3 1
DDR_B_D3 2
DDR_B_D3 3
DDR_B_D3 4
DDR_B_D3 5
DDR_B_D3 6
DDR_B_D3 7
DDR_B_D3 8
DDR_B_D3 9
DDR_B_D4 0
DDR_B_D4 1
DDR_B_D4 2
DDR_B_D4 3
DDR_B_D4 4
DDR_B_D4 5
DDR_B_D4 6
DDR_B_D4 7
DDR_B_D4 8
DDR_B_D4 9
DDR_B_D5 0
DDR_B_D5 1
DDR_B_D5 2
DDR_B_D5 3
DDR_B_D5 4
DDR_B_D5 5
DDR_B_D5 6
DDR_B_D5 7
DDR_B_D5 8
DDR_B_D5 9
DDR_B_D6 0
DDR_B_D6 1
DDR_B_D6 2
DDR_B_D6 3
DDR_B_CL K0
DDR_B_CL K#0
DDR_B_CL K1
DDR_B_CL K#1
DDR_B_CKE 0
DDR_B_CKE 1
DDR_B_CS# 0
DDR_B_CS# 1
DDR_B_ODT 0
DDR_B_ODT 1
DDR_B_MA1 6_RAS#
DDR_B_MA1 4_WE#
DDR_B_MA1 5_CAS#
DDR_B_BG0
DDR_B_BA1
DDR_B_BA0
DDR_B_MA9 <24>
DDR_B_MA5 <24>
DDR_B_MA1 2 <24>
DDR_B_MA7 <24>
DDR_B_MA8 <24>
DDR_B_MA6 <24>
DDR_B_BG1 <24>
DDR_B_ACT# <24>
DDR_B_MA1 1 <24>
DDR_B_MA0 <24>
DDR_B_MA1 <24>
DDR_B_MA1 0 <24>
DDR_B_MA2 <24>
DDR_B_MA4 <24>
DDR_B_MA3 <24>
DDR_B_MA1 3 <24>
DDR_B_PAR <24>
DDR_B_ALER T# <24>
DDR_B_DQS #0 <24 >
DDR_B_DQS 0 <24>
DDR_B_DQS #1 <24 >
DDR_B_DQS 1 <24>
DDR_B_DQS #2 <24 >
DDR_B_DQS 2 <24>
DDR_B_DQS #3 <24 >
DDR_B_DQS 3 <24>
DDR_B_DQS #4 <24 >
DDR_B_DQS 4 <24>
DDR_B_DQS #5 <24 >
DDR_B_DQS 5 <24>
DDR_B_DQS #6 <24 >
DDR_B_DQS 6 <24>
DDR_B_DQS #7 <24 >
DDR_B_DQS 7 <24>
DDR_B_D[0..63 ]<24>
DDR_B_CK E0 <24>
DDR_B_CK E1 <24>
DDR_B_CLK #0 <24>
DDR_B_CLK 1 <24>
DDR_B_CLK 0 <24>
DDR_B_CLK #1 <24>
DDR_B_CS #0 <24>
DDR_B_CS #1 <24>
DDR_B_OD T0 <24>
DDR_B_OD T1 <24>
DDR_B_MA1 6_RAS# <24 >
DDR_B_MA1 4_WE# <24>
DDR_B_MA1 5_CAS# <24 >
DDR_B_BG0 <24>
DDR_B_BA0 <24>
DDR_B_BA1 <24>
+0.6V_VREF CA
+0.6V_B_V REFDQ
Title
Size Document Number R e v
Date: Sheet o f
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEE RING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET IN FORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AU THORIZED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHEET NOR THE INFORMA TION IT CONTAINS
MAY BE USED BY OR DISC LOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELEC TRONICS, INC.
Issued Date
Deciphered Date
FH51M M/B LA-J871P
1.0
CFL-H(3/8)DIMMB
Custom
8 112Tuesday, Feb ruary 11, 2020
2019/09/20 2020/09/20
Compal Electronics, Inc.
Title
Size Document Number R e v
Date: Sheet o f
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEE RING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET IN FORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AU THORIZED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHEET NOR THE INFORMA TION IT CONTAINS
MAY BE USED BY OR DISC LOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELEC TRONICS, INC.
Issued Date
Deciphered Date
FH51M M/B LA-J871P
1.0
CFL-H(3/8)DIMMB
Custom
8 112Tuesday, Feb ruary 11, 2020
2019/09/20 2020/09/20
Compal Electronics, Inc.
Title
Size Document Number R e v
Date: Sheet o f
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEE RING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET IN FORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AU THORIZED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHEET NOR THE INFORMA TION IT CONTAINS
MAY BE USED BY OR DISC LOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELEC TRONICS, INC.
Issued Date
Deciphered Date
FH51M M/B LA-J871P
1.0
CFL-H(3/8)DIMMB
Custom
8 112Tuesday, Feb ruary 11, 2020
2019/09/20 2020/09/20
Compal Electronics, Inc.
2 OF 13
DDR CHANNEL B
CFL-H
DDR4(IL)/LP3-DDR4(NIL)
DDR4(IL)/LP3-DDR4(NIL)
LP3/DDR4
LP3/DDR4
DDR4(IL)/LP3-DDR4(NIL)
UC1B
CFL-H_BGA14 40
@
DDR_VREF_CA
BN13
DDR1_DQSP_5/DDR1_DQSP_3
V9
DDR1_DQ_55/DDR1_DQ_55
P8
DDR1_DQ_58/DDR1_DQ_58
L7
DDR1_DQ_0/DDR0_DQ_16
BT11
NC/DDR1_ECC_1
AY11
DDR1_CAA_0/DDR1_MA_5
AM6
NC/DDR1_PAR
AJ7
DDR1_DQ_45/DDR1_DQ_29
W10
DDR1_DQ_42/DDR1_DQ_26
V10
DDR1_DQ_49/DDR1_DQ_49
P11
DDR1_DQ_3/DDR0_DQ_19
BR8
DDR1_DQ_5/DDR0_DQ_21
BN11
DDR1_DQ_22/DDR0_DQ_54
BG7
DDR1_DQ_25/DDR0_DQ_57
BC11
NC/DDR1_ECC_2
AY8
DDR1_CAA_5/DDR1_BG_0
AR9
DDR1_DQ_47/DDR1_DQ_31
V8
DDR1_DQ_8/DDR0_DQ_24
BL12
DDR1_DQ_12/DDR0_DQ_28
BJ11
DDR1_DQ_16/DDR0_DQ_48
BG11
DDR1_DQSN_3/DDR0_DQSN_7
BC9
NC/DDR1_ECC_3
AW8
NC/DDR1_CKN_2
AM10
DDR1_CAB_9/DDR1_MA_0
AJ9
NC/DDR1_CS#_2
AF10
DDR1_DQ_33/DDR1_DQ_17
AA10
DDR1_VREF_DQ
BR13
DDR1_DQSN_1/DDR0_DQSN_3
BL9
DDR1_DQ_14/DDR0_DQ_30
BL7
DDR1_DQ_18/DDR0_DQ_50
BG8
DDR1_DQSP_3/DDR0_DQSP_7
BB9
DDR1_DQSN_8/DDR1_DQSN_8
AY9
NC/DDR1_ECC_4
AY10
DDR1_CAA_3/DDR1_MA_8
AN8
NC/DDR1_CKN_3
AJ11
DDR1_CAB_1/DDR1_MA_15
AF8
DDR1_CS#_0/DDR1_CS#_0
AF11
NC/DDR1_CS#_3
AE10
DDR1_DQ_38/DDR1_DQ_22
AC8
DDR1_DQ_62/DDR1_DQ_62
M7
NC/DDR1_ECC_5
AW10
DDR1_CKN_0/DDR1_CKN_0
AN9
NC/DDR1_CKP_2
AM11
DDR1_DQ_50/DDR1_DQ_50
P7
DDR1_DQ_53/DDR1_DQ_53
P10
DDR1_DQSP_1/DDR0_DQSP_3
BJ9
NC/DDR1_ECC_6
AY7
DDR1_DQSP_8/DDR1_DQSP_8
AW9
DDR1_CKE_0/DDR1_CKE_0
AT8
DDR1_CKE_3/DDR1_CKE_3
AT11
NC/DDR1_CKP_3
AJ10
DDR1_ODT_0/DDR1_ODT_0
AF7
DDR1_DQ_40/DDR1_DQ_24
W8
DDR1_DQ_43/DDR1_DQ_27
V11
DDR1_DQ_59/DDR1_DQ_59
M8
DDR1_DQ_56/DDR1_DQ_56
L11
DDR1_DQ_1/DDR0_DQ_17
BR11
DDR1_DQ_23/DDR0_DQ_55
BF7
DDR1_DQ_20/DDR0_DQ_52
BF11
NC/DDR1_ECC_7
AW7
NC/DDR1_ALERT#
AR8
NC/DDR1_MA_3
AL5
DDR1_CAB_4/DDR1_BA_0
AH8
DDR1_DQSN_6/DDR1_DQSN_6
R9
DDR1_DQ_6/DDR0_DQ_22
BP8
DDR0_VREF_DQ
BP13
DDR1_DQ_10/DDR0_DQ_26
BL8
DDR1_DQ_9/DDR0_DQ_25
BL11
DDR1_DQ_28/DDR0_DQ_60
BC10
DDR1_DQ_26/DDR0_DQ_58
BB8
DDR1_CAA_6/DDR1_MA_12
AR10
DDR1_CAA_2/DDR1_MA_6
AN7
DDR1_CKP_0/DDR1_CKP_0
AM9
NC/DDR1_MA_4
AL6
DDR1_CAB_2/DDR1_MA_14
AH11
DDR1_DQ_15/DDR0_DQ_31
BJ7
DDR1_DQ_13/DDR0_DQ_29
BJ10
DDR1_DQ_17/DDR0_DQ_49
BG10
DDR1_CAB_8/DDR1_MA_1
AK6
DDR1_DQSN_4/DDR1_DQSN_2
AC9
DDR1_DQ_34/DDR1_DQ_18
AC11
DDR1_DQ_36/DDR1_DQ_20
AA7
DDR1_DQSP_6/DDR1_DQSP_6
P9
DDR1_DQ_60/DDR1_DQ_60
L10
DDR1_DQ_19/DDR0_DQ_51
BF8
DDR1_CKN_1/DDR1_CKN_1
AM8
DDR1_CAB_5/DDR1_MA_2
AK5
NC/DDR1_ODT_1
AE8
DDR1_CS#_1/DDR1_CS#_1
AE7
DDR1_DQ_39/DDR1_DQ_23
AC7
DDR1_DQ_63/DDR1_DQ_63
L8
DDR1_CKE_1/DDR1_CKE_1
AT10
DDR1_CAB_7/DDR1_MA_10
AH7
NC/DDR1_ODT_2
AE9
DDR1_DQSP_4/DDR1_DQSP_2
AA9
DDR1_DQ_51/DDR1_DQ_51
R8
DDR1_DQ_54/DDR1_DQ_54
R7
DDR1_DQ_57/DDR1_DQ_57
M11
DDR_RCOMP_0
G1
DDR1_DQ_30/DDR0_DQ_62
BC7
DDR1_CAA_7/DDR1_MA_11
AN11
NC/DDR1_ODT_3
AE11
DDR1_DQ_41/DDR1_DQ_25
W7
DDR1_DQ_44/DDR1_DQ_28
W11
DDR_RCOMP_1
H1
DDR1_DQ_2/DDR0_DQ_18
BT9
DDR1_DQ_4/DDR0_DQ_20
BP11
DDR1_DQSN_2/DDR0_DQSN_6
BG9
DDR1_DQ_21/DDR0_DQ_53
BF10
DDR1_DQ_24/DDR0_DQ_56
BB11
DDR1_DQ_46/DDR1_DQ_30
V7
DDR1_DQ_48/DDR1_DQ_48
R11
DDR_RCOMP_2
J2
DDR1_DQ_7/DDR0_DQ_23
BN8
DDR1_DQ_11/DDR0_DQ_27
BJ8
DDR1_DQ_27/DDR0_DQ_59
BC8
DDR1_DQ_29/DDR0_DQ_61
BB10
DDR1_CKP_1/DDR1_CKP_1
AM7
DDR1_CAB_6/DDR1_BA_1
AH9
DDR1_DQ_35/DDR1_DQ_19
AC10
DDR1_DQ_32/DDR1_DQ_16
AA11
DDR1_DQSN_7/DDR1_DQSN_7
M9
DDR1_DQSN_0/DDR0_DQSN_2
BN9
DDR1_DQSP_2/DDR0_DQSP_6
BF9
DDR1_CAA_8/DDR1_ACT#
AT9
DDR1_CAA_9/DDR1_BG_1
AR7
DDR1_CAA_4/DDR1_MA_7
AN10
DDR1_CAB_3/DDR1_MA_16
AH10
DDR1_CAB_0/DDR1_MA_13
AF9
DDR1_DQ_37/DDR1_DQ_21
AA8
DDR1_DQSN_5/DDR1_DQSN_3
W9
DDR1_DQ_61/DDR1_DQ_61
M10
DDR1_DQSP_7/DDR1_DQSP_7
L9
DDR1_DQSP_0/DDR0_DQSP_2
BP9
DDR1_CAA_1/DDR1_MA_9
AR11
DDR1_DQ_52/DDR1_DQ_52
R10
DDR1_DQ_31/DDR0_DQ_63
BB7
NC/DDR1_ECC_0
AW11
DDR1_CKE_2/DDR1_CKE_2
AT7
RC4 75_0402_ 1%
1 2
RC3 121_0402 _1%
1 2
RC5 100_0402 _1%
1 2
www.laptoprepairsecrets.com
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
Trace Width/Space: 15 mil/ 15 mil
Max Trace Length: 600 mil
To DGPU
PEG Lane Reversed
To DGPU
PEG Lane Reversed
To PCH
To PCH
PEG&DMI
DMI_CRX_PT X_P0
DMI_CRX_PT X_N0
DMI_CRX_PT X_N1
DMI_CRX_PT X_P1
DMI_CRX_PT X_P2
DMI_CRX_PT X_N2
DMI_CRX_PT X_N3
DMI_CRX_PT X_P3
DMI_CTX_PR X_P0
DMI_CTX_PR X_N0
DMI_CTX_PR X_N1
DMI_CTX_PR X_P1
DMI_CTX_PR X_P2
DMI_CTX_PR X_N2
DMI_CTX_PR X_N3
DMI_CTX_PR X_P3
PEG_RCOMP
PEG_CRX_G TX_N1
PEG_CRX_G TX_P1
PEG_CRX_G TX_P2
PEG_CRX_G TX_N2
PEG_CRX_G TX_P3
PEG_CRX_G TX_N3
PEG_CRX_G TX_N4
PEG_CRX_G TX_P4
PEG_CRX_G TX_N5
PEG_CRX_G TX_P5
PEG_CRX_G TX_N6
PEG_CRX_G TX_P6
PEG_CRX_G TX_N7
PEG_CRX_G TX_P7
PEG_CRX_G TX_N8
PEG_CRX_G TX_P8
PEG_CRX_G TX_N9
PEG_CRX_G TX_P9
PEG_CRX_G TX_N10
PEG_CRX_G TX_P10
PEG_CRX_G TX_N11
PEG_CRX_G TX_P11
PEG_CRX_G TX_N12
PEG_CRX_G TX_P12
PEG_CRX_G TX_N13
PEG_CRX_G TX_P13
PEG_CRX_G TX_N14
PEG_CRX_G TX_P14
PEG_CRX_G TX_P0
PEG_CRX_G TX_N0
PEG_CRX_G TX_N15
PEG_CRX_G TX_P15
PEG_CTX_G RX_N1
PEG_CTX_G RX_P1
PEG_CTX_G RX_N2
PEG_CTX_G RX_P2
PEG_CTX_G RX_N3
PEG_CTX_G RX_P3
PEG_CTX_G RX_N4
PEG_CTX_G RX_P4
PEG_CTX_G RX_N5
PEG_CTX_G RX_P5
PEG_CTX_G RX_N6
PEG_CTX_G RX_P6
PEG_CTX_G RX_N7
PEG_CTX_G RX_P7
PEG_CTX_G RX_N8
PEG_CTX_G RX_P8
PEG_CTX_G RX_N9
PEG_CTX_G RX_P9
PEG_CTX_G RX_N10
PEG_CTX_G RX_P10
PEG_CTX_G RX_N11
PEG_CTX_G RX_P11
PEG_CTX_G RX_N12
PEG_CTX_G RX_P12
PEG_CTX_G RX_N13
PEG_CTX_G RX_P13
PEG_CTX_G RX_N14
PEG_CTX_G RX_P14
PEG_CTX_G RX_N15
PEG_CTX_G RX_P15
PEG_CTX_G RX_N0
PEG_CTX_G RX_P0
DMI_CRX_PTX _N0<14>
DMI_CRX_PTX _P0<14>
DMI_CRX_PTX _N1<14>
DMI_CRX_PTX _P1<14>
DMI_CRX_PTX _P2<14>
DMI_CRX_PTX _N2<14>
DMI_CRX_PTX _N3<14>
DMI_CRX_PTX _P3<14>
DMI_CTX_PR X_N1 <14>
DMI_CTX_PR X_P1 <14>
DMI_CTX_PR X_N0 <14>
DMI_CTX_PR X_P0 <14>
DMI_CTX_PR X_P3 <14>
DMI_CTX_PR X_N3 <14>
DMI_CTX_PR X_N2 <14>
DMI_CTX_PR X_P2 <14>
PEG_CRX_ C_GTX_P0<27>
PEG_CRX_ C_GTX_N0<27>
PEG_CRX_ C_GTX_P1<27>
PEG_CRX_ C_GTX_N1<27>
PEG_CRX_ C_GTX_P2<27>
PEG_CRX_ C_GTX_N2<27>
PEG_CRX_ C_GTX_N3<27>
PEG_CRX_ C_GTX_P3<27>
PEG_CRX_ C_GTX_P4<27>
PEG_CRX_ C_GTX_N4<27>
PEG_CRX_ C_GTX_P5<27>
PEG_CRX_ C_GTX_N5<27>
PEG_CRX_ C_GTX_N6<27>
PEG_CRX_ C_GTX_P6<27>
PEG_CRX_ C_GTX_P7<27>
PEG_CRX_ C_GTX_N7<27>
PEG_CRX_ C_GTX_N8<27>
PEG_CRX_ C_GTX_P8<27>
PEG_CRX_ C_GTX_P9<27>
PEG_CRX_ C_GTX_N9<27>
PEG_CRX_ C_GTX_P10<27>
PEG_CRX_ C_GTX_N10<27>
PEG_CRX_ C_GTX_N11<27>
PEG_CRX_ C_GTX_P11<27>
PEG_CRX_ C_GTX_P12<27>
PEG_CRX_ C_GTX_N12<27>
PEG_CRX_ C_GTX_P13<27>
PEG_CRX_ C_GTX_N13<27>
PEG_CRX_ C_GTX_N14<27>
PEG_CRX_ C_GTX_P14<27>
PEG_CRX_ C_GTX_P15<27>
PEG_CRX_ C_GTX_N15<27>
PEG_CTX_C_ GRX_N0 <27>
PEG_CTX_ C_GRX_P0 <27>
PEG_CTX_C_ GRX_N1 <27>
PEG_CTX_ C_GRX_P1 <27>
PEG_CTX_ C_GRX_P2 <27>
PEG_CTX_C_ GRX_N2 <27>
PEG_CTX_C_ GRX_N3 <27>
PEG_CTX_ C_GRX_P3 <27>
PEG_CTX_C_ GRX_N4 <27>
PEG_CTX_ C_GRX_P4 <27>
PEG_CTX_ C_GRX_P5 <27>
PEG_CTX_C_ GRX_N5 <27>
PEG_CTX_ C_GRX_P6 <27>
PEG_CTX_C_ GRX_N6 <27>
PEG_CTX_C_ GRX_N7 <27>
PEG_CTX_ C_GRX_P7 <27>
PEG_CTX_ C_GRX_P8 <27>
PEG_CTX_C_ GRX_N8 <27>
PEG_CTX_C_ GRX_N9 <27>
PEG_CTX_ C_GRX_P9 <27>
PEG_CTX_C_ GRX_N10 <27>
PEG_CTX_ C_GRX_P10 <27>
PEG_CTX_ C_GRX_P11 <27>
PEG_CTX_C_ GRX_N11 <27>
PEG_CTX_C_ GRX_N12 <27>
PEG_CTX_ C_GRX_P12 <27>
PEG_CTX_ C_GRX_P13 <27>
PEG_CTX_C_ GRX_N13 <27>
PEG_CTX_ C_GRX_P14 <27>
PEG_CTX_C_ GRX_N14 <27>
PEG_CTX_C_ GRX_N15 <27>
PEG_CTX_ C_GRX_P15 <27>
+VCCIO
Title
Size Document Number R e v
Date: Sheet o f
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEE RING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET IN FORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AU THORIZED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHEET NOR THE INFORMA TION IT CONTAINS
MAY BE USED BY OR DISC LOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELEC TRONICS, INC.
Issued Date
Deciphered Date
FH51M M/B LA-J871P
1.0
PEG/DMI
Custom
9 112Tuesday, Feb ruary 11, 2020
2019/09/20 2020/09/20
Compal Electronics, Inc.
Title
Size Document Number R e v
Date: Sheet o f
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEE RING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET IN FORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AU THORIZED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHEET NOR THE INFORMA TION IT CONTAINS
MAY BE USED BY OR DISC LOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELEC TRONICS, INC.
Issued Date
Deciphered Date
FH51M M/B LA-J871P
1.0
PEG/DMI
Custom
9 112Tuesday, Feb ruary 11, 2020
2019/09/20 2020/09/20
Compal Electronics, Inc.
Title
Size Document Number R e v
Date: Sheet o f
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEE RING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET IN FORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AU THORIZED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHEET NOR THE INFORMA TION IT CONTAINS
MAY BE USED BY OR DISC LOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELEC TRONICS, INC.
Issued Date
Deciphered Date
FH51M M/B LA-J871P
1.0
PEG/DMI
Custom
9 112Tuesday, Feb ruary 11, 2020
2019/09/20 2020/09/20
Compal Electronics, Inc.
CC14 0.22U_0201_6.3V6KVGA@
1 2
CC20 0.22U_0201_6.3V6KVGA@
1 2
CC130.22U_020 1_6.3V6K VGA@
12
CC57 0.22U_0201_6.3V6KVGA@
1 2
CC180.22U_020 1_6.3V6K VGA@
12
CC620.22U_020 1_6.3V6K VGA@
12
CC25 0.22U_0201_6.3V6KVGA@
1 2
CC17 0.22U_0201_6.3V6KVGA@
1 2
CC260.22U_020 1_6.3V6K VGA@
12
CC39 0.22U_0201_6.3V6KVGA@
1 2
CC640.22U_020 1_6.3V6K VGA@
12
CC560.22U_020 1_6.3V6K VGA@
12
CC27 0.22U_0201_6.3V6KVGA@
1 2
CC35 0.22U_0201_6.3V6KVGA@
1 2
CC540.22U_020 1_6.3V6K VGA@
12
CC63 0.22U_0201_6.3V6KVGA@
1 2
CC420.22U_020 1_6.3V6K VGA@
12
CC110.22U_020 1_6.3V6K VGA@
12
CC53 0.22U_0201_6.3V6KVGA@
1 2
CC43 0.22U_0201_6.3V6KVGA@
1 2
CC280.22U_020 1_6.3V6K VGA@
12
CC23 0.22U_0201_6.3V6KVGA@
1 2
CC240.22U_020 1_6.3V6K VGA@
12
CC480.22U_020 1_6.3V6K VGA@
12
CC59 0.22U_0201_6.3V6KVGA@
1 2
CC55 0.22U_0201_6.3V6KVGA@
1 2
CC400.22U_020 1_6.3V6K VGA@
12
CC19 0.22U_0201_6.3V6KVGA@
1 2
CC600.22U_020 1_6.3V6K VGA@
12
CC440.22U_0201 _6.3V6K VGA@
12
CC51 0.22U_0201_6.3V6KVGA@
1 2
CC16 0.22U_0201_6.3V6KVGA@
1 2
CC520.22U_0201 _6.3V6K VGA@
12
CC29 0.22U_0201_6.3V6KVGA@
1 2
CC210.22U_0201 _6.3V6K VGA@
12
CC340.22U_0201 _6.3V6K VGA@
12
3 OF 13
CFL-H
UC1C
CFL-H_BGA144 0
@
PEG_RXP_0
E25
PEG_RXN_0
D25
PEG_RXP_1
E24
PEG_RXN_1
F24
PEG_RXP_2
E23
PEG_RXN_2
D23
PEG_RXP_3
E22
PEG_RXN_3
F22
PEG_RXP_4
E21
PEG_RXN_4
D21
PEG_RXP_5
E20
PEG_RXN_5
F20
PEG_RXP_6
E19
PEG_RXN_6
D19
PEG_RXP_7
E18
PEG_RXN_7
F18
PEG_RXP_8
D17
PEG_RXN_8
E17
PEG_RXP_9
F16
PEG_RXN_9
E16
PEG_RXP_10
D15
PEG_RXN_10
E15
PEG_RXP_11
F14
PEG_RXN_11
E14
PEG_RXP_12
D13
PEG_RXN_12
E13
PEG_RXP_13
F12
PEG_RXN_13
E12
PEG_RXP_14
D11
PEG_RXN_14
E11
PEG_RXP_15
F10
PEG_RXN_15
E10
DMI_RXP_0
D8
DMI_RXN_0
E8
DMI_RXP_1
E6
DMI_RXN_1
F6
DMI_RXP_2
D5
DMI_RXN_2
E5
DMI_RXP_3
J8
DMI_RXN_3
J9
PEG_TXP_0
B25
PEG_TXN_0
A25
PEG_TXP_1
B24
PEG_TXN_1
C24
PEG_TXP_2
B23
PEG_TXN_2
A23
PEG_TXP_3
B22
PEG_TXN_3
C22
PEG_TXP_4
B21
PEG_TXN_4
A21
PEG_TXP_5
B20
PEG_TXN_5
C20
PEG_TXP_6
B19
PEG_TXN_6
A19
PEG_TXP_7
B18
PEG_TXN_7
C18
PEG_TXP_8
A17
PEG_TXN_8
B17
PEG_TXP_9
C16
PEG_TXN_9
B16
PEG_TXP_10
A15
PEG_TXN_10
B15
PEG_TXP_11
C14
PEG_TXN_11
B14
PEG_TXP_12
A13
PEG_TXN_12
B13
PEG_TXP_13
C12
PEG_TXN_13
B12
PEG_TXP_14
A11
PEG_TXN_14
B11
PEG_TXP_15
C10
PEG_TXN_15
B10
DMI_TXP_0
B8
DMI_TXN_0
A8
DMI_TXP_1
C6
DMI_TXN_1
B6
DMI_TXP_2
B5
DMI_TXN_2
A5
DMI_TXP_3
D4
DMI_TXN_3
B4
PEG_RCOMP
G2
CC47 0.22U_0201_6.3V6KVGA@
1 2
CC3 0.22U_0 201_6.3V6KVGA@
1 2
CC500.22U_0201 _6.3V6K VGA@
12
CC61 0.22U_0201_6.3V6KVGA@
1 2
CC150.22U_0201 _6.3V6K VGA@
12
CC120.22U_0201 _6.3V6K VGA@
12
CC37 0.22U_0201_6.3V6KVGA@
1 2
CC31 0.22U_0201_6.3V6KVGA@
1 2
CC49 0.22U_0201_6.3V6KVGA@
1 2
CC220.22U_0201 _6.3V6K VGA@
12
CC300.22U_0201 _6.3V6K VGA@
12
CC6 0.22U_0 201_6.3V6KVGA@
1 2
CC41 0.22U_0201_6.3V6KVGA@
1 2
CC5 0.22U_0 201_6.3V6KVGA@
1 2
CC320.22U_0201 _6.3V6K VGA@
12
CC460.22U_0201 _6.3V6K VGA@
12
CC10 0.22U_0201_6.3V6KVGA@
1 2
CC580.22U_0201 _6.3V6K VGA@
12
CC1 0.22U_0 201_6.3V6KVGA@
1 2
CC7 0.22U_0 201_6.3V6KVGA@
1 2
CC380.22U_0201 _6.3V6K VGA@
12
CC40.22U_0201 _6.3V6K VGA@
12
CC20.22U_0201 _6.3V6K VGA@
12
CC33 0.22U_0201_6.3V6KVGA@
1 2
CC45 0.22U_0201_6.3V6KVGA@
1 2
CC90.22U_020 1_6.3V6K VGA@
12
RC6 24.9_0402_ 1%
1 2
CC360.22U_020 1_6.3V6K VGA@
12
CC80.22U_020 1_6.3V6K VGA@
12
www.laptoprepairsecrets.com
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
Trace Width/Space: 4 mil/ 12 mil
Max Trace Length: 600 mil
CFG[0]: Stall reset sequence after PCU PLL lock until de-asserted
1 = (Default) Normal Operation;
0 = Stall.
1 = Normal operation
0 = Lane numbers reversed.
CFG[2]: PCI Express* Static x16 Lane Numbering Reversal.
CFG[4]: eDP enable:
1 = Disabled.
0 = Enabled.
CFG[6:5]: PCI Express* Bifurcation:
00 = 1 x8, 2 x4 PCI Express*
01 = reserved
10 = 2 x8 PCI Express*
11 = 1 x16 PCI Express*
CFG[7]: PEG Training:
1 = (default) PEG Train immediately following RESET# de assertion.
0 = PEG Wait for BIOS for training.
The CFG signals have a default value of '1' if not terminated on the board.
*CFG Pin Use CMC debug on DDX03 R02 Schematic.
To be confirm
SVID
Sensitive
Sensitive
571391_CFL_H_P DG_Rev0p5
1. The total Length of Data and Clock (from CPU to each VR) must be equal (± 0.1 inch).
2. Route the Alert signal between the Clock and the Data signals.
3. Place those resistors close CPU side.
8/21 follow 1050 Request
Near CPU side
20191024
PROC_SELECT#
> should be unconnected on CFL/CML processor
*20191024
- CML RCP/PDG/ Check list , PROC_TDO PU 10 0 ohm to VCCX T
*20191104
- CMC@ change to always pop (RC76/77/78/7 9)
Place to CPU side
*
*
*
*
*
8/21 PU 330K follow CRB
Place to CPU side
PCH_CPU_BCL K_P
PCH_CPU_BCL K_N
PCH_CPU_PCIBC LK_P
PCH_CPU_PCIBC LK_N
PCH_CPU_24 M_CLK_P
PCH_CPU_24 M_CLK_N
CFG_RCOMP
CATERR#
CPU_SVID_ ALERT#
CPU_SVID_ DAT_R
CPU_SVID_ CLK_R
XDP_BPM# 0
XDP_BPM# 1
XDP_BPM# 2
XDP_BPM# 3
H_PROCHO T#_R
CPU_XDP_TC K0
CPU_XDP_TM S
CPU_XDP_T DI
CPU_XDP_T RST#
CPU_XDP_T DO
XDP_PRDY#
XDP_PRE Q#
DDR_PG_C TRL
H_CPUPWRG D
H_PLTRST _CPU#
H_PM_SYNC _R
H_PM_DOWN
H_PECI
H_THERMTR IP#
SKTOCC#
CFG0
CFG4
CFG2
CFG7
CFG6
CFG5
CFG0
CFG2
CFG4
CFG5
CFG6
CFG7
EC_VCCST _PG
H_THERMT RIP#
EC_VCCST_ PG
H_CPUPWRG D
H_THERMTR IP#
H_PROCHOT #_R
EC_VCCST_P G
H_PM_DOWN CPU_SVID_A LERT#
CPU_SVID_DA T_R
CPU_XDP_TDO
CPU_XDP_ TMS
CPU_XDP_ TDI
CPU_XDP_T CK0
PCH_JTAG_T CK1
CPU_XDP_T RST#
H_PROCHO T#_R
XDP_PREQ #
XDP_PRDY #
DDR_PG_CTRL
PCH_CPU_P CIBCLK_P<15>
PCH_CPU_BC LK_N<15>
PCH_CPU_BC LK_P<15>
PCH_CPU_ 24M_CLK_N<15>
PCH_CPU_ 24M_CLK_P<15>
PCH_CPU_P CIBCLK_N<15 >
CPU_XDP_TDI <18>
CPU_XDP_TMS <18>
CPU_XDP_TCK0 <18>
CPU_XDP_TRST# <21>
CPU_XDP_TD O <18>
H_CPUPWRGD<18>
H_PLTRST_C PU#<17>
H_PM_SYNC_R<17>
PCH_THERM TRIP#_R< 17>
H_PECI<17,58>
H_PROCHO T#<58,85>
EC_VCCST_ PG_R<58,78>
H_PM_DOWN_ R<17>
CPU_SVID_ALERT#_R<91>
CPU_SVID_CLK _R<91>
CPU_SVID_DA T_R<91>
PCH_JTAG_T CK1 <18>
XDP_PREQ# <21>
XDP_PRDY# <21>
SM_PG_CTR L <88>
+1.05V_VCCS T
+1.05VS_V CCSTG
+1.05V_VCC ST
+1.05V_VCCS T
+1.05VS_V CCSTG
+1.2V_VDDQ
+3VS
Title
Size Document Number R e v
Date: Sheet o f
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEE RING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET IN FORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AU THORIZED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHEET NOR THE INFORMA TION IT CONTAINS
MAY BE USED BY OR DISC LOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELEC TRONICS, INC.
Issued Date
Deciphered Date
FH51M M/B LA-J871P
1.0
CFL-H(5/8)CFG,SVID
Custom
10 112Tue sday, February 11, 2020
2019/09/20 2020/09/20
Compal Electronics, Inc.
Title
Size Document Number R e v
Date: Sheet o f
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEE RING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET IN FORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AU THORIZED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHEET NOR THE INFORMA TION IT CONTAINS
MAY BE USED BY OR DISC LOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELEC TRONICS, INC.
Issued Date
Deciphered Date
FH51M M/B LA-J871P
1.0
CFL-H(5/8)CFG,SVID
Custom
10 112Tue sday, February 11, 2020
2019/09/20 2020/09/20
Compal Electronics, Inc.
Title
Size Document Number R e v
Date: Sheet o f
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEE RING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET IN FORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AU THORIZED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHEET NOR THE INFORMA TION IT CONTAINS
MAY BE USED BY OR DISC LOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELEC TRONICS, INC.
Issued Date
Deciphered Date
FH51M M/B LA-J871P
1.0
CFL-H(5/8)CFG,SVID
Custom
10 112Tue sday, February 11, 2020
2019/09/20 2020/09/20
Compal Electronics, Inc.
RC18
49.9_0402 _1%
1 2
RC16 20_0402_5 %
1 2
TC1 @
RC17 0_0402_5 %@
1 2
CC681000P_0402_50V 7K
ESD@
1 2
CC670.1U_0201_ 10V6K
XESD@
1 2
TC3 @
RC23
330K_0402 _5%
12
RC12 1K_0402_5 %@
1 2
RC14 499_0402_ 1%
1 2
RC80 51_ 0402_5%@
12
UC3
74AUP1G07 SE-7_SOT353-5
2
A4Y
5
Vcc
1
NC
3
G
RC7 1K_0402_5 %@
1 2
RC21
1K_0402_5 %
12
TC4 @
RC13 220_0402_ 5%
1 2
RC78 51_ 0402_5%
12
RC10 1K_0402_5 %@
1 2
RC76 51_ 0402_5%
12
TC2 @
RC9 1K_0402_5 %
1 2
RC81 51_ 0402_5%@
12
RC22
1K_0402_5 %
12
CC661000P_0402_50V 7K
ESD@
1 2
CC69
0.1U_0201_1 0V6K
12
RC15 60.4_0402_ 1%
1 2
TC5@
5 OF 13
CFL-H
UC1E
CFL-H_BGA1 440
@
VIDSOUT
BH29
DDR_VTT_CNTL
BT13
VCCST_PWRGD
H13
PM_SYNC
BM34
PM_DOWN
BP31
PECI
BT34
CFG_18
BN22
PROC_TCK
BR28
CFG_19
BP22
THERMTRIP#
J31
PROC_TDO
BT28
CFG_0
BN25
PROC_TRST#
BP30
CFG_1
BN27
PROC_SELECT#
BN1
ZVM#
AT13
SKTOCC#
BR33
CFG_2
BN26
CFG_RCOMP
BT25
CFG_3
BN28
PROC_PREQ#
BL30
CFG_4
BR20
CFG_10
BT23
RESET#
BP35
CFG_5
BM20
CLK24N
D31
PROCPWRGD
BT31
CFG_11
BT22
CFG_6
BT20
BPM#_0
BR27
VIDSCK
BH32
BCLKN
A32
PCI_BCLKN
C36
BPM#_1
BT27
CFG_7
BP20
CFG_12
BM19
CLK24P
E31
CFG_8
BR23
CFG_13
BR19
BPM#_2
BM31
BCLKP
B31
PCI_BCLKP
D35
BPM#_3
BT30
PROCHOT#
BR30
CFG_9
BR22
CFG_14
BP19
RSVD2
AY13
CFG_15
BT19
RSVD1
AU13
PROC_PRDY#
BP27
CFG_16
BP23
CATERR#
BM30
PROC_TDI
BL32
MSM#
AW13
PROC_TMS
BP28
CFG_17
BN23
VIDALERT#
BH31
RC77 51_ 0402_5%
12
TC6@
RC11 1K_0402_5 %@
1 2
CC650.1U_0201_ 10V6K
XESD@
1 2
RC79 51_ 0402_5%
12
TC19 @
RH2
13_0402_ 5%
@
12
RC20
100_0402 _1%
12
RC19
56_0402_ 1%
12
RC8 1K_0402_5 %
1 2
RH1 1K_0402_ 5%
1 2
TC20 @
www.laptoprepairsecrets.com
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
1. Vcc_SENSE/ Vss_SENSE Tr ace Length Ma tch < 25 mils
2. Maintain 2 5-mil separat ion distance away from any other dynamic s ignals.
1. VccGT_SENS E / VssGT_SENS E Trace Lengt h Match < 25 m ils
2. Maintain 2 5-mil separati on distance a way from any o ther dynamic si gnals.
128000mA(Hexa Core GT2)
GT
32000mA(Hexa Core GT2)
0926
Modify net by power
VCC_SENSE_ IA
VSS_SENSE_ IA
VCC_SENSE _GT
VSS_SENSE _GT
VSS_SENSE _IA <91>
VCC_SENSE_IA <91>
VSS_SENSE _GT <91>
VCC_SENSE_ GT <91>
+VCC_CORE +VCC_CORE +VCC_CORE +VCC_CORE
+VCC_GT+VCC_GT
Title
Size Document Number R e v
Date: Sheet o f
Security Classification
Compal Secret Data
THIS SHEET OF ENGINE ERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, IN C. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFO RMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTODY OF THE COMP ETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHEET NOR THE INFORM ATION IT CONTAINS
MAY BE USED BY OR DIS CLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELEC TRONICS, INC.
Issued Date
Deciphered Date
FH51M M/B LA-J871P
1.0
CFL-H(6/8)VCC_CORE/GT
Custom
11 11 2Tuesday, F ebruary 11, 2020
2019/09/20 2020/09/20
Compal Electronics, Inc.
Title
Size Document Number R e v
Date: Sheet o f
Security Classification
Compal Secret Data
THIS SHEET OF ENGINE ERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, IN C. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFO RMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTODY OF THE COMP ETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHEET NOR THE INFORM ATION IT CONTAINS
MAY BE USED BY OR DIS CLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELEC TRONICS, INC.
Issued Date
Deciphered Date
FH51M M/B LA-J871P
1.0
CFL-H(6/8)VCC_CORE/GT
Custom
11 11 2Tuesday, F ebruary 11, 2020
2019/09/20 2020/09/20
Compal Electronics, Inc.
Title
Size Document Number R e v
Date: Sheet o f
Security Classification
Compal Secret Data
THIS SHEET OF ENGINE ERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, IN C. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFO RMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTODY OF THE COMP ETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHEET NOR THE INFORM ATION IT CONTAINS
MAY BE USED BY OR DIS CLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELEC TRONICS, INC.
Issued Date
Deciphered Date
FH51M M/B LA-J871P
1.0
CFL-H(6/8)VCC_CORE/GT
Custom
11 11 2Tuesday, F ebruary 11, 2020
2019/09/20 2020/09/20
Compal Electronics, Inc.
10 OF 13
CFL-H
UC1J
CFL-H_BGA1 440
@
VCC71
Y32
VCC60
W29
VCC5
N14
VCC70
Y31
VCC4
N13
VCC3
L14
VCC19
P33
VCC2
L13
VCC29
R36
VCC18
P32
VCC1
K14
VCC39
T38
VCC28
R35
VCC17
P31
VCC49
V14
VCC38
T37
VCC27
R34
VCC16
P30
VCC59
W14
VCC48
V13
VCC37
T36
VCC26
R33
VCC15
P29
VCC69
Y30
VCC58
W13
VCC47
U36
VCC36
T35
VCC25
R32
VCC14
P14
VCC68
Y29
VCC57
V38
VCC46
U35
VCC35
T32
VCC24
R31
VCC13
P13
VCC67
W38
VCC56
V37
VCC45
U34
VCC34
T31
VCC23
R13
VCC12
N38
VCC66
W37
VCC55
V36
VCC44
U33
VCC33
T30
VCC22
P36
VCC11
N37
VCC65
W36
VCC54
V35
VCC43
U32
VCC32
T29
VCC21
P35
VCC10
N36
VCC75
Y36
VCC64
W35
VCC53
V34
VCC42
U31
VCC31
R38
VCC20
P34
VCC9
N35
VCC74
Y35
VCC63
W32
VCC52
V33
VCC41
U30
VCC30
R37
VCC8
N32
VCC73
Y34
VCC62
W31
VCC51
V32
VCC40
U29
VCC7
N31
VCC72
Y33
VCC61
W30
VCC50
V31
VCC6
N30
11 OF 13
CFL-H
UC1K
CFL-H_BGA1 440
@
VCCGT63
BB38
VCCGT64
BC29
VCCGT65
BC30
VCCGT66
BC31
VCCGT67
BC32
VCCGT68
BC35
VCCGT69
BC36
VCCGT70
BC37
VCCGT71
BC38
VCCGT72
BD13
VCCGT73
BD14
VCCGT74
BD29
VCCGT75
BD30
VCCGT76
BD31
VCCGT77
BD32
VCCGT78
BD33
VCCGT79
BD34
VCCGT80
BD35
VCCGT81
BD36
VCCGT82
BE31
VCCGT83
BE32
VCCGT84
BE33
VCCGT129
BK21
VCCGT130
BK23
VCCGT131
BK24
VCCGT132
BK26
VCCGT133
BK27
VCCGT134
BL15
VCCGT135
BL16
VCCGT136
BL17
VCCGT137
BL23
VCCGT138
BL24
VCCGT143
BL36
VCCGT148
BM36
VCCGT149
BM37
VCCGT150
BN15
VCCGT151
BN16
VCCGT152
BN17
VCCGT153
BN36
VCCGT154
BN37
VCCGT155
BN38
VCCGT156
BP15
VCCGT157
BP16
VCCGT158
BP17
VCCGT159
BP37
VCCGT160
BP38
VCCGT161
BR15
VCCGT162
BR16
VCCGT163
BR17
VCCGT164
BR37
VCCGT165
BT15
VCCGT166
BT16
VCCGT167
BT17
VCCGT168
BT37
VCCGT_SENSE
AH38
VSSGT_SENSE
AH37
VCCGT141
BL27
VCCGT57
BB32
VCCGT46
BA29
VCCGT35
AW38
VCCGT24
AV34
VCCGT13
AU31
VCCGT2
AT31
VCCGT140
BL26
VCCGT89
BE38
VCCGT56
BB31
VCCGT45
BA14
VCCGT34
AW37
VCCGT23
AV33
VCCGT12
AU30
VCCGT1
AT14
VCCGT99
BF38
VCCGT88
BE37
VCCGT55
BB14
VCCGT44
BA13
VCCGT33
AW36
VCCGT22
AV32
VCCGT11
AU29
VCCGT98
BF37
VCCGT87
BE36
VCCGT54
BB13
VCCGT43
AY38
VCCGT32
AW35
VCCGT21
AV31
VCCGT10
AU14
VCCGT97
BF36
VCCGT86
BE35
VCCGT53
BA36
VCCGT42
AY37
VCCGT31
AW34
VCCGT20
AV30
VCCGT109
BH34
VCCGT96
BF35
VCCGT85
BE34
VCCGT52
BA35
VCCGT41
AY36
VCCGT30
AW33
VCCGT119
BJ23
VCCGT108
BH33
VCCGT95
BF32
VCCGT62
BB37
VCCGT51
BA34
VCCGT40
AY35
VCCGT118
BJ21
VCCGT107
BG36
VCCGT94
BF31
VCCGT61
BB36
VCCGT50
BA33
VCCGT139
BL25
VCCGT128
BK20
VCCGT117
BJ20
VCCGT106
BG35
VCCGT93
BF30
VCCGT60
BB35
VCCGT127
BK19
VCCGT116
BJ19
VCCGT105
BG34
VCCGT92
BF29
VCCGT126
BK17
VCCGT115
BJ17
VCCGT104
BG33
VCCGT91
BF14
VCCGT9
AT38
VCCGT147
BM17
VCCGT125
BK16
VCCGT114
BJ16
VCCGT103
BG32
VCCGT90
BF13
VCCGT19
AV29
VCCGT8
AT37
VCCGT146
BM16
VCCGT124
BJ38
VCCGT113
BH38
VCCGT102
BG31
VCCGT29
AW32
VCCGT18
AU38
VCCGT7
AT36
VCCGT145
BM15
VCCGT123
BJ37
VCCGT112
BH37
VCCGT101
BG30
VCCGT39
AY32
VCCGT28
AW31
VCCGT17
AU37
VCCGT6
AT35
VCCGT144
BL37
VCCGT122
BJ27
VCCGT111
BH36
VCCGT100
BG29
VCCGT49
BA32
VCCGT38
AY31
VCCGT27
AW14
VCCGT16
AU36
VCCGT5
AT34
VCCGT121
BJ26
VCCGT110
BH35
VCCGT59
BB34
VCCGT48
BA31
VCCGT37
AY30
VCCGT26
AV36
VCCGT15
AU35
VCCGT4
AT33
VCCGT142
BL28
VCCGT120
BJ24
VCCGT58
BB33
VCCGT47
BA30
VCCGT36
AY29
VCCGT25
AV35
VCCGT14
AU32
VCCGT3
AT32
9 OF 13
CFL-H
UC1I
CFL-H_BGA14 40
@
VCC93
AL36
VCC82
AK34
VCC71
AJ29
VCC60
AG33
VCC5
AA34
VCC92
AL35
VCC81
AK33
VCC70
AJ14
VCC4
AA33
VCC91
AL32
VCC80
AK32
VCC3
AA32
VCC90
AL31
VCC_SENSE
AG37
VCC19
AC14
VCC2
AA31
VCC29
AD14
VCC18
AC13
VCC1
AA13
VCC109
AN32
VCC39
AE14
VCC28
AD13
VCC17
AB38
VCC119
AP32
VCC108
AN31
VCC49
AF31
VCC38
AE13
VCC27
AC36
VCC16
AB37
VCC118
AP31
VCC107
AN14
VCC59
AG32
VCC48
AF30
VCC37
AD38
VCC26
AC35
VCC15
AB36
VCC117
AP30
VCC106
AN13
VCC69
AH32
VCC58
AG31
VCC47
AF29
VCC36
AD37
VCC25
AC34
VCC14
AB35
VCC116
AP13
VCC105
AM36
VCC79
AK31
VCC68
AH31
VCC57
AG14
VCC46
AE38
VCC35
AD36
VCC24
AC33
VCC13
AB32
VCC115
AN38
VCC104
AM35
VCC89
AL30
VCC78
AJ36
VCC67
AH30
VSS_SENSE
AG38
VCC56
AF38
VCC45
AE37
VCC34
AD35
VCC23
AC32
VCC12
AB31
VCC114
AN37
VCC103
AM34
VCC99
AM30
VCC88
AL29
VCC77
AJ35
VCC66
AH29
VCC55
AF37
VCC44
AE36
VCC33
AD34
VCC22
AC31
VCC11
AB30
VCC124
K13
VCC113
AN36
VCC102
AM33
VCC98
AM29
VCC87
AL13
VCC76
AJ34
VCC65
AH14
VCC54
AF36
VCC43
AE35
VCC32
AD33
VCC21
AC30
VCC10
AB29
VCC123
AP38
VCC112
AN35
VCC101
AM32
VCC97
AM14
VCC86
AK38
VCC75
AJ33
VCC64
AH13
VCC53
AF35
VCC42
AE32
VCC31
AD32
VCC20
AC29
VCC9
AA38
VCC122
AP37
VCC111
AN34
VCC100
AM31
VCC96
AM13
VCC85
AK37
VCC74
AJ32
VCC63
AG36
VCC52
AF34
VCC41
AE31
VCC30
AD31
VCC8
AA37
VCC121
AP36
VCC110
AN33
VCC95
AL38
VCC84
AK36
VCC73
AJ31
VCC62
AG35
VCC51
AF33
VCC40
AE30
VCC7
AA36
VCC120
AP35
VCC94
AL37
VCC83
AK35
VCC72
AJ30
VCC61
AG34
VCC50
AF32
VCC6
AA35
www.laptoprepairsecrets.com
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
+1.2V_VDDQ
Max: 3300mA
+VCC_IO
Max: 6400mA
1. VccGT_SENSE / VssGT_SENS E Trace Lengt h Match < 25 m ils
2. Maintain 25 -mil separati on distance a way from any o ther dynamic si gnals.
+1.2V_VCCPLL_OC
Max: 130mA
Max: 150mA
Max: 60mA
Max: 20mA
571483_CFL_H_RVP_CRB_TDK_Rev0p5
+1.2V_VDDQ_CPU: 10uF * 12 22uF * 4
571483_CFL_H_RVP_CRB_TDK_Rev0p5
+1.05V_VCCST: 1uF * 1
571483_CFL_H_RVP_CRB_TDK_Rev0p5
+0.95VS_VCCIO: 10uF * 12 22uF * 4
571483_CFL_H_RVP_CRB_TDK_Rev0p5
+1.05V_VCCSFR: 1uF * 1
571483_CFL_H_RVP_CRB_TDK_Rev0p5
+1.05VS_VCCSTG: 1uF * 1
PLACE CAP BACKSIDE
150mA
PLACE CAP BACKSIDE PLACE CAP BACKSIDE
+VCC_SA
Max: 11100mA
PLACE CAP BACKSIDE
571483_CFL_H_RVP_CRB_TDK_Rev0p5
+1.2V_VCCPLL_OC: 1uF * 2
VSS_SENSE _SA
VCC_SENS E_SA
VCC_SENS E_VCCIO
VSSIO_SENS E
VCC_SENSE _SA <91>
VSS_SENSE_ SA <91>
VCC_SENSE _VCCIO <90>
VSS_SENSE_ VCCIO <90>
+VCC_SA
+VCCIO
+1.2V_VDDQ
+1.2V_VCCP LL_OC
+1.05V_VCC ST
+1.05VS_VC CSTG
+1.05V_VCC SFR
+1.2V_VDDQ
+1.05V_VCC ST
+VCCIO
+1.05V_VCC SFR
+1.05VS_ VCCSTG
+1.2V_VCCP LL_OC+1.2V_VDDQ
Title
Size Document Number R e v
Date: Sheet o f
Security Classification
Compal Secret Data
THIS SHEET OF ENGINE ERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, IN C. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFO RMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTODY OF THE COMP ETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHEET NOR THE INFORM ATION IT CONTAINS
MAY BE USED BY OR DIS CLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELEC TRONICS, INC.
Issued Date
Deciphered Date
FH51M M/B LA-J871P
1.0
CFL-H(7/8)VCCSA/VCCIO/VDDQ
Custom
12 11 2Tuesday, F ebruary 11, 2020
2019/09/20 2020/09/20
Compal Electronics, Inc.
Title
Size Document Number R e v
Date: Sheet o f
Security Classification
Compal Secret Data
THIS SHEET OF ENGINE ERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, IN C. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFO RMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTODY OF THE COMP ETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHEET NOR THE INFORM ATION IT CONTAINS
MAY BE USED BY OR DIS CLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELEC TRONICS, INC.
Issued Date
Deciphered Date
FH51M M/B LA-J871P
1.0
CFL-H(7/8)VCCSA/VCCIO/VDDQ
Custom
12 11 2Tuesday, Feb ruary 11, 2020
2019/09/20 2020/09/20
Compal Electronics, Inc.
Title
Size Document Number R e v
Date: Sheet o f
Security Classification
Compal Secret Data
THIS SHEET OF ENGINE ERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, IN C. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFO RMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTODY OF THE COMP ETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHEET NOR THE INFORM ATION IT CONTAINS
MAY BE USED BY OR DIS CLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELEC TRONICS, INC.
Issued Date
Deciphered Date
FH51M M/B LA-J871P
1.0
CFL-H(7/8)VCCSA/VCCIO/VDDQ
Custom
12 11 2Tuesday, Feb ruary 11, 2020
2019/09/20 2020/09/20
Compal Electronics, Inc.
C
C
9
4
1
U
_
0
2
0
1
_
6
.
3
V
6
M
1
2
C
C
9
2
1
U
_
0
2
0
1
_
6
.
3
V
6
M
1
2
C
C
7
3
1
0
U
_
0
4
0
2
_
6
.
3
V
6
M
1
2
RC24 0_0402_5%@
1 2
C
C
8
4
2
2
U
_
0
6
0
3
_
6
.
3
V
6
M
1
2
C
C
7
4
1
0
U
_
0
4
0
2
_
6
.
3
V
6
M
1
2
C
C
7
1
1
0
U
_
0
4
0
2
_
6
.
3
V
6
M
1
2
C
C
8
1
1
0
U
_
0
4
0
2
_
6
.
3
V
6
M
1
2
C
C
8
9
1
0
U
_
0
4
0
2
_
6
.
3
V
6
M
1
2
C
C
8
2
2
2
U
_
0
6
0
3
_
6
.
3
V
6
M
1
2
C
C
7
8
1
0
U
_
0
4
0
2
_
6
.
3
V
6
M
1
2
C
C
7
2
1
0
U
_
0
4
0
2
_
6
.
3
V
6
M
1
2
C
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6
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12 OF 13
CFL-H
UC1L
CFL-H_BGA144 0
@
VCCSA1
J30
VCCSA2
K29
VCCSA3
K30
VCCSA4
K31
VCCSA5
K32
VCCSA6
K33
VCCSA7
K34
VCCSA8
K35
VCCSA9
L31
VCCSA10
L32
VCCSA11
L35
VCCSA12
L36
VCCSA13
L37
VCCSA14
L38
VCCSA15
M29
VCCSA16
M30
VCCSA17
M31
VCCSA18
M32
VCCSA19
M33
VCCSA20
M34
VCCSA21
M35
VCCSA22
M36
VCCIO1
AG12
VCCIO2
G15
VCCIO3
G17
VCCIO4
G19
VCCIO5
G21
VCCIO6
H15
VCCIO7
H16
VCCIO8
H17
VCCIO9
H19
VCCIO10
H20
VCCIO11
H21
VCCIO12
H26
VCCIO13
H27
VCCIO14
J15
VCCIO15
J16
VCCIO16
J17
VCCIO17
J19
VCCIO18
J20
VCCIO19
J21
VCCIO20
J26
VCCIO21
J27
VCCST
H30
VCCSA_SENSE
M38
VCCIO_SENSE
H14
VDDQ18
K12
VDDQ2
AE12
VDDQ17
J6
VDDQ1
AA6
VDDQ16
J5
VDDQ15
AY6
VDDQ25
Y12
VDDQ14
AW6
VDDQ24
W6
VDDQ13
AT12
VDDQ23
T6
VCCSTG2
H29
VDDQ12
AR6
VDDQ22
R6
VCCSTG1
G30
VDDQ11
AR12
VDDQ21
L6
VDDQ10
AP7
VDDQ20
L12
VCCPLL_OC3
G11
VCCPLL_OC2
BJ13
VDDQ9
AP6
VCCPLL_OC1
BH13
VDDQ8
AL11
VDDQ7
AJ12
VCCPLL2
J28
VDDQ6
AG9
VCCPLL1
H28
VDDQ5
AG5
VSSSA_SENSE
M37
VSSIO_SENSE
J14
VDDQ4
AF6
VDDQ19
K6
VDDQ3
AF5
C
C
7
6
1
0
U
_
0
4
0
2
_
6
.
3
V
6
M
1
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RC25 0_0402_5 %@
1 2
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1
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2
2
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C
C
7
7
1
0
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_
0
4
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2
_
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3
V
6
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1
2
www.laptoprepairsecrets.com
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
Impedance Spectrum Tool Trigger
Add for Corner NCTF testing
PCH_TRIGOUT _R
CPU_TRIGOUT
IST_TRIG
PCH_TRIGOUT _R<21>
CPU_TRIGOUT_ R<21>
Title
Size Document Number R e v
Date: Sheet o f
Security Classification
Compal Secret Data
THIS SHEET OF ENGINE ERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, IN C. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFO RMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTODY OF THE COMP ETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHEET NOR THE INFORM ATION IT CONTAINS
MAY BE USED BY OR DIS CLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELEC TRONICS, INC.
Issued Date
Deciphered Date
FH51M M/B LA-J871P
1.0
CFL-H(8/8)GND/RSVD
Custom
13 11 2Tuesday, F ebruary 11, 2020
2019/09/20 2020/09/20
Compal Electronics, Inc.
Title
Size Document Number R e v
Date: Sheet o f
Security Classification
Compal Secret Data
THIS SHEET OF ENGINE ERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, IN C. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFO RMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTODY OF THE COMP ETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHEET NOR THE INFORM ATION IT CONTAINS
MAY BE USED BY OR DIS CLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELEC TRONICS, INC.
Issued Date
Deciphered Date
FH51M M/B LA-J871P
1.0
CFL-H(8/8)GND/RSVD
Custom
13 11 2Tuesday, F ebruary 11, 2020
2019/09/20 2020/09/20
Compal Electronics, Inc.
Title
Size Document Number R e v
Date: Sheet o f
Security Classification
Compal Secret Data
THIS SHEET OF ENGINE ERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, IN C. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFO RMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTODY OF THE COMP ETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHEET NOR THE INFORM ATION IT CONTAINS
MAY BE USED BY OR DIS CLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELEC TRONICS, INC.
Issued Date
Deciphered Date
FH51M M/B LA-J871P
1.0
CFL-H(8/8)GND/RSVD
Custom
13 11 2Tuesday, F ebruary 11, 2020
2019/09/20 2020/09/20
Compal Electronics, Inc.
TC11@
TC10@
TC9@
TC8@
8 OF 13
CFL-H
UC1H
CFL-H_BGA14 40
@
VSS_325
BN4
VSS_326
BN7
VSS_327
BP12
VSS_328
BP14
VSS_329
BP18
VSS_330
BP21
VSS_331
BP24
VSS_332
BP25
VSS_333
BP26
VSS_334
BP29
VSS_335
BP33
VSS_336
BP34
VSS_337
BP7
VSS_338
BR12
VSS_339
BR14
VSS_340
BR18
VSS_341
BR21
VSS_342
BR24
VSS_343
BR25
VSS_344
BR26
VSS_345
BR29
VSS_346
BR34
VSS_347
BR36
VSS_348
BR7
VSS_349
BT12
VSS_350
BT14
VSS_351
BT18
VSS_352
BT21
VSS_353
BT24
VSS_354
BT26
VSS_355
BT29
VSS_356
BT32
VSS_357
BT5
VSS_358
C11
VSS_359
C13
VSS_360
C15
VSS_361
C17
VSS_362
C19
VSS_363
C21
VSS_364
C23
VSS_365
C25
VSS_366
C27
VSS_367
C29
VSS_368
C31
VSS_369
C37
VSS_370
C5
VSS_371
C8
VSS_372
C9
VSS_373
D10
VSS_374
D12
VSS_375
D14
VSS_376
D16
VSS_377
D18
VSS_378
D20
VSS_379
D22
VSS_380
D24
VSS_381
D26
VSS_382
D28
VSS_383
D3
VSS_384
D30
VSS_385
D33
VSS_386
D6
VSS_387
D9
VSS_388
E34
VSS_389
E35
VSS_390
E38
VSS_391
E4
VSS_392
E9
VSS_393
N3
VSS_394
N33
VSS_395
N34
VSS_396
N4
VSS_397
N5
VSS_398
N6
VSS_399
N7
VSS_400
N8
VSS_401
N9
VSS_402
P12
VSS_403
P37
VSS_404
M14
VSS_405
M6
VSS_406
N1
VSS_407
F11
VSS_408
F13
VSS_409
F15
VSS_410
F17
VSS_411
F19
VSS_412
F2
VSS_413
F21
VSS_414
F23
VSS_415
F25
VSS_416
F27
VSS_417
F29
VSS_418
F3
VSS_419
F31
VSS_420
F36
VSS_421
F4
VSS_422
F5
VSS_423
F8
VSS_424
F9
VSS_425
G10
VSS_426
G12
VSS_427
G14
VSS_428
G16
VSS_429
G18
VSS_430
G20
VSS_431
G22
VSS_432
G23
VSS_433
G24
VSS_434
G26
VSS_435
G28
VSS_436
G4
VSS_437
G5
VSS_438
G6
VSS_439
G8
VSS_440
G9
VSS_441
H11
VSS_442
H12
VSS_443
H18
VSS_444
H22
VSS_445
H25
VSS_446
H32
VSS_447
H35
VSS_448
J10
VSS_449
J18
VSS_450
J22
VSS_451
J25
VSS_452
J32
VSS_453
J33
VSS_454
J36
VSS_455
J4
VSS_456
J7
VSS_457
K1
VSS_458
K10
VSS_459
K11
VSS_460
K2
VSS_461
K3
VSS_462
K38
VSS_463
K4
VSS_464
K5
VSS_465
K7
VSS_466
K8
VSS_467
K9
VSS_468
L29
VSS_469
L30
VSS_470
L33
VSS_471
L34
VSS_472
M12
VSS_473
M13
VSS_474
N10
VSS_475
N11
VSS_476
N12
VSS_477
N2
VSS_478
BT8
VSS_479
BR9
VSS_BT35
BT35
VSS_BT36
BT36
VSS_BR38
BR38
VSS_B37
B37
VSS_D38
D38
VSS_C2
C2
VSS_B3
B3
VSS_A3
A3
VSS_A4
A4
VSS_A34
A34
VSS_BT3
BT3
VSS_BT4
BT4
TC18 @
TC14 @
TC13 @
TC17 @
TC16 @
TC15 @
TC12@
TC7@
7 OF 13
CFL-H
UC1G
CFL-H_BGA14 40
@
VSS_163
AW5
VSS_164
AY12
VSS_165
AY33
VSS_166
AY34
VSS_167
B9
VSS_168
BA10
VSS_169
BA11
VSS_170
BA12
VSS_171
BA37
VSS_172
BA38
VSS_173
BA6
VSS_174
BA7
VSS_175
BA8
VSS_176
BA9
VSS_177
BB1
VSS_178
BB12
VSS_179
BB2
VSS_180
BB29
VSS_181
BB3
VSS_182
BB30
VSS_183
BB4
VSS_184
BB5
VSS_185
BB6
VSS_186
BC12
VSS_187
BC13
VSS_188
BC14
VSS_189
BC33
VSS_190
BC34
VSS_191
BC6
VSS_192
BD10
VSS_193
BD11
VSS_194
BD12
VSS_195
BD37
VSS_196
BD6
VSS_197
BD7
VSS_198
BD8
VSS_199
BD9
VSS_200
BE1
VSS_201
BE2
VSS_202
BE29
VSS_203
BE3
VSS_204
BE30
VSS_205
BE4
VSS_206
BE5
VSS_207
BE6
VSS_208
BF12
VSS_209
BF33
VSS_210
BF34
VSS_211
BF6
VSS_212
BG12
VSS_213
BG13
VSS_214
BG14
VSS_215
BG37
VSS_216
BG38
VSS_217
BG6
VSS_218
BH1
VSS_219
BH10
VSS_220
BH11
VSS_221
BH12
VSS_222
BH14
VSS_223
BH2
VSS_224
BH3
VSS_225
BH4
VSS_226
BH5
VSS_227
BH6
VSS_228
BH7
VSS_229
BH8
VSS_230
BH9
VSS_231
T2
VSS_232
T3
VSS_233
T33
VSS_234
T34
VSS_235
T4
VSS_236
T5
VSS_237
T7
VSS_238
T8
VSS_239
T9
VSS_240
U37
VSS_241
U38
VSS_242
BJ12
VSS_243
BJ14
VSS_244
BJ15
VSS_245
BJ18
VSS_246
BJ22
VSS_247
BJ25
VSS_248
BJ29
VSS_249
BJ30
VSS_250
BJ31
VSS_251
BJ32
VSS_252
BJ33
VSS_253
BJ34
VSS_254
BJ35
VSS_255
BJ36
VSS_256
BK13
VSS_257
BK14
VSS_258
BK15
VSS_259
BK18
VSS_260
BK22
VSS_261
BK25
VSS_262
BK29
VSS_263
BK6
VSS_264
BL13
VSS_265
BL14
VSS_266
BL18
VSS_267
BL19
VSS_268
BL20
VSS_269
BL21
VSS_270
BL22
VSS_271
BL29
VSS_272
BL33
VSS_273
BL35
VSS_274
BL38
VSS_275
BL6
VSS_276
BM11
VSS_277
BM12
VSS_278
BM13
VSS_279
BM14
VSS_280
BM18
VSS_281
BM2
VSS_282
BM21
VSS_283
BM22
VSS_284
BM23
VSS_285
BM24
VSS_286
BM25
VSS_287
BM26
VSS_288
BM27
VSS_289
BM28
VSS_290
BM29
VSS_291
BM3
VSS_292
BM33
VSS_293
BM35
VSS_294
BM38
VSS_295
BM5
VSS_296
BM6
VSS_297
BM7
VSS_298
BM8
VSS_299
BM9
VSS_300
BN12
VSS_301
BN14
VSS_302
BN18
VSS_303
BN19
VSS_304
BN2
VSS_305
BN20
VSS_306
BN21
VSS_307
BN24
VSS_308
BN29
VSS_309
BN30
VSS_310
BN31
VSS_311
BN34
VSS_312
P38
VSS_313
P6
VSS_314
R12
VSS_315
R29
VSS_316
AY14
VSS_317
BD38
VSS_318
R30
VSS_319
T1
VSS_320
T10
VSS_321
T11
VSS_322
T12
VSS_323
T13
VSS_324
T14
13 OF 13
CFL-H
UC1M
CFL-H_BGA14 40
@
VSS_A37
A37
RSVD19
BR35
RSVD29
J3
RSVD18
BR31
RSVD9
BH30
RSVD28
J24
RSVD_TP5
E2
RSVD17
BR2
RSVD8
B38
RSVD27
H24
RSVD_TP4
E1
RSVD16
BP1
RSVD7
B30
RSVD26
G3
RSVD_TP3
D1
RSVD15
BN35
RSVD6
B2
RSVD25
G13
RSVD_TP2
BT2
RSVD14
BN33
RSVD5
AP29
RSVD24
F30
RSVD_TP1
BR1
RSVD13
BL34
RSVD4
AP14
RSVD23
E30
RSVD12
BL31
RSVD3
AJ8
RSVD22
C38
RSVD11
BK28
RSVD2
AE29
PROC_TRIGOUT
J23
RSVD21
C30
RSVD10
BJ28
RSVD1
AA14
RSVD31
R14
PROC_TRIGIN
H23
IST_TRIG
E3
RSVD20
C1
RSVD30
N29
VSS_A36
A36
RC26 30_0402_5 %
1 2
6 OF 13
CFL-H
UC1F
CFL-H_BGA1 440
@
VSS_1
A10
VSS_2
A12
VSS_3
A16
VSS_4
A18
VSS_5
A20
VSS_6
A22
VSS_7
A24
VSS_8
A26
VSS_9
A28
VSS_10
A30
VSS_11
A6
VSS_12
A9
VSS_13
AA12
VSS_14
AA29
VSS_15
AA30
VSS_16
AB33
VSS_17
AB34
VSS_18
AB6
VSS_19
AC1
VSS_20
AC12
VSS_21
AC2
VSS_22
AC3
VSS_23
AC37
VSS_24
AC38
VSS_25
AC4
VSS_26
AC5
VSS_27
AC6
VSS_28
AD10
VSS_29
AD11
VSS_30
AD12
VSS_31
AD29
VSS_32
AD30
VSS_33
AD6
VSS_34
AD8
VSS_35
AD9
VSS_36
AE33
VSS_37
AE34
VSS_38
AE6
VSS_39
AF1
VSS_40
AF12
VSS_41
AF13
VSS_42
AF14
VSS_43
AF2
VSS_44
AF3
VSS_45
AF4
VSS_46
AG10
VSS_47
AG11
VSS_48
AG13
VSS_49
AG29
VSS_50
AG30
VSS_51
AG6
VSS_52
AG7
VSS_53
AG8
VSS_54
AH12
VSS_55
AH33
VSS_56
AH34
VSS_57
AH35
VSS_58
AH36
VSS_59
AH6
VSS_60
AJ1
VSS_61
AJ13
VSS_62
AJ2
VSS_63
AJ3
VSS_64
AJ37
VSS_65
AJ38
VSS_66
AJ4
VSS_67
AJ5
VSS_68
AJ6
VSS_69
W4
VSS_70
W5
VSS_71
Y10
VSS_72
Y11
VSS_73
Y13
VSS_74
Y14
VSS_75
Y37
VSS_76
Y38
VSS_77
Y7
VSS_78
Y8
VSS_79
Y9
VSS_80
AK29
VSS_81
AK30
VSS_82
AK4
VSS_83
AL10
VSS_84
AL12
VSS_85
AL14
VSS_86
AL33
VSS_87
AL34
VSS_88
AL4
VSS_89
AL7
VSS_90
AL8
VSS_91
AL9
VSS_92
AM1
VSS_93
AM12
VSS_94
AM2
VSS_95
AM3
VSS_96
AM37
VSS_97
AM38
VSS_98
AM4
VSS_99
AM5
VSS_100
AN12
VSS_101
AN29
VSS_102
AN30
VSS_103
AN5
VSS_104
AN6
VSS_105
AP10
VSS_106
AP11
VSS_107
AP12
VSS_108
AP33
VSS_109
AP34
VSS_110
AP8
VSS_111
AP9
VSS_112
AR1
VSS_113
AR13
VSS_114
AR14
VSS_115
AR2
VSS_116
AR29
VSS_117
AR3
VSS_118
AR30
VSS_119
AR31
VSS_120
AR32
VSS_121
AR33
VSS_122
AR34
VSS_123
AR35
VSS_124
AR36
VSS_125
AR37
VSS_126
AR38
VSS_127
AR4
VSS_128
AR5
VSS_129
AT29
VSS_130
AT30
VSS_131
AT6
VSS_132
AU10
VSS_133
AU11
VSS_134
AU12
VSS_135
AU33
VSS_136
AU34
VSS_137
AU6
VSS_138
AU7
VSS_139
AU8
VSS_140
AU9
VSS_141
AV37
VSS_142
AV38
VSS_143
AW1
VSS_144
AW12
VSS_145
AW2
VSS_146
AW29
VSS_147
AW3
VSS_148
AW30
VSS_149
AW4
VSS_150
U6
VSS_151
V12
VSS_152
V29
VSS_153
V30
VSS_154
A14
VSS_155
AD7
VSS_156
V6
VSS_157
W1
VSS_158
W12
VSS_159
W2
VSS_160
W3
VSS_161
W33
VSS_162
W34
www.laptoprepairsecrets.com
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
The 30 HSIO la nes on PCH-H supports the f ollowing confi gurations:
1. Up to 24 PC Ie* Lanes
— A maximum o f 16 PCIe* Por ts (or device s) can be enabl ed
When a GbE Po rt is enabled , the maximum number of PCIe * Ports (or
‧
devices) that can be enable d reduces base d off the foll owing:
Max PCIe* Port s (or devices ) = 16 - GbE ( 0 or 1)
— PCIe* Lanes 1-4 (PCIe* C ontroller #1), 5-8 (PCIe* Co ntroller #2), 9 -12 (PCIe*
Controller #3) , 13-16 (PCIe * Controller # 4), 17-20 (PC Ie* Controller #5), and
21-24 (PCIe* C ontroller #6) can be indivi dually configu red
2. Up to 6 SAT A Lanes
— A maximum o f 6 SATA Port s (or devices) can be enable d
— SATA Lane 0 has the flexibility to be mapped to Flex I/O Lane 16 or 18
— SATA Lane 1 has the flexibility to be mapped to Flex I/O Lane 17 or 19
3. Up to 10 USB 3.1 Lanes
— A maximum of 10 USB 3.1 Ports (or devices) can be enabled
4. Up to 4 GbE Lanes
— A maximum of 1 GbE Port (or device) can be enabled
5. Supports up to 3 Remapped (IntelR Rapid Storage Technology) PCIe* storage
devices
— x2 and x4 PCIe* NVMe SSD
— x2 IntelR Optane? Memory Device
— See the “ PCI Express* (PCIe*)” chapter for the PCH PCIe* Controllers,configurations
, and lanes that can be used for IntelR Rapid Storage Technology PCIe* storage support
6. For unused SATA/PCIe* Combo Lanes, Flex I/O Lanes that can be configured as PCIe* or SATA,
the lanes must be statically assigned to SATA or PCIe* via the SATA/PCIe Combo Port Soft
Straps discussed in the SPI Programming Guide and
through the IntelR Flash Image Tool (FIT) tool.
X'tal Input:
High: Different ial
Low: Single en ded
For CNVI follow 571906_CNL_PCH_TA_WW11.pdf
STRAP
USB3 MB
Camera
TS
FingerPrint
BT
USB2 (SUB/B)
TYPE C
USB2 (SUB/B)
M.2 SSD1 PCIE L0
M.2 SSD1 PCIE L1
M.2 SSD1 PCIE L2
M.2 SSD1 PCIE L3
DMI_CTX_PRX_ N0
DMI_CTX_PRX_ P0
DMI_CRX_PTX_ N0
DMI_CRX_PTX_ P0
DMI_CTX_PRX_ P1
DMI_CTX_PRX_ N1
DMI_CRX_PTX_ N1
DMI_CRX_PTX_ P1
DMI_CTX_PRX_ P2
DMI_CTX_PRX_ N2
DMI_CRX_PTX_ N2
DMI_CRX_PTX_ P2
DMI_CTX_PRX_ P3
DMI_CTX_PRX_ N3
DMI_CRX_PTX_ P3
DMI_CRX_PTX_ N3
USB2_RCOM P
USB2_VBUS_S ENSE
USB2_ID
GPD_7
USB_OC0 #
USB_OC1 #
GPD_7
USB20_P1
USB20_N1
USB20_P2
USB20_N2
USB20_P3
USB20_N3
USB20_N4
USB20_P4
USB20_P5
USB20_N5
USB20_N6
USB20_P6
USB20_N8
USB20_P8
USB20_N1 4
USB20_P14
USB_OC1#
USB_OC0#
DMI_CTX_PRX _N0<9>
DMI_CTX_PRX _P0< 9>
DMI_CRX_PTX_ P0<9 >
DMI_CRX_PTX _N0<9>
DMI_CTX_PRX _P1< 9>
DMI_CTX_PRX _N1<9>
DMI_CTX_PRX _P2< 9>
DMI_CTX_PRX _N2<9>
DMI_CTX_PRX _P3< 9>
DMI_CTX_PRX _N3<9>
DMI_CRX_PTX_ P1<9 >
DMI_CRX_PTX _N1<9>
DMI_CRX_PTX_ P2<9 >
DMI_CRX_PTX _N2<9>
DMI_CRX_PTX_ P3<9 >
DMI_CRX_PTX _N3<9>
USB_OC1# <71>
USB20_P1 < 71>
USB20_N1 <71>
USB20_N2 <73>
USB20_P2 < 73>
USB20_N3 <73>
USB20_P3 < 73>
USB20_P4 < 43>
USB20_N4 <43>
USB20_P5 < 38>
USB20_N5 <38>
USB20_N6 <38>
USB20_P6 < 38>
USB20_N8 <66>
USB20_P8 < 66>
USB20_N1 4 < 52>
USB20_P14 <52>
USB_OC0# <43>
PCIE_PRX_DT X_P24 <68>
PCIE_PTX_DR X_N24 <68>
PCIE_PTX_DR X_P24 <68>
PCIE_PRX_DT X_N24 <68>
PCIE_PRX_DT X_P23 <68>
PCIE_PTX_DR X_N23 <68>
PCIE_PTX_DR X_P23 <68>
PCIE_PRX_DT X_N23 <68>
PCIE_PRX_DT X_P22 <68>
PCIE_PTX_DR X_N22 <68>
PCIE_PTX_DR X_P22 <68>
PCIE_PRX_DT X_N22 <68>
PCIE_PRX_DT X_P21 <68>
PCIE_PTX_DR X_N21 <68>
PCIE_PTX_DR X_P21 <68>
PCIE_PRX_DT X_N21 <68>
+3VALW
+3VALW
Title
Size Document Number R e v
Date: Sheet o f
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEE RING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET IN FORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AU THORIZED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHEET NOR THE INFORMA TION IT CONTAINS
MAY BE USED BY OR DISC LOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELEC TRONICS, INC.
Issued Date
Deciphered Date
FH51M M/B LA-J871P
1.0
PCH(1/8)DMI/PCIE/USB2
Custom
14 112Tue sday, February 11, 2020
2019/09/20 2020/09/20
Compal Electronics, Inc.
Title
Size Document Number R e v
Date: Sheet o f
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEE RING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET IN FORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AU THORIZED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHEET NOR THE INFORMA TION IT CONTAINS
MAY BE USED BY OR DISC LOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELEC TRONICS, INC.
Issued Date
Deciphered Date
FH51M M/B LA-J871P
1.0
PCH(1/8)DMI/PCIE/USB2
Custom
14 112Tue sday, February 11, 2020
2019/09/20 2020/09/20
Compal Electronics, Inc.
Title
Size Document Number R e v
Date: Sheet o f
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEE RING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET IN FORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AU THORIZED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHEET NOR THE INFORMA TION IT CONTAINS
MAY BE USED BY OR DISC LOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELEC TRONICS, INC.
Issued Date
Deciphered Date
FH51M M/B LA-J871P
1.0
PCH(1/8)DMI/PCIE/USB2
Custom
14 112Tue sday, February 11, 2020
2019/09/20 2020/09/20
Compal Electronics, Inc.
RH200 10K_04 02_5%
1 2
RH3
10K_0402 _5%
12
RH201 10K_04 02_5%
1 2
RH5 0_0402_5%@
1 2
RH6 0_0402_5%@
1 2
RH4 113_0402_1%
1 2
2 OF 13
CNP-H
Rev1.0
UH1B
CNP-H_BGA87 4
@
USB2N_1
J3
USB2P_1
J2
USB2N_2
N13
USB2P_2
N15
USB2N_3
K4
USB2P_3
K3
USB2N_4
M10
USB2P_4
L9
USB2N_5
M1
USB2P_5
L2
USB2N_6
K7
USB2P_6
K6
USB2N_7
L4
USB2P_7
L3
USB2N_8
G4
USB2P_8
G5
USB2N_9
M6
USB2P_9
N8
USB2N_10
H3
USB2P_10
H2
USB2N_11
R10
USB2P_11
P9
USB2N_12
G1
USB2P_12
G2
USB2N_13
N3
USB2P_13
N2
USB2N_14
E5
USB2P_14
F6
USB2_COMP
F4
USB2_VBUSSENSE
F3
USB2_ID
G3
RSVD
K29
RSVD
G26
RSVD
E28
DMI2_TXP
B31
PCIE1_TXN/USB31_7_TXN
A17
RSVD
R24
RSVD
L26
RSVD
C27
DMI3_TXP
B29
PCIE4_RXP/USB31_10_RXP
R18
RSVD
F26
RSVD
D29
RSVD
B26
GPP_F17/USB2_OC6#
AR37
RSVD
P24
PCIE3_RXP/USB31_9_RXP
J18
RSVD
B27
RSVD
B25
RSVD
C26
PCIE3_TXP/USB31_9_TXP
C19
RSVD
A25
PCIE21_RXN
T43
PCIE3_RXN/USB31_9_RXN
K18
GPP_E10/USB2_OC1#
AL40
GPP_E9/USB2_OC0#
AH36
PCIE22_RXN
U40
PCIE2_RXP/USB31_8_RXP
P21
PCIE5_RXN
F20
PCIE23_RXN
W43
PCIE21_RXP
R44
PCIE6_RXN
K21
PCIE21_TXN
G47
PCIE4_TXN/USB31_10_TXN
D20
PCIE3_TXN/USB31_9_TXN
B19
GPP_F16/USB2_OC5#
AR35
PCIE24_RXN
Y40
PCIE22_RXP
U41
PCIE7_RXN
L24
PCIE22_TXN
H47
PCIE5_RXP
G20
PCIE2_TXP/USB31_8_TXP
C18
PCIE5_TXN
B21
PCIE23_RXP
W44
PCIE6_RXP
J21
PCIE23_TXN
G49
PCIE21_TXP
F46
PCIE8_RXN
F24
PCIE6_TXN
D21
GPP_E12/USB2_OC3#
AL41
PCIE24_RXP
Y41
PCIE2_RXN/USB31_8_RXN
R21
DMI0_RXN
K34
PCIE7_RXP
J24
PCIE22_TXP
H48
PCIE24_TXN
G46
PCIE7_TXN
C23
PCIE5_TXP
A22
PCIE23_TXP
G48
DMI1_RXN
G33
PCIE8_RXP
G24
PCIE1_RXP/USB31_7_RXP
F16
PCIE6_TXP
C21
PCIE4_TXP/USB31_10_TXP
C20
PCIE8_TXN
B24
GPP_F18/USB2_OC7#
AV43
DMI2_RXN
K32
DMI0_RXP
J35
PCIE24_TXP
G45
DMI0_TXN
C33
GPD7
BE41
PCIE7_TXP
B23
PCIE2_TXN/USB31_8_TXN
B18
PCIE1_TXP/USB31_7_TXP
B17
DMI3_RXN
G30
DMI1_RXP
F34
DMI1_TXN
C32
PCIE8_TXP
C24
RSVD1
U13
PCIE4_RXN/USB31_10_RXN
N18
RSVD
M29
DMI2_RXP
J32
PCIE1_RXN/USB31_7_RXN
G17
DMI2_TXN
C31
DMI0_TXP
B33
GPP_F15/USB2_OC4#
AV47
RSVD
M26
DMI3_RXP
F30
DMI3_TXN
C29
DMI1_TXP
B32
GPP_E11/USB2_OC2#
AJ44
RH7
10K_0402 _5%
@
12
www.laptoprepairsecrets.com
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
Trace Space: 15 mil
Max Trace Length: 1000 mil
XCLK_BIASREF (PDG)
Trace Width/Space: 15mil /15 mil
Max Trace Length: 1000 mil
8/24
#571483_CFL_H_RVP_CRB_TDK_Rev0p5
Recommend external test point
This signal has a weak internal pull-down 20K.
0 = 38.4/19.2MHz XTAL frequency selected.
1 = 24MHz XTAL frequency selected. (DDX03)
Notes:
1. The internal pull-down is disabled after RSMRST#
de-asserts.
2. This signal is in the primary well.
For DDX03 R02
The signal has a weak internal pull-down 20K
0 = VCCPSPI is connected to 3.3V rail
1 = VCCPSPI is connected to 1.8V rail
Note: If VCCPSPI is connected to 1.8V rail, this pin
strap must be a ‘ 1’ for the proper functionality
of the SPI (Flash) I/Os
1.8V
3.3V
STRAP
STRAP
STRAP
An external pull-up or pull-down is required.
0 = Integrated CNVi enable.
1 = Integrated CNVi disable.
XTAL Frequency Select
M.2 CNV Mode Select
PCH-H XTAL_IN/OUT POR is 24MHz for 571697_CNL_MOW_WW16_2017.pdf
571391_CFL_H_PDG_Rev0p71
To avoid floating input at the I/O pin BRI_RSP and RGI_RSP it is recommended to add
a weak pull up resistor to the SoC pin with a recommended value of 20K ohm.
Pulled down by CRF CNVi RGI_DT pin
VCCPSPI Select
DGPU
GLAN
NGFF WL+BT(KEY E)
remove CPU_C10_GATE#
M2 SSD1
remove no use srcclkreq
remove SD signal from PCH
remove TP as C5PRH
use same part w C5MMH
M2 SSD2
M2 SSD3
20190927
20191024
- CML Check list OK
20190918 SSD2&3 Change
20191209
> SSD1 - GPP_B9/CLKREQ4# (PCIE only) (2018 @SSD2)
> SSD2 - GPP_B8/CLKREQ3# (PCIE/SATA) (2018 @SSD1)
> SSD3 - GPP_B10/CLKREQ5# (PCIE/SATA) (2019 NEW)
20191210C
- RH22 change to 20K for CNVI review
20200114
- CH7/CH8 Chan ge to SE17310 0J80
PCH_CPU_ 24M_CLK_P
PCH_CPU_ 24M_CLK_N
PCH_CPU_ BCLK_N
PCH_CPU_ BCLK_P
XTAL_24M _PCH_OUT_R
XTAL_24M _PCH_IN_R
XTAL_24M_ PCH_OUT
PCH_RTCX1
PCH_RTCX2
PCH_RTCX2
PCH_RTCX1
XCLK_BIASR EF
PCIE_RCOMPN
PCIE_RCOMPP
SD_RCOMP_1 P8
SD_RCOMP_3 P3
GPPJ_RCOMP _1P8
CNV_WT_R COMP
CNV_BRI_PTX _DRX
GPP_J9
GPP_J9
VGA_CLKRE Q#
XTAL_24M_ PCH_IN
XTAL_24M_P CH_OUT_R
XTAL_24M_P CH_IN_R
CLK_CNV_P TX_DRX_N
CLK_CNV_P TX_DRX_P
CLK_CNV_PRX _DTX_N
CLK_CNV_PRX _DTX_P
CNV_PRX_D TX_N0
CNV_PRX_D TX_P0
CNV_PRX_D TX_N1
CNV_PRX_D TX_P1
CNV_PTX_D RX_N0
CNV_PTX_D RX_P0
CNV_PTX_D RX_N1
CNV_PTX_D RX_P1
CNV_BRI_P RX_DTX
CNV_RGI_PT X_DRX
CNV_RGI_PR X_DTX
CNV_BRI_P TX_DRX
LAN_CLK REQ#
WLAN_CLK REQ#
SSD2_CL KREQ#
SSD3_CL KREQ#
SSD1_CL KREQ#
I2C_TS_INT #
I2C_TS_RS T#
CNV_RGI_PTX _DRX
CNV_BRI_PRX _DTX
CNV_RGI_P RX_DTX
PCH_CPU_2 4M_CLK_P<10>
PCH_CPU_2 4M_CLK_N<10>
PCH_CPU_B CLK_P<10>
PCH_CPU_B CLK_N<10> PCH_CPU_PC IBCLK_P <10>
PCH_CPU_PC IBCLK_N <10>
LAN_CLK REQ#<73>
WLAN_CLKR EQ#<52>
CLK_CNV_P RX_DTX_N <52>
CLK_CNV_P RX_DTX_P <52>
CNV_PRX_DT X_N0 <52>
CNV_PRX_DT X_P0 <52>
CNV_PRX_DT X_N1 <52>
CNV_PRX_DT X_P1 <52>
CLK_CNV_PTX _DRX_N <52>
CLK_CNV_PTX _DRX_P <52>
CNV_PTX_D RX_N0 <52>
CNV_PTX_D RX_P0 <52>
CNV_PTX_D RX_N1 <52>
CNV_PTX_D RX_P1 <52>
REFCLK_C NV <5 2>
CNV_BRI_PRX _DTX<52>
CNV_RGI_P TX_DRX<52>
CNV_RGI_PRX _DTX<52>
CNV_BRI_P TX_DRX<52>
SSD2_CLKRE Q#<68>
CLK_PEG_VGA <27>
CLK_PEG_VGA# <27>
CLK_PCIE_L AN <73>
CLK_PCIE_L AN# <7 3>
CLK_PCIE_W LAN# <52>
CLK_PCIE_WL AN <52>
CLK_PCIE_NGF F1 <68>
CLK_PCIE_NGF F1# <68>
VGA_CLKR EQ# <27>
CLK_PCIE_NGF F2 <69>
CLK_PCIE_NGF F2# <69>
CLK_PCIE_NGF F3 <68>
CLK_PCIE_NGF F3# <68>
SSD3_CLKRE Q#<69>
SSD1_CLKRE Q#<68>
I2C_TS_INT#<38>
I2C_TS_RST#<38>
+1.8VALW_PR IM
+1.8VALW_PR IM
+3VS
+1.8VALW_PR IM
+1.8VALW_PR IM
Title
Size Document Number R e v
Date: Sheet o f
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEE RING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET IN FORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AU THORIZED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHEET NOR THE INFORMA TION IT CONTAINS
MAY BE USED BY OR DISC LOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELEC TRONICS, INC.
Issued Date
Deciphered Date
FH51M M/B LA-J871P
1.0
PCH(2/8)CLK/CNVI/SD
Custom
15 112Tue sday, February 11, 2020
2019/09/20 2020/09/20
Compal Electronics, Inc.
Title
Size Document Number R e v
Date: Sheet o f
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEE RING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET IN FORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AU THORIZED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHEET NOR THE INFORMA TION IT CONTAINS
MAY BE USED BY OR DISC LOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELEC TRONICS, INC.
Issued Date
Deciphered Date
FH51M M/B LA-J871P
1.0
PCH(2/8)CLK/CNVI/SD
Custom
15 112Tue sday, February 11, 2020
2019/09/20 2020/09/20
Compal Electronics, Inc.
Title
Size Document Number R e v
Date: Sheet o f
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEE RING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET IN FORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AU THORIZED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHEET NOR THE INFORMA TION IT CONTAINS
MAY BE USED BY OR DISC LOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELEC TRONICS, INC.
Issued Date
Deciphered Date
FH51M M/B LA-J871P
1.0
PCH(2/8)CLK/CNVI/SD
Custom
15 112Tue sday, February 11, 2020
2019/09/20 2020/09/20
Compal Electronics, Inc.
C
H
5
3
3
P
_
0
4
0
2
_
5
0
V
8
J
RH300 10K_040 2_5%
1 2
C
H
6
1
8
P
_
0
4
0
2
_
5
0
V
8
J
C
H
8
1
0
P
_
0
2
0
1
_
5
0
V
8
J
1
2
RH220 10K_040 2_5%
1 2
7 OF 13
CNP-H
Rev1.0
UH1G
CNP-H_BGA8 74
@
CLKOUT_CPUNSSC_P
D7
CLKOUT_CPUBCLK_P
B8
XTAL_OUT
U9
XTAL_IN
U10
XCLK_BIASREF
T3
RTCX1
BA49
RTCX2
BA48
CLKOUT_ITPXDP_P
Y4
CLKOUT_CPUPCIBCLK_P
A6
CLKOUT_CPUBCLK#
C8
CLKOUT_CPUNSSC#
C6
CLKOUT_CPUPCIBCLK#
B6
CLKOUT_ITPXDP#
Y3
CLKOUT_PCIE_P15
V3
GPP_B10/SRCCLKREQ5#
AN29
GPP_H0/SRCCLKREQ6#
AE47
GPP_B6/SRCCLKREQ1#
BE31
CLKOUT_PCIE_P0
AJ7
CLKOUT_PCIE_P1
AH10
CLKOUT_PCIE_N0
AJ6
CLKOUT_PCIE_P2
AE15
CLKOUT_PCIE_N1
AH9
CLKOUT_PCIE_P3
AE7
GPP_B7/SRCCLKREQ2#
AR32
CLKOUT_PCIE_N2
AE14
GPP_H1/SRCCLKREQ7#
AC48
CLKOUT_PCIE_P4
AC3
CLKIN_XTAL
R6
CLKOUT_PCIE_N3
AE6
CLKOUT_PCIE_P5
AB3
CLKOUT_PCIE_P6
W3
CLKOUT_PCIE_N4
AC2
CLKOUT_PCIE_P7
W6
GPP_H9/SRCCLKREQ15#
AC43
CLKOUT_PCIE_N5
AB2
CLKOUT_PCIE_N6
W4
GPP_H6/SRCCLKREQ12#
AE39
CLKOUT_PCIE_N10
AC9
GPP_H8/SRCCLKREQ14#
AC44
GPP_H5/SRCCLKREQ11#
AC39
CLKOUT_PCIE_P8
AC15
GPP_H7/SRCCLKREQ13#
AB48
CLKOUT_PCIE_N7
W7
CLKOUT_PCIE_P9
U3
GPP_B8/SRCCLKREQ3#
BB30
CLKOUT_PCIE_N11
AE9
GPP_H2/SRCCLKREQ8#
AE41
GPP_H4/SRCCLKREQ10#
AC41
GPP_A16/CLKOUT_48
BE33
CLKOUT_PCIE_N12
AC7
CLKOUT_PCIE_N8
AC14
CLKOUT_PCIE_P10
AC11
CLKOUT_PCIE_N9
U2
CLKOUT_PCIE_P11
AE11
CLKOUT_PCIE_N13
AA1
CLKOUT_PCIE_N14
T2
GPP_B5/SRCCLKREQ0#
BF31
CLKOUT_PCIE_P12
AC6
CLKOUT_PCIE_P13
Y2
CLKOUT_PCIE_N15
V2
GPP_H3/SRCCLKREQ9#
AF48
CLKOUT_PCIE_P14
T1
GPP_B9/SRCCLKREQ4#
BA30
RH10 60.4_0402 _1%
1 2
RH20 200_0402_ 1%
1 2
RH181 20K_040 2_1%CNVI@
1 2
RH9 33_0 402_1%
EMI@
1 2
RH17 100_0402_ 1%
1 2
RH182 20K_040 2_1%CNVI@
1 2
RH23 10K_0402_5%@
12
RH11 33_0 402_1%
EMI@
1 2
TH2@
RH12 10M_0402_5%
1 2
RH22 20K_0402_1%
1 2
RH16
150_0402_ 1%
1 2
RH15 4.7K_040 2_5%
1 2
RH14
10K_040 2_5%
12
RH19 200_0402 _1%
1 2
YH1
24MHZ_18P F_7R24000001
NC
2
3
3
1
1
NC
4
C
H
7
1
0
P
_
0
2
0
1
_
5
0
V
8
J
1
2
TH3@
YH2
32.768KHZ_ 9PF_X1A000141000 200
1 2
13 OF 13
CNP-H
Rev1.0
UH1M
CNP-H_BGA87 4
@
GPP_J_2
AW3
GPP_J_3
AT10
GPP_J4/CNV_BRI_DT/UART0B_RTS#
AV4
CNV_WR_CLKN
BD4
CNV_WR_CLKP
BE3
CNV_WR_D0N
BB3
CNV_WR_D0P
BB4
CNV_WR_D1N
BA3
CNV_WR_D1P
BA2
CNV_WT_CLKN
BC5
CNV_WT_CLKP
BB6
CNV_WT_D0N
BE6
CNV_WT_D0P
BD7
CNV_WT_D1N
BG6
CNV_WT_D1P
BF6
CNV_WT_RCOMP
BA1
GPPJ_RCOMP_1P81
BD1
GPPJ_RCOMP_1P82
BE1
GPPJ_RCOMP_1P83
BE2
GPP_J0/CNV_PA_BLANKING
AV6
GPP_I11/M2_SKT2_CFG0
AP3
GPP_G1/SD_DATA0
BE9
GPP_G7/SD_WP
AV13
GPP_G5/SD_CD#
BE8
GPP_I12/M2_SKT2_CFG1
AP2
GPP_G2/SD_DATA1
BF8
PCIE_RCOMPN
B12
GPP_G3/SD_DATA2
BF9
GPP_J9/CNV_MFUART2_TXD
AU9
GPP_I13/M2_SKT2_CFG2
AN4
GPP_I14/M2_SKT2_CFG3
AM7
PCIE_RCOMPP
A13
GPP_G4/SD_DATA3
BG8
GPP_G6/SD_CLK
BD8
GPP_J1/CPU_C10_GATE#
AY3
GPP_J7/CNV_RGI_RSP/UART0B_CTS#
AV3
GPP_J8/CNV_MFUART2_RXD
AW2
GPP_J10
AV7
SD_3P3_RCOMP
BE4
RSVD3
Y36
GPP_J5/CNV_BRI_RSP/UART0B_RXD
AY2
GPP_J6/CNV_RGI_DT/UART0B_TXD
BA4
TP
AL35
RSVD2
Y35
SD_1P8_RCOMP
BE5
GPP_J11/A4WP_PRESENT
AR13
RSVD1
BC1
GPP_G0/SD_CMD
AW13
RH205 10K_040 2_5%
1 2
RH18 200_0402_1 %
1 2
RH204 10K_040 2_5%
1 2
RH8 1M_0402_5%
1 2
TH4@
RH206 10K_040 2_5%
1 2
RH21 4.7K_040 2_5%
@
1 2
RH207 10K_040 2_5%
1 2
www.laptoprepairsecrets.com
A
A
1 1
RVP: 330K
A 1 M pull-up is used on the customer reference
board (CRB). This is needed to reduce leakage
from Coin Cell Battery in G3 state.
GPIO Serial Expander (GSX) is the capability
provided by the PCH to expand the GPIOs
on a platform that needs more GPIOs than the
ones provided by the PCH.
DDP[B..F]CTRLDATA
This signal has a weak internal Pull-down.
0 = Port B~D is not detected.
1 = Port B,C,D is detected. (Default)
Notes:
1. The internal Pull-down is disabled after
PCH_PWROK de-asserts.
2. This signal is in the primary well.
#571182_CNL_PCH_H_EDS_V1_Rev0.7
External pull-up is required. Recommend 100K if pulled
up to 3.3V or 75K if pulled up to 1.8V.
571007_CFL_MOW_Archive_WW22_2017
STUFF R on GPP_H15
#571391_CFL_H_PDG_Rev0p71
STRAP
SPI ROM ( 16MByte )
XMC P/N: SA0000B8400
can remove if no use DP
08/18
CRB connect GND
no follow naming
remove CIO_PLUG_EVENT#
remove PCH DP SCLK/SDATA
#571182_CFL_PC H_EDS_Rev1.0 recommend 1 00k
CRB PU 20k
PDG P348 quad mode support PH1K
* wait confirm CG7
intel critical net recommend
intel critical net recommend
PCH PLTRST Buffer
20191016
- BT_ON For Intel (GPP_B3)
- TP_INT# change to GPP_B4
*20191024
- CML RVP PU 330K
20191206
- RH304 pop
SM_INTRUDER#
PCH_SPI_SI_R
GPP_H15
GPP_H15
GPP_H12
PLT_RST#
PCH_SPI_C S#0
PCH_SPI_CLK _0_R
PCH_SPI_CS #0
PCH_SPI_SI_0_ R
PCH_SPI_IO3_0_ RPCH_SPI_SO_ 0_R
PCH_SPI_IO2_0 _R
PCH_SPI_CLK_ 0_R
PCH_SPI_CS# 0
PCH_SPI_IO2
PCH_SPI_IO3
PCH_SPI_CLK
PCH_SPI_SI
PCH_SPI_SO
EC_PME#_R PLT_RST #
PCH_SPI_IO3
PCH_SPI_IO2
PCH_SPI_IO2PCH_SPI_IO2_0 _R
PCH_SPI_SI_0_ R
PCH_SPI_SO_ 0_R
PCH_SPI_IO3_0 _R
PCH_SPI_C LK_0_R
PCH_SPI_SI_R
PCH_SPI_SO _R
PCH_SPI_IO3
PCH_SPI_C LK_R
PCH_SPI_CLK _R
PLT_RST#
PCH_SPI_SO_ 0_R
PCH_SPI_IO2 _0_R
PCH_SPI_SI_0_ R
PCH_SPI_CLK _0_R
PCH_SPI_IO3 _0_R
PCH_SPI_CS# 0
TP_INT# EC_TP_INT#
BT_ON
GPP_B3
TP_INT#
GPP_B3
GPP_H12 <19 >
EC_PME#<58,73> PLT_RST# < 27,58,66>
EDP_HPD<38>
HDMI_HPD _PCH<27,40>
PCH_SPI_CS#2<66>
PCH_SPI_SI_R<66>
PCH_SPI_SO_ R<66>
PCH_SPI_CL K_R<66>
PLT_RST_B UF# <52,68,69,73>
DP0_HPD_P CH<27,39>
EC_TP_INT# <58,63>
BT_ON <52,5 8>
+RTCVCC
+3VALW
+3VALW
+3VALW
+3VALW
+3VS
+3VALW
+3VS
Title
Size Document Number R e v
Date: Sheet o f
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEE RING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET IN FORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AU THORIZED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHEET NOR THE INFORMA TION IT CONTAINS
MAY BE USED BY OR DISC LOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELEC TRONICS, INC.
Issued Date
Deciphered Date
FH51M M/B LA-J871P
1.0
PCH(3/8)DDC/SPI
Custom
16 11 2Tuesday, Feb ruary 11, 2020
2019/09/20 2020/09/20
Compal Electronics, Inc.
Title
Size Document Number R e v
Date: Sheet o f
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEE RING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET IN FORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AU THORIZED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHEET NOR THE INFORMA TION IT CONTAINS
MAY BE USED BY OR DISC LOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELEC TRONICS, INC.
Issued Date
Deciphered Date
FH51M M/B LA-J871P
1.0
PCH(3/8)DDC/SPI
Custom
16 11 2Tuesday, Feb ruary 11, 2020
2019/09/20 2020/09/20
Compal Electronics, Inc.
Title
Size Document Number R e v
Date: Sheet o f
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEE RING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET IN FORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AU THORIZED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHEET NOR THE INFORMA TION IT CONTAINS
MAY BE USED BY OR DISC LOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELEC TRONICS, INC.
Issued Date
Deciphered Date
FH51M M/B LA-J871P
1.0
PCH(3/8)DDC/SPI
Custom
16 11 2Tuesday, Feb ruary 11, 2020
2019/09/20 2020/09/20
Compal Electronics, Inc.
CH12
68P_0402 _50V8J
XEMI@
1 2
RH195 100K_020 1_5%@
1 2
RH26 1K_0 402_5%
12
RH259 0_0402 _5%NTPM@
1 2
CH10 0.1U_0201_10V6K
1 2
RH258 0_0402 _5%NTPM@
1 2
RH28 100K_04 02_5%
12
RH304 0_040 2_5%
1 2
RH107 33_04 02_1%
1 2
RH24 0_0 402_5%
@
1 2
RH198 100K_020 1_5%
1 2
RH260 0_0402 _5%NTPM@
1 2
UH2
W25Q128FVS IQ_SO8
/CS
1
DO(IO1)
2
/WP(IO2)
3
GND
4
DI(IO0)
5
CLK
6
/HOLD(IO3)
7
VCC
8
RH108 33_04 02_1%
1 2
TH6 @
RH186 0_0402_ 5%@
1 2
RH27 1K_0 402_5%
12
RH109 33_04 02_1%
1 2
JC1
ACES_9196 0-0084N_MX25L3206 EM2I
CONN@
CS#
1
SO/SIO1
2
WP#
3
GND
4
VCC
8
HOLD#
7
SCLK
6
SI/SIO0
5
RH29 100K_040 2_5%
12
CH11
0.1U_0201 _10V6K
1 2
1 OF 13
CNP-H
Rev1.0
UH1A
CNP-H_BGA87 4
@
SPI0_CLK
AW47
GPP_D22/SPI1_IO3
BC17
SPI0_MISO
BA45
SPI0_MOSI
AU41
VSS
AL37
GPP_K14/GSXDIN
W46
GPP_D2/SPI1_MISO/SBK2_BK2
BE18
GPP_E3/CPU_GP0
AL47
GPP_H16/SML4CLK
AE43
GPP_B4/CPU_GP3
BC33
GPP_K16/GSXCLK
Y47
GPP_B3/CPU_GP2
BF32
GPP_E7/CPU_GP1
AM45
GPP_H17/SML4DATA
AJ46
SPI0_IO2
AY48
GPP_B13/PLTRST#
AV29
GPP_H14/SML3DATA
AD48
SPI0_IO3
BA46
SPI0_CS2#
AT40
GPP_H10/SML2CLK
AE48
GPP_H11/SML2DATA
AD47
SPI0_CS1#
AW48
GPP_K12/GSXDOUT
Y46
GPP_D21/SPI1_IO2
BD17
SPI0_CS0#
AY47
GPP_H18/SML4ALERT#
AE44
GPP_D0/SPI1_CS#/SBK0_BK0
BF19
GPP_D1/SPI1_CLK/SBK1_BK1
BE19
TP
AN35
RSVD2
R15
GPP_H15/SML3ALERT#
AC47
GPP_K15/GSXSRESET#
AA45
GPP_K13/GSXSLOAD
Y48
RSVD1
R13
GPP_H13/SML3CLK
AF47
GPP_D3/SPI1_MOSI/SBK3_BK3
BF18
GPP_H12/SML2ALERT#
AB47
GPP_A11/PME#/SD_VDD2_PWR_EN#
BE36
INTRUDER#
BB44
RH110 33_04 02_1%
1 2
DH1
RB751V-40_S OD323-2
12
RH305 100K_04 02_5%@
12
RH32 0_0402_5 %@
1 2
5 OF 13
CNP-H
Rev1.0
UH1E
CNP-H_BGA87 4
@
GPP_K22/IMGCLKOUT0
L48
GPP_F14/PS_ON#
AP41
GPP_F22/DDPF_CTRLCLK
AT49
GPP_I1/DDPC_HPD1/DISP_MISC1
AN10
GPP_I10/DDPD_CTRLDATA
AR3
GPP_K23/IMGCLKOUT1
M45
GPP_I6/DDPB_CTRLDATA
AR8
GPP_I2/DDPD_HPD2/DISP_MISC2
AP9
GPP_I9/DDPD_CTRLCLK
AL9
GPP_I0/DDPB_HPD0/DISP_MISC0
AT6
GPP_I4/EDP_HPD/DISP_MISC4
AN6
GPP_F23/DDPF_CTRLDATA
AN40
GPP_I7/DDPC_CTRLCLK
AN13
GPP_K20
T46
GPP_I8/DDPC_CTRLDATA
AL10
GPP_K21
T45
GPP_I5/DDPB_CTRLCLK
AL13
GPP_H23/TIME_SYNC0
AJ47
GPP_I3/DDPF_HPD3/DISP_MISC3
AL15
RH111 33_04 02_1%
1 2
RH33
0_0402_5%
XEMI@
1 2
RH199
100K_020 1_5%
@
12
RH258
4.99_0402_1%
TPM@
SD034499B80
RH301M_0402_5 %
12
RH25 1K_0 402_5%
12
UH3
MC74VHC1 G08DFT2G_SC70-5
IN1
1
IN2
2
OUT
4
VCC
5
GND
3
RH31 4.7K _0402_5%
@
1 2
RH259
4.99_0402_1%
TPM@
SD034499B80
CH9 100 P_0402_50V8J
XESD@
1 2
RH260
4.99_0402_1%
TPM@
SD034499B80
www.laptoprepairsecrets.com
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
For Intel CLINK
#571391_CFL_H_PDG_Rev0p5
eSPI clock and eSPI data mismatched: <500 mils.
‧
eSPI clock and eSPI chip select mismatched: <500 mils.
‧
eSPI signal maximum 9 Vias
‧
* If DATA signals are entirely routed on MS, stuff the resistor with 15 Ohm.
#571391_CFL_H_PDG_Rev0p5.pdf
1.8V
(eSPI)
LPC Bus
LPC : +3.3V
check straps
DGPU_PRSNT#
UMA
DIS,Optimus10
GPP_F13
USB3 MB
NGFF
WL+BT(KEY E)
M.2 SSD2 PCIE L0
M.2 SSD2 PCIE L1
M.2 SSD2 PCIE L2
M.2 SSD2 PCIE L3
GLAN
20190924
20190918 Port4 change to Port3
M.2 SSD PCIE/SATA select pin
20190918
20190918
USB3 IO/B
USB3 IO/B
USB3 Type C
20191016
USB3 Type C
20191016
HDD
20191016
- HDD change to Port 0B
20191025
- SATA Port 4
20191206
- JSSD3 detect pin change to SATA_GP4
M.2 SSD3 PCIE L3
M.2 SSD3 PCIE L2
M.2 SSD3 PCIE L1
M.2 SSD3 PCIE L0
CL_CLK
CL_DATA
CL_RST#
H_PECI
H_PM_DOWN_ R
H_PM_SYNC _R
ENBKL
PCH_BKL_PW M
PCH_ENVD D
PCH_PECI
H_PLTRST_C PU#
H_PM_SYNC
SATA_GP5
PCH_THERM TRIP#
TPM_SERIRQ
LPC_PIRQA#
LPC_AD2
LPC_AD0
LPC_AD3
LPC_AD1
CLK_LPC
ESPI_RST#
TPM_SERIRQ
LPC_FRAM E#
LPC_PIRQA#
DGPU_PRSNT #
DGPU_PRSNT #
PCIE_PRX_DT X_P15
PCIE_PRX_DT X_N15
PCIE_PTX_DR X_N15
PCIE_PTX_DR X_P15
H_PECI
PCIE_PRX_DT X_N9
PCIE_PRX_DT X_P9
PCIE_PTX_DR X_N9
PCIE_PTX_DR X_P9
PCIE_PRX_DT X_N10
PCIE_PRX_DT X_P10
PCIE_PTX_DR X_P10
PCIE_PTX_DR X_N10
SATA_GP1
SSD_DEVSLP 1
RCIN#
RCIN#
PCIE_PRX_ DTX_P14
PCIE_PRX_ DTX_N14
PCIE_PTX_ DRX_N14
PCIE_PTX_ DRX_P14
USB3_PTX _DRX_P4
USB3_PTX _DRX_N4
USB3_PRX _DTX_P4
USB3_PRX _DTX_N4
PCIE_PRX_DT X_N17
PCIE_PRX_DT X_P17
PCIE_PTX_DR X_P17
PCIE_PTX_DR X_N17
PCIE_PRX_DT X_N18
PCIE_PRX_DT X_P18
PCIE_PTX_DR X_P18
PCIE_PTX_DR X_N18
PCIE_PRX_DTX _N19
PCIE_PRX_DTX _P19
PCIE_PTX_D RX_N19
PCIE_PTX_D RX_P19
SATA_GP1
PCIE_PRX_DTX _N20
PCIE_PRX_DTX _P20
PCIE_PTX_D RX_N20
PCIE_PTX_D RX_P20
SATA_GP2
SATA_GP4
USB3_PTX _DRX_P5
USB3_PRX _DTX_P5
USB3_PTX _DRX_N5
USB3_PRX _DTX_N5
SATA_PTX_ DRX_N0B
SATA_PTX_ DRX_P0B
SATA_PRX_D TX_N0B
SATA_PRX_D TX_P0B
SSD_DEVSLP 4
SATA_GP4
H_PLTRST _CPU# <10>
H_PECI <10,58>
H_PM_DOW N_R <10>
H_PM_SYNC _R < 10>
PCH_THERM TRIP#_R <10>
ENBKL <58>
PCH_BKL_ PWM <38>
PCH_ENVDD <38>
USB3_PRX_D TX_P2<73>
USB3_PRX_D TX_N2<73>
USB3_PTX_D RX_N2<73>
USB3_PTX_D RX_P2<73>
LPC_AD3 <58>
LPC_AD0 <58>
LPC_AD2 <58>
LPC_AD1 <58>
CLK_LPC_R <58>
LPC_FRAM E# <58>
TPM_SERIRQ <58,66>
PCIE_PRX_DTX_N15 <52>
PCIE_PRX_DTX_P15 <52>
PCIE_PTX_C_D RX_N15 <52>
PCIE_PTX_C_ DRX_P15 <52>
USB3_PRX_D TX_N3<43>
USB3_PRX_D TX_P3<43>
USB3_PTX_D RX_N3<43>
USB3_PTX_D RX_P3<43>
USB3_PRX_D TX_N1<71>
USB3_PRX_D TX_P1<71>
USB3_PTX_D RX_N1<71>
USB3_PTX_D RX_P1<71>
PCIE_PRX_D TX_N9 <68>
PCIE_PRX_D TX_P9 <68>
PCIE_PTX_DR X_P9 <68>
PCIE_PTX_D RX_N9 <68>
PCIE_PTX_DR X_P10 <68>
PCIE_PRX_D TX_N10 <68>
PCIE_PRX_D TX_P10 <68>
PCIE_PTX_D RX_N10 <68>
PCIE_PTX_D RX_P12<68>
PCIE_PTX_D RX_N12<68>
PCIE_PRX_D TX_P12<68>
PCIE_PRX_DT X_N12<68>
PCIE_PTX_D RX_N11<68>
PCIE_PTX_D RX_P11<68>
PCIE_PRX_D TX_P11<68>
PCIE_PRX_DT X_N11<68>
SATA_GP1 <6 8>
SSD_DEVSL P1 <68>
OVRM_EN <3 6,58>
PCIE_PRX_DTX_N14<73>
PCIE_PRX_DTX_P14<73>
PCIE_PTX_DR X_N14<73>
PCIE_PTX_DR X_P14<73>
USB3_PRX_D TX_N4<43>
USB3_PRX_D TX_P4<43>
USB3_PTX_D RX_N4<43>
USB3_PTX_D RX_P4<43>
PCIE_PTX_DR X_P17 <69>
PCIE_PRX_D TX_N17 <69>
PCIE_PRX_D TX_P17 <69>
PCIE_PTX_D RX_N17 <69>
PCIE_PTX_DR X_P18 <69>
PCIE_PRX_D TX_N18 <69>
PCIE_PRX_D TX_P18 <69>
PCIE_PTX_D RX_N18 <69>
PCIE_PTX_ DRX_P19<69>
PCIE_PTX_ DRX_N19<69>
PCIE_PRX_D TX_P19<69>
PCIE_PRX_DT X_N19<69>
PCIE_PTX_ DRX_P20<69>
PCIE_PTX_ DRX_N20<69>
PCIE_PRX_D TX_P20<69>
PCIE_PRX_DT X_N20<69>
USB3_PRX_D TX_P5<73>
USB3_PTX_D RX_P5<73>
USB3_PTX_D RX_N5<73>
USB3_PRX_D TX_N5<73>
SATA_PTX_D RX_P0B<67>
SATA_PTX_D RX_N0B<67>
SATA_PRX_D TX_N0B< 67>
SATA_PRX_ DTX_P0B<67>
SSD_DEVSL P4 <69>
SATA_GP4 <6 9>
+3VS
+3VALW
+3VS
+3VS
Title
Size Document Number R e v
Date: Sheet o f
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEE RING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET IN FORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AU THORIZED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHEET NOR THE INFORMA TION IT CONTAINS
MAY BE USED BY OR DISC LOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELEC TRONICS, INC.
Issued Date
Deciphered Date
FH51M M/B LA-J871P
1.0
PCIE/SATA/USB3/eSPI
Custom
17 112Tue sday, February 11, 2020
2019/09/20 2020/09/20
Compal Electronics, Inc.
Title
Size Document Number R e v
Date: Sheet o f
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEE RING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET IN FORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AU THORIZED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHEET NOR THE INFORMA TION IT CONTAINS
MAY BE USED BY OR DISC LOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELEC TRONICS, INC.
Issued Date
Deciphered Date
FH51M M/B LA-J871P
1.0
PCIE/SATA/USB3/eSPI
Custom
17 112Tue sday, February 11, 2020
2019/09/20 2020/09/20
Compal Electronics, Inc.
Title
Size Document Number R e v
Date: Sheet o f
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEE RING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET IN FORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AU THORIZED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHEET NOR THE INFORMA TION IT CONTAINS
MAY BE USED BY OR DISC LOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELEC TRONICS, INC.
Issued Date
Deciphered Date
FH51M M/B LA-J871P
1.0
PCIE/SATA/USB3/eSPI
Custom
17 112Tue sday, February 11, 2020
2019/09/20 2020/09/20
Compal Electronics, Inc.
TH10 @
RH43
10K_040 2_5%
UMA@
12
CH1.1U_0402_16 V7K
1 2
RH44
10K_040 2_5%
VGA@
12
TH12 @
RH42 30_0402_5 %
1 2
3 OF 13
CNP-H
Rev1.0
UH1C
CNP-H_BGA87 4
@
PCIE_15_SATA_2_TXN
B40
PECI
AF2
PM_SYNC
AF3
PM_DOWN
AE2
GPP_K3
U47
PCIE12_RXN/SATA1A_RXN
H42
PCIE20_TXP/SATA7_TXP
B44
PCIE16_TXN/SATA3_TXN
B41
GPP_K4
N48
PCIE13_RXP/SATA0B_RXP
C46
PCIE17_TXP/SATA4_TXP
B42
PCIE11_TXN/SATA0A_TXN
B36
GPP_F19/EDP_VDDEN
AV44
CL_RST#
AU4
GPP_K5
N47
PCIE19_TXP/SATA6_TXP
D43
PCIE18_TXN/SATA5_TXN
C42
GPP_E2/SATAXPCIE2/SATAGP2
AK47
GPP_E0/SATAXPCIE0/SATAGP0
AH41
GPP_K6
P47
PCIE15_RXP/SATA2_RXP
E45
PCIE14_RXP/SATA1B_RXP
C47
GPP_K7
R46
PCIE20_RXP/SATA7_RXP
R37
PCIE16_RXN/SATA3_RXN
L41
PCIE17_RXP/SATA4_RXP
K44
PCIE12_TXN/SATA1A_TXN
D38
PCIE13_TXP/SATA0B_TXP
C38
GPP_F12/SATA_SDATAOUT1
AU46
THRMTRIP#
AD3
GPP_K8
P48
GPP_F10/SATA_SCLOCK
AR42
GPP_K9
V47
PCIE18_RXN/SATA5_RXN
P41
PCIE19_RXP/SATA6_RXP
N42
PCIE10_RXN
K37
PCIE13_RXN/SATA0B_RXN
C45
GPP_F21/EDP_BKLTCTL
AU48
PCIE14_TXP/SATA1B_TXP
D39
GPP_F13/SATA_SDATAOUT0
AU47
GPP_F2/SATAXPCIE5/SATAGP5
AM43
PLTRST_CPU#
AG5
PCIE10_RXP
J37
PCIE16_TXP/SATA3_TXP
C41
PCIE10_TXN
C35
GPP_F4/SATAXPCIE7/SATAGP7
AM48
PCIE11_RXP/SATA0A_RXP
F39
PCIE14_RXN/SATA1B_RXN
D46
PCIE13_TXN/SATA0B_TXN
B38
GPP_F11/SATA_SLOAD
AR48
PCIE20_TXN/SATA7_TXN
A44
PCIE18_TXP/SATA5_TXP
D42
PCIE10_TXP
B35
GPP_F20/EDP_BKLTEN
AV46
CL_DATA
AT5
GPP_E8/SATA_LED#
AK48
GPP_E1/SATAXPCIE1/SATAGP1
AJ43
PCIE17_TXN/SATA4_TXN
A42
GPP_K10
V48
PCIE9_RXN
G36
PCIE19_TXN/SATA6_TXN
C44
GPP_K11
W47
PCIE16_RXP/SATA3_RXP
M40
PCIE15_RXN/SATA2_RXN
F44
PCIE14_TXN/SATA1B_TXN
C39
PCIE11_TXP/SATA0A_TXP
C36
PCIE20_RXN/SATA7_RXN
R35
PCIE17_RXN/SATA4_RXN
K43
PCIE12_RXP/SATA_1A_RXP
J41
PCIE9_RXP
F36
PCIE9_TXN
C34
PCIE18_RXP/SATA5_RXP
R40
GPP_K0
L47
PCIE11_RXN/SATA0A_RXN
G38
CL_CLK
AR2
GPP_F0/SATAXPCIE3/SATAGP_3
AN47
PCIE19_RXN/SATA6_RXN
M44
GPP_K1
L46
PCIE12_TXP/SATA1A_TXP
E37
PCIE9_TXP
D34
GPP_K2
U48
PCIE15_TXP/SATA2_TXP
C40
GPP_F3/SATAXPCIE6/SATAGP6
AM47
GPP_F1/SATAXPCIE4/SATAGP4
AM46
6 OF 13
CNP-H
Rev1.0
UH1F
CNP-H_BGA87 4
@
USB31_1_TXN
F9
USB31_1_TXP
F7
USB31_1_RXN
D11
USB31_1_RXP
C11
USB31_2_TXN
C3
USB31_2_TXP
D4
USB31_2_RXN
B9
USB31_2_RXP
C9
USB31_6_TXN
C17
USB31_6_TXP
C16
USB31_6_RXN
G14
USB31_6_RXP
F14
USB31_5_TXN
C15
USB31_5_TXP
B15
USB31_5_RXN
J13
USB31_5_RXP
K13
USB31_3_TXP
G12
USB31_3_TXN
F11
USB31_3_RXP
C10
USB31_3_RXN
B10
USB31_4_TXP
C14
USB31_4_TXN
B14
USB31_4_RXP
J15
USB31_4_RXN
K16
GPP_A1/LAD0/ESPI_IO0
BB39
GPP_K18/NMI#
T47
GPP_A6/SERIRQ/ESPI_CS1#
AW35
GPP_A14/SUS_STAT#/ESPI_RESET#
BF38
GPP_F5/SATA_DEVSLP3
AP48
GPP_A4/LAD3/ESPI_IO3
BA38
GPP_F6/SATA_DEVSLP4
AR47
GPP_A9/CLKOUT_LPC0/ESPI_CLK
BB36
GPP_F7/SATA_DEVSLP5
AN46
GPP_A3/LAD2/ESPI_IO2
AV37
GPP_A5/LFRAME#/ESPI_CS0#
BE38
GPP_F8/SATA_DEVSLP6
AN37
GPP_E4/SATA_DEVSLP0
AL48
GPP_A10/CLKOUT_LPC1
BB34
GPP_E5/SATA_DEVSLP1
AH35
GPP_A0/RCIN#/ESPI_ALERT1#
BE39
GPP_A7/PIRQA#/ESPI_ALERT0#
BA36
GPP_A2/LAD1/ESPI_IO1
AW37
GPP_F9/SATA_DEVSLP7
AP47
GPP_K19/SMI#
T48
GPP_E6/SATA_DEVSLP2
AH40
RH37
10K_0402_ 5%
12
RH40 620_040 2_5%
1 2
RH35 22_0402_5 %
12
TH13
@
RH219
10K_0402_ 5%
12
RH38
10K_0402_ 5%
1 2
RH41 13_0402 _5%@
1 2
RH187 10K_0402_5%PBA@
1 2
TH50
@
RH261 0_040 2_5%@
1 2
RH39 10K_0402_ 5%
12
CH500.1U_0201_1 0V6K
XESD@
1 2
TH11 @
CH2.1U_0402_16V 7K
1 2
RH303 10K_040 2_5%
12
www.laptoprepairsecrets.com
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
CLR ME
Delay 18~25 ms
ECLR CMOS
Delay 18~25 ms
Connect CPU & PCH
--No Support Deep Sx
FOR Jefferson Peak RESET pin is glitch free,it
is recommended that a pull-down resistor of 75K
ohm on GPP_D5(CNV_RF_RESET#)
From ESD Team Request
Near PCH side
1.8V
(EC,VGA,Thermal Sensor)
del RF reserve cap on HDA
intel critical net recommend
intel critical net recommend
(DDR,G-Sensor)
UART BT (20191014)
- RH301 change to 100K
HDA_BIT_CL K
HDA_RST#
HDA_SDIN0
HDA_SDOUT
HDA_SYNC
CPU_DISPA_SD O
CPU_DISPA_SD I_R
CPU_DISPA_BC LK
PCH_SRTCR ST#
PCH_RTCRS T#
PCH_SRTCRS T#
SLP_WLAN#
LAN_DISABL E_N
WAKE#
DRAM_RESET #
DRAM_RESE T#
PCH_VRALE RT#
SYS_PWROK
PCH_GPP_K 17
PCH_GPP_B 11
PM_SLP_A#
SLP_LAN#
PM_SLP_S5#
PM_SLP_S4#
PM_SLP_S3#
PM_SLP_S0#
SUSCLK
PM_BATLOW#
PM_BATLOW #
SUSACK#_ R
PM_CLKRUN #
PM_CLKRU N#
LAN_WAKE#
SLP_SUS#
AC_PRESEN T_R
PBTN_OUT# _R
SYS_RESET#
H_CPUPWRGD
PCH_SPKR
PCH_PWROK
EC_RSMRST #
PCH_DPWROK
PCH_DPWRO K
PCH_DPWROK
PCH_SML0A LERT#
PCH_SML0CLK
PCH_SML0DA TA
PCH_SML1A LERT#
PCH_SML1CLK
PCH_SML1DA TA
PCH_SMBAL ERT#
XDP_ITP_PMO DE
CPU_XDP_T CK0
CPU_XDP_T MS
CPU_XDP_T DI
CPU_XDP_T DO
SYS_RESET #
SYS_PWROK
PCH_PWROK
PCH_SMBCLK
PCH_SMBDAT A
PCH_SMBC LK
PCH_SMBD ATA
WAKE#
PCH_RTCRS T#
EC_RSMRST#
PCH_VRALE RT#
TYPEC_3A
PCH_SML0 CLK
PCH_SML0 DATA
D_CK_SCLK
D_CK_SDAT A
CNV_RF_RE SET#
CLKREQ_CN V#
PCH_JTAG_T CK1
PM_SLP_S3 #
PM_SLP_S4 #
SYS_RESET #
SYS_PWROK
EC_RSMRST#
HDA_BIT_CL K
HDA_RST#
HDA_BIT_CLK
HDA_SDOUT
HDA_SYNC
HDA_RST#
LAN_WAKE#
PCH_PWROK
EC_RSMRST#
AC_PRESENT _R
PBTN_OUT#_ R
PCM_OUT
PCM_CLK
D_CK_SCLK
D_CK_SDAT APCH_SMBD ATA
PCH_SMBC LK
PCH_SMBA LERT#UART_WAK E#
CPU_DISPA_SD O_R<6 >
CPU_DISPA_BC LK_R<6>
CPU_DISPA_SD I_R<6>
HDA_SDIN0<56>
PCH_DMIC_CL K0<56>
PCH_DMIC_DAT A0<56>
DDR_DRAMR ST#_R <23,24>
SYS_PWROK <5 8,78>
PM_SLP_S3# <58,78>
PM_SLP_S4# <58,78>
SUSCLK <5 2,68,69>
AC_PRESENT <58>
PBTN_OUT# < 58>
H_CPUPWRG D <10>
PCH_SPKR <19,56>
PCH_PWROK<5 8,78>
CPU_XDP_T CK0 <10>
CPU_XDP_T DI <10>
CPU_XDP_ TDO <10>
CPU_XDP_ TMS <10>
PCH_RTCRS T#<58>
TYPEC_3A < 43>
SUSPWRDNA CK <58>
EC_RSMRST#<58>
PCH_SMBALE RT#<19>
PCH_SML0AL ERT#<19>
PCH_SML1A LERT#<19>
CLKREQ_ CNV#< 52>
CNV_RF_ RESET#<52>
PCH_JTAG_T CK1 <10>
HDA_BIT_CL K_R<5 6>
HDA_SDOU T_R<56>
HDA_SYNC_ R< 56>
HDA_RST# _R<56>
ME_EN<58>
PCH_SML1CL K <27,58,66>
PCH_SML1DA TA <27,58,66>
PCM_CLK<52>
PCM_OUT<52>
D_CK_SCLK < 23,24>
D_CK_SDATA <23,24>
UART_WAKE#<52>
+RTCVCC
+1.2V_VDDQ
+3VALW_DSW
+3VS
+3VALW
+3VALW
+3VALW
+3VALW_DSW
+3VS
+3VALW
Title
Size Document Number R e v
Date: Sheet o f
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEE RING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET IN FORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AU THORIZED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHEET NOR THE INFORMA TION IT CONTAINS
MAY BE USED BY OR DISC LOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELEC TRONICS, INC.
Issued Date
Deciphered Date
FH51M M/B LA-J871P
1.0
PCH(5/8)PMU/HDA/SMBUS/DMIC
Custom
18 112Tue sday, February 11, 2020
2019/09/20 2020/09/20
Compal Electronics, Inc.
Title
Size Document Number R e v
Date: Sheet o f
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEE RING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET IN FORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AU THORIZED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHEET NOR THE INFORMA TION IT CONTAINS
MAY BE USED BY OR DISC LOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELEC TRONICS, INC.
Issued Date
Deciphered Date
FH51M M/B LA-J871P
1.0
PCH(5/8)PMU/HDA/SMBUS/DMIC
Custom
18 112Tue sday, February 11, 2020
2019/09/20 2020/09/20
Compal Electronics, Inc.
Title
Size Document Number R e v
Date: Sheet o f
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEE RING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET IN FORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AU THORIZED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHEET NOR THE INFORMA TION IT CONTAINS
MAY BE USED BY OR DISC LOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELEC TRONICS, INC.
Issued Date
Deciphered Date
FH51M M/B LA-J871P
1.0
PCH(5/8)PMU/HDA/SMBUS/DMIC
Custom
18 112Tue sday, February 11, 2020
2019/09/20 2020/09/20
Compal Electronics, Inc.
RH193 100K_02 01_5%
1 2
CH13 0.1U_0201 _10V6K
@
12
RH63 499_0402_ 1%
1 2
RH183 10 K_0402_5%
12
RH46
470_0402_ 1%
1 2
RH49
30_0402_5%
1 2
RH251 2.2K_040 2_5%
12
RH208 33_040 2_5%
1 2
RH194 100K_02 01_5%
1 2
RH51 0_0 402_5%
@
1 2
RH50 20K_0402_ 1%
1 2
TH37@
G
D
S
QH7B
2N7002KD W_SOT363-6
5
3 4
RH254 2.2K_040 2_5%
12
CH200.1U_0201_ 10V6K
XESD@
1 2
RH209 33_040 2_5%
1 2
TH21@
G
D
S
QH7A
2N7002KDW _SOT363-6
2
6 1
RH210 33_040 2_5%
1 2
CH210.1U_0201_ 10V6K
XESD@
1 2
RH57 100K_040 2_5%@
1 2
RH62 10K_0402 _5%@
12
RH52 20K_0402_ 1%
1 2
RH60 8.2K_0402_5 %
12
RH192 2.2K_040 2_5%
12
RH55 1K_0402_ 5%
12
TH20@
CH51100P_0402_50V8 J
XESD@
1 2
RH211 33_040 2_5%
1 2
CH220.1U_0201_ 10V6K
XESD@
1 2
RH58 100K_040 2_5%@
1 2
TH22 @
RH53 0_0402_5%@
1 2
RH252 2.2K_040 2_5%
12
RH61100K_0402_5% @
1 2
TH19@
RH48
30_0402_5%
1 2
T209
@
TH24 @
TH38@
T207@
JCMOS1 0_0603_5%@
1 2
RH184100K_040 2_5% @
1 2
RH196100K_0201_5%
12
TH14@
T208
@
RH213 10K_04 02_5%
1 2
TH15@
RH56 8.2K_0402_ 5%
12
CH19 1U_0201_6 .3V6M
1 2
TH23@
RH197100K_0201_5%
12
RH191 2.2K_040 2_5%
12
RH212 10K_0402 _5%
1 2
RH253 2.2K_040 2_5%
12
RH301 100K_0 402_5%
UART_BT@
1 2
RH47 0_0402_5 %
@
1 2
RH45 0_0 402_5%
@
1 2
RH54
0_0402_5%@
1 2
4 OF 13
CNP-H
Rev1.0
UH1D
CNP-H_BGA87 4 @
HDACPU_SDO
AM2
HDACPU_SDI
AN3
HDACPU_SCLK
AM3
PCH_PWROK
AY42
DSW_PWROK
AW41
SYS_PWROK
AU3
CPUPWRGD
AE3
ITP_PMODE
AL3
GPD0/BATLOW#
BF44
GPD3/PWRBTN#
BE46
GPD5/SLP_S4#
BE42
GPP_C4/SML0DATA
BE24
GPP_D19/DMIC_CLK0/SNDW4_CLK
BD16
I2S1_SFRM/SNDW2_CLK
BD12
GPP_B11/I2S_MCLK
AP29
HDA_BCLK/I2S0_SCLK
BD11
HDA_SDO/I2S0_TXD
BF12
SRTCRST#
BD46
RSMRST#
BA47
GPP_D17/DMIC_CLK1/SNDW3_CLK
AW15
GPP_D8/I2S2_SCLK
AV18
GPD4/SLP_S3#
BF42
GPP_C3/SML0CLK
BF25
GPD11/LANPHYPC
BF41
PCH_JTAGX
AH4
HDA_SYNC/I2S0_SFRM
BG13
GPP_C0/SMBCLK
BE26
HDA_RST#/I2S1_SCLK
BE10
SYS_RESET#
AU2
GPP_A12/BM_BUSY#/ISH_GP6/SX_EXIT_HOLDOFF#
BF36
HDA_SDI0/I2S0_RXD
BE11
GPD9/SLP_WLAN#
BD42
SLP_LAN#
BF40
GPP_C5/SML0ALERT#
BF24
GPP_D20/DMIC_DATA0/SNDW4_DATA
BF15
GPP_D6/I2S2_TXD/MODEM_CLKREQ
BA17
RTCRST#
BE47
GPD6/SLP_A#
BE40
GPP_A15/SUSACK#
BE35
GPP_B2/VRALERT#
BE32
GPP_D5/I2S2_SFRM/CNV_RF_RESET#
BE16
GPP_B1/GSPI1_CS1#/TIME_SYNC1
BF33
GPP_C6/SML1CLK
BF27
GPD10/SLP_S5#
BC42
GPP_A8/CLKRUN#
AV32
PCH_JTAG_TDI
AH2
GPD8/SUSCLK
BE45
GPP_C2/SMBALERT#
BE25
PCH_JTAG_TMS
AJ4
GPP_K17/ADR_COMPLETE
R47
GPP_C1/SMBDATA
BF26
GPP_B23/SML1ALERT#/PCHHOT#
BD33
WAKE#
BB47
DRAM_RESET#
BB46
GPP_D18/DMIC_DATA1/SNDW3_DATA
AV16
HDA_SDI1/I2S1_RXD
BF10
PCH_JTAG_TCK
AJ3
GPP_B0/GSPI0_CS1#
BE29
GPP_B14/SPKR
AW29
GPD2/LAN_WAKE#
BG44
GPD1/ACPRESENT
BG42
GPP_C7/SML1DATA
BE27
I2S1_TXD/SNDW2_DATA
BE12
SLP_SUS#
BD39
GPP_A13/SUSWARN#/SUSPWRDNACK
BC37
GPP_B12/SLP_S0#
BC28
GPP_D7/I2S2_RXD
AW18
PCH_JTAG_TDO
AH3
RH64 499_0402_ 1%
1 2
RH214 10K_04 02_5%
1 2
CH18 1U_0201_6 .3V6M
1 2
RH302 0_0402_5 %
UART_BT@
1 2
RH59 0_0 402_5%
@
1 2
www.laptoprepairsecrets.com
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
SCI capability is available on all GPIOs
PCH GPIOs that can be routed to generate SMI# or NMI:
GPP_B14, GPP_B20, GPP_B23
‧
GPP_C[23:22]
‧
GPP_D[4:0]
‧
GPP_E[8:0]
‧
GPP_I[3:0]
‧
GPP_G[7:0] (support SMI# only).
‧
The voltage of all GPIO pads in each GPP group is determined by the voltage supplied to the group (either 3.3V or 1.8V),
except for GPP_I and GPD group, (which are 3.3V only), and GPP_J group (which is 1.8V only).
All GPIOs have programmable internal pull-up/pull-down resistors which are off by default.
The internal pull-up/pull-down for each GPIO can be enabled by BIOS programming.
The signal has a weak internal Pull-down.
0 = Disable “ No Reboot” mode. (Default)
1 = Enable “ No Reboot” mode (PCH will disable the
TCO Timer system reboot feature). This function is
useful when running ITP/XDP.
Notes:
1. The internal Pull-down is disabled after
PCH_PWROK is high.
2. This signal is in the primary well.
This Signal has a weak internal Pull-down.
0: SPI (Default)
1: LPC
Notes:
1. The internal Pull-down is disabled after PCH_PWROK is high.
2. This signal is in the primary well.
Top Swap Override
0 = Disable “ Top Swap” mode. (Default)
1 = Enable “ Top Swap” mode.
The internal Pull-down is disabled after PCH_PWROK is high.
This signal has a weak internal pull-down.
0 = Master Attached Flash Sharing (MAFS) enabled (Default)
1 = Slave Attached Flash Sharing (SAFS) enabled.
Notes:
1. This signal is in the primary well.
Warning: This strap must be configured to ‘ 0’ if the
eSPI or LPC strap is configured to ‘ 0’
STRAP
STRAP
STRAP
STRAP
CG11 connect to GPP_B15
<Touch PAD>
check needed?
SMBALERT# / GPP_C2 has a weak internal Pull-down.
0 = Disable Intel ME (TLS) (Default)
1 = Enable Intel ME (TLS)
SML0ALERT# / GPP_C5 has a weak internal Pull-down.
0 = LPC is selected (for EC 9022).
1 = eSPI is selected
SML1ALERT# / GPP_B23 has an internal pull-down.
0 = Disable IntelR DCI-OOB (Default)
1 = Enable IntelR DCI-OOB
STRAP
check for remove (PCH or Both)
*
Reserved
Reserved
Reserved 0
00
for 8 Layer
GPP_D10 GPP_D9
01
1
11
0 0
0
0
Project ID
GPP_D11GPP_D12
1
1
1 1
Project_ID0Project_ID1
20190927
<EMR>
2020 A7
2020 Gaming 60
*
2020 Gaming 50
20190506
- defined as Project
NA
UART_2_PT XD_DRXD
UART_2_PR XD_DTXD
UART_2_PR TS_DCTS
UART_2_PC TS_DRTS
DGPU_PWR_ EN
GSPI0_MOSI
GSPI0_MOSI
GSPI1_MOSI
GSPI1_MOSI
PCH_SPKR
GPP_H12
EC_SCI#
UART_2_PR XD_DTXD
UART_2_PT XD_DRXD
UART_2_PC TS_DRTS
UART_2_PR TS_DCTS
I2C_1_SCL
I2C_1_SDA
TS_EN
GPU_EVENT#
DGPU_AC_D ETECT
EC_SCI# GC6_FB_E N3V3 GC6_FB_E N
DGPU_HOLD_ RST#
DGPU_PWR_EN
DGPU_HOLD_ RST#
GPP_D10
GPP_D9
PROJECT_ID0
PROJECT_ID1
GPP_D9
GPP_D10
I2C_0_SCL
I2C_0_SDA
CPU_ID
SUB_DET
PROJECT_ ID0
PROJECT_ID1
I2C_1_SCL
I2C_1_SDA
I2C_0_SCL
I2C_0_SDA
SUB_DET
CPU_ID
I2C_SCL_T S
I2C_SDA_T S
PEN_IRQ#
PEN_PDCT #
PEN_RST#
WAKE_BT
PCH_SPKR <1 8,56>
GPP_H12 <1 6>
EC_SCI#<58>
I2C_1_SDA<63>
I2C_1_SCL<63 >
TS_EN<38,58>
GPU_EVENT#<27>
GC6_FB_E N3V3<27>
DGPU_AC_DE TECT<27,58,85>
DGPU_HOLD _RST#<27>
DGPU_PWR_E N<27>
UART_2_PT XD_DRXD<52>
UART_2_PR XD_DTXD<52>
PCH_SMBALE RT# <18>
PCH_SML0A LERT# <18>
PCH_SML1A LERT# <18>
PANEL_OD _EN <38>
I2C_SCL_TS<38>
I2C_SDA_T S<38>
I2C_0_SCL<64 >
I2C_0_SDA<64>
PEN_IRQ# <64>
PEN_PDCT#<64>
PEN_RST#<64>
WAKE_BT<5 2>
+3VS
+3VS
+3VALW
+3VALW
+1.8VALW_P RIM
+1.8VALW_PRIM
+1.8VALW_PR IM
+3VALW
+1.8VALW_PR IM
Title
Size Document Number R e v
Date: Sheet o f
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEE RING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET IN FORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AU THORIZED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHEET NOR THE INFORMA TION IT CONTAINS
MAY BE USED BY OR DISC LOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELEC TRONICS, INC.
Issued Date
Deciphered Date
FH51M M/B LA-J871P
1.0
PCH(6/8)GPIO/I2C/UART/STRAP
Custom
19 11 2Tuesday, Feb ruary 11, 2020
2019/09/20 2020/09/20
Compal Electronics, Inc.
Title
Size Document Number R e v
Date: Sheet o f
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEE RING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET IN FORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AU THORIZED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHEET NOR THE INFORMA TION IT CONTAINS
MAY BE USED BY OR DISC LOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELEC TRONICS, INC.
Issued Date
Deciphered Date
FH51M M/B LA-J871P
1.0
PCH(6/8)GPIO/I2C/UART/STRAP
Custom
19 112Tue sday, February 11, 2020
2019/09/20 2020/09/20
Compal Electronics, Inc.
Title
Size Document Number R e v
Date: Sheet o f
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEE RING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET IN FORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AU THORIZED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHEET NOR THE INFORMA TION IT CONTAINS
MAY BE USED BY OR DISC LOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELEC TRONICS, INC.
Issued Date
Deciphered Date
FH51M M/B LA-J871P
1.0
PCH(6/8)GPIO/I2C/UART/STRAP
Custom
19 112Tue sday, February 11, 2020
2019/09/20 2020/09/20
Compal Electronics, Inc.
RH86 1K_0402_5%@
1 2
RH255 1K_040 2_5%H82@
1 2
RH113 4.7K_0402 _5%@
1 2
RH70 49.9K_0402_ 1%@
12
RH256 10K_04 02_5%H6 2@
1 2
RH72 10K_0402_ 5%VGA@
1 2
RH185 1K_04 02_5%@
1 2
RH83 100K_0402 _5%@
12
RH114 150K_04 02_1%
1 2
RH77 4.7K_0402 _5%@
1 2
RH88 1K_0402_5%@
1 2
RH68 49.9K_0402_ 1%
12
RH89 10K_0402_5%
1 2
RH85 10K_0402_5%
1 2
RH73 10K_0402_ 5%VGA@
1 2
RH87 10K_0402_5%
1 2
RH90 1K_0402_5%
1 2
RH91 10K_0402_5%@
1 2
RH66 10K_0402_ 5%@
12
RH215 2.2K_04 02_5%
1 2
RH71 49.9K_0402_ 1%@
12
RH80 150K_04 02_1%
@
1 2
RH69 49.9K_0402_ 1%
12
RH216 2.2K_04 02_5%
1 2
RH67 0_0402_5%@
1 2
RH74 4.7K_0402_ 5%@
1 2
RH217 2.2K_04 02_5%
1 2
RH112 4.7K_040 2_5%@
1 2
11 OF 13
CNP-H
Rev1.0
UH1K
CNP-H_BGA87 4
@
GPP_B21/GSPI1_MISO
BD30
GPP_C22/UART2_RTS#
AW21
GPP_C8/UART0A_RXD
BE23
GPP_C20/UART2_RXD
BD20
GPP_D13/ISH_UART0_RXD/I2C2_SDA
BE17
GPP_C10/UART0A_RTS#
BA24
GPP_C23/UART2_CTS#
AV21
GPP_B22/GSPI1_MOSI
BA26
GPP_D12/ISH_SPI_MOSI/GP_BSSB_DI/GSPI2_MOSI
AN18
GPP_C18/I2C1_SDA
BF21
GPP_C19/I2C1_SCL
BE21
GPP_C11/UART0A_CTS#
AP24
GPP_C13/UART1_TXD/ISH_UART1_TXD
AP21
GPP_D14/ISH_UART0_TXD/I2C2_SCL
BF17
GPP_H20/ISH_I2C0_SCL
AG45
GPP_A17/SD_VDD1_PWR_EN#/ISH_GP7
BD38
GPP_B17/GSPI0_MISO
BD29
GPP_C12/UART1_RXD/ISH_UART1_RXD
AU24
GPP_B16/GSPI0_CLK
BF29
GPP_D16/ISH_UART0_CTS#/CNV_WCEN
BF14
GPP_B15/GSPI0_CS0#
BB26
GPP_A23/ISH_GP5
AV34
GPP_D10/ISH_SPI_CLK/GSPI2_CLK
BB20
GPP_B19/GSPI1_CS0#
AW26
GPP_H22/ISH_I2C1_SCL
AH47
GPP_A22/ISH_GP4
AW32
GPP_D15/ISH_UART0_RTS#/GSPI2_CS1#/CNV_WFEN
AR18
GPP_H19/ISH_I2C0_SDA
AH46
GPP_B18/GSPI0_MOSI
BE30
GPP_C17/I2C0_SCL
BC22
GPP_C16/I2C0_SDA
BF23
GPP_D23/ISH_I2C2_SCL/I2C3_SCL
BE14
GPP_A19/ISH_GP1
BD34
GPP_D11/ISH_SPI_MISO/GP_BSSB_CLK/GSPI2_MISO
BB16
GPP_A21/ISH_GP3
BA33
GPP_D9/ISH_SPI_CS#/GSPI2_CS0#
BA20
GPP_B20/GSPI1_CLK
AU26
GPP_H21/ISH_I2C1_SDA
AH48
GPP_C21/UART2_TXD
BE20
GPP_D4/ISH_I2C2_SDA/I2C3_SDA/SBK4_BK4
BE15
GPP_C15/UART1_CTS#/ISH_UART1_CTS#
BD21
GPP_C9/UART0A_TXD
BB24
GPP_A18/ISH_GP0
BF35
GPP_A20/ISH_GP2
BE34
GPP_C14/UART1_RTS#/ISH_UART1_RTS#
AW24
RH218 2.2K_04 02_5%
1 2
RH84 1K_0402_5%@
1 2
www.laptoprepairsecrets.com
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
5.95A
3-5MM FROM PACKAGE EDGE
6.6A
GPPH
3.3V Only
3.3V
GPPA
GPPB
GPPC
GPIO Group Volta ge
3.3V
3.3V
GPPD
GPPE
GPPF
GPPG
3.3V
3.3V
GPPK
1.8V Only
GPPI
GPPJ
GPD
3.3V Only
SP02000RO00
0.0895A
0.14A
0.343A
0.101A
0.766A
RH174 for 571391_CFL_H_PDG_Rev0p71.pdf
0.113A
0.00767A
0.106A
0.145A
0.97A
0.262A
0.174A
Close to BB11
0.05A
For DDX03 R02
Internal LDO
Short pins AJ22,AJ23,AK22,AK23 together
at surface layer from PDG Rev0.71
VCCPHVLDO_1P8
(External VRM mode RH172 unmount)
0.182A
0.095A
0.882A
0.193A
0.00428A
6.6A
0.169A
0.0085A
0.0198A
0.021A
0.2A
0.42A
0.109A
0.015A
0.213A
HSIO for DMIU/USB3.1/PCIE=4162mA
5.95A
0.0012A
1-3MM FROM PACKAGE EDGE
1-3MM FROM PACKAGE
VCCPRIM_MPHY W31
1-3MM FROM PACKAGE EDGE
1uF 1-3MM FROM PACKAGE EDGE
LC filter close to pin
1-5MM FROM PACKAGE EDGE
FOR VCCAPLL C1/C2
1-3MM FROM PACKAGE EDGE
FOR VCCA_BCLK V19
1-5MM FROM PACKAGE EDGE
FOR VCCAPLL B1/B2/B3
place near VCCDUSB
FOR W22/W23
1-3MM FROM PACKAGE
FOR VCCPRIM AY8/BB7
1-3MM FROM PACKAGE
FOR PGPPHK AC35/AC36
1-3MM FROM PACKAGE
FOR PGPPEF AE35/AE37
reserve filter follow CRB
8/21
change to 10k
3.3V
1.8V
*
Place Near UH1 VCCPRIM_1_0523~29
reserved for cnvi
near AG19/AG20
20200114
- RH100 Change to R-short
VCCMPHY_SENSE
VSSMPHY_SENSE
+1.8V_PHVLDO
+VCCRTCEXT
+1.05VALW_PCH +1.05V_VCCDSW
+1.05VALW_VCCAMPHYPLL
+1.05VALW_VCCAZPLL
+1.05VALW_XTAL
+1.05VALW_PCH
+1.05VALW_PCH
+1.05VALW_PCH
+RTCVCC
+RTCBATT
+CHGRTC
+3VALW
+3VALW+3VALW
+3VALW_DSW
+1.05VALW
+1.05VALW_PCH_PRIM
+1.05VALW
+1.05VALW_PCH
+1.05VALW_PCH
+1.05VALW_PCH
+3VALW
+1.8VALW_PRIM+1.8VALW
+3VALW_HDA
+RTCBATT
+RTCVCC
+3VALW_DSW
+1.24V_VCCLDOSRAM_IN
+1.24V_PRIM_DPHY
+VCCRTCEXT
+1.24V_PRIM_MAR
+1.24V_PRIM_MAR
+3VALW
+3VALW_HDA
+1.05VALW_PCH
+1.05VALW_PCH
+1.8V_PHVLDO
+1.24V_VCCLDOSRAM_IN +1.24V_PRIM_DPHY
+1.05VALW
+1.05V_VCCDSW
+1.05VALW_VCCAMPHYPLL
+1.05VALW_VCCAZPLL
+1.05VALW_XTAL
+1.05VALW_PCH_PRIM
+1.05VALW_PCH
+3VALW
+1.8VALW_PRIM
+1.8VALW_PRIM
+1.8VALW_PRIM
+1.8VALW_PRIM
+1.8VALW_PRIM +1.8VALW_PRIM
+VCCRTCEXT
Title
Size Document Number R ev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
FH51M M/B LA-J871P
1.0
PCH(7/8)Power
Custom
20 112Tuesday, February 11, 2020
2019/09/20 2020/09/20
Compal Electronics, Inc.
Title
Size Document Number R ev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
FH51M M/B LA-J871P
1.0
PCH(7/8)Power
Custom
20 112Tuesday, February 11, 2020
2019/09/20 2020/09/20
Compal Electronics, Inc.
Title
Size Document Number R ev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
FH51M M/B LA-J871P
1.0
PCH(7/8)Power
Custom
20 112Tuesday, February 11, 2020
2019/09/20 2020/09/20
Compal Electronics, Inc.
C
H
4
6
1
U
_
0
2
0
1
_
6
.
3
V
6
M
1
2
C
H
2
3
1
U
_
0
2
0
1
_
6
.
3
V
6
M
1
2
C
H
4
3
1
P
_
0
4
0
2
_
5
0
V
8
@
1
2
C
H
3
4
0
.
1
U
_
0
2
0
1
_
1
0
V
6
K
1
2
C
H
3
6
0
.
1
U
_
0
2
0
1
_
1
0
V
6
K
@
1
2
C
H
2
4
0
.
1
U
_
0
2
0
1
_
1
0
V
6
K
1
2
RH94 0_0603_5%@
1 2
C
H
4
0
0
.
1
U
_
0
2
0
1
_
1
0
V
6
K
1
2
8 OF 13
CNP-H
Rev1.0
UH1H
CNP-H_BGA874
@
VCCPRIM_1P051
AA22
VCCPRIM_1P052
AA23
VCCPRIM_1P053
AB20
VCCPRIM_1P054
AB22
VCCPRIM_1P055
AB23
VCCPRIM_1P056
AB27
VCCPRIM_1P057
AB28
VCCPRIM_1P058
AB30
VCCPRIM_1P059
AD20
VCCPRIM_1P0510
AD23
VCCPRIM_1P0511
AD27
VCCPRIM_1P0512
AD28
VCCPRIM_1P0513
AD30
VCCPRIM_1P0514
AD31
VCCPRIM_1P0515
AE17
VCCPRIM_1P0516
AF23
VCCDUSB_1P051
W22
VCCDUSB_1P052
W23
VCCDSW_1P051
BG45
VCCDSW_1P052
BG46
VCCAMPHYPLL_1P051
C49
VCCAMPHYPLL_1P052
D49
VCCAMPHYPLL_1P053
E49
VCCA_XTAL_1P051
P2
VCCA_XTAL_1P052
P3
VCCA_SRC_1P051
W19
VCCA_SRC_1P052
W20
VCCPGPPHK1
AC35
VCCPGPPHK2
AC36
VCCPGPPEF1
AE35
VCCPGPPEF2
AE36
VCCPGPPD
AN24
VCCPGPPBC1
AN26
VCCPGPPBC2
AP26
VCCPGPPA
AN32
VCCPRIM_1P81
AF19
VCCPRIM_1P82
AF20
VCCPRIM_1P83
AG19
VCCPRIM_1P84
AG20
VCCPRIM_1P85
AN15
VCCDPHY_1P241
AJ22
VCCDPHY_1P242
AJ23
VCCDPHY_1P243
BG5
VCCMPHY_SENSE
K47
VSSMPHY_SENSE
K46
VCCAPLL_1P055
C2
VCCDSW_3P32
BE49
VCCHDA
BB14
VCCAPLL_1P054
C1
VCCDSW_3P31
BE48
VCCAPLL_1P053
B3
VCCAPLL_1P052
B2
VCCPRIM_MPHY_1P05
W31
VCCAPLL_1P051
B1
VCCPRIM_1P0519
AF31
VCCPRIM_1P0529
V31
VCCPRIM_1P0518
AF30
VCCPRIM_1P0528
V30
VCCPRIM_1P0517
AF27
VCCPRIM_1P0527
V28
VCCPRIM_1P87
BB11
VCCSPI
AN44
VCCPRIM_1P0526
V27
VCCPRIM_1P86
AR15
VCCPRIM_1P0525
V25
VCCPRIM_1P0524
U29
VCCPRIM_1P0523
U26
VCCRTC2
BD49
VCCPRIM_3P35
V23
VCCRTC1
BC49
VCCPRIM_1P0522
E1
VCCPRIM_3P34
BB7
VCCPGPPG_3P3
AN21
VCCPRIM_1P0521
D1
DCPRTC2
BG47
VCCPRIM_3P33
AY8
VCCPRIM_1P0520
AG31
DCPRTC1
BF47
VCCPRIM_3P32
AW9
VCCA_BCLK_1P05
V19
VCCPRIM_3P31
AT44
VCCPRIM_1P242
AK23
VCCPRIM_1P241
AK22
RH101 0_0402_5%@
12
C
H
5
4
0
.
1
U
_
0
2
0
1
_
1
0
V
6
K
1
2
C
H
2
7
4
.
7
U
_
0
4
0
2
_
6
.
3
V
6
M
1
2
C
H
4
9
2
2
U
_
0
6
0
3
_
6
.
3
V
6
M
1
2
C
H
3
8
0
.
1
U
_
0
2
0
1
_
1
0
V
6
K
1
2
RH104 1K_0402_5%
12
TH28@
C
H
3
1
1
U
_
0
2
0
1
_
6
.
3
V
6
M
1
2
C
H
3
3
1
U
_
0
2
0
1
_
6
.
3
V
6
M
1
2
RH105 0_0402_5%@
1 2
C
H
2
6
1
U
_
0
2
0
1
_
6
.
3
V
6
M
1
2
C
H
3
2
4
.
7
U
_
0
4
0
2
_
6
.
3
V
6
M
1
2
JPH1
JUMP_43X79
@
112
2
C
H
5
3
0
.
1
U
_
0
2
0
1
_
1
0
V
6
K
@
1
2
RH100 0_0603_5%@
1 2
TH27@
C
H
5
2
0
.
1
U
_
0
2
0
1
_
1
0
V
6
K
1
2
JRTC1
ACES_50271-0020N-001
CONN@
1
1
2
2
GND
3
GND
4
BAV70W_SOT323-3
DH2
2
3
1
RH96 0_0402_5%@
1 2
C
H
4
2
1
P
_
0
4
0
2
_
5
0
V
8
@
1
2
C
H
3
7
1
U
_
0
2
0
1
_
6
.
3
V
6
M
1
2
C
H
4
7
1
U
_
0
2
0
1
_
6
.
3
V
6
M
1
2
RH103 0_0402_5%@
1 2
C
H
3
9
0
.
1
U
_
0
2
0
1
_
1
0
V
6
K
@
1
2
C
H
3
0
0
.
1
U
_
0
2
0
1
_
1
0
V
6
K
1
2
RH99 0_0402_5%@
1 2
C
H
2
9
0
.
1
U
_
0
2
0
1
_
1
0
V
6
K
1
2
C
H
2
8
1
U
_
0
2
0
1
_
6
.
3
V
6
M
1
2
C
H
4
8
0
.
1
U
_
0
2
0
1
_
1
0
V
6
K
1
2
RH102 0_0402_5%@
1 2
C
H
4
5
2
2
U
_
0
6
0
3
_
6
.
3
V
6
M
1
2
C
H
4
4
1
P
_
0
4
0
2
_
5
0
V
8
@
1
2
RH95 0_0402_5%@
1 2
C
H
4
1
1
P
_
0
4
0
2
_
5
0
V
8
@
1
2
C
H
3
5
1
U
_
0
2
0
1
_
6
.
3
V
6
M
1
2
C
H
2
5
2
2
U
_
0
6
0
3
_
6
.
3
V
6
M
1
2
www.laptoprepairsecrets.com
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
CPU_TRIGOUT _R
PCH_TRIGOUT PCH_TRIGOUT_ R
CPU_XDP_ TRST#
XDP_PREQ #
XDP_PRDY #
CPU_TRIGOU T_R <13>
PCH_TRIGOU T_R <13>
XDP_PRDY# <10>
CPU_XDP_TR ST# <10>
XDP_PREQ # <10>
Title
Size Document Number R e v
Date: Sheet o f
Security Classification
Compal Secret Data
THIS SHEET OF ENGINE ERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, IN C. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFO RMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTODY OF THE COMP ETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHEET NOR THE INFORM ATION IT CONTAINS
MAY BE USED BY OR DIS CLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELEC TRONICS, INC.
Issued Date
Deciphered Date
FH51M M/B LA-J871P
1.0
PCH(8/8)GND/RSVD
Custom
21 11 2Tuesday, F ebruary 11, 2020
2019/09/20 2020/09/20
Compal Electronics, Inc.
Title
Size Document Number R e v
Date: Sheet o f
Security Classification
Compal Secret Data
THIS SHEET OF ENGINE ERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, IN C. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFO RMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTODY OF THE COMP ETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHEET NOR THE INFORM ATION IT CONTAINS
MAY BE USED BY OR DIS CLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELEC TRONICS, INC.
Issued Date
Deciphered Date
FH51M M/B LA-J871P
1.0
PCH(8/8)GND/RSVD
Custom
21 11 2Tuesday, F ebruary 11, 2020
2019/09/20 2020/09/20
Compal Electronics, Inc.
Title
Size Document Number R e v
Date: Sheet o f
Security Classification
Compal Secret Data
THIS SHEET OF ENGINE ERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, IN C. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFO RMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTODY OF THE COMP ETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHEET NOR THE INFORM ATION IT CONTAINS
MAY BE USED BY OR DIS CLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELEC TRONICS, INC.
Issued Date
Deciphered Date
FH51M M/B LA-J871P
1.0
PCH(8/8)GND/RSVD
Custom
21 11 2Tuesday, F ebruary 11, 2020
2019/09/20 2020/09/20
Compal Electronics, Inc.
RH106 30_0402 _5%
1 2
10 OF 13
CNP-H
Rev1.0
UH1J
CNP-H_BGA87 4
@
TRIGGER_OUT
AK3
TRIGGER_IN
AK2
CPU_TRST#
AM4
PREQ#
AL2
RSVD8
Y15
RSVD7
Y14
RSVD6
U37
RSVD5
U35
RSVD4
R32
RSVD3
N32
PRDY#
AM5
RSVD2
AH15
RSVD1
AH14
9 OF 13
CNP-H
Rev1.0
UH1I
CNP-H_BGA87 4
@
VSS
BF2
VSS
BC19
VSS
BA12
VSS
AT34
VSS
AP46
VSS
AA31
VSS
BF3
VSS
BC24
VSS
BA14
VSS
AT45
VSS
AR12
VSS
AL38
VSS
BF48
VSS
BC26
VSS
BA44
VSS
AV11
VSS
AR16
VSS
AM1
VSS
AK31
VSS
BF49
VSS
BC31
VSS
BA5
VSS
AV39
VSS
AR34
VSS
AM18
VSS
AK4
VSS
AJ27
VSS
BC35
VSS
BA6
VSS
AW10
VSS
AR38
VSS
AM32
VSS
AK46
VSS
AJ28
VSS
AG28
VSS
BB41
VSS
AW4
VSS
AT1
VSS
AM49
VSS
AL12
VSS
AJ30
VSS
AG30
VSS
AE4
VSS
AW40
VSS
AT16
VSS
AN12
VSS
AL17
VSS
AJ31
VSS
AG49
VSS
AE46
VSS
AC46
VSS
A2
VSS
AT18
VSS
AN16
VSS
AL21
VSS
AK19
VSS
AH12
VSS
AF22
VSS
AD1
VSS
AA49
VSS
A28
VSS
AT21
VSS
AN34
VSS
AL24
VSS
AK20
VSS
AH17
VSS
AF25
VSS
AD19
VSS
AA5
VSS
A48
VSS
A3
VSS
AT24
VSS
AN38
VSS
AL26
VSS
AK25
VSS
AH33
VSS
AF28
VSS
AD2
VSS
AB19
VSS
A5
VSS
A33
VSS
BG17
VSS
AP4
VSS
AL29
VSS
AK27
VSS
AH38
VSS
AG1
VSS
AD22
VSS
AB25
VSS
A8
VSS
A37
VSS
BG2
VSS
BC40
VSS
AL33
VSS
AK28
VSS
AJ19
VSS
AG22
VSS
AD25
VSS
AB31
VSS
AA19
VSS
A4
VSS
BG22
VSS
BC45
VSS
BB43
VSS
AK30
VSS
AJ20
VSS
AG23
VSS
AD49
VSS
AC12
VSS
AA20
VSS
A45
VSS
BG25
VSS
BC8
VSS
BB9
VSS
AW46
VSS
AJ25
VSS
AG25
VSS
AE12
VSS
AC17
VSS
AA25
VSS
A46
VSS
BG28
VSS
BD43
VSS
BC10
VSS
B47
VSS
AT26
VSS
AG27
VSS
AE33
VSS
AC33
VSS
AA27
VSS
A47
VSS
BE44
VSS
BC13
VSS
B48
VSS
AT29
VSS
AE38
VSS
AC38
VSS
AA28
VSS
BF1
VSS
BC15
VSS
B49
VSS
AT32
VSS
AC4
VSS
AA30
12 OF 13
CNP-H
Rev1.0
UH1L
CNP-H_BGA8 74
@
VSS
Y9
VSS
V4
VSS
T5
VSS
R26
VSS
N16
VSS
E26
VSS
D17
VSS
BG37
VSS
V46
VSS
T7
VSS
R29
VSS
N34
VSS
D30
VSS
BG4
VSS
W25
VSS
U12
VSS
R3
VSS
N35
VSS
BG48
VSS
W27
VSS
U15
VSS
R34
VSS
N37
VSS
W28
VSS
U17
VSS
R38
VSS
N38
VSS
U21
VSS
R4
VSS
P26
VSS
J9
VSS
T17
VSS
P29
VSS
K11
VSS
G6
VSS
P4
VSS
K39
VSS
H8
VSS
E31
VSS
M16
VSS
J10
VSS
E33
VSS
D33
VSS
M18
VSS
J26
VSS
E35
VSS
D8
VSS
C12
VSS
J29
VSS
E40
VSS
E10
VSS
C25
VSS
M21
VSS
W30
VSS
J4
VSS
E42
VSS
E13
VSS
C30
VSS
M24
VSS
Y10
VSS
U24
VSS
M32
VSS
J40
VSS
E8
VSS
E15
VSS
C4
VSS
Y12
VSS
U33
VSS
T18
VSS
M34
VSS
J46
VSS
F41
VSS
E17
VSS
C48
VSS
Y17
VSS
U38
VSS
T32
VSS
P46
VSS
M49
VSS
J47
VSS
F43
VSS
E19
VSS
C5
VSS
Y33
VSS
V20
VSS
T4
VSS
R12
VSS
M5
VSS
J48
VSS
F47
VSS
E22
VSS
D12
VSS
BG3
VSS
Y38
VSS
V22
VSS
T49
VSS
R16
VSS
N12
VSS
G44
VSS
E24
VSS
D16
VSS
BG33
www.laptoprepairsecrets.com
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Layout Note:
PLACE THE CAP near JDIMM1. 164
10uF*6
1uF*8
330uF*1
DIMM Side
SPD ADDRESS FOR CHANNEL A :
WRITE ADDRESS: 0XA0
READ ADDRESS: 0XA1
SA0 = 0; SA1 = 0; SA2 = 0.
DDR4 POR OPERATING SPEED: 1867 MT/S
STRETCH GOAL IS 2133 MT/S
Layout Note:
Place near JDIMM1
Layout Note:
Place near JDIMM1.257,259
Layout Note:
Place near JDIMM1.258
CPU Side
CHANNEL-A ( Interleaved Memory )
> BOT : Reverse type (4mm)
> Non-ECC SO-DIMM
10uF*2
1uF*2
10uF*2
1uF*1
2.2uF*1
0.1uF*1
For ECC DIMM
PLACE NEAR TO PIN
PLACE NEAR TO SODIMM
VREF traces should be at least 20 mils
wide with 20 mils spacing to other
signals
Part Number: SP07001CY00
Part Value: S SOCKET LOTES ADDR0206-P001A 260P DDR4
DDR_A_DQS0
DDR_A_DQS#0
DDR_A_DQS1
DDR_A_DQS#1
DDR_A_DQS2
DDR_A_DQS#2
DDR_A_DQS3
DDR_A_DQS#3
DDR_A_DQS4
DDR_A_DQS#4
DDR_A_DQS5
DDR_A_DQS#5
DDR_A_DQS6
DDR_A_DQS#6
DDR_A_DQS7
DDR_A_DQS#7
DDR_A_CLK0
DDR_A_CLK#0
DDR_A_CLK1
DDR_A_CLK#1
DDR_A_CKE0
DDR_A_CKE1
DDR_A_CS#0
DDR_A_CS#1
DDR_A_ODT0
DDR_A_ODT1
DDR_A_BG1
DDR_A_BG0
DDR_A_BA1
DDR_A_BA0
DDR_A_MA1
DDR_A_MA0
DDR_A_MA3
DDR_A_MA2
DDR_A_MA5
DDR_A_MA4
DDR_A_MA7
DDR_A_MA6
DDR_A_MA9
DDR_A_MA8
DDR_A_MA10
DDR_A_MA12
DDR_A_MA11
DDR_A_MA13
DDR_A_MA14_WE#
DDR_A_MA15_CAS#
DDR_A_MA16_RAS#
DDR_A_ACT#
DDR_A_ALERT#
DDR_A_PAR
DIMM1_CHA_EVENT#
DDR_DRAMRST#_R
DDR_DRAMRST#_R
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D15
DDR_A_D6
DDR_A_D5
DDR_A_D4
DDR_A_D7
DDR_A_D14
DDR_A_D13
DDR_A_D12
DDR_A_D46
DDR_A_D17
DDR_A_D16
DDR_A_D19
DDR_A_D18
DDR_A_D47
DDR_A_D48
DDR_A_D24
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D8
DDR_A_D9
DDR_A_D49
DDR_A_D10
DDR_A_D11
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D20
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D21
DDR_A_D61
DDR_A_D22
DDR_A_D62
DDR_A_D63
DDR_A_D23
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_CLK0<7>
DDR_A_CLK#0<7>
DDR_A_CLK1<7>
DDR_A_CLK#1<7>
DDR_A_CKE0<7>
DDR_A_CKE1<7>
DDR_A_CS#0<7>
DDR_A_CS#1<7>
DDR_A_ODT0<7>
DDR_A_ODT1<7>
DDR_A_D[48..63]<7>
DDR_A_D[0..15]<7>
DDR_A_D[16..31]<7>
DDR_A_D[32..47]<7>
DDR_A_BG0<7>
DDR_A_BG1<7>
DDR_A_BA0<7>
DDR_A_BA1<7>
DDR_A_MA0<7>
DDR_A_MA1<7>
DDR_A_MA2<7>
DDR_A_MA3<7>
DDR_A_MA4<7>
DDR_A_MA5<7>
DDR_A_MA6<7>
DDR_A_MA7<7>
DDR_A_MA8<7>
DDR_A_MA9<7>
DDR_A_MA10<7>
DDR_A_MA11<7>
DDR_A_MA12<7>
DDR_A_MA13<7>
DDR_A_MA14_WE#<7>
DDR_A_MA15_CAS#<7>
DDR_A_MA16_RAS#<7>
DDR_A_ACT#<7>
DDR_A_PAR<7>
DDR_A_ALERT#<7>
DDR_A_DQS0 <7>
DDR_A_DQS#0 <7>
DDR_A_DQS1 <7>
DDR_A_DQS#1 <7>
DDR_A_DQS2 <7>
DDR_A_DQS#2 <7>
DDR_A_DQS3 <7>
DDR_A_DQS#3 <7>
DDR_A_DQS4 <7>
DDR_A_DQS#4 <7>
DDR_A_DQS5 <7>
DDR_A_DQS#5 <7>
DDR_A_DQS6 <7>
DDR_A_DQS#6 <7>
DDR_A_DQS7 <7>
DDR_A_DQS#7 <7>
DDR_DRAMRST#_R<18,24>
D_CK_SCLK<18,24>
D_CK_SDATA<18,24>
+0.6V_DDR_VREFCA
+1.2V_VDDQ+1.2V_VDDQ
+1.2V_VDDQ
+1.2V_VDDQ
+0.6V_DDR_VREFCA
+2.5V +0.6VS_VTT
+0.6V_VREFCA
+0.6V_DDR_VREFCA
+1.2V_VDDQ
+0.6VS_VTT
+2.5V
+3VS
+1.2V_VDDQ
+1.2V_VDDQ
+1.2V_VDDQ
Title
Size Document Number R ev
Date: Sheet o f
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
FH51M M/B LA-J871P
1.0
23 112Tuesday, February 11, 2020
2019/09/20 2020/09/20
Compal Electronics, Inc.
DDRIV_CHA: DIMM0
Title
Size Document Number R ev
Date: Sheet o f
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
FH51M M/B LA-J871P
1.0
23 112Tuesday, February 11, 2020
2019/09/20 2020/09/20
Compal Electronics, Inc.
DDRIV_CHA: DIMM0
Title
Size Document Number R ev
Date: Sheet o f
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
FH51M M/B LA-J871P
1.0
23 112Tuesday, February 11, 2020
2019/09/20 2020/09/20
Compal Electronics, Inc.
DDRIV_CHA: DIMM0
C
D
2
3
1
0
U
_
0
4
0
2
_
6
.
3
V
6
M
@
1
2
C
D
3
1
1
U
_
0
2
0
1
_
6
.
3
V
6
M
1
2
C
D
4
1
0
U
_
0
4
0
2
_
6
.
3
V
6
M
1
2
REVERSE
JDIMM1B
LOTES_ADDR0206-P001A
CONN@
VDD1
111
VDD2
112
VDD3
117
VDD4
118
VDD5
123
VDD6
124
VDD7
129
VDD8
130
VDD9
135
VDD10
136
VDDSPD
255
VREFCA
164
VSS
1
VSS
2
VSS
5
VSS
6
VSS
9
VSS
10
VSS
14
VSS
15
VSS
18
VSS
19
VSS
22
VSS
23
VSS
26
VSS
27
VSS
30
VSS
31
VSS
35
VSS
36
VSS
39
VSS
40
VSS
43
VSS
44
VSS
47
VSS
48
VSS
51
VSS
52
VSS
56
VSS
57
VSS
60
VSS
61
VSS
64
VSS
65
VSS
68
VSS
69
VSS
72
VSS
73
VSS
77
VSS
78
VSS
81
VSS
82
VSS
85
VSS
86
VSS
89
VSS
90
VSS
93
VSS
94
VSS
98
GND
262
VDD11
141
VDD12
142
VDD13
147
VDD14
148
VDD15
153
VDD16
154
VDD17
159
VDD18
160
VDD19
163
VTT
258
VPP1
257
VPP2
259
VSS
99
VSS
102
VSS
103
VSS
106
VSS
107
VSS
167
VSS
168
VSS
171
VSS
172
VSS
175
VSS
176
VSS
180
VSS
181
VSS
184
VSS
185
VSS
188
VSS
189
VSS
192
VSS
193
VSS
196
VSS
197
VSS
201
VSS
202
VSS
205
VSS
206
VSS
209
VSS
210
VSS
213
VSS
214
VSS
217
VSS
218
VSS
222
VSS
223
VSS
226
VSS
227
VSS
230
VSS
231
VSS
234
VSS
235
VSS
238
VSS
239
VSS
243
VSS
244
VSS
247
VSS
248
VSS
251
VSS
252
GND
261
C
D
3
0
1
U
_
0
2
0
1
_
6
.
3
V
6
M
1
2
CD15
0.022U_0402_16V7K
1
2
C
D
7
1
0
U
_
0
4
0
2
_
6
.
3
V
6
M
1
2
RD8
1K_0402_1%
1 2
RD10
1K_0402_1%
1 2
C
D
1
0
.
1
U
_
0
2
0
1
_
1
0
V
6
K
1
2
C
D
2
5
1
U
_
0
2
0
1
_
6
.
3
V
6
M
1
2
C
D
2
9
1
U
_
0
2
0
1
_
6
.
3
V
6
M
1
2
C
D
2
6
1
U
_
0
2
0
1
_
6
.
3
V
6
M
1
2
C
D
9
1
U
_
0
2
0
1
_
6
.
3
V
6
M
1
2
CD10
33P_0201_50V8J
ESD@
1
2
CD14
0.1U_0201_10V6K
1
2
RD9
2_0402_1%
1 2
RD11
24.9_0402_1%
1 2
C
D
1
9
1
0
U
_
0
4
0
2
_
6
.
3
V
6
M
1
2
+
CD32
330U_D2_2V_Y
1
2
C
D
2
1
1
0
U
_
0
4
0
2
_
6
.
3
V
6
M
1
2
CD12
2.2U_0402_6.3V6M
1
2
C
D
2
2
1
0
U
_
0
4
0
2
_
6
.
3
V
6
M
@
1
2
C
D
3
1
0
U
_
0
4
0
2
_
6
.
3
V
6
M
1
2
C
D
2
0
1
0
U
_
0
4
0
2
_
6
.
3
V
6
M
1
2
C
D
8
1
0
U
_
0
4
0
2
_
6
.
3
V
6
M
1
2
C
D
2
2
.
2
U
_
0
4
0
2
_
6
.
3
V
6
M
1
2
C
D
6
1
U
_
0
2
0
1
_
6
.
3
V
6
M
1
2
C
D
1
8
1
0
U
_
0
4
0
2
_
6
.
3
V
6
M
1
2
RD7 240_0402_1%
12
C
D
2
7
1
U
_
0
2
0
1
_
6
.
3
V
6
M
1
2
CD11
0.1U_0201_10V6K
1
2
C
D
2
4
1
U
_
0
2
0
1
_
6
.
3
V
6
M
1
2
C
D
1
7
1
0
U
_
0
4
0
2
_
6
.
3
V
6
M
1
2
CD13
0.1U_0201_10V6K
@
1
2
REVERSE
JDIMM1A
LOTES_ADDR0206-P001A
CONN@
ACT#
114
ALERT#
116
BA0
150
BA1
145
BG0
115
BG1
113
CB0_NC
92
CB1_NC
91
CB2_NC
101
CB3_NC
105
CB4_NC
88
CB5_NC
87
CB6_NC
100
CB7_NC
104
CK0#(C)
139
CK0(T)
137
CK1#(C)
140
CK1(T)
138
CKE0
109
CKE1
110
DM0#/DBI0#
12
DM1#/DBI1#
33
DM2#/DBI2#
54
DM3#/DBI3#
75
DM4#/DBI4#
178
DM5#/DBI5#
199
DM6#/DBI6#
220
DM7#/DBI7#
241
DM8#/DBI8#
96
DQS8#(C)
95
DQS8(T)
97
ODT0
155
ODT1
161
PARITY
143
S0#
149
S1#
157
S3#/C1
165
SCL
253
A0
144
A1
133
A10_AP
146
A11
120
A12
119
A13
158
A14_WE#
151
A15_CAS#
156
A16_RAS#
152
A2
132
A3
131
A4
128
A5
126
A6
127
A7
122
A8
125
A9
121
DQ0
8
DQ1
7
DQ10
41
DQ11
42
DQ12
24
DQ13
25
DQ14
38
DQ15
37
DQ16
50
DQ17
49
DQ18
62
DQ19
63
DQ2
20
DQ20
46
DQ21
45
DQ22
58
DQ23
59
DQ24
70
DQ25
71
DQ26
83
DQ27
84
DQ28
66
DQ29
67
DQ3
21
DQ30
79
DQ31
80
DQ32
174
DQ33
173
DQ34
187
DQ35
186
DQ36
170
DQ37
169
DQ38
183
DQ39
182
DQ4
4
DQ40
195
DQ41
194
DQ42
207
DQ43
208
DQ44
191
DQ45
190
DQ46
203
DQ47
204
DQ48
216
DQ49
215
DQ5
3
DQ50
228
DQ51
229
DQ52
211
DQ53
212
DQ54
224
DQ55
225
DQ56
237
DQ57
236
DQ58
249
DQ59
250
DQ6
16
DQ60
232
DQ61
233
DQ62
245
DQ63
246
DQ7
17
DQ8
28
DQ9
29
DQS0#(C)
11
DQS0(T)
13
DQS1#(C)
32
DQS1(T)
34
DQS2#(C)
53
DQS2(T)
55
DQS3#(C)
74
DQS3(T)
76
DQS4#(C)
177
DQS4(T)
179
DQS5#(C)
198
DQS5(T)
200
DQS6#(C)
219
DQS6(T)
221
DQS7#(C)
240
DQS7(T)
242
EVENT#
134
RESET#
108
S2#/C0
162
SA0
256
SA1
260
SA2
166
SDA
254
C
D
1
6
1
0
U
_
0
4
0
2
_
6
.
3
V
6
M
1
2
C
D
5
1
U
_
0
2
0
1
_
6
.
3
V
6
M
1
2
C
D
2
8
1
U
_
0
2
0
1
_
6
.
3
V
6
M
1
2
www.laptoprepairsecrets.com
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
SPD ADDRESS FOR CHANNEL B :
WRITE ADDRESS: 0XA4
READ ADDRESS: 0XA3
SA0 = 0; SA1 = 1; SA2 = 0.
DDR4 POR OPERATING SPEED: 1867 MT/S
STRETCH GOAL IS 2133 MT/S
10uF*6
1uF*8
330uF*1
Layout Note:
Place near JDIMM3
Layout Note:
Place near JDIMM3.257,259
Layout Note:
Place near JDIMM3.258
Layout Note:
PLACE THE CAP WITHIN 200 MILS
FROM THE JDIMM3
CPU Side
DIMM Side
10uF*2
1uF*2
10uF*2
1uF*1
2.2uF*1
0.1uF*1
For ECC DIMM
PLACE NEAR TO PIN
VREF traces should be at least 20 mils
wide with 20 mils spacing to other
signals
Part Number: SP07001HW00
Part Value: S SOCKET LOTES ADDR0205-P001A DDR4 STD
CHANNEL-B ( Interleaved Memory )
> BOT : STD type (4mm)
> Non-ECC SO-DIMM
DDR_B_CLK0
DDR_B_CLK#0
DDR_B_CLK1
DDR_B_CLK#1
DDR_B_CKE0
DDR_B_CKE1
DDR_B_CS#0
DDR_B_CS#1
DDR_B_ODT0
DDR_B_ODT1
DIMM3_CHB_EVENT#
DDR_DRAMRST#_R
DDR_B_DQS1
DDR_B_DQS#1
DDR_B_DQS2
DDR_B_DQS#2
DDR_B_DQS3
DDR_B_DQS#3
DDR_B_DQS4
DDR_B_DQS#4
DDR_B_DQS5
DDR_B_DQS#5
DDR_B_DQS6
DDR_B_DQS#6
DDR_B_DQS7
DDR_B_DQS#7
DDR_B_DQS0
DDR_B_DQS#0
DDR_B_BG1
DDR_B_BG0
DDR_B_BA1
DDR_B_BA0
DDR_B_MA1
DDR_B_MA0
DDR_B_MA3
DDR_B_MA2
DDR_B_MA5
DDR_B_MA4
DDR_B_MA7
DDR_B_MA6
DDR_B_MA9
DDR_B_MA8
DDR_B_MA10
DDR_B_MA12
DDR_B_MA11
DDR_B_MA13
DDR_B_MA14_WE#
DDR_B_MA15_CAS#
DDR_B_MA16_RAS#
DDR_B_ACT#
DDR_B_ALERT#
DDR_B_PAR
DDR_B_D31
DDR_B_D63
DDR_B_D58
DDR_B_D50
DDR_B_D38
DDR_B_D60
DDR_B_D39
DDR_B_D35
DDR_B_D34
DDR_B_D2
DDR_B_D33
DDR_B_D3
DDR_B_D4
DDR_B_D37
DDR_B_D5
DDR_B_D6
DDR_B_D36
DDR_B_D32
DDR_B_D49
DDR_B_D53
DDR_B_D51
DDR_B_D54
DDR_B_D52
DDR_B_D55
DDR_B_D56
DDR_B_D59
DDR_B_D16
DDR_B_D61
DDR_B_D17
DDR_B_D14
DDR_B_D62
DDR_B_D10
DDR_B_D13
DDR_B_D12
DDR_B_D11
DDR_B_D15
DDR_B_D9
DDR_B_D8
DDR_B_D18
DDR_B_D40
DDR_B_D22
DDR_B_D41
DDR_B_D42
DDR_B_D23
DDR_B_D43
DDR_B_D44
DDR_B_D21
DDR_B_D45
DDR_B_D46
DDR_B_D19
DDR_B_D7
DDR_B_D47
DDR_B_D48
DDR_B_D0
DDR_B_D1
DDR_B_D20
DDR_B_D57
DDR_B_D24
DDR_B_D25
DDR_B_D29
DDR_B_D30
DDR_B_D27
DDR_B_D26
DDR_B_D28
DDR_B_CLK0<8>
DDR_B_CLK#0<8>
DDR_B_CLK1<8>
DDR_B_CLK#1<8>
DDR_B_CKE0<8>
DDR_B_CKE1<8>
DDR_B_CS#0<8>
DDR_B_CS#1<8>
DDR_B_ODT0<8>
DDR_B_ODT1<8>
DDR_B_D[16..31]<8>
DDR_B_D[0..15]<8>
DDR_B_D[48..63]<8>
DDR_B_D[32..47]<8>
DDR_B_DQS0 <8>
DDR_B_DQS#0 <8>
DDR_B_DQS1 <8>
DDR_B_DQS#1 <8>
DDR_B_DQS2 <8>
DDR_B_DQS#2 <8>
DDR_B_DQS3 <8>
DDR_B_DQS#3 <8>
DDR_B_DQS4 <8>
DDR_B_DQS#4 <8>
DDR_B_DQS5 <8>
DDR_B_DQS#5 <8>
DDR_B_DQS6 <8>
DDR_B_DQS#6 <8>
DDR_B_DQS7 <8>
DDR_B_DQS#7 <8>
DDR_B_BG0<8>
DDR_B_BG1<8>
DDR_B_BA0<8>
DDR_B_BA1<8>
DDR_B_MA14_WE#<8>
DDR_B_MA15_CAS#<8>
DDR_B_MA16_RAS#<8>
DDR_B_MA0<8>
DDR_B_MA1<8>
DDR_B_MA2<8>
DDR_B_MA3<8>
DDR_B_MA4<8>
DDR_B_MA5<8>
DDR_B_MA6<8>
DDR_B_MA7<8>
DDR_B_MA8<8>
DDR_B_MA9<8>
DDR_B_MA10<8>
DDR_B_MA11<8>
DDR_B_MA12<8>
DDR_B_MA13<8>
DDR_B_ACT#<8>
DDR_B_PAR<8>
DDR_B_ALERT#<8>
DDR_DRAMRST#_R<18,23>
D_CK_SCLK<18,23>
D_CK_SDATA<18,23>
+0.6V_DDRB_VREFCA
+1.2V_VDDQ
+0.6V_DDRB_VREFCA
+1.2V_VDDQ+1.2V_VDDQ
+0.6VS_VTT+2.5V
+0.6V_B_VREFDQ
+0.6V_DDRB_VREFCA
+1.2V_VDDQ
+0.6VS_VTT
+2.5V
+3VS
+1.2V_VDDQ
+1.2V_VDDQ
+1.2V_VDDQ
+3VS
Title
Size Document Number R ev
Date: Sheet o f
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
FH51M M/B LA-J871P
1.0
24 112Tuesday, February 11, 2020
2019/09/20 2020/09/20
Compal Electronics, Inc.
DDRIV_CHB: DIMM0
Title
Size Document Number R ev
Date: Sheet o f
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
FH51M M/B LA-J871P
1.0
24 112Tuesday, February 11, 2020
2019/09/20 2020/09/20
Compal Electronics, Inc.
DDRIV_CHB: DIMM0
Title
Size Document Number R ev
Date: Sheet o f
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
FH51M M/B LA-J871P
1.0
24 112Tuesday, February 11, 2020
2019/09/20 2020/09/20
Compal Electronics, Inc.
DDRIV_CHB: DIMM0
C
D
4
8
1
0
U
_
0
4
0
2
_
6
.
3
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6
M
1
2
C
D
3
4
2
.
2
U
_
0
4
0
2
_
6
.
3
V
6
M
1
2
CD55
0.022U_0402_16V7K
1
2
C
D
4
9
1
0
U
_
0
4
0
2
_
6
.
3
V
6
M
1
2
C
D
3
6
1
0
U
_
0
4
0
2
_
6
.
3
V
6
M
1
2
C
D
3
3
0
.
1
U
_
0
2
0
1
_
1
0
V
6
K
1
2
C
D
5
0
1
0
U
_
0
4
0
2
_
6
.
3
V
6
M
1
2
CD43
2.2U_0402_6.3V6M
1
2
C
D
3
5
1
0
U
_
0
4
0
2
_
6
.
3
V
6
M
1
2
RD19
1K_0402_1%
1 2
C
D
5
7
1
U
_
0
2
0
1
_
6
.
3
V
6
M
1
2
CD51
0.1U_0201_10V6K
1
2
C
D
3
8
1
U
_
0
2
0
1
_
6
.
3
V
6
M
1
2
C
D
4
7
1
0
U
_
0
4
0
2
_
6
.
3
V
6
M
1
2
RD22
24.9_0402_1%
1 2
C
D
6
0
1
U
_
0
2
0
1
_
6
.
3
V
6
M
1
2
C
D
5
2
1
0
U
_
0
4
0
2
_
6
.
3
V
6
M
1
2
C
D
4
6
1
0
U
_
0
4
0
2
_
6
.
3
V
6
M
1
2
CD45
0.1U_0201_10V6K
1
2
C
D
3
9
1
0
U
_
0
4
0
2
_
6
.
3
V
6
M
1
2
C
D
5
8
1
U
_
0
2
0
1
_
6
.
3
V
6
M
1
2
C
D
5
3
1
0
U
_
0
4
0
2
_
6
.
3
V
6
M
@
1
2
RD20
2_0402_1%
1 2
C
D
6
1
1
U
_
0
2
0
1
_
6
.
3
V
6
M
1
2
RD18
240_0402_1%
12
C
D
4
1
1
U
_
0
2
0
1
_
6
.
3
V
6
M
1
2
C
D
5
4
1
0
U
_
0
4
0
2
_
6
.
3
V
6
M
@
1
2
C
D
4
0
1
0
U
_
0
4
0
2
_
6
.
3
V
6
M
1
2
C
D
6
3
1
U
_
0
2
0
1
_
6
.
3
V
6
M
1
2
C
D
3
7
1
U
_
0
2
0
1
_
6
.
3
V
6
M
1
2
STD
JDIMM2A
LOTES_ADDR0205-P001A
CONN@
ACT#
114
ALERT#
116
BA0
150
BA1
145
BG0
115
BG1
113
CB0_NC
92
CB1_NC
91
CB2_NC
101
CB3_NC
105
CB4_NC
88
CB5_NC
87
CB6_NC
100
CB7_NC
104
CK0#(C)
139
CK0(T)
137
CK1#(C)
140
CK1(T)
138
CKE0
109
CKE1
110
DM0#/DBI0#
12
DM1#/DBI1#
33
DM2#/DBI2#
54
DM3#/DBI3#
75
DM4#/DBI4#
178
DM5#/DBI5#
199
DM6#/DBI6#
220
DM7#/DBI7#
241
DM8#/DBI8#
96
DQS8#(C)
95
DQS8(T)
97
ODT0
155
ODT1
161
PARITY
143
S0#
149
S1#
157
S3#/C1
165
SCL
253
A0
144
A1
133
A10_AP
146
A11
120
A12
119
A13
158
A14_WE#
151
A15_CAS#
156
A16_RAS#
152
A2
132
A3
131
A4
128
A5
126
A6
127
A7
122
A8
125
A9
121
DQ0
8
DQ1
7
DQ10
41
DQ11
42
DQ12
24
DQ13
25
DQ14
38
DQ15
37
DQ16
50
DQ17
49
DQ18
62
DQ19
63
DQ2
20
DQ20
46
DQ21
45
DQ22
58
DQ23
59
DQ24
70
DQ25
71
DQ26
83
DQ27
84
DQ28
66
DQ29
67
DQ3
21
DQ30
79
DQ31
80
DQ32
174
DQ33
173
DQ34
187
DQ35
186
DQ36
170
DQ37
169
DQ38
183
DQ39
182
DQ4
4
DQ40
195
DQ41
194
DQ42
207
DQ43
208
DQ44
191
DQ45
190
DQ46
203
DQ47
204
DQ48
216
DQ49
215
DQ5
3
DQ50
228
DQ51
229
DQ52
211
DQ53
212
DQ54
224
DQ55
225
DQ56
237
DQ57
236
DQ58
249
DQ59
250
DQ6
16
DQ60
232
DQ61
233
DQ62
245
DQ63
246
DQ7
17
DQ8
28
DQ9
29
DQS0#(C)
11
DQS0(T)
13
DQS1#(C)
32
DQS1(T)
34
DQS2#(C)
53
DQS2(T)
55
DQS3#(C)
74
DQS3(T)
76
DQS4#(C)
177
DQS4(T)
179
DQS5#(C)
198
DQS5(T)
200
DQS6#(C)
219
DQS6(T)
221
DQS7#(C)
240
DQS7(T)
242
EVENT#
134
RESET#
108
S2#/C0
162
SA0
256
SA1
260
SA2
166
SDA
254
GND1
261
GND2
262
STD
JDIMM2B
LOTES_ADDR0205-P001A
CONN@
VDD1
111
VDD2
112
VDD3
117
VDD4
118
VDD5
123
VDD6
124
VDD7
129
VDD8
130
VDD9
135
VDD10
136
VDDSPD
255
VREFCA
164
VSS
1
VSS
2
VSS
5
VSS
6
VSS
9
VSS
10
VSS
14
VSS
15
VSS
18
VSS
19
VSS
22
VSS
23
VSS
26
VSS
27
VSS
30
VSS
31
VSS
35
VSS
36
VSS
39
VSS
40
VSS
43
VSS
44
VSS
47
VSS
48
VSS
51
VSS
52
VSS
56
VSS
57
VSS
60
VSS
61
VSS
64
VSS
65
VSS
68
VSS
69
VSS
72
VSS
73
VSS
77
VSS
78
VSS
81
VSS
82
VSS
85
VSS
86
VSS
89
VSS
90
VSS
93
VSS
94
VSS
98
GND
262
VDD11
141
VDD12
142
VDD13
147
VDD14
148
VDD15
153
VDD16
154
VDD17
159
VDD18
160
VDD19
163
VTT
258
VPP1
257
VPP2
259
VSS
99
VSS
102
VSS
103
VSS
106
VSS
107
VSS
167
VSS
168
VSS
171
VSS
172
VSS
175
VSS
176
VSS
180
VSS
181
VSS
184
VSS
185
VSS
188
VSS
189
VSS
192
VSS
193
VSS
196
VSS
197
VSS
201
VSS
202
VSS
205
VSS
206
VSS
209
VSS
210
VSS
213
VSS
214
VSS
217
VSS
218
VSS
222
VSS
223
VSS
226
VSS
227
VSS
230
VSS
231
VSS
234
VSS
235
VSS
238
VSS
239
VSS
243
VSS
244
VSS
247
VSS
248
VSS
251
VSS
252
GND
261
CD42
0.1U_0201_10V6K
1
2
C
D
5
9
1
U
_
0
2
0
1
_
6
.
3
V
6
M
1
2
RD21
1K_0402_1%
1 2
C
D
5
6
1
U
_
0
2
0
1
_
6
.
3
V
6
M
1
2
C
D
6
2
1
U
_
0
2
0
1
_
6
.
3
V
6
M
1
2
CD44
0.1U_0201_10V6K
@
1
2
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