Acer Nitro 5 AN515-54 Schematic

A

1 1

B

C

D

E

Compal Confidential

EH50F/EH51F

2 2

EH5VF/EH70F

MB Schematic Document

LA-H501P

3 3

Rev:1A

2019.02.22

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

2017/10/ 30 2018/10/ 30

2017/10/ 30 2018/10/ 30

2017/10/ 30 2018/10/ 30

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Cover Sheet

Cover Sheet

Cover Sheet

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

D

EH5VF M/B LA-H501P

EH5VF M/B LA-H501P

EH5VF M/B LA-H501P

Date : Sheet o f

Date : Sheet o f

Date : Sheet o f

1 1 01Friday, February 22, 2019

1 1 01Friday, February 22, 2019

1 1 01Friday, February 22, 2019

E

1A

1A

1A

A

B

C

D

E

1 1

HDMI Conn.

eDP

Fan Control*2

page 77

Interleaved Memory

page 40

HDMI x 4 lanes

N18P-G0 with gDDR5 x4
or
N17P-G0-K1 with gDDR5 x3

page 25~36

page 38

eDP

PEG x16
8GT/s

CoffeeLake H Processor
BGA1440
(42X28) (CFL-H_6+2)

Processor

page 06~13

Memory BUS

Dual Channel

1.2V DDR4 2400/2666

260 pin DDR4-SO-DIMM X1

BANK 0, 1, 2, 3

page 23

260pin DDR4-SO-DIMM X1

BANK 4, 5, 6, 7

page 24

USB 3.0
conn x1

USB (port 1)

USB 3.0
Type-C

USB (port 2)

page 72 page 38

Int. Speaker

48MHz

HD Audio

page 16

USB 3.0
conn x1

USB (port 3)

3.3V 24MHz

2 2

3 3

NGFF

WLAN

USB port 7

RTC CKT.

Power On/Off CKT.

page 52

PCIE 1.0

2.5GT/s

port 15

page 20

page 63

page 68

PCIE 3.0 x4
8GT/s
Port 9-12

page 51

PCIE 2.0
5GT/s

port 14

LAN(GbE)

Realtek 8118ASA

RJ45 conn.

page 32.

Sub Board

HS/B

IO/B

Flexible IO

SATA Re-Driver

PARADE PS8527

SATA HDD Conn.

page 47

page 66

page 73

page 68

PCIE 3.0 x4
8GT/s
Port 21-24

page 67

SATA3.0

6.0 Gb/s

port 4

Cannonlake PCH - H
FCBGA(25X24)

874pin FCBGA

LPC/eSPI BUS

CLK=24MHz

ENE
KB9022

Touch Pad Int.KBD

PS2 / I2C

page 63

page 58

X4 DMI

page 63

page 14~21

TPM

page 66

USBx8

SPI

SPI ROM x1

page 42,43

page 42

CMOS
Camera

USB (port 5)

HDA Codec

ALC255

Int. DMIC
on Camera/B

Finger_Print

USB (port 8)

page 66

page 42

UAJ

page 48 page 48

on Sub/B

USB charger

SLGC55544

page 71

DC/DC Interface CKT.

page 78

4 4

Power Circuit DC/DC

page 81~97

A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

C

2017/07/20 2018/07/20

2017/07/20 2018/07/20

2017/07/20 2018/07/20

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Nu mber R ev

Size Document Nu mber R ev

Size Document Nu mber Re v

Custom

Custom

Custom

Date : Sheet of

Date : Sheet of

D

Date : Sheet of

Compal Electronics, Inc.

Block Diagrams

Block Diagrams

Block Diagrams

EH5VF M/B LA-H501P

EH5VF M/B LA-H501P

EH5VF M/B LA-H501P

E

1A

1A

2 101Friday, February 22, 2019

2 101Friday, February 22, 2019

2 101Friday, February 22, 2019

1A

A

B

C

D

E

Board ID Table for AD channel

Vcc 3.3V +/- 5%
Ra

Board ID

1 1

2 2

100K +/- 1%

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19

0
12K +/- 1% 0.347 V 0.345 V 0.360 V
15K +/- 1%
20K +/- 1%
27K +/- 1%
33K +/- 1%
43K +/- 1%
56K +/- 1%
75K +/- 1%
100K +/- 1%
130K +/- 1%
160K +/- 1%
200K +/- 1%
240K +/- 1%
270K +/- 1%
330K +/- 1%
430K +/- 1%
560K +/- 1%
750K +/- 1%

NC

Rb V min

BID

0.423 V 0.430 V 0.438 V

1.398 V

1.634 V

1.849 V

2.015 V

2.185 V

2.316 V

2.395 V

2.521 V

2.667 V

2.791 V

2.905 V

3.000 V

V typ

BID

0.000 V

1.414 V

1.650 V

1.865 V

2.031 V

2.200 V

2.329 V

2.408 V

2.533 V

2.677 V

2.800 V

2.912 V

3.000 V

V

BID

0.300 V

1.430 V

1.667 V

1.881 V

2.046 V

2.215 V

2.343 V

2.421 V

2.544 V

2.687 V

2.808 V

2.919 V

max

EC AD

0x00 - 0x13
0x14 - 0x1E
0x1F - 0x25
0x26 - 0x300.541 V 0.550 V 0.559 V
0x31 - 0x3A0.691 V 0.702 V 0.713 V
0x3B - 0x450.807 V 0.819 V 0.831 V
0x46 - 0x540.978 V 0.992 V 1.006 V
0x55 - 0x641.169 V 1.185 V 1.200 V
0x65 - 0x76
0x77 - 0x87
0x88 - 0x96
0x97 - 0xA4
0xA5 - 0xAF
0xB0 - 0xB7
0xB8 - 0xBF
0xC0 - 0xC9
0xCA - 0xD4
0xD5 - 0xDD
0xDE - 0xF0
0xF1 - 0xFF

I2C Address Table

BUS

Device

Address(7 bit)

I2C_0 (+3VS)
I2C_1 (+3VS)

TM-P3393-003 (Touch Pad)
SA577C-12A0 (Touch Pad)

PCH_SMBCLK

(+3VS)

PCH_SML1CLK
EC_SMB_CK2

(+3VS)

EC_SMB_CK1
(+3VLP)

3 3

EC_SMB_CK3
(+3VALW)

DIMM1
DIMM2

N18P-G0/N17P-G0-K1 (VGA)

Thermal Sensor (W83L771)

0x9E

1001_100xb 1001_1001b 1001_1000b

PCH 0x90

BQ24780 (Charger IC)

BATTERY PACK

0x12
0x16

LED driver 0xC0

Address( 8bit)

Write Rea d

BOM Structure Table

BOM Option Table

Ite m BOM Structure

Unpop

Connector

CMC CMC@
dGPU circuit VGA@

N17P GPU N17P@
TPM TPM@

For Acer IOAC
No Acer IOAC

KB LED driver LED14P@
OVRM-ON ON_X76@
OVRM-uPI

Thermal sensor
for SW debug board
Intel CNVi
Finger Print

EMI require reserve
ESD requirement ESD@

FP ESD requirement FPESD@
Pidgey ESD requirement PGESD@
SATA HDD W REDRIVER
SATA HDD WO REDRIVER

i5 CPU i5@
i7 CPU
H62 CPU H62@

LAN LDO mode LDO@
LAN Switch mode

@

CONN@

N18P@N18P GPU

IOAC@
NIOAC@
KBLED@KB backlight

uPI_X76@

TMS@

UART@
CNVI@

FP@

PBA@FinerPrint(with PBA)

EMI@EMI requirement
XEMI@

XESD@ESD require reserve

SATARD@
SATANRD@

i7@

H82@H82 CPU

SWR@

Power State

STATE

S0 (Full ON) ON ON ON ONHIGH HIGH HIGH

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

SIGNA L

SLP_S3 # SLP_S 4# SLP_ S5# +VALW +V +V S Clock

LOW HIGH

HIGH

LOWLOW

HIGH

Voltage Rails

Power Plane

+RTCVCC

+19V_VIN

+12.6V_B ATT Battery power supply

+19VB

+3VLP

+5VALW

+3VALW System +3VALW always on power rail

+3VALW_DSW +3VALW power for PCH DSW rails

+1.05VALW +1.05V Always power rail

+1.05V_VCCST

+5VS System +5V power rail

+3VS

+1.05VS_VCCSTG +1.05VALW_PRIM Gated version of VCCST

+0.6VS_VTT DDR +0.6VS power rail for DDR terminator .

+VCC_CORE

+VCC_GT

+VCCIO

+VCC_SA

+1.8VSDGPU_AON

+NVVDD1

+1.35VSDGPU +1.35VS power rail for GPU

+1.0VSDGPU

+1.8VALW System +1.8VALW always on power rail

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

Description

RTC Battery Power

Adapter power supply

AC or battery power r ail for power circuit.

+19VB to +3VLP power rail for suspend power

+5V Always power rail

DDR4 +1.2V power rail+1.2V_VDDQ

Sustain voltage for processor in Standby modes

System +3V power rail

Core voltage for CPU

Sliced graphics power r ail

CPU IO +0.95VS power r ail

System Agent power rail

+1.8VS power rail for GPU(AON rails)

+1.8VS power rail for GPU GC6+1.8VSDGPU_MAIN

Core voltage for VGA (merge core & core_s)

+1.0VS power rail for GPU

ONONON

ON

OFF

OFFLOW LOW LOW

OFF

OFF

OFF

OFF

OFF

OFF

S0

S3

ON

ON

N/A N/A N/A

N/A

N/A

N/A

N/A

ON

ON

ON

ON

ON

ON

ON

ON

ON

ON

ON

ON ON

ON

ON

ON

ON

ON

ON

ON

ON

ON

ON

ON

ON

ON

ON

ON

OFF

OFF

OFF

OFF

OFF OFF

OFF OFF OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF OFF OFF

OFF

OFF

OFF OFF

OFF

OFF OFF

OFF OFF

OFF OFF OFF

OFF OFF OFF

ONON

S4

ON ON

N/A N/A

ON ON

ON ON

ON

ON ON

ON

S5

N/AN/AN/A

ON*

ON

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFFOFF

OFF

ON*

43 level BOM table

BOARD ID Table

BOM Structure43 Level Descr ipt io n

431AC5BO L01

4 4

SMT MB AF952 DH53F I5PG1 4G 28P 8L HDMI 255@/CHG@/CMC@/CN VI@/FP@/G0@ /I5@/IOAC@/ LDO@/SAT ARD@ /TYP EC@/ V15@ /VGA @/X7 6@

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

C

Compal Secret Data

Compal Secret Data

2017/10/30 2018/10/30

2017/10/30 2018/10/30

2017/10/30 2018/10/30

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

Board ID

0
1
2
3
4
5
6
7
8
9

PCB Revision

2050 Rev0.1
2050 Rev0.2
2050 Rev0.3
2050 Rev1.0/1A
2060 Rev0.1
2060 Rev0.2
2060 Rev0.3
2060 Rev1.0

Board ID

10
11
12
13
14
15
16
17
18

PCB Revision

19

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Notes List

Notes List

Notes List

Size Document Nu mber R ev

Size Document Nu mber R ev

Size Document Nu mber R ev

Custom

Custom

Custom

EH5VF M/B LA-H501P

EH5VF M/B LA-H501P

EH5VF M/B LA-H501P

Date : Sheet of

Date : Sheet of

Date : Sheet of

E

1A

1A

3 101Friday, February 22, 2019

3 101Friday, February 22, 2019

3 101Friday, February 22, 2019

1A

5

Vinafix

4

3

2

1

DC_IN

PJP101

AC CONN.

D D

C C

B B

A A

PL101,2,3

PUB1

CHARGER

+19V_V IN

+12.6V _BAT T

5

PL201,2

IMVP8

PUZ2,3,4,5

+19VB

EN:DRV ON

+19VB

+19VB

+19VB

+19VB

+19VB

+19VB

+19VB

+19VB

+19VB

+19VB

PRG5

EN:DRV ON

PRA3

EN:DRV ON

EN:3V_ EN

PU301

EN:SYS ON

PUM1

PU1101

EN:+1. 8_PG

PUH1 PJH1

EN:SUS P#

PU1801 PJ180 1

EN:SPO K_3V

PU501

PUV1

EN:1.35 VSDGP U_EN

PUW1

+19VB → +19VB_CPU

+12.6V_BATT+

PJP201

+19VB_C PU

PLZ1,2,3,4

+19VB_C PU

PLG1

+19VB_C PU

PLA1

+3VALWP

PJ302

+1.2VP

PJM2

EN:SM_P G_CT RL

+0.6VSP

PJM3

+1.05VAL WP

PJ1101

+1.0VS_V CCIOP

+1.8VAL WP

+5VALWP

PJ502

NVVDD_B +

PUV2,3

GPU_B+

PLW1

LX1

BATTERY

+VCC_C ORE

+VCC_ GT

+VCC_ SA

+3VAL W

EC,LID

+3VLP

CPU,Memory

+1.2V_ VDDQ

+0.6VS _VTT

+1.05V ALW

+VCCI O

+1.8VA LW

+5VAL W

PLV2,3

GPU

+1.35V SDGP U

+INVPW R_B+

4

CPU

CPU

CPU

CPU

+NVVD D1

PANEL

RC24

GPU

+1.2V_V CCPL L_OC

EN:DGPU _PWR _EN

+1.8VSD GPU_ AON

+1.8VSD GPU_ MAIN

UG27

UQ2

RH100

+ 1.8VALW _PRIM

RQ9

RS127

JIO1

US11

US12

US13

UE5

UK2

CPU

+1.8V S

PCH

UV48

GPU

RA3

+5VALW _MUX

+5VAL W

+USB3_ VCCC

+USB_V CCA

+USB_V CCB

+5V_LE DPWR

+FP_V CC

JPQ2UQ1

+2.5V P

PU2501 PJ2502

+1.0VS DGPU P

PU1002 PJ1003

UQ1

R19

UM1

UL1

UK1

UM2

UM2

RH101

RH99

UK2

JPH1

RH94

UQ2

UC4

JPQ1

+3VALW _TPM

+3VS_W LAN

+3V_L AN

+3V_P TP

RM54

RM55

+3VALW _HDA

+3VALW _DSW

+FP_V CC

+FP_FUS E_GP U

+1.8VS _VDD A

US3

JIO1

JTYPEC1

JUSB1

JUSB2

JBL2

JFP1

+5VS

3

+2.5V

+1.0VS DGPU

+3VS

+3VS_S SD1

+3VS_S SD2

+1.05VA LW_P RIM

+1.05VA LW_P CH

RH102

RH103

RH105

+1.05V_ VCCS T

RQ5

+1.05VS _VCC STG

GPU

CODEC

CC logic/U3 MUX

IO/B Conn.

Type-C Conn.

USB3.0 Conn.

USB3.0 Conn.

KB BackLight Conn.

FP Conn.

GPU

U5

TPM

JNGFF1

WLAN CARD Conn.

UL2

LAN

JTP1

TP Conn.

JSSD1

SSD Conn.

JSSD2

SSD Conn.

PCH

PCH

JFP1

FP Conn.

PCH

PCH

+1.05VA LW_VC CAZP LL

+1.05VAL W_VCC AMPH YPLL

+1.05VA LW_X TAL

CPU

JDIMM1

DDR4 Conn.

JDIMM2

UO1

UV45

R20

UX1

RA2

RA4

PCH

RF4

RF7

JPA1

U4

RO4

UY2

RX7 JEDP1

+VCC_F AN1

+VCC_F AN2

+VDDA

+5VS_ BL

+5VS_H DD

+HDMI_5 V_OU T

JFAN1

JFAN1

UA1

JBL1

JHDD1

JHDMI1

+TS_P WR

Security Classificati on

Security Classificati on

Security Classificati on

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY O F THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY O F THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY O F THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WR ITTEN CONSENT O F CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WR ITTEN CONSENT O F CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WR ITTEN CONSENT O F CO MPAL ELECTRONICS, INC.

2

+3VS

+3VSDG PU

+3VS_W LAN

+3VS_T PM

+LCDV DD

+3VS_D VDDI O

+3VS_D VDD

SATA Re-driver

GPU

JNGFF1RM11

U5

JEDP1

CODEC

CODEC

FAN1 Conn.

FAN2 Conn.

CODEC

KB BackLight Conn.

HDD Conn.

HDMI Conn.

Touch Screen

Compal Secret Data

Compal Secret Data

Compal Secret Data

2017/10/30 2018/1 0/30

2017/10/30 2018/1 0/30

2017/10/30 2018/1 0/30

Deciphered Date

Deciphered Date

Deciphered Date

WLAN CARD Conn.

TPM

PANEL

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Power Map

Power Map

Power Map

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

EH5VF M/B LA-H501P

EH5VF M/B LA-H501P

EH5VF M/B LA-H501P

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

4 101Friday, February 22, 2019

4 101Friday, February 22, 2019

4 101Friday, February 22, 2019

1A

1A

1A

A

BIOS ver: V0.02W1
EC: ver: V002AT0 4

1 1

AC mo deDH5VF_EVT P ower Sequenc e

B

C

D

E

Plug in

+3VLP

EC_ON

+5VALW

ON/OFFBT N#

+3VALW

+1.05VAL W

EC_RSMRS T#

PBTN_OUT #

PM_SLP_S 4#

PM_SLP_S 3#

2 2

3 3

SYSON

+1.05V_V CCST

+1.2V_VD DQ

+2.5VS

SUSP#

+1.05VS_ VCCSTG

+5VS

+3VS

+1.8VS

EC_VCCST _PG

SM_PG_CT RL

+0.6VS_V TT

VR_ON

+VCC_S A

+VCC_COR E

+VCC_G T

PCH_PWRO K

SYS_PWRO K

PLT_RST #

→

→

330.8ms

333.3ms

→

92.03ms

→

94.88ms

2.439ms

→

→

174.6ms

29.19ms

20.1ms

← →

→

→

Power On

19.18ms

19.22ms

72.1us

→

275.9us

→

692.9us

→
→

910.1us

→

12.7ms

8.378us

→

→

→

412us

→

→

→

→

→

877.7us

630.4us

25.34ms

25.35ms

25.36ms

25.19ms

→

→

→

→

→

→

→

→

1.759ms

173.0ms

NA

12.42ms

150.3ms

152.3ms 318.7us

→

S3 S3 Resume

Power Off

100.5us

152.8us

→

88.37us

→

367.6us

→

→

13.01us

55.47us

→

618.5us

→

8.679ms

→

347.6us

→

0us

→

0us 13.97ms

→

3.819ms

→

26.91us

51.25us

→

87.75us

→

NA

→

47.39us

→

61.95us

→

→

67.04ms

→

→

→

→

→

→

→

→

8.502us

906.0us

656.1us

424.9us

25.25ms

25.25ms

25.26ms

25.59ms

→

→

→

→

→

→

1.757ms

167.1ms

NA

12.18ms

150.6ms

151.8ms

→

→

→

→

→

0us

→

→

27.06us

→

→

NA

→

→

13us

686.0us

2.034ms

48.00us

112.0us

47.83us

62.37us

2.266ms

68.53us

11.65ms

446.2us

→

293.7us

+3VLP

EC_ON

+5VALW

ON/OFFBT N#

+3VALW

+1.05VAL W

EC_RSMRS T#

PBTN_OUT #

PM_SLP_S 4#

PM_SLP_S 3#

SYSON

+1.05V_V CCST

+1.2V_VD DQ

+2.5VS

SUSP#

+1.05VS_ VCCSTG

+5VS

+3VS

+1.8VS

EC_VCCST _PG

SM_PG_CT RL

+0.6VS_V TT

VR_ON

+VCC_S A

+VCC_COR E

+VCC_G T

PCH_PWRO K

SYS_PWRO K

PLT_RST #

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECT RONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECT RONICS, INC.

A

B

C

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECT RONICS, INC.

2017/10/30 2018/10/30

2017/10/30 2018/10/30

2017/10/30 2018/10/30

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Power Sequence

Power Sequence

Power Sequence

Size

Size

Size

Document Number Re v

Document Number Re v

Document Number Re v

Custom

Custom

Custom

EH5VF M/B LA-H501P

EH5VF M/B LA-H501P

EH5VF M/B LA-H501P

Date : Shee t o f

Date : Shee t o f

Date : Shee t o f

E

5 101Friday, February 22, 2019

5 101Friday, February 22, 2019

5 101Friday, February 22, 2019

1A

1A

1A

A

B

C

D

E

ZZZ

PCB10@

PCB EH5VF LA-H501P L S-H501P/H50 2P

DAZ2K700100

1 1

Coffee Lake-H CPU SKU

UC1

I5@

S IC CL8068 40337352 2 SR3Z0 U0 2.3G ABO!

SA0000BPJ40

UC1

I7@

S IC CL8068 40335952 4 SR3YY U0 2.2 G ABO!

SA0000BPZ40

UC1

I5QS@

S IC CL8068 40337352 2 QP89 U0 2.3G BGA

2 2

SA0000BPJ10

Cannon Lake PCH SKU

UH1

PCH@

S IC FH82HM370 SR40B B0 BGA 874P PCH-H ABO!

SA0000BVP10

UH1

3 3

PCHQS@

S IC FHHM370 QNYF B0 BGA 87 4P PCH-H

SA0000BPF10

NV GPU SKU

UV1

N17P@

S IC N17P-G0-K 1-A1 FCBGA 908P GPU ABO !

SA0000CFM20

UV1

N18PQS@

S IC N18P-G0-A 1 QS FCBGA 960P GPU ABO !

SA0000CK210

UV1

4 4

N18PMP@

S IC N18P-G0-MP-A 1 FCBGA 96 0P GPU AB O !

SA0000CK230

ZZZ1

PCB1A@

PCB EH5VF LA-H501P L S-H501P/H50 2P

DAZ2K700101

UC1

I5RQS@

S IC CL8068 40412190 5 QRR5 U0 2 .4G FCBGA

SA0000COG00

UC1

I7RQS@

S IC CL8068 40412181 7 QRR2 U0 2 .6G FCBGA 1 440

SA0000COF10

K36
K37

J35

J34
H37
H36

J37

J38

D27
E27

H34
H33
F37
G38
F34
F35
E37
E36

F26
E26

C34
D34
B36
B34
F33
E33
C33
B33

A27
B27

UC1D

DDI1_TXP_0
DDI1_TXN_0
DDI1_TXP_1
DDI1_TXN_1
DDI1_TXP_2
DDI1_TXN_2
DDI1_TXP_3
DDI1_TXN_3

DDI1_AUXP
DDI1_AUXN

DDI2_TXP_0
DDI2_TXN_0
DDI2_TXP_1
DDI2_TXN_1
DDI2_TXP_2
DDI2_TXN_2
DDI2_TXP_3
DDI2_TXN_3

DDI2_AUXP
DDI2_AUXN

DDI3_TXP_0
DDI3_TXN_0
DDI3_TXP_1
DDI3_TXN_1
DDI3_TXP_2
DDI3_TXN_2
DDI3_TXP_3
DDI3_TXN_3

DDI3_AUXP
DDI3_AUXN

CFL-H_BG A1440

@

CFL-H

EDP_TXP_0
EDP_TXN_0
EDP_TXP_1
EDP_TXN_1
EDP_TXP_2
EDP_TXN_2
EDP_TXP_3
EDP_TXN_3

EDP_AUXP
EDP_AUXN

EDP_DISP_UTIL

DISP_RCOMP

PROC_AUDIO_CLK

PROC_AUDIO_SDI

PROC_AUDIO_SDO

4 of 13

D29
E29
F28
E28
A29
B29
C28
B28

C26
B26

A33

D37

G27
G25
G29

EDP_TXP 0
EDP_TXN 0
EDP_TXP 1
EDP_TXN 1
EDP_TXP 2
EDP_TXN 2
EDP_TXP 3
EDP_TXN 3

EDP_AUX P
EDP_AUX N

DP_RCOM P

Trace Width/Space: 15 mil/ 20 mil
Max Trace Length: 600 mil

CPU_DISPA _SDI

RC1 24.9_04 02_1%

RC2 20_040 2_5%

1 2

follow CRB

12

EDP_TXP 0 <38>
EDP_TXN 0 <38 >
EDP_TXP 1 <38>
EDP_TXN 1 <38 >
EDP_TXP 2 <38>
EDP_TXN 2 <38 >
EDP_TXP 3 <38>
EDP_TXN 3 <38 >

EDP_AUX P < 38>
EDP_AUX N <38>

+VCCIO

CPU_DISPA _BCLK_R
CPU_DISPA _SDO_R
CPU_DISPA _SDI_R

eDP

CPU_DISPA _BCLK_R <18>
CPU_DISPA _SDO_R <18>

CPU_DISPA _SDI_R <18>

Security Classification

Security Classification

Security Classification

2017/10/ 30 2018/10/ 30

2017/10/ 30 2018/10/ 30

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

2017/10/ 30 2018/10/ 30

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

CFL-H(1/8)DDI/eDP

CFL-H(1/8)DDI/eDP

CFL-H(1/8)DDI/eDP

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

EH5VF M/B LA-H501P

EH5VF M/B LA-H501P

EH5VF M/B LA-H501P

Date : Sheet o f

Date : Sheet o f

D

Date : Sheet o f

6 1 01Friday, February 22, 2019

6 1 01Friday, February 22, 2019

6 1 01Friday, February 22, 2019

E

1A

1A

1A

A

B

C

D

E

CHANNEL-A

Interleaved Memory

UC1A

1 1

2 2

3 3

DDR_A_D [0..63]<23>

For ECC DIMM

DDR_A_D 0
DDR_A_D 1
DDR_A_D 2
DDR_A_D 3
DDR_A_D 4
DDR_A_D 5
DDR_A_D 6
DDR_A_D 7
DDR_A_D 8
DDR_A_D 9
DDR_A_D 10
DDR_A_D 11
DDR_A_D 12
DDR_A_D 13
DDR_A_D 14
DDR_A_D 15
DDR_A_D 16
DDR_A_D 17
DDR_A_D 18
DDR_A_D 19
DDR_A_D 20
DDR_A_D 21
DDR_A_D 22
DDR_A_D 23
DDR_A_D 24
DDR_A_D 25
DDR_A_D 26
DDR_A_D 27
DDR_A_D 28
DDR_A_D 29
DDR_A_D 30
DDR_A_D 31
DDR_A_D 32
DDR_A_D 33
DDR_A_D 34
DDR_A_D 35
DDR_A_D 36
DDR_A_D 37
DDR_A_D 38
DDR_A_D 39
DDR_A_D 40
DDR_A_D 41
DDR_A_D 42
DDR_A_D 43
DDR_A_D 44
DDR_A_D 45
DDR_A_D 46
DDR_A_D 47
DDR_A_D 48
DDR_A_D 49
DDR_A_D 50
DDR_A_D 51
DDR_A_D 52
DDR_A_D 53
DDR_A_D 54
DDR_A_D 55
DDR_A_D 56
DDR_A_D 57
DDR_A_D 58
DDR_A_D 59
DDR_A_D 60
DDR_A_D 61
DDR_A_D 62
DDR_A_D 63

DDR4(IL)/LP3-DDR4(NIL) LP3/D DR4

BR6

DDR0_DQ_0/DDR0_DQ_0

BT6

DDR0_DQ_1/DDR0_DQ_1

BP3

DDR0_DQ_2/DDR0_DQ_2

BR3

DDR0_DQ_3/DDR0_DQ_3

BN5

DDR0_DQ_4/DDR0_DQ_4

BP6

DDR0_DQ_5/DDR0_DQ_5

BP2

DDR0_DQ_6/DDR0_DQ_6

BN3

DDR0_DQ_7/DDR0_DQ_7

BL4

DDR0_DQ_8/DDR0_DQ_8

BL5

DDR0_DQ_9/DDR0_DQ_9

BL2

DDR0_DQ_10/DDR0_DQ_10

BM1

DDR0_DQ_11/DDR0_DQ_11

BK4

DDR0_DQ_12/DDR0_DQ_12

BK5

DDR0_DQ_13/DDR0_DQ_13

BK1

DDR0_DQ_14/DDR0_DQ_14

BK2

DDR0_DQ_15/DDR0_DQ_15

BG4

DDR0_DQ_16/DDR0_DQ_32

BG5

DDR0_DQ_17/DDR0_DQ_33

BF4

DDR0_DQ_18/DDR0_DQ_34

BF5

DDR0_DQ_19/DDR0_DQ_35

BG2

DDR0_DQ_20/DDR0_DQ_36

BG1

DDR0_DQ_21/DDR0_DQ_37

BF1

DDR0_DQ_22/DDR0_DQ_38

BF2

DDR0_DQ_23/DDR0_DQ_39

BD2

DDR0_DQ_24/DDR0_DQ_40

BD1

DDR0_DQ_25/DDR0_DQ_41

BC4

DDR0_DQ_26/DDR0_DQ_42

BC5

DDR0_DQ_27/DDR0_DQ_43

BD5

DDR0_DQ_28/DDR0_DQ_44

BD4

DDR0_DQ_29/DDR0_DQ_45

BC1

DDR0_DQ_30/DDR0_DQ_46

BC2

DDR0_DQ_31/DDR0_DQ_47

AB1

DDR0_DQ_32/DDR1_DQ_0

AB2

DDR0_DQ_33/DDR1_DQ_1

AA4

DDR0_DQ_34/DDR1_DQ_2

AA5

DDR0_DQ_35/DDR1_DQ_3

AB5

DDR0_DQ_36/DDR1_DQ_4

AB4

DDR0_DQ_37/DDR1_DQ_5

AA2

DDR0_DQ_38/DDR1_DQ_6

AA1

DDR0_DQ_39/DDR1_DQ_7

V5

DDR0_DQ_40/DDR1_DQ_8

V2

DDR0_DQ_41/DDR1_DQ_9

U1

DDR0_DQ_42/DDR1_DQ_10

U2

DDR0_DQ_43/DDR1_DQ_11

V1

DDR0_DQ_44/DDR1_DQ_12

V4

DDR0_DQ_45/DDR1_DQ_13

U5

DDR0_DQ_46/DDR1_DQ_14

U4

DDR0_DQ_47/DDR1_DQ_15

R2

DDR0_DQ_48/DDR1_DQ_32

P5

DDR0_DQ_49/DDR1_DQ_33

R4

DDR0_DQ_50/DDR1_DQ_34

P4

DDR0_DQ_51/DDR1_DQ_35

R5

DDR0_DQ_52/DDR1_DQ_36

P2

DDR0_DQ_53/DDR1_DQ_37

R1

DDR0_DQ_54/DDR1_DQ_38

P1

DDR0_DQ_55/DDR1_DQ_39

M4

DDR0_DQ_56/DDR1_DQ_40

M1

DDR0_DQ_57/DDR1_DQ_41

L4

DDR0_DQ_58/DDR1_DQ_42

L2

DDR0_DQ_59/DDR1_DQ_43

M5

DDR0_DQ_60/DDR1_DQ_44

M2

DDR0_DQ_61/DDR1_DQ_45

L5

DDR0_DQ_62/DDR1_DQ_46

L1

DDR0_DQ_63/DDR1_DQ_47

LP3/DDR4

BA2

NC/DDR0_ECC_0

BA1

NC/DDR0_ECC_1

AY4

NC/DDR0_ECC_2

AY5

NC/DDR0_ECC_3

BA5

NC/DDR0_ECC_4

BA4

NC/DDR0_ECC_5

AY1

NC/DDR0_ECC_6

AY2

NC/DDR0_ECC_7

CFL-H_BG A1440

@

CFL-H

DDR CHANNEL A

DDR0_CKP_0/DDR0_CKP_0
DDR0_CKN_0/DDR0_CKN_0
DDR0_CKP_1/DDR0_CKP_1
DDR0_CKN_1/DDR0_CKN_1

NC/DDR0_CKP_2
NC/DDR0_CKN_2
NC/DDR0_CKP_3
NC/DDR0_CKN_3

DDR0_CKE_0/DDR0_CKE_0
DDR0_CKE_1/DDR0_CKE_1
DDR0_CKE_2/DDR0_CKE_2
DDR0_CKE_3/DDR0_CKE_3

DDR0_CS#_0/DDR0_CS#_0
DDR0_CS#_1/DDR0_CS#_1

NC/DDR0_CS#_2
NC/DDR0_CS#_3

DDR0_ODT_0/DDR0_ODT_0

NC/DDR0_ODT_1
NC/DDR0_ODT_2
NC/DDR0_ODT_3

DDR0_CAB_4/DDR0_BA_0
DDR0_CAB_6/DDR0_BA_1
DDR0_CAA_5/DDR0_BG_0

DDR0_CAB_3/DDR0_MA_16
DDR0_CAB_2/DDR0_MA_14
DDR0_CAB_1/DDR0_MA_15

DDR0_CAB_9/DDR0_MA_0
DDR0_CAB_8/DDR0_MA_1
DDR0_CAB_5/DDR0_MA_2

NC/DDR0_MA_3

NC/DDR0_MA_4
DDR0_CAA_0/DDR0_MA_5
DDR0_CAA_2/DDR0_MA_6
DDR0_CAA_4/DDR0_MA_7
DDR0_CAA_3/DDR0_MA_8
DDR0_CAA_1/DDR0_MA_9

DDR0_CAB_7/DDR0_MA_10
DDR0_CAA_7/DDR0_MA_11
DDR0_CAA_6/DDR0_MA_12
DDR0_CAB_0/DDR0_MA_13

DDR0_CAA_9/DDR0_BG_1
DDR0_CAA_8/DDR0_ACT#

NC/DDR0_PAR

NC/DDR0_ALERT#

DDR4(IL)/LP3-DDR4(NIL)

DDR0_DQSN_0/DDR0_DQSN_0
DDR0_DQSN_1/DDR0_DQSN_1
DDR0_DQSN_2/DDR0_DQSN_4
DDR0_DQSN_3/DDR0_DQSN_5
DDR0_DQSN_4/DDR1_DQSN_0
DDR0_DQSN_5/DDR1_DQSN_1
DDR0_DQSN_6/DDR1_DQSN_4
DDR0_DQSN_7/DDR1_DQSN_5

DDR0_DQSP_0/DDR0_DQSP_0
DDR0_DQSP_1/DDR0_DQSP_1
DDR0_DQSP_2/DDR0_DQSP_4
DDR0_DQSP_3/DDR0_DQSP_5
DDR0_DQSP_4/DDR1_DQSP_0
DDR0_DQSP_5/DDR1_DQSP_1
DDR0_DQSP_6/DDR1_DQSP_4
DDR0_DQSP_7/DDR1_DQSP_5

DDR0_DQSP_8/DDR0_DQSP_8
DDR0_DQSN_8/DDR0_DQSN_8

1 OF 13

AG1
AG2
AK2
AK1
AL3
AK3
AL2
AL1

AT1
AT2
AT3
AT5

AD5
AE2
AD2
AE5

AD3
AE4
AE1
AD4

AH5
AH1
AU1

AH4
AG4
AD1

AH3
AP4
AN4
AP5
AP2
AP1
AP3
AN1
AN3
AT4
AH2
AN2
AU4
AE3
AU2
AU3

AG3
AU5

BR5
BL3
BG3
BD3
AA3
U3
P3
L3

BP5
BK3
BF3
BC3
AB3
V3
R3
M3

AY3
BA3

DDR_A_C LK0
DDR_A_C LK#0
DDR_A_C LK1
DDR_A_C LK#1

DDR_A_C KE0
DDR_A_C KE1

DDR_A_C S#0
DDR_A_C S#1

DDR_A_O DT0
DDR_A_O DT1

DDR_A_B A0
DDR_A_B A1
DDR_A_B G0

DDR_A_M A16_RAS#
DDR_A_M A14_WE#
DDR_A_M A15_CAS#

DDR_A_M A0
DDR_A_M A1
DDR_A_M A2
DDR_A_M A3
DDR_A_M A4
DDR_A_M A5
DDR_A_M A6
DDR_A_M A7
DDR_A_M A8
DDR_A_M A9
DDR_A_M A10
DDR_A_M A11
DDR_A_M A12
DDR_A_M A13
DDR_A_B G1
DDR_A_A CT#

DDR_A_P AR
DDR_A_A LERT#

DDR_A_D QS#0
DDR_A_D QS#1
DDR_A_D QS#2
DDR_A_D QS#3
DDR_A_D QS#4
DDR_A_D QS#5
DDR_A_D QS#6
DDR_A_D QS#7

DDR_A_D QS0
DDR_A_D QS1
DDR_A_D QS2
DDR_A_D QS3
DDR_A_D QS4
DDR_A_D QS5
DDR_A_D QS6
DDR_A_D QS7

DDR_A_C LK0 <23>
DDR_A_C LK#0 <23>
DDR_A_C LK1 <23>
DDR_A_C LK#1 <23>

DDR_A_C KE0 <23>
DDR_A_C KE1 <23>

DDR_A_C S#0 <23>
DDR_A_C S#1 <23>

DDR_A_O DT0 <23>
DDR_A_O DT1 <23>

DDR_A_B A0 < 23>
DDR_A_B A1 < 23>
DDR_A_B G0 < 23>

DDR_A_M A16_RAS# <23>
DDR_A_M A14_WE# <23>
DDR_A_M A15_CAS# <23>

DDR_A_M A0 <23>
DDR_A_M A1 <23>
DDR_A_M A2 <23>
DDR_A_M A3 <23>
DDR_A_M A4 <23>
DDR_A_M A5 <23>
DDR_A_M A6 <23>
DDR_A_M A7 <23>
DDR_A_M A8 <23>
DDR_A_M A9 <23>
DDR_A_M A10 <23 >
DDR_A_M A11 <23 >
DDR_A_M A12 <23 >
DDR_A_M A13 <23 >
DDR_A_B G1 < 23>
DDR_A_A CT# <23>

DDR_A_P AR <23>
DDR_A_A LERT# <23>

DDR_A_D QS#0 <23>
DDR_A_D QS#1 <23>
DDR_A_D QS#2 <23>
DDR_A_D QS#3 <23>
DDR_A_D QS#4 <23>
DDR_A_D QS#5 <23>
DDR_A_D QS#6 <23>
DDR_A_D QS#7 <23>

DDR_A_D QS0 <23>
DDR_A_D QS1 <23>
DDR_A_D QS2 <23>
DDR_A_D QS3 <23>
DDR_A_D QS4 <23>
DDR_A_D QS5 <23>
DDR_A_D QS6 <23>
DDR_A_D QS7 <23>

For ECC DIMM

4 4

Security Classification

Security Classification

Security Classification

2017/10/ 30 2018/10/ 30

2017/10/ 30 2018/10/ 30

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

2017/10/ 30 2018/10/ 30

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

CFL-H(2/8)DIMMA

CFL-H(2/8)DIMMA

CFL-H(2/8)DIMMA

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

EH5VF M/B LA-H501P

EH5VF M/B LA-H501P

EH5VF M/B LA-H501P

Date : Sheet o f

Date : Sheet o f

D

Date : Sheet o f

7 1 01Friday, February 22, 2019

7 1 01Friday, February 22, 2019

7 1 01Friday, February 22, 2019

E

1A

1A

1A

A

B

C

D

E

CHANNEL-B

Interleaved Memory

1 1

2 2

3 3

DDR_B_D [0..63]<24>

For ECC DIMM

DDR_B_D 0
DDR_B_D 1
DDR_B_D 2
DDR_B_D 3
DDR_B_D 4
DDR_B_D 5
DDR_B_D 6
DDR_B_D 7
DDR_B_D 8
DDR_B_D 9
DDR_B_D 10
DDR_B_D 11
DDR_B_D 12
DDR_B_D 13
DDR_B_D 14
DDR_B_D 15
DDR_B_D 16
DDR_B_D 17
DDR_B_D 18
DDR_B_D 19
DDR_B_D 20
DDR_B_D 21
DDR_B_D 22
DDR_B_D 23
DDR_B_D 24
DDR_B_D 25
DDR_B_D 26
DDR_B_D 27
DDR_B_D 28
DDR_B_D 29
DDR_B_D 30
DDR_B_D 31
DDR_B_D 32
DDR_B_D 33
DDR_B_D 34
DDR_B_D 35
DDR_B_D 36
DDR_B_D 37
DDR_B_D 38
DDR_B_D 39

DDR_B_D 40
DDR_B_D 41
DDR_B_D 42
DDR_B_D 43
DDR_B_D 44
DDR_B_D 45
DDR_B_D 46
DDR_B_D 47
DDR_B_D 48
DDR_B_D 49
DDR_B_D 50
DDR_B_D 51
DDR_B_D 52
DDR_B_D 53
DDR_B_D 54
DDR_B_D 55
DDR_B_D 56
DDR_B_D 57
DDR_B_D 58
DDR_B_D 59
DDR_B_D 60
DDR_B_D 61
DDR_B_D 62
DDR_B_D 63

UC1B

DDR4(IL)/LP3-DDR4(NIL)

BT11

DDR1_DQ_0/DDR0_DQ_16

BR11

DDR1_DQ_1/DDR0_DQ_17

BT9

DDR1_DQ_2/DDR0_DQ_18

BR8

DDR1_DQ_3/DDR0_DQ_19

BP11

DDR1_DQ_4/DDR0_DQ_20

BN11

DDR1_DQ_5/DDR0_DQ_21

BP8

DDR1_DQ_6/DDR0_DQ_22

BN8

DDR1_DQ_7/DDR0_DQ_23

BL12

DDR1_DQ_8/DDR0_DQ_24

BL11

DDR1_DQ_9/DDR0_DQ_25

BL8

DDR1_DQ_10/DDR0_DQ_26

BJ8

DDR1_DQ_11/DDR0_DQ_27

BJ11

DDR1_DQ_12/DDR0_DQ_28

BJ10

DDR1_DQ_13/DDR0_DQ_29

BL7

DDR1_DQ_14/DDR0_DQ_30

BJ7

DDR1_DQ_15/DDR0_DQ_31

BG11

DDR1_DQ_16/DDR0_DQ_48

BG10

DDR1_DQ_17/DDR0_DQ_49

BG8

DDR1_DQ_18/DDR0_DQ_50

BF8

DDR1_DQ_19/DDR0_DQ_51

BF11

DDR1_DQ_20/DDR0_DQ_52

BF10

DDR1_DQ_21/DDR0_DQ_53

BG7

DDR1_DQ_22/DDR0_DQ_54

BF7

DDR1_DQ_23/DDR0_DQ_55

BB11

DDR1_DQ_24/DDR0_DQ_56

BC11

DDR1_DQ_25/DDR0_DQ_57

BB8

DDR1_DQ_26/DDR0_DQ_58

BC8

DDR1_DQ_27/DDR0_DQ_59

BC10

DDR1_DQ_28/DDR0_DQ_60

BB10

DDR1_DQ_29/DDR0_DQ_61

BC7

DDR1_DQ_30/DDR0_DQ_62

BB7

DDR1_DQ_31/DDR0_DQ_63

AA11

DDR1_DQ_32/DDR1_DQ_16

AA10

DDR1_DQ_33/DDR1_DQ_17

AC11

DDR1_DQ_34/DDR1_DQ_18

AC10

DDR1_DQ_35/DDR1_DQ_19

AA7

DDR1_DQ_36/DDR1_DQ_20

AA8

DDR1_DQ_37/DDR1_DQ_21

AC8

DDR1_DQ_38/DDR1_DQ_22

AC7

DDR1_DQ_39/DDR1_DQ_23

DDR4(IL)/LP3-DDR4(NIL)

W8

DDR1_DQ_40/DDR1_DQ_24

W7

DDR1_DQ_41/DDR1_DQ_25

V10

DDR1_DQ_42/DDR1_DQ_26

V11

DDR1_DQ_43/DDR1_DQ_27

W11

DDR1_DQ_44/DDR1_DQ_28

W10

DDR1_DQ_45/DDR1_DQ_29

V7

DDR1_DQ_46/DDR1_DQ_30

V8

DDR1_DQ_47/DDR1_DQ_31

R11

DDR1_DQ_48/DDR1_DQ_48

P11

DDR1_DQ_49/DDR1_DQ_49

P7

DDR1_DQ_50/DDR1_DQ_50

R8

DDR1_DQ_51/DDR1_DQ_51

R10

DDR1_DQ_52/DDR1_DQ_52

P10

DDR1_DQ_53/DDR1_DQ_53

R7

DDR1_DQ_54/DDR1_DQ_54

P8

DDR1_DQ_55/DDR1_DQ_55

L11

DDR1_DQ_56/DDR1_DQ_56

M11

DDR1_DQ_57/DDR1_DQ_57

L7

DDR1_DQ_58/DDR1_DQ_58

M8

DDR1_DQ_59/DDR1_DQ_59

L10

DDR1_DQ_60/DDR1_DQ_60

M10

DDR1_DQ_61/DDR1_DQ_61

M7

DDR1_DQ_62/DDR1_DQ_62

L8

DDR1_DQ_63/DDR1_DQ_63

LP3/DDR4

AW11

NC/DDR1_ECC_0

AY11

NC/DDR1_ECC_1

AY8

NC/DDR1_ECC_2

AW8

NC/DDR1_ECC_3

AY10

NC/DDR1_ECC_4

AW10

NC/DDR1_ECC_5

AY7

NC/DDR1_ECC_6

AW7

NC/DDR1_ECC_7

CFL-H

DDR CHANNEL B

DDR1_CKP_0/DDR1_CKP_0
DDR1_CKN_0/DDR1_CKN_0
DDR1_CKP_1/DDR1_CKP_1
DDR1_CKN_1/DDR1_CKN_1

DDR1_CKE_0/DDR1_CKE_0
DDR1_CKE_1/DDR1_CKE_1
DDR1_CKE_2/DDR1_CKE_2
DDR1_CKE_3/DDR1_CKE_3

DDR1_CS#_0/DDR1_CS#_0
DDR1_CS#_1/DDR1_CS#_1

DDR1_ODT_0/DDR1_ODT_0

DDR1_CAB_3/DDR1_MA_16
DDR1_CAB_2/DDR1_MA_14
DDR1_CAB_1/DDR1_MA_15

DDR1_CAB_4/DDR1_BA_0
DDR1_CAB_6/DDR1_BA_1

DDR1_CAA_5/DDR1_BG_0

DDR1_CAB_9/DDR1_MA_0
DDR1_CAB_8/DDR1_MA_1
DDR1_CAB_5/DDR1_MA_2

DDR1_CAA_0/DDR1_MA_5
DDR1_CAA_2/DDR1_MA_6
DDR1_CAA_4/DDR1_MA_7

DDR1_CAA_3/DDR1_MA_8

DDR1_CAA_1/DDR1_MA_9
DDR1_CAB_7/DDR1_MA_10
DDR1_CAA_7/DDR1_MA_11
DDR1_CAA_6/DDR1_MA_12
DDR1_CAB_0/DDR1_MA_13

DDR1_CAA_9/DDR1_BG_1

DDR1_CAA_8/DDR1_ACT#

DDR4(IL)/LP3-DDR4(NIL)

DDR1_DQSN_0/DDR0_DQSN_2
DDR1_DQSN_1/DDR0_DQSN_3
DDR1_DQSN_2/DDR0_DQSN_6
DDR1_DQSN_3/DDR0_DQSN_7
DDR1_DQSN_4/DDR1_DQSN_2
DDR1_DQSN_5/DDR1_DQSN_3
DDR1_DQSN_6/DDR1_DQSN_6
DDR1_DQSN_7/DDR1_DQSN_7

DDR1_DQSP_0/DDR0_DQSP_2
DDR1_DQSP_1/DDR0_DQSP_3
DDR1_DQSP_2/DDR0_DQSP_6
DDR1_DQSP_3/DDR0_DQSP_7
DDR1_DQSP_4/DDR1_DQSP_2
DDR1_DQSP_5/DDR1_DQSP_3
DDR1_DQSP_6/DDR1_DQSP_6
DDR1_DQSP_7/DDR1_DQSP_7

DDR1_DQSP_8/DDR1_DQSP_8
DDR1_DQSN_8/DDR1_DQSN_8

LP3/DDR4

NC/DDR1_CKP_2
NC/DDR1_CKN_2
NC/DDR1_CKP_3
NC/DDR1_CKN_3

NC/DDR1_CS#_2
NC/DDR1_CS#_3

NC/DDR1_ODT_1
NC/DDR1_ODT_2
NC/DDR1_ODT_3

NC/DDR1_MA_3
NC/DDR1_MA_4

NC/DDR1_PAR

NC/DDR1_ALERT#

AM9
AN9
AM7
AM8
AM11
AM10
AJ10
AJ11

AT8
AT10
AT7
AT11

AF11
AE7
AF10
AE10

AF7
AE8
AE9
AE11

AH10
AH11
AF8

AH8
AH9
AR9

AJ9
AK6
AK5
AL5
AL6
AM6
AN7
AN10

AN8
AR11
AH7
AN11
AR10
AF9
AR7
AT9

AJ7
AR8

BN9
BL9
BG9
BC9
AC9
W9
R9
M9

BP9
BJ9
BF9
BB9
AA9
V9
P9
L9

AW9
AY9

DDR_B_C LK0
DDR_B_C LK#0
DDR_B_C LK1
DDR_B_C LK#1

DDR_B_C KE0
DDR_B_C KE1

DDR_B_C S#0
DDR_B_C S#1

DDR_B_O DT0
DDR_B_O DT1

DDR_B_M A16_RAS#
DDR_B_M A14_WE#
DDR_B_M A15_CAS#

DDR_B_B A0
DDR_B_B A1
DDR_B_B G0

DDR_B_M A0
DDR_B_M A1
DDR_B_M A2
DDR_B_M A3
DDR_B_M A4
DDR_B_M A5
DDR_B_M A6
DDR_B_M A7

DDR_B_M A8
DDR_B_M A9
DDR_B_M A10
DDR_B_M A11
DDR_B_M A12
DDR_B_M A13
DDR_B_B G1
DDR_B_A CT#

DDR_B_P AR
DDR_B_A LERT#

DDR_B_D QS#0
DDR_B_D QS#1
DDR_B_D QS#2
DDR_B_D QS#3
DDR_B_D QS#4
DDR_B_D QS#5
DDR_B_D QS#6
DDR_B_D QS#7

DDR_B_D QS0
DDR_B_D QS1
DDR_B_D QS2
DDR_B_D QS3
DDR_B_D QS4
DDR_B_D QS5
DDR_B_D QS6
DDR_B_D QS7

DDR_B_C LK0 <24>
DDR_B_C LK#0 <24>
DDR_B_C LK1 <24>
DDR_B_C LK#1 <24>

DDR_B_C KE0 <24>
DDR_B_C KE1 <24>

DDR_B_C S#0 <24>
DDR_B_C S#1 <24>

DDR_B_O DT0 <24>
DDR_B_O DT1 <24>

DDR_B_M A16_RAS# <24>
DDR_B_M A14_WE# <24>
DDR_B_M A15_CAS# <24>

DDR_B_B A0 < 24>
DDR_B_B A1 < 24>
DDR_B_B G0 < 24>

DDR_B_M A0 <24>
DDR_B_M A1 <24>
DDR_B_M A2 <24>
DDR_B_M A3 <24>
DDR_B_M A4 <24>
DDR_B_M A5 <24>
DDR_B_M A6 <24>
DDR_B_M A7 <24>

DDR_B_M A8 <24>
DDR_B_M A9 <24>
DDR_B_M A10 <24 >
DDR_B_M A11 <24 >
DDR_B_M A12 <24 >
DDR_B_M A13 <24 >
DDR_B_B G1 < 24>
DDR_B_A CT# <24>

DDR_B_P AR <24>
DDR_B_A LERT# <24>

DDR_B_D QS#0 <24>
DDR_B_D QS#1 <24>
DDR_B_D QS#2 <24>
DDR_B_D QS#3 <24>
DDR_B_D QS#4 <24>
DDR_B_D QS#5 <24>
DDR_B_D QS#6 <24>
DDR_B_D QS#7 <24>

DDR_B_D QS0 <24>
DDR_B_D QS1 <24>
DDR_B_D QS2 <24>
DDR_B_D QS3 <24>
DDR_B_D QS4 <24>
DDR_B_D QS5 <24>
DDR_B_D QS6 <24>
DDR_B_D QS7 <24>

For ECC DIMM

1 2

RC3 121_ 0402_1%

1 2

RC4 75_040 2_1%

1 2

RC5 100_04 02_1%

Trace Width/Space: 15 mil/ 25 mil

4 4

A

Max Trace Length: 500 mil

B

SM_RCOM P0
SM_RCOM P1
SM_RCOM P2

G1

DDR_RCOMP_0

H1

DDR_RCOMP_1

J2

DDR_RCOMP_2

CFL-H_BG A1440

@

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2 OF 13

DDR_VREF_CA
DDR0_VREF_DQ
DDR1_VREF_DQ

Compal Secret Data

Compal Secret Data

2017/10/ 30 2018/10/ 30

2017/10/ 30 2018/10/ 30

2017/10/ 30 2018/10/ 30

C

Compal Secret Data

BN13
BP13
BR13

Deciphered Date

Deciphered Date

Deciphered Date

+0.6V_VR EFCA

+0.6V_B_ VREFDQ

+0.6V_VR EFCA

+0.6V_B_ VREFDQ

D

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

CFL-H(3/8)DIMMB

CFL-H(3/8)DIMMB

CFL-H(3/8)DIMMB

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

EH5VF M/B LA-H501P

EH5VF M/B LA-H501P

EH5VF M/B LA-H501P

Date : Sheet o f

Date : Sheet o f

Date : Sheet o f

8 1 01Friday, February 22, 2019

8 1 01Friday, February 22, 2019

8 1 01Friday, February 22, 2019

E

1A

1A

1A

A

PEG&DMI

B

C

D

E

1 1

2 2

3 3

To DGPU
PEG Lane Reversed

PEG_CRX _C_GTX_P15<27>
PEG_CRX _C_GTX_N15<27>

PEG_CRX _C_GTX_P14<27>
PEG_CRX _C_GTX_N14<27>

PEG_CRX _C_GTX_P13<27>
PEG_CRX _C_GTX_N13<27>

PEG_CRX _C_GTX_P12<27>
PEG_CRX _C_GTX_N12<27>

PEG_CRX _C_GTX_P11<27>
PEG_CRX _C_GTX_N11<27>

PEG_CRX _C_GTX_P10<27>
PEG_CRX _C_GTX_N10<27>

PEG_CRX _C_GTX_P9<27>
PEG_CRX _C_GTX_N9<27>

PEG_CRX _C_GTX_P8<27>
PEG_CRX _C_GTX_N8<27>

PEG_CRX _C_GTX_P7<27>
PEG_CRX _C_GTX_N7<27>

PEG_CRX _C_GTX_P6<27>
PEG_CRX _C_GTX_N6<27>

PEG_CRX _C_GTX_P5<27>
PEG_CRX _C_GTX_N5<27>

PEG_CRX _C_GTX_P4<27>
PEG_CRX _C_GTX_N4<27>

PEG_CRX _C_GTX_P3<27>
PEG_CRX _C_GTX_N3<27>

PEG_CRX _C_GTX_P2<27>
PEG_CRX _C_GTX_N2<27>

PEG_CRX _C_GTX_P1<27>
PEG_CRX _C_GTX_N1<27>

PEG_CRX _C_GTX_P0<27>
PEG_CRX _C_GTX_N0<27>

+VCCIO

To PCH

1 2

CC1 0.22U_020 1_6.3V6KVGA@

1 2

CC3 0.22U_020 1_6.3V6KVGA@

1 2

CC5 0.22U_020 1_6.3V6KVGA@

1 2

CC6 0.22U_020 1_6.3V6KVGA@

1 2

CC7 0.22U_020 1_6.3V6KVGA@

1 2

CC14 0.22U_0 201_6.3V6KVGA@

1 2

CC16 0.22U_0 201_6.3V6KVGA@

1 2

CC17 0.22U_0 201_6.3V6KVGA@

1 2

CC19 0.22U_0 201_6.3V6KVGA@

1 2

CC20 0.22U_0 201_6.3V6KVGA@

1 2

CC10 0.22U_0 201_6.3V6KVGA@

1 2

CC23 0.22U_0 201_6.3V6KVGA@

1 2

CC25 0.22U_0 201_6.3V6KVGA@

1 2

CC27 0.22U_0 201_6.3V6KVGA@

1 2

CC29 0.22U_0 201_6.3V6KVGA@

1 2

CC31 0.22U_0 201_6.3V6KVGA@

1 2

CC33 0.22U_0 201_6.3V6KVGA@

1 2

CC35 0.22U_0 201_6.3V6KVGA@

1 2

CC37 0.22U_0 201_6.3V6KVGA@

1 2

CC39 0.22U_0 201_6.3V6KVGA@

1 2

CC41 0.22U_0 201_6.3V6KVGA@

1 2

CC43 0.22U_0 201_6.3V6KVGA@

1 2

CC45 0.22U_0 201_6.3V6KVGA@

1 2

CC47 0.22U_0 201_6.3V6KVGA@

1 2

CC49 0.22U_0 201_6.3V6KVGA@

1 2

CC51 0.22U_0 201_6.3V6KVGA@

1 2

CC53 0.22U_0 201_6.3V6KVGA@

1 2

CC55 0.22U_0 201_6.3V6KVGA@

1 2

CC57 0.22U_0 201_6.3V6KVGA@

1 2

CC59 0.22U_0 201_6.3V6KVGA@

1 2

CC61 0.22U_0 201_6.3V6KVGA@

1 2

CC63 0.22U_0 201_6.3V6KVGA@

1 2

RC6 24.9_04 02_1%

DMI_CRX_P TX_P0<14>
DMI_CRX_P TX_N0<14>

DMI_CRX_P TX_P1<14>
DMI_CRX_P TX_N1<14>

DMI_CRX_P TX_P2<14>
DMI_CRX_P TX_N2<14>

DMI_CRX_P TX_P3<14>
DMI_CRX_P TX_N3<14>

PEG_CRX _GTX_P15
PEG_CRX _GTX_N15

PEG_CRX _GTX_P14
PEG_CRX _GTX_N14

PEG_CRX _GTX_P13
PEG_CRX _GTX_N13

PEG_CRX _GTX_P12
PEG_CRX _GTX_N12

PEG_CRX _GTX_P11
PEG_CRX _GTX_N11

PEG_CRX _GTX_P10
PEG_CRX _GTX_N10

PEG_CRX _GTX_P9
PEG_CRX _GTX_N9

PEG_CRX _GTX_P8
PEG_CRX _GTX_N8

PEG_CRX _GTX_P7
PEG_CRX _GTX_N7

PEG_CRX _GTX_P6
PEG_CRX _GTX_N6

PEG_CRX _GTX_P5
PEG_CRX _GTX_N5

PEG_CRX _GTX_P4
PEG_CRX _GTX_N4

PEG_CRX _GTX_P3
PEG_CRX _GTX_N3

PEG_CRX _GTX_P2
PEG_CRX _GTX_N2

PEG_CRX _GTX_P1
PEG_CRX _GTX_N1

PEG_CRX _GTX_P0
PEG_CRX _GTX_N0

PEG_RCO MP

Trace Width/Space: 15 mil/ 15 mil
Max Trace Length: 600 mil

DMI_CRX_P TX_P0
DMI_CRX_P TX_N0

DMI_CRX_P TX_P1
DMI_CRX_P TX_N1

DMI_CRX_P TX_P2
DMI_CRX_P TX_N2

DMI_CRX_P TX_P3
DMI_CRX_P TX_N3

E25

D25

E24
F24

E23

D23

E22
F22

E21

D21

E20
F20

E19

D19

E18
F18

D17

E17

F16
E16

D15

E15

F14
E14

D13

E13

F12
E12

D11

E11

F10
E10

G2

D8
E8

E6
F6

D5
E5

J8
J9

CFL-H_BG A1440

@

UC1C

PEG_RXP_0
PEG_RXN_0

PEG_RXP_1
PEG_RXN_1

PEG_RXP_2
PEG_RXN_2

PEG_RXP_3
PEG_RXN_3

PEG_RXP_4
PEG_RXN_4

PEG_RXP_5
PEG_RXN_5

PEG_RXP_6
PEG_RXN_6

PEG_RXP_7
PEG_RXN_7

PEG_RXP_8
PEG_RXN_8

PEG_RXP_9
PEG_RXN_9

PEG_RXP_10
PEG_RXN_10

PEG_RXP_11
PEG_RXN_11

PEG_RXP_12
PEG_RXN_12

PEG_RXP_13
PEG_RXN_13

PEG_RXP_14
PEG_RXN_14

PEG_RXP_15
PEG_RXN_15

PEG_RCOMP

DMI_RXP_0
DMI_RXN_0

DMI_RXP_1
DMI_RXN_1

DMI_RXP_2
DMI_RXN_2

DMI_RXP_3
DMI_RXN_3

CFL-H

PEG_TXP_0
PEG_TXN_0

PEG_TXP_1
PEG_TXN_1

PEG_TXP_2
PEG_TXN_2

PEG_TXP_3
PEG_TXN_3

PEG_TXP_4
PEG_TXN_4

PEG_TXP_5
PEG_TXN_5

PEG_TXP_6
PEG_TXN_6

PEG_TXP_7
PEG_TXN_7

PEG_TXP_8
PEG_TXN_8

PEG_TXP_9
PEG_TXN_9

PEG_TXP_10

PEG_TXN_10

PEG_TXP_11

PEG_TXN_11

PEG_TXP_12

PEG_TXN_12

PEG_TXP_13

PEG_TXN_13

PEG_TXP_14

PEG_TXN_14

PEG_TXP_15

PEG_TXN_15

3 OF 13

DMI_TXP_0
DMI_TXN_0

DMI_TXP_1
DMI_TXN_1

DMI_TXP_2
DMI_TXN_2

DMI_TXP_3
DMI_TXN_3

B25
A25

B24
C24

B23
A23

B22
C22

B21
A21

B20
C20

B19
A19

B18
C18

A17
B17

C16
B16

A15
B15

C14
B14

A13
B13

C12
B12

A11
B11

C10
B10

B8
A8

C6
B6

B5
A5

D4
B4

PEG_CTX _GRX_P15

PEG_CTX _GRX_N15

PEG_CTX _GRX_P14

PEG_CTX _GRX_N14

PEG_CTX _GRX_P13

PEG_CTX _GRX_N13

PEG_CTX _GRX_P12

PEG_CTX _GRX_N12

PEG_CTX _GRX_P11

PEG_CTX _GRX_N11

PEG_CTX _GRX_P10

PEG_CTX _GRX_N10

PEG_CTX _GRX_P9

PEG_CTX _GRX_N9

PEG_CTX _GRX_P8

PEG_CTX _GRX_N8

PEG_CTX _GRX_P7

PEG_CTX _GRX_N7

PEG_CTX _GRX_P6

PEG_CTX _GRX_N6

PEG_CTX _GRX_P5

PEG_CTX _GRX_N5

PEG_CTX _GRX_P4

PEG_CTX _GRX_N4

PEG_CTX _GRX_P3

PEG_CTX _GRX_N3

PEG_CTX _GRX_P2

PEG_CTX _GRX_N2

PEG_CTX _GRX_P1

PEG_CTX _GRX_N1

PEG_CTX _GRX_P0

PEG_CTX _GRX_N0

DMI_CTX_P RX_P0
DMI_CTX_P RX_N0

DMI_CTX_P RX_P1
DMI_CTX_P RX_N1

DMI_CTX_P RX_P2
DMI_CTX_P RX_N2

DMI_CTX_P RX_P3
DMI_CTX_P RX_N3

12

CC20.22U_02 01_6.3V6K VGA@

12

CC40.22U_02 01_6.3V6K VGA@

12

CC110.22U_02 01_6.3V6K VGA@

12

CC120.22U_02 01_6.3V6K VGA@

12

CC130.22U_02 01_6.3V6K VGA@

12

CC150.22U_02 01_6.3V6K VGA@

12

CC80.22U_02 01_6.3V6K VGA@

12

CC180.22U_02 01_6.3V6K VGA@

12

CC90.22U_02 01_6.3V6K VGA@

12

CC210.22U_02 01_6.3V6K VGA@

12

CC220.22U_02 01_6.3V6K VGA@

12

CC240.22U_02 01_6.3V6K VGA@

12

CC260.22U_02 01_6.3V6K VGA@

12

CC280.22U_02 01_6.3V6K VGA@

12

CC300.22U_02 01_6.3V6K VGA@

12

CC320.22U_02 01_6.3V6K VGA@

12

CC340.22U_02 01_6.3V6K VGA@

12

CC360.22U_02 01_6.3V6K VGA@

12

CC380.22U_02 01_6.3V6K VGA@

12

CC400.22U_02 01_6.3V6K VGA@

12

CC420.22U_02 01_6.3V6K VGA@

12

CC440.22U_02 01_6.3V6K VGA@

12

CC460.22U_02 01_6.3V6K VGA@

12

CC480.22U_02 01_6.3V6K VGA@

12

CC500.22U_02 01_6.3V6K VGA@

12

CC520.22U_02 01_6.3V6K VGA@

12

CC540.22U_02 01_6.3V6K VGA@

12

CC560.22U_02 01_6.3V6K VGA@

12

CC580.22U_02 01_6.3V6K VGA@

12

CC600.22U_02 01_6.3V6K VGA@

12

CC620.22U_02 01_6.3V6K VGA@

12

CC640.22U_02 01_6.3V6K VGA@

DMI_CTX_P RX_P0 <14>
DMI_CTX_P RX_N0 <14>

DMI_CTX_P RX_P1 <14>
DMI_CTX_P RX_N1 <14>

DMI_CTX_P RX_P2 <14>
DMI_CTX_P RX_N2 <14>

DMI_CTX_P RX_P3 <14>
DMI_CTX_P RX_N3 <14>

PEG_CTX _C_GRX_P15 <27>
PEG_CTX _C_GRX_N15 <2 7>

PEG_CTX _C_GRX_P14 <27>
PEG_CTX _C_GRX_N14 <2 7>

PEG_CTX _C_GRX_P13 <27>
PEG_CTX _C_GRX_N13 <2 7>

PEG_CTX _C_GRX_P12 <27>
PEG_CTX _C_GRX_N12 <2 7>

PEG_CTX _C_GRX_P11 <27>
PEG_CTX _C_GRX_N11 <2 7>

PEG_CTX _C_GRX_P10 <27>
PEG_CTX _C_GRX_N10 <2 7>

PEG_CTX _C_GRX_P9 <27>
PEG_CTX _C_GRX_N9 <27 >

PEG_CTX _C_GRX_P8 <27>
PEG_CTX _C_GRX_N8 <27 >

PEG_CTX _C_GRX_P7 <27>
PEG_CTX _C_GRX_N7 <27 >

PEG_CTX _C_GRX_P6 <27>
PEG_CTX _C_GRX_N6 <27 >

PEG_CTX _C_GRX_P5 <27>
PEG_CTX _C_GRX_N5 <27 >

PEG_CTX _C_GRX_P4 <27>
PEG_CTX _C_GRX_N4 <27 >

PEG_CTX _C_GRX_P3 <27>
PEG_CTX _C_GRX_N3 <27 >

PEG_CTX _C_GRX_P2 <27>
PEG_CTX _C_GRX_N2 <27 >

PEG_CTX _C_GRX_P1 <27>
PEG_CTX _C_GRX_N1 <27 >

PEG_CTX _C_GRX_P0 <27>
PEG_CTX _C_GRX_N0 <27 >

To PCH

To DGPU
PEG Lane Reversed

4 4

Security Classification

Security Classification

Security Classification

2017/10/ 30 2018/10/ 30

2017/10/ 30 2018/10/ 30

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

2017/10/ 30 2018/10/ 30

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

PEG/DMI

PEG/DMI

PEG/DMI

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

EH5VF M/B LA-H501P

EH5VF M/B LA-H501P

EH5VF M/B LA-H501P

Date : Sheet o f

Date : Sheet o f

D

Date : Sheet o f

9 1 01Friday, February 22, 2019

9 1 01Friday, February 22, 2019

9 1 01Friday, February 22, 2019

E

1A

1A

1A

A

571391_CFL_H_PDG_Rev0p5

1. The total Length of Data and Clock (from CPU to each VR) must be equal (± 0.1 inch).

2. Route the Alert signal between the Clock and the Data signals.

1 1

3. Place those resistors close CPU side.

2 2

PGESD@

1 2

PGESD@

1 2

PGESD@

1 2

PGESD@

1 2

XESD@

1 2

PGESD@

1 2

PGESD@

1 2

PGESD@

1 2

PGESD@

1 2

CC951000P _0402_50V7K

CC961000P _0402_50V7K

CC971000P _0402_50V7K

CC981000P _0402_50V7K

CC991000P _0402_50V7K

CC1001000P_0 402_50V7K

CC1011000P_0 402_50V7K

CC1021000P_0 402_50V7K

CC1031000P_0 402_50V7K

PROC_S ELEC T#
should be unconnected on CFL processor
EDS1.2 8/21

XESD@

1 2

ESD@

1 2

XESD@

1 2

ESD@

1 2

CC650.1U_020 1_10V6K

CC661000P _0402_50V7K

CC670.1U_020 1_10V6K

CC681000P _0402_50V7K

H_CPUPW RGD

H_PROCH OT#_R

H_THERM TRIP#

EC_VCCS T_PG

Sensitive

Sensitive

H_CPUPW RGD<18>
H_PLTRS T_CPU#<17>
H_PM_SYNC _R<17>

H_PECI<17,58>

PCH_THE RMTRIP#_R<1 7>

Near CPU side

follow 1050 Request

+1.05V_V CCST

3 3

8/21

1 2

RH1 1K_040 2_5%

+1.05VS_ VCCSTG

12

RC21
1K_0402 _5%

H_THERM TRIP#

PCH_CPU _PCIBCLK_P<15>
PCH_CPU _PCIBCLK_N<1 5>

PCH_CPU _24M_CLK_P<15>
PCH_CPU _24M_CLK_N<15>

PCH_CPU _BCLK_P<15>
PCH_CPU _BCLK_N<15>

CPU_SVID_ CLK<89>

RC17 0_0 402_5%@

B

1 2

TC5@

TC6@

DDR_PG_ CTRL

PCH_CPU _BCLK_P
PCH_CPU _BCLK_N

PCH_CPU _PCIBCLK_P
PCH_CPU _PCIBCLK_N

PCH_CPU _24M_CLK_P
PCH_CPU _24M_CLK_N

CPU_SVID_ ALERT#
CPU_SVID_ CLK
CPU_SVID_ DAT
H_PROCH OT#_R

DDR_PG_ CTRL

EC_VCCS T_PG

H_CPUPW RGD
H_PLTRS T_CPU#
H_PM_SYNC _R
H_PM_DO WN
H_PECI
H_THERM TRIP#

SKTOCC#

CATERR#

+1.2V_VD DQ

2

A4Y

B31
A32

D35
C36

E31
D31

BH31
BH32

BH29

BR30

BT13

H13

BT31
BP35

BM34

BP31
BT34

J31

BR33

BN1

BM30

AT13

AW13

AU13

AY13

CC69

0.1U_020 1_10V6K

12

5

1

UC3

Vcc

NC

G

74AUP1G 07SE-7_SOT353 -5

3

C

UC1E

BCLKP
BCLKN

PCI_BCLKP
PCI_BCLKN

CLK24P
CLK24N

VIDALERT#
VIDSCK
VIDSOUT
PROCHOT#

DDR_VTT_CNTL

VCCST_PWRGD

PROCPWRGD
RESET#
PM_SYNC
PM_DOWN
PECI
THERMTRIP#

SKTOCC#
PROC_SELECT#

CATERR#

ZVM#
MSM#

RSVD1
RSVD2

CFL-H_BG A1440

@

CFL-H

BN25

CFG_0

BN27

CFG_1

BN26

CFG_2

BN28

CFG_3

BR20

CFG_4

BM20

CFG_5

BT20

CFG_6

BP20

CFG_7

BR23

CFG_8

BR22

CFG_9

BT23

CFG_10

BT22

CFG_11

BM19

CFG_12

BR19

CFG_13

BP19

CFG_14

BT19

CFG_15

BN23

CFG_17

BP23

CFG_16

BP22

CFG_19

BN22

CFG_18

BR27

BPM#_0

BT27

BPM#_1

BM31

BPM#_2

BT30

BPM#_3

PROC_TDI

+3VS

12

RC23
330K_04 02_5%

BT28
BL32
BP28
BR28

BP30
BL30
BP27

BT25

PROC_TDO

PROC_TMS
PROC_TCK

PROC_TRST#
PROC_PREQ#
PROC_PRDY#

CFG_RCOMP

5 OF 13

PU 330K follow CRB
8/21

CFG0

CFG2

CFG4
CFG5
CFG6
CFG7

XDP_BPM #0
XDP_BPM #1
XDP_BPM #2
XDP_BPM #3

CPU_XDP _TDO
CPU_XDP _TDI
CPU_XDP _TMS
CPU_XDP _TCK0

CPU_XDP _TRST#
XDP_PRE Q#
XDP_PRD Y#

CFG_RCO MP

Trace Width/Space: 4 mil/ 12 mil
Max Trace Length: 600 mil

SM_PG_C TRL <85>

RC18

1 2

TC1 @
TC2 @
TC3 @
TC4 @

TC19 @
TC20 @

49.9_040 2_1%

D

CPU_XDP _TDO <18>
CPU_XDP_TDI <18>
CPU_XDP_TMS <18>
CPU_XDP_TCK0 <18>

CPU_XDP_TRST# <21 >

+1.05VS_ VCCSTG

RC76 51_0402 _5%CMC@

RC77 51_0402 _5%CMC@

RC78 51_0402 _5%CMC@

RC79 51_0402 _5%CMC@

RC80 51_0402 _5%@

RC81 51_0402 _5%@

E

CFG0
CFG2
CFG4
CFG5
CFG6
CFG7

The CFG signals have a default value of '1' if not terminated on the board.

CFG[0]: Stall reset sequence after PCU PLL lock until de-asserted

1 = (Default) Normal Operation;

*

0 = Stall.

CFG[2]: PCI Express* Static x16 Lane Numbering Reversal.

1 = Normal operation
0 = Lane numbers reversed.

*

CFG[4]: eDP enable:

1 = Disabled.
0 = Enabled.

*

CFG[6:5]: PCI Express* Bifurcation:

00 = 1 x8, 2 x4 PCI Express*
01 = reserved
10 = 2 x8 PCI Express*
11 = 1 x16 PCI Express*

*

CFG[7]: PEG Training:

*

1 = (default) PEG Train immediately following RESET# de assertion.
0 = PEG Wait for BIOS for training.

*CFG Pin Use CMC debug on DDX03 R02 Schematic.

To be confirm

XDP_PRE Q#
XDP_PRD Y#

1 2

RC7 1K_040 2_5%@

1 2

RC8 1K_040 2_5%

1 2

RC9 1K_040 2_5%

1 2

RC10 1K_0 402_5%@

1 2

RC11 1K_0 402_5%@

1 2

RC12 1K_0 402_5%@

XDP_PREQ# <21>
XDP_PRD Y# <21>

Place to CPU side

12

12

12

CPU_XDP _TMS

CPU_XDP _TDI

CPU_XDP _TDO

Place to CPU side

12

12

12

CPU_XDP _TCK0

PCH_JTA G_TCK1

CPU_XDP _TRST#

PCH_JTA G_TCK1 <18>

SVID

1 2

H_PROCH OT#<58,83>

EC_VCCS T_PG_R<58,78>

H_PM_DO WN_R<17>

4 4

A

RC14 499 _0402_1%

+1.05V_V CCST

12

RC22
1K_0402 _5%

1 2

RC15 60.4_040 2_1%

1 2

RC16 20_ 0402_5%

12

RH2

@

13_0402 _5%

H_PROCH OT#_R

+1.05V_V CCST

12

12

RC19

Issued Date

Issued Date

Issued Date

56_0402 _1%

EC_VCCS T_PG

H_PM_DO WN CPU_SVID_ ALERT#

B

CPU_SVID_ALERT#_R<89>

CPU_SVID_ DAT<89>

Security Classification

Security Classification

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

RC20
100_040 2_1%

1 2

RC13 220 _0402_5%

CPU_SVID_ DAT

Compal Secret Data

Compal Secret Data

2017/10/ 30 2018/10/ 30

2017/10/ 30 2018/10/ 30

2017/10/ 30 2018/10/ 30

C

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

CFL-H(5/8)CFG,SVID

CFL-H(5/8)CFG,SVID

CFL-H(5/8)CFG,SVID

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

EH5VF M/B LA-H501P

EH5VF M/B LA-H501P

EH5VF M/B LA-H501P

Date : Sheet o f

Date : Sheet o f

D

Date : Sheet o f

10 1 01Friday, February 22, 2019

10 1 01Friday, February 22, 2019

10 1 01Friday, February 22, 2019

E

1A

1A

1A

A

B

C

D

E

GT
32000mA(Hexa Core GT2)

AT14
AT31
AT32
AT33
AT34
AT35
AT36
AT37

1 1

2 2

3 3

4 4

AT38
AU14
AU29
AU30
AU31
AU32
AU35
AU36
AU37
AU38
AV29
AV30
AV31
AV32
AV33
AV34
AV35

AV36
AW14
AW31
AW32
AW33
AW34
AW35
AW36
AW37
AW38

AY29

AY30

AY31

AY32

AY35

AY36

AY37

AY38

BA13

BA14

BA29

BA30

BA31

BA32

BA33

BA34

BA35

BA36

BB13

BB14

BB31

BB32

BB33

BB34

BB35

BB36

BB37

BB38

BC29

BC30

BC31

BC32

BC35

BC36

BC37

BC38

BD13

BD14

BD29

BD30

BD31

BD32

BD33

BD34

BP37

BP38

BR15

BR16

BR17

CFL-H

UC1K

VCCGT1
VCCGT2
VCCGT3
VCCGT4
VCCGT5
VCCGT6
VCCGT7
VCCGT8
VCCGT9
VCCGT10
VCCGT11
VCCGT12
VCCGT13
VCCGT14
VCCGT15
VCCGT16
VCCGT17
VCCGT18
VCCGT19
VCCGT20
VCCGT21
VCCGT22
VCCGT23
VCCGT24
VCCGT25
VCCGT26
VCCGT27
VCCGT28
VCCGT29
VCCGT30
VCCGT31
VCCGT32
VCCGT33
VCCGT34
VCCGT35
VCCGT36
VCCGT37
VCCGT38
VCCGT39
VCCGT40
VCCGT41
VCCGT42
VCCGT43
VCCGT44
VCCGT45
VCCGT46
VCCGT47
VCCGT48
VCCGT49
VCCGT50
VCCGT51
VCCGT52
VCCGT53
VCCGT54
VCCGT55
VCCGT56
VCCGT57
VCCGT58
VCCGT59
VCCGT60
VCCGT61
VCCGT62
VCCGT63
VCCGT64
VCCGT65
VCCGT66
VCCGT67
VCCGT68
VCCGT69
VCCGT70
VCCGT71
VCCGT72
VCCGT73
VCCGT74
VCCGT75
VCCGT76
VCCGT77
VCCGT78
VCCGT79
VCCGT159
VCCGT160
VCCGT161
VCCGT162
VCCGT163

11 OF 13

CFL-H_BG A1440

@

+VCC_GT+ VCC_GT

BD35

VCCGT80

BD36

VCCGT81

BE31

VCCGT82

BE32

VCCGT83

BE33

VCCGT84

BE34

VCCGT85

BE35

VCCGT86

BE36

VCCGT87

BE37

VCCGT88

BE38

VCCGT89

BF13

VCCGT90

BF14

VCCGT91

BF29

VCCGT92

BF30

VCCGT93

BF31

VCCGT94

BF32

VCCGT95

BF35

VCCGT96

BF36

VCCGT97

BF37

VCCGT98

BF38

VCCGT99

BG29

VCCGT100

BG30

VCCGT101

BG31

VCCGT102

BG32

VCCGT103

BG33

VCCGT104

BG34

VCCGT105

BG35

VCCGT106

BG36

VCCGT107

BH33

VCCGT108

BH34

VCCGT109

BH35

VCCGT110

BH36

VCCGT111

BH37

VCCGT112

BH38

VCCGT113

BJ16

VCCGT114

BJ17

VCCGT115

BJ19

VCCGT116

BJ20

VCCGT117

BJ21

VCCGT118

BJ23

VCCGT119

BJ24

VCCGT120

BJ26

VCCGT121

BJ27

VCCGT122

BJ37

VCCGT123

BJ38

VCCGT124

BK16

VCCGT125

BK17

VCCGT126

BK19

VCCGT127

BK20

VCCGT128

BK21

VCCGT129

BK23

VCCGT130

BK24

VCCGT131

BK26

VCCGT132

BK27

VCCGT133

BL15

VCCGT134

BL16

VCCGT135

BL17

VCCGT136

BL23

VCCGT137

BL24

VCCGT138

BL25

VCCGT139

BL26

VCCGT140

BL27

VCCGT141

BL28

VCCGT142

BL36

VCCGT143

BL37

VCCGT144

BM15

VCCGT145

BM16

VCCGT146

BM17

VCCGT147

BM36

VCCGT148

BM37

VCCGT149

BN15

VCCGT150

BN16

VCCGT151

BN17

VCCGT152

BN36

VCCGT153

BN37

VCCGT154

BN38

VCCGT155

BP15

VCCGT156

BP16

VCCGT157

BP17

VCCGT158

BR37

VCCGT164

BT15

VCCGT165

BT16

VCCGT166

BT17

VCCGT167

BT37

VCCGT168

VSSGT_S ENSE

VSSGT_SENSE
VCCGT_SENSE

AH37

VCCGT_S ENSE

AH38

1. VccGT_S ENSE / VssGT_SENSE Trace Length Ma tch < 25 mil s

2. Ma intain 25-mil separation distance away from any other dynamic sign als.

+VCC_CO RE +VCC_CO RE +VCC_CO RE +VCC_CO RE

AA13
AA31
AA32
AA33
AA34
AA35
AA36
AA37
AA38
AB29
AB30
AB31
AB32
AB35
AB36
AB37
AB38
AC13
AC14
AC29
AC30
AC31
AC32
AC33
AC34
AC35
AC36
AD13
AD14
AD31
AD32
AD33
AD34
AD35
AD36
AD37
AD38
AE13
AE14
AE30
AE31
AE32
AE35
AE36
AE37
AE38

AF29
AF30
AF31
AF32
AF33
AF34
AF35
AF36
AF37

AF38
AG14
AG31
AG32
AG33
AG34
AG35
AG36

CFL-H_BG A1440

@

VSSGT_S ENSE <89>

VCCGT_S ENSE < 89>

UC1I

VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63

CFL-H

AH13

VCC64

AH14

VCC65

AH29

VCC66

AH30

VCC67

AH31

VCC68

AH32

VCC69

AJ14

VCC70

AJ29

VCC71

AJ30

VCC72

AJ31

VCC73

AJ32

VCC74

AJ33

VCC75

AJ34

VCC76

AJ35

VCC77

AJ36

VCC78

AK31

VCC79

AK32

VCC80

AK33

VCC81

AK34

VCC82

AK35

VCC83

AK36

VCC84

AK37

VCC85

AK38

VCC86

AL13

VCC87

AL29

VCC88

AL30

VCC89

AL31

VCC90

AL32

VCC91

AL35

VCC92

AL36

VCC93

AL37

VCC94

AL38

VCC95

AM13

VCC96

AM14

VCC97

AM29

VCC98

AM30

VCC99

AM31

VCC100

AM32

VCC101

AM33

VCC102

AM34

VCC103

AM35

VCC104

AM36

VCC105

AN13

VCC106

AN14

VCC107

AN31

VCC108

AN32

VCC109

AN33

VCC110

AN34

VCC111

AN35

VCC112

AN36

VCC113

AN37

VCC114

AN38

VCC115

AP13

VCC116

AP30

VCC117

AP31

VCC118

AP32

VCC119

AP35

VCC120

AP36

VCC121

AP37

VCC122

AP38

VCC123

K13

VCC124

VCC_SENSE

9 OF 13

VSS_SENSE

1. Vcc_S ENSE/ Vss _SENSE Tr ace Length Match < 25 mils

2. Ma intain 25-mil separation distance away from any other dynamic sign als.

AG37
AG38

128000mA(Hexa Core GT2)

VCCSENS E
VSSSENS E

VCCSENS E <8 9>

VSSSENS E <89>

K14

L13

L14
N13
N14
N30
N31
N32
N35
N36
N37
N38
P13
P14
P29
P30
P31
P32
P33
P34
P35
P36
R13
R31
R32
R33
R34
R35
R36
R37
R38
T29
T30
T31
T32
T35
T36
T37
T38
U29
U30
U31
U32
U33
U34
U35
U36
V13
V14
V31
V32
V33
V34
V35
V36
V37
V38

W13
W14
W29
W30
W31
W32

CFL-H_BG A1440

@

UC1J

VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63

CFL-H

10 OF 13

VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCC72
VCC73
VCC74
VCC75

W35
W36
W37
W38
Y29
Y30
Y31
Y32
Y33
Y34
Y35
Y36

Security Classification

Security Classification

Security Classification

2017/10/ 30 2018/10/ 30

2017/10/ 30 2018/10/ 30

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

2017/10/ 30 2018/10/ 30

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

CFL-H(6/8)VCC_CORE/GT

CFL-H(6/8)VCC_CORE/GT

CFL-H(6/8)VCC_CORE/GT

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

EH5VF M/B LA-H501P

EH5VF M/B LA-H501P

EH5VF M/B LA-H501P

Date : Sheet o f

Date : Sheet o f

D

Date : Sheet o f

11 1 01Friday, February 22, 2019

11 1 01Friday, February 22, 2019

11 1 01Friday, February 22, 2019

E

1A

1A

1A

A

+1.2V_VDDQ

+VCC_SA

+VCC_SA
Max: 11100mA

1 1

+VCC_IO
Max: 6400mA

2 2

+VCCIO

K29
K30
K31
K32
K33
K34
K35
L31
L32
L35
L36
L37

L38
M29
M30
M31
M32
M33
M34
M35
M36

AG12

G15
G17
G19
G21

H15

H16

H17

H19

H20

H21

H26

H27

J30

J15
J16
J17
J19
J20
J21
J26
J27

CFL-H_BG A1440

@

UC1L

VCCSA1
VCCSA2
VCCSA3
VCCSA4
VCCSA5
VCCSA6
VCCSA7
VCCSA8
VCCSA9
VCCSA10
VCCSA11
VCCSA12
VCCSA13
VCCSA14
VCCSA15
VCCSA16
VCCSA17
VCCSA18
VCCSA19
VCCSA20
VCCSA21
VCCSA22

VCCIO1
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
VCCIO8
VCCIO9
VCCIO10
VCCIO11
VCCIO12
VCCIO13
VCCIO14
VCCIO15
VCCIO16
VCCIO17
VCCIO18
VCCIO19
VCCIO20
VCCIO21

CFL-H

12 OF 13

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8

VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18
VDDQ19
VDDQ20
VDDQ21
VDDQ22
VDDQ23
VDDQ24
VDDQ25

VCCPLL_OC1
VCCPLL_OC2
VCCPLL_OC3

VCCST

VCCSTG2

VCCSTG1

VCCPLL1
VCCPLL2

VCCSA_SENSE
VSSSA_SENSE

VCCIO_SENSE

VSSIO_SENSE

Max: 3300mA

+1.2V_VD DQ

AA6
AE12
AF5
AF6
AG5
AG9
AJ12
AL11
AP6
AP7
AR12
AR6
AT12
AW6
AY6
J5
J6
K12
K6
L12
L6
R6
T6
W6
Y12

+1.2V_VC CPLL_OC

BH13
BJ13
G11

H30

H29

G30

H28
J28

M38
M37

H14
J14

B

+1.2V_VD DQ

+1.2V_VCCPLL_OC
Max: 130mA

+1.05V_V CCST

Max: 60mA

Max: 20mA

Max: 150mA

VCCIO_SEN SE
VSSIO_SEN SE

1. VccGT_S ENSE / VssGT_SENSE Trace Length Ma tch < 25 mil s

2. Ma intain 25-mil separation distance away from any other dynamic sign als.

+1.05VS_ VCCSTG

+1.05V_V CCSFR

VCCSA_S ENSE
VSSSA_S ENSE

VCCSA_S ENSE <89>

VSSSA_S ENSE <89 >

VCCIO_SEN SE <88>

VSSIO_SEN SE <8 8>

C

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

1

1

2

CC71

CC70

2

571483_CFL_H_RVP_CRB_TDK_Rev0p5
+1.2V_VDDQ_CPU: 10uF * 12 22uF * 4

1

1

CC72

2

2

10U_0402_6.3V6M

CC73

10U_0402_6.3V6M

1

CC74

2

RC24 0_0 402_5%@

10U_0402_6.3V6M

1

CC75

2

10U_0402_6.3V6M

10U_0402_6.3V6M

1

1

CC76

CC77

2

2

PLACE CAP BACKSIDE

+1.2V_VC CPLL_OC+1.2 V_VDDQ

1 2

1

2

571483_CFL_H_RVP_CRB_TDK_Rev0p5
+1.2V_VCCPLL_OC: 1uF * 2

PLACE CAP BACKSIDE

+1.05V_V CCST

1U_0201_6.3V6M

1

CC92

2

571483_CFL_H_RVP_CRB_TDK_Rev0p5
+1.05V_VCCST: 1uF * 1

10U_0402_6.3V6M

1

CC78

2

1U_0201_6.3V6M

1

CC86

2

RC25 0_0 402_5%@

D

10U_0402_6.3V6M

1

CC79

2

1U_0201_6.3V6M

CC87

1 2

E

22U_0603_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

1

1

CC80

2

2

1

CC81

+VCCIO

150mA

CC82

2

10U_0402_6.3V6M

10U_0402_6.3V6M

1

1

CC88

2

2

571483_CFL_H_RVP_CRB_TDK_Rev0p5
+0.95VS_VCCIO: 10uF * 12 22uF * 4

+1.05V_V CCSFR

1U_0201_6.3V6M

1

CC93

2

571483_CFL_H_RVP_CRB_TDK_Rev0p5
+1.05V_VCCSFR: 1uF * 1

22U_0603_6.3V6M

22U_0603_6.3V6M

1

CC83

2

10U_0402_6.3V6M

1

CC89

2

22U_0603_6.3V6M

1

1

CC84

CC85

2

2

10U_0402_6.3V6M

1

@

CC91

CC90

2

PLACE CAP BACKSIDE PLACE CAP BACKSIDE

3 3

4 4

Security Classification

Security Classification

Security Classification

2017/10/ 30 2018/10/ 30

2017/10/ 30 2018/10/ 30

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

2017/10/ 30 2018/10/ 30

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

+1.05VS_ VCCSTG

1U_0201_6.3V6M

1

CC94

2

571483_CFL_H_RVP_CRB_TDK_Rev0p5
+1.05VS_VCCSTG: 1uF * 1

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

CFL-H(7/8)VCCSA/VCCIO/VDDQ

CFL-H(7/8)VCCSA/VCCIO/VDDQ

CFL-H(7/8)VCCSA/VCCIO/VDDQ

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

EH5VF M/B LA-H501P

EH5VF M/B LA-H501P

EH5VF M/B LA-H501P

Date : Sheet o f

Date : Sheet o f

Date : Sheet o f

12 1 01Friday, February 22, 2019

12 1 01Friday, February 22, 2019

12 1 01Friday, February 22, 2019

E

1A

1A

1A

A

B

C

D

E

CFL-H

UC1F

A10

VSS_1

A12

VSS_2

A16

VSS_3

A18

VSS_4

A20

VSS_5

A22

VSS_6

A24

VSS_7

A26

VSS_8

1 1

2 2

3 3

A28
A30

AA12
AA29
AA30
AB33
AB34

AB6

AC1

AC12

AC2

AC3
AC37
AC38

AC4

AC5

AC6
AD10
AD11
AD12
AD29
AD30

AD6

AD8

AD9
AE33
AE34

AE6

AF1
AF12
AF13
AF14

AF2

AF3

AF4
AG10
AG11
AG13
AG29
AG30

AG6
AG7

AG8
AH12
AH33
AH34
AH35
AH36

AH6

AJ1

AJ13

AJ2

AJ3
AJ37
AJ38

AJ4

AJ5

AJ6

Y10

Y11

Y13

Y14

Y37

Y38

AK29
AK30

A6
A9

W4
W5

Y7
Y8
Y9

VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80

6 OF 13

VSS_81

CFL-H_BG A1440

@

VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98

VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162

AK4
AL10
AL12
AL14
AL33
AL34
AL4
AL7
AL8
AL9
AM1
AM12
AM2
AM3
AM37
AM38
AM4
AM5
AN12
AN29
AN30
AN5
AN6
AP10
AP11
AP12
AP33
AP34
AP8
AP9
AR1
AR13
AR14
AR2
AR29
AR3
AR30
AR31
AR32
AR33
AR34
AR35
AR36
AR37
AR38
AR4
AR5
AT29
AT30
AT6
AU10
AU11
AU12
AU33
AU34
AU6
AU7
AU8
AU9
AV37
AV38
AW1
AW12
AW2
AW29
AW3
AW30
AW4
U6
V12
V29
V30
A14
AD7
V6
W1
W12
W2
W3
W33
W34

AW5
AY12
AY33
AY34

BA10
BA11
BA12
BA37
BA38

BA6
BA7
BA8
BA9
BB1

BB12

BB2

BB29

BB3

BB30

BB4
BB5

BB6
BC12
BC13
BC14
BC33
BC34

BC6
BD10
BD11
BD12
BD37

BD6

BD7

BD8

BD9

BE1
BE2

BE29

BE3

BE30

BE4
BE5

BE6
BF12
BF33
BF34

BF6

BG12
BG13
BG14
BG37
BG38

BG6

BH1
BH10
BH11
BH12
BH14

BH2

BH3

BH4

BH5

BH6

BH7

BH8

BH9

T33
T34

U37

U38
BJ12
BJ14

UC1G

VSS_163
VSS_164
VSS_165
VSS_166

B9

VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230

T2

VSS_231

T3

VSS_232
VSS_233
VSS_234

T4

VSS_235

T5

VSS_236

T7

VSS_237

T8

VSS_238

T9

VSS_239
VSS_240
VSS_241
VSS_242
VSS_243

CFL-H_BG A1440

@

CFL-H

7 OF 13

VSS_244
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
VSS_253
VSS_254
VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272
VSS_273
VSS_274
VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
VSS_314
VSS_315
VSS_316
VSS_317
VSS_318
VSS_319
VSS_320
VSS_321
VSS_322
VSS_323
VSS_324

BJ15
BJ18
BJ22
BJ25
BJ29
BJ30
BJ31
BJ32
BJ33
BJ34
BJ35
BJ36
BK13
BK14
BK15
BK18
BK22
BK25
BK29
BK6
BL13
BL14
BL18
BL19
BL20
BL21
BL22
BL29
BL33
BL35
BL38
BL6
BM11
BM12
BM13
BM14
BM18
BM2
BM21
BM22
BM23
BM24
BM25
BM26
BM27
BM28
BM29
BM3
BM33
BM35
BM38
BM5
BM6
BM7
BM8
BM9
BN12
BN14
BN18
BN19
BN2
BN20
BN21
BN24
BN29
BN30
BN31
BN34
P38
P6
R12
R29
AY14
BD38
R30
T1
T10
T11
T12
T13
T14

BN4

BN7
BP12
BP14
BP18
BP21
BP24
BP25
BP26
BP29
BP33
BP34

BP7
BR12
BR14
BR18
BR21
BR24
BR25
BR26
BR29
BR34
BR36

BR7

BT12
BT14
BT18
BT21
BT24
BT26
BT29
BT32

BT5

C11

C13

C15

C17

C19

C21

C23

C25

C27

C29

C31

C37

D10

D12

D14

D16

D18

D20

D22

D24

D26

D28

D30

D33

E34

E35

E38

N33

N34

P12

P37

M14

M6

F11
F13

UC1H

VSS_325
VSS_326
VSS_327
VSS_328
VSS_329
VSS_330
VSS_331
VSS_332
VSS_333
VSS_334
VSS_335
VSS_336
VSS_337
VSS_338
VSS_339
VSS_340
VSS_341
VSS_342
VSS_343
VSS_344
VSS_345
VSS_346
VSS_347
VSS_348
VSS_349
VSS_350
VSS_351
VSS_352
VSS_353
VSS_354
VSS_355
VSS_356
VSS_357
VSS_358
VSS_359
VSS_360
VSS_361
VSS_362
VSS_363
VSS_364
VSS_365
VSS_366
VSS_367
VSS_368
VSS_369

C5

VSS_370

C8

VSS_371

C9

VSS_372
VSS_373
VSS_374
VSS_375
VSS_376
VSS_377
VSS_378
VSS_379
VSS_380
VSS_381
VSS_382

D3

VSS_383
VSS_384
VSS_385

D6

VSS_386

D9

VSS_387
VSS_388
VSS_389
VSS_390

E4

VSS_391

E9

VSS_392

N3

VSS_393
VSS_394
VSS_395

N4

VSS_396

N5

VSS_397

N6

VSS_398

N7

VSS_399

N8

VSS_400

N9

VSS_401
VSS_402
VSS_403
VSS_404
VSS_405

N1

VSS_406
VSS_407
VSS_408

CFL-H_BG A1440

@

CFL-H

VSS_409
VSS_410
VSS_411
VSS_412
VSS_413
VSS_414
VSS_415
VSS_416
VSS_417
VSS_418
VSS_419
VSS_420
VSS_421
VSS_422
VSS_423
VSS_424
VSS_425
VSS_426
VSS_427
VSS_428
VSS_429
VSS_430
VSS_431
VSS_432
VSS_433
VSS_434
VSS_435
VSS_436
VSS_437
VSS_438
VSS_439
VSS_440
VSS_441
VSS_442
VSS_443
VSS_444
VSS_445
VSS_446
VSS_447
VSS_448
VSS_449
VSS_450
VSS_451
VSS_452
VSS_453
VSS_454
VSS_455
VSS_456
VSS_457
VSS_458
VSS_459
VSS_460
VSS_461
VSS_462
VSS_463
VSS_464
VSS_465
VSS_466
VSS_467
VSS_468
VSS_469
VSS_470
VSS_471
VSS_472
VSS_473
VSS_474
VSS_475
VSS_476
VSS_477
VSS_478
VSS_479

VSS_A34

VSS_B37

VSS_BR38

VSS_BT3
VSS_BT35
VSS_BT36

VSS_BT4

8 OF 13

VSS_D38

VSS_A3

VSS_A4
VSS_B3

VSS_C2

F15
F17
F19
F2
F21
F23
F25
F27
F29
F3
F31
F36
F4
F5
F8
F9
G10
G12
G14
G16
G18
G20
G22
G23
G24
G26
G28
G4
G5
G6
G8
G9
H11
H12
H18
H22
H25
H32
H35
J10
J18
J22
J25
J32
J33
J36
J4
J7
K1
K10
K11
K2
K3
K38
K4
K5
K7
K8
K9
L29
L30
L33
L34
M12
M13
N10
N11
N12
N2
BT8
BR9

A3
A34
A4
B3
B37
BR38
BT3
BT35
BT36
BT4
C2
D38

Impedance Spectrum Tool Trigger

PCH_TRIGO UT_R<21>
CPU_TRIGO UT_R<21>

1 2

RC26 30_ 0402_5%

TC7@

IST_TRIG

TC8@

TC9@
TC10@

TC11@
TC12@

PCH_TRIGO UT_R
CPU_TRIGO UT

BN35

BN33

BL34

AE29
AA14
AP29
AP14

BR35
BR31
BH30

BR1
BT2

J24

H24

N29
R14

A36

A37

H23

J23

F30

E30

B30
C30

E2
E3
E1
D1

G3

J3

UC1M

RSVD_TP5
IST_TRIG
RSVD_TP4
RSVD_TP3

RSVD_TP1
RSVD_TP2

RSVD15

RSVD28
RSVD27
RSVD14
RSVD13

RSVD30
RSVD31
RSVD2
RSVD1
RSVD5
RSVD4
VSS_A36

VSS_A37

PROC_TRIGIN
PROC_TRIGOUT

RSVD24

RSVD23

RSVD7
RSVD21

RSVD26
RSVD29

RSVD19
RSVD18
RSVD9

CFL-H_BG A1440

@

CFL-H

13 OF 13

BK28

RSVD11

BJ28

RSVD10

BL31

RSVD12

AJ8

RSVD3

G13

RSVD25

C38

RSVD22

C1

RSVD20

BR2

RSVD17

BP1

RSVD16

B38

RSVD8

B2

RSVD6

Add for Corner NCTF testing

TC13 @
TC14 @
TC15 @
TC16 @
TC17 @
TC18 @

4 4

Security Classification

Security Classification

Security Classification

2017/10/ 30 2018/10/ 30

2017/10/ 30 2018/10/ 30

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

2017/10/ 30 2018/10/ 30

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

CFL-H(8/8)GND/RSVD

CFL-H(8/8)GND/RSVD

CFL-H(8/8)GND/RSVD

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

EH5VF M/B LA-H501P

EH5VF M/B LA-H501P

EH5VF M/B LA-H501P

Date : Sheet o f

Date : Sheet o f

D

Date : Sheet o f

13 1 01Friday, February 22, 2019

13 1 01Friday, February 22, 2019

13 1 01Friday, February 22, 2019

E

1A

1A

1A

A

DMI_CTX_P RX_N0<9>

DMI_CTX_P RX_P0< 9>
DMI_CRX_P TX_N0<9>
DMI_CRX_P TX_P0< 9>

DMI_CTX_P RX_N1<9>

DMI_CTX_P RX_P1< 9>
DMI_CRX_P TX_N1<9>
DMI_CRX_P TX_P1< 9>

DMI_CTX_P RX_N2<9>

DMI_CTX_P RX_P2< 9>

1 1

The 30 HSIO lanes on PCH-H supports the following configurations:

1. Up to 24 PCIe* Lanes

— A maximum of 16 PCIe* Ports (or devices) can be enabled

When a GbE Port is enabled, the maximum number of PCIe* Ports (or

‧‧‧‧

devices) that can be enabled reduces based off the following:
Max PCIe* Ports (or devices) = 16 - GbE (0 or 1)
— PCIe* Lanes 1-4 (PCIe* Controller #1), 5-8 (PCIe* Controller #2), 9-12 (PCIe*
Controller #3), 13-16 (PCIe* Controller #4), 17-20 (PCIe* Controller #5), and
21-24 (PCIe* Controller #6) can be individually configured

2. Up to 6 SATA Lanes
— A maximum of 6 SATA Ports (or devices) can be enabled
— SATA Lane 0 has the flexibility to be mapped to Flex I/O Lane 16 or 18
— SATA Lane 1 has the flexibility to be mapped to Flex I/O Lane 17 or 19

3. Up to 10 USB 3.1 Lanes
— A maximum of 10 USB 3.1 Ports (or devices) can be enabled

4. Up to 4 GbE Lanes
— A maximum of 1 GbE Port (or device) can be enabled

5. Supports up to 3 Remapped (IntelR Rapid Storage Technology) PCIe* storage
devices
— x2 and x4 PCIe* NVMe SSD
— x2 IntelR Optane? Memory Device
— See the “ PC I Express* (PCIe*)” chapt er for t he P CH PCIe* Controllers,configurations
, and lanes that can be used for IntelR Rapid Storage Technology PCIe* storage support

6. For unused SATA/PCIe* Combo Lanes, Flex I/O Lanes that can be configured as PCIe* or SATA,
the lanes must be statically assigned to SATA or PCIe* via the SATA/PCIe Combo Port Soft
Straps discussed in the SPI Programming Guide and
through the IntelR Flash Image Tool (FIT) tool.

2 2

3 3

DMI_CRX_P TX_N2<9>
DMI_CRX_P TX_P2< 9>

DMI_CTX_P RX_N3<9>

DMI_CTX_P RX_P3< 9>
DMI_CRX_P TX_N3<9>
DMI_CRX_P TX_P3< 9>

B

DMI_CTX_P RX_N0

DMI_CTX_P RX_P0
DMI_CRX_P TX_N0
DMI_CRX_P TX_P0

DMI_CTX_P RX_N1

DMI_CTX_P RX_P1
DMI_CRX_P TX_N1
DMI_CRX_P TX_P1

DMI_CTX_P RX_N2

DMI_CTX_P RX_P2
DMI_CRX_P TX_N2
DMI_CRX_P TX_P2

DMI_CTX_P RX_N3

DMI_CTX_P RX_P3
DMI_CRX_P TX_N3
DMI_CRX_P TX_P3

UH1B

K34

DMI0_RXN

J35

DMI0_RXP

C33

DMI0_TXN

B33

DMI0_TXP

G33

DMI1_RXN

F34

DMI1_RXP

C32

DMI1_TXN

B32

DMI1_TXP

K32

DMI2_RXN

J32

DMI2_RXP

C31

DMI2_TXN

B31

DMI2_TXP

G30

DMI3_RXN

F30

DMI3_RXP

C29

DMI3_TXN

B29

DMI3_TXP

A25

RSVD

B25

RSVD

P24

RSVD

R24

RSVD

C26

RSVD

B26

RSVD

F26

RSVD

G26

RSVD

B27

RSVD

C27

RSVD

L26

RSVD

M26

RSVD

D29

RSVD

E28

RSVD

K29

RSVD

M29

RSVD

G17

PCIE1_RXN/USB31_7_RXN

F16

PCIE1_RXP/USB31_7_RXP

A17

PCIE1_TXN/USB31_7_TXN

B17

PCIE1_TXP/USB31_7_TXP

R21

PCIE2_RXN/USB31_8_RXN

P21

PCIE2_RXP/USB31_8_RXP

B18

PCIE2_TXN/USB31_8_TXN

C18

PCIE2_TXP/USB31_8_TXP

K18

PCIE3_RXN/USB31_9_RXN

J18

PCIE3_RXP/USB31_9_RXP

B19

PCIE3_TXN/USB31_9_TXN

C19

PCIE3_TXP/USB31_9_TXP

N18

PCIE4_RXN/USB31_10_RXN

R18

PCIE4_RXP/USB31_10_RXP

D20

PCIE4_TXN/USB31_10_TXN

C20

PCIE4_TXP/USB31_10_TXP

F20

PCIE5_RXN

G20

PCIE5_RXP

B21

PCIE5_TXN

A22

PCIE5_TXP

K21

PCIE6_RXN

J21

PCIE6_RXP

D21

PCIE6_TXN

C21

PCIE6_TXP

B23

PCIE7_TXP

C23

PCIE7_TXN

J24

PCIE7_RXP

L24

PCIE7_RXN

F24

PCIE8_RXN

G24

PCIE8_RXP

B24

PCIE8_TXN

C24

PCIE8_TXP

CNP-H_BG A874

@

C

CNP-H

GPP_E9/USB2_OC0#
GPP_E10/USB2_OC1#
GPP_E11/USB2_OC2#
GPP_E12/USB2_OC3#
GPP_F15/USB2_OC4#
GPP_F16/USB2_OC5#
GPP_F17/USB2_OC6#
GPP_F18/USB2_OC7#

USB2_VBUSSENSE

2 OF 13

USB2N_1
USB2P_1
USB2N_2
USB2P_2
USB2N_3
USB2P_3
USB2N_4
USB2P_4
USB2N_5
USB2P_5
USB2N_6
USB2P_6
USB2N_7
USB2P_7
USB2N_8
USB2P_8
USB2N_9

USB2P_9
USB2N_10
USB2P_10
USB2N_11
USB2P_11
USB2N_12
USB2P_12
USB2N_13
USB2P_13
USB2N_14
USB2P_14

USB2_COMP

RSVD1

USB2_ID

GPD7

PCIE24_TXP
PCIE24_TXN
PCIE24_RXP
PCIE24_RXN

PCIE23_TXP
PCIE23_TXN
PCIE23_RXP
PCIE23_RXN

PCIE22_TXP
PCIE22_TXN
PCIE22_RXP
PCIE22_RXN

PCIE21_TXP
PCIE21_TXN
PCIE21_RXP
PCIE21_RXN

Rev1.0

J3
J2
N13
N15
K4
K3
M10
L9
M1
L2
K7
K6
L4
L3
G4
G5
M6
N8
H3
H2
R10
P9
G1
G2
N3
N2
E5
F6

AH36
AL40
AJ44
AL41
AV47
AR35
AR37
AV43

F4
F3
U13
G3

BE41

G45
G46
Y41
Y40
G48
G49
W44
W43
H48
H47
U41
U40
F46
G47
R44
T43

USB20_N 1
USB20_P 1
USB20_N 2
USB20_P 2
USB20_N 3
USB20_P 3
USB20_N 4
USB20_P 4
USB20_N 5
USB20_P 5
USB20_N 6
USB20_P 6

USB20_N 8
USB20_P 8

USB20_N 14
USB20_P 14

USB_OC0 #
USB_OC1 #

USB2_RC OMP
USB2_VB US_SENSE

USB2_ID

GPD_7

D

USB20_N 1 <71>
USB20_P 1 <71>
USB20_N 2 <43>
USB20_P 2 <43>
USB20_N 3 <72>
USB20_P 3 <72>
USB20_N 4 <73>
USB20_P 4 <73>
USB20_N 5 <38>
USB20_P 5 <38>
USB20_N 6 <38>
USB20_P 6 <38>

USB20_N 8 <66>
USB20_P 8 <66>

USB20_N 14 <52>
USB20_P 14 <52>

USB_OC0 # <43>

USB_OC1 # <71>

1 2

RH4 113_040 2_1%

1 2

RH5 0_0402_ 5%@

1 2

RH6 0_0402_ 5%@

PCIE_PTX_ DRX_P24 <68>
PCIE_PTX_ DRX_N24 < 68>

PCIE_PRX_ DTX_P24 <68>
PCIE_PRX_ DTX_N24 < 68>
PCIE_PTX_ DRX_P23 <68>
PCIE_PTX_ DRX_N23 < 68>

PCIE_PRX_ DTX_P23 <68>
PCIE_PRX_ DTX_N23 < 68>
PCIE_PTX_ DRX_P22 <68>
PCIE_PTX_ DRX_N22 < 68>

PCIE_PRX_ DTX_P22 <68>
PCIE_PRX_ DTX_N22 < 68>
PCIE_PTX_ DRX_P21 <68>
PCIE_PTX_ DRX_N21 < 68>

PCIE_PRX_ DTX_P21 <68>
PCIE_PRX_ DTX_N21 < 68>

USB3 MB

TYPE C

USB3 MB

USB2 (SUB/B)

Camera

TS

FingerPrint

USB_OC0 #

RH200 10K_ 0402_5%

USB_OC1 #

RH201 10K_ 0402_5%

BT

For CNVI follow 571906_CNL_PCH_TA_WW11.pdf

GPD_7

STRAP

X'tal Input:
High: Differential
Low: Single ended

E

1 2
1 2

+3VALW

12

12

RH3
10K_040 2_5%

RH7
10K_040 2_5%

@

+3VALW

4 4

Security Classification

Security Classification

Security Classification

2017/10/ 30 2018/10/ 30

2017/10/ 30 2018/10/ 30

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

2017/10/ 30 2018/10/ 30

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

PCH(1/8)DMI/PCIE/USB2

PCH(1/8)DMI/PCIE/USB2

PCH(1/8)DMI/PCIE/USB2

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

EH5VF M/B LA-H501P

EH5VF M/B LA-H501P

EH5VF M/B LA-H501P

Date : Sheet o f

Date : Sheet o f

D

Date : Sheet o f

14 1 01Friday, February 22, 2019

14 1 01Friday, February 22, 2019

14 1 01Friday, February 22, 2019

E

1A

1A

1A

A

Vinafix

B

C

D

E

PCH-H XTAL_IN/OUT POR is 24MHz for 571697_CNL_MOW_WW16_2017.pdf

RH8 1M_0402_5%

YH1
24MHZ_1 8PF_7R240000 01

1 1

2 2

3

33P_0402_50V8J

3

CH5

10P_0402_50V8J

1

32.768KH Z_9PF_X1A000 141000200

CH7

2

Trace Space: 15 mil
Max Trace Length: 1000 mil

XTAL_24 M_PCH_OUT

4

NC

2

XTAL_24 M_PCH_IN

1

1 2

NC

1 2

RH12 10M _0402_5%

YH2

1 2

1 2

EMI@

RH11 33_ 0402_1%

1 2

EMI@

RH9 33_0402_1%

1

18P_0402_50V8J

CH6

PCH_RTC X1

PCH_RTC X2

XTAL_24 M_PCH_OUT_R

XTAL_24 M_PCH_IN_R

PCH_CPU _24M_CLK_P<10>
PCH_CPU _24M_CLK_N<10>

PCH_CPU _BCLK_P<10>
PCH_CPU _BCLK_N<10> PCH_CPU _PCIBCLK_P <10>

1 2

XCLK_BIASREF (PDG)
Trace Width/Space: 15mil /15 mil
Max Trace Length: 1000 mil
8/24

RH10 60.4_ 0402_1%

WLA N_CLKREQ#<52>
SSD1_CL KREQ#<68>
SSD2_CL KREQ#<68>

remove no use srcclkreq

10P_0402_50V8J

1

CH8

2

remove TP as C5PRH

PCH_CPU _24M_CLK_P
PCH_CPU _24M_CLK_N

PCH_CPU _BCLK_P
PCH_CPU _BCLK_N

XTAL_24 M_PCH_OUT_R
XTAL_24 M_PCH_IN_R

XCLK_BIAS REF

PCH_RTC X1
PCH_RTC X2

LAN_CLK REQ#<51>

VGA_CLK REQ#

use same part w C5MMH

+3VS

12

12

A

LAN_CLK REQ#

WLA N_CLKREQ#
SSD1_CL KREQ#
SSD2_CL KREQ#

CNV_BRI_P TX_DRX

GPP_J9

CNV_RGI_P TX_DRX

VGA_CLK REQ# <2 7>

STRAP

STRAP

STRAP

AW13

BE9

BF8
BF9

BG8

remove SD signal from PCH

remove CPU_C10_GATE#

CNV_BRI_P TX_DRX<52>
CNV_BRI_P RX_DTX<52>
CNV_RGI_P TX_DRX<52>
CNV_RGI_P RX_DTX<52>

+1.8VALW _PRIM

1 2

RH181 20K_04 02_1%CNVI@

1 2

571391_CFL_H_PDG_Rev0p71
To avoid floating input at the I/O pin BRI_RSP and RGI_RSP it is recommended to add
a weak pull up resistor to the SoC pin with a recommended value of 20K ohm.

B

RH182 20K_04 02_1%CNVI@

CNV_BRI_P TX_DRX
CNV_BRI_P RX_DTX
CNV_RGI_P TX_DRX
CNV_RGI_P RX_DTX

GPP_J9

CNV_BRI_P RX_DTX

CNV_RGI_P RX_DTX

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

BE8
BD8

AV13

AP3
AP2
AN4
AM7

AV6
AY3

AR13

AV7
AW3
AT10

AV4

AY2

BA4

AV3
AW2

AU9

2017/10/ 30 2018/10/ 30

2017/10/ 30 2018/10/ 30

2017/10/ 30 2018/10/ 30

C

1 2

RH204 10K_ 0402_5%

1 2

RH205 10K_ 0402_5%

1 2

RH206 10K_ 0402_5%

1 2

RH207 10K_ 0402_5%

1 2

RH220 10K_ 0402_5%

For DDX03 R02

+1.8VALW _PRIM

3 3

+1.8VALW _PRIM

+1.8VALW _PRIM

4 4

XTAL Frequency Select

1 2

RH15 4.7K_0 402_5%

This signal has a weak internal pull-down 20K.
0 = 38.4/19.2MHz XTAL frequency selected.
1 = 24MHz XTAL frequency selected. (DDX03)
Notes:

1. The internal pull-down is disabled after RSMRST#
de-asserts.

2. This signal is in the primary well.

VCCPSPI Select

@

1 2

RH21 4.7K_0 402_5%

The signal has a weak internal pull-down 20K
0 = VCCPSPI is connected to 3.3V rail
1 = VCCPSPI is connected to 1.8V rail
Note: If VCCPSPI is connected to 1.8V rail, this pin

strap must be a ‘ 1’ fo r the prope r functionality
of the SPI (Flash) I/Os

M.2 CNV Mode Select

RH22 10K_04 02_5%

RH23 10K_04 02_5%@

An external pull-up or pull-down is required.
0 = Integrated CNVi enable.
1 = Integrated CNVi disable.

Pulled down by CRF CNVi RGI_DT pin

UH1G

BE33

GPP_A16/CLKOUT_48

D7

CLKOUT_CPUNSSC_P

C6

CLKOUT_CPUNSSC#

B8

CLKOUT_CPUBCLK_P

C8

CLKOUT_CPUBCLK#

U9

XTAL_OUT

U10

XTAL_IN

T3

XCLK_BIASREF

BA49

RTCX1

BA48

RTCX2

BF31

GPP_B5/SRCCLKREQ0#

BE31

GPP_B6/SRCCLKREQ1#

AR32

GPP_B7/SRCCLKREQ2#

BB30

GPP_B8/SRCCLKREQ3#

BA30

GPP_B9/SRCCLKREQ4#

AN29

GPP_B10/SRCCLKREQ5#

AE47

GPP_H0/SRCCLKREQ6#

AC48

GPP_H1/SRCCLKREQ7#

AE41

GPP_H2/SRCCLKREQ8#

AF48

GPP_H3/SRCCLKREQ9#

AC41

GPP_H4/SRCCLKREQ10#

AC39

GPP_H5/SRCCLKREQ11#

AE39

GPP_H6/SRCCLKREQ12#

AB48

GPP_H7/SRCCLKREQ13#

AC44

GPP_H8/SRCCLKREQ14#

AC43

GPP_H9/SRCCLKREQ15#

V2

CLKOUT_PCIE_N15

V3

CLKOUT_PCIE_P15

T2

CLKOUT_PCIE_N14

T1

CLKOUT_PCIE_P14

AA1

CLKOUT_PCIE_N13

Y2

CLKOUT_PCIE_P13

AC7

CLKOUT_PCIE_N12

AC6

CLKOUT_PCIE_P12

CNP-H_BG A874

@

UH1M

GPP_G0/SD_CMD
GPP_G1/SD_DATA0
GPP_G2/SD_DATA1
GPP_G3/SD_DATA2
GPP_G4/SD_DATA3
GPP_G5/SD_CD#
GPP_G6/SD_CLK
GPP_G7/SD_WP

GPP_I11/M2_SKT2_CFG0
GPP_I12/M2_SKT2_CFG1
GPP_I13/M2_SKT2_CFG2
GPP_I14/M2_SKT2_CFG3

GPP_J0/CNV_PA_BLANKING
GPP_J1/CPU_C10_GATE#
GPP_J11/A4WP_PRESENT
GPP_J10
GPP_J_2
GPP_J_3
GPP_J4/CNV_BRI_DT/UART0B_RTS#
GPP_J5/CNV_BRI_RSP/UART0B_RXD
GPP_J6/CNV_RGI_DT/UART0B_TXD
GPP_J7/CNV_RGI_RSP/UART0B_CTS#
GPP_J8/CNV_MFUART2_RXD
GPP_J9/CNV_MFUART2_TXD

CNP-H_BG A874

@

Compal Secret Data

Compal Secret Data

Compal Secret Data

CNP-H

CLKOUT_ITPXDP#

CLKOUT_ITPXDP_P

CLKOUT_CPUPCIBCLK#

CLKOUT_CPUPCIBCLK_P

CLKOUT_PCIE_N0
CLKOUT_PCIE_P0

CLKOUT_PCIE_N1
CLKOUT_PCIE_P1

CLKOUT_PCIE_N2
CLKOUT_PCIE_P2

CLKOUT_PCIE_N3
CLKOUT_PCIE_P3

CLKOUT_PCIE_N4
CLKOUT_PCIE_P4

CLKOUT_PCIE_N5
CLKOUT_PCIE_P5

CLKOUT_PCIE_N6
CLKOUT_PCIE_P6

CLKOUT_PCIE_N7
CLKOUT_PCIE_P7

CLKOUT_PCIE_N8
CLKOUT_PCIE_P8

CLKOUT_PCIE_N9
CLKOUT_PCIE_P9

CLKOUT_PCIE_N10
CLKOUT_PCIE_P10

CLKOUT_PCIE_N11
CLKOUT_PCIE_P11

7 OF 13

CNP-H

3.3V

1.8V

13 OF 13

Deciphered Date

Deciphered Date

Deciphered Date

Y3
Y4

B6
A6

AJ6
AJ7

AH9
AH10

AE14
AE15

AE6
AE7

AC2
AC3

AB2
AB3

W4
W3

W7
W6

AC14
AC15

U2
U3

AC9
AC11

AE9
AE11

CLKIN_XTAL

GPPJ_RCOMP_1P81
GPPJ_RCOMP_1P82
GPPJ_RCOMP_1P83

R6

Rev1.0

CNV_WR_CLKN
CNV_WR_CLKP

CNV_WR_D0N
CNV_WR_D0P
CNV_WR_D1N
CNV_WR_D1P

CNV_WT_CLKN
CNV_WT_CLKP

CNV_WT_D0N
CNV_WT_D0P
CNV_WT_D1N
CNV_WT_D1P

CNV_WT_RCOMP

PCIE_RCOMPN

PCIE_RCOMPP
SD_1P8_RCOMP
SD_3P3_RCOMP

RSVD2
RSVD3

RSVD1

TP

Rev1.0

12

CLK_CNV _PRX_DTX_N

BD4

CLK_CNV _PRX_DTX_P

BE3

CNV_PRX _DTX_N0

BB3

CNV_PRX _DTX_P0

BB4

CNV_PRX _DTX_N1

BA3

CNV_PRX _DTX_P1

BA2

CLK_CNV _PTX_DRX_N

BC5

CLK_CNV _PTX_DRX_P

BB6

CNV_PTX _DRX_N0

BE6

CNV_PTX _DRX_P0

BD7

CNV_PTX _DRX_N1

BG6

CNV_PTX _DRX_P1

BF6

CNV_W T_RCOMP

BA1

PCIE_RCOM PN

B12

PCIE_RCOM PP

A13

SD_RCOM P_1P8

BE5

SD_RCOM P_3P3

BE4
BD1
BE1
BE2

Y35
Y36

BC1
AL35

D

TH2@
TH3@

CLK_PEG_VGA# <27>
CLK_PEG_VGA <27>

RH14

10K_040 2_5%

RH16

1 2

1 2

RH17 100 _0402_1%

1 2

RH18 200 _0402_1%

1 2

GPPJ_RC OMP_1P8

RH19 200 _0402_1%

1 2

RH20 200 _0402_1%

#571483_CFL_H_RVP_CRB_TDK_Rev0p5
Recommend external test point

TH4@

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

Date : Sheet o f

Date : Sheet o f

Date : Sheet o f

PCH_CPU _PCIBCLK_N <10>

DGPU

CLK_PCIE_ LAN# <51>

CLK_PCIE_ LAN <51>

CLK_PCIE_ WLAN# <5 2>

CLK_PCIE_ WLAN <52 >

CLK_PCIE_ NGFF1# <68>
CLK_PCIE_ NGFF1 < 68>

CLK_PCIE_ NGFF2# <68>
CLK_PCIE_ NGFF2 < 68>

REFCLK_ CNV <52>

150_040 2_1%

GLAN

NGFF WL+BT(KEY E)

M2 SSD1

M2 SSD2

CLK_CNV _PRX_DTX_N <52>
CLK_CNV _PRX_DTX_P <52>

CNV_PRX _DTX_N0 <52>
CNV_PRX _DTX_P0 <52>
CNV_PRX _DTX_N1 <52>
CNV_PRX _DTX_P1 <52>

CLK_CNV _PTX_DRX_N <52>
CLK_CNV _PTX_DRX_P <52>

CNV_PTX _DRX_N0 <52>

CNV_PTX _DRX_P0 <52>

CNV_PTX _DRX_N1 <52>

CNV_PTX _DRX_P1 <52>

checked CRB

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

PCH(2/8)CLK/CNVI/SD

PCH(2/8)CLK/CNVI/SD

PCH(2/8)CLK/CNVI/SD

EH5VF M/B LA-H501P

EH5VF M/B LA-H501P

EH5VF M/B LA-H501P

E

1A

1A

1A

15 1 01Friday, February 22, 2019

15 1 01Friday, February 22, 2019

15 1 01Friday, February 22, 2019

A

UH1E

no follow naming

can remove if no use DP
08/1 8

remove PCH DP SCLK/SDATA

DDP[B..F]CTRLDATA
This signal has a weak internal Pull-down.
0 = Port B~D is not detected.
1 = Port B,C,D is detected. (Default)
Notes:

1. The internal Pull-down is disabled after
PCH_PWROK de-asserts.

2. This signal is in the primary well.

HDMI_HPD_ PCH<2 7,40>

EDP_HPD<38>

EC_PME#<51,58>

1 2

RH24 0_0 402_5%

EC_PME# _R

@

CRB connect GND

1 2

RH186 0_0402 _5%@

PCH_SPI_S I_R<66>

PCH_SPI_S O_R<66>

PCH_SPI_C LK_R<66>

* wait confirm CG7
PDG P348 quad mode support PH1K

+3VALW

1 1

+3VALW

CRB PU 20k
#571182_CFL_PCH _EDS_Rev1.0 rec ommend 100k

#571391_CFL_H_PDG_Rev0p71

RH25 1K_0402 _5%

RH26 1K_0402 _5%

RH27 1K_0402 _5%

RH29 100 K_0402_5%

#571182_CNL_PCH_H_EDS_V1_Rev0.7
External pull-up is required. Recommend 100K if pulled
up to 3.3V or 75K if pulled up to 1.8V.
571007_CFL_MOW_Archive_WW22_2017
STUFF R on GPP_H15

PCH_SPI_C LK_R

12

12

12

12

RH195 100K_0 201_5%@

1 2

PCH_SPI_IO2

PCH_SPI_IO3

PCH_SPI_S I_R

GPP_H15

STRAP

RH258 0_04 02_5%NTPM@

1 2

RH259 0_04 02_5%NTPM@

1 2

RH260 0_04 02_5%NTPM@

PCH_SPI_C S#2<6 6>

RH258

TPM@

4.99_040 2_1%

SD034499B80

TH6 @

1 2

PCH_SPI_S I
PCH_SPI_S O
PCH_SPI_C S#0
PCH_SPI_C LK

PCH_SPI_IO2
PCH_SPI_IO3

RH259

TPM@

4.99_040 2_1%

SD034499B80

AT6

AN10

AP9

AL15

AN6

CNP-H_BG A874

@

BE36

R15
R13

AL37

AN35

AU41
BA45

AY47
AW47
AW48

AY48

BA46

AT40

BE19

BF19

BF18
BE18
BC17
BD17

CNP-H_BG A874

@

RH260

TPM@

4.99_040 2_1%

SD034499B80

GPP_I0/DDPB_HPD0/DISP_MISC0
GPP_I1/DDPC_HPD1/DISP_MISC1
GPP_I2/DDPD_HPD2/DISP_MISC2
GPP_I3/DDPF_HPD3/DISP_MISC3

GPP_I4/EDP_HPD/DISP_MISC4

UH1A

GPP_A11/PME#/SD_VDD2_PWR_EN#

RSVD2
RSVD1

VSS
TP

SPI0_MOSI
SPI0_MISO
SPI0_CS0#
SPI0_CLK
SPI0_CS1#

SPI0_IO2
SPI0_IO3
SPI0_CS2#

GPP_D1/SPI1_CLK/SBK1_BK1
GPP_D0/SPI1_CS#/SBK0_BK0
GPP_D3/SPI1_MOSI/SBK3_BK3
GPP_D2/SPI1_MISO/SBK2_BK2
GPP_D22/SPI1_IO3
GPP_D21/SPI1_IO2

CNP-H

5 OF 13

CNP-H

GPP_K15/GSXSRESET#

GPP_H18/SML4ALERT#

GPP_H15/SML3ALERT#

GPP_H12/SML2ALERT#

1 OF 13

GPP_I5/DDPB_CTRLCLK

GPP_I6/DDPB_CTRLDATA

GPP_I7/DDPC_CTRLCLK

GPP_I8/DDPC_CTRLDATA

GPP_I9/DDPD_CTRLCLK

GPP_I10/DDPD_CTRLDATA

GPP_F23/DDPF_CTRLDATA

GPP_F22/DDPF_CTRLCLK

GPP_F14/PS_ON#

GPP_K23/IMGCLKOUT1
GPP_K22/IMGCLKOUT0

GPP_H23/TIME_SYNC0

GPP_B13/PLTRST#

GPP_K16/GSXCLK

GPP_K12/GSXDOUT

GPP_K13/GSXSLOAD

GPP_K14/GSXDIN

GPP_E3/CPU_GP0
GPP_E7/CPU_GP1
GPP_B3/CPU_GP2
GPP_B4/CPU_GP3

GPP_H17/SML4DATA

GPP_H16/SML4CLK

GPP_H14/SML3DATA

GPP_H13/SML3CLK

GPP_H11/SML2DATA

GPP_H10/SML2CLK

INTRUDER#

Rev1.0

GPP_K21
GPP_K20

AL13
AR8
AN13
AL10
AL9
AR3
AN40
AT49

AP41

M45
L48
T45
T46
AJ47

Rev1.0

AV29

Y47
Y46
Y48
W46
AA45

AL47
AM45
BF32
BC33

AE44
AJ46
AE43
AC47
AD48
AF47
AB47
AD47
AE48

BB44

remove CIO_PLUG_EVENT#

PLT_RST #

TP_INT#

GPP_H15

GPP_H12

SM_INTRUD ER#

RVP: 330K
A 1 M pull-up is used on the customer reference
board (CRB). This is needed to reduce leakage
from Coin Cell Battery in G3 state.

PLT_RST # <27,58,6 6>

GPIO Serial Expander (GSX) is the capability
provided by the PCH to expand the GPIOs
on a platform that needs more GPIOs than the
ones provided by the PCH.

12

DH1
RB751V-4 0_SOD323-2

GPP_H12 <19>

EC_TP_INT# < 58,63>

+RTCVCC

12

RH301M_0402 _5%

intel critical net recommend

1 2

RH198 100K_0 201_5%

PLT_RST #

1 2

CH9 100P_0402_5 0V8J

XESD@

TP_INT#

RH28 100 K_0402_5%

+3VS

12

intel critical net recommend

SPI ROM ( 16MByte )

PCH_SPI_C S#0

PCH_SPI_IO2_ 0_R

UH2

1
2
3
4

W25 Q128FVSIQ_SO8

XMC P/N: SA0000B8400

PCH_SPI_C LK_0_R

/CS
DO(IO1)
/WP(IO2)
GND

XEMI@

1 2

RH33
0_0402_ 5%

VCC

/HOLD(IO3)

CLK

DI(IO0)

+3VALW

CH10 0.1U_ 0201_10V6K

8

PCH_SPI_IO3_ 0_RPCH_SPI_S O_0_R

7

PCH_SPI_C LK_0_R

6

PCH_SPI_S I_0_R

5

XEMI@

1 2

CH12
68P_040 2_50V8J

1 2

PCH_SPI_S I_0_R
PCH_SPI_S O_0_R
PCH_SPI_IO3_ 0_R
PCH_SPI_C LK_0_R

PCH_SPI_C S#0

RH107 33_0 402_1%
RH108 33_0 402_1%
RH109 33_0 402_1%
RH110 33_0 402_1%
RH111 33_0 402_1%

PCH PLTRST Buffer

+3VALW +3VS

1 2

@

RH31 4.7K_ 0402_5%

PLT_RST #

1 2
1 2
1 2
1 2
1 2

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PCH_SPI_S I_R
PCH_SPI_S O_R
PCH_SPI_IO3
PCH_SPI_C LK_R
PCH_SPI_IO2PCH_SPI_IO2_ 0_R

Compal Secret Data

Compal Secret Data

2017/10/ 30 2018/10/ 30

2017/10/ 30 2018/10/ 30

2017/10/ 30 2018/10/ 30

A

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

1 2

RH32 0_0 402_5%@

CH11

0.1U_020 1_10V6K

1 2

5

1

2

MC74VHC 1G08DFT2G_SC 70-5

UH3

IN1

VCC

4

OUT

IN2

GND

3

12

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

PCH(3/8)DDC/SPI

PCH(3/8)DDC/SPI

PCH(3/8)DDC/SPI

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

Date : Sheet o f

Date : Sheet o f

Date : Sheet o f

PLT_RST _BUF# <51,5 2,68>

RH199
100K_02 01_5%

@

EH5VF M/B LA-H501P

EH5VF M/B LA-H501P

EH5VF M/B LA-H501P

16 1 01Friday, February 22, 2019

16 1 01Friday, February 22, 2019

16 1 01Friday, February 22, 2019

1A

1A

1A

A

USB3 MB

1 1

USB3 Type C

USB3 MB

2 2

For Intel CLINK

M.2 SSD PCIE L1

3 3

GLAN

PCIE_PTX_ C_DRX_N14<51>

PCIE_PTX_ C_DRX_P14<51>

PCIE_PRX_DTX_N14<51>
PCIE_PRX_DTX_P14<51>

CH3 .1U_0402_16V7K
CH4 .1U_0402_16V7K

M.2 SSD PCIE L0

+3VALW

12

RH43

10K_040 2_5%

4 4

UMA@

DGPU_PR SNT#

12
12

TH10 @
TH11 @
TH12 @

PCIE_PTX_ DRX_P11<68>
PCIE_PTX_ DRX_N11<68>
PCIE_PRX_ DTX_P11<68>
PCIE_PRX_ DTX_N11<68>

PCIE_PTX_ DRX_P12<68>

PCIE_PTX_ DRX_N12<68>
PCIE_PRX_ DTX_P12<68>
PCIE_PRX_ DTX_N12<68>

USB3_PT X_DRX_N1<71>
USB3_PT X_DRX_P1<71>
USB3_PR X_DTX_N1<71>
USB3_PR X_DTX_P1<71>

USB3_PT X_DRX_N2<42>
USB3_PT X_DRX_P2<42>
USB3_PR X_DTX_N2<42>
USB3_PR X_DTX_P2<42>

USB3_PT X_DRX_P3<72>
USB3_PT X_DRX_N3<72>
USB3_PR X_DTX_P3<72>
USB3_PR X_DTX_N3<72>

DGPU_PR SNT#

PCIE_PTX_ DRX_N14
PCIE_PTX_ DRX_P14

PCIE_PRX_ DTX_N14
PCIE_PRX_ DTX_P14

B

CL_CLK
CL_DATA
CL_RST#

UH1F

F9

USB31_1_TXN

F7

USB31_1_TXP

D11

USB31_1_RXN

C11

USB31_1_RXP

C3

USB31_2_TXN

D4

USB31_2_TXP

B9

USB31_2_RXN

C9

USB31_2_RXP

C17

USB31_6_TXN

C16

USB31_6_TXP

G14

USB31_6_RXN

F14

USB31_6_RXP

C15

USB31_5_TXN

B15

USB31_5_TXP

J13

USB31_5_RXN

K13

USB31_5_RXP

G12

USB31_3_TXP

F11

USB31_3_TXN

C10

USB31_3_RXP

B10

USB31_3_RXN

C14

USB31_4_TXP

B14

USB31_4_TXN

J15

USB31_4_RXP

K16

USB31_4_RXN

CNP-H_BG A874

@

UH1C

AR2

CL_CLK

AT5

CL_DATA

AU4

CL_RST#

P48

GPP_K8

V47

GPP_K9

V48

GPP_K10

W47

GPP_K11

L47

GPP_K0

L46

GPP_K1

U48

GPP_K2

U47

GPP_K3

N48

GPP_K4

N47

GPP_K5

P47

GPP_K6

R46

GPP_K7

C36

PCIE11_TXP/SATA0A_TXP

B36

PCIE11_TXN/SATA0A_TXN

F39

PCIE11_RXP/SATA0A_RXP

G38

PCIE11_RXN/SATA0A_RXN

AR42

GPP_F10/SATA_SCLOCK

AR48

GPP_F11/SATA_SLOAD

AU47

GPP_F13/SATA_SDATAOUT0

AU46

GPP_F12/SATA_SDATAOUT1

C39

PCIE14_TXN/SATA1B_TXN

D39

PCIE14_TXP/SATA1B_TXP

D46

PCIE14_RXN/SATA1B_RXN

C47

PCIE14_RXP/SATA1B_RXP

B38

PCIE13_TXN/SATA0B_TXN

C38

PCIE13_TXP/SATA0B_TXP

C45

PCIE13_RXN/SATA0B_RXN

C46

PCIE13_RXP/SATA0B_RXP

E37

PCIE12_TXP/SATA1A_TXP

D38

PCIE12_TXN/SATA1A_TXN

J41

PCIE12_RXP/SATA_1A_RXP

H42

PCIE12_RXN/SATA1A_RXN

B44

PCIE20_TXP/SATA7_TXP

A44

PCIE20_TXN/SATA7_TXN

R37

PCIE20_RXP/SATA7_RXP

R35

PCIE20_RXN/SATA7_RXN

D43

PCIE19_TXP/SATA6_TXP

C44

PCIE19_TXN/SATA6_TXN

N42

PCIE19_RXP/SATA6_RXP

M44

PCIE19_RXN/SATA6_RXN

CNP-H_BG A874

@

C

CNP-H

GPP_A1/LAD0/ESPI_IO0

1.8V

GPP_A2/LAD1/ESPI_IO1

(eSPI)

GPP_A3/LAD2/ESPI_IO2
GPP_A4/LAD3/ESPI_IO3

GPP_A5/LFRAME#/ESPI_CS0#

GPP_A6/SERIRQ/ESPI_CS1#

GPP_A7/PIRQA#/ESPI_ALERT0#

GPP_A0/RCIN#/ESPI_ALERT1#

GPP_A14/SUS_STAT#/ESPI_RESET#

GPP_A9/CLKOUT_LPC0/ESPI_CLK

GPP_A10/CLKOUT_LPC1

GPP_K19/SMI#

GPP_K18/NMI#

GPP_E6/SATA_DEVSLP2
GPP_E5/SATA_DEVSLP1
GPP_E4/SATA_DEVSLP0

GPP_F9/SATA_DEVSLP7
GPP_F8/SATA_DEVSLP6
GPP_F7/SATA_DEVSLP5
GPP_F6/SATA_DEVSLP4
GPP_F5/SATA_DEVSLP3

6 OF 13

CNP-H

PCIE9_RXN
PCIE9_RXP

PCIE9_TXN
PCIE9_TXP

PCIE10_RXN
PCIE10_RXP
PCIE10_TXN
PCIE10_TXP

PCIE15_RXN/SATA2_RXN

PCIE15_RXP/SATA2_RXP

PCIE_15_SATA_2_TXN

PCIE15_TXP/SATA2_TXP

PCIE16_RXN/SATA3_RXN

PCIE16_RXP/SATA3_RXP

PCIE16_TXN/SATA3_TXN
PCIE16_TXP/SATA3_TXP

PCIE17_RXN/SATA4_RXN

PCIE17_RXP/SATA4_RXP
PCIE17_TXN/SATA4_TXN

PCIE17_TXP/SATA4_TXP

PCIE18_RXN/SATA5_RXN

PCIE18_RXP/SATA5_RXP

PCIE18_TXN/SATA5_TXN
PCIE18_TXP/SATA5_TXP

GPP_E8/SATA_LED#

GPP_E0/SATAXPCIE0/SATAGP0
GPP_E1/SATAXPCIE1/SATAGP1
GPP_E2/SATAXPCIE2/SATAGP2

GPP_F0/SATAXPCIE3/SATAGP_3

GPP_F1/SATAXPCIE4/SATAGP4
GPP_F2/SATAXPCIE5/SATAGP5
GPP_F3/SATAXPCIE6/SATAGP6
GPP_F4/SATAXPCIE7/SATAGP7

GPP_F21/EDP_BKLTCTL

GPP_F20/EDP_BKLTEN

GPP_F19/EDP_VDDEN

THRMTRIP#

PECI

PM_SYNC

3 OF 13

PLTRST_CPU#

PM_DOWN

Rev1.0

Rev1.0

BB39
AW37
AV37
BA38

BE38
AW35
BA36
BE39
BF38

BB36
BB34

T48
T47

AH40
AH35
AL48
AP47
AN37
AN46
AR47
AP48

G36
F36
C34
D34

K37
J37
C35
B35

F44
E45
B40
C40

L41
M40
B41
C41

K43
K44
A42
B42

P41
R40
C42
D42

AK48

AH41
AJ43
AK47
AN47

RH187 10K_0402_ 5%PBA@

AM46
AM43
AM47
AM48

AU48
AV46
AV44

AD3
AF2
AF3
AG5
AE2

#571391_CFL_H_PDG_Rev0p5

‧‧‧‧
‧‧‧‧
‧‧‧‧

* If DATA signals are entirely routed on MS, stuff the resistor with 15 Ohm.

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

LPC_FRA ME#
TPM_SER IRQ
LPC_PIRQA #

RCIN#
ESPI_RST#

CLK_LPC

SSD_DEV SLP1

PCIE_PRX_ DTX_N9
PCIE_PRX_ DTX_P9
PCIE_PTX_ DRX_N9
PCIE_PTX_ DRX_P9

PCIE_PRX_ DTX_N10
PCIE_PRX_ DTX_P10
PCIE_PTX_ DRX_N10
PCIE_PTX_ DRX_P10

PCIE_PRX_ DTX_N15
PCIE_PRX_ DTX_P15
PCIE_PTX_ DRX_N15
PCIE_PTX_ DRX_P15

SATA_PR X_DTX_N4
SATA_PR X_DTX_P4
SATA_PT X_DRX_N4
SATA_PT X_DRX_P4

1 2

SATA_GP 5

PCH_BKL _PWM
ENBKL

PCH_ENV DD

PCH_THE RMTRIP#
PCH_PEC I

H_PM_SYNC
H_PLTRS T_CPU#
H_PM_DO WN_R

D

eSPI clock and eSPI data mismatched: <500 mils.
eSPI clock and eSPI chip select mismatched: <500 mils.
eSPI signal maximum 9 Vias

LPC_AD0 <58>
LPC_AD1 <58>
LPC_AD2 <58>
LPC_AD3 <58>

LPC_FRA ME# <58 >
TPM_SER IRQ <58,66 >

1 2

RH261 0_04 02_5%@

RH35 22_ 0402_5%

12

SSD_DEV SLP1 <6 8>

LPC Bus

LPC : +3.3V

OVRM_EN <36,58>

CLK_LPC _R < 58>

CONFIRM WITH SW

PCIE_PRX_ DTX_N9 <68>
PCIE_PRX_ DTX_P9 <68>
PCIE_PTX_ DRX_N9 <6 8>

PCIE_PTX_ DRX_P9 <68>

PCIE_PRX_ DTX_N10 <68 >
PCIE_PRX_ DTX_P10 <68>
PCIE_PTX_ DRX_N10 < 68>

PCIE_PTX_ DRX_P10 <68>

PCIE_PRX_DTX_N15 <52>

1 2

CH1.1U_0402 _16V7K

1 2

CH2.1U_0402 _16V7K

SATA_PR X_DTX_N4 < 67>
SATA_PR X_DTX_P4 <67>
SATA_PT X_DRX_N4 < 67>

SATA_PT X_DRX_P4 <67>

SATA_GP 1 <68>

PCIE_PRX_DTX_P15 <52>
PCIE_PTX_ C_DRX_N15 <52>

PCIE_PTX_ C_DRX_P15 <52>

SATA_GP 1

M.2 SSD PCIE/SATA select pin

TH13@

CONFIRM WITH SW

PCH_BKL _PWM < 38>
ENBKL <58>
PCH_ENV DD <38>

1 2

RH40 620_0 402_5%

1 2

RH41 13_04 02_5%@

1 2

RH42 30_ 0402_5%

#571391_CFL_H_PDG_Rev0p5.pdf

H_PECI
H_PM_SYNC _R

check straps

TPM_SER IRQ

LPC_PIRQA #

M.2 SSD PCIE L3

M.2 SSD PCIE L2

HDD

RH39 10K_ 0402_5%

PCH_THE RMTRIP#_R <10 >
H_PECI <10,58>
H_PM_SYNC _R <10>
H_PLTRS T_CPU# <10>
H_PM_DO WN_R <10>

H_PECI

E

RCIN#

10K_040 2_5%

10K_040 2_5%

1 2

10K_040 2_5%

NGFF
WL+BT(KEY E)

+3VS

12

XESD@

1 2

+3VS

12

RH219

+3VS

12

RH37

RH38

CH500.1U_020 1_10V6K

RH44

10K_040 2_5%

12

VGA@

DIS,Optimus10

UMA

A

GPP_F13

DGPU_PRSNT#

Security Classification

Security Classification

Security Classification

2017/10/ 30 2018/10/ 30

2017/10/ 30 2018/10/ 30

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

2017/10/ 30 2018/10/ 30

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

PCIE/SATA/USB3/eSPI

PCIE/SATA/USB3/eSPI

PCIE/SATA/USB3/eSPI

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

EH5VF M/B LA-H501P

EH5VF M/B LA-H501P

EH5VF M/B LA-H501P

Date : Sheet o f

Date : Sheet o f

D

Date : Sheet o f

17 1 01Friday, February 22, 2019

17 1 01Friday, February 22, 2019

17 1 01Friday, February 22, 2019

E

1A

1A

1A

A

1 2

ME_EN<58>

1 2

HDA_RST #_R<56>
HDA_BIT_C LK_R<5 6>
HDA_SDO UT_R<56>
HDA_SYNC_ R<56>

1 1

RH208 33_0 402_5%

1 2

RH209 33_0 402_5%

1 2

RH210 33_0 402_5%

1 2

RH211 33_0 402_5%

12

RH196100K _0201_5%

12

RH197100K _0201_5%

@

RH45 0_0 402_5%

HDA_BIT_C LK
HDA_RST #

HDA_RST #
HDA_BIT_C LK
HDA_SDO UT
HDA_SYNC

intel critical net recommend

del RF reserve cap on HDA

CPU_DISPA _SDO_R< 6>

CPU_DISPA _SDI_R<6>

FOR Jefferson Peak RESET pin is glitch free,it
is recommended that a pull-down resistor of 75K
ohm on GPP_D5(CNV_RF_RESET#)

+RTCVCC

1 2

RH50 20K_ 0402_1%

1 2

2 2

3 3

+3VS

+3VALW

4 4

CH18 1U_0201_6.3 V6M

1 2

RH52 20K_ 0402_1%

1 2

CH19 1U_0201_6.3 V6M

1 2

JCMOS1 0_06 03_5%@

+3VALW _DSW

RH55 1K_0 402_5%

RH56 8.2K_ 0402_5%

1 2

RH57 100 K_0402_5%@

1 2

RH58 100 K_0402_5%@

RH60 8.2K_ 0402_5%

RH191 2.2K_ 0402_5%
RH192 2.2K_ 0402_5%

RH251 2.2K_ 0402_5%
RH252 2.2K_ 0402_5%
RH253 2.2K_ 0402_5%
RH254 2.2K_ 0402_5%

1 2

RH63 499_040 2_1%

1 2

RH64 499_040 2_1%

12

12

12

12
12

12
12
12
12

PCH_SML 0CLK

PCH_SML 0DATA

A

CPU_DISPA _BCLK_R<6>

PCH_SRT CRST#

CLR ME
Delay 18~25 ms

PCH_RTC RST#

ECLR CMOS
Delay 18~25 ms

WAKE #

PM_BATL OW#

AC_PRES ENT_R

PBTN_OU T#_R

PM_CLKR UN#

D_CK_SC LK
D_CK_SD ATA

PCH_SMB CLK
PCH_SMB DATA

2N7002K DW_SOT36 3-6

PCH_SMB CLK

PCH_SML 1CLK <2 7,58,66>
PCH_SML 1DATA <27 ,58,66>

B

HDA_SDIN0<56>

RH48

1 2

RH49

1 2

CLKREQ_ CNV#<5 2>
CNV_RF_ RESET#< 52>
PCH_DMIC_ DATA0<56>
PCH_DMIC_ CLK0<56>

TH22 @
TH24 @

PCH_RTC RST#<58>

PCH_PW ROK<58,78>
EC_RSMR ST#<58>

PCH_SMB ALERT#<19>

PCH_SML 0ALERT#<19>

PCH_SML 1ALERT#<19>

QH7B

3 4

2N7002K DW_SOT36 3-6

B

HDA_BIT_C LK
HDA_SDIN0
HDA_SDO UT
HDA_SYNC

HDA_RST #

S

2

G

6 1

D

CPU_DISPA _SDO
CPU_DISPA _SDI_R
CPU_DISPA _BCLK

CLKREQ_ CNV#
CNV_RF_ RESET#

PCH_RTC RST#
PCH_SRT CRST#

PCH_PW ROK
EC_RSMR ST#

PCH_DPW ROK
PCH_SMB ALERT#
PCH_SMB CLK
PCH_SMB DATA
PCH_SML 0ALERT#
PCH_SML 0CLK
PCH_SML 0DATA
PCH_SML 1ALERT#
PCH_SML 1CLK
PCH_SML 1DATA

D_CK_SC LK

D_CK_SD ATAPCH_SMB DATA

S

+3VS

D

5

G

QH7A

30_0402 _5%

30_0402 _5%

(EC,VGA,Thermal Sensor)

Security Classification

Security Classification

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

UH1D

BD11

HDA_BCLK/I2S0_SCLK

BE11

HDA_SDI0/I2S0_RXD

BF12

HDA_SDO/I2S0_TXD

BG13

HDA_SYNC/I2S0_SFRM

BE10

HDA_RST#/I2S1_SCLK

BF10

HDA_SDI1/I2S1_RXD

BE12

I2S1_TXD/SNDW2_DATA

BD12

I2S1_SFRM/SNDW2_CLK

AM2

HDACPU_SDO

AN3

HDACPU_SDI

AM3

HDACPU_SCLK

AV18

GPP_D8/I2S2_SCLK

AW18

GPP_D7/I2S2_RXD

BA17

GPP_D6/I2S2_TXD/MODEM_CLKREQ

BE16

GPP_D5/I2S2_SFRM/CNV_RF_RESET#

BF15

GPP_D20/DMIC_DATA0/SNDW4_DATA

BD16

GPP_D19/DMIC_CLK0/SNDW4_CLK

AV16

GPP_D18/DMIC_DATA1/SNDW3_DATA

AW15

GPP_D17/DMIC_CLK1/SNDW3_CLK

BE47

RTCRST#

BD46

SRTCRST#

AY42

PCH_PWROK

BA47

RSMRST#

AW41

DSW_PWROK

BE25

GPP_C2/SMBALERT#

BE26

GPP_C0/SMBCLK

BF26

GPP_C1/SMBDATA

BF24

GPP_C5/SML0ALERT#

BF25

GPP_C3/SML0CLK

BE24

GPP_C4/SML0DATA

BD33

GPP_B23/SML1ALERT#/PCHHOT#

BF27

GPP_C6/SML1CLK

BE27

GPP_C7/SML1DATA

CNP-H_BG A874

@

(DDR,G- Sens or)

D_CK_SC LK < 23,24>

D_CK_SD ATA <23 ,24>

Issued Date

Issued Date

Issued Date

C

CNP-H

GPP_A12/BM_BUSY#/ISH_GP6/SX_EXIT_HOLDOFF#

GPP_B1/GSPI1_CS1#/TIME_SYNC1

1.8V

GPP_A13/SUSWARN#/SUSPWRDNACK

4 OF 13

Compal Secret Data

Compal Secret Data

2017/10/ 30 2018/10/ 30

2017/10/ 30 2018/10/ 30

2017/10/ 30 2018/10/ 30

C

Compal Secret Data

GPP_A8/CLKRUN#

GPD11/LANPHYPC

GPD9/SLP_WLAN#

DRAM_RESET#

GPP_B2/VRALERT#

GPP_B0/GSPI0_CS1#

GPP_K17/ADR_COMPLETE

GPP_B11/I2S_MCLK

SYS_PWROK

GPD6/SLP_A#

GPP_B12/SLP_S0#

GPD4/SLP_S3#
GPD5/SLP_S4#

GPD10/SLP_S5#

GPD8/SUSCLK

GPD0/BATLOW#

GPP_A15/SUSACK#

GPD2/LAN_WAKE#
GPD1/ACPRESENT

GPD3/PWRBTN#

SYS_RESET#

GPP_B14/SPKR

CPUPWRGD

ITP_PMODE

PCH_JTAGX
PCH_JTAG_TMS
PCH_JTAG_TDO

PCH_JTAG_TDI

PCH_JTAG_TCK

+3VALW

RH183 10K_ 0402_5%

Deciphered Date

Deciphered Date

Deciphered Date

BF36
AV32

BF41

BD42

BB46
BE32
BF33
BE29
R47
AP29
AU3

BB47

WAKE#

BE40
BF40

SLP_LAN#

BC28
BF42
BE42
BC42

BE45
BF44
BE35
BC37

BG44
BG42
BD39

SLP_SUS#

BE46
AU2
AW29
AE3

AL3
AH4
AJ4
AH3
AH2
AJ3

Rev1.0

12

1 2

RH184100K_04 02_5% @

1 2

RH61100K_ 0402_5% @

XESD@

1 2

CH200.1U_020 1_10V6K

XESD@

1 2

CH210.1U_020 1_10V6K

XESD@

1 2

CH220.1U_020 1_10V6K

XESD@

1 2

CH51100P_ 0402_50V8J

From ESD Team Request

Near PCH side

D

DRAM_RE SET#

PM_CLKR UN#

LAN_DISAB LE_N

SLP_W LAN#

DRAM_RE SET#
PCH_VRA LERT#
TYPEC_3A
LAN_GPO
PCH_GPP _K17
PCH_GPP _B11
SYS_PW ROK

WAKE #
PM_SLP_ A#

SLP_LAN #
PM_SLP_ S0#
PM_SLP_ S3#
PM_SLP_ S4#
PM_SLP_ S5#

SUSCLK
PM_BATL OW#

SUSACK# _R

1 2

RH51 0_0 402_5%

LAN_W AKE#
AC_PRES ENT_R
SLP_SUS #
PBTN_OU T#_R
SYS_RESET #
PCH_SPK R
H_CPUPW RGD

XDP_ITP_P MODE
CPU_XDP _TCK0
CPU_XDP _TMS
CPU_XDP _TDO
CPU_XDP _TDI
PCH_JTA G_TCK1

SYS_RESET #

SYS_PW ROK

PCH_DPW ROK

SYS_RESET #

SYS_PW ROK

PCH_PW ROK

EC_RSMR ST#

D

1 2
1 2

AC_PRES ENT <58 >

PBTN_OU T# < 58>

E

DDR_DRA MRST#_R < 23,24>

Connect CPU & PCH

+1.2V_VD DQ

RH46
470_040 2_1%

1 2

1 2

@

RH47 0_0402_ 5%

12

CH13 0.1U_02 01_10V6K

@

TH14@

TH15@

TYPEC_3A <43>
LAN_GPO <51>

TH19@
TH20@

SYS_PW ROK <58,78>

TH37@
TH21@
TH38@

PM_SLP_ S3# <58 ,78>
PM_SLP_ S4# <58 ,78>

TH23@

@

T207@

SUSPW RDNACK <5 8>

1 2

RH53 0_0 402_5%@

T208

@

1 2

RH54

PCH_SPK R <1 9,56>

H_CPUPW RGD <10 >

T209

@

CPU_XDP _TCK0 <10 >

CPU_XDP _TMS <10>
CPU_XDP _TDO <10>

CPU_XDP _TDI <10 >

PCH_JTA G_TCK1 <10>

PM_SLP_ S3#
PM_SLP_ S4#

SUSCLK <52,68>

--No Support Deep Sx

0_0402_ 5%@

RH193 100K_0 201_5%
RH194 100K_0 201_5%

intel critical net recommend

12

E

PCH_DPW ROK

+3VALW _DSW

+3VALW

18 1 01Friday, February 22, 2019

18 1 01Friday, February 22, 2019

18 1 01Friday, February 22, 2019

1A

1A

1A

EC_RSMR ST#

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

Date : Sheet o f

Date : Sheet o f

Date : Sheet o f

1 2

@

RH59 0_0 402_5%

LAN_W AKE#
PCH_PW ROK
EC_RSMR ST#

PCH_VRA LERT#

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

PCH(5/8)PMU/HDA/SMBUS/DMIC

PCH(5/8)PMU/HDA/SMBUS/DMIC

PCH(5/8)PMU/HDA/SMBUS/DMIC

EH5VF M/B LA-H501P

EH5VF M/B LA-H501P

EH5VF M/B LA-H501P

1 2

RH212 10K_ 0402_5%

1 2

RH213 10K_ 0402_5%

1 2

RH214 10K_ 0402_5%

RH62 10K_ 0402_5%@

A

+3VALW

1 2

RH215 2.2K_ 0402_5%

1 2

RH216 2.2K_ 0402_5%

1 2

RH217 2.2K_ 0402_5%

1 2

RH218 2.2K_ 0402_5%

+3VS

RH66 10K_0402 _5%@

1 1

2 2

3 3

4 4

RH68 49.9K_04 02_1%

RH69 49.9K_04 02_1%

RH70 49.9K_04 02_1%@

RH71 49.9K_04 02_1%@

RH72 10K_0402 _5%VGA@

RH73 10K_0402 _5%VGA@

+3VALW

RH74 4.7K_ 0402_5%@

This signal has a weak internal pull-down.
0 = Master Attached Flash Sharing (MAFS) enabled (Default)
1 = Slave Attached Flash Sharing (SAFS) enabled.
Notes:

1. This signal is in the primary well.

Warning: This strap must be configured to ‘ 0’ if the
eSPI or LPC strap is configured to ‘ 0’

+3VALW

+3VS

12

12

12

12

12

1 2

1 2

1 2

1 2

RH112 4.7K_04 02_5%@

SMBALERT# / GPP_C2 has a weak internal Pull-down.
0 = Disable Intel ME (TLS) (Default)
1 = Enable Intel ME (TLS)

1 2

RH113 4.7K_04 02_5%@

SML0ALERT# / GPP_C5 has a weak internal Pull-down.
0 = LPC is selected (for EC 9022).
1 = eSPI is selected

1 2

RH114 15 0K_0402_1%

SML1ALERT# / GPP_B23 has an internal pull-down.
0 = Disable IntelR DCI-OOB (Default)
1 = Enable IntelR DCI-OOB

*

1 2

RH77 4.7K_ 0402_5%@

The signal has a weak internal Pull-down.

0 = Disable “ No Reboot” mode . (Default)
1 = Enable “ No Reboot” mod e (PCH wil l disable th e
TCO Timer system reboot feature). This function is
useful when running ITP/XDP.
Notes:

1. The internal Pull-down is disabled after
PCH_PWROK is high.

2. This signal is in the primary well.

@

1 2

RH80 150K_ 0402_1%

This Signal has a weak internal Pull-down.
0: SPI (Default)
1: LPC
Notes:

1. The internal Pull-down is disabled after PCH_PWROK is high.

2. This signal is in the primary well.

RH83 100 K_0402_5%@

Top Swap Override

0 = Disable “ Top Swap” mode . (Default)
1 = Enable “ Top Swap” mode.
The internal Pull-down is disabled after PCH_PWROK is high.

12

I2C_1_SCL
I2C_1_SDA
I2C_0_SCL
I2C_0_SDA

EC_SCI# GC6_FB_ EN3V3 GC6_FB_ EN

UART_2_ PRXD_DTXD

UART_2_ PTXD_DRXD

UART_2_ PRTS_DCTS

UART_2_ PCTS_DRTS

DGPU_PW R_EN

DGPU_HO LD_RST#

GPP_H12

GC6_FB_ EN3V3<27>

check needed?

CG11 connect to GPP_B15

GPP_H12 <16>

STRAP

PCH_SMB ALERT# < 18>

PCH_SML 0ALERT# <18>

PCH_SML 1ALERT# <18>

GSPI0_MOS I

GSPI1_MOS I

PCH_SPK R

STRAP

STRAP

PCH_SPK R <1 8,56>

STRAP

B

<Touch PAD>

STRAP

GSPI1_MOS I

1 2

EC_SCI#

GSPI0_MOS I

EC_SCI#<58>

RH67 0_0402 _5%@

TS_EN<38,58>

check for remove (PCH or Both)

DGPU_AC _DETECT<27 ,58,83>

GPU_EVENT#<27>

DGPU_HO LD_RST#<27>

DGPU_PW R_EN<27,37>

UART_2_ PTXD_DRXD<52>

UART_2_ PRXD_DTXD<52>

I2C_1_SCL<6 3>

I2C_1_SDA<63>

Reserved
Reserved 0
Reserved
for 8 Layer

TS_EN

DGPU_AC _DETECT

GPU_EVE NT#

DGPU_HO LD_RST#
DGPU_PW R_EN

UART_2_ PCTS_DRTS
UART_2_ PRTS_DCTS
UART_2_ PTXD_DRXD
UART_2_ PRXD_DTXD

I2C_1_SCL
I2C_1_SDA
I2C_0_SCL
I2C_0_SDA

GPP_D9

GPP_D10

C

BA26

GPP_B22/GSPI1_MOSI

BD30

GPP_B21/GSPI1_MISO

AU26

GPP_B20/GSPI1_CLK

AW26

GPP_B19/GSPI1_CS0#

BE30

GPP_B18/GSPI0_MOSI

BD29

GPP_B17/GSPI0_MISO

BF29

GPP_B16/GSPI0_CLK

BB26

GPP_B15/GSPI0_CS0#

BB24

GPP_C9/UART0A_TXD

BE23

GPP_C8/UART0A_RXD

AP24

GPP_C11/UART0A_CTS#

BA24

GPP_C10/UART0A_RTS#

BD21

GPP_C15/UART1_CTS#/ISH_UART1_CTS#

AW24

GPP_C14/UART1_RTS#/ISH_UART1_RTS#

AP21

GPP_C13/UART1_TXD/ISH_UART1_TXD

AU24

GPP_C12/UART1_RXD/ISH_UART1_RXD

AV21

GPP_C23/UART2_CTS#

AW21

GPP_C22/UART2_RTS#

BE20

GPP_C21/UART2_TXD

BD20

GPP_C20/UART2_RXD

BE21

GPP_C19/I2C1_SCL

BF21

GPP_C18/I2C1_SDA

BC22

GPP_C17/I2C0_SCL

BF23

GPP_C16/I2C0_SDA

BE15

GPP_D4/ISH_I2C2_SDA/I2C3_SDA/SBK4_BK4

BE14

GPP_D23/ISH_I2C2_SCL/I2C3_SCL

CNP-H_BG A874

@

1 2

RH84 1K_040 2_5%@

1 2

RH85 10K_04 02_5%

1 2

RH86 1K_040 2_5%@

1 2

RH87 10K_04 02_5%

GPP_D10 GPP_D9

UH1K

+1.8VALW _PRIM

00
1
01
11

D

CNP-H

GPP_D9

Rev1.0

1 2

1 2

1 2

1 2

BA20

GPP_D10

BB20

PROJECT _ID0

BB16

PROJECT _ID1

AN18

BF14
AR18

SUB_DET

BF17

CPU_ID

BE17

AG45
AH46

AH47
AH48

AV34
AW32
BA33
BE34
BD34
BF35
BD38

+1.8VALW _PRIM

Project_ID0Project_ID1

GPP_D11GPP_D12
0 0
0
1
1 1

CPU_ID

1
0

SUB_DET

PANEL_O D_EN <38>

RH255 1K_0 402_5%H82 @

RH256 10K_ 0402_5%H62@

RH185 1K_0 402_5%@

GPP_D9/ISH_SPI_CS#/GSPI2_CS0#

GPP_D11/ISH_SPI_MISO/GP_BSSB_CLK/GSPI2_MISO

GPP_D12/ISH_SPI_MOSI/GP_BSSB_DI/GSPI2_MOSI

GPP_D15/ISH_UART0_RTS#/GSPI2_CS1#/CNV_WFEN

GPP_D10/ISH_SPI_CLK/GSPI2_CLK

GPP_D16/ISH_UART0_CTS#/CNV_WCEN

GPP_D14/ISH_UART0_TXD/I2C2_SCL

GPP_D13/ISH_UART0_RXD/I2C2_SDA

GPP_H20/ISH_I2C0_SCL
GPP_H19/ISH_I2C0_SDA

GPP_H22/ISH_I2C1_SCL
GPP_H21/ISH_I2C1_SDA

GPP_A23/ISH_GP5
GPP_A22/ISH_GP4
GPP_A21/ISH_GP3
GPP_A20/ISH_GP2
GPP_A19/ISH_GP1

GPP_A17/SD_VDD1_PWR_EN#/ISH_GP7

11 OF 13

PROJECT _ID0

PROJECT _ID1

GPP_A18/ISH_GP0

RH88 1K_040 2_5%SATAR D@

RH89 10K_04 02_5%SA TANRD@

RH90 1K_040 2_5%

RH91 10K_04 02_5%@

Project ID

EH50F(2060 WO RD)
EH50F(2060 W RD)
EH5VF(2050 WO RD)

*

EH5VF(2050 W RD)

SCI capability is available on all GPIOs
PCH GPIOs that can be routed to generate SMI# or NMI:

GPP_B14, GPP_B20, GPP_B23

‧‧‧‧

GPP_C[23:22]

‧‧‧‧

GPP_D[4:0]

‧‧‧‧

GPP_E[8:0]

‧‧‧‧

GPP_I[3:0]

‧‧‧‧

GPP_G[7:0] (support SMI# only).

‧‧‧‧

The voltage of all GPIO pads in each GPP group is determined by the voltage supplied to the group (either 3.3V or 1.8V),
except for GPP_I and GPD group, (which are 3.3V only), and GPP_J group (which is 1.8V only).

All GPIOs have programmable internal pull-up/pull-down resistors which are off by default.
The internal pull-up/pull-down for each GPIO can be enabled by BIOS programming.

E

+1.8VALW _PRIM

1 2

1 2

+1.8VALW _PRIM

1 2

Security Classification

Security Classification

Security Classification

2017/10/ 30 2018/10/ 30

2017/10/ 30 2018/10/ 30

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

2017/10/ 30 2018/10/ 30

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

PCH(6/8)GPIO/I2C/UART/STRAP

PCH(6/8)GPIO/I2C/UART/STRAP

PCH(6/8)GPIO/I2C/UART/STRAP

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

EH5VF M/B LA-H501P

EH5VF M/B LA-H501P

EH5VF M/B LA-H501P

Date : Sheet o f

Date : Sheet o f

D

Date : Sheet o f

19 1 01Friday, February 22, 2019

19 1 01Friday, February 22, 2019

19 1 01Friday, February 22, 2019

E

1A

1A

1A

A

Vinafix

B

C

D

E

GPIO Group Voltag e

GPP A

GPP B
GPP C

GPP D

GPP E
GPP F

GPP G

GPP H
GPP K

GPP I

GPP J

GPD

1U_0201_6.3V6M

CH28

Close to BB11

+1.24V_VCCLDOSR AM_IN +1.24V_PRIM_DPHY

RH96 0_0402 _5%@

RH174 for 571391_CFL_H_PDG_Rev0p71.pdf

CH39

@

1-3MM FROM PACKAGE
FOR VCCPRIM AY8/BB7

E

+1.05VALW

+1.05VALW_PC H_PRIM

+3VALW

1P_0402_50V8

1

CH41

2

@

5.95A

6.6A

0.0012A

0.2A

0.42A

BG45
BG46

0.109A

0.015A

0.213A

0.00428A

0.169A

0.0198A

0.0085A

0.021A

1 2

RH99 0_0402 _5%@

RH101 0_0402_ 5%@

UH1H

AA22

VCCPRIM_1P051

AA23

VCCPRIM_1P052

AB20

VCCPRIM_1P053

AB22

VCCPRIM_1P054

AB23

VCCPRIM_1P055

AB27

VCCPRIM_1P056

AB28

VCCPRIM_1P057

AB30

VCCPRIM_1P058

AD20

VCCPRIM_1P059

AD23

VCCPRIM_1P0510

AD27

VCCPRIM_1P0511

AD28

VCCPRIM_1P0512

AD30

VCCPRIM_1P0513

AF23

VCCPRIM_1P0516

AF27

VCCPRIM_1P0517

AF30

VCCPRIM_1P0518

U26

VCCPRIM_1P0523

U29

VCCPRIM_1P0524

V25

VCCPRIM_1P0525

V27

VCCPRIM_1P0526

V28

VCCPRIM_1P0527

V30

VCCPRIM_1P0528

V31

VCCPRIM_1P0529

AD31

VCCPRIM_1P0514

AE17

VCCPRIM_1P0515

W22

VCCDUSB_1P051

W23

VCCDUSB_1P052

VCCDSW_1P051
VCCDSW_1P052

W31

VCCPRIM_MPHY_1P05

D1

VCCPRIM_1P0521

E1

VCCPRIM_1P0522

C49

VCCAMPHYPLL_1P051

D49

VCCAMPHYPLL_1P052

E49

VCCAMPHYPLL_1P053

P2

VCCA_XTAL_1P051

P3

VCCA_XTAL_1P052

W19

VCCA_SRC_1P051

W20

VCCA_SRC_1P052

C1

VCCAPLL_1P054

C2

VCCAPLL_1P055

V19

VCCA_BCLK_1P05

B1

VCCAPLL_1P051

B2

VCCAPLL_1P052

B3

VCCAPLL_1P053

CNP-H_BGA874

@

12

+1.05VALW

JPH1

@

2

112

JUMP_43X79

1 1

1 2

RH94 0_0603 _5%@

+1.05VALW_PC H

2 2

place near VCCDUSB
FOR W22/W23

1-5MM FROM PACKAGE EDGE
FOR VCCAPLL C1/C2

3 3

+1.05VALW_PC H

0.1U_0201_10V6K

1

2

+1.05VALW_PC H

1U_0201_6.3V6M

1

2

CH29

CH33

1 2

RH102 0_0 402_5%@

1P_0402_50V8

1

CH43

2

@

1-3MM FROM PACKAGE EDGE
FOR VCCA_BCLK V19

+1.05VALW_PC H_PRIM

5.95A

1U_0201_6.3V6M

CH23

1

2

+1.05VALW

6.6A

22U_0603_6.3V6M

1U_0201_6.3V6M

CH26

1

1

CH25

2

2

Place Near UH1 VCCPRIM_1_0523~29
3-5MM FROM PACKAGE EDGE

+1.05VALW_PC H

+1.05VALW_PC H +1.05V_VCCDSW

0.1U_0201_10V6K
CH30

1

2

1-3MM FROM PACKAGE
VCCPRIM_MPHY W31

+1.05VALW_PC H

0.1U_0201_10V6K
CH34

1

2

+1.05VALW_VCC AZPLL

1P_0402_50V8

1

CH44

2

@

1-3MM FROM PACKAGE EDGE

1-5MM FROM PACKAGE EDGE
FOR VCCAPLL B1/B2/B3

1U_0201_6.3V6M

1

2

+1.05VALW_PC H

1U_0201_6.3V6M

1

2

HSIO for DMIU/USB3.1/PCIE=4162mA

+1.05VALW_PC H

+1.05V_VCCDSW

+1.05VALW_VCC AZPLL

+1.05VALW_VCC AMPHYPLL

+1.05VALW_XTAL

CH31

0.1U_0201_10V6K
CH54

1

CH35

2

1-3MM FROM PACKAGE EDGE

A

+1.05VALW_VCC AMPHYPLL

22U_0603_6.3V6M

1

1

CH45

2

2

+1.05VALW_XTAL

22U_0603_6.3V6M

1

CH49

2

1U_0201_6.3V6M

CH46

+RTCBATT

change to 10k

RH104 1K_0 402_5%

+CHGRTC

B

12

DH2

2

3

BAV70W_SOT32 3-3

+RTCVCC

1

1U_0201_6.3V6M

0.1U_0201_10V6K
CH48

1

1

CH47

2

2

1 2

RH103 0_0 402_5%@

LC filter close to pin

4 4

1uF 1-3MM FROM PACKAGE EDGE

1 2

RH105 0_0 402_5%@

CNP-H

VCCPRIM_3P32

VCCPRIM_3P35

VCCPGPPG_3P3

VCCPRIM_3P33
VCCPRIM_3P34

VCCPRIM_3P31
VCCDSW_3P31
VCCDSW_3P32

VCCPRIM_1P83
VCCPRIM_1P84
VCCPRIM_1P85
VCCPRIM_1P86
VCCPRIM_1P87

VCCPRIM_1P81
VCCPRIM_1P82

VCCPRIM_1P0520
VCCPRIM_1P0519

VCCPRIM_1P241
VCCPRIM_1P242

VCCDPHY_1P241
VCCDPHY_1P242
VCCDPHY_1P243

VCCMPHY_SENSE
VSSMPHY_SENSE

8 OF 13

+3VALW_DSW

0.1U_0201_10V6K
CH40

1

2

+3VALW_HDA

1P_0402_50V8

1

CH42

2

@

reserve filter follow CRB
8/21

+RTCBATT

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

DCPRTC1
DCPRTC2

VCCSPI

VCCRTC1
VCCRTC2

VCCPGPPHK1
VCCPGPPHK2
VCCPGPPEF1
VCCPGPPEF2

VCCPGPPD
VCCPGPPBC1
VCCPGPPBC2

VCCPGPPA

VCCHDA

Rev1.0

JRTC1

1

1

2

2

3

GND

4

GND

ACES_50271-00 20N-001

CONN@

SP02000RO00

AW9

BF47
BG47

V23

AN44

BC49
BD49

AN21
AY8
BB7

AC35
AC36
AE35
AE36

AN24
AN26
AP26

AN32

AT44
BE48
BE49

BB14
AG19
AG20
AN15
AR15
BB11

AF19
AF20

AG31
AF31
AK22
AK23

AJ22
AJ23
BG5

K47
K46

RH100 0_0 603_5%

2017/10/30 2018/10/30

2017/10/30 2018/10/30

2017/10/30 2018/10/30

0.182A

+VCCRTCEXT

0.095A

0.05A

0.145A

0.97A

0.262A

0.174A

0.14A

0.343A

0.101A

0.106A

0.113A

0.00767A

0.766A

0.882A

+1.8V_PHVLDO

0.193A

0.0895A

VCCMPHY_SENSE
VSSMPHY_SENSE

1 2

Compal Secret Data

Compal Secret Data

Compal Secret Data

Internal LDO

+3VALW

+1.8VALW_PRIM

+1.8V_PHVLDO

RH95 0_0402_5%@

TH27@
TH28@

+1.8VALW_PRIM+1.8VALW

Deciphered Date

Deciphered Date

Deciphered Date

D

+VCCRTCEXT

+3VALW

+RTCVCC

+1.8VALW_PRIM

+3VALW_DSW

+3VALW_HDA

1 2

+1.05VALW_PC H
+1.05VALW_PC H

+1.24V_VCCLDOSR AM_IN

+1.24V_PRIM_DPHY

+1.24V_PRIM_MAR

1-3MM FROM PACKAGE
FOR PGPPEF AE35/AE37

+1.8VALW_PRIM

Short pins AJ22,AJ23,AK22,AK23 together
at surface layer from PDG Rev0.71

0.1U_0201_10V6K
CH36

1

2

@

reserved for c nvi

+1.8VALW_PRIM + 1.8VALW_PRIM

0.1U_0201_10V6K
CH52

1

2

near AG19/AG20

+VCCRTCEXT

0.1U_0201_10V6K
CH24

1

2

+1.8VALW_PRIM

4.7U_0402_6.3V6M

1

1

CH27

2

2

VCCPHVLDO_1P8
(External VRM mode RH172 unmount)

For DDX03 R02

+1.24V_PRIM_MAR

4.7U_0402_6.3V6M

1

CH32

2

+3VALW+3VALW

0.1U_0201_10V6K

1

2

1-3MM FROM PACKAGE
FOR PGPPHK AC35/AC36

0.1U_0201_10V6K
CH53

1

2

@

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

PCH(7/8)Power

PCH(7/8)Power

PCH(7/8)Power

Size Document Nu mber R ev

Size Document Nu mber R ev

Size Document Nu mber R ev

Custom

Custom

Custom

EH5VF M/B LA-H501P

EH5VF M/B LA-H501P

EH5VF M/B LA-H501P

Date : Sheet of

Date : Sheet of

Date : Sheet of

1 2

1

2

1U_0201_6.3V6M

*

+3VALW

CH37

3.3 V

3.3 V

3.3 V

1.8 V

3.3 V

3.3 V

3.3 V

3.3V Only

1.8V Only

3.3V Only

0.1U_0201_10V6K
CH38

1

2

20 101Friday, February 22, 2019

20 101Friday, February 22, 2019

20 101Friday, February 22, 2019

1A

1A

1A

A

B

C

D

E

CNP-H

CNP-H

UH1I

A2

VSS

1 1

2 2

3 3

A28

A33
A37

A45
A46
A47
A48

AA19
AA20
AA25
AA27
AA28
AA30
AA31
AA49

AA5
AB19
AB25
AB31
AC12
AC17
AC33
AC38

AC4

AC46

AD1
AD19

AD2
AD22
AD25
AD49
AE12
AE33
AE38

AE4
AE46
AF22
AF25
AF28

AG1
AG22
AG23
AG25
AG27
AG28
AG30
AG49
AH12
AH17
AH33
AH38

AJ19
AJ20
AJ25
AJ27
AJ28
AJ30

AJ31
AK19
AK20
AK25
AK27
AK28
AK30
AK31

AK4

AK46

A3

A4

A5
A8

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

9 OF 13

VSS

CNP-H_BG A874

@

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

Rev1.0

AL12
AL17
AL21
AL24
AL26
AL29
AL33
AL38
AM1
AM18
AM32
AM49
AN12
AN16
AN34
AN38
AP4
AP46
AR12
AR16
AR34
AR38
AT1
AT16
AT18
AT21
AT24
AT26
AT29
AT32
AT34
AT45
AV11
AV39
AW10
AW4
AW40
AW46
B47
B48
B49
BA12
BA14
BA44
BA5
BA6
BB41
BB43
BB9
BC10
BC13
BC15
BC19
BC24
BC26
BC31
BC35
BC40
BC45
BC8
BD43
BE44
BF1
BF2
BF3
BF48
BF49
BG17
BG2
BG22
BG25
BG28

BG3
BG33
BG37

BG4
BG48

C12
C25
C30

C48

D12
D16
D17
D30
D33

E10
E13
E15
E17
E19
E22
E24
E26
E31
E33
E35
E40
E42

F41
F43
F47

G44

K11

K39
M16
M18
M21

C4

C5

D8

E8

G6

H8
J10
J26
J29

J4
J40
J46
J47
J48

J9

UH1L

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

12 OF 13

VSS

CNP-H_BG A874

@

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

Rev1.0

M24
M32
M34
M49
M5
N12
N16
N34
N35
N37
N38
P26
P29
P4
P46
R12
R16
R26
R29
R3
R34
R38
R4
T17
T18
T32
T4
T49
T5
T7
U12
U15
U17
U21
U24
U33
U38
V20
V22
V4
V46
W25
W27
W28
W30
Y10
Y12
Y17
Y33
Y38
Y9

CNP-H

UH1J

RSVD7
RSVD8
RSVD6
RSVD5

RSVD3
RSVD4

RSVD2
RSVD1

PREQ#
PRDY#

CPU_TRST#

TRIGGER_OUT

TRIGGER_IN

10 OF 13

CNP-H_BG A874

@

Rev1.0

Y14
Y15
U37
U35

N32
R32

AH15
AH14

XDP_PRE Q#

AL2

XDP_PRD Y#

AM5

CPU_XDP _TRST#

AM4

PCH_TRIGO UT PCH_TRIGO UT_R

AK3

CPU_TRIGO UT_R

AK2

1 2

RH106 30_040 2_5%

XDP_PRE Q# <10>
XDP_PRD Y# <10>
CPU_XDP _TRST# <10>

PCH_TRIGO UT_R <13>
CPU_TRIGO UT_R <13>

4 4

Security Classification

Security Classification

Security Classification

2017/10/ 30 2018/10/ 30

2017/10/ 30 2018/10/ 30

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

2017/10/ 30 2018/10/ 30

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

PCH(8/8)GND/RSVD

PCH(8/8)GND/RSVD

PCH(8/8)GND/RSVD

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

EH5VF M/B LA-H501P

EH5VF M/B LA-H501P

EH5VF M/B LA-H501P

Date : Sheet o f

Date : Sheet o f

D

Date : Sheet o f

21 1 01Friday, February 22, 2019

21 1 01Friday, February 22, 2019

21 1 01Friday, February 22, 2019

E

1A

1A

1A

5

D D

C C

4

3

2

1

Reserve Page

B B

A A

Security Cl assification

Security Cl assification

Security Cl assification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2017/11/23 2017/12/31

2017/11/23 2017/12/31

2017/11/23 2017/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet o f

Date: Sheet o f

2

Date: Sheet o f

Compal Electronics, Inc.

N18E-GDDR6_D

N18E-GDDR6_D

N18E-GDDR6_D

EH5VF M/B LA-H501P

EH5VF M/B LA-H501P

EH5VF M/B LA-H501P

1

1A

1A

22 101Friday, February 22, 2019

22 101Friday, February 22, 2019

22 101Friday, February 22, 2019

1A

5

4

3

2

1

CHANNEL-A

BOT

REVERSE TYPE

Interleaved Memory

TOP: JDIMM1 CONN Non-ECC DIMM

D D

+1.2V_VDDQ

+3VS

0.1U_0201_10V6K

2.2U_0402_6.3V6M

+0.6V_DDR_VREFC A

CD1

2

2

CD2

1

SPD ADDRESS FOR CHANNEL A :
WRITE ADDRESS: 0XA0
READ ADDRESS: 0XA1
SA0 = 0; SA1 = 0; SA2 = 0.
DDR4 POR OPERATING SPEED: 1867 MT/S

C C

STRETCH GOAL IS 2133 MT/S

Layout Note:
Place near JDIMM1.257,259

+2.5V + 0.6VS_VTT

10U_0402_6.3V6M

10U_0402_6.3V6M

1

1

CD3

2

2

Layout Note:
PLACE THE CAP near JDIMM1. 164

B B

+0.6V_DDR_VREFC A

2

CD11

0.1U_0201_ 10V6K

1

10uF* 2
1uF*2

1U_0201_6.3V6M

1U_0201_6.3V6M

1

1

CD4

2

CD5

2

2

1

CD6

2.2uF* 1

0.1uF* 1

CD12

2.2U_0402_ 6.3V6M

Layout Note:
Place near JDIMM1.258

10uF* 2

10U_0402_6.3V6M

1

2

1uF*1

1U_0201_6.3V6M

10U_0402_6.3V6M

1

1

CD7

CD9

CD8

2

2

1

PLACE NEAR TO PIN

Part Number: SP07001CY00
Part Value: S SOCKET LOTES ADDR0206-P001A 260P DDR4

DDR_A_D[0..15]<7>

DDR_A_D[16..31 ]<7>

DDR_A_D[32..47 ]<7>

DDR_A_D[48..63 ]<7>

JDIMM1B

REVERSE

111

VDD1

112

VDD2

117

VDD3

118

VDD4

123

VDD5

124

VDD6

129

VDD7

130

VDD8

135

VDD9

136

VDD10

255

VDDSPD

164

VREFCA

1

VSS

2

VSS

5

VSS

6

VSS

9

VSS

10

VSS

14

VSS

15

VSS

18

VSS

19

VSS

22

VSS

23

VSS

26

VSS

27

VSS

30

VSS

31

VSS

35

VSS

36

VSS

39

VSS

40

VSS

43

VSS

44

VSS

47

VSS

48

VSS

51

VSS

52

VSS

56

VSS

57

VSS

60

VSS

61

VSS

64

VSS

65

VSS

68

VSS

69

VSS

72

VSS

73

VSS

77

VSS

78

VSS

81

VSS

82

VSS

85

VSS

86

VSS

89

VSS

90

VSS

93

VSS

94

VSS

98

VSS

262

GND

LOTES_ADDR02 06-P001A

CONN@

VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
VDD19

VPP1
VPP2

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

GND

141
142
147
148
153
154
159
160
163

258

VTT

257
259

99
102
103
106
107
167
168
171
172
175
176
180
181
184
185
188
189
192
193
196
197
201
202
205
206
209
210
213
214
217
218
222
223
226
227
230
231
234
235
238
239
243
244
247
248
251
252

261

+1.2V_VDDQ

+0.6VS_VTT

+2.5V

+1.2V_VDDQ

RD7 240_0 402_1%

DDR_DRAMRST #_R

2

1

+1.2V_VDDQ

(4 mm)

DDR_A_CLK0<7>
DDR_A_CLK#0<7>
DDR_A_CLK1<7>
DDR_A_CLK#1<7>

DDR_A_CKE0<7>
DDR_A_CKE1<7>

DDR_A_CS#0<7>
DDR_A_CS#1<7>

DDR_A_ODT0<7>
DDR_A_ODT1<7>

DDR_A_BG0<7>
DDR_A_BG1<7>
DDR_A_BA0<7>
DDR_A_BA1<7>

DDR_A_MA0<7>
DDR_A_MA1<7>
DDR_A_MA2<7>
DDR_A_MA3<7>
DDR_A_MA4<7>
DDR_A_MA5<7>
DDR_A_MA6<7>
DDR_A_MA7<7>
DDR_A_MA8<7>
DDR_A_MA9<7>
DDR_A_MA10<7>
DDR_A_MA11<7>
DDR_A_MA12<7>
DDR_A_MA13<7>
DDR_A_MA14_W E#< 7>
DDR_A_MA15_CAS#<7>
DDR_A_MA16_RAS#<7>

DDR_A_ACT#<7>

DDR_A_PAR<7>
DDR_A_ALERT#<7 >

12

DDR_DRAMRST #_R<1 8,24>

D_CK_SDATA<18,24>
D_CK_SCLK<18,24>

For ECC DIMM

+1.2V_VDDQ

CD10

ESD@

33P_0201_5 0V8J

PLACE NEAR TO SODIMM

DDR_A_CLK0
DDR_A_CLK#0
DDR_A_CLK1
DDR_A_CLK#1

DDR_A_CKE0
DDR_A_CKE1

DDR_A_CS#0
DDR_A_CS#1

DDR_A_ODT0
DDR_A_ODT1

DDR_A_BG0
DDR_A_BG1
DDR_A_BA0
DDR_A_BA1

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14_W E#
DDR_A_MA15_CAS#
DDR_A_MA16_RAS#

DDR_A_ACT#

DDR_A_PAR
DDR_A_ALERT#
DIMM1_CHA_EVENT#
DDR_DRAMRST #_R

JDIMM1A

REVERSE

137

CK0(T)

139

CK0#(C)

138

CK1(T)

140

CK1#(C)

109

CKE0

110

CKE1

149

S0#

157

S1#

162

S2#/C0

165

S3#/C1

155

ODT0

161

ODT1

115

BG0

113

BG1

150

BA0

145

BA1

144

A0

133

A1

132

A2

131

A3

128

A4

126

A5

127

A6

122

A7

125

A8

121

A9

146

A10_AP

120

A11

119

A12

158

A13

151

A14_WE#

156

A15_CAS#

152

A16_RAS#

114

ACT#

143

PARITY

116

ALERT#

134

EVENT#

108

RESET#

254

SDA

253

SCL

166

SA2

260

SA1

256

SA0

92

CB0_NC

91

CB1_NC

101

CB2_NC

105

CB3_NC

88

CB4_NC

87

CB5_NC

100

CB6_NC

104

CB7_NC

97

DQS8(T)

95

DQS8#(C)

12

DM0#/DBI0#

33

DM1#/DBI1#

54

DM2#/DBI2#

75

DM3#/DBI3#

178

DM4#/DBI4#

199

DM5#/DBI5#

220

DM6#/DBI6#

241

DM7#/DBI7#

96

DM8#/DBI8#

LOTES_ADDR02 06-P001A

CONN@

DQS0(T)

DQS0#(C)

DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

DQS1(T)

DQS1#(C)

DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23

DQS2(T)

DQS2#(C)

DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

DQS3(T)

DQS3#(C)

DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39

DQS4(T)

DQS4#(C)

DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47

DQS5(T)

DQS5#(C)

DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55

DQS6(T)

DQS6#(C)

DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

DQS7(T)

DQS7#(C)

DDR_A_D0

8

DQ0

DDR_A_D1

7

DQ1

DDR_A_D2

20

DQ2

DDR_A_D3

21

DQ3

DDR_A_D4

4

DQ4

DDR_A_D5

3

DQ5

DDR_A_D6

16

DQ6

DDR_A_D7

17

DQ7

DDR_A_DQS0

13

DDR_A_DQS#0

11

DDR_A_D8

28

DQ8

DDR_A_D9

29

DQ9

DDR_A_D10

41

DDR_A_D11

42

DDR_A_D12

24

DDR_A_D13

25

DDR_A_D14

38

DDR_A_D15

37

DDR_A_DQS1

34

DDR_A_DQS#1

32

DDR_A_D16

50

DDR_A_D17

49

DDR_A_D18

62

DDR_A_D19

63

DDR_A_D20

46

DDR_A_D21

45

DDR_A_D22

58

DDR_A_D23

59

DDR_A_DQS2

55

DDR_A_DQS#2

53

DDR_A_D24

70

DDR_A_D25

71

DDR_A_D26

83

DDR_A_D27

84

DDR_A_D28

66

DDR_A_D29

67

DDR_A_D30

79

DDR_A_D31

80

DDR_A_DQS3

76

DDR_A_DQS#3

74

DDR_A_D32

174

DDR_A_D33

173

DDR_A_D34

187

DDR_A_D35

186

DDR_A_D36

170

DDR_A_D37

169

DDR_A_D38

183

DDR_A_D39

182

DDR_A_DQS4

179

DDR_A_DQS#4

177

DDR_A_D40

195

DDR_A_D41

194

DDR_A_D42

207

DDR_A_D43

208

DDR_A_D44

191

DDR_A_D45

190

DDR_A_D46

203

DDR_A_D47

204

DDR_A_DQS5

200

DDR_A_DQS#5

198

DDR_A_D48

216

DDR_A_D49

215

DDR_A_D50

228

DDR_A_D51

229

DDR_A_D52

211

DDR_A_D53

212

DDR_A_D54

224

DDR_A_D55

225

DDR_A_DQS6

221

DDR_A_DQS#6

219

DDR_A_D56

237

DDR_A_D57

236

DDR_A_D58

249

DDR_A_D59

250

DDR_A_D60

232

DDR_A_D61

233

DDR_A_D62

245

DDR_A_D63

246

DDR_A_DQS7

242

DDR_A_DQS#7

240

DDR_A_DQS0 <7>

DDR_A_DQS#0 <7>

DDR_A_DQS1 <7>

DDR_A_DQS#1 <7>

DDR_A_DQS2 <7>

DDR_A_DQS#2 <7>

DDR_A_DQS3 <7>

DDR_A_DQS#3 <7>

DDR_A_DQS4 <7>

DDR_A_DQS#4 <7>

DDR_A_DQS5 <7>

DDR_A_DQS#5 <7>

DDR_A_DQS6 <7>

DDR_A_DQS#6 <7>

DDR_A_DQS7 <7>

DDR_A_DQS#7 <7>

DIMM Side

+0.6V_DDR_VREFC A

Layout Note:
Place near JDIMM1

10uF* 6
1uF*8
330uF* 1

10U_0402_6.3V6M

CD16

A A

1

2

CD18

CD17

1

1

1

2

2

2

5

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

CD19

CD21

CD20

1

1

2

1

2

2

+1.2V_VDDQ+1.2V_VDDQ

10U_0402_6.3V6M

10U_0402_6.3V6M

CD23

CD22

1

2

@

@

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1

1

CD24

2

2

1U_0201_6.3V6M

1

CD25

2

1U_0201_6.3V6M

1

1

CD26

CD27

2

2

4

1U_0201_6.3V6M

1U_0201_6.3V6M

1

1

CD30

CD29

CD28

2

2

+1.2V_VDDQ

1U_0201_6.3V6M

1

2

1

+

2

CD32
330U_D2_2 V_Y

CD31

2

CD13

@

0.1U_0201_ 10V6K

1

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

RD8
1K_0402_1%

1 2

RD10
1K_0402_1%

1 2

2017/10/30 2018/10/30

2017/10/30 2018/10/30

2017/10/30 2018/10/30

2

CD14

0.1U_0201_ 10V6K

1

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

1 2

RD9

2_0402_1%

2

CPU Side

+0.6V_VREFCA

VREF traces should be at least 20 mils
wide with 20 mils spacing to other

1

sign al s

CD15

0.022U_040 2_16V7K

2

RD11

24.9_0402_1 %

1 2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Nu mber R ev

Size Document Nu mber R ev

Size Document Nu mber R ev

Date : Sheet of

Date : Sheet of

Date : Sheet of

Compal Electronics, Inc.

DDRIV_CHA: DIMM0

DDRIV_CHA: DIMM0

DDRIV_CHA: DIMM0

EH5VF M/B LA-H501P

EH5VF M/B LA-H501P

EH5VF M/B LA-H501P

1

23 101Friday, February 22, 2019

23 101Friday, February 22, 2019

23 101Friday, February 22, 2019

1A

1A

1A

5

4

3

2

1

CHANNEL-B

TOP: JDIMM2 CONN

D D

Non-ECC DIMM

SPD ADDRESS FOR CHANNEL B :
WRITE ADDRESS: 0XA4
READ ADDRESS: 0XA3
SA0 = 0; SA1 = 1; SA2 = 0.
DDR4 POR OPERATING SPEED: 1867 MT/S
STRETCH GOAL IS 2133 MT/S

C C

Layout Note:
Place near JDIMM3.257,259

10uF* 2
1uF*2

10U_0402_6.3V6M

10U_0402_6.3V6M

1

1

CD35

2

2

Layout Note:
PLACE THE CAP WITHIN 200 MILS
FROM THE JDIMM3

B B

+0.6V_DDRB_VRE FCA

2

CD42

0.1U_0201_ 10V6K

1

Layout Note:
Place near JDIMM3

10U_0402_6.3V6M

1

A A

2

1U_0201_6.3V6M

1U_0201_6.3V6M

1

1

CD36

CD46

2

1

2

CD37

10U_0402_6.3V6M

CD47

CD38

2

2.2uF* 1

0.1uF* 1

2

CD43

2.2U_0402_ 6.3V6M

1

10U_0402_6.3V6M

CD48

1

1

2

2

10uF* 6
1uF*8
330uF* 1

10U_0402_6.3V6M

10U_0402_6.3V6M

CD49

CD50

1

2

Layout Note:
Place near JDIMM3.258

+0.6VS_VTT+2.5V

10U_0402_6.3V6M

1

2

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

CD52

CD53

1

1

1

2

2

2

@

10uF* 2
1uF*1

1U_0201_6.3V6M

10U_0402_6.3V6M

1

1

CD39

CD41

CD40

2

2

+1.2V_VDDQ+1.2V_VDDQ

1U_0201_6.3V6M

1U_0201_6.3V6M

CD54

@

1

1

CD57

CD56

2

2

Interleaved Memory

+3VS

0.1U_0201_10V6K

CD33

2

1

PLACE NEAR TO PIN

1U_0201_6.3V6M

1

2

1U_0201_6.3V6M

1U_0201_6.3V6M

1

CD58

2

1U_0201_6.3V6M

1

1

CD60

CD59

2

2

+1.2V_VDDQ

2.2U_0402_6.3V6M

+0.6V_DDRB_VRE FCA

2

CD34

1

1U_0201_6.3V6M

1

CD61

CD62

2

DDR_B_D[0..15 ]<8>

DDR_B_D[16 ..31]<8>

DDR_B_D[32 ..47]<8>

DDR_B_D[48 ..63]<8>

111
112
117
118
123
124
129
130
135
136

255

164

10
14
15
18
19
22
23
26
27
30
31
35
36
39
40
43
44
47
48
51
52
56
57
60
61
64
65
68
69
72
73
77
78
81
82
85
86
89
90
93
94
98

262

Part Number: SP07001HW00
Part Value: S SOCKET LOTES ADDR0205-P001A DDR4 STD

1U_0201_6.3V6M

1

CD63

2

JDIMM2B

STD

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10

VDDSPD

VREFCA

1

VSS

2

VSS

5

VSS

6

VSS

9

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

GND

LOTES_ADDR02 05-P001A

CONN@

VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
VDD19

VPP1
VPP2

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

GND

141
142
147
148
153
154
159
160
163

258

VTT

257
259

99
102
103
106
107
167
168
171
172
175
176
180
181
184
185
188
189
192
193
196
197
201
202
205
206
209
210
213
214
217
218
222
223
226
227
230
231
234
235
238
239
243
244
247
248
251
252

261

+1.2V_VDDQ

+0.6VS_VTT

+2.5V

+1.2V_VDDQ

+1.2V_VDDQ

+1.2V_VDDQ

2

CD44

0.1U_0201_ 10V6K

1

2

CD51

0.1U_0201_ 10V6K

1

@

1 2

1 2

RD19
1K_0402_1%

RD21
1K_0402_1%

DDR_B_CLK 0<8>
DDR_B_CLK #0< 8>

DDR_B_CLK 1<8>

DDR_B_CLK #1< 8>

DDR_B_CKE0<8>
DDR_B_CKE1<8>

DDR_B_CS# 0<8>
DDR_B_CS# 1<8>

DDR_B_ODT 0<8 >
DDR_B_ODT 1<8 >

DDR_B_BG0<8>
DDR_B_BG1<8>
DDR_B_BA0<8 >
DDR_B_BA1<8 >

DDR_B_MA0<8>
DDR_B_MA1<8>
DDR_B_MA2<8>
DDR_B_MA3<8>
DDR_B_MA4<8>
DDR_B_MA5<8>
DDR_B_MA6<8>
DDR_B_MA7<8>
DDR_B_MA8<8>
DDR_B_MA9<8>
DDR_B_MA10<8>
DDR_B_MA11<8>
DDR_B_MA12<8>
DDR_B_MA13<8>
DDR_B_MA14_ WE#<8>
DDR_B_MA15_ CAS#<8>
DDR_B_MA16_ RAS#<8>

DDR_B_ACT#<8>

DDR_B_PAR<8>

DDR_B_ALERT #<8>

RD18

240_0402_ 1%

DDR_DRAMRST #_R<1 8,23>

DIMM Side

+0.6V_DDRB_VRE FCA

STD

12

D_CK_SDATA<18,23>
D_CK_SCLK<18,23>

For ECC DIMM

1 2

RD20

2_0402_1%

2

CD45

0.1U_0201_ 10V6K

1

DIMM3_CHB_EVENT #
DDR_DRAMRST #_R

+3VS

(4 mm)BOT

DDR_B_CLK 0
DDR_B_CLK #0
DDR_B_CLK 1
DDR_B_CLK #1

DDR_B_CKE0
DDR_B_CKE1

DDR_B_CS# 0
DDR_B_CS# 1

DDR_B_ODT 0
DDR_B_ODT 1

DDR_B_BG0
DDR_B_BG1
DDR_B_BA0
DDR_B_BA1

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14_ WE#
DDR_B_MA15_ CAS#
DDR_B_MA16_ RAS#

DDR_B_ACT#

DDR_B_PAR
DDR_B_ALERT #

CPU Side

1

CD55

0.022U_040 2_16V7K

2

RD22

24.9_0402_1 %

1 2

JDIMM2A

STD

137

CK0(T)

139

CK0#(C)

138

CK1(T)

140

CK1#(C)

109

CKE0

110

CKE1

149

S0#
S1#
S2#/C0
S3#/C1

ODT0
ODT1

BG0
BG1
BA0
BA1

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10_AP
A11
A12
A13
A14_WE#
A15_CAS#
A16_RAS#

ACT#

PARITY
ALERT#
EVENT#
RESET#

SDA
SCL

SA2
SA1
SA0

CB0_NC
CB1_NC
CB2_NC
CB3_NC
CB4_NC
CB5_NC
CB6_NC
CB7_NC
DQS8(T)
DQS8#(C)

DM0#/DBI0#
DM1#/DBI1#
DM2#/DBI2#
DM3#/DBI3#
DM4#/DBI4#
DM5#/DBI5#
DM6#/DBI6#
DM7#/DBI7#
DM8#/DBI8#

GND1
GND2

DQS0(T)

DQS0#(C)

DQS1(T)

DQS1#(C)

DQS2(T)

DQS2#(C)

DQS3(T)

DQS3#(C)

DQS4(T)

DQS4#(C)

DQS5(T)

DQS5#(C)

DQS6(T)

DQS6#(C)

DQS7(T)

DQS7#(C)

157
162
165

155
161

115
113
150
145

144
133
132
131
128
126
127
122
125
121
146
120
119
158
151
156
152

114

143
116
134
108

254
253

166
260
256

92

91
101
105

88

87
100
104

97

95

12

33

54

75
178
199
220
241

96

261
262

LOTES_ADDR02 05-P001A

CONN@

+0.6V_B_VREFDQ

VREF traces should be at least 20 mils
wide with 20 mils spacing to other
sign al s

DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23

DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39

DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47

DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55

DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

DDR_B_D0

8

DQ0

DDR_B_D1

7

DQ1

DDR_B_D2

20

DQ2

DDR_B_D3

21

DQ3

DDR_B_D4

4

DQ4

DDR_B_D5

3

DQ5

DDR_B_D6

16

DQ6

DDR_B_D7

17

DQ7

DQ8
DQ9

13
11

28
29
41
42
24
25
38
37
34
32

50
49
62
63
46
45
58
59
55
53

70
71
83
84
66
67
79
80
76
74

174
173
187
186
170
169
183
182
179
177

195
194
207
208
191
190
203
204
200
198

216
215
228
229
211
212
224
225
221
219

237
236
249
250
232
233
245
246
242
240

DDR_B_DQS0
DDR_B_DQS# 0

DDR_B_D8
DDR_B_D9
DDR_B_D11
DDR_B_D15
DDR_B_D14
DDR_B_D10
DDR_B_D12
DDR_B_D13

DDR_B_DQS1
DDR_B_DQS# 1

DDR_B_D16
DDR_B_D17
DDR_B_D19
DDR_B_D20
DDR_B_D22
DDR_B_D18
DDR_B_D23
DDR_B_D21

DDR_B_DQS2
DDR_B_DQS# 2

DDR_B_D30
DDR_B_D25
DDR_B_D26
DDR_B_D24
DDR_B_D28
DDR_B_D27
DDR_B_D29
DDR_B_D31

DDR_B_DQS3
DDR_B_DQS# 3

DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D32
DDR_B_D39
DDR_B_D38
DDR_B_D37
DDR_B_D33

DDR_B_DQS4
DDR_B_DQS# 4

DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47

DDR_B_DQS5
DDR_B_DQS# 5

DDR_B_D48
DDR_B_D52
DDR_B_D50
DDR_B_D55
DDR_B_D51
DDR_B_D54
DDR_B_D49
DDR_B_D53

DDR_B_DQS6
DDR_B_DQS# 6

DDR_B_D61
DDR_B_D57
DDR_B_D60
DDR_B_D56
DDR_B_D62
DDR_B_D59
DDR_B_D63
DDR_B_D58

DDR_B_DQS7
DDR_B_DQS# 7

DDR_B_DQS0 <8>

DDR_B_DQS# 0 <8>

DDR_B_DQS1 <8>

DDR_B_DQS# 1 <8>

DDR_B_DQS2 <8>

DDR_B_DQS# 2 <8>

DDR_B_DQS3 <8>

DDR_B_DQS# 3 <8>

DDR_B_DQS4 <8>

DDR_B_DQS# 4 <8>

DDR_B_DQS5 <8>

DDR_B_DQS# 5 <8>

DDR_B_DQS6 <8>

DDR_B_DQS# 6 <8>

DDR_B_DQS7 <8>

DDR_B_DQS# 7 <8>

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2017/10/30 2018/10/30

2017/10/30 2018/10/30

2017/10/30 2018/10/30

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Nu mber R ev

Size Document Nu mber R ev

Size Document Nu mber R ev

Date : Sheet of

Date : Sheet of

2

Date : Sheet of

Compal Electronics, Inc.

DDRIV_CHB: DIMM0

DDRIV_CHB: DIMM0

DDRIV_CHB: DIMM0

EH5VF M/B LA-H501P

EH5VF M/B LA-H501P

EH5VF M/B LA-H501P

1

1A

1A

24 101Friday, February 22, 2019

24 101Friday, February 22, 2019

24 101Friday, February 22, 2019

1A

5

D D

C C

4

3

2

1

Reserve Page

B B

A A

Security Cl assification

Security Cl assification

Security Cl assification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2017/11/23 2017/12/31

2017/11/23 2017/12/31

2017/11/23 2017/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet o f

Date: Sheet o f

2

Date: Sheet o f

Compal Electronics, Inc.

N18E-GDDR6_D

N18E-GDDR6_D

N18E-GDDR6_D

EH5VF M/B LA-H501P

EH5VF M/B LA-H501P

EH5VF M/B LA-H501P

1

1A

1A

25 101Friday, February 22, 2019

25 101Friday, February 22, 2019

25 101Friday, February 22, 2019

1A

5

D D

C C

4

3

2

1

Reserve Page

B B

A A

Security Cl assification

Security Cl assification

Security Cl assification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2017/11/23 2017/12/31

2017/11/23 2017/12/31

2017/11/23 2017/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet o f

Date: Sheet o f

2

Date: Sheet o f

Compal Electronics, Inc.

N18E-GDDR6_D

N18E-GDDR6_D

N18E-GDDR6_D

EH5VF M/B LA-H501P

EH5VF M/B LA-H501P

EH5VF M/B LA-H501P

1

1A

1A

26 101Friday, February 22, 2019

26 101Friday, February 22, 2019

26 101Friday, February 22, 2019

1A

A

UV1A

PEX_TREMP

1

2

IN B

IN A

AN12
AM12
AN14
AM14
AP14
AP15
AN15
AM15
AN17
AM17
AP17
AP18
AN18
AM18
AN20
AM20
AP20
AP21
AN21
AM21
AN23
AM23
AP23
AP24
AN24
AM24
AN26
AM26
AP26
AP27
AN27
AM27

AK14
AJ14
AH14
AG14
AK15
AJ15
AL16
AK16
AK17
AJ17
AH17
AG17
AK18
AJ18
AL19
AK19
AK20
AJ20
AH20
AG20
AK21
AJ21
AL22
AK22
AK23
AJ23
AH23
AG23
AK24
AJ24
AL25
AK25

AJ11

AL13
AK13
AK12

AJ26
AK26

AJ12
AP29

+1.8VSDGPU_AON

UV2
NL17SZ08DFT2G_SC70-5

5

VGA@

VCC

4

OUT Y

GND

3

N18P-G0_FCBGA960~D

@

RV16 100K_0201_5%VGA@

CV200 0.1U_0201_10V6K

PEG_CTX_C_GRX_P0<9>
PEG_CTX_C_GRX_N0<9>
PEG_CTX_C_GRX_P1<9>
PEG_CTX_C_GRX_N1<9>
PEG_CTX_C_GRX_P2<9>
PEG_CTX_C_GRX_N2<9>
PEG_CTX_C_GRX_P3<9>
PEG_CTX_C_GRX_N3<9>
PEG_CTX_C_GRX_P4<9>
PEG_CTX_C_GRX_N4<9>
PEG_CTX_C_GRX_P5<9>

CLK_PEG_VGA<15>
CLK_PEG_VGA#<15>

PEG_CTX_C_GRX_N5<9>
PEG_CTX_C_GRX_P6<9>
PEG_CTX_C_GRX_N6<9>
PEG_CTX_C_GRX_P7<9>
PEG_CTX_C_GRX_N7<9>
PEG_CTX_C_GRX_P8<9>
PEG_CTX_C_GRX_N8<9>
PEG_CTX_C_GRX_P9<9>
PEG_CTX_C_GRX_N9<9>
PEG_CTX_C_GRX_P10<9>
PEG_CTX_C_GRX_N10<9>
PEG_CTX_C_GRX_P11<9>
PEG_CTX_C_GRX_N11<9>
PEG_CTX_C_GRX_P12<9>
PEG_CTX_C_GRX_N12<9>
PEG_CTX_C_GRX_P13<9>
PEG_CTX_C_GRX_N13<9>
PEG_CTX_C_GRX_P14<9>
PEG_CTX_C_GRX_N14<9>
PEG_CTX_C_GRX_P15<9>
PEG_CTX_C_GRX_N15<9>

PEG_CRX_C_GTX_P0<9>
PEG_CRX_C_GTX_N0<9>
PEG_CRX_C_GTX_P1<9>
PEG_CRX_C_GTX_N1<9>
PEG_CRX_C_GTX_P2<9>
PEG_CRX_C_GTX_N2<9>
PEG_CRX_C_GTX_P3<9>
PEG_CRX_C_GTX_N3<9>
PEG_CRX_C_GTX_P4<9>
PEG_CRX_C_GTX_N4<9>
PEG_CRX_C_GTX_P5<9>
PEG_CRX_C_GTX_N5<9>
PEG_CRX_C_GTX_P6<9>
PEG_CRX_C_GTX_N6<9>
PEG_CRX_C_GTX_P7<9>
PEG_CRX_C_GTX_N7<9>
PEG_CRX_C_GTX_P8<9>
PEG_CRX_C_GTX_N8<9>
PEG_CRX_C_GTX_P9<9>
PEG_CRX_C_GTX_N9<9>
PEG_CRX_C_GTX_P10<9>
PEG_CRX_C_GTX_N10<9>
PEG_CRX_C_GTX_P11<9>
PEG_CRX_C_GTX_N11<9>
PEG_CRX_C_GTX_P12<9>
PEG_CRX_C_GTX_N12<9>
PEG_CRX_C_GTX_P13<9>
PEG_CRX_C_GTX_N13<9>
PEG_CRX_C_GTX_P14<9>
PEG_CRX_C_GTX_N14<9>
PEG_CRX_C_GTX_P15<9>
PEG_CRX_C_GTX_N15<9>

RV7 10K_0201_5%VGA@

PLT_RST#

DGPU_HOLD_RST#

VGA_CLKREQ#_R

1 2

PLTRST_VGA#_1V8

1 2

RV10

VGA@

2.49K_0402_1%

No support S0ix

1 1

2 2

+1.8VSDGPU_AON

3 3

PLT_RST#<16,58,66>

DGPU_HOLD_RST#<19>

PEX_RX0
PEX_RX0_N
PEX_RX1
PEX_RX1_N
PEX_RX2
PEX_RX2_N
PEX_RX3
PEX_RX3_N
PEX_RX4
PEX_RX4_N
PEX_RX5
PEX_RX5_N
PEX_RX6
PEX_RX6_N
PEX_RX7
PEX_RX7_N
PEX_RX8
PEX_RX8_N
PEX_RX9
PEX_RX9_N
PEX_RX10
PEX_RX10_N
PEX_RX11
PEX_RX11_N
PEX_RX12
PEX_RX12_N
PEX_RX13
PEX_RX13_N
PEX_RX14
PEX_RX14_N
PEX_RX15
PEX_RX15_N

PEX_TX0
PEX_TX0_N
PEX_TX1
PEX_TX1_N
PEX_TX2
PEX_TX2_N
PEX_TX3
PEX_TX3_N
PEX_TX4
PEX_TX4_N
PEX_TX5
PEX_TX5_N
PEX_TX6
PEX_TX6_N
PEX_TX7
PEX_TX7_N
PEX_TX8
PEX_TX8_N
PEX_TX9
PEX_TX9_N
PEX_TX10
PEX_TX10_N
PEX_TX11
PEX_TX11_N
PEX_TX12
PEX_TX12_N
PEX_TX13
PEX_TX13_N
PEX_TX14
PEX_TX14_N
PEX_TX15
PEX_TX15_N

PEX_WAKE#

PEX_REFCLK
PEX_REFCLK_N
PEX_CLKREQ_N

NC
NC

PEX_RST_N
PEX_TERMP

1 2

1 2

VGA@

Part 1 of 7

OVR-M

Thermal Sensor

PCI EXPRESS

+1.8VSDGPU_AON

12

RV100
10K_0201_5%

PLTRST_VGA#_1V8

GPIO

RESI2C

GPCPLL_AVDD

XSN_PLLVDD

CLK

XTAL_OUTBUFF

EXT_REFCLK_FL

@

ADC_IN_N

I2CC_SDA

SP_PLLVDD

VID_PLLVDD

XTAL_OUT

GC6 2.0 function

+3VS

12

RV113

QV8A

VGA@

5

10K_0201_5%

GC6_FB_EN3V3

34

D

G

S

PJT138KA 2N SOT363-6

A

VGA@

4 4

GC6_FB_EN1V8

PJT138KA 2N SOT363-6

RV111

VGA@

100K_0201_5%

2

QV8B

VGA@

12

61

D

G

S

GC6_FB_EN3V3

1VSDGPU_PG<94>

GC6_FB_EN3V3 <19>

DV3

2

3

BAV70W_SOT323-3

VGA@

1

12

P6

GPIO0

M3

GPIO1

L6

GPIO2

P5

GPIO3

P7

GPIO4

L7

GPIO5

M7

GPIO6

N8

GPIO7

L3

GPIO8

M2

GPIO9

L1

GPIO10

M5

GPIO11

N3

GPIO12

M4

GPIO13

N4

GPIO14

P2

GPIO15

R8

GPIO16

M6

GPIO17

R1

GPIO18

P3

GPIO19

P4

GPIO20

P1

GPIO21

P8

GPIO22

T8

GPIO23

L2

GPIO24

R4

GPIO25

R5

GPIO26

U3

GPIO27

AN9

ADC_IN

AM9

AG10

TS_AVDD

AK9

RES

AL10

RES

AL9

RES

AP8

RES

AP9

TS_VREF

R7

I2CB_SCL

R6

I2CB_SDA

R2

I2CC_SCL

R3

T4

I2CS_SCL

T3

I2CS_SDA

H26

AD8

AE8

AD7

H3

XTAL_IN

H2

J4
H1

1.35VSDGPU_EN <37,93>

RV12
100K_0201_5%

VGA@

B

GC6_FB_EN1V8
GPU_EVENT#_1

1.8VSDGPU_MAIN_EN
FRM_LCK#

VGA_ALERT#

ACIN_BUF

SYS_PEX_RST_MON#

GPU_PEX_RST_HOLD#

HDMI_HPD_GPU#

TS_AVDD

RV86 2K_0402_5%VGA@
RV85 2K_0402_5%VGA@

VGA_I2CC_SCL
VGA_I2CC_SDA

VGA_I2CS_SCL
VGA_I2CS_SDA

XTALIN
XTALOUT

XTAL_OUTBUFF
XTAL_SSIN

B

NVVDD_VID <95>

NVVDD_PSI <95>

VRAM_VDD_CTL <93>

VRAM_VREF_CTL <32,33>

DV2

VGA@

RB751S40T1G_SOD523-2

GPIO22_OC_WARN# <36>

FBVDDQ_PSI <93 >
GPIO26_FP_FUSE <37>

ADC_IN_P <36>
ADC_IN_N <36>

1 2

RV385 0_0402_5%N18P@

1 2

CV377 1U_0201_6.3V6M

N18P@

unused pin PH 2K to 1V8AON

1 2
1 2

+GPU_PLLVDD

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

CV6

CV195

CV5

1

1

1

VGA@

VGA@

VGA@

2

2

2

Near

Near

Near

AD8

AD7

H26

1 2

RV9 100K_0201_5%VGA@

1 2

RV11 10K_0201_5%VGA@

DV8

12

+1.8VSDGPU_AON

+1.8VSDGPU_AON

1U_0201_6.3V6M

CV3

1

VGA@

2

Near
AE8

VGA_OVERT#<29>

VGA@

12

GPU_EVENT# <19>

RB751S40T1G_SOD523-2

DGPU_AC_DETECT <19,58,83>

SM01000JX00
3000ma 33ohm@100mhz DCR 0.04

LV1

1

CV42

VGA@

2

TAI-TECH HCB1608KF-330T30

22U_0603_6.3V6M

1

CV4

VGA@

2

Near
GPU

VGA_OVERT#

PJT138KA 2N SOT363-6

4.7U_0402_6.3V6M

VGA@

1 2

SM01000JX00

+1.8VSDGPU_MAIN

2

QV1B

VGA@

12

61

D

G

S

C

+1.8VSDGPU_MAIN

RV131
100K_0201_5%

VGA@

C

G

5

HDMI_HPD_PCH<16,40>

1.35VSDGPU_PG<93>

1.8VSDGPU_MAIN_EN

PU at EC side

34

D

QV1A

S

PJT138KA 2N SOT363-6

VGA@

QV13A

PJT138KA 2N SOT363-6

VGA_I2CC_SCL

PJT138KA 2N SOT363-6

VGA_I2CC_SDA

0.1U_0201_10V6K

PLTRST_VGA#_1V8

NL17SZ08DFT2G_SC70-5

NL17SZ08DFT2G_SC70-5

1VSDGPU_PG

PJT138KA 2N SOT363-6

GPU_OVERT# <58>

D

VGA_OVERT#
VGA_ALERT#
FRM_LCK#
ACIN_BUF
GPU_EVENT#_1

1.8VSDGPU_MAIN_EN
NVVDD_PSI

SYS_PEX_RST_MON#
GPU_PEX_RST_HOLD#

FBVDDQ_PSI
GPIO22_OC_WARN#

VGA_I2CS_SDA
VGA_I2CS_SCL

VGA_I2CC_SDA
VGA_I2CC_SCL

NVVDD_PSI

VRAM_VREF_CTL
GC6_FB_EN1V8

GPU_PEX_RST_HOLD#

+1.8VSDGPU_MAIN

N18P@

5

34

SGD

QV13B

N18P@

2

G

61

S

D

+1.8VSDGPU_AON +1.8VSDGPU_AON

VGA@

CG340

12

5

1

IN B

VCC

OUT Y

2

IN A

GND

VGA@

3

UG28

+1.8VSDGPU_AON

UV11

VGA@

5

1

IN B

VCC

OUT Y

2

IN A

GND

3

+3VS

12

RV106
100K_0201_5%

VGA@

5

61

D

G

2

QV7A

S

QV7B

VGA@

VGA@

GPU_OVERT#

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECT RONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECT RONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECT RONICS, INC.

VGA_I2CC_SCL_PWR <95>

VGA_I2CC_SDA_PWR <95>

XTALOUT

12

VGA@

RG180
10K_0201_5%

HDMI_HPD_GPU#

61

D

G

2

4

4

12

34

G

QV5B

S

PJT138KA 2N SOT363-6

1

VGA@

@

CV201

0.1U_0201_10V6K

2

+1.8VSDGPU_AON

RV83

@

10K_0201_5%

1 2

ALL_GPWRGD

1

VGA@

CV226

0.1U_0201_10V6K

2

VGA@

RV108
10K_0201_5%

D

S

PJT138KA 2N SOT363-6

1 2

DV7

RB751S40T1G_SOD523-2

VGA@

2017/10/30 2018/10/30

2017/10/30 2018/10/30

2017/10/30 2018/10/30

PU at PCH side

34

QV5A

D

G

5

PJT138KA 2N SOT363-6

S

VGA@

VGA_CLKREQ#_R

1.8VSDGPU_MAIN_EN3V3 <37>

+3VS

UV10

5

NL17SZ08DFT2G_SC70-5

1

IN B

VCC
OUT Y

2

IN A

GND

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

D

Deciphered Date

Deciphered Date

Deciphered Date

RV80
470_0402_1%

18P_0402_50V8J

VGA_CLKREQ# <15>

VGA@

4

QV2A

PJT138KA 2N SOT363-6

VGA_I2CS_SCL

PJT138KA 2N SOT363-6

VGA_I2CS_SDA

VGA@

XTALOUT_R

12

CV1

VGA@

@

DV4

RB751S40T1G_SOD523-2

RV105
12K_0402_1%

VGA@

VGA@

1 2

DV5

RB751S40T1G_SOD523-2

1 2

RV103

28.7K_0402_1%

VGA@

RV327 10K_0201_5%VGA@
RV328 10K_0201_5%VGA@
RV329 10K_0201_5%VGA@
RV330 10K_0201_5%VGA@
RV331 10K_0201_5%VGA@
RV1 10K_0201_5%VGA@
RV4 10K_0201_5%VGA@

RV332 10K_0201_5%N17P @
RV82 10K_0201_5%N17P@

RV335 10K_0201_5%N18P @
RV386 10K_0201_5%N18P @

1 2

RV2 1.8K_0402_1%VGA@

1 2

RV3 1.8K_0402_1%VGA@

1 2

RV5 2K_0402_5%VGA@

1 2

RV6 2K_0402_5%VGA@

RV398 10K_0201_5%@

RV333 100K_0201_5%VGA@
RV334 10K_0201_5%VGA@

RV396 100K_0201_5%N18P@

+1.8VSDGPU_MAIN

VGA@

5

34

SGD

QV2B

VGA@

2

G

61

S

D

27MHZ_10PF_XRCGB27M000F2P18R0
XV1

1

1

1

VGA@

2

Crystals must have a max ESR of 80 ohm

12

12

2

CV197

0.22U_0402_16V7K

1

2

CV196

0.22U_0402_16V7K

1

E

+1.8VSDGPU_AON

12
12
12
12
12
12
12

12
12

12
12

12

12
12

12

PCH_SML1CLK <18,58,66>

PCH_SML1DATA <18,58,66>

3

XTALIN

3

NC

NC

2

VGA@

VGA@

Title

Title

Title

Size

Size

Size

Custom

Custom

Custom

Date : Shee t o f

Date : Shee t o f

Date : Shee t o f

1

4

GPUCORE_EN < 37>

NVVDD1_EN <37,95>DGPU_PWR_EN <19,37>

1VSDGPU_EN <94>

CV2

VGA@

18P_0402_50V8J

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

N17P PEG 1/7

N17P PEG 1/7

Document Number Re v

Document Number Re v

Document Number Re v

EH5VF M/B LA-H501P

EH5VF M/B LA-H501P

EH5VF M/B LA-H501P

N17P PEG 1/7

E

1A

1A

27 101Friday, February 22, 2019

27 101Friday, February 22, 2019

27 101Friday, February 22, 2019

1A

A

Vinafix

FBA_D[63..0]< 32>

1 1

2 2

FBA_DBI[7..0]<32>

FBA_EDC[7..0]<32>

3 3

FBA_D0
FBA_D1
FBA_D2
FBA_D3
FBA_D4
FBA_D5
FBA_D6
FBA_D7
FBA_D8
FBA_D9
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31
FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63

FBA_DBI0
FBA_DBI1
FBA_DBI2
FBA_DBI3
FBA_DBI4
FBA_DBI5
FBA_DBI6
FBA_DBI7

FBA_EDC0
FBA_EDC1
FBA_EDC2
FBA_EDC3
FBA_EDC4
FBA_EDC5
FBA_EDC6
FBA_EDC7

UV1B

L28

FBA_D0

M29

FBA_D1

L29

FBA_D2

M28

FBA_D3

N31

FBA_D4

P29

FBA_D5

R29

FBA_D6

P28

FBA_D7

J28

FBA_D8

H29

FBA_D9

J29

FBA_D10

H28

FBA_D11

G29

FBA_D12

E31

FBA_D13

E32

FBA_D14

F30

FBA_D15

C34

FBA_D16

D32

FBA_D17

B33

FBA_D18

C33

FBA_D19

F33

FBA_D20

F32

FBA_D21

H33

FBA_D22

H32

FBA_D23

P34

FBA_D24

P32

FBA_D25

P31

FBA_D26

P33

FBA_D27

L31

FBA_D28

L34

FBA_D29

L32

FBA_D30

L33

FBA_D31

AG28

FBA_D32

AF29

FBA_D33

AG29

FBA_D34

AF28

FBA_D35

AD30

FBA_D36

AD29

FBA_D37

AC29

FBA_D38

AD28

FBA_D39

AJ29

FBA_D40

AK29

FBA_D41

AJ30

FBA_D42

AK28

FBA_D43

AM29

FBA_D44

AM31

FBA_D45

AN29

FBA_D46

AM30

FBA_D47

AN31

FBA_D48

AN32

FBA_D49

AP30

FBA_D50

AP32

FBA_D51

AM33

FBA_D52

AL31

FBA_D53

AK33

FBA_D54

AK32

FBA_D55

AD34

FBA_D56

AD32

FBA_D57

AC30

FBA_D58

AD33

FBA_D59

AF31

FBA_D60

AG34

FBA_D61

AG32

FBA_D62

AG33

FBA_D63

P30

FBA_DQM0

F31

FBA_DQM1

F34

FBA_DQM2

M32

FBA_DQM3

AD31

FBA_DQM4

AL29

FBA_DQM5

AM32

FBA_DQM6

AF34

FBA_DQM7

M31

FBA_DQS_WP0

G31

FBA_DQS_WP1

E33

FBA_DQS_WP2

M33

FBA_DQS_WP3

AE31

FBA_DQS_WP4

AK30

FBA_DQS_WP5

AN33

FBA_DQS_WP6

AF33

FBA_DQS_WP7

M30

RES

H30

RES

E34

RES

M34

RES

AF30

RES

AK31

RES

AM34

RES

AF32

RES

N18P-G0_FCBGA96 0~D

@

Part 2 of 7

MEMORY INTERFACE

FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8

FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
FBA_CMD29
FBA_CMD30
FBA_CMD31
FBA_CMD32
FBA_CMD33
FBA_CMD34
FBA_CMD35

FBA_CLK0

FBA_CLK0_N

FBA_CLK1

FBA_CLK1_N

FBA_WCK01

FBA_WCK01_N

FBA_WCK23

FBA_WCK23_N

FBA_WCK45

FBA_WCK45_N

FBA_WCK67

FBA_WCK67_N

A

FBA_WCKB01

FBA_WCKB01_N

FBA_WCKB23

FBA_WCKB23_N

FBA_WCKB45

FBA_WCKB45_N

FBA_WCKB67

FBA_WCKB67_N

FB_REFPLL_AVDD

FBA_PLL_AVDD

FB_VREF

U30
T31
U29
R34
R33
U32
U33
U28
V28
V29
V30
U34
U31
V34
V33
Y32
AA31
AA29
AA28
AC34
AC33
AA32
AA33
Y28
Y29
W31
Y30
AA34
Y31
Y34
Y33
V31
R28
AC28
R32
AC32

R30
R31
AB31
AC31

K31
L30
H34
J34
AG30
AG31
AJ34
AK34

J30
J31
J32
J33
AH31
AJ31
AJ32
AJ33

K27

U27

H31

B

FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
FBA_CMD29
FBA_CMD30
FBA_CMD31

+FB_PLLAVDD

FB_VREF

FBA_CMD[31..0] <32> FBB_D[63..0]< 33>

FBA_CLKA0 <32>
FBA_CLKA0# <32>
FBA_CLKA1 <32>
FBA_CLKA1# <32>

FBA_WCK01 <3 2>
FBA_WCK01# < 32>
FBA_WCK23 <3 2>
FBA_WCK23# < 32>
FBA_WCK45 <3 2>
FBA_WCK45# < 32>
FBA_WCK67 <3 2>
FBA_WCK67# < 32>

+1.8VSDGPU_MAIN

1 2

LV3

1U_0201_6.3V6M

1

2

Near
U27

FBA_CMD14

FBA_CMD30

FBA_CMD13

FBA_CMD29

1U_0201_6.3V6M

CV10

CV9

1

1

VGA@

VGA@

2

2

Near
K27

12

VGA@

RV87 10K_0402_5%

12

VGA@

RV88 10K_0402_5%

12

VGA@

RV89 10K_0402_5%

12

VGA@

RV90 10K_0402_5%

22U_0603_6.3V6M

CV11

1

VGA@

2

+1.35VSDGPU

4.7U_0402_6.3V6M

TAI-TECH HCB160 8KF-330T30

CV379

SM01000JX00

SM01000J X00

VGA@

3000ma 33ohm@100mhz DCR 0.04

VGA@

FB_VREF

C

UV1C

FBB_D0

G9

FBB_D1

E9

FBB_D2

G8

FBB_D3

F9

FBB_D4

F11

FBB_D5

G11

FBB_D6

F12

FBB_D7

G12

FBB_D8

G6

FBB_D9

F5

FBB_D10

E6

FBB_D11

F6

FBB_D12

F4

FBB_D13

G4

FBB_D14

E2

FBB_D15

F3

FBB_D16

C2

FBB_D17

D4

FBB_D18

D3

FBB_D19

C1

FBB_D20

B3

FBB_D21

C4

FBB_D22

B5

FBB_D23

C5

FBB_D24

A11

FBB_D25

C11

FBB_D26

D11

FBB_D27

B11

FBB_D28

D8

FBB_D29

A8

FBB_D30

C8

FBB_D31

B8

FBB_D32

F24

FBB_D33

G23

FBB_D34

E24

FBB_D35

G24

FBB_D36

D21

FBB_D37

E21

FBB_D38

G21

FBB_D39

F21

FBB_D40

G27

FBB_D41

D27

FBB_D42

G26

FBB_D43

E27

FBB_D44

E29

FBB_D45

F29

FBB_D46

E30

FBB_D47

D30

FBB_D48

A32

FBB_D49

C31

FBB_D50

C32

FBB_D51

B32

FBB_D52

D29

FBB_D53

A29

FBB_D54

C29

FBB_D55

B29

FBB_D56

B21

FBB_D57

C23

FBB_D58

A21

FBB_D59

C21

FBB_D60

B24

FBB_D61

C24

FBB_D62

B26

FBB_D63

FBB_DBI[7..0]<33>

FBB_EDC[7..0]<33>

CV378

3.9P_0402_50V8C

RV393

49.9_0402_1%

12

1

N18P@

N18P@

2

FBB_DBI0
FBB_DBI1
FBB_DBI2
FBB_DBI3
FBB_DBI4
FBB_DBI5
FBB_DBI6
FBB_DBI7

FBB_EDC0
FBB_EDC1
FBB_EDC2
FBB_EDC3
FBB_EDC4
FBB_EDC5
FBB_EDC6
FBB_EDC7

C26

E11

E3
A3

C9
F23
F27
C30
A24

D10

D5

C3

B9
E23
E28
B30
A23

D9

E4

B2

A9
D22
D28
A30
B23

CKE

signal

RST
signal

Part 3 of 7

FBB_D0
FBB_D1
FBB_D2
FBB_D3
FBB_D4
FBB_D5
FBB_D6
FBB_D7
FBB_D8
FBB_D9
FBB_D10
FBB_D11
FBB_D12
FBB_D13
FBB_D14
FBB_D15
FBB_D16
FBB_D17
FBB_D18
FBB_D19
FBB_D20
FBB_D21
FBB_D22
FBB_D23
FBB_D24
FBB_D25
FBB_D26
FBB_D27
FBB_D28
FBB_D29
FBB_D30
FBB_D31
FBB_D32
FBB_D33
FBB_D34
FBB_D35
FBB_D36
FBB_D37
FBB_D38
FBB_D39
FBB_D40
FBB_D41
FBB_D42
FBB_D43
FBB_D44
FBB_D45
FBB_D46
FBB_D47
FBB_D48
FBB_D49
FBB_D50
FBB_D51
FBB_D52
FBB_D53
FBB_D54
FBB_D55
FBB_D56
FBB_D57
FBB_D58
FBB_D59
FBB_D60
FBB_D61
FBB_D62
FBB_D63

FBB_DQM0
FBB_DQM1
FBB_DQM2
FBB_DQM3
FBB_DQM4
FBB_DQM5
FBB_DQM6
FBB_DQM7

FBB_DQS_WP0
FBB_DQS_WP1
FBB_DQS_WP2
FBB_DQS_WP3
FBB_DQS_WP4
FBB_DQS_WP5
FBB_DQS_WP6
FBB_DQS_WP7

RES
RES
RES
RES
RES
RES
RES
RES

N18P-G0_FCBGA96 0~D

@

FBB_CMD14

FBB_CMD30

FBB_CMD13

FBB_CMD29

D

FBB_CMD0
FBB_CMD1
FBB_CMD2
FBB_CMD3
FBB_CMD4
FBB_CMD5
FBB_CMD6
FBB_CMD7
FBB_CMD8

FBB_CMD9
FBB_CMD10
FBB_CMD11
FBB_CMD12
FBB_CMD13
FBB_CMD14
FBB_CMD15
FBB_CMD16
FBB_CMD17
FBB_CMD18
FBB_CMD19
FBB_CMD20
FBB_CMD21
FBB_CMD22
FBB_CMD23
FBB_CMD24
FBB_CMD25
FBB_CMD26
FBB_CMD27
FBB_CMD28
FBB_CMD29
FBB_CMD30
FBB_CMD31
FBB_CMD32
FBB_CMD33
FBB_CMD34
FBB_CMD35

FBB_CLK0

FBB_CLK0_N

MEMORY INTERFACE B

FBB_CLK1

FBB_CLK1_N

FBB_WCK01

FBB_WCK01_N

FBB_WCK23

FBB_WCK23_N

FBB_WCK45

FBB_WCK45_N

FBB_WCK67

FBB_WCK67_N

FBB_WCKB01

FBB_WCKB01_N

FBB_WCKB23

FBB_WCKB23_N

FBB_WCKB45

FBB_WCKB45_N

FBB_WCKB67

FBB_WCKB67_N

FBB_PLL_AVDD

12

VGA@

RV91 10K_0402_5%

12

VGA@

RV92 10K_0402_5%

12

VGA@

RV93 10K_0402_5%

12

VGA@

RV94 10K_0402_5%

D13
E14
F14
A12
B12
C14
B14
G15
F15
E15
D15
A14
D14
A15
B15
C17
D18
E18
F18
A20
B20
C18
B18
G18
G17
F17
D16
A18
D17
A17
B17
E17
G14
G20
C12
C20

D12
E12
E20
F20

F8
E8
A5
A6
D24
D25
B27
C27

D6
D7
C6
B6
F26
E26
A26
A27

H17

+1.35VSDGPU

FBB_CMD0
FBB_CMD1
FBB_CMD2
FBB_CMD3
FBB_CMD4
FBB_CMD5
FBB_CMD6
FBB_CMD7
FBB_CMD8
FBB_CMD9
FBB_CMD10
FBB_CMD11
FBB_CMD12
FBB_CMD13
FBB_CMD14
FBB_CMD15
FBB_CMD16
FBB_CMD17
FBB_CMD18
FBB_CMD19
FBB_CMD20
FBB_CMD21
FBB_CMD22
FBB_CMD23
FBB_CMD24
FBB_CMD25
FBB_CMD26
FBB_CMD27
FBB_CMD28
FBB_CMD29
FBB_CMD30
FBB_CMD31

Near
H17

1

2

FBB_CLKA0 <33>
FBB_CLKA0# <33>
FBB_CLKA1 <33>
FBB_CLKA1# <33>

FBB_WCK01 <3 3>
FBB_WCK01 # <33 >
FBB_WCK23 <3 3>
FBB_WCK23 # <33 >
FBB_WCK45 <3 3>
FBB_WCK45 # <33 >
FBB_WCK67 <3 3>
FBB_WCK67 # <33 >

+FB_PLLAVDD

1U_0201_6.3V6M

CV7

1

VGA@

2

FBB_CMD[31..0] <33>

4.7U_0402_6.3V6M
CV12

VGA@

E

GDDR5 Mode H Mapping

Addr ess

CMD0

CMD1

CMD2

CMD3

CMD4

CMD5

CMD6

CMD7

CMD8

CMD9

CMD10

CMD11

CMD12

CMD13

CMD14

CMD15

CMD16

CMD17

CMD18

CMD19

CMD20

CMD21

CMD22

CMD23

CMD24

CMD25

CMD26

CMD27

CMD28

CMD29

CMD30

CMD31

DATA Bus

0..31 32..63

CS#

A3_BA 3

A2_BA 0

A4_BA 2

A5_BA 1

WE#

A7_A8

A6_A1 1

ABI#

A12_RF U

A0_A1 0

A1_A9

RAS#

RST#

CKE#

CAS#

CS#

A3_BA 3

A2_BA 0

A4_BA 2

A5_BA 1

WE#

A7_A8

A6_A1 1

ABI#

A12_RF U

A0_A1 0

A1_A9

RAS#

RST#

CKE#

CAS#

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2017/10/30 2018/10/30

2017/10/30 2018/10/30

2017/10/30 2018/10/30

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Nu mber R ev

Size Document Nu mber R ev

Size Document Nu mber R ev

Custom

Custom

Custom

Date : Sheet of

Date : Sheet of

D

Date : Sheet of

Compal Electronics, Inc.

N17P VRAM 2/7

N17P VRAM 2/7

N17P VRAM 2/7

EH5VF M/B LA-H501P

EH5VF M/B LA-H501P

EH5VF M/B LA-H501P

E

1A

1A

28 101Friday, February 22, 2019

28 101Friday, February 22, 2019

28 101Friday, February 22, 2019

1A

A

1 1

GPU_DP2_P0< 40>
GPU_DP2_N0<40>
GPU_DP2_P1< 40>

HDMI

2.0

2 2

GPU_DP2_N1<40>
GPU_DP2_P2< 40>
GPU_DP2_N2<40>
GPU_DP2_P3< 40>
GPU_DP2_N3<40>

GPU_DP2_CT RL_CLK<40>
GPU_DP2_CT RL_DAT<40>

UV1D

AM6
AN6
AP3
AN3
AN5
AM5

AL6

AK6

AJ6

AH6

AJ9
AH9
AP6
AP5
AM7

AL7
AN8
AM8
AK8

AL8

AK1

AJ1

AJ3

AJ2
AH3
AH4
AG5
AG4

AM1
AM2
AM3
AM4

AL3

AL4
AK4
AK5

AD2
AD3
AD1
AC1
AC2
AC3
AC4
AC5

AE3
AE4

AF4

AF5
AD4
AD5
AG1

AF1

AG3
AG2

AK3
AK2

AB3
AB4

AF3

AF2

IFPA_L3
IFPA_L3_N
IFPA_L2
IFPA_L2_N
IFPA_L1
IFPA_L1_N
IFPA_L0
IFPA_L0_N
IFPA_AUX_SCL
IFPA_AUX_SDA_N

IFPB_L3
IFPB_L3_N
IFPB_L2
IFPB_L2_N
IFPB_L1
IFPB_L1_N
IFPB_L0
IFPB_L0_N
IFPB_AUX_SCL
IFPB_AUX_SDA_N

IFPC_L0
IFPC_L0_N
IFPC_L1
IFPC_L1_N
IFPC_L2
IFPC_L2_N
IFPC_L3
IFPC_L3_N

IFPD_L0
IFPD_L0_N
IFPD_L1
IFPD_L1_N
IFPD_L2
IFPD_L2_N
IFPD_L3
IFPD_L3_N

IFPE_L0
IFPE_L0_N
IFPE_L1
IFPE_L1_N
IFPE_L2
IFPE_L2_N
IFPE_L3
IFPE_L3_N

NC
NC
NC
NC
NC
NC
NC
NC

IFPC_AUX_SCL
IFPC_AUX_SDA_N

IFPD_AUX_SCL
IFPD_AUX_SDA_N

IFPE_AUX_SCL
IFPE_AUX_SDA_N

NC
NC

Part 4 of 7

TMDS

NC

VDD_SENSE

GND_SENSE

TEST

NVJTAG_SEL

JTAG_TCK

JTAG_TDI
JTAG_TDO
JTAG_TMS

JTAG_TRST_N

SERIAL

ROM_CS_N

ROM_SCLK

GENERAL

BUFRST_N

THERMDP
THERMDN

ROM_SI

ROM_SO

OVERT

STRAP0
STRAP1
STRAP2
STRAP3
STRAP4
STRAP5

B

+1.8VSDGPU_MAIN

AC6

NC

AJ28

NC

AJ4

NC

AJ5

NC

AL11

NC

C15

NC

D19

NC

D20

NC

D23

NC

D26

NC

V32

NC

L4

L5

NVVDD1_VCC_SENSE <95>

NVVDD1_VSS_SENSE < 95>

STRAP0
STRAP1
STRAP2
STRAP3
STRAP4
STRAP5

C

+1.8VSDGPU_AON

RV26
100K_0402_ 5%

@

1 2

RV34
100K_0402_ 5%

@

1 2

RV27
100K_0402_ 5%

@

1 2

RV35
100K_0402_ 5%

@

1 2

MULTI LEVEL
STRAPS

strap3strap2strap1st rap0 strap5

RV28
100K_0201_ 5%

@

1 2

RV36
100K_0201_ 5%

@

1 2

RV29
100K_0201_ 5%

VGA@

1 2

RV37
100K_0201_ 5%

@

1 2

strap4

RV30
100K_0201_ 5%

@

1 2

RV38
100K_0201_ 5%

VGA@

1 2

D

RV78
100K_0402_ 5%

@

1 2

RV79
100K_0402_ 5%

VGA@

1 2

RV31
100K_0402_ 5%

N17P@

1 2

RV39
100K_0402_ 5%

N18P@

1 2

RV32
100K_0402_ 5%

N17P@

1 2

RV40
10K_0402_5 %

N18P@

1 2

RV33
100K_0201_ 5%

N17P@

1 2

ROM_SI
ROM_SO
ROM_SCLK

RV41
100K_0201_ 5%

N18P@

1 2

E

X76 BOM

RV336
10K_0402_5 %

ROM_CS_R#
ROM_SO_R

+1.8VSDGPU_AON

12

N18P@

UV49

1

CS#

2

DO(IO1)

3

WP#(IO2)

4

GND

W25Q80EW SSIG_SO8

N18P@

SA00009QP00

VCC

HOLD#(IO3)

DI(IO0)

CLK

+1.8VSDGPU_AON

8
7

ROM_SCLK_R

6

ROM_SI_R

5

1

CV355

N18P@

0.1U_0201_ 10V6K

2

N18P@

RV339
33_0402_5 %

1 2
1 2

RV340
33_0402_5 %

N18P@

ROM_SCLK
ROM_SI

AK11

AM10
AM11
AP12
AP11
AN11

H6
H4
H5
H7

TESTMODE

ROM_CS#
ROM_SCLK
ROM_SI
ROM_SO

JTAG_TCK_VGA
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_RST

1 2

RV42 10K_0402_5%VGA@

TV5@
TV6@
TV7@
TV8@

1 2

RV43 10K_0402_5%VGA@

ROM_CS#
ROM_SO

N18P@

RV337
33_0402_5 %

1 2
1 2

RV338
0_0402_5%

@

DGPU VBIOS ROM 8Mb

GPU_BUFRST#

E1

M1

J2

STRAP0

J7

STRAP1

J6

STRAP2

J5

STRAP3

J3

STRAP4

J1

STRAP5

K3
K4

TV9@

VGA_OVERT# <27>

3 3

4 4

A

N18P-G0_FCBGA96 0~D

@

*

*

*

*

SMB_ATL_ADDR

LOW

High

DEVID_SEL

LOW

High

VGA_DEVICE

LOW

High

PCIE_CFG

LOW

High

Orig. Device ID

Support G-Sync GPUID

Single GPU

Dual GPU

3D Device

VGA Device

Normal signal swing

Reduce the signal amplitude

B

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2017/10/30 2018/10/30

2017/10/30 2018/10/30

2017/10/30 2018/10/30

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Nu mber R ev

Size Document Nu mber R ev

Size Document Nu mber R ev

Custom

Custom

Custom

Date : Sheet of

Date : Sheet of

Date : Sheet of

Compal Electronics, Inc.

N17P STRAP 3/7

N17P STRAP 3/7

N17P STRAP 3/7

EH5VF M/B LA-H501P

EH5VF M/B LA-H501P

EH5VF M/B LA-H501P

E

29 101Friday, February 22, 2019

29 101Friday, February 22, 2019

29 101Friday, February 22, 2019

1A

1A

1A

A

+1.35VSDGPU

CHA
/6*1uF+2*10 uF

CV395

0.47U_0201_6.3V6K

CV396

0.47U_0201_6.3V6K

1

1

2

2

@

@

1 1

CHB
/6*1uF+2*10 uF

reserve

CV397

0.47U_0201_6.3V6K

CV398

0.47U_0201_6.3V6K

1

1

2

2

@

@

Under
GPU

CV18

1U_0201_6.3V6M

CV19

1U_0201_6.3V6M

CV20

1U_0201_6.3V6M

CV21

1

1

VGA@

VGA@

2

2

CV127

1U_0201_6.3V6M

CV126

1U_0201_6.3V6M

1

1

VGA@

VGA@

2

2

1U_0201_6.3V6M

1

1

VGA@

VGA@

2

2

CV129

1U_0201_6.3V6M

CV128

1U_0201_6.3V6M

1

1

VGA@

VGA@

2

2

CV23

1U_0201_6.3V6M

CV22

1U_0201_6.3V6M

1

1

VGA@

VGA@

2

2

CV131

1U_0201_6.3V6M

CV130

1U_0201_6.3V6M

1

1

VGA@

VGA@

2

2

reserve

GPU
/5*22uF+2*1 0uF

10U_0402_6.3V6M

10U_0402_6.3V6M

22U_0603_6.3V6M

CV37

1

2

2 2

10U_0402_6.3V6M

1

2

CV38

1

1

2

VGA@

CV217

@

2

VGA@

10U_0402_6.3V6M

CV218

1

1

2

2

@

CV202

VGA@

Place close to
GPU

22U_0603_6.3V6M

CV219

@

22U_0603_6.3V6M

CV36

1

2

1

2

1

2

VGA@

22U_0603_6.3V6M

CV220

1

2

@

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

CV40

CV39

1

2

VGA@

VGA@

22U_0603_6.3V6M

CV222

CV221

1

2

@

@

near GPU for NV update s pec 1210

FB_VDDQ_SENSE<93>

+1.35VSDGPU

3 3

1 2

RV47 40.2_ 0402_1%VGA@

1 2

RV48 40.2_ 0402_1%VGA@

1 2

N17P@

RV49 60.4_0402_1%

RV49

40.2_0402_1%

SD034402A80

10U_0402_6.3V6M

1

2

10U_0402_6.3V6M

1

2

22U_0603_6.3V6M

CV41

1

2

VGA@

22U_0603_6.3V6M

CV223

1

2

@

FB_VDDQ_SENSE

N18P@

CV24

VGA@

CV132

VGA@

B

1

2

1

2

TV10@

CV26

10U_0402_6.3V6M

VGA@

CV133

10U_0402_6.3V6M

VGA@

+1.35VSDGPU

@

1 2

FB_GND_SENSE

FB_CAL_PD_VDDQ

FB_CAL_PU_GND

FB_CAL_TERM_ GND

RV45
0_0402_5%

UV1E

AA27

FBVDDQ_0

AA30

FBVDDQ_1

AB27

FBVDDQ_2

AB33

FBVDDQ_3

AC27

FBVDDQ_4

AD27

FBVDDQ_5

AE27

FBVDDQ_6

AF27

FBVDDQ_7

AG27

FBVDDQ_8

B13

FBVDDQ_9

B19

FBVDDQ_11

E13

FBVDDQ_12

E19

FBVDDQ_14

H10

FBVDDQ_15

H11

FBVDDQ_16

H12

FBVDDQ_17

H13

FBVDDQ_18

H14

FBVDDQ_19

H18

FBVDDQ_22

H19

FBVDDQ_23

H20

FBVDDQ_24

H21

FBVDDQ_25

H22

FBVDDQ_26

H23

FBVDDQ_27

H24

FBVDDQ_28

H8

FBVDDQ_29

H9

FBVDDQ_30

L27

FBVDDQ_31

M27

FBVDDQ_32

N27

FBVDDQ_33

P27

FBVDDQ_34

R27

FBVDDQ_35

T27

FBVDDQ_36

T30

FBVDDQ_37

T33

FBVDDQ_38

Y27

FBVDDQ_43

B16

FBVDDQ

E16

FBVDDQ

H15

FBVDDQ

H16

FBVDDQ

V27

FBVDDQ

W27

FBVDDQ

W30

FBVDDQ

W33

FBVDDQ

F1

FBVDDQ_SENSE

F2

PROBE_FB_GND

J27

FB_CAL_PD_VDDQ

H27

FB_CAL_PU_GND

H25

FB_CAL_TERM_GND

N18P-G0_FCBGA96 0~D

@

Part 5 of 7

PEX_HVDD_10
PEX_HVDD_11
PEX_HVDD_12
PEX_HVDD_13

PEX_PLL_HVDD

FP_FUSE_SRC

POWER

IFPAB_PLLVDD

IFPCD_PLLVDD

PEX_DVDD_0
PEX_DVDD_1
PEX_DVDD_2
PEX_DVDD_3
PEX_DVDD_4
PEX_DVDD_5

PEX_HVDD_0
PEX_HVDD_1
PEX_HVDD_2
PEX_HVDD_3
PEX_HVDD_4
PEX_HVDD_5
PEX_HVDD_6
PEX_HVDD_7
PEX_HVDD_8
PEX_HVDD_9

1V8_AON
1V8_AON

IFPAB_RSET

IFPCD_RSET

IFPE_PLLVDD

IFPE_RSET

IFP_IOVDD
IFP_IOVDD

IFP_IOVDD
IFP_IOVDD

IFP_IOVDD
IFP_IOVDD

NC

NC
NC

NC
NC

C

AG19
AG21
AG22
AG24
AH21
AH25

AG13
AG15
AG16
AG18
AG25
AH15
AH18
AH26
AH27
AJ27
AK27
AL27
AM28
AN28

AH12

12mils

AG12

+1.8VSDGPU_MAIN

AG26

J8
K8
L8
M8

AH8
AJ8

AF7
AF8

RG38 1K_ 0402_1%

VGA@

AB8
AD6

AG8
AG9

AF6
AG6

AC7
AC8

AG7
AN2

+FP_FUSE_GPU

12

2*22uF+3*10uF+3*4.7u F+6*1uF

Under
GPU

CV134

1U_0201_6.3V6M

CV13

1U_0201_6.3V6M

1

2

1U_0201_6.3V6M

1

1

VGA@

VGA@

2

2

2*22uF+3*10uF+3*4.7u F+7*1uF

CV381

1U_0201_6.3V6M

CV399

1

2

1U_0201_6.3V6M

Under
GPU

VGA@

1

VGA@

2

1

2

1

2

CV380

1U_0201_6.3V6M

1

VGA@

2

+1.8VSDGPU_MAIN

CV43

1U_0201_6 .3V6M

Near
GPU

CV135

1U_0201_6.3V6M

1

VGA@

2

RV394 0_0402_5%N17P@

CV33

1U_0201_6.3V6M

CV14

1

VGA@

VGA@

2

Under
GPU

CV137

1U_0201_6.3V6M

1

1

VGA@

2

2

VGA@

3*4.7uF+5*1uF

CV49

1U_0201_6.3V6M

1

VGA@

2

12

3*4.7uF+9*1uF

D

Near
GPU

CV28

CV29

CV385

1U_0201_6.3V6M

1

VGA@

2

CV136

1U_0201_6.3V6M

1

VGA@

2

CV51

1U_0201_6.3V6M

1

VGA@

2

Near
GPU

Under
GPU

CV214

1U_0201_6.3V6M

1

VGA@

2

4.7U_0402_6.3V6M

CV386

1U_0201_6.3V6M

1

VGA@

2

1U_0201_6.3V6M

CV25

1U_0201_6.3V6M

1

VGA@

2

CV391

1U_0201_6.3V6M

1U_0201_6.3V6M

1

VGA@

2

1U_0201_6.3V6M

1

2

CV16

4.7U_0402_6.3V6M

1

2

CV15

VGA@

CV392

VGA@

1U_0201_6.3V6M

1

2

CV213

VGA@

1

1

2

2

VGA@

VGA@

CV17

4.7U_0402_6.3V6M

CV382

4.7U_0402_6.3V6M

1

1

2

2

VGA@

VGA@

CV393

4.7U_0402_6.3V6M

CV50

4.7U_0402_6.3V6M

1

1

VGA@

VGA@

2

2

0.1U_0201_10V6K

CV52

0.1U_0201_10V6K

1

1

N17P@

2

2

CV216

1U_0201_6.3V6M

CV215

1

VGA@

VGA@

2

Under GPU
1 per ball

CV212

1U_0201_6.3V6M

1

VGA@

2

10U_0402_6.3V6M

CV387

4.7U_0402_6.3V6M

1

2

VGA@

CV32

4.7U_0402_6.3V6M

1

1

2

2

VGA@

CV394

4.7U_0402_6.3V6M

1

VGA@

2

2*4.7uF+1*1uF+2*0. 1uF

CV53

1

N17P@

2

Near
GPU

+GPU_PLLVDD

4.7U_0402_6.3V6M

CV205

4.7U_0402_6.3V6M

1

1

2

2

VGA@

CV388

10U_0402_6.3V6M

1

2

VGA@

VGA@

CV30

10U_0402_6.3V6M

CV27

10U_0402_6.3V6M

1

2

VGA@

VGA@

+1.8VSDGPU_AON

CV54

1U_0201_6.3V6M

N17P@

CV204

4.7U_0402_6.3V6M

1

2

VGA@

1

2

Near
GPU

1

2

CV203

VGA@

CV389

10U_0402_6.3V6M

VGA@

10U_0402_6.3V6M

1

2

CV55

4.7U_0402_6.3V6M

N17P@

CV34

22U_0603_6.3V6M

1

2

VGA@

+1.8VSDGPU_MAIN

22U_0603_6.3V6M

CV383

1

2

VGA@

+1.8VSDGPU_MAIN

+1.0VSDGPU

1

2

CV31

VGA@

+1.0VSDGPU

22U_0603_6.3V6M

1

2

E

CV390

VGA@

CV384

22U_0603_6.3V6M

VGA@

Near
GPU

CV206

1U_0201_6.3V6M

CV207

1U_0201_6.3V6M

CV208

1U_0201_6.3V6M

CV209

1U_0201_6.3V6M

CV210

1U_0201_6.3V6M

CV211

1U_0201_6.3V6M

1

1

VGA@

VGA@

2

2

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2017/10/30 2018/10/30

2017/10/30 2018/10/30

2017/10/30 2018/10/30

Under GPU 1
per ball

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

1

1

VGA@

VGA@

2

2

D

1

1

VGA@

VGA@

2

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Nu mber R ev

Size Document Nu mber R ev

Size Document Nu mber R ev

Custom

Custom

Custom

Date : Sheet of

Date : Sheet of

Date : Sheet of

Compal Electronics, Inc.

N17P POWER 4/7

N17P POWER 4/7

N17P POWER 4/7

EH5VF M/B LA-H501P

EH5VF M/B LA-H501P

EH5VF M/B LA-H501P

E

1A

1A

30 101Friday, February 22, 2019

30 101Friday, February 22, 2019

30 101Friday, February 22, 2019

1A