Acer LA 4921P Diagram
A
1 1
B
C
D
E
Compal Confidential
2 2
KBLG0 Schematics Document
AMD Puma : Griffin Processor with RS780MN/SB700/M92-M2 XT
Tigris : Caspian Processor with RS880M/SB710/M92-M2 XT
3 3
2009-03-11
REV:1.0
4 4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2008/10/06 2009/10/06
2008/10/06 2009/10/06
2008/10/06 2009/10/06
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
B
B
B
Date: Sheet of
Date: Sheet of
D
Date: Sheet of
Compal Electronics, Inc.
Cover Page
Cover Page
Cover Page
KBLG0 LA-4921P
KBLG0 LA-4921P
KBLG0 LA-4921P
E
0.1
0.1
1 57Wednesday, March 11, 2009
1 57Wednesday, March 11, 2009
1 57Wednesday, March 11, 2009
0.1
A
Compal Confidential
Model Name : KBLG0
PowerXpress (MUX)
1 1
2 2
3 3
LCD (LED BL)
page 24
CRT
page 26
HDMI Conn.
page 25
MINI Card x1
WLAN
page 36
LED
page 40
RTC CKT.
page 26
LID SW / MEDIA/B
page 39
MUX
(1:2)
MUX
(1:2)
Atheros AR8131
port 3port 2
VRAM 512MB
64M16 x 4
page 19, 20
DDR2 500MHz
ATI M92-M2 XT
uFCBGA-962
Page 14,15,16,17,18,21,22
LAN(GbE) Card Reader
page 34
RJ45
page 35
B
PCI-Express 1x
option2
JMB385
page 33
port 4
5 in 1 socket
page 33
Tigris
AMD S1G3 Processor
uPGA-638 Package
Caspian
Fan Control
page 44
PCI-Express 16x
Gen2
ATI SB710
uFCBGA-528
C
Puma
AMD S1G2 Processor
uPGA-638 Package
Griffin
Hyper Transport Link
16 x 16
page 4,5,6,7
ATI RS780MN
uFCBGA-528
page 10,11,12,13
A link Express2
ATI SB700
uFCBGA-528
page 27,28,29,30,31
LPC BUS
ENE KB926
page 38
Touch Pad
page 39
Int.KBD
Memory BUS(DDRII)
Dual Channel
1.8V DDRII 667/800
ATI RS880M
uFCBGA-528
page 36,37 page 27 page 37 page 36 page 36
USB
conn
X 2
USB port 0,6
3.3V 48MHz
3.3V 24.576MHz/48Mhz
S-ATA
USB
SATA HDD
Conn.
page 32
port 0
page 39
D
200pin DDRII-SO-DIMM X2
BANK 0, 1, 2, 3
Thermal Sensor
ADM1032
page 6 page 23
CMOS
Camera
Bluetooth
Conn
Clock Generator
SLG8SP626VTR
USB port 3 USB port 12 USB port 13 USB port 8
HD Audio
USB port 1
MDC 1.5
Conn
CDROM
Conn.
page 32
port 1
ESATA
Conn.
page 37
port 2
page 8,9
Finger
printer
AES1610
page 41
Mini
card
(WL)X1
HDA Codec
ALC888
Audio AMP
Phone Jack x3
E
page 42
page 43
page 43
5 in 1 socket
page 33
Card Reader
RTS5159
page 33
option1
USB port 4
Digital MIC
page 42
Power On/Off CKT.
page 41
EC I/O Buffer
page 38
BIOS
page 39
DC/DC Interface CKT.
page 45
Power Circuit
4 4
page 46,47,48,49,50,51
52,53,54
A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2008/10/06 2009/10/06
2008/10/06 2009/10/06
2008/10/06 2009/10/06
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
B
B
B
Date: Sheet of
Date: Sheet of
D
Date: Sheet of
Compal Electronics, Inc.
Block Diagrams
Block Diagrams
Block Diagrams
KBLG0 LA-4921P
KBLG0 LA-4921P
KBLG0 LA-4921P
E
0.1
0.1
2 57Wednesday, March 11, 2009
2 57Wednesday, March 11, 2009
2 57Wednesday, March 11, 2009
0.1
A
Voltage Rails
Power Plane Description
VIN
1 1
2 2
B+
+CPU_CORE_0
+CPU_CORE_1 Core voltage for CPU (0.7-1.2V)
+CPU_CORE_NB Voltage for On-die Northbridge of CPU(0.8-1.1V)
+0.9V 0.9V switched power rail for DDR terminator
+1.1VS
+1.2V_HT 1.2V switched power rail ON OFF OFF
+VGA_CORE OFFOFFON
+1.5VS
+1.8V
+1.8VS 1.8V switched power rail
+2.5VS
+3VALW
+3V_LAN 3.3V power rail for LAN ON ON ON
+3VS
+5VALW
+5VS
+VSB VSB always on power rail ON ON*
+RTCVCC RTC power
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
Adapter power supply (19V)
AC or battery power rail for power circuit.
Core voltage for CPU (0.7-1.2V)
1.1V switched power rail for NB VDDC & VGA
0.95-1.2V switched power rail
1.5V power rail for PCIE Card
1.8V power rail for CPU VDDIO and DDR
2.5V for CPU_VDDA
3.3V always on power rail
3.3V switched power rail
5V always on power rail
5V switched power rail
External PCI Devices
Device IDSEL#
REQ#/GNT#
B
S1 S3 S5
N/A N/A N/A
ON OFF
ON OFF OFF
ON OFF OFF
ON
ON
ON OFF OFF
OFF OFF
ON
ON
ON
OFF
ON
OFF
ON
ON ON*
ON
OFF
ON
ON
ON
OFF
ON
ON
Interrupts
N/AN/AN/A
OFF
OFF
OFF
OFF
OFF
OFF
ON*
OFFON
ONON
C
STATE
SIGNAL
Full ON
S1(Power On Suspend)
S3 (Suspend to RAM)
S4 (Suspend to Disk)
S5 (Soft OFF)
SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
HIGH HIGH HIGH HIGH
LOW
LOW
LOW
LOW LOW LOW LOW
HIGH
LOWLOWLOW
D
HIGHHIGHHIGH
HIGH
HIGH
ON
ON
ON ON
ON
ON
ON
ON
ON
OFF
ON
ON
OFF
OFF
OFF
OFF
Board ID / SKU ID Table for AD channel
Vcc 3.3V +/- 5%
Board ID
0
1
2
3
4
5
6
7 NC
100K +/- 5%Ra/Rc/Re
Rb / Rd / Rf V min
0
8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%
AD_BID
0 V
0.216 V 0.250 V 0.289 V
0.436 V
0.712 V
1.036 V
1.453 V 1.650 V 1.759 V
1.935 V
2.500 V
V typ
AD_BID
V
AD_BID
0 V 0 V
0.503 V
0.819 V
0.538 V
0.875 V
1.185 V 1.264 V
2.200 V
3.300 V
2.341 V
3.300 V
max
BOARD ID Table BTO Option Table
Board ID
0
1
2
3
4
5
6
7
PCB Revision
0.1
0.2
0.3
0.4
1.0
BTO Item BOM Structure
Discrete
UMA UMA@
VRAM STRAP VRAM@
LAN 8121 8121@
LAN 8131 8131@
HDT debug HDT@
JMB385 CR JMB385@
E
LOW
OFF
OFF
OFF
VGA@
M92@M92-M2 XT
RTS5159 CR RTS5159@
FOR PUMA PUMA@
3 3
EC SM Bus1 address
Device
Smart Battery
Address Address
HEX
16H
SB700
SM Bus 0 address
Device
Clock Generator
(SILEGO SLG8SP626)
DDR DIMM1
DDR DIMM2
Mini card
4 4
Address
1101 001Xb
1001 000Xb
1001 010Xb
HEX
D2
90
94
EC SM Bus2 address
Device
ADI ADM1032 (CPU)
GMT G781-1 (GPU)
SB-Temp Sensor
1001 100X b0001 011X b
1001 101X b
SB700
SM Bus 1 address
Device Address
New card
HEX
98H
9AH
9CH
IGP only mode
PowerXpress mode
IGP only mode
PowerXpress mode
PX_GPIO0
IGP only mode
PX_GPIO1
Enable +1.1VS_PXFunction Description
H : Enable Reserved H : Enable
Trigger from SB to Enable (PX_GPIO1/PX_+3VS/PX_+1.8VS/PX_+VGA_CORE)Function Description
dGPU_ResetFunction Description
PX MODE SWITCH
XX
KB926
PX_GPIO1_SB
X
H : Enable
PX_GPIO1
dGPU_PWR_Enable
XX
H : EnableH : Enable
KB926
PX_+3VSPX_GPIO2
Enable +3VS_DELAY
X
L : iGPU(DC) / H : dGPU(AC)
FOR TIGRIS TIGRIS@
FOR TEST UB@
RS780MNSB700 SB700
PX_GPIO2
PX Mode Switch
X
PX_+1.8VS
Enable +1.8VS_PX
X
H : Enable
PX_+VGA_CORE
Enable +VGA_CORE
DISPLAY OUTPUT
LVDS / CRTPowerXpress mode
X
H : Enable
PX_GPIO2_NB
Trigger from SB
X
Reserved
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2008/10/06 2009/10/06
2008/10/06 2009/10/06
2008/10/06 2009/10/06
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
B
B
B
Date: Sheet of
Date: Sheet of
D
Date: Sheet of
Compal Electronics, Inc.
Notes List
Notes List
Notes List
KBLG0 LA-4921P
KBLG0 LA-4921P
KBLG0 LA-4921P
E
0.1
0.1
3 57Wednesday, March 11, 2009
3 57Wednesday, March 11, 2009
3 57Wednesday, March 11, 2009
0.1
A
1 1
B
C
D
E
+1.2V_HT
250 mil
1
C727
C727
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
PUMA@
PUMA@
Change as 10U
for Tigris
AE2
AE3
AE4
AE5
AD1
AC1
AC2
AC3
AB1
AA1
AA2
AA3
W2
W3
V1
U1
U2
U3
T1
R1
AD4
AD3
AD5
AC5
AB4
AB3
AB5
AA5
Y5
W5
V4
V3
V5
U5
T4
T3
Y1
W1
Y4
Y3
R2
R3
T5
R5
+1.2V_HT
H_CADOP[0..15]
H_CADON[0..15]
Change as 10U
for Tigris
PUMA@
PUMA@
1 2
C664 4.7U_0805_10V4Z
C664 4.7U_0805_10V4Z
H_CADOP0
H_CADON0
H_CADOP1
H_CADON1
H_CADOP2
H_CADON2
H_CADOP3
H_CADON3
H_CADOP4
H_CADON4
H_CADOP5
H_CADON5
H_CADOP6
H_CADON6
H_CADOP7
H_CADON7
H_CADOP8
H_CADON8
H_CADOP9
H_CADON9
H_CADOP10
H_CADON10
H_CADOP11
H_CADON11
H_CADOP12
H_CADON12
H_CADOP13
H_CADON13
H_CADOP14
H_CADON14
H_CADOP15
H_CADON15
H_CADOP[0..15] 10
H_CADON[0..15] 10H_CADIN[0..15]10
H_CLKOP0 10
H_CLKON0 10
H_CLKOP1 10
H_CLKON1 10
H_CTLOP0 10
H_CTLON0 10H_CTLIN010
H_CTLON1 10
H_CADIP[0..15]10
2 2
3 3
H_CLKIP010
H_CLKIN010
H_CLKIP110
H_CLKIN110
H_CTLIP010
H_CTLIP110 H_CTLOP1 10
H_CTLIN110
H_CADIP[0..15]
H_CADIN[0..15]
VLDT=1.5A
+1.2V_HT
H_CADIP0
H_CADIN0
H_CADIP1
H_CADIN1
H_CADIP2
H_CADIN2
H_CADIP3
H_CADIN3
H_CADIP4
H_CADIN4
H_CADIP5
H_CADIN5
H_CADIP6
H_CADIN6
H_CADIP7
H_CADIN7
H_CADIP8
H_CADIN8
H_CADIP9
H_CADIN9
H_CADIP10
H_CADIN10
H_CADIP11
H_CADIN11
H_CADIP12
H_CADIN12
H_CADIP13
H_CADIN13
H_CADIP14
H_CADIN14
H_CADIP15
H_CADIN15
D1
D2
D3
D4
E3
E2
E1
F1
G3
G2
G1
H1
J1
K1
L3
L2
L1
M1
N3
N2
E5
F5
F3
F4
G5
H5
H3
H4
K3
K4
L5
M5
M3
M4
N5
P5
J3
J2
J5
K5
N1
P1
P3
P4
VLDT_A0
VLDT_A1
VLDT_A2
VLDT_A3
L0_CADIN_H0
L0_CADIN_L0
L0_CADIN_H1
L0_CADIN_L1
L0_CADIN_H2
L0_CADIN_L2
L0_CADIN_H3
L0_CADIN_L3
L0_CADIN_H4
L0_CADIN_L4
L0_CADIN_H5
L0_CADIN_L5
L0_CADIN_H6
L0_CADIN_L6
L0_CADIN_H7
L0_CADIN_L7
L0_CADIN_H8
L0_CADIN_L8
L0_CADIN_H9
L0_CADIN_L9
L0_CADIN_H10
L0_CADIN_L10
L0_CADIN_H11
L0_CADIN_L11
L0_CADIN_H12
L0_CADIN_L12
L0_CADIN_H13
L0_CADIN_L13
L0_CADIN_H14
L0_CADIN_L14
L0_CADIN_H15
L0_CADIN_L15
L0_CLKIN_H0
L0_CLKIN_L0
L0_CLKIN_H1
L0_CLKIN_L1
L0_CTLIN_H0
L0_CTLIN_L0
L0_CTLIN_H1
L0_CTLIN_L1
6090022100G_B
6090022100G_B
JCPU1A
JCPU1A
HT LINK
HT LINK
VLDT_B0
VLDT_B1
VLDT_B2
VLDT_B3
L0_CADOUT_H0
L0_CADOUT_L0
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H4
L0_CADOUT_L4
L0_CADOUT_H5
L0_CADOUT_L5
L0_CADOUT_H6
L0_CADOUT_L6
L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H8
L0_CADOUT_L8
L0_CADOUT_H9
L0_CADOUT_L9
L0_CADOUT_H10
L0_CADOUT_L10
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H15
L0_CADOUT_L15
L0_CLKOUT_H0
L0_CLKOUT_L0
L0_CLKOUT_H1
L0_CLKOUT_L1
L0_CTLOUT_H0
L0_CTLOUT_L0
L0_CTLOUT_H1
L0_CTLOUT_L1
conn@
conn@
1
C666
C666
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
PUMA@
PUMA@
VLDT CAP.
1
C725
C725
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
Near CPU Socket
1
2
C726
C726
0.22U_0603_16V4Z
0.22U_0603_16V4Z
1
C722
C722
180P_0402_50V8J
180P_0402_50V8J
2
1
C668
C668
180P_0402_50V8J
180P_0402_50V8J
2
4 4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2008/10/06 2009/10/06
2008/10/06 2009/10/06
2008/10/06 2009/10/06
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
D
Date: Sheet of
Compal Electronics, Inc.
AMD CPU S1G2 HT I/F
AMD CPU S1G2 HT I/F
AMD CPU S1G2 HT I/F
KBLG0 LA-4921P
KBLG0 LA-4921P
KBLG0 LA-4921P
4 57Wednesday, March 11, 2009
4 57Wednesday, March 11, 2009
4 57Wednesday, March 11, 2009
E
0.1
0.1
0.1
A
B
C
D
E
PLACE CLOSE TO PROCESSOR
WITHIN 1.5 INCH
AD10
AF10
AE10
AA16
D10
C10
B10
H16
T19
V22
U21
V19
T20
U19
U20
V20
N19
N20
E16
F16
Y16
P19
P20
N21
M20
N22
M19
M22
M24
K22
R21
K20
V24
K24
K19
R20
R23
R19
T22
T24
J22
J20
L20
L21
L19
L22
J21
DDRA_CLK0
DDRA_CLK0#
DDRA_CLK1
DDRA_CLK1#
DDRB_CLK0
DDRB_CLK0#
DDRB_CLK1
DDRB_CLK1#
VTT1
MEM:CMD/CTRL/CLK
MEM:CMD/CTRL/CLK
VTT2
VTT3
VTT4
MEMZP
MEMZN
RSVD_M1
MA0_ODT0
MA0_ODT1
MA1_ODT0
MA1_ODT1
MA0_CS_L0
MA0_CS_L1
MA1_CS_L0
MA1_CS_L1
MA_CKE0
MA_CKE1
MA_CLK_H0
MA_CLK_L0
MA_CLK_H1
MA_CLK_L1
MA_CLK_H2
MA_CLK_L2
MA_CLK_H3
MA_CLK_L3
MA_ADD0
MA_ADD1
MA_ADD2
MA_ADD3
MA_ADD4
MA_ADD5
MA_ADD6
MA_ADD7
MA_ADD8
MA_ADD9
MA_ADD10
MA_ADD11
MA_ADD12
MA_ADD13
MA_ADD14
MA_ADD15
MA_BANK0
MA_BANK1
MA_BANK2
MA_RAS_L
MA_CAS_L
MA_WE_L
6090022100G_B
6090022100G_B
conn@
conn@
JCPU1B
JCPU1B
1
2
1
2
1
2
1
2
VTT5
VTT6
VTT7
VTT8
VTT9
VTT_SENSE
MEMVREF
RSVD_M2
MB0_ODT0
MB0_ODT1
MB1_ODT0
MB0_CS_L0
MB0_CS_L1
MB1_CS_L0
MB_CKE0
MB_CKE1
MB_CLK_H0
MB_CLK_L0
MB_CLK_H1
MB_CLK_L1
MB_CLK_H2
MB_CLK_L2
MB_CLK_H3
MB_CLK_L3
MB_ADD0
MB_ADD1
MB_ADD2
MB_ADD3
MB_ADD4
MB_ADD5
MB_ADD6
MB_ADD7
MB_ADD8
MB_ADD9
MB_ADD10
MB_ADD11
MB_ADD12
MB_ADD13
MB_ADD14
MB_ADD15
MB_BANK0
MB_BANK1
MB_BANK2
MB_RAS_L
MB_CAS_L
MB_WE_L
C379
C379
1.5P_0402_50V9C
1.5P_0402_50V9C
C111
C111
1.5P_0402_50V9C
1.5P_0402_50V9C
C380
C380
1.5P_0402_50V9C
1.5P_0402_50V9C
C112
C112
1.5P_0402_50V9C
1.5P_0402_50V9C
W10
AC10
AB10
AA10
A10
Y10
W17
B18
W26
W23
Y26
V26
W25
U22
J25
H26
P22
R22
A17
A18
AF18
AF17
R26
R25
P24
N24
P26
N23
N26
L23
N25
L24
M26
K26
T26
L26
L25
W24
J23
J24
R24
U26
J26
U25
U24
U23
+0.9V+0.9V
VTT_SENSE
+MCH_REF
DDRB_ODT0
DDRB_ODT1
DDRB_SCS1#
DDRB_CKE0
DDRB_CKE1
DDRB_CLK0
DDRB_CLK0#
DDRB_CLK1
DDRB_CLK1#DDRA_CLK1#
DDRB_SMA0
DDRB_SMA1
DDRB_SMA2
DDRB_SMA3
DDRB_SMA4
DDRB_SMA5
DDRB_SMA6
DDRB_SMA7
DDRB_SMA8
DDRB_SMA9
DDRB_SMA10
DDRB_SMA11
DDRB_SMA12
DDRB_SMA13
DDRB_SMA14
DDRB_SMA15
DDRB_SBS0#
DDRB_SBS1#
DDRB_SBS2#
DDRB_SRAS#
DDRB_SCAS#
DDRB_SWE#
T4PAD T4PAD
DDRB_ODT0 9
DDRB_ODT1 9
DDRB_SCS1# 9
DDRB_CKE0 9
DDRB_CKE1 9
DDRB_CLK0 9
DDRB_CLK0# 9
DDRB_CLK1 9
DDRB_CLK1# 9
DDRB_SBS0# 9
DDRB_SBS1# 9
DDRB_SBS2# 9
DDRB_SRAS# 9
DDRB_SCAS# 9
DDRB_SWE# 9
1 1
2 2
3 3
4 4
+1.8V
R78
R78
1K_0402_1%
1K_0402_1%
1 2
+MCH_REF
1
R79
R79
1K_0402_1%
1K_0402_1%
1 2
Place them clos e to CPU within 1"
DDRA_SMA[15..0]8 DDRB_SMA[15..0] 9
1
C178
C178
C177
2
C177
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1000P_0402_25V8J
1000P_0402_25V8J
VTT=0.75A
R77 39.2_0402_1%R77 39.2_0402_1%
1 2
+1.8V
DDRA_ODT08
DDRA_ODT18
DDRA_SCS0#8
DDRA_SCS1#8 DDRB_SCS0# 9
DDRA_CKE08
DDRA_CKE18
DDRA_CLK08
DDRA_CLK0#8
DDRA_CLK18
DDRA_CLK1#8
DDRA_SBS0#8
DDRA_SBS1#8
DDRA_SBS2#8
DDRA_SRAS#8
DDRA_SCAS#8
DDRA_SWE#8
1 2
R76 39.2_0402_1%R76 39.2_0402_1%
DDRA_ODT0
DDRA_ODT1
DDRA_SCS0#
DDRA_SCS1# DDRB_SCS0#
DDRA_CKE0
DDRA_CKE1
DDRA_CLK0
DDRA_CLK0#
DDRA_CLK1
DDRA_SMA0
DDRA_SMA1
DDRA_SMA2
DDRA_SMA3
DDRA_SMA4
DDRA_SMA5
DDRA_SMA6
DDRA_SMA7
DDRA_SMA8
DDRA_SMA9
DDRA_SMA10
DDRA_SMA11
DDRA_SMA12
DDRA_SMA13
DDRA_SMA14
DDRA_SMA15
DDRA_SBS0#
DDRA_SBS1#
DDRA_SBS2#
DDRA_SRAS#
DDRA_SCAS#
DDRA_SWE#
DDRB_SDQ[63..0]9
DDRB_SDM[7..0]9 DDRA_SDM[7..0] 8
DDRB_SDQS09
DDRB_SDQS0#9
DDRB_SDQS19
DDRB_SDQS1#9
DDRB_SDQS29
DDRB_SDQS2#9
DDRB_SDQS39
DDRB_SDQS3#9
DDRB_SDQS49
DDRB_SDQS4#9
DDRB_SDQS59
DDRB_SDQS5#9
DDRB_SDQS69
DDRB_SDQS6#9
DDRB_SDQS79
DDRB_SDQS7#9
Processor DDR2 Memory Interface
JCPU1C
DDRB_SDQ0
DDRB_SDQ1
DDRB_SDQ2
DDRB_SDQ3
DDRB_SDQ4
DDRB_SDQ5
DDRB_SDQ6
DDRB_SDQ7
DDRB_SDQ8
DDRB_SDQ9
DDRB_SDQ10
DDRB_SDQ11
DDRB_SDQ12
DDRB_SDQ13
DDRB_SDQ14
DDRB_SDQ15
DDRB_SDQ16
DDRB_SDQ17
DDRB_SDQ18
DDRB_SDQ19
DDRB_SDQ20
DDRB_SDQ21
DDRB_SDQ22
DDRB_SDQ23
DDRB_SDQ24
DDRB_SDQ25
DDRB_SDQ26
DDRB_SDQ27
DDRB_SDQ28
DDRB_SDQ29
DDRB_SDQ30
DDRB_SDQ31
DDRB_SDQ32
DDRB_SDQ33
DDRB_SDQ34
DDRB_SDQ35
DDRB_SDQ36
DDRB_SDQ37
DDRB_SDQ38
DDRB_SDQ39
DDRB_SDQ40
DDRB_SDQ41
DDRB_SDQ42
DDRB_SDQ43
DDRB_SDQ44
DDRB_SDQ45
DDRB_SDQ46
DDRB_SDQ47
DDRB_SDQ48
DDRB_SDQ49
DDRB_SDQ50
DDRB_SDQ51
DDRB_SDQ52
DDRB_SDQ53
DDRB_SDQ54
DDRB_SDQ55
DDRB_SDQ56
DDRB_SDQ57
DDRB_SDQ58
DDRB_SDQ59
DDRB_SDQ60
DDRB_SDQ61
DDRB_SDQ62
DDRB_SDQ63
DDRB_SDM0
DDRB_SDM1
DDRB_SDM2
DDRB_SDM3
DDRB_SDM4
DDRB_SDM5
DDRB_SDM6
DDRB_SDM7
DDRB_SDQS0
DDRB_SDQS0#
DDRB_SDQS1
DDRB_SDQS1#
DDRB_SDQS2
DDRB_SDQS2#
DDRB_SDQS3
DDRB_SDQS3#
DDRB_SDQS4
DDRB_SDQS4#
DDRB_SDQS5
DDRB_SDQS5#
DDRB_SDQS6
DDRB_SDQS6#
DDRB_SDQS7
DDRB_SDQS7#
AA24
AA23
AD24
AE24
AA26
AA25
AD26
AE25
AC22
AD22
AE20
AF20
AF24
AF23
AC20
AD20
AD18
AE18
AC14
AD14
AF19
AC18
AF16
AF15
AF13
AC12
AB11
AE14
AF14
AF11
AD11
AB26
AE22
AC16
AD12
AC25
AC26
AF21
AF22
AE16
AD16
AF12
AE12
C11
A11
A14
B14
G11
E11
D12
A13
A15
A16
A19
A20
C14
D14
C18
D18
D20
A21
D24
C25
B20
C20
B24
C24
E23
E24
G25
G26
C26
D26
G23
G24
Y11
A12
B16
A22
E25
C12
B12
D16
C16
A24
A23
F26
E26
JCPU1C
6090022100G_B
6090022100G_B
conn@
conn@
MB_DATA0
MB_DATA1
MB_DATA2
MB_DATA3
MB_DATA4
MB_DATA5
MB_DATA6
MB_DATA7
MB_DATA8
MB_DATA9
MB_DATA10
MB_DATA11
MB_DATA12
MB_DATA13
MB_DATA14
MB_DATA15
MB_DATA16
MB_DATA17
MB_DATA18
MB_DATA19
MB_DATA20
MB_DATA21
MB_DATA22
MB_DATA23
MB_DATA24
MB_DATA25
MB_DATA26
MB_DATA27
MB_DATA28
MB_DATA29
MB_DATA30
MB_DATA31
MB_DATA32
MB_DATA33
MB_DATA34
MB_DATA35
MB_DATA36
MB_DATA37
MB_DATA38
MB_DATA39
MB_DATA40
MB_DATA41
MB_DATA42
MB_DATA43
MB_DATA44
MB_DATA45
MB_DATA46
MB_DATA47
MB_DATA48
MB_DATA49
MB_DATA50
MB_DATA51
MB_DATA52
MB_DATA53
MB_DATA54
MB_DATA55
MB_DATA56
MB_DATA57
MB_DATA58
MB_DATA59
MB_DATA60
MB_DATA61
MB_DATA62
MB_DATA63
MB_DM0
MB_DM1
MB_DM2
MB_DM3
MB_DM4
MB_DM5
MB_DM6
MB_DM7
MB_DQS_H0
MB_DQS_L0
MB_DQS_H1
MB_DQS_L1
MB_DQS_H2
MB_DQS_L2
MB_DQS_H3
MB_DQS_L3
MB_DQS_H4
MB_DQS_L4
MB_DQS_H5
MB_DQS_L5
MB_DQS_H6
MB_DQS_L6
MB_DQS_H7
MB_DQS_L7
MEM:DATA
MEM:DATA
MA_DATA0
MA_DATA1
MA_DATA2
MA_DATA3
MA_DATA4
MA_DATA5
MA_DATA6
MA_DATA7
MA_DATA8
MA_DATA9
MA_DATA10
MA_DATA11
MA_DATA12
MA_DATA13
MA_DATA14
MA_DATA15
MA_DATA16
MA_DATA17
MA_DATA18
MA_DATA19
MA_DATA20
MA_DATA21
MA_DATA22
MA_DATA23
MA_DATA24
MA_DATA25
MA_DATA26
MA_DATA27
MA_DATA28
MA_DATA29
MA_DATA30
MA_DATA31
MA_DATA32
MA_DATA33
MA_DATA34
MA_DATA35
MA_DATA36
MA_DATA37
MA_DATA38
MA_DATA39
MA_DATA40
MA_DATA41
MA_DATA42
MA_DATA43
MA_DATA44
MA_DATA45
MA_DATA46
MA_DATA47
MA_DATA48
MA_DATA49
MA_DATA50
MA_DATA51
MA_DATA52
MA_DATA53
MA_DATA54
MA_DATA55
MA_DATA56
MA_DATA57
MA_DATA58
MA_DATA59
MA_DATA60
MA_DATA61
MA_DATA62
MA_DATA63
MA_DM0
MA_DM1
MA_DM2
MA_DM3
MA_DM4
MA_DM5
MA_DM6
MA_DM7
MA_DQS_H0
MA_DQS_L0
MA_DQS_H1
MA_DQS_L1
MA_DQS_H2
MA_DQS_L2
MA_DQS_H3
MA_DQS_L3
MA_DQS_H4
MA_DQS_L4
MA_DQS_H5
MA_DQS_L5
MA_DQS_H6
MA_DQS_L6
MA_DQS_H7
MA_DQS_L7
G12
F12
H14
G14
H11
H12
C13
E13
H15
E15
E17
H17
E14
F14
C17
G17
G18
C19
D22
E20
E18
F18
B22
C23
F20
F22
H24
J19
E21
E22
H20
H22
Y24
AB24
AB22
AA21
W22
W21
Y22
AA22
Y20
AA20
AA18
AB18
AB21
AD21
AD19
Y18
AD17
W16
W14
Y14
Y17
AB17
AB15
AD15
AB13
AD13
Y12
W11
AB14
AA14
AB12
AA12
E12
C15
E19
F24
AC24
Y19
AB16
Y13
G13
H13
G16
G15
C22
C21
G22
G21
AD23
AC23
AB19
AB20
Y15
W15
W12
W13
DDRA_SDQ0
DDRA_SDQ1
DDRA_SDQ2
DDRA_SDQ3
DDRA_SDQ4
DDRA_SDQ5
DDRA_SDQ6
DDRA_SDQ7
DDRA_SDQ8
DDRA_SDQ9
DDRA_SDQ10
DDRA_SDQ11
DDRA_SDQ12
DDRA_SDQ13
DDRA_SDQ14
DDRA_SDQ15
DDRA_SDQ16
DDRA_SDQ17
DDRA_SDQ18
DDRA_SDQ19
DDRA_SDQ20
DDRA_SDQ21
DDRA_SDQ22
DDRA_SDQ23
DDRA_SDQ24
DDRA_SDQ25
DDRA_SDQ26
DDRA_SDQ27
DDRA_SDQ28
DDRA_SDQ29
DDRA_SDQ30
DDRA_SDQ31
DDRA_SDQ32
DDRA_SDQ33
DDRA_SDQ34
DDRA_SDQ35
DDRA_SDQ36
DDRA_SDQ37
DDRA_SDQ38
DDRA_SDQ39
DDRA_SDQ40
DDRA_SDQ41
DDRA_SDQ42
DDRA_SDQ43
DDRA_SDQ44
DDRA_SDQ45
DDRA_SDQ46
DDRA_SDQ47
DDRA_SDQ48
DDRA_SDQ49
DDRA_SDQ50
DDRA_SDQ51
DDRA_SDQ52
DDRA_SDQ53
DDRA_SDQ54
DDRA_SDQ55
DDRA_SDQ56
DDRA_SDQ57
DDRA_SDQ58
DDRA_SDQ59
DDRA_SDQ60
DDRA_SDQ61
DDRA_SDQ62
DDRA_SDQ63
DDRA_SDM0
DDRA_SDM1
DDRA_SDM2
DDRA_SDM3
DDRA_SDM4
DDRA_SDM5
DDRA_SDM6
DDRA_SDM7
DDRA_SDQS0
DDRA_SDQS0#
DDRA_SDQS1
DDRA_SDQS1#
DDRA_SDQS2
DDRA_SDQS2#
DDRA_SDQS3
DDRA_SDQS3#
DDRA_SDQS4
DDRA_SDQS4#
DDRA_SDQS5
DDRA_SDQS5#
DDRA_SDQS6
DDRA_SDQS6#
DDRA_SDQS7
DDRA_SDQS7#
DDRA_SDQ[63..0] 8
DDRA_SDQS0 8
DDRA_SDQS0# 8
DDRA_SDQS1 8
DDRA_SDQS1# 8
DDRA_SDQS2 8
DDRA_SDQS2# 8
DDRA_SDQS3 8
DDRA_SDQS3# 8
DDRA_SDQS4 8
DDRA_SDQS4# 8
DDRA_SDQS5 8
DDRA_SDQS5# 8
DDRA_SDQS6 8
DDRA_SDQS6# 8
DDRA_SDQS7 8
DDRA_SDQS7# 8
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2008/10/06 2009/10/06
2008/10/06 2009/10/06
2008/10/06 2009/10/06
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
D
Date: Sheet of
Compal Electronics, Inc.
AMD CPU S1G2 DDRII I/F
AMD CPU S1G2 DDRII I/F
AMD CPU S1G2 DDRII I/F
KBLG0 LA-4921P
KBLG0 LA-4921P
KBLG0 LA-4921P
5 57Thursday, February 19, 2009
5 57Thursday, February 19, 2009
5 57Thursday, February 19, 2009
E
0.1
0.1
0.1
A
B
C
D
E
1 2
C92 0.1U_0402_16V4Z@C92 0.1U_0402_16V4Z@
R53
R53
34.8K_0402_1%
34.8K_0402_1%
@
@
2
13
D
D
2
13
D
D
+2.5VDDA
3300P_0402_50V7K
3300P_0402_50V7K
1
1
C3854.7U_0805_10V4Z C3854.7U_0805_10V4Z
2
2
CPU_CLKIN_SC_P
CPU_CLKIN_SC_N
CPU_LDT_REQ#11
R70 2.2K_0402_5%R70 2.2K_0402_5%
+1.8V
+1.8V
R71 2.2K_0402_5%R71 2.2K_0402_5%
R82 44.2_0402_1%R82 44.2_0402_1%
R89 44.2_0402_1%R89 44.2_0402_1%
+1.2V_HT
12
EC_SMB_DA
DVT
EC_SMB_CK
EC_SMB_CK2 22,38
EC_SMB_DA2 22,38
B
VDDA=0.25A
1
C384
C384
C319
C319
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
LDT_RST#
H_PWRGD
LDT_STOP#
12
12
1 2
1 2
CPU_VDD0_FB_H53
CPU_VDD0_FB_L53
CPU_VDD1_FB_H53
CPU_VDD1_FB_L53
CPU_DBRDY
CPU_TMS
CPU_TCK
CPU_TRST#
CPU_TDI
T44 PADT44 PAD
T25 PADT25 PAD
T26 PADT26 PAD
T37 PADT37 PAD
T33 PADT33 PAD
T43 PADT43 PAD
T42 PADT42 PAD
T3 PADT3 PAD
T41 PADT41 PAD
R330 0_0402_5%R 330 0_0402_5 %
1 2
T2 PADT2 PAD
FDV301N, the Vgs is:
min = 0.65V
Typ = 0.85V
Max = 1.5V
2.09V for Gate
@
@
1 2
R479 0_0402_5%
R479 0_0402_5%
@
@
1 2
R484 0_0402_5%
R484 0_0402_5%
@
@
1 2
R480 0_0402_5%
R480 0_0402_5%
@
@
1 2
R485 0_0402_5%
R485 0_0402_5%
JCPU1D
JCPU1D
CPU_SIC
CPU_SID
CPU_HTREF0
CPU_HTREF1
CPU_VDD0_FB_H
CPU_VDD0_FB_L
CPU_VDD1_FB_H
CPU_VDD1_FB_L
CPU_TEST23
CPU_TEST18
CPU_TEST19
CPU_TEST25H
CPU_TEST25L
CPU_TEST21
CPU_TEST20
CPU_TEST24
CPU_TEST22
CPU_TEST12
CPU_TEST27
CPU_TEST6
EC_SMB_DA2
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_CK1
F8
VDDA1
F9
VDDA2
A9
CLKIN_H
A8
CLKIN_L
B7
RESET_L
A7
PWROK
F10
LDTSTOP_L
C6
LDTREQ_L
AF4
SIC
AF5
SID
AE6
ALERT_L
R6
HT_REF0
P6
HT_REF1
F6
VDD0_FB_H
E6
VDD0_FB_L
Y6
VDD1_FB_H
AB6
VDD1_FB_L
G10
DBRDY
AA9
TMS
AC9
TCK
AD9
TRST_L
AF9
TDI
AD7
TEST23
H10
TEST18
G9
TEST19
E9
TEST25_H
E8
TEST25_L
AB8
TEST21
AF7
TEST20
AE7
TEST24
AE8
TEST22
AC8
TEST12
AF8
TEST27
C2
TEST9
AA6
TEST6
A3
RSVD1
A5
RSVD2
B3
RSVD3
B5
RSVD4
C1
RSVD5
6090022100G_B
6090022100G_B
conn@
conn@
EC_SMB_DA1 38,47
EC_SMB_CK1 38,47
THERMTRIP_L
PROCHOT_L
VDDIO_FB_H
VDDIO_FB_L
VDDNB_FB_H
VDDNB_FB_L
KEY1
KEY2
SVC
SVD
MEMHOT_L
THERMDC
THERMDA
DBREQ_L
TDO
TEST28_H
TEST28_L
TEST17
TEST16
TEST15
TEST14
TEST7
TEST10
TEST8
TEST29_H
TEST29_L
RSVD10
RSVD9
RSVD8
RSVD7
RSVD6
M11
W18
CPU_SVC
A6
CPU_SVD
A4
CPU_THERMTRIP#_R
AF6
H_PROCHOT#
AC7
AA8
THERMDC_CPU
W7
THERMDA_CPU
W8
W9
Y9
H6
G6
E10
AE9
J7
H8
D7
E7
F7
C7
C3
K8
C4
C9
C8
H18
H19
AA7
D5
C5
T6PAD T6PAD
T5PAD T5PAD
CPU_VDDNB_FB_H
CPU_VDDNB_FB_L
CPU_DBREQ#
CPU_TDO
CPU_TEST28_H_PLLCHRZ _P
CPU_TEST28_L_PLLCHRZ_N
CPU_TEST17
CPU_TEST16
CPU_TEST15
CPU_TEST14
CPU_TEST7
CPU_TEST10
CPU_TEST8
CPU_TEST29_H_FBCLKOUT_P
CPU_TEST29_L_FBCLKOUT_N
+1.8V
R117220_0402_5%
R117220_0402_5%
12
CPU_DBREQ#
CPU_DBRDY
HDT@
HDT@
CPU_TCK
CPU_TMS
CPU_TDI
CPU_TRST#
CPU_TDO
CPU_SVC 53
CPU_SVD 53
R119220_0402_5%
R119220_0402_5%
R118220_0402_5%
R118220_0402_5%
12
12
HDT@
HDT@
HDT@
HDT@
CPU_VDDNB_FB_H 53
CPU_VDDNB_FB_L 53
R120220_0402_5%
R120220_0402_5%
12
HDT@
HDT@
+1.8V
MP(Remove)
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2008/10/06 2009/10/06
2008/10/06 2009/10/06
2008/10/06 2009/10/06
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
+1.8V
T24PAD T24PAD
T21PAD T21PAD
T34PAD T34PAD
T36PAD T36PAD
T32PAD T32PAD
T38PAD T38PAD
T31PAD T31PAD
T18PAD T18PAD
T67PAD T67PAD
T39PAD T39PAD
T35PAD T35PAD
For Tigris
For Tigris
CONN@ SAMTEC_ASP-68200-07
CONN@
D
1 2
R66 10K_0402_5%R66 10K_0402_5%
1 2
R67 30 0_0402_5%R67 30 0_0402_5%
CPU_THERMTRIP#_R
1 2
+1.8V
R69 30 0_0402_5%R69 30 0_0402_5%
H_PROCHOT#
CPU_SVC
CPU_SVD
CPU_TEST25H
CPU_TEST25L
CPU_DBREQ#
CPU_TEST21
CPU_TEST24
CPU_TEST20
CPU_TEST23
CPU_TEST25H
CPU_TEST25L
JP1
JP1
2
1
4
3
6
5
8
7
10
9
12
11
14
13
16
15
18
17
20
19
22
21
2423
26
SAMTEC_ASP-68200-07
MP(mask)
B
B
2
Q9
Q9
E
E
3 1
C
C
MMBT3904_NL_SOT23-3
MMBT3904_NL_SOT23-3
TIGRIS@
TIGRIS@
1 2
R144 300_0402_5%
R144 300_0402_5%
1 2
R143 300_0402_5%R143 300_0402_5%
1 2
R327 300_0402_5%R327 300_0402_5%
1 2
R75 30 0_0402_5%R75 30 0_0402_5%
1 2
R74 30 0_0402_5%R74 30 0_0402_5%
1 2
R73 30 0_0402_5%R73 30 0_0402_5%
1 2
R72 30 0_0402_5%R72 30 0_0402_5%
1 2
R136 300_0402_5%R136 300_0402_5%
1 2
R135 300_0402_5%
R135 300_0402_5%
TIGRIS@
TIGRIS@
HDT_RST#
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
R65
R65
1 2
0_0402_5%
0_0402_5%
R68
R68
1 2
0_0402_5%
0_0402_5%
+1.8V
1 2
R328 1K_0402_5%R328 1K_0402_5%
1 2
R329 1K_0402_5%R329 1K_0402_5%
+1.8V
R140
R140
1 2
0_0402_5%@
0_0402_5%@
+3VS
MP(Remove)
5
U15
U15
4
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
AMD CPU S1G2 CTRL
AMD CPU S1G2 CTRL
AMD CPU S1G2 CTRL
2
P
B
Y
1
A
G
NC7SZ08P5X_NL_SC70-5
NC7SZ08P5X_NL_SC70-5
3
HDT@
HDT@
KBLG0 LA-4921P
KBLG0 LA-4921P
KBLG0 LA-4921P
E
H_THERMTRIP# 28
H_PROCHOT_R# 27
LDT_RST#
SB_PWRGD 11,28,41
6 57Wednesday, March 11, 2009
6 57Wednesday, March 11, 2009
6 57Wednesday, March 11, 2009
0.1
0.1
0.1
L35
+2.5VS
1
+
+
C391
C391
150U_B2_6.3VM
150U_B2_6.3VM
1 1
CLK_CPU_BCLK23
CLK_CPU_BCLK#23
+1.8VS
R339
R339
300_0402_5%
300_0402_5%
1 2
LDT_RST#27
2 2
H_PWRGD27
LDT_STOP#11,27
3 3
+3VS
1
C206
C206
4 4
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C194
C194
1 2
2200P_0402_50V7K
2200P_0402_50V7K
PUMA@
PUMA@
Change as 3300pF
For Tigris
LDT_RST#
1
C721
C721
0.01U_0402_25V4Z
0.01U_0402_25V4Z
@
@
2
+1.8VS
R338
R338
300_0402_5%
300_0402_5%
1 2
H_PWRGD
1
C720
C720
0.01U_0402_25V4Z
0.01U_0402_25V4Z
@
@
2
+1.8VS
R337
R337
300_0402_5%
300_0402_5%
1 2
LDT_STOP#
1
C719
C719
0.01U_0402_25V4Z
0.01U_0402_25V4Z
@
@
2
THERMDA_CPU
THERMDC_CPU
A
1
2
3
Address
2
C723
C723
C724 3900P_0402_50V7KC724 3900P_0402_50V7K
DVT2
+3VS
U11
U11
VDD
SCLK
D+
SDATA
ALERT#
D-
THERM#4GND
ADM1032ARMZ_MSOP8
ADM1032ARMZ_MSOP8
1001 100X b
1 2
1 2
8
7
6
5
20K_0402_5%
20K_0402_5%
L35
1 2
FBM_L11_201209_300L_0805
FBM_L11_201209_300L_0805
3900P_0402_50V7K
3900P_0402_50V7K
12
R325
R325
169_0402_1%
169_0402_1%
CPU internal thermal sensor
R52
R52
12
@
@
G
G
CPU_SID
S
S
Q7 FDV301N_NL_SOT23-3@
Q7 FDV301N_NL_SOT23-3@
G
G
CPU_SIC
S
S
Q8 FDV301N_NL_SOT23-3@
Q8 FDV301N_NL_SOT23-3@
EC_SMB_CK2
EC_SMB_DA2
A
VDD(+CPU_CORE) decoupling.
+CPU_CORE_0
1
+
+
C106
1 1
C106
330U_X_2VM_R6M
330U_X_2VM_R6M
2
1
+
+
C661
C661
330U_X_2VM_R6M
330U_X_2VM_R6M
2
Near CPU Socket
+CPU_CORE_0
1
C280
C280
22U_0805_6.3V6M
22U_0805_6.3V6M
2
+CPU_CORE_0
1
C253
C253
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
2 2
1
C281
C281
22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
C276
C276
0.01U_0402_25V4Z
0.01U_0402_25V4Z
2
1
C273
C273
22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
C290
C290
180P_0402_50V8J
180P_0402_50V8J
2
1
C257
C257
22U_0805_6.3V6M
22U_0805_6.3V6M
2
Under CPU Socket
VDDIO decoupling.
+1.8V
1
C195
C195
22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
C228
C228
22U_0805_6.3V6M
22U_0805_6.3V6M
2
Under CPU Socket
1
C222
C222
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
1
C294
C294
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
B
+CPU_CORE_1
+CPU_CORE_1
1
C214
C214
22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
C295
C295
180P_0402_50V8J
180P_0402_50V8J
2
1
+
+
C96
C96
330U_X_2VM_R6M
330U_X_2VM_R6M
2
+CPU_CORE_1
1
C274
C274
180P_0402_50V8J
180P_0402_50V8J
2
1
C238
C238
22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
C244
C244
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
C
VDD0 = 18A VDD1 =18A
JCPU1E
M10
M16
M18
M21
M23
M25
G4
H2
J9
J11
J13
J15
K6
K10
K12
K14
L4
L7
L9
L11
L13
L15
M2
M6
M8
N7
N9
N11
K16
P16
T16
V16
H25
J17
K18
K21
K23
K25
L17
N17
JCPU1E
VDD0_1
VDD0_2
VDD0_3
VDD0_4
VDD0_5
VDD0_6
VDD0_7
VDD0_8
VDD0_9
VDD0_10
VDD0_11
VDD0_12
VDD0_13
VDD0_14
VDD0_15
VDD0_16
VDD0_17
VDD0_18
VDD0_19
VDD0_20
VDD0_21
VDD0_22
VDD0_23
VDDNB_1
VDDNB_2
VDDNB_3
VDDNB_4
VDDNB_5
VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
VDDIO6
VDDIO7
VDDIO8
VDDIO9
VDDIO10
VDDIO11
VDDIO12
6090022100G_B
6090022100G_B
Athlon 64 S1
Processor Socket
conn@
conn@
1
+
+
C643
C643
330U_X_2VM_R6M
330U_X_2VM_R6M
2
1
C227
C227
22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
C184
C184
0.01U_0402_25V4Z
0.01U_0402_25V4Z
2
1
C215
C215
22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
C230
C230
180P_0402_50V8J
180P_0402_50V8J
2
+CPU_CORE_0
VDDNB=4A
(For Tigris)
VDDNB=3A
+CPU_CORE_NB
+1.8V
VDDIO=3A
+CPU_CORE_NB decoupling.
+CPU_CORE_NB
1
C207
C207
22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
C186
C186
22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
C249
C249
22U_0805_6.3V6M
22U_0805_6.3V6M
2
VDD1_1
VDD1_2
VDD1_3
VDD1_4
VDD1_5
VDD1_6
VDD1_7
VDD1_8
VDD1_9
VDD1_10
VDD1_11
VDD1_12
VDD1_13
VDD1_14
VDD1_15
VDD1_16
VDD1_17
VDD1_18
VDD1_19
VDD1_20
VDD1_21
VDD1_22
VDD1_23
VDD1_24
VDD1_25
VDD1_26
VDDIO27
VDDIO26
VDDIO25
VDDIO24
VDDIO23
VDDIO22
VDDIO21
VDDIO20
VDDIO19
VDDIO18
VDDIO17
VDDIO16
VDDIO15
VDDIO14
VDDIO13
D
JCPU1F
JCPU1F
AA4
P8
P10
R4
R7
R9
R11
T2
T6
T8
T10
T12
T14
U7
U9
U11
U13
U15
V6
V8
V10
V12
V14
W4
Y2
AC4
AD2
Y25
V25
V23
V21
V18
U17
T25
T23
T21
T18
R17
P25
P23
P21
P18
+CPU_CORE_1
+1.8V
AA11
AA13
AA15
AA17
AA19
AB23
AB25
AC11
AC13
AC15
AC17
AC19
AC21
AD25
AE11
AE13
AE15
AE17
AE19
AE21
AE23
AB2
AB7
AB9
AD6
AD8
B11
B13
B15
B17
B19
B21
B23
B25
D11
D13
D15
D17
D19
D21
D23
D25
H21
H23
B4
B6
B8
B9
D6
D8
D9
E4
F2
F11
F13
F15
F17
F19
F21
F23
F25
H7
H9
J4
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
6090022100G_B
6090022100G_B
Athlon 64 S1
Processor Socket
conn@
conn@
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
E
J6
J8
J10
J12
J14
J16
J18
K2
K7
K9
K11
K13
K15
K17
L6
L8
L10
L12
L14
L16
L18
M7
M9
AC6
M17
N4
N8
N10
N16
N18
P2
P7
P9
P11
P17
R8
R10
R16
R18
T7
T9
T11
T13
T15
T17
U4
U6
U8
U10
U12
U14
U16
U18
V2
V7
V9
V11
V13
V15
V17
W6
Y21
Y23
N6
3 3
4 4
+1.8V
1
C301
C301
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
+1.8V +1.8V
1
C309
C309
0.01U_0402_25V4Z
0.01U_0402_25V4Z
2
+1.8V
1
2
Between CPU Socket and DIMM
1
C303
C303
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
180PF Qt'y foll ow the distance between
CPU socket and DIMM0. <2.5inch >
1
C218
C218
180P_0402_50V8J
180P_0402_50V8J
2
1
C208
C208
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
C211
C211
4.7U_0805_10V4Z
4.7U_0805_10V4Z
1
C302
C302
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
1
C307
C307
0.01U_0402_25V4Z
0.01U_0402_25V4Z
2
1
C209
C209
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
1
C300
C300
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
1
C308
C308
180P_0402_50V8J
180P_0402_50V8J
2
A: Add C165 and C176
to follow AMD L ayout
review recomman d for
EMI
1
C210
C210
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
1
C310
C310
180P_0402_50V8J
180P_0402_50V8J
2
1
C: Change to NB O CAP
+
+
C226
C226
330U_X_2VM_R6M
330U_X_2VM_R6M
2
1
C219
C219
180P_0402_50V8J
180P_0402_50V8J
2
VTT decoupling.
220U_D2_4VM_R15
220U_D2_4VM_R15
+0.9V
1
C163
C163
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
+0.9V
1
C387
C387
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
1
C164
C164
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
Near CPU Socket Right side.
1
C386
C386
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
1
C109
C109
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
1
C383
C383
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
+0.9V
Near Power Supply
1
C107
C107
C: Change to NB O CAP
+
+
2
1
C110
C110
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
1
C382
C382
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
1
C113
C113
22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
C190
C190
1000P_0402_25V8J
1000P_0402_25V8J
2
1
C718
C718
1000P_0402_25V8J
1000P_0402_25V8J
2
1
C191
C191
1000P_0402_25V8J
1000P_0402_25V8J
2
1
C717
C717
1000P_0402_25V8J
1000P_0402_25V8J
2
1
C189
C189
180P_0402_50V8J
180P_0402_50V8J
2
1
C716
C716
180P_0402_50V8J
180P_0402_50V8J
2
1
C173
C173
180P_0402_50V8J
180P_0402_50V8J
2
1
C715
C715
180P_0402_50V8J
180P_0402_50V8J
2
Near CPU Socket Left side.
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2008/10/06 2009/10/06
2008/10/06 2009/10/06
2008/10/06 2009/10/06
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
D
Date: Sheet of
Compal Electronics, Inc.
AMD CPU S1G2 PWR & GND
AMD CPU S1G2 PWR & GND
AMD CPU S1G2 PWR & GND
KBLG0 LA-4921P
KBLG0 LA-4921P
KBLG0 LA-4921P
7 57Thursday, January 15, 2009
7 57Thursday, January 15, 2009
7 57Thursday, January 15, 2009
E
0.1
0.1
0.1
A
+1.8V +1.8V
JDIMM1
JDIMM1
+V_DDR_MCH_REF
DDRA_SDQS0#5
1 1
2 2
3 3
4 4
DDRA_SDQS05
DDRA_SDQS1#5
DDRA_SDQS15
DDRA_SDQS2#5
DDRA_SDQS25
DDRA_CKE05
DDRA_SBS2#5
DDRA_SBS0#5
DDRA_SWE#5
DDRA_SCAS#5
DDRA_SCS1#5
DDRA_ODT15
DDRA_SDQS4#5
DDRA_SDQS45
DDRA_SDQS6#5
DDRA_SDQS65
ICH_SMBDATA09,23,28,36
ICH_SMBCLK09,23,28,36
DDRA_SDQ0
DDRA_SDQ1
DDRA_SDQS0#
DDRA_SDQS0
DDRA_SDQ2
DDRA_SDQ3
DDRA_SDQ8
DDRA_SDQ9
DDRA_SDQS1#
DDRA_SDQS1
DDRA_SDQ10
DDRA_SDQ11
DDRA_SDQ16
DDRA_SDQ17
DDRA_SDQS2#
DDRA_SDQS2
DDRA_SDQ18
DDRA_SDQ19
DDRA_SDQ24
DDRA_SDQ25 DDRA_SDQ29
DDRA_SDM3
DDRA_SDQ26
DDRA_SDQ27
DDRA_SBS2#
DDRA_SMA12
DDRA_SMA9
DDRA_SMA8
DDRA_SMA5
DDRA_SMA3
DDRA_SMA1
DDRA_SMA10
DDRA_SBS0#
DDRA_SWE#
DDRA_SCAS#
DDRA_SCS1#
DDRA_ODT1
DDRA_SDQ32
DDRA_SDQ33
DDRA_SDQS4#
DDRA_SDQS4
DDRA_SDQ34
DDRA_SDQ35
DDRA_SDQ40
DDRA_SDQ41
DDRA_SDM5
DDRA_SDQ42
DDRA_SDQ43
DDRA_SDQ48
DDRA_SDQ49
DDRA_SDQS6#
DDRA_SDQS6
DDRA_SDQ50
DDRA_SDQ51
DDRA_SDQ56
DDRA_SDQ57
DDRA_SDM7
DDRA_SDQ58
DDRA_SDQ59
ICH_SMBDATA0
ICH_SMBCLK0
+3VS
+3VS
1
VREF
3
VSS
5
DQ0
7
DQ1
9
VSS
11
DQS0#
13
DQS0
15
VSS
17
DQ2
19
DQ3
21
VSS
23
DQ8
25
DQ9
27
VSS
29
DQS1#
31
DQS1
33
VSS
35
DQ10
37
DQ11
39
VSS
41
VSS
43
DQ16
45
DQ17
47
VSS
49
DQS2#
51
DQS2
53
VSS
55
DQ18
57
DQ19
59
VSS
61
DQ24
63
DQ25
65
VSS
67
DM3
69
NC
71
VSS
73
DQ26
75
DQ27
77
VSS
79
CKE0
81
VDD
83
NC
85
BA2
87
VDD
89
A12
91
A9
93
A8
95
VDD
97
A5
99
A3
101
A1
103
VDD
105
A10/AP
107
BA0
109
WE#
111
VDD
113
CAS#
115
NC/S1#
117
VDD
119
NC/ODT1
121
VSS
123
DQ32
125
DQ33
127
VSS
129
DQS4#
131
DQS4
133
VSS
135
DQ34
137
DQ35
139
VSS
141
DQ40
143
DQ41
145
VSS
147
DM5
149
VSS
151
DQ42
153
DQ43
155
VSS
157
DQ48
159
DQ49
161
VSS
163
NC,TEST
165
VSS
167
DQS6#
169
DQS6
171
VSS
173
DQ50
175
DQ51
177
VSS
179
DQ56
181
DQ57
183
VSS
185
DM7
187
VSS
189
DQ58
191
DQ59
193
VSS
195
SDA
197
SCL
199
VDDSPD
203
GND
FOX_AS0A426-M2RN-7F
FOX_AS0A426-M2RN-7F
CONN@
CONN@
VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0#
VSS
DQ14
DQ15
VSS
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
VDD
VDD
RAS#
VDD
ODT0
NC/A13
VDD
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SAO
GND
CK0
BA1
CK1
SA1
B
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
NC
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
A11
92
A7
94
A6
96
98
A4
100
A2
102
A0
104
106
108
110
S0#
112
114
116
118
120
NC
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
204
DDRA_SDQ4
DDRA_SDQ5
DDRA_SDM0
DDRA_SDQ6
DDRA_SDQ7
DDRA_SDQ12
DDRA_SDQ13
DDRA_SDM1
DDRA_SDQ14
DDRA_SDQ15
DDRA_SDQ20
DDRA_SDQ21
DDRA_SDM2
DDRA_SDQ22
DDRA_SDQ23
DDRA_SDQ28
DDRA_SDQS3#
DDRA_SDQS3
DDRA_SDQ30
DDRA_SDQ31
DDRA_CKE1DDRA_CKE0
DDRA_SMA15
DDRA_SMA14
DDRA_SMA11
DDRA_SMA7
DDRA_SMA6
DDRA_SMA4
DDRA_SMA2
DDRA_SMA0
DDRA_SBS1#
DDRA_SRAS#
DDRA_SCS0#
DDRA_ODT0
DDRA_SMA13
DDRA_SDQ36
DDRA_SDQ37
DDRA_SDM4
DDRA_SDQ38
DDRA_SDQ39
DDRA_SDQ44
DDRA_SDQ45
DDRA_SDQS5#
DDRA_SDQS5
DDRA_SDQ46
DDRA_SDQ47
DDRA_SDQ52
DDRA_SDQ53
DDRA_SDM6
DDRA_SDQ54
DDRA_SDQ55
DDRA_SDQ60
DDRA_SDQ61
DDRA_SDQS7#
DDRA_SDQS7
DDRA_SDQ62
DDRA_SDQ63
R39 10K_0402_5%R39 10K_0402_5%
1 2
R36 10K_0402_5%R36 10K_0402_5%
1 2
DDRA_CLK0 5
DDRA_CLK0# 5
DDRA_SDQS3# 5
DDRA_SDQS3 5
DDRA_CKE1 5
DDRA_SBS1# 5
DDRA_SRAS# 5
DDRA_SCS0# 5
DDRA_ODT0 5
DDRA_SDQS5# 5
DDRA_SDQS5 5
DDRA_CLK1 5
DDRA_CLK1# 5
DDRA_SDQS7# 5
DDRA_SDQS7 5
C
DDRA_SDQ[0..63]
DDRA_SDM[0..7]
DDRA_SMA[0..15]
+V_DDR_MCH_REF
1
C392
C392
2
1000P_0402_25V8J
1000P_0402_25V8J
1
C394
C394
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
DDRA_SDQ[0..63] 5
DDRA_SDM[0..7] 5
DDRA_SMA[0..15] 5
+1.8V
R147
R147
1K_0402_1%
1K_0402_1%
1 2
R148
R148
1K_0402_1%
1K_0402_1%
1 2
+V_DDR_MCH_REF
D
DDRA_SMA6
DDRA_SMA7
DDRA_SMA11
DDRA_SMA15
DDRA_CKE0
DDRA_SBS2#
DDRA_SMA14
DDRA_CKE1
DDRA_SBS1#
DDRA_SMA0
DDRA_SMA2
DDRA_SMA4
DDRA_SMA5
DDRA_SMA8
DDRA_SMA9
DDRA_SMA12
DDRA_SBS0#
DDRA_SMA10
DDRA_SMA1
DDRA_SMA3
DDRA_SCS1#
DDRA_ODT1
DDRA_SWE#
DDRA_SCAS#
DDRA_SMA13
DDRA_ODT0
DDRA_SCS0#
DDRA_SRAS#
RP10
RP10
1 8
2 7
3 6
4 5
47_0804_8P4R_5%
47_0804_8P4R_5%
RP13
RP13
47_0804_8P4R_5%
47_0804_8P4R_5%
RP8
RP8
1 8
2 7
3 6
4 5
47_0804_8P4R_5%
47_0804_8P4R_5%
RP9
RP9
47_0804_8P4R_5%
47_0804_8P4R_5%
RP7
RP7
47_0804_8P4R_5%
47_0804_8P4R_5%
RP4
RP4
47_0804_8P4R_5%
47_0804_8P4R_5%
RP3
RP3
1 8
2 7
3 6
4 5
47_0804_8P4R_5%
47_0804_8P4R_5%
DVT(EMI)
+1.8V
C174 0.1U_0402_16V4ZC174 0.1U_0402_16V4Z
C175 0.1U_0402_16V4ZC175 0.1U_0402_16V4Z
C176 0.1U_0402_16V4ZC176 0.1U_0402_16V4Z
+0.9V
C182 0.1U_0402_16V4ZC182 0.1U_0402_16V4Z
C198 0.1U_0402_16V4ZC198 0.1U_0402_16V4Z
18
C225 0.1U_0402_16V4ZC225 0.1U_0402_16V4Z
27
36
C223 0.1U_0402_16V4ZC223 0.1U_0402_16V4Z
45
C159 0.1U_0402_16V4ZC159 0.1U_0402_16V4Z
C167 0.1U_0402_16V4ZC167 0.1U_0402_16V4Z
18
C179 0.1U_0402_16V4ZC179 0.1U_0402_16V4Z
27
36
C185 0.1U_0402_16V4ZC185 0.1U_0402_16V4Z
45
18
C169 0.1U_0402_16V4ZC169 0.1U_0402_16V4Z
27
36
C161 0.1U_0402_16V4ZC161 0.1U_0402_16V4Z
45
18
C157 0.1U_0402_16V4ZC157 0.1U_0402_16V4Z
27
36
C142 0.1U_0402_16V4ZC142 0.1U_0402_16V4Z
45
C145 0.1U_0402_16V4ZC145 0.1U_0402_16V4Z
C135 0.1U_0402_16V4ZC135 0.1U_0402_16V4Z
1 2
1 2
1 2
E
+1.8V
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1
C67
C67
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
2.2U_0805_10V6K
2.2U_0805_10V6K
A
1
C63
C63
2
DIMM1 REV H:5.2mm (BOT)
B
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2008/10/06 2009/10/06
2008/10/06 2009/10/06
2008/10/06 2009/10/06
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
DDRII SO-DIMM 1
DDRII SO-DIMM 1
DDRII SO-DIMM 1
KBLG0 LA-4921P
KBLG0 LA-4921P
KBLG0 LA-4921P
E
8 57Thursday, February 19, 2009
8 57Thursday, February 19, 2009
8 57Thursday, February 19, 2009
0.1
0.1
0.1
A
B
C
D
E
+V_DDR_MCH_REF
1
C390
C390
2
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
1 1
2 2
3 3
4 4
DDRB_SDQS0#5
DDRB_SDQS05
DDRB_SDQS1#5
DDRB_SDQS15
DDRB_SDQS2#5
DDRB_SDQS25
DDRB_CKE05
DDRB_SBS2#5
DDRB_SBS0#5
DDRB_SWE#5
DDRB_SCAS#5
DDRB_SCS1#5
DDRB_ODT15
DDRB_SDQS4#5
DDRB_SDQS45
DDRB_SDQS6#5
DDRB_SDQS65
ICH_SMBDATA08,23,28,36
ICH_SMBCLK08,23,28,36
DDRB_SDQ0
DDRB_SDQ1
DDRB_SDQS0#
DDRB_SDQS0
DDRB_SDQ2
DDRB_SDQ3
DDRB_SDQ8
DDRB_SDQ9
DDRB_SDQS1#
DDRB_SDQS1
DDRB_SDQ10
DDRB_SDQ11
DDRB_SDQ16
DDRB_SDQ17
DDRB_SDQS2#
DDRB_SDQS2
DDRB_SDQ18
DDRB_SDQ19
DDRB_SDQ24
DDRB_SDQ25
DDRB_SDM3
DDRB_SDQ26 DDRB_SDQ30
DDRB_SDQ27
DDRB_CKE0
DDRB_SBS2#
DDRB_SMA12
DDRB_SMA9
DDRB_SMA8
DDRB_SMA5
DDRB_SMA3
DDRB_SMA1
DDRB_SMA10
DDRB_SBS0#
DDRB_SWE#
DDRB_SCAS#
DDRB_SCS1#
DDRB_ODT1
DDRB_SDQ32
DDRB_SDQ33
DDRB_SDQS4#
DDRB_SDQS4
DDRB_SDQ34
DDRB_SDQ35
DDRB_SDQ40
DDRB_SDQ41
DDRB_SDM5
DDRB_SDQ42
DDRB_SDQ43
DDRB_SDQ48
DDRB_SDQ49
DDRB_SDQS6#
DDRB_SDQS6
DDRB_SDQ50
DDRB_SDQ51
DDRB_SDQ56
DDRB_SDQ57
DDRB_SDM7
DDRB_SDQ58
DDRB_SDQ59
ICH_SMBDATA0
ICH_SMBCLK0
+3VS
+1.8V
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
JDIMM2
JDIMM2
1
VREF
3
VSS
5
DQ0
7
DQ1
9
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD
GND
FOX_AS0A426-MARG-7F
FOX_AS0A426-MARG-7F
CONN@
CONN@
NC/CKE1
DIMM2 REV H:9.2mm (BOT)
A
VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0#
VSS
DQ14
DQ15
VSS
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
VDD
NC/A15
NC/A14
VDD
VDD
VDD
RAS#
VDD
ODT0
NC/A13
VDD
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SAO
GND
CK0
BA1
CK1
SA1
+1.8V
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
NC
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
A11
92
A7
94
A6
96
98
A4
100
A2
102
A0
104
106
108
110
S0#
112
114
116
118
120
NC
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
B
DDRB_SDQ4
DDRB_SDQ5
DDRB_SDM0
DDRB_SDQ6
DDRB_SDQ7
DDRB_SDQ12
DDRB_SDQ13
DDRB_SDM1
DDRB_SDQ14
DDRB_SDQ15
DDRB_SDQ20
DDRB_SDQ21
DDRB_SDM2
DDRB_SDQ22
DDRB_SDQ23
DDRB_SDQ28
DDRB_SDQ29
DDRB_SDQS3#
DDRB_SDQS3
DDRB_SDQ31
DDRB_CKE1
DDRB_SMA15
DDRB_SMA14
DDRB_SMA11
DDRB_SMA7
DDRB_SMA6
DDRB_SMA4
DDRB_SMA2
DDRB_SMA0
DDRB_SBS1#
DDRB_SRAS#
DDRB_SCS0#
DDRB_ODT0
DDRB_SMA13
DDRB_SDQ36
DDRB_SDQ37
DDRB_SDM4
DDRB_SDQ38
DDRB_SDQ39
DDRB_SDQ44
DDRB_SDQ45
DDRB_SDQS5#
DDRB_SDQS5
DDRB_SDQ46
DDRB_SDQ47
DDRB_SDQ52
DDRB_SDQ53
DDRB_SDM6
DDRB_SDQ54
DDRB_SDQ55
DDRB_SDQ60
DDRB_SDQ61
DDRB_SDQS7#
DDRB_SDQS7
DDRB_SDQ62
DDRB_SDQ63
R37 10K_0402_5%R37 10K_0402_5%
1 2
R35 10K_0402_5%R35 10K_0402_5%
1 2
DDRB_CLK0 5
DDRB_CLK0# 5
DDRB_SDQS3# 5
DDRB_SDQS3 5
DDRB_CKE1 5
DDRB_SBS1# 5
DDRB_SRAS# 5
DDRB_SCS0# 5
DDRB_ODT0 5
DDRB_SDQS5# 5
DDRB_SDQS5 5
DDRB_CLK1 5
DDRB_CLK1# 5
DDRB_SDQS7# 5
DDRB_SDQS7 5
+3VS
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
DDRB_SDQ[0..63]
DDRB_SDM[0..7]
DDRB_SMA[0..15]
2008/10/06 2009/10/06
2008/10/06 2009/10/06
2008/10/06 2009/10/06
DDRB_SDQ[0..63] 5
DDRB_SDM[0..7] 5
DDRB_SMA[0..15] 5
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
DDRB_SRAS#
DDRB_SMA0
DDRB_SMA2
DDRB_SMA4
DDRB_SMA6
DDRB_SMA7
DDRB_SMA11
DDRB_SMA14
DDRB_CKE0
DDRB_SBS2#
DDRB_SMA15
DDRB_CKE1
DDRB_SMA8
DDRB_SMA5
DDRB_SMA12
DDRB_SMA9
DDRB_SBS0#
DDRB_SMA10
DDRB_SMA3
DDRB_SMA1
DDRB_ODT1
DDRB_SCS1#
DDRB_SWE#
DDRB_SCAS#
DDRB_SMA13
DDRB_ODT0
DDRB_SCS0#
DDRB_SBS1#
D
RP6
RP6
1 8
2 7
3 6
4 5
47_0804_8P4R_5%
47_0804_8P4R_5%
RP12
RP12
1 8
2 7
3 6
4 5
47_0804_8P4R_5%
47_0804_8P4R_5%
RP14
RP14
47_0804_8P4R_5%
47_0804_8P4R_5%
RP11
RP11
47_0804_8P4R_5%
47_0804_8P4R_5%
RP5
RP5
47_0804_8P4R_5%
47_0804_8P4R_5%
RP1
RP1
47_0804_8P4R_5%
47_0804_8P4R_5%
RP2
RP2
1 8
2 7
3 6
4 5
47_0804_8P4R_5%
47_0804_8P4R_5%
+0.9V
18
27
36
45
18
27
36
45
18
27
36
45
18
27
36
45
12
C171 0.1U_0402_16V4ZC171 0.1U_0402_16V4Z
1 2
C201 0.1U_0402_16V4ZC201 0.1U_0402_16V4Z
12
C180 0.1U_0402_16V4ZC180 0.1U_0402_16V4Z
1 2
C224 0.1U_0402_16V4ZC224 0.1U_0402_16V4Z
12
C200 0.1U_0402_16V4ZC200 0.1U_0402_16V4Z
1 2
C231 0.1U_0402_16V4ZC231 0.1U_0402_16V4Z
12
C183 0.1U_0402_16V4ZC183 0.1U_0402_16V4Z
1 2
C197 0.1U_0402_16V4ZC197 0.1U_0402_16V4Z
12
C146 0.1U_0402_16V4ZC146 0.1U_0402_16V4Z
1 2
C170 0.1U_0402_16V4ZC170 0.1U_0402_16V4Z
12
C122 0.1U_0402_16V4ZC122 0.1U_0402_16V4Z
1 2
C117 0.1U_0402_16V4ZC117 0.1U_0402_16V4Z
12
C147 0.1U_0402_16V4ZC147 0.1U_0402_16V4Z
1 2
C118 0.1U_0402_16V4ZC118 0.1U_0402_16V4Z
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
DDRII SO-DIMM 2
DDRII SO-DIMM 2
DDRII SO-DIMM 2
+1.8V
KBLG0 LA-4921P
KBLG0 LA-4921P
KBLG0 LA-4921P
E
9 57Thursday, February 19, 2009
9 57Thursday, February 19, 2009
9 57Thursday, February 19, 2009
0.1
0.1
0.1
A
B
C
D
E
PCIE_GTX_C_MRX_P[0..15]14
PCIE_GTX_C_MRX_N[0..15]14
1 1
2 2
PCIE_PTX_C_IRX_P236
PCIE_PTX_C_IRX_N236
PCIE_PTX_C_IRX_P334
PCIE_PTX_C_IRX_N334
PCIE_PTX_C_IRX_P433
PCIE_PTX_C_IRX_N433
PCIE_GTX_C_MRX_P[0..15]
PCIE_GTX_C_MRX_N[0..15]
PCIE_GTX_C_MRX_P0
PCIE_GTX_C_MRX_N0
PCIE_GTX_C_MRX_N1
PCIE_GTX_C_MRX_P1
PCIE_GTX_C_MRX_P2
PCIE_GTX_C_MRX_N2
PCIE_GTX_C_MRX_P3
PCIE_GTX_C_MRX_N3
PCIE_GTX_C_MRX_P4
PCIE_GTX_C_MRX_N4
PCIE_GTX_C_MRX_P5
PCIE_GTX_C_MRX_N5
PCIE_GTX_C_MRX_N6
PCIE_GTX_C_MRX_P6
PCIE_GTX_C_MRX_P7
PCIE_GTX_C_MRX_N7
PCIE_GTX_C_MRX_P8
PCIE_GTX_C_MRX_N8
PCIE_GTX_C_MRX_P9
PCIE_GTX_C_MRX_N9
PCIE_GTX_C_MRX_P10
PCIE_GTX_C_MRX_N10
PCIE_GTX_C_MRX_P11
PCIE_GTX_C_MRX_N11
PCIE_GTX_C_MRX_P12
PCIE_GTX_C_MRX_N12
PCIE_GTX_C_MRX_P13
PCIE_GTX_C_MRX_N13
PCIE_GTX_C_MRX_P14
PCIE_GTX_C_MRX_N14
PCIE_GTX_C_MRX_P15
PCIE_GTX_C_MRX_N15
SB_RX0P27
SB_RX0N27
SB_RX1P27
SB_RX1N27
SB_RX2P27
SB_RX2N27
SB_RX3P27
SB_RX3N27
U3B
U3B
D4
GFX_RX0P
C4
GFX_RX0N
A3
GFX_RX1P
B3
GFX_RX1N
C2
GFX_RX2P
C1
GFX_RX2N
E5
GFX_RX3P
F5
GFX_RX3N
G5
GFX_RX4P
G6
GFX_RX4N
H5
GFX_RX5P
H6
GFX_RX5N
J6
GFX_RX6P
J5
GFX_RX6N
J7
GFX_RX7P
J8
GFX_RX7N
L5
GFX_RX8P
L6
GFX_RX8N
M8
GFX_RX9P
L8
GFX_RX9N
P7
GFX_RX10P
M7
GFX_RX10N
P5
GFX_RX11P
M5
GFX_RX11N
R8
GFX_RX12P
P8
GFX_RX12N
R6
GFX_RX13P
R5
GFX_RX13N
P4
GFX_RX14P
P3
GFX_RX14N
T4
GFX_RX15P
T3
GFX_RX15N
AE3
GPP_RX0P
AD4
GPP_RX0N
AE2
GPP_RX1P
AD3
GPP_RX1N
AD1
GPP_RX2P
AD2
GPP_RX2N
V5
GPP_RX3P
W6
GPP_RX3N
U5
GPP_RX4P
U6
GPP_RX4N
U8
GPP_RX5P
U7
GPP_RX5N
AA8
SB_RX0P
Y8
SB_RX0N
AA7
SB_RX1P
Y7
SB_RX1N
AA5
SB_RX2P
AA6
SB_RX2N
W5
SB_RX3P
Y5
SB_RX3N
RS780M_FCBGA528
RS780M_FCBGA528
PART 2 OF 6
PART 2 OF 6
PCIE I/F GPP
PCIE I/F GPP
PCIE I/F SB
PCIE I/F SB
PCE_CALRP(PCE_BCALR P)
PCE_CALRN(PCE_BCALR N)
GFX_TX0P
GFX_TX0N
GFX_TX1P
GFX_TX1N
GFX_TX2P
GFX_TX2N
GFX_TX3P
GFX_TX3N
GFX_TX4P
GFX_TX4N
GFX_TX5P
GFX_TX5N
GFX_TX6P
GFX_TX6N
GFX_TX7P
GFX_TX7N
GFX_TX8P
GFX_TX8N
GFX_TX9P
GFX_TX9N
GFX_TX10P
GFX_TX10N
GFX_TX11P
GFX_TX11N
GFX_TX12P
GFX_TX12N
GFX_TX13P
GFX_TX13N
GFX_TX14P
GFX_TX14N
GFX_TX15P
GFX_TX15N
PCIE I/F GFX
PCIE I/F GFX
GPP_TX0P
GPP_TX0N
GPP_TX1P
GPP_TX1N
GPP_TX2P
GPP_TX2N
GPP_TX3P
GPP_TX3N
GPP_TX4P
GPP_TX4N
GPP_TX5P
GPP_TX5N
SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N
PCIE_MTX_GRX_P0 PCIE_MTX_C_GRX_P0
A5
B5
PCIE_MTX_GRX_P1
A4
PCIE_MTX_GRX_N1 PCIE_MTX_C_GRX_N1
B4
PCIE_MTX_GRX_P2
C3
PCIE_MTX_GRX_N2
B2
PCIE_MTX_GRX_P3
D1
PCIE_MTX_GRX_N3
D2
PCIE_MTX_GRX_P4
E2
PCIE_MTX_GRX_N4
E1
PCIE_MTX_GRX_P5
F4
PCIE_MTX_GRX_N5 PCIE_MTX_C_GRX_N5
F3
PCIE_MTX_GRX_P6
F1
PCIE_MTX_GRX_N6
F2
PCIE_MTX_GRX_P7
H4
PCIE_MTX_GRX_N7 PCIE_MTX_C_GRX_N7
H3
PCIE_MTX_GRX_P8
H1
PCIE_MTX_GRX_N8 PCIE_MTX_C_GRX_N8
H2
PCIE_MTX_GRX_P9
J2
PCIE_MTX_GRX_N9
J1
PCIE_MTX_GRX_P10 PCIE_MTX_C_GRX_P10
K4
PCIE_MTX_GRX_N10
K3
PCIE_MTX_GRX_P11
K1
PCIE_MTX_GRX_N11
K2
PCIE_MTX_GRX_P12
M4
PCIE_MTX_GRX_N12
M3
PCIE_MTX_GRX_P13
M1
PCIE_MTX_GRX_N13 PCIE_MTX_C_GRX_N13
M2
PCIE_MTX_GRX_P14
N2
PCIE_MTX_GRX_N14
N1
PCIE_MTX_GRX_P15
P1
PCIE_MTX_GRX_N15 PCIE_MTX_C_GRX_N15
P2
AC1
AC2
AB4
AB3
PCIE_ITX_PRX_P2
AA2
PCIE_ITX_PRX_N2
AA1
PCIE_ITX_PRX_P3
Y1
PCIE_ITX_PRX_N3
Y2
PCIE_ITX_PRX_P4
Y4
PCIE_ITX_PRX_N4
Y3
V1
V2
SB_TX0P_C
AD7
SB_TX0N_C
AE7
SB_TX1P_C
AE6
SB_TX1N_C
AD6
SB_TX2P_C
AB6
SB_TX2N_C
AC6
SB_TX3P_C
AD5
SB_TX3N_C
AE5
AC8
AB8
R32 1.27K_0402_1%R32 1.27K_0402_1%
R267 2K_0402_1%R267 2K_0402_1%
RS780M Display Port Support (muxed on GFX)
DP0
3 3
4 4
DP1
GFX_TX0,TX1,TX2 and TX3
AUX0 and HPD0
GFX_TX4,TX5,TX6 and TX7
AUX1 and HPD1
PCIE_MTX_C_GRX_P[0..15]
PCIE_MTX_C_GRX_N[0..15]
C646 0.1U_0402_16V7KVGA@C646 0.1U_0402_16V7KVGA@
1 2
C648 0.1U_0402_16V7KVGA@C648 0.1U_0402_16V7KVGA@
1 2
C650 0.1U_0402_16V7KVGA@C650 0.1U_0402_16V7KVGA@
1 2
C652 0.1U_0402_16V7KVGA@C652 0.1U_0402_16V7KVGA@
1 2
C655 0.1U_0402_16V7KVGA@C655 0.1U_0402_16V7KVGA@
1 2
C657 0.1U_0402_16V7KVGA@C657 0.1U_0402_16V7KVGA@
1 2
C659 0.1U_0402_16V7KVGA@C659 0.1U_0402_16V7KVGA@
1 2
C641 0.1U_0402_16V7KVGA@C641 0.1U_0402_16V7KVGA@
1 2
C636 0.1U_0402_16V7KVGA@C636 0.1U_0402_16V7KVGA@
1 2
C635 0.1U_0402_16V7KVGA@C635 0.1U_0402_16V7KVGA@
1 2
C632 0.1U_0402_16V7KVGA@C632 0.1U_0402_16V7KVGA@
1 2
C630 0.1U_0402_16V7KVGA@C630 0.1U_0402_16V7KVGA@
1 2
C627 0.1U_0402_16V7KVGA@C627 0.1U_0402_16V7KVGA@
1 2
C623 0.1U_0402_16V7KVGA@C623 0.1U_0402_16V7KVGA@
1 2
C624 0.1U_0402_16V7KVGA@C624 0.1U_0402_16V7KVGA@
1 2
C619 0.1U_0402_16V7KVGA@C619 0.1U_0402_16V7KVGA@
1 2
C617 0.1U_0402_16V7KC617 0.1U_0402_16V7K
1 2
C618 0.1U_0402_16V7KC618 0.1U_0402_16V7K
1 2
C614 0.1U_0402_16V7KC614 0.1U_0402_16V7K
1 2
C613 0.1U_0402_16V7KC613 0.1U_0402_16V7K
1 2
C46 0.1U_0402_16V7K
C46 0.1U_0402_16V7K
1 2
C42 0.1U_0402_16V7K
C42 0.1U_0402_16V7K
1 2
@
@
@
@
MP
C615 0.1U_0 402_16V7KC615 0.1U_0 402_16V7K
1 2
C609 0.1U_0 402_16V7KC609 0.1U_0 402_16V7K
1 2
C38 0.1U_0402_16V7KC38 0.1U_0402_16V 7K
1 2
C33 0.1U_0402_16V7KC33 0.1U_0402_16V 7K
1 2
C37 0.1U_0402_16V7KC37 0.1U_0402_16V 7K
1 2
C32 0.1U_0402_16V7KC32 0.1U_0402_16V 7K
1 2
C610 0.1U_0 402_16V7KC610 0.1U_0 402_16V7K
1 2
C616 0.1U_0 402_16V7KC616 0.1U_0 402_16V7K
1 2
1 2
1 2
C647 0.1U_0402_16V7KVGA@C647 0.1U_0402_16V7KVGA@
C649 0.1U_0402_16V7KVGA@C649 0.1U_0402_16V7KVGA@
C651 0.1U_0402_16V7KVGA@C651 0.1U_0402_16V7KVGA@
C653 0.1U_0402_16V7KVGA@C653 0.1U_0402_16V7KVGA@
C654 0.1U_0402_16V7KVGA@C654 0.1U_0402_16V7KVGA@
C656 0.1U_0402_16V7KVGA@C656 0.1U_0402_16V7KVGA@
C658 0.1U_0402_16V7KVGA@C658 0.1U_0402_16V7KVGA@
C642 0.1U_0402_16V7KVGA@C642 0.1U_0402_16V7KVGA@
C638 0.1U_0402_16V7KVGA@C638 0.1U_0402_16V7KVGA@
C637 0.1U_0402_16V7KVGA@C637 0.1U_0402_16V7KVGA@
C634 0.1U_0402_16V7KVGA@C634 0.1U_0402_16V7KVGA@
C631 0.1U_0402_16V7KVGA@C631 0.1U_0402_16V7KVGA@
C629 0.1U_0402_16V7KVGA@C629 0.1U_0402_16V7KVGA@
C625 0.1U_0402_16V7KVGA@C625 0.1U_0402_16V7KVGA@
C620 0.1U_0402_16V7KVGA@C620 0.1U_0402_16V7KVGA@
C621 0.1U_0402_16V7KVGA@C621 0.1U_0402_16V7KVGA@
+1.1VS
PCIE_MTX_C_GRX_P[0..15] 14
PCIE_MTX_C_GRX_N[0..15] 14
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
PCIE_ITX_C_PRX_P2 36
PCIE_ITX_C_PRX_N2 36
PCIE_ITX_C_PRX_P3 34
PCIE_ITX_C_PRX_N3 34
PCIE_ITX_C_PRX_P4 33
PCIE_ITX_C_PRX_N4 33
SB_TX0P 27
SB_TX0N 27
SB_TX1P 27
SB_TX1N 27
SB_TX2P 27
SB_TX2N 27
SB_TX3P 27
SB_TX3N 27
PCIE_MTX_C_GRX_N0PCIE_MTX_GRX_N0
PCIE_MTX_C_GRX_P1
PCIE_MTX_C_GRX_P2
PCIE_MTX_C_GRX_N2
PCIE_MTX_C_GRX_P3
PCIE_MTX_C_GRX_N3
PCIE_MTX_C_GRX_P4
PCIE_MTX_C_GRX_N4
PCIE_MTX_C_GRX_P5
PCIE_MTX_C_GRX_P6
PCIE_MTX_C_GRX_N6
PCIE_MTX_C_GRX_P7
PCIE_MTX_C_GRX_P8
PCIE_MTX_C_GRX_P9
PCIE_MTX_C_GRX_N9
PCIE_MTX_C_GRX_N10
PCIE_MTX_C_GRX_P11
PCIE_MTX_C_GRX_N11
PCIE_MTX_C_GRX_P12
PCIE_MTX_C_GRX_N12
PCIE_MTX_C_GRX_P13
PCIE_MTX_C_GRX_P14
PCIE_MTX_C_GRX_N14
PCIE_MTX_C_GRX_P15
DVT
New Card
WLAN
GLAN
Card Reader
H_CLKOP04
H_CLKON04
H_CLKOP14
H_CLKON14
H_CTLOP04
H_CTLON04
H_CTLON14
R56
R56
1 2
301_0402_1%~D
0718 Place within 1"
layout 1:2
301_0402_1%~D
PCIE_MTX_GRX_N[0..3]
PCIE_MTX_GRX_P[0..3]
H_CADOP[0..15]4
H_CADON[0..15]4 H_CADIN[0..15] 4
H_CADOP0
H_CADON0
H_CADOP1
H_CADON1
H_CADOP2
H_CADON2
H_CADOP3
H_CADON3
H_CADOP4
H_CADON4
H_CADOP5
H_CADON5
H_CADOP6
H_CADON6
H_CADOP7
H_CADON7
H_CADOP8
H_CADON8
H_CADOP9
H_CADON9
H_CADOP10
H_CADON10
H_CADOP11
H_CADON11
H_CADOP12
H_CADON12
H_CADOP13
H_CADON13
H_CADOP14
H_CADON14
H_CADOP15
H_CADON15
H_CTLOP0
H_CTLON0
H_CTLOP1
H_CTLON1
H_CADON[0..15]
Y25
Y24
V22
V23
V25
V24
U24
U25
T25
T24
P22
P23
P25
P24
N24
N25
AC24
AC25
AB25
AB24
AA24
AA25
Y22
Y23
W21
W20
V21
V20
U20
U21
U19
U18
T22
T23
AB23
AA22
M22
M23
R21
R20
C23
A24
PCIE_MTX_GRX_N[0..3] 25
PCIE_MTX_GRX_P[0..3] 25
U3A
U3A
HT_RXCAD0P
PART 1 OF 6
PART 1 OF 6
HT_RXCAD0N
HT_RXCAD1P
HT_RXCAD1N
HT_RXCAD2P
HT_RXCAD2N
HT_RXCAD3P
HT_RXCAD3N
HT_RXCAD4P
HT_RXCAD4N
HT_RXCAD5P
HT_RXCAD5N
HT_RXCAD6P
HT_RXCAD6N
HT_RXCAD7P
HT_RXCAD7N
HT_RXCAD8P
HT_RXCAD8N
HT_RXCAD9P
HT_RXCAD9N
HT_RXCAD10P
HT_RXCAD10N
HT_RXCAD11P
HT_RXCAD11N
HT_RXCAD12P
HT_RXCAD12N
HT_RXCAD13P
HT_RXCAD13N
HT_RXCAD14P
HT_RXCAD14N
HT_RXCAD15P
HT_RXCAD15N
HT_RXCLK0P
HT_RXCLK0N
HT_RXCLK1P
HT_RXCLK1N
HT_RXCTL0P
HT_RXCTL0N
HT_RXCTL1P
HT_RXCTL1N
HT_RXCALP
HT_RXCALN
RS780M_FCBGA528
RS780M_FCBGA528
HYPER TRANSPORT CPU I/F
HYPER TRANSPORT CPU I/F
H_CADIP[0..15]H_CADOP[0..15]
H_CADIN[0..15]
HT_TXCAD0P
HT_TXCAD0N
HT_TXCAD1P
HT_TXCAD1N
HT_TXCAD2P
HT_TXCAD2N
HT_TXCAD3P
HT_TXCAD3N
HT_TXCAD4P
HT_TXCAD4N
HT_TXCAD5P
HT_TXCAD5N
HT_TXCAD6P
HT_TXCAD6N
HT_TXCAD7P
HT_TXCAD7N
HT_TXCAD8P
HT_TXCAD8N
HT_TXCAD9P
HT_TXCAD9N
HT_TXCAD10P
HT_TXCAD10N
HT_TXCAD11P
HT_TXCAD11N
HT_TXCAD12P
HT_TXCAD12N
HT_TXCAD13P
HT_TXCAD13N
HT_TXCAD14P
HT_TXCAD14N
HT_TXCAD15P
HT_TXCAD15N
HT_TXCLK0P
HT_TXCLK0N
HT_TXCLK1P
HT_TXCLK1N
HT_TXCTL0P
HT_TXCTL0N
HT_TXCTL1P
HT_TXCTL1N
HT_TXCALP
HT_TXCALN
H_CADIP[0..15] 4
H_CADIP0
D24
H_CADIN0
D25
H_CADIP1
E24
H_CADIN1
E25
H_CADIP2
F24
H_CADIN2
F25
H_CADIP3
F23
H_CADIN3
F22
H_CADIP4
H23
H_CADIN4
H22
H_CADIP5
J25
H_CADIN5
J24
H_CADIP6
K24
H_CADIN6
K25
H_CADIP7
K23
H_CADIN7
K22
H_CADIP8
F21
H_CADIN8
G21
H_CADIP9
G20
H_CADIN9
H21
H_CADIP10
J20
H_CADIN10
J21
H_CADIP11
J18
H_CADIN11
K17
H_CADIP12
L19
H_CADIN12
J19
H_CADIP13
M19
H_CADIN13
L18
H_CADIP14
M21
H_CADIN14
P21
H_CADIP15
P18
H_CADIN15
M18
H24
H25
L21
L20
H_CTLIP0
M24
H_CTLIN0
M25
H_CTLIP1
P19
H_CTLIN1
R18
B24
B25
0718 Place within 1"
layout 1:2
SA00002DR30 S IC 216-0674026 A13 RS780MN FCBGA 0FA
H_CLKIP0 4
H_CLKIN0 4
H_CLKIP1 4
H_CLKIN1 4
H_CTLIP0 4
H_CTLIN0 4
H_CTLIP1 4H_CTLOP14
H_CTLIN1 4
R51
R51
1 2
301_0402_1%~D
301_0402_1%~D
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2008/10/06 2009/10/06
2008/10/06 2009/10/06
2008/10/06 2009/10/06
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
D
Date: Sheet of
Compal Electronics, Inc.
RS780-HT/PCIE
RS780-HT/PCIE
RS780-HT/PCIE
KBLG0 LA-4921P
KBLG0 LA-4921P
KBLG0 LA-4921P
E
0.1
0.1
10 57Wednesday, March 11, 2009
10 57Wednesday, March 11, 2009
10 57Wednesday, March 11, 2009
0.1
A
For RS780M A13
RED: Connected to GND through two separate 140ohm 1% resistor
+1.8VS
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
2
1
PLT_RST#13,14,24,27,33,34,36,38
NB_PWRGD28
+1.8VS
R283 300_0402_5%R283 300_0402_5%
@
@
1 2
R486 0_0402_5%
R486 0_0402_5%
1 2
R490 0_0402_5%
R490 0_0402_5%
@
@
+1.8VS
R60
R60
300_0402_5%
300_0402_5%
PUMA@
PUMA@
1 2
R59 0_0402_5%R5 9 0_0402_5%
GMCH_CRT_R
GMCH_CRT_G
GMCH_CRT_B
+1.8VS
1 2
+1.8VS
1 2
UMA@
UMA@
1 2
R45 14 0_0402_1%
R45 14 0_0402_1%
UMA@
UMA@
1 2
R49 15 0_0402_1%
R49 15 0_0402_1%
UMA@
UMA@
1 2
R50 15 0_0402_1%
1 1
+1.1VS
1 2
MBK2012221YZF 0805
MBK2012221YZF 0805
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
1 2
MBK2012221YZF 0805
MBK2012221YZF 0805
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
+1.8VS
1 2
MBK2012221YZF 0805
2 2
3 3
4 4
MBK2012221YZF 0805
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
+1.8VS
1 2
MBK2012221YZF 0805
MBK2012221YZF 0805
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
CLK_NB_14.318M
12
R477
R477
100_0402_5%
100_0402_5%
@
@
1
C854
C854
100P_0402_25V8K
100P_0402_25V8K
2
@
@
+3VS
R295 4.7K_0402_5%
R295 4.7K_0402_5%
R289 4.7K_0402_5%
R289 4.7K_0402_5%
PLLVDD=65mA
L59
L59
L13
L13
L9
L9
L14
L14
CPU_LDT_REQ#6
ALLOW_LDTSTOP27
+NB_PLLVDD
1
C645
C645
2
PLLVDD18=20mA
+NB_HTPVDD+1.8VS
1
C93
C93
2
VDDA18HTPLL=20mA
+VDDA18HTPLL
1
C66
C66
2
VDDA18PCIEPLL=0.12A
+VDDA18PCIEPLL
1
C87
C87
2
+1.1VS
PX_GPIO2_NB38
UMA@
UMA@
1 2
1 2
UMA@
UMA@
A
1
C663
C663
1U_0402_6.3V4Z
1U_0402_6.3V4Z
2
1
C84
C84
1U_0402_6.3V4Z
1U_0402_6.3V4Z
2
1
C72
C72
1U_0402_6.3V4Z
1U_0402_6.3V4Z
2
1
C86
C86
1U_0402_6.3V4Z
1U_0402_6.3V4Z
2
1 2
R293
R293
4.7K_0402_5%
4.7K_0402_5%
PX_GPIO224,26,38
Un-stuff for Tigris
R61 0_0402_5%
R61 0_0402_5%
1 2
1.5K_0402_5%
1.5K_0402_5%
GMCH_LCD_CLK
GMCH_LCD_DATA
PUMA@
PUMA@
R50 15 0_0402_1%
FBM-L11-201209-300LMA30T_0805
FBM-L11-201209-300LMA30T_0805
PVT
NB_PWRGD28
SB_PWRGD6,28,41
1 2
R290
R290
4.7K_0402_5%
4.7K_0402_5%
+3VS
12
R483
R483
@
@
DVT
B
+3VS
FBM-L11-201209-300LMA30T_0805
FBM-L11-201209-300LMA30T_0805
AVDDDI=20mA
L10
L10
1 2
FBM-L11-201209-300LMA30T_0805
FBM-L11-201209-300LMA30T_0805
AVDDQ=4mA
L8
L8
C61
C61
U50
U50
5
NC7SZ08P5X_NL_SC70-5
NC7SZ08P5X_NL_SC70-5
P
B
Y
A
G
3
12
POWER_SEL50
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+AVDDQ
1
2
GMCH_CRT_HSYNC13,26
GMCH_CRT_VSYNC13 ,26
4
R296 0_0402_5%R296 0_0402_5%
1 2
1 2
R511 0_0402_5%@R511 0_0402_5%@
CLK_NBGFX23
CLK_NBGFX#23
CLK_SBLINK_BCLK23
CLK_SBLINK_BCLK#23
GMCH_LCD_CLK24
GMCH_LCD_DATA24
+3VS
GMCH_CRT_CLK26
GMCH_CRT_DATA26
CLK_NB_14.318M23
PVT
C74
C74
POWER_SEL
HIGH 1.0V
1.1VLOW
Change as 1K_5% ohm
for Tigris
NB_ALLOW_LDTSTOP
B
AVDD=0.11A
L15
L15
1 2
C874
C874
1U_0402_6.3V4Z
1U_0402_6.3V4Z
+AVDD2
1
2
1
PVT
C875
C875
1U_0402_6.3V4Z
1U_0402_6.3V4Z
2
GMCH_CRT_R26
GMCH_CRT_G26
GMCH_CRT_B26
R42 715_0402_1%R42 715_0402_1%
1 2
+NB_PLLVDD
+NB_HTPVDD
+VDDA18HTPLL
+VDDA18PCIEPLL
CLK_NBHT23
CLK_NBHT#23
GMCH_LCD_CLK
GMCH_LCD_DATA
DVT
@
@
12
R288 10K_0402_5%
R288 10K_0402_5%
POWER_SEL
AUX_CAL13
Strap pin
PVT
+AVDD1
1
1
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
2
2
GMCH_CRT_R
GMCH_CRT_G
GMCH_CRT_B
GMCH_CRT_HSYNC
GMCH_CRT_VSYNC
GMCH_CRT_CLK
GMCH_CRT_DATA
+NB_PLLVDD
+NB_HTPVDD
NB_RESET#
NB_PWRGD_R
NB_LDTSTOP#
NB_ALLOW_LDTSTOP
CLK_NB_14.318M
GMCH_HDMI_DATA_R2
GMCH_HDMI_CLK_R2
GMCH_HDMI_CLK_R1
GMCH_HDMI_DATA_R1
DVT
GMCH_HDMI_CLK25
GMCH_HDMI_DATA25
C
C94
C94
U3C
U3C
F12
AVDD1(NC)
E12
AVDD2(NC)
F14
AVDDDI(NC)
G15
AVSSDI(NC)
H15
AVDDQ(NC)
H14
AVSSQ(NC)
E17
C_Pr(DFT_GPIO5)
F17
Y(DFT_GPIO2)
F15
COMP_Pb(DFT_GPIO4)
G18
RED(DFT_GPIO0)
G17
REDb(NC)
E18
GREEN(DFT_GPIO1)
F18
GREENb(NC)
E19
BLUE(DFT_GPIO3)
F19
BLUEb(NC)
A11
DAC_HSYNC(PWM_GPIO4)
B11
DAC_VSYNC(PWM_GPIO6)
F8
DAC_SCL(PCE_RCALRN)
E8
DAC_SDA(PCE_TCALRN)
G14
DAC_RSET(PWM_GPIO1)
A12
PLLVDD(NC)
D14
PLLVDD18(NC)
B12
PLLVSS(NC)
H17
VDDA18HTPLL
D7
VDDA18PCIEPLL1
E7
VDDA18PCIEPLL2
D8
SYSRESETb
A10
POWERGOOD
C10
LDTSTOPb
C12
ALLOW_LDTSTOP
C25
HT_REFCLKP
C24
HT_REFCLKN
E11
REFCLK_P/OSCIN(OSCIN)
F11
REFCLK_N(PWM_GPIO3)
T2
GFX_REFCLKP
T1
GFX_REFCLKN
U1
GPP_REFCLKP
U2
GPP_REFCLKN
V4
GPPSB_REFCLKP(SB_REFCLK P)
V3
GPPSB_REFCLKN(SB_REFCLK N)
B9
I2C_CLK
A9
I2C_DATA
B8
DDC_DATA0/AUX0N(NC)
A8
DDC_CLK0/AUX0P(NC)
B7
DDC_CLK1/AUX1P(NC)
A7
DDC_DATA1/AUX1N(NC)
B10
STRP_DATA
G11
RSVD
C8
AUX_CAL(NC)
RS780M_FCBGA528
RS780M_FCBGA528
GMCH_HDMI_CLK
GMCH_HDMI_DATA
LDT_STOP#6,27
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PART 3 OF 6
PART 3 OF 6
TXOUT_U1P(PCIE_RESET_GPIO3)
TXOUT_U1N(PCIE_RESET_GPIO2)
TXOUT_U3P(PCIE_RESET_GPIO5)
CRT/TVOUT
CRT/TVOUT
TXCLK_UP(PCIE_RESET_GPIO4)
TXCLK_UN(PCIE_RESET_GPIO1)
LVTM
LVTM
PM
PM
CLOCKs PLL PWR
CLOCKs PLL PWR
MIS.
MIS.
R491 0_0402_5%@R491 0_0402_5%@
1 2
R488 0_0402_5%UMA@R488 0_0402_5%UMA@
1 2
1 2
R489 0_0402_5%UMA@R489 0_0402_5%UMA@
1 2
R492 0_0402_5%@R492 0_0402_5%@
0_0402_5%
0_0402_5%
1 2
R280
R280
2008/10/06 2009/10/06
2008/10/06 2009/10/06
2008/10/06 2009/10/06
C
TXOUT_L0P(NC)
TXOUT_L0N(NC)
TXOUT_L1P(NC)
TXOUT_L1N(NC)
TXOUT_L2P(NC)
TXOUT_L2N(DBG_GPIO0)
TXOUT_L3P(NC)
TXOUT_L3N(DBG_GPIO2)
TXOUT_U0P(NC)
TXOUT_U0N(NC)
TXOUT_U2P(NC)
TXOUT_U2N(NC)
TXOUT_U3N(NC)
TXCLK_LP(DBG_GPIO1)
TXCLK_LN(DBG_GPIO3)
VDDLTP18(NC)
VSSLTP18(NC)
VDDLT18_1(NC)
VDDLT18_2(NC)
VDDLT33_1(NC)
VDDLT33_2(NC)
VSSLT1(VSS)
VSSLT2(VSS)
VSSLT3(VSS)
VSSLT4(VSS)
VSSLT5(VSS)
VSSLT6(VSS)
VSSLT7(VSS)
LVDS_DIGON(PCE_TCALRP)
LVDS_BLON(PCE_RCALRP)
LVDS_ENA_BL(PWM _GPIO2)
TMDS_HPD(NC)
SUS_STAT#(PWM_GPIO5)
THERMALDIODE_P
THERMALDIODE_N
GMCH_HDMI_CLK_R2
GMCH_HDMI_CLK_R1
GMCH_HDMI_DATA_R1
GMCH_HDMI_DATA_R2
NB_LDTSTOP#
Compal Secret Data
Compal Secret Data
Compal Secret Data
HPD(NC)
TESTMODE
Deciphered Date
Deciphered Date
Deciphered Date
A22
B22
A21
B21
B20
A20
A19
B19
B18
A18
A17
B17
D20
D21
D18
D19
B16
A16
D16
D17
A13
B13
A15
B15
A14
B14
C14
D15
C16
C18
C20
E20
C22
E9
F7
G12
1.27K_0402_1%
1.27K_0402_1%
D9
D10
D12
AE8
AD8
D13
+VDDLTP18
+VDDLT18
12
R469
R469
@
@
DVT
1 2
R297 0_0 402_5%R 297 0_0402_5%
1 2
R279
R279
1.8K_0402_5%
1.8K_0402_5%
D
GMCH_TXOUT0+ 24
GMCH_TXOUT0- 24
GMCH_TXOUT1+ 24
GMCH_TXOUT1- 24
GMCH_TXOUT2+ 24
GMCH_TXOUT2- 24
GMCH_TXCLK+ 24
GMCH_TXCLK- 24
UMA@
UMA@
R294
R294
1 2
D
1.27K_0402_1%
1.27K_0402_1%
R29
R29
1 2
UMA_ENVDD
NB_PWRGD
UMA_ENBKL
UMA@
UMA@
1.27K_0402_1%
1.27K_0402_1%
HDMI_DET 15,25
SUS_STAT# 28
SUS_STAT_R# 13
E
1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
UMA_ENVDD
UMA_ENBKL 38
UMA_DPST 24
VDDLTP18=15mA
+VDDLTP18
1
C665
C665
2
VDDLT18=0.3A
+VDDLT18
1
C90
C90
2
1
2
1
2
L56
L56
1 2
MBC1608121YZF_0603
MBC1608121YZF_0603
C644
C644
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
L12
L12
1 2
MBC1608121YZF_0603
MBC1608121YZF_0603
C95
C95
4.7U_0805_10V4Z
4.7U_0805_10V4Z
+1.8VS
+1.8VS
Strap pin
UMA@
UMA@
R744 0_0402_5%
R744 0_0402_5%
1 2
+3VS
C857 0.1U_ 0402_16V4Z
C857 0.1U_ 0402_16V4Z
@
@
5
PVT
2
P
B
4
Y
1
A
G
U48
U48
NC7SZ08P5X_NL_SC70-5
NC7SZ08P5X_NL_SC70-5
3
@
@
5
PVT
2
P
B
4
Y
1
A
G
U49
U49
NC7SZ08P5X_NL_SC70-5@
NC7SZ08P5X_NL_SC70-5@
3
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
RS780 VEDIO/CLK GEN
RS780 VEDIO/CLK GEN
RS780 VEDIO/CLK GEN
KBLG0 LA-4921P
KBLG0 LA-4921P
KBLG0 LA-4921P
E
DVT2
UMA_ENVDD_R 24
ENBKL 38
11 57Thursday, March 19, 2009
11 57Thursday, March 19, 2009
11 57Thursday, March 19, 2009
0.1
0.1
0.1
A
1 1
2 2
FOR Version A11 pop 1.35VS A12
use 1.2V_HT
3 3
4 4
+1.1VS
FBMA-L11-201209-221LMA30T_0805
FBMA-L11-201209-221LMA30T_0805
FBMA-L11-201209-221LMA30T_0805
FBMA-L11-201209-221LMA30T_0805
L4
+1.2V_HT
FBMA-L11-201209-221LMA30T_0805
FBMA-L11-201209-221LMA30T_0805
L4
+1.8VS
FBMA-L11-201209-221LMA30T_0805
FBMA-L11-201209-221LMA30T_0805
4.7U_0805_10V4Z
4.7U_0805_10V4Z
12
L5
L5
VDDHTRX+VDDHT=0.68A
L49
L49
12
4.7U_0805_10V4Z
4.7U_0805_10V4Z
L11
L11
12
C83
C83
4.7U_0805_10V4Z
4.7U_0805_10V4Z
VDDHTTX=0.68A
VDDA18PCIE=0.7A
12
1
C45
C45
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C75
C75
C612
C612
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
C82
C82
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C31
C31
C49
C49
2
4.7U_0805_10V4Z
4.7U_0805_10V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C40
C40
C47
C47
2
4.7U_0805_10V4Z
4.7U_0805_10V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1
1
C71
C71
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1
C85
C85
C91
C91
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
C50
C50
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
C51
C51
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+1.8VS
C89
C89
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1
C62
C62
2
1
2
1
C52
C52
C54
C54
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1
C48
C48
C73
C73
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
VDD18=10mA
1
2
+VDDHTRX
+VDDHT
+VDDHTTX
1
2
+VDDA18PCIE
1
2
B
U3E
U3E
J17
VDDHT_1
K16
VDDHT_2
L16
VDDHT_3
M16
VDDHT_4
P16
VDDHT_5
R16
VDDHT_6
T16
VDDHT_7
H18
VDDHTRX_1
G19
VDDHTRX_2
F20
VDDHTRX_3
E21
VDDHTRX_4
D22
VDDHTRX_5
B23
VDDHTRX_6
A23
VDDHTRX_7
AE25
VDDHTTX_1
AD24
VDDHTTX_2
AC23
VDDHTTX_3
AB22
VDDHTTX_4
AA21
VDDHTTX_5
Y20
VDDHTTX_6
W19
VDDHTTX_7
V18
VDDHTTX_8
U17
VDDHTTX_9
T17
VDDHTTX_10
R17
VDDHTTX_11
P17
VDDHTTX_12
M17
VDDHTTX_13
J10
VDDA18PCIE_1
P10
VDDA18PCIE_2
K10
VDDA18PCIE_3
M10
VDDA18PCIE_4
L10
VDDA18PCIE_5
W9
VDDA18PCIE_6
H9
VDDA18PCIE_7
T10
VDDA18PCIE_8
R10
VDDA18PCIE_9
Y9
VDDA18PCIE_10
AA9
VDDA18PCIE_11
AB9
VDDA18PCIE_12
AD9
VDDA18PCIE_13
AE9
VDDA18PCIE_14
U10
VDDA18PCIE_15
F9
VDD18_1
G9
VDD18_2
AE11
VDD18_MEM1(NC)
AD11
VDD18_MEM2(NC)
RS780M_FCBGA528
RS780M_FCBGA528
PART 5/6
PART 5/6
VDDPCIE_1
VDDPCIE_2
VDDPCIE_3
VDDPCIE_4
VDDPCIE_5
VDDPCIE_6
VDDPCIE_7
VDDPCIE_8
VDDPCIE_9
VDDPCIE_10
VDDPCIE_11
VDDPCIE_12
VDDPCIE_13
VDDPCIE_14
VDDPCIE_15
VDDPCIE_16
VDDPCIE_17
VDDC_1
VDDC_2
VDDC_3
VDDC_4
VDDC_5
VDDC_6
VDDC_7
VDDC_8
VDDC_9
VDDC_10
VDDC_11
VDDC_12
POWER
POWER
VDDC_13
VDDC_14
VDDC_15
VDDC_16
VDDC_17
VDDC_18
VDDC_19
VDDC_20
VDDC_21
VDDC_22
VDD_MEM1(NC)
VDD_MEM2(NC)
VDD_MEM3(NC)
VDD_MEM4(NC)
VDD_MEM5(NC)
VDD_MEM6(NC)
VDD33_1(NC)
VDD33_2(NC)
VDDPCIE=1.1A
A6
B6
C6
D6
E6
F6
G7
H8
J9
K9
M9
L9
P9
R9
T9
V9
U9
K12
J14
U16
J11
K15
M12
L14
L11
M13
M15
N12
N14
P11
P13
P14
R12
R15
T11
T15
U12
T14
J16
AE10
AA11
Y11
AD10
AB10
AC10
H11
H12
C
+VDDA11PCIE
C350.1U_0402_16V4Z C350.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1 2
FBMA-L11-201209-221LMA30T_0805
FBMA-L11-201209-221LMA30T_0805
C30 10U_0805_10V4ZC30 10U_0805_10V4Z
C28 10U_0805_10V4ZC28 10U_0805_10V4Z
C29 4.7U_0805_10V4ZC29 4.7U_08 05_10V4Z
C53 1U_0402_6.3V4ZC53 1U_0402_6.3V4Z
C79 1U_0402_6.3V4ZC79 1U_0402_6.3V4Z
C88 0.1U_0402_16V4ZC88 0.1U_04 02_16V4Z
C57 0.1U_0402_16V4ZC57 0.1U_04 02_16V4Z
VDDC=7.6A
DVT
C430.1U_0402_16V4Z C430.1U_0402_16V4Z
C690.1U_0402_16V4Z C690.1U_0402_16V4Z
C340.1U_0402_16V4Z C340.1U_0402_16V4Z
C600.1U_0402_16V4Z C600.1U_0402_16V4Z
1
1
1
1
1
2
2
2
2
2
1
C80
C80
C78
C78
2
L3
L3
1 2
1 2
1 2
1 2
1 2
1 2
1 2
VGA@
VGA@
1 2
L6 0_1206_5%
L6 0_1206_5%
1 2
L7 0_1206_5%
L7 0_1206_5%
VGA@
VGA@
C680.1U_0402_16V4Z C680.1U_0402_16V4Z
C640.1U_0402_16V4Z C640.1U_0402_16V4Z
C810.1U_0402_16V4Z C810.1U_0402_16V4Z
C760.1U_0402_16V4Z C760.1U_0402_16V4Z
1
1
1
1
2
2
2
2
VDD33=60mA
+3VS
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
D
U3F
U3F
A25
VSSAHT1
D23
VSSAHT2
E22
VSSAHT3
G22
VSSAHT4
G24
VSSAHT5
G25
VSSAHT6
H19
VSSAHT7
J22
VSSAHT8
L17
VSSAHT9
L22
VSSAHT10
L24
VSSAHT11
+1.1VS
+NB_CORE+1.1VS
C27 330U_D2E_2.5VM+C27 330U_D2E_2.5VM
1
C4410U_0805_10V4Z C4410U_0805_10V4Z
C3610U_0805_10V4Z C3610U_0805_10V4Z
1
1
+
2
2
2
L25
VSSAHT12
M20
VSSAHT13
N22
VSSAHT14
P20
VSSAHT15
R19
VSSAHT16
R22
VSSAHT17
R24
VSSAHT18
R25
VSSAHT19
H20
VSSAHT20
U22
VSSAHT21
V19
VSSAHT22
W22
VSSAHT23
W24
VSSAHT24
W25
VSSAHT25
Y21
VSSAHT26
AD25
VSSAHT27
L12
VSS11
M14
VSS12
N13
VSS13
P12
VSS14
P15
VSS15
R11
VSS16
R14
VSS17
T12
VSS18
U14
VSS19
U11
VSS20
U15
VSS21
V12
VSS22
W11
VSS23
W15
VSS24
AC12
VSS25
AA14
VSS26
Y18
VSS27
AB11
VSS28
AB15
VSS29
AB17
VSS30
AB19
VSS31
AE20
VSS32
AB21
VSS33
K11
VSS34
RS780M_FCBGA528
RS780M_FCBGA528
U3D
U3D
AB12
MEM_A0(NC)
AE16
MEM_A1(NC)
V11
MEM_A2(NC)
AE15
MEM_A3(NC)
AA12
MEM_A4(NC)
AB16
MEM_A5(NC)
AB14
MEM_A6(NC)
AD14
MEM_A7(NC)
AD13
MEM_A8(NC)
AD15
MEM_A9(NC)
AC16
MEM_A10(NC)
AE13
MEM_A11(NC)
AC14
MEM_A12(NC)
Y14
MEM_A13(NC)
AD16
MEM_BA0(NC)
AE17
MEM_BA1(NC)
AD17
MEM_BA2(NC)
W12
MEM_RASb(NC)
Y12
MEM_CASb(NC)
AD18
MEM_WEb(NC)
AB13
MEM_CSb(NC)
AB18
MEM_CKE(NC)
V14
MEM_ODT(NC)
V15
MEM_CKP(NC)
W14
MEM_CKN(NC)
AE12
MEM_COMPP(NC)
AD12
MEM_COMPN(NC)
RS780M_FCBGA528
RS780M_FCBGA528
VSSAPCIE1
PART 6/6
PART 6/6
VSSAPCIE2
VSSAPCIE3
VSSAPCIE4
VSSAPCIE5
VSSAPCIE6
VSSAPCIE7
VSSAPCIE8
VSSAPCIE9
VSSAPCIE10
VSSAPCIE11
VSSAPCIE12
VSSAPCIE13
VSSAPCIE14
VSSAPCIE15
VSSAPCIE16
VSSAPCIE17
VSSAPCIE18
VSSAPCIE19
VSSAPCIE20
VSSAPCIE21
VSSAPCIE22
VSSAPCIE23
VSSAPCIE24
VSSAPCIE25
VSSAPCIE26
VSSAPCIE27
VSSAPCIE28
VSSAPCIE29
VSSAPCIE30
GROUND
GROUND
VSSAPCIE31
VSSAPCIE32
VSSAPCIE33
VSSAPCIE34
VSSAPCIE35
VSSAPCIE36
VSSAPCIE37
VSSAPCIE38
VSSAPCIE39
VSSAPCIE40
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
PAR 4 OF 6
PAR 4 OF 6
MEM_DQ0/DVO_VSYNC(NC)
MEM_DQ1/DVO_HSYNC(NC)
MEM_DQ2/DVO_DE(NC)
MEM_DQ3/DVO_D0(NC)
MEM_DQ4(NC)
MEM_DQ5/DVO_D1(NC)
MEM_DQ6/DVO_D2(NC)
MEM_DQ7/DVO_D4(NC)
MEM_DQ8/DVO_D3(NC)
MEM_DQ9/DVO_D5(NC)
MEM_DQ10/DVO_D6(NC)
MEM_DQ11/DVO_D7(NC)
MEM_DQ12(NC)
MEM_DQ13/DVO_D9(NC)
MEM_DQ14/DVO_D10(NC)
MEM_DQ15/DVO_D11(NC)
MEM_DQS0P/DVO_IDCKP(NC)
MEM_DQS0N/DVO_IDCKN(NC)
MEM_DQS1P(NC)
MEM_DQS1N(NC)
MEM_DM0(NC)
MEM_DM1/DVO_D8(NC)
SBD_MEM/DVO_I/F
SBD_MEM/DVO_I/F
IOPLLVDD18(NC)
IOPLLVDD(NC)
IOPLLVSS(NC)
MEM_VREF(NC)
+1.8VS=W/S=20/1 0mil For Memory PLL power
+1.1VS=W/S=20/1 0mil For Memory PLL power
A2
B1
D3
D5
E4
G1
G2
G4
H7
J4
R7
L1
L2
L4
L7
M6
N4
P6
R1
R2
R4
V7
U4
V8
V6
W1
W2
W4
W7
W8
Y6
AA4
AB5
AB1
AB7
AC3
AC4
AE1
AE4
AB2
AE14
D11
G8
E14
E15
J15
J12
K14
M11
L15
E
AA18
AA20
AA19
Y19
V17
AA17
AA15
Y15
AC20
AD19
AE22
AC18
AB20
AD22
AC22
AD21
Y17
W18
AD20
AE21
W17
AE19
AE23
AE24
AD23
AE18
15mA
+1.8VS
+1.1VS
26mA
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2008/10/06 2009/10/06
2008/10/06 2009/10/06
2008/10/06 2009/10/06
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
D
Date: Sheet of
Compal Electronics, Inc.
RS780 PWR/GND
RS780 PWR/GND
RS780 PWR/GND
KBLG0 LA-4921P
KBLG0 LA-4921P
KBLG0 LA-4921P
E
0.1
0.1
12 57Thursday, January 15, 2009
12 57Thursday, January 15, 2009
12 57Thursday, January 15, 2009
0.1
A
B
C
D
E
DFT_GPIO5:STRAP_DEBUG_BUS_GPIO_ENABLEb
GMCH_CRT_VSYNC11 ,26
1 1
12
R286 3K_0402_5%R286 3K_0402_5%
12
R287 3K_0402_5%@R287 3K_0402_5%@
+3VS
Enables the Test Debug Bus using GPIO. (VSYNC)
1 : Disable (RS780)
0 : Enable (Rs780)
DFT_GPIO1: LOAD_EEPROM_STRAPS
AUX_CAL11
RS780 DFT_GPIO1
2 2
SUS_STAT_R#11 PLT_RST# 11,14,24,27,33,34,36,38
1 2
R284 150_0402_1%@ R284 150_0402_ 1%@
D29
D29
CH751H-40_SC76@
CH751H-40_SC76@
2 1
Selects Loading of STRAPS from EPROM
1 : Bypass the loading of EEPROM straps and use Hardware Default Values
0 : I2C Master can load strap values from EEPROM if connected, or use
default values if not connected
RS740/RX780: DFT_GPIO1 RS780:SUS_STAT
RS780 use HSYNC to enable SIDE PORT
RS780 use HSYNC to enable SIDE PORT
GMCH_CRT_HSYNC11,26
12
R281 3K_0402_5%R281 3K_0402_5%
@
@
12
R282 3K_0402_5%
R282 3K_0402_5%
+3VS
RS740/RS780: Enables Side port memory ( RS780 use HSYNC#)
0. Enable (RS780)
1 : Disable(RS780)
3 3
4 4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2008/10/06 2009/10/06
2008/10/06 2009/10/06
2008/10/06 2009/10/06
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
D
Date: Sheet of
Compal Electronics, Inc.
RS780 STRAPS
RS780 STRAPS
RS780 STRAPS
KBLG0 LA-4921P
KBLG0 LA-4921P
KBLG0 LA-4921P
E
0.1
0.1
13 57Thursday, February 19, 2009
13 57Thursday, February 19, 2009
13 57Thursday, February 19, 2009
0.1
5
4
3
2
1
U4A
U4A
PCIE_RX0P
PCIE_RX0N
PCIE_RX1P
PCIE_RX1N
PCIE_RX2P
PCIE_RX2N
PCIE_RX3P
PCIE_RX3N
PCIE_RX4P
PCIE_RX4N
PCIE_RX5P
PCIE_RX5N
PCIE_RX6P
PCIE_RX6N
PCIE_RX7P
PCIE_RX7N
PCIE_RX8P
PCIE_RX8N
PCIE_RX9P
PCIE_RX9N
PCIE_RX10P
PCIE_RX10N
PCIE_RX11P
PCIE_RX11N
PCIE_RX12P
PCIE_RX12N
PCIE_RX13P
PCIE_RX13N
PCIE_RX14P
PCIE_RX14N
PCIE_RX15P
PCIE_RX15N
CLOCK
CLOCK
PCIE_REFCLKP
PCIE_REFCLKN
NC#1
NC#2
NC_PWRGOOD
PERSTB
Issued Date
Issued Date
Issued Date
PCIE_GTX_ C_MRX_P[0..15]
PCIE_GTX_ C_MRX_N[0..15]
PCIE_MTX_ C_GRX_P[0..15]
PCIE_MTX_ C_GRX_N[0..15]
PCIE_TX0P
PCIE_TX0N
PCIE_TX1P
PCIE_TX1N
PCIE_TX2P
PCIE_TX2N
PCIE_TX3P
PCIE_TX3N
PCIE_TX4P
PCI EXPRESS INTERFACE
PCI EXPRESS INTERFACE
PCIE_TX4N
PCIE_TX5P
PCIE_TX5N
PCIE_TX6P
PCIE_TX6N
PCIE_TX7P
PCIE_TX7N
PCIE_TX8P
PCIE_TX8N
PCIE_TX9P
PCIE_TX9N
PCIE_TX10P
PCIE_TX10N
PCIE_TX11P
PCIE_TX11N
PCIE_TX12P
PCIE_TX12N
PCIE_TX13P
PCIE_TX13N
PCIE_TX14P
PCIE_TX14N
PCIE_TX15P
PCIE_TX15N
CALIBRATION
CALIBRATION
PCIE_CALRP
PCIE_CALRN
2008/10/ 06 20 09/10/06
2008/10/ 06 20 09/10/06
2008/10/ 06 20 09/10/06
3
M92@
M92@
PCIE LANE REVERSAL
PCIE_GTX_ MRX_P15
Y33
PCIE_GTX_ MRX_N15 PCIE_GTX_ C_MRX_N15
Y32
PCIE_GTX_ MRX_P14
W33
PCIE_GTX_ MRX_N14
W32
PCIE_GTX_ MRX_P13
U33
PCIE_GTX_ MRX_N13
U32
PCIE_GTX_ MRX_P12
U30
PCIE_GTX_ MRX_N12
U29
T33
PCIE_GTX_ MRX_N11
T32
PCIE_GTX_ MRX_P10
T30
PCIE_GTX_ MRX_N10 PCIE_GTX_ C_MRX_N10
T29
PCIE_GTX_ MRX_P9
P33
PCIE_GTX_ MRX_N9
P32
PCIE_GTX_ MRX_P8
P30
PCIE_GTX_ MRX_N8
P29
N33
PCIE_GTX_ MRX_N7 PCIE_GTX_ C_MRX_N7
N32
PCIE_GTX_ MRX_P6
N30
PCIE_GTX_ MRX_N6
N29
L33
PCIE_GTX_ MRX_N5 PCIE_GTX_ C_MRX_N5
L32
L30
PCIE_GTX_ MRX_N4
L29
K33
PCIE_GTX_ MRX_N3
K32
PCIE_GTX_ MRX_P2
J33
PCIE_GTX_ MRX_N2
J32
PCIE_GTX_ MRX_P1
K30
PCIE_GTX_ MRX_N1
K29
H33
PCIE_GTX_ MRX_N0
H32
VGA@
VGA@
R83 1.27K_ 0402_1%
R83 1.27K_ 0402_1%
Y30
Y29
1 2
R90 2K_0402 _1%
R90 2K_0402 _1%
1 2
VGA@
VGA@
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
C172 0.1U_040 2_16V7K
C172 0.1U_040 2_16V7K
1 2
C181 0.1U_040 2_16V7K
C181 0.1U_040 2_16V7K
1 2
VGA@
VGA@
VGA@
1 2
VGA@
VGA@
1 2
VGA@
VGA@
1 2
VGA@
VGA@
1 2
VGA@
VGA@
1 2
VGA@
VGA@
1 2
VGA@
VGA@
1 2
VGA@
VGA@
1 2
VGA@
VGA@
1 2
VGA@
VGA@
1 2
VGA@
VGA@
1 2
VGA@
VGA@
1 2
VGA@
VGA@
1 2
VGA@
VGA@
1 2
VGA@
VGA@
1 2
VGA@
VGA@
VGA@
1 2
VGA@
VGA@
1 2
VGA@
VGA@
1 2
VGA@
VGA@
1 2
VGA@
VGA@
1 2
VGA@
VGA@
1 2
VGA@
VGA@
1 2
VGA@
VGA@
1 2
VGA@
VGA@
1 2
VGA@
VGA@
1 2
VGA@
VGA@
1 2
VGA@
VGA@
1 2
VGA@
VGA@
1 2
VGA@
VGA@
1 2
VGA@
VGA@
1 2
VGA@
VGA@
+1.1VS_P X
2
C160 0.1U_040 2_16V7K
C160 0.1U_040 2_16V7K
C162 0.1U_040 2_16V7K
C162 0.1U_040 2_16V7K
C139 0.1U_040 2_16V7K
C139 0.1U_040 2_16V7K
C143 0.1U_040 2_16V7K
C143 0.1U_040 2_16V7K
C141 0.1U_040 2_16V7K
C141 0.1U_040 2_16V7K
C148 0.1U_040 2_16V7K
C148 0.1U_040 2_16V7K
C134 0.1U_040 2_16V7K
C134 0.1U_040 2_16V7K
C138 0.1U_040 2_16V7K
C138 0.1U_040 2_16V7K
C128 0.1U_040 2_16V7K
C128 0.1U_040 2_16V7K
C137 0.1U_040 2_16V7K
C137 0.1U_040 2_16V7K
C126 0.1U_040 2_16V7K
C126 0.1U_040 2_16V7K
C133 0.1U_040 2_16V7K
C133 0.1U_040 2_16V7K
C156 0.1U_040 2_16V7K
C156 0.1U_040 2_16V7K
C158 0.1U_040 2_16V7K
C158 0.1U_040 2_16V7K
C136 0.1U_040 2_16V7K
C136 0.1U_040 2_16V7K
C127 0.1U_040 2_16V7K
C127 0.1U_040 2_16V7K
C144 0.1U_040 2_16V7K
C144 0.1U_040 2_16V7K
C140 0.1U_040 2_16V7K
C140 0.1U_040 2_16V7K
C116 0.1U_040 2_16V7K
C116 0.1U_040 2_16V7K
C114 0.1U_040 2_16V7K
C114 0.1U_040 2_16V7K
C154 0.1U_040 2_16V7K
C154 0.1U_040 2_16V7K
C155 0.1U_040 2_16V7K
C155 0.1U_040 2_16V7K
C129 0.1U_040 2_16V7K
C129 0.1U_040 2_16V7K
C130 0.1U_040 2_16V7K
C130 0.1U_040 2_16V7K
C120 0.1U_040 2_16V7K
C120 0.1U_040 2_16V7K
C115 0.1U_040 2_16V7K
C115 0.1U_040 2_16V7K
C152 0.1U_040 2_16V7K
C152 0.1U_040 2_16V7K
C153 0.1U_040 2_16V7K
C153 0.1U_040 2_16V7K
C131 0.1U_040 2_16V7K
C131 0.1U_040 2_16V7K
C132 0.1U_040 2_16V7K
C132 0.1U_040 2_16V7K
PCIE_GTX_ C_MRX_P15
PCIE_GTX_ C_MRX_P14
PCIE_GTX_ C_MRX_N14
PCIE_GTX_ C_MRX_P13
PCIE_GTX_ C_MRX_N13
PCIE_GTX_ C_MRX_P12
PCIE_GTX_ C_MRX_N12
PCIE_GTX_ C_MRX_P11PCIE_GTX_ MRX_P11
PCIE_GTX_ C_MRX_N11
PCIE_GTX_ C_MRX_P10
PCIE_GTX_ C_MRX_P9
PCIE_GTX_ C_MRX_N9
PCIE_GTX_ C_MRX_P8
PCIE_GTX_ C_MRX_N8
PCIE_GTX_ C_MRX_P7PCIE_GTX_ MRX_P7
PCIE_GTX_ C_MRX_P6
PCIE_GTX_ C_MRX_N6
PCIE_GTX_ C_MRX_P5PCIE_GTX_ MRX_P5
PCIE_GTX_ C_MRX_P4PCIE_GTX_ MRX_P4
PCIE_GTX_ C_MRX_N4
PCIE_GTX_ C_MRX_P3PCIE_GTX_ MRX_P3
PCIE_GTX_ C_MRX_N3
PCIE_GTX_ C_MRX_P2
PCIE_GTX_ C_MRX_N2
PCIE_GTX_ C_MRX_P1
PCIE_GTX_ C_MRX_N1
PCIE_GTX_ C_MRX_P0PCIE_GTX_ MRX_P0
PCIE_GTX_ C_MRX_N0
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
M92 PCIE interface
M92 PCIE interface
M92 PCIE interface
KBLG0 LA-4921P
KBLG0 LA-4921P
KBLG0 LA-4921P
1
0.1
0.1
0.1
14 57Thursday, February 19, 20 09
14 57Thursday, February 19, 20 09
14 57Thursday, February 19, 20 09
PCIE_GTX_ C_MRX_P[0..15]10
PCIE_GTX_ C_MRX_N[0..15]10
PCIE_MTX_ C_GRX_P[0..15]10
PCIE_MTX_ C_GRX_N[0..15]10
D D
PCIE LANE REVERSAL
PCIE_MTX_ C_GRX_P15
PCIE_MTX_ C_GRX_N15
PCIE_MTX_ C_GRX_P14
PCIE_MTX_ C_GRX_N14
PCIE_MTX_ C_GRX_P13
PCIE_MTX_ C_GRX_N13
PCIE_MTX_ C_GRX_P12
PCIE_MTX_ C_GRX_N12
PCIE_MTX_ C_GRX_P11
PCIE_MTX_ C_GRX_N11
C C
B B
CLK_PCIE_ VGA23
CLK_PCIE_ VGA#23
+3VS_DE LAY
A A
D4
D4
PLT_RST #11,13,24,2 7,33,34,36,38
PX_GPIO027
12
R481 2.2 K_0402_5%@R481 2.2 K_0402_5%@
5
2
3
CHP202U PT_SOT323-3
CHP202U PT_SOT323-3
VGA@
VGA@
12
R474
R474
10K_040 2_5%
10K_040 2_5%
VGA@
VGA@
GPU_RST #
1
PCIE_MTX_ C_GRX_P10
PCIE_MTX_ C_GRX_N10
PCIE_MTX_ C_GRX_P9
PCIE_MTX_ C_GRX_N9
PCIE_MTX_ C_GRX_P8
PCIE_MTX_ C_GRX_N8
PCIE_MTX_ C_GRX_P7
PCIE_MTX_ C_GRX_N7
PCIE_MTX_ C_GRX_P6
PCIE_MTX_ C_GRX_N6
PCIE_MTX_ C_GRX_P5
PCIE_MTX_ C_GRX_N5
PCIE_MTX_ C_GRX_P4
PCIE_MTX_ C_GRX_N4
PCIE_MTX_ C_GRX_P3
PCIE_MTX_ C_GRX_N3
PCIE_MTX_ C_GRX_P2
PCIE_MTX_ C_GRX_N2
PCIE_MTX_ C_GRX_P1
PCIE_MTX_ C_GRX_N1
PCIE_MTX_ C_GRX_P0
PCIE_MTX_ C_GRX_N0
CLK_PCIE_ VGA
CLK_PCIE_ VGA#
4
GPU_RST #
AA38
Y37
Y35
W36
W38
V37
V35
U36
U38
T37
T35
R36
R38
P37
P35
N36
N38
M37
M35
L36
L38
K37
K35
J36
J38
H37
H35
G36
G38
F37
F35
E37
AB35
AA36
AJ21
AK21
AH16
AA30
216-0729002 A12 M96_BGA962
216-0729002 A12 M96_BGA962
Security Class ification
Security Class ification
Security Class ification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
D D
+3VS_DELAY
VGA_LCD_CLK
1 2
R92 4.7K_0402_5%
R92 4.7K_0402_5%
VGA@
VGA@
VGA_LCD_DATA
1 2
R88 4.7K_0402_5%
R88 4.7K_0402_5%
VGA@
VGA@
R97
R97
C C
+3VS_DELAY
12
R104
R104
10K_0402_5%
10K_0402_5%
@
@
GPIO23_CLKREQB
+3VS_DELAY
12
R98
R98
10K_0402_5%
10K_0402_5%
@
@
BB_EN
Back bias (BB) control
Back Bias Disabled :
GPIO_21_BB_EN = 0V
B B
BBP connect directly to VDDC
+3VS_DELAY
12
R95
R95
10K_0402_5%
10K_0402_5%
@
@
GPIO24_TRSTB
12
@
@
R96
R96
1K_0402_5%
1K_0402_5%
+1.8VS_PX
L66
L66
1 2
MCK1608471YZF 0603
MCK1608471YZF 0603
VGA@
VGA@
10U_0603_6.3V6M
10U_0603_6.3V6M
A A
+1.1VS_PX
L24
L24
1 2
MCK1608471YZF 0603
MCK1608471YZF 0603
VGA@
VGA@
10U_0603_6.3V6M
10U_0603_6.3V6M
1
C688
C688
VGA@
VGA@
2
1
C254
C254
VGA@
VGA@
2
VGA_PWRSEL
12
10K_0402_5%@
10K_0402_5%@
GPIO_5_AC_BATT
AC (Performance mode) = 3.3 V
Battery saving mode = 0.0 V
+3VS_DELAY
ACIN29,38,40,46,49
VGA_PWRSEL
High:VGA_CORE 0 .95V
Low :VGA_CORE 1 .2V
27M_SSC23
27M_SSC_R19
R334 & R335 be place close
DPLL_PVDD=0.12A
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1
1
C689
C689
VGA@
VGA@
2
2
DPLL_VDDC=0.3A
+DPLL_VDDC
1
1
C256
C256
VGA@
VGA@
2
2
5
+DPLL_PVDD
C690
C690
0.1U_0402_16V7K
0.1U_0402_16V7K
VGA@
VGA@
C255
C255
0.1U_0402_16V7K
0.1U_0402_16V7K
VGA@
VGA@
GPU_GPIO022
GPU_GPIO122
GPU_GPIO222
1 2
R99 100K_0402_5%VGA@R99 100K_0402_5%VGA@
21
D13 RB751V_SOD323VGA@D13 RB751V_SOD323VGA@
VGA_ENBKL38
GPU_GPIO822
GPU_GPIO922
GPU_GPIO1122
GPU_GPIO1222
GPU_GPIO1322
27M_SSC 27M_SSC_M92
27M_SSC_R
VGA_PWRSEL54
1 2
R334 0_0402_5%@ R334 0_0402_5%@
1 2
R335 0_0402_5%@ R335 0_0402_5%@
GPU_GPIO0
GPU_GPIO1
GPU_GPIO2
GPIO_5_AC_BATT#
GPU_GPIO8
GPU_GPIO9
GPU_GPIO11
GPU_GPIO12
GPU_GPIO13
CTF (High activ e)
+1.8VS_PX
12
R110
R110
499_0402_1%
499_0402_1%
VGA@
VGA@
12
R107
R107
249_0402_1%
249_0402_1%
VGA@
VGA@
Internal 2% dow nspread (disabl e)
27M_NSSC19,23
+1.8VS_PX
61.9 ohm
R306 75_0402_1%
R306 75_0402_1%
75 ohm
1 2
VGA@
VGA@
R305
R305
100_0402_5%
100_0402_5%
L65
L65
BLM18PG121SN1D_0603
BLM18PG121SN1D_0603
VGA@
VGA@
4
VGA_LCD_CLK24
VGA_LCD_DATA24
R101 10K_0402_5%
R101 10K_0402_5%
1 2
VGA_PWRSEL
THM_ALERT#22
R100 10K_0402_5%@ R100 10K_0402_5%@
1 2
HDMI_DET11,25
+VGA_VREF
1
C354
C354
0.1U_0402_16V7K
0.1U_0402_16V7K
VGA@
VGA@
2
Voltage Swing: 1.8 V
VGA@
VGA@
1 2
GPU_THERMAL_D+22
GPU_THERMAL_D-22
TSVDD=20mA
1U_0402_6.3V4Z
1U_0402_6.3V4Z
12
10U_0805_10V4Z
10U_0805_10V4Z
1
1
C685
C685
VGA@
VGA@
2
2
4
VRAM_ID022
VRAM_ID122
VRAM_ID222
VRAM_ID322
VGA@
VGA@
GPIO23_CLKREQB
GPIO24_TRSTB
C687
C687
VGA@
VGA@
0.1U_0402_16V7K
0.1U_0402_16V7K
T64 PADT64 PAD
T45 PADT45 PAD
T27 PADT27 PAD
T51 PADT51 PAD
T55 PADT55 PAD
T65 PADT65 PAD
T66 PADT66 PAD
T30 PADT30 PAD
T60 PADT60 PAD
T29 PADT29 PAD
T61 PADT61 PAD
T56 PADT56 PAD
T63 PADT63 PAD
T57 PADT57 PAD
T62 PADT62 PAD
T58 PADT58 PAD
T50 PADT50 PAD
T28 PADT28 PAD
T46 PADT46 PAD
T59 PADT59 PAD
T52 PADT52 PAD
T53 PADT53 PAD
T47 PADT47 PAD
T48 PADT48 PAD
T49 PADT49 PAD
T54 PADT54 PAD
GPU_CTF
BB_EN
T16 PADT16 PAD
T17 PADT17 PAD
T14 PADT14 PAD
T12 PADT12 PAD
T23 PADT23 PAD
T22 PADT22 PAD
T20 PADT20 PAD
T19 PADT19 PAD
T13 PADT13 PAD
T15 PADT15 PAD
+DPLL_PVDD
+DPLL_VDDC
27MCLK
T7 PADT7 PAD
+TSVDD
1
C686
C686
VGA@
VGA@
2
U4B
U4B
MUTI GFX
MUTI GFX
AR8
DVPCNTL_MVP_0
AU8
DVPCNTL_MVP_1
AP8
DVPCNTL_0
AW8
DVPCNTL_1
AR3
DVPCNTL_2
AR1
DVPCLK
AU1
DVPDATA_0
AU3
DVPDATA_1
AW3
DVPDATA_2
AP6
DVPDATA_3
AW5
DVPDATA_4
AU5
DVPDATA_5
AR6
DVPDATA_6
AW6
DVPDATA_7
AU6
DVPDATA_8
AT7
DVPDATA_9
AV7
DVPDATA_10
AN7
DVPDATA_11
AV9
DVPDATA_12
AT9
DVPDATA_13
AR10
DVPDATA_14
AW10
DVPDATA_15
AU10
DVPDATA_16
AP10
DVPDATA_17
AV11
DVPDATA_18
AT11
DVPDATA_19
AR12
DVPDATA_20
AW12
DVPDATA_21
AU12
DVPDATA_22
AP12
DVPDATA_23
I2C
I2C
AK26
SCL
AJ26
SDA
GENERAL PURPOSE I/O
GENERAL PURPOSE I/O
AH20
GPIO_0
AH18
GPIO_1
AN16
GPIO_2
AH23
GPIO_3_SMBDATA
AJ23
GPIO_4_SMBCLK
AH17
GPIO_5_AC_BATT
AJ17
GPIO_6
AK17
GPIO_7_BLON
AJ13
GPIO_8_ROMSO
AH15
GPIO_9_ROMSI
AJ16
GPIO_10_ROMSCK
AK16
GPIO_11
AL16
GPIO_12
AM16
GPIO_13
AM14
GPIO_14_HPD2
AM13
GPIO_15_PWRCNTL_0
AK14
GPIO_16_SSIN
AG30
GPIO_17_THERMAL_INT
AN14
GPIO_18_HPD3
AM17
GPIO_19_CTF
AL13
GPIO_20_PWRCNTL_1
AJ14
GPIO_21_BB_EN
AK13
GPIO_22_ROMCSB
AN13
GPIO_23_CLKREQB
AM23
JTAG_TRSTB
AN23
JTAG_TDI
AK23
JTAG_TCK
AL24
JTAG_TMS
AM24
JTAG_TDO
AJ19
GENERICA
AK19
GENERICB
AJ20
GENERICC
AK20
GENERICD
AJ24
GENERICE_HPD4
AH26
GENERICF
AH24
GENERICG
AK24
HPD1
AH13
VREFG
AM32
DPLL_PVDD
AN32
DPLL_PVSS
AN31
DPLL_VDDC
AV33
XTALIN
AU34
XTALOUT
AF29
DPLUS
AG29
DMINUS
AK32
TS_FDO
AJ32
TSVDD
AJ33
TSVSS
216-0729002 A12 M96_BGA962
216-0729002 A12 M96_BGA962
PLL/CLOCK
PLL/CLOCK
THERMAL
THERMAL
TXCAP_DPA3P
TXCAM_DPA3N
TX0P_DPA2P
TX0M_DPA2N
DPA
DPA
TX1P_DPA1P
TX1M_DPA1N
TX2P_DPA0P
TX2M_DPA0N
TXCBP_DPB3P
TXCBM_DPB3N
TX3P_DPB2P
TX3M_DPB2N
DPB
DPB
TX4P_DPB1P
TX4M_DPB1N
TX5P_DPB0P
TX5M_DPB0N
TXCCP_DPC3P
TXCCM_DPC3N
TX0P_DPC2P
TX0M_DPC2N
DPC
DPC
TX1P_DPC1P
TX1M_DPC1N
TX2P_DPC0P
TX2M_DPC0N
TXCDP_DPD3P
TXCDM_DPD3N
TX3P_DPD2P
TX3M_DPD2N
DPD
DPD
TX4P_DPD1P
TX4M_DPD1N
TX5P_DPD0P
TX5M_DPD0N
DAC1
DAC1
DAC2
DAC2
A2VDDQ
DDC/AUX
DDC/AUX
DDC1CLK
DDC1DATA
DDC2CLK
DDC2DATA
DDCCLK_AUX3P
DDCDATA_AUX3N
DDCCLK_AUX4P
DDCDATA_AUX4N
DDCCLK_AUX5P
DDCDATA_AUX5N
DDC6CLK
DDC6DATA
NC_DDCCLK_AUX7P
NC_DDCDATA_AUX7N
3
AU24
AV23
AT25
AR24
AU26
AV25
AT27
AR26
AR30
AT29
AV31
AU30
AR32
AT31
AT33
AU32
AU14
AV13
AT15
AR14
AU16
AV15
AT17
AR16
AU20
AT19
AT21
AR20
AU22
AV21
AT23
AR22
AD39
R
AD37
RB
AE36
G
AD35
GB
AF37
B
AE38
BB
AC36
HSYNC
AC38
VSYNC
RSET
AVDD
AVSSQ
VDD1DI
VSS1DI
COMP
H2SYNC
V2SYNC
VDD2DI
VSS2DI
A2VDD
A2VSSQ
R2SET
AUX1P
AUX1N
AUX2P
AUX2N
M92@
M92@
R2
R2B
G2
G2B
B2
B2B
C
Y
3
VGA@
VGA@
R80
R80
AB34
1 2
499_0402_1%
499_0402_1%
+AVDD
AD34
AE34
+VDD1DI
AC33
AC34
AC30
AC31
AD30
AD31
AF30
AF31
AC32
AD32
AF32
AD29
AC29
+VDD1DI
AG31
AG32
AG33
+A2VDDQ
AD33
AF33
R86
R86
1 2
AA29
715_0402_1%
715_0402_1%
VGA@
VGA@
AM26
AN26
AM27
AL27
AM19
AL19
AN20
AM20
AL30
AM30
AL29
AM29
AN21
AM21
AJ30
AJ31
AK30
AK29
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
HDMI_CLK+_VGA 25
HDMI_CLK-_VGA 25
HDMI_TX0+_VGA 25
HDMI_TX0-_VGA 25
HDMI_TX1+_VGA 25
HDMI_TX1-_VGA 25
HDMI_TX2+_VGA 25
HDMI_TX2-_VGA 25
VGA_CRT_R 26
VGA_CRT_G 26
VGA_CRT_B 26
VGA_CRT_HSYNC 22,26
VGA_CRT_VSYNC 22,26
HSYNC_DAC2 22
VSYNC_DAC2 22
+3VS_DELAY
VGA_CRT_R
VGA_CRT_G
VGA_CRT_B
VGA@
VGA@
1 2
R303 150_0402_1%
R303 150_0402_1%
VGA@
VGA@
1 2
R302 150_0402_1%
R302 150_0402_1%
VGA@
VGA@
1 2
R301 150_0402_1%
R301 150_0402_1%
VGA_CRT_CLK 26
VGA_CRT_DATA 26
VGA_HDMI_SCLK 25
VGA_HDMI_SDATA 25
Compal Secret Data
Compal Secret Data
2008/10/06 2009/10/06
2008/10/06 2009/10/06
2008/10/06 2009/10/06
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
U4G
U4G
LVDS CONTROL
LVDS CONTROL
TXCLK_UP_DPF3P
TXCLK_UN_DPF3N
TXOUT_U0P_DPF2P
TXOUT_U0N_DPF2N
TXOUT_U1P_DPF1P
TXOUT_U1N_DPF1N
TXOUT_U2P_DPF0P
TXOUT_U2N_DPF0N
LVTMDP
LVTMDP
TXCLK_LP_DPE3P
TXCLK_LN_DPE3N
TXOUT_L0P_DPE2P
TXOUT_L0N_DPE2N
TXOUT_L1P_DPE1P
TXOUT_L1N_DPE1N
TXOUT_L2P_DPE0P
TXOUT_L2N_DPE0N
216-0729002 A12 M96_BGA962
216-0729002 A12 M96_BGA962
M92@
M92@
+1.8VS_PX +AVDD
BLM18PG121SN1D_0603
BLM18PG121SN1D_0603
BLM18PG121SN1D_0603
BLM18PG121SN1D_0603
BLM18PG121SN1D_0603
BLM18PG121SN1D_0603
2
L61
L61
VGA@
VGA@
L62
L62
VGA@
VGA@
L63
L63
VGA@
VGA@
AVDD=70mA
12
VDD1DI=45mA
12
A2VDDQ=1mA
12
AK27
VARY_BL
AJ27
DIGON
AK35
AL36
AJ38
AK37
AH35
AJ36
AG38
AH37
AF35
TXOUT_U3P
AG36
TXOUT_U3N
AP34
AR34
AW37
AU35
AR37
AU39
AP35
AR35
AN36
TXOUT_L3P
AP37
TXOUT_L3N
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1
C680
C680
VGA@
VGA@
2
0.1U_0402_16V7K
0.1U_0402_16V7K
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1
C676
C676
VGA@
VGA@
2
0.1U_0402_16V7K
0.1U_0402_16V7K
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1
C682
C682
VGA@
VGA@
2
0.1U_0402_16V7K
0.1U_0402_16V7K
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
Date: Sheet of
Date: Sheet of
Date: Sheet of
T11 PADT11 PAD
VGA_ENVDD 24
VGA_TXCLK+ 24
VGA_TXCLK- 24
VGA_TXOUT0+ 24
VGA_TXOUT0- 24
VGA_TXOUT1+ 24
VGA_TXOUT1- 24
VGA_TXOUT2+ 24
VGA_TXOUT2- 24
1
1
C684
C684
C671
C671
10U_0805_10V4Z
10U_0805_10V4Z
VGA@
VGA@
VGA@
VGA@
2
2
1
1
C681
C681
C673
C673
10U_0805_10V4Z
10U_0805_10V4Z
VGA@
VGA@
VGA@
VGA@
2
2
1
1
C672
C672
C677
C677
10U_0805_10V4Z
10U_0805_10V4Z
VGA@
VGA@
VGA@
VGA@
2
2
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
M92 LVDS/HDMI/CRT
M92 LVDS/HDMI/CRT
M92 LVDS/HDMI/CRT
KBLG0 LA-4921P
KBLG0 LA-4921P
KBLG0 LA-4921P
1
+VDD1DI
+A2VDDQ
1
0.1
0.1
15 57Thursday, February 19, 2009
15 57Thursday, February 19, 2009
15 57Thursday, February 19, 2009
0.1
5
U4D
U4D
4
3
U4C
U4C
2
1
MDA0
C5
DQB_0
MDA1
C3
DQB_1
MDA2
E3
DQB_2
MDA3
E1
DQB_3
MDA4
F1
DQB_4
MDA5
F3
DQB_5
MDA6
F5
DQB_6
MDA7
G4
DQB_7
MDA8
H5
DQB_8
MDA9
D D
MAA[12..0]
BA[2..0]
MDA[63..32]21
MDA[31..0]20
C C
B B
A A
5
MAA[12..0] 20 ,21
BA[2..0] 20,21
MDA[63..32]
MDA[31..0]
+3VS_DELAY
12
R87
R87
5.11K_0402_1%
5.11K_0402_1%
@
@
12
R91
R91
1K_0402_1%
1K_0402_1%
VGA@
VGA@
+1.8VS_PX +1.8VS_PX
12
R139
R139
100_0402_1%
100_0402_1%
VGA@
VGA@
12
R131
R131
100_0402_1%
100_0402_1%
VGA@
VGA@
+VDD_MEM18_REFD
+VDD_MEM18_REFS
TESTEN
MP
4.7K_0402_5%
4.7K_0402_5%
R111
R111
VGA@
VGA@
12
Close to pin Y12 Close to pin AA12
+VDD_MEM18_REFD +VDD_MEM18_REFS
1
C388
C388
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
VGA@
VGA@
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63
12
R109
R109
4.7K_0402_5%
4.7K_0402_5%
VGA@
VGA@
H6
DQB_9
J4
DQB_10
K6
DQB_11
K5
DQB_12
L4
DQB_13
M6
DQB_14
M1
DQB_15
M3
DQB_16
M5
DQB_17
N4
DQB_18
P6
DQB_19
P5
DQB_20
R4
DQB_21
T6
DQB_22
T1
DQB_23
U4
DQB_24
V6
DQB_25
V1
DQB_26
V3
DQB_27
Y6
DQB_28
Y1
DQB_29
Y3
DQB_30
Y5
DQB_31
AA4
DQB_32
AB6
DQB_33
AB1
DQB_34
AB3
DQB_35
AD6
DQB_36
AD1
DQB_37
AD3
DQB_38
AD5
DQB_39
AF1
DQB_40
AF3
DQB_41
AF6
DQB_42
AG4
DQB_43
AH5
DQB_44
AH6
DQB_45
AJ4
DQB_46
AK3
DQB_47
AF8
DQB_48
AF9
DQB_49
AG8
DQB_50
AG7
DQB_51
AK9
DQB_52
AL7
DQB_53
AM8
DQB_54
AM7
DQB_55
AK1
DQB_56
AL4
DQB_57
AM6
DQB_58
AM1
DQB_59
AN4
DQB_60
AP3
DQB_61
AP1
DQB_62
AP5
DQB_63
Y12
MVREFDB
AA12
MVREFSB
AD28
TESTEN
AK10
CLKTESTA
AL10
CLKTESTB
216-0729002 A12 M96_BGA962
216-0729002 A12 M96_BGA962
M92@
M92@
100_0402_1%
100_0402_1%
100_0402_1%
100_0402_1%
VGA@
VGA@
VGA@
VGA@
4
MAB_13/BA2
MAB_14/BA0
MAB_15/BA1
DQMB_0
DQMB_1
DQMB_2
DQMB_3
DQMB_4
DQMB_5
DQMB_6
MEMORY INTERFACE B
MEMORY INTERFACE B
DQMB_7
QSB_0/RDQSB_0
QSB_1/RDQSB_1
QSB_2/RDQSB_2
QSB_3/RDQSB_3
QSB_4/RDQSB_4
QSB_5/RDQSB_5
QSB_6/RDQSB_6
QSB_7/RDQSB_7
QSB_0B/W DQSB_0
QSB_1B/W DQSB_1
QSB_2B/W DQSB_2
QSB_3B/W DQSB_3
QSB_4B/W DQSB_4
QSB_5B/W DQSB_5
QSB_6B/W DQSB_6
QSB_7B/W DQSB_7
CSB0B_0
CSB0B_1
CSB1B_0
CSB1B_1
DRAM_RST
12
R138
R138
12
R127
R127
MAB_0
MAB_1
MAB_2
MAB_3
MAB_4
MAB_5
MAB_6
MAB_7
MAB_8
MAB_9
MAB_10
MAB_11
MAB_12
ODTB0
ODTB1
CLKB0
CLKB0B
CLKB1
CLKB1B
RASB0B
RASB1B
CASB0B
CASB1B
CKEB0
CKEB1
WEB0B
WEB1B
1
2
C381
C381
0.1U_0402_16V4Z
0.1U_0402_16V4Z
P8
T9
P9
N7
N8
N9
U9
U8
Y9
W9
AC8
AC9
AA7
AA8
Y8
AA9
H3
H1
T3
T5
AE4
AF5
AK6
AK5
F6
K3
P3
V5
AB5
AH1
AJ9
AM5
G7
K1
P1
W4
AC4
AH3
AJ8
AM3
T7
W7
L9
L8
AD8
AD7
T10
Y10
W10
AA10
P10
L10
AD10
AC10
U10
AA11
N10
AB11
AH11
VGA@
VGA@
MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
BA2
BA0
BA1
DQMA#0
DQMA#1
DQMA#2
DQMA#3
DQMA#4
DQMA#5
DQMA#6
DQMA#7
QSA0
QSA1
QSA2
QSA3
QSA4
QSA5
QSA6
QSA7
QSA#0
QSA#1
QSA#2
QSA#3
QSA#4
QSA#5
QSA#6
QSA#7
ODTA0
ODTA1
CLKA0
CLKA0#
CLKA1
CLKA1#
RASA#0
RASA#1
CASA#0
CASA#1
CSA0#
CSA1#
CKEA0
CKEA1
WEA#0
WEA#1
C37
DQA_0
C35
DQA_1
A35
DQA_2
E34
DQA_3
G32
DQA_4
D33
DQA_5
F32
DQA_6
E32
DQA_7
D31
DQA_8
F30
DQA_9
C30
DQA_10
A30
DQA_11
F28
DQA_12
C28
DQA_13
A28
DQA_14
E28
DQA_15
DQMA#[7..0] 20,21
QSA[7..0] 20,21
QSA#[7..0] 20,21
ODTA0 20
ODTA1 21
CLKA0 20
CLKA0# 20
CLKA1 21
CLKA1# 21
RASA#0 20
RASA#1 21
CASA#0 20
CASA#1 21
CSA0# 20
CSA1# 21
CKEA0 20
CKEA1 21
WEA#0 20
WEA#1 21
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETARY PROPERT Y OF COMPAL ELECTRONICS, INC. AND CONTAINS CON FIDENTIAL
THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETARY PROPERT Y OF COMPAL ELECTRONICS, INC. AND CONTAINS CON FIDENTIAL
THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETARY PROPERT Y OF COMPAL ELECTRONICS, INC. AND CONTAINS CON FIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
+1.8VS_PX
R94243_0402_1% @R94243_0402_1% @
1 2
R105243_0402_1% @R105243_0 402_1% @
1 2
R108243_0402_1% @R108243_0 402_1% @
1 2
R106243_0402_1% R106243_040 2_1%
1 2
R93243_0402_1% @R93243_0402_1% @
1 2
R122243_0402_1% @R122243_0 402_1% @
1 2
Compal Secret Data
Compal Secret Data
2008/10/06 2009/10/06
2008/10/06 2009/10/06
2008/10/06 2009/10/06
Compal Secret Data
D27
DQA_16
F26
DQA_17
C26
DQA_18
A26
DQA_19
F24
DQA_20
C24
DQA_21
A24
DQA_22
E24
DQA_23
C22
DQA_24
A22
DQA_25
F22
DQA_26
D21
DQA_27
A20
DQA_28
F20
DQA_29
D19
DQA_30
E18
DQA_31
C18
DQA_32
A18
DQA_33
F18
DQA_34
D17
DQA_35
A16
DQA_36
F16
DQA_37
D15
DQA_38
E14
DQA_39
F14
DQA_40
D13
DQA_41
F12
DQA_42
A12
DQA_43
D11
DQA_44
F10
DQA_45
A10
DQA_46
C10
DQA_47
G13
DQA_48
H13
DQA_49
J13
DQA_50
H11
DQA_51
G10
DQA_52
G8
DQA_53
K9
DQA_54
K10
DQA_55
G9
DQA_56
A8
DQA_57
C8
DQA_58
E8
DQA_59
A6
DQA_60
C6
DQA_61
E6
DQA_62
A5
DQA_63
L18
MVREFDA
L20
MVREFSA
L27
NC_MEM_CALRN0
N12
NC_MEM_CALRN1
AG12
NC_MEM_CALRN2
M12
MEM_CALRP1
M27
NC_MEM_CALRP0
AH12
NC_MEM_CALRP2
216-0729002 A12 M96_BGA962
216-0729002 A12 M96_BGA962
M92@
M92@
M92-S2 and M92-M use memory group A only
while M92-M2 uses memory group B only.
Deciphered Date
Deciphered Date
Deciphered Date
2
MAA_0
MAA_1
MAA_2
MAA_3
MAA_4
MAA_5
MAA_6
MAA_7
MAA_8
MAA_9
MAA_10
MAA_11
MAA_12
MAA_13/BA2
MAA_14/BA0
MAA_15/BA1
DQMA_0
DQMA_1
DQMA_2
DQMA_3
DQMA_4
DQMA_5
DQMA_6
MEMORY INTERFACE A
MEMORY INTERFACE A
DQMA_7
QSA_0/RDQSA_0
QSA_1/RDQSA_1
QSA_2/RDQSA_2
QSA_3/RDQSA_3
QSA_4/RDQSA_4
QSA_5/RDQSA_5
QSA_6/RDQSA_6
QSA_7/RDQSA_7
QSA_0B/W DQSA_0
QSA_1B/W DQSA_1
QSA_2B/W DQSA_2
QSA_3B/W DQSA_3
QSA_4B/W DQSA_4
QSA_5B/W DQSA_5
QSA_6B/W DQSA_6
QSA_7B/W DQSA_7
ODTA0
ODTA1
CLKA0
CLKA0B
CLKA1
CLKA1B
RASA0B
RASA1B
CASA0B
CASA1B
CSA0B_0
CSA0B_1
CSA1B_0
CSA1B_1
CKEA0
CKEA1
WEA0B
WEA1B
RSVD#1
RSVD#2
RSVD#3
RSVD#5
RSVD#6
RSVD#9
RSVD#11
G24
J23
H24
J24
H26
J26
H21
G21
H19
H20
L13
G16
J16
H16
J17
H17
A32
C32
D23
E22
C14
A14
E10
D9
C34
D29
D25
E20
E16
E12
J10
D7
A34
E30
E26
C20
C16
C12
J11
F8
J21
G19
H27
G27
J14
H14
K23
K19
K20
K17
K24
K27
M13
K16
K21
J20
K26
L15
AF28
AG28
AL31
H23
J19
T8
W8
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Title
Title
Title
Custom
Custom
Custom
T10PAD T10PAD
T9PADT9PAD
T8PADT8PAD
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
M92 MEM
M92 MEM
M92 MEM
KBLG0 LA-4921P
KBLG0 LA-4921P
KBLG0 LA-4921P
1
16 57Wednesday, March 11, 2009
16 57Wednesday, March 11, 2009
16 57Wednesday, March 11, 2009
0.1
0.1
0.1
5
D D
C C
DPE_VDD18: Output Driver Analo g Power Supply.
+1.8VS_PX
BLM18PG121SN1D_0603
BLM18PG121SN1D_0603
DPE_VDD18=0.31A
L17
L17
1U_0402_6.3V4Z
1U_0402_6.3V4Z
12
VGA@
VGA@
10U_0805_10V4Z V GA@
10U_0805_10V4Z V GA@
C149
C149
1
2
1
2
C151
C151
VGA@
VGA@
+DPE_VDD18
1
C150
C150
2
VGA@
VGA@
0.1U_0402_16V7K
0.1U_0402_16V7K
DPE_VDD10: Output Driver Analo g Power Supply.
+1.1VS_PX
BLM18PG121SN1D_0603
B B
BLM18PG121SN1D_0603
DPE_VDD10=0.27A
L20
L20
1U_0402_6.3V4Z
1U_0402_6.3V4Z
12
VGA@
VGA@
10U_0805_10V4Z V GA@
10U_0805_10V4Z V GA@
C192
C192
1
2
1
2
C188
C188
VGA@
VGA@
+DPE_VDD10
1
C187
C187
VGA@
VGA@
2
0.1U_0402_16V7K
0.1U_0402_16V7K
4
U4H
U4H
AP20
NC_DPC_VDD18#1
AP21
+1.1VS_PX
+1.1VS_PX
R316
R316
150_0402_1%
150_0402_1%
1 2
VGA@
VGA@
+DPE_VDD18
+DPE_VDD10
+DPE_VDD18
+DPE_VDD10
R304
R304
150_0402_1%
150_0402_1%
1 2
VGA@
VGA@
NC_DPC_VDD18#2
AP13
DPC_VDD10#1
AT13
DPC_VDD10#2
AN17
DPC_VSSR#1
AP16
DPC_VSSR#2
AP17
DPC_VSSR#3
AW14
DPC_VSSR#4
AW16
DPC_VSSR#5
AP22
NC_DPD_VDD18#1
AP23
NC_DPD_VDD18#2
AP14
DPD_VDD10#1
AP15
DPD_VDD10#2
AN19
DPD_VSSR#1
AP18
DPD_VSSR#2
AP19
DPD_VSSR#3
AW20
DPD_VSSR#4
AW22
DPD_VSSR#5
AW18
DPCD_CALR
DP E/F POWER
DP E/F POWER
AH34
DPE_VDD18#1
AJ34
DPE_VDD18#2
AL33
DPE_VDD10#1
AM33
DPE_VDD10#2
AN34
DPE_VSSR#1
AP39
DPE_VSSR#2
AR39
DPE_VSSR#3
AU37
DPE_VSSR#4
AW35
DPE_VSSR#5
AF34
DPF_VDD18#1
AG34
DPF_VDD18#2
AK33
DPF_VDD10#1
AK34
DPF_VDD10#2
AF39
DPF_VSSR#1
AH39
DPF_VSSR#2
AK39
DPF_VSSR#3
AL34
DPF_VSSR#4
AM34
DPF_VSSR#5
AM39
DPEF_CALR
216-0729002 A12 M96_BGA 962
216-0729002 A12 M96_BGA 962
M92@
M92@
3
DP A/B POWERDP C/D POWER
DP A/B POWERDP C/D POWER
NC_DPA_VDD18#1
NC_DPA_VDD18#2
DPA_VDD10#1
DPA_VDD10#2
DPA_VSSR#1
DPA_VSSR#2
DPA_VSSR#3
DPA_VSSR#4
DPA_VSSR#5
NC_DPB_VDD18#1
NC_DPB_VDD18#2
DPB_VDD10#1
DPB_VDD10#2
DPB_VSSR#1
DPB_VSSR#2
DPB_VSSR#3
DPB_VSSR#4
DPB_VSSR#5
DPAB_CALR
DP PLL POWER
DP PLL POWER
DPA_PVDD
DPA_PVSS
DPB_PVDD
DPB_PVSS
DPC_PVDD
DPC_PVSS
DPD_PVDD
DPD_PVSS
DPE_PVDD
DPE_PVSS
NC_DPF_PVDD
NC_DPF_PVSS
DPA_VDD10: Transmitter Power 1 .1V +/-3%
AN24
AP24
DPA_VDD10=0.2A
+DPA_VDD10
1U_0402_6.3V4Z
VGA@
VGA@
+1.1VS_PX
R308
R308
150_0402_1%
150_0402_1%
1 2
VGA@
VGA@
+DPA_PVDD
+1.8VS_PX
+DPE_PVDD
+DPE_PVDD
1U_0402_6.3V4Z
1
1
C24110U_0603_6.3V6M
C24110U_0603_6.3V6M
2
2
VGA@
VGA@
C235
C235
1
C234
C234
0.1U_0402_16V7K
0.1U_0402_16V7K
2
VGA@
VGA@
AP31
AP32
AN27
AP27
AP28
AW24
AW26
AP25
AP26
AN33
AP33
AN29
AP29
AP30
AW30
AW32
AW28
AU28
AV27
AV29
AR28
AU18
AV17
AV19
AR18
AM37
AN38
AL38
AM35
2
+1.1VS_PX
L23
L23
BLM18PG121SN1D_0603
BLM18PG121SN1D_0603
12
VGA@
VGA@
DPA_PVDD=20mA
+DPA_PVDD
10U_0603_6.3V6M
10U_0603_6.3V6M
DPE_PVDD=20mA
+DPE_PVDD
10U_0603_6.3V6M
10U_0603_6.3V6M
DPA_PVDD: DP PLL Power 1.8V +/ -3%
1U_0402_6.3V4Z
C696
C696
VGA@
VGA@
1U_0402_6.3V4Z
1
2
VGA@
VGA@
1
C695
C695
2
BLM18PG121SN1D_0603
BLM18PG121SN1D_0603
1
C694
C694
0.1U_0402_16V7K
0.1U_0402_16V7K
2
VGA@
VGA@
DPE_PVDD: DP PLL Power 1.8V +/ -3%
1U_0402_6.3V4Z
C165
C165
VGA@
VGA@
1U_0402_6.3V4Z
1
2
VGA@
VGA@
1
C168
C168
2
BLM18PG121SN1D_0603
BLM18PG121SN1D_0603
1
C166
C166
0.1U_0402_16V7K
0.1U_0402_16V7K
2
VGA@
VGA@
L68
L68
VGA@
VGA@
L18
L18
VGA@
VGA@
1
+1.8VS_PX
12
+1.8VS_PX
12
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
2008/10/06 2009/10/06
2008/10/06 2009/10/06
2008/10/06 2009/10/06
3
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
M92 DRX PWR
M92 DRX PWR
M92 DRX PWR
KBLG0 LA-4921P
KBLG0 LA-4921P
KBLG0 LA-4921P
1
0.1
0.1
17 57Thursday, January 15, 2009
17 57Thursday, January 15, 2009
17 57Thursday, January 15, 2009
0.1
5
VDDR1+VDDRHA+VDDRHB=TBD(2.9A/M96)
1
+
+
C355 330U_V _2.5VM_R9M
C355 330U_V _2.5VM_R9M
VGA@
VGA@
2
D D
C C
1 2
C331 10U_060 3_6.3V6M VGA@C 331 10U_0603_6.3V6M VG A@
1 2
C239 10U_060 3_6.3V6M VGA@C 239 10U_0603_6.3V6M VG A@
1 2
C314 10U_060 3_6.3V6M VGA@C 314 10U_0603_6.3V6M VG A@
1 2
C376 10U_060 3_6.3V6M VGA@C 376 10U_0603_6.3V6M VG A@
1 2
C389 10U_060 3_6.3V6M VGA@C 389 10U_0603_6.3V6M VG A@
VDDR5 for DVPDATA[0..11]
+1.8VS_PX
L32 BLM18PG121 SN1D_0603
L32 BLM18PG121 SN1D_0603
+1.8VS_PX
L34 BLM18PG121 SN1D_0603
L34 BLM18PG121 SN1D_0603
B B
A A
12
VGA@
VGA@
VGA@
VGA@
2
1
10U_0603_6.3V6M
10U_0603_6.3V6M
12
2
1
10U_0603_6.3V6M
10U_0603_6.3V6M
VDDR4 for DVPDATA[12..23]
5
1U_0402_6.3V4Z
1U_0402_6.3V4Z
2
C366
C366
C364
C364
VGA@
VGA@
VGA@
VGA@
1
1U_0402_6.3V4Z
1U_0402_6.3V4Z
2
C374
C374
C377
C377
VGA@
VGA@
VGA@
VGA@
1
VDDR5=0.17A
2
C365
C365
VGA@
VGA@
1
0.1U_0402_16V7K
0.1U_0402_16V7K
VDDR4=0.17A
2
C375
C375
VGA@
VGA@
1
0.1U_0402_16V7K
0.1U_0402_16V7K
+1.8VS_PX
1 2
C339 1U_0402 _6.3V4Z VGA@C339 1U_0402 _6.3V4Z VGA@
1 2
C373 1U_0402 _6.3V4Z VGA@C373 1U_0402 _6.3V4Z VGA@
1 2
C370 1U_0402 _6.3V4Z VGA@C370 1U_0402 _6.3V4Z VGA@
1 2
C357 1U_0402 _6.3V4Z VGA@C357 1U_0402 _6.3V4Z VGA@
1 2
C361 1U_0402 _6.3V4Z VGA@C361 1U_0402 _6.3V4Z VGA@
1 2
C371 1U_0402 _6.3V4Z VGA@C371 1U_0402 _6.3V4Z VGA@
1 2
C326 1U_0402 _6.3V4Z VGA@C326 1U_0402 _6.3V4Z VGA@
1 2
C283 1U_0402 _6.3V4Z VGA@C283 1U_0402 _6.3V4Z VGA@
1 2
C338 1U_0402 _6.3V4Z VGA@C338 1U_0402 _6.3V4Z VGA@
1 2
C342 1U_0402 _6.3V4Z VGA@C342 1U_0402 _6.3V4Z VGA@
VDD_CT:Level translation betwe en core and I/O
+1.8VS_PX
L69 BLM 18PG121SN1D_0603
L69 BLM 18PG121SN1D_0603
+VDDR5
L60 BLM18PG121 SN1D_0603
L60 BLM18PG121 SN1D_0603
VGA@
VGA@
+VGA_CORE
10U_0603_6.3V6M
10U_0603_6.3V6M
L30 BLM18PG121 SN1D_0603
L30 BLM18PG121 SN1D_0603
SPV10: Dedicated power pin for memory
and engine PLLs.
4
VDD_CT=0.11A
VGA@
VGA@
12
1 2
C706 10U_060 3_6.3V6M VGA@C 706 10U_0603_6.3V6M VG A@
1 2
C271 1U_0402 _6.3V4Z VGA@C271 1U_0402 _6.3V4Z VGA@
1 2
C703 1U_0402 _6.3V4Z VGA@C703 1U_0402 _6.3V4Z VGA@
1 2
C702 1U_0402 _6.3V4Z VGA@C702 1U_0402 _6.3V4Z VGA@
1 2
C245 0.1U _0402_16V7K V GA@C245 0.1U_0402_16V7K VGA @
+3VS_DELAY
+VDD_CT
VDDR3:ROM+Sync+DDC
1 2
C266 10U_060 3_6.3V6M VGA@C 266 10U_0603_6.3V6M VG A@
1 2
C259 1U_0402 _6.3V4Z VGA@C259 1U_0402 _6.3V4Z VGA@
1 2
C258 1U_0402 _6.3V4Z VGA@C258 1U_0402 _6.3V4Z VGA@
1 2
C260 1U_0402 _6.3V4Z VGA@C260 1U_0402 _6.3V4Z VGA@
VDDRHA:MCLK PAD Power
+1.8VS_PX
L26 BLM18PG 121SN1D_0603@L26 BLM 18PG121SN1D_0603@
+1.8VS_PX
VDDRHB:MCLK PAD Power
1U_0402_6.3V4Z
1U_0402_6.3V4Z
12
2
2
C679
C679
VGA@
VGA@
1
12
10U_0603_6.3V6M
10U_0603_6.3V6M
4
2
C675
C675
VGA@
VGA@
1
0.1U_0402_16V7K
0.1U_0402_16V7K
2
C348
C348
VGA@
VGA@
1
VGA@
VGA@
1
C669
C669
VGA@
VGA@
+1.8VS_PX
1 2
C378 1U_0402 _6.3V4Z VGA@C378 1U_0402 _6.3V4Z VGA@
1 2
C363 1U_0402 _6.3V4Z VGA@C363 1U_0402 _6.3V4Z VGA@
1 2
C362 1U_0402 _6.3V4Z VGA@C362 1U_0402 _6.3V4Z VGA@
1 2
C369 1U_0402 _6.3V4Z VGA@C369 1U_0402 _6.3V4Z VGA@
1 2
C426 1U_0402 _6.3V4Z VGA@C426 1U_0402 _6.3V4Z VGA@
1 2
C372 1U_0402 _6.3V4Z VGA@C372 1U_0402 _6.3V4Z VGA@
1 2
C293 1U_0402 _6.3V4Z VGA@C293 1U_0402 _6.3V4Z VGA@
1 2
C282 1U_0402 _6.3V4Z VGA@C282 1U_0402 _6.3V4Z VGA@
1 2
C292 1U_0402 _6.3V4Z VGA@C292 1U_0402 _6.3V4Z VGA@
1 2
C350 1U_0402 _6.3V4Z VGA@C350 1U_0402 _6.3V4Z VGA@
+VDD_CT
VDDR3=50mA
+VDDR5
VDDRHA=20mA
VDDRHA for M96 ONLY
C304 1U_0402_6.3V4Z@C304 1U_0402_6.3V4Z@
VDDRHB=20mA
VGA@
VGA@
L33 BLM18PG121SN 1D_0603
L33 BLM18PG121SN 1D_0603
C349 1U_0402 _6.3V4Z
C349 1U_0402 _6.3V4Z
PCIE_PVDD=40mA
PCIE_PVDD:PCI-E PLL power.
1U_0402_6.3V4Z
1U_0402_6.3V4Z
2
C360
C360
VGA@
VGA@
1
+VGA_CORE
1U_0402_6.3V4Z
1U_0402_6.3V4Z
+VDDR4+VDDR4
+VDDARHA
12
1 2
+VDDARHB
12
1 2
VGA@
VGA@
+PCIE_PVDD
SPV10=414mA
+SPV10
2
C359
C359
VGA@
VGA@
1
0.1U_0402_16V7K
0.1U_0402_16V7K
BBP=0.12A
2
C327
C327
VGA@
VGA@
2
1
1
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
AC7
AD11
AF7
AG10
AJ7
AK8
AL9
G11
G14
G17
G20
G23
G26
G29
H10
J7
J9
K11
K13
K8
L12
L16
L21
L23
L26
L7
M11
N11
P7
R11
U11
U7
Y11
Y7
AF26
AF27
AG26
AG27
AF23
AF24
AG23
AG24
AF13
AF15
AG13
AG15
AD12
AF11
AF12
AG11
M20
M21
V12
U12
AB37
H7
H8
AM10
AN9
AN10
AA13
Y13
C318
C318
VGA@
VGA@
0.1U_0402_16V7K
0.1U_0402_16V7K
3
U4E
U4E
MEM I/O
MEM I/O
VDDR1#1
VDDR1#2
VDDR1#3
VDDR1#4
VDDR1#5
VDDR1#6
VDDR1#7
VDDR1#8
VDDR1#9
VDDR1#10
VDDR1#11
VDDR1#12
VDDR1#13
VDDR1#14
VDDR1#15
VDDR1#16
VDDR1#17
VDDR1#18
VDDR1#19
VDDR1#20
VDDR1#21
VDDR1#22
VDDR1#23
VDDR1#24
VDDR1#25
VDDR1#26
VDDR1#27
VDDR1#28
VDDR1#29
VDDR1#30
VDDR1#31
VDDR1#32
VDDR1#33
VDDR1#34
LEVEL
LEVEL
TRANSLATION
TRANSLATION
VDD_CT#1
VDD_CT#2
VDD_CT#3
VDD_CT#4
I/O
I/O
VDDR3#1
VDDR3#2
VDDR3#3
VDDR3#4
VDDR5#1
VDDR5#2
VDDR5#3
VDDR5#4
VDDR4#1
VDDR4#2
VDDR4#3
VDDR4#4
MEM CLK
MEM CLK
VDDRHA
VSSRHA
VDDRHB
VSSRHB
PLL
PLL
PCIE_PVDD
NC_MPV18#1
NC_MPV18#2
NC_SPV18
SPV10
SPVSS
BACK BIAS
BACK BIAS
BBP#1
BBP#2
216-0729002 A12 M96_BGA 962
216-0729002 A12 M96_BGA 962
2008/10/06 2009/10/06
2008/10/06 2009/10/06
2008/10/06 2009/10/06
3
PCIE
PCIE
PCIE_VDDR#1
PCIE_VDDR#2
PCIE_VDDR#3
PCIE_VDDR#4
PCIE_VDDR#5
PCIE_VDDR#6
PCIE_VDDR#7
PCIE_VDDR#8
PCIE_VDDC#1
PCIE_VDDC#2
PCIE_VDDC#3
PCIE_VDDC#4
PCIE_VDDC#5
PCIE_VDDC#6
PCIE_VDDC#7
PCIE_VDDC#8
PCIE_VDDC#9
PCIE_VDDC#10
PCIE_VDDC#11
PCIE_VDDC#12
CORE
CORE
VDDC#10
VDDC#11
VDDC#12
VDDC#13
VDDC#14
VDDC#15
POWER
POWER
VDDC#16
VDDC#17
VDDC#18
VDDC#19
VDDC#20
VDDC#21
VDDC#22
VDDC#23
VDDC#24
VDDC#25
VDDC#26
VDDC#27
VDDC#28
VDDC#29
VDDC#30
VDDC#31
VDDC#32
VDDC#33
VDDC#34
VDDC#35
VDDC#36
VDDC#37
VDDC#38
VDDC#39
VDDC#40
VDDC#41
VDDC#42
VDDC#43
VDDC#44
VDDC#45
VDDC#46
VDDC#47
VDDC#48
VDDC#49
VDDC#50
VDDC#51
VDDC#52
VDDC#53
VDDC#54
VDDC#55
VDDC#56
VDDC#57
VDDC#58
VDDC#59
VDDC#60
VDDC#61
VDDC#62
VDDC#63
VDDC#64
VDDC#65
VDDC#66
VDDC#67
VDDC#68
VDDC#69
VDDC#70
VDDC#71
VDDC#72
VDDC#73
VDDC#74
VDDCI#1
ISOLATED
ISOLATED
VDDCI#2
CORE I/O
CORE I/O
VDDCI#3
VDDCI#4
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
VDDC#1
VDDC#2
VDDC#3
VDDC#4
VDDC#5
VDDC#6
VDDC#7
VDDC#8
VDDC#9
M92@
M92@
+PCIE_VDDR_M92
AA31
AA32
AA33
AA34
V28
W29
W30
Y31
G30
G31
H29
H30
J29
J30
L28
M28
N28
R28
T28
U28
AA15
AA17
AA20
AA22
AA24
AA27
AB13
AB16
AB18
AB21
AB23
AB26
AB28
AC12
AC15
AC17
AC20
AC22
AC24
AC27
AD13
AD16
AD18
AD21
AD23
AD26
AF17
AF20
AF22
AG16
AG18
AG21
AH22
M16
M18
M23
M26
N15
N17
N20
N22
N24
N27
R13
R16
R18
R21
R23
R26
T15
T17
T20
T22
T24
T27
U16
U18
U21
U23
U26
V15
V17
V20
V22
V24
V27
Y16
Y18
Y21
Y23
Y26
Y28
AH27
AH28
M15
N13
R12
T12
2
PCIE_VDDR=0.5A
PCIE_VDDR:PCI-E I/O power.
PCIE_VDDC: PCI-E Digital Power Supply
+1.1VS_PX
PCIE_VDDC=2A
1 2
C196 10U_060 3_6.3V6M VGA@C 196 10U_0603_6.3V6M VGA@
1 2
C233 1U_0402 _6.3V4Z VGA@C233 1U_0402 _6.3V4Z VGA@
1 2
C229 1U_0402 _6.3V4Z VGA@C229 1U_0402 _6.3V4Z VGA@
1 2
C242 1U_0402 _6.3V4Z VGA@C242 1U_0402 _6.3V4Z VGA@
1 2
C220 1U_0402 _6.3V4Z VGA@C220 1U_0402 _6.3V4Z VGA@
1 2
C216 1U_0402 _6.3V4Z VGA@C216 1U_0402 _6.3V4Z VGA@
1 2
C217 1U_0402 _6.3V4Z VGA@C217 1U_0402 _6.3V4Z VGA@
1 2
C202 1U_0402 _6.3V4Z VGA@C202 1U_0402 _6.3V4Z VGA@
1 2
C311 10U_060 3_6.3V6M VGA@C 311 10U_0603_6.3V6M VGA@
1 2
C312 10U_060 3_6.3V6M VGA@C 312 10U_0603_6.3V6M VGA@
1 2
C313 10U_060 3_6.3V6M VGA@C 313 10U_0603_6.3V6M VGA@
1 2
C263 10U_060 3_6.3V6M VGA@C 263 10U_0603_6.3V6M VGA@
1 2
C264 10U_060 3_6.3V6M VGA@C 264 10U_0603_6.3V6M VGA@
1 2
C265 10U_060 3_6.3V6M VGA@C 265 10U_0603_6.3V6M VGA@
1 2
C262 10U_060 3_6.3V6M VGA@C 262 10U_0603_6.3V6M VGA@
1 2
C252 1U_0402 _6.3V4Z VGA@C252 1U_0402 _6.3V4Z VGA@
1 2
C289 1U_0402 _6.3V4Z VGA@C289 1U_0402 _6.3V4Z VGA@
1 2
C351 1U_0402 _6.3V4Z VGA@C351 1U_0402 _6.3V4Z VGA@
VDDC+VDDCI=16A
C352 1U_0402 _6.3V4Z VGA@C352 1U_0402 _6.3V4Z VGA@
C343 1U_0402 _6.3V4Z VGA@C343 1U_0402 _6.3V4Z VGA@
C279 1U_0402 _6.3V4Z VGA@C279 1U_0402 _6.3V4Z VGA@
C291 1U_0402 _6.3V4Z VGA@C291 1U_0402 _6.3V4Z VGA@
C299 1U_0402 _6.3V4Z VGA@C299 1U_0402 _6.3V4Z VGA@
C336 1U_0402 _6.3V4Z VGA@C336 1U_0402 _6.3V4Z VGA@
C298 1U_0402 _6.3V4Z VGA@C298 1U_0402 _6.3V4Z VGA@
C328 1U_0402 _6.3V4Z VGA@C328 1U_0402 _6.3V4Z VGA@
C270 1U_0402 _6.3V4Z VGA@C270 1U_0402 _6.3V4Z VGA@
C269 1U_0402 _6.3V4Z VGA@C269 1U_0402 _6.3V4Z VGA@
C284 1U_0402 _6.3V4Z VGA@C284 1U_0402 _6.3V4Z VGA@
C335 1U_0402 _6.3V4Z VGA@C335 1U_0402 _6.3V4Z VGA@
C320 1U_0402 _6.3V4Z VGA@C320 1U_0402 _6.3V4Z VGA@
C286 1U_0402 _6.3V4Z VGA@C286 1U_0402 _6.3V4Z VGA@
C247 1U_0402 _6.3V4Z VGA@C247 1U_0402 _6.3V4Z VGA@
C287 1U_0402 _6.3V4Z VGA@C287 1U_0402 _6.3V4Z VGA@
C275 1U_0402 _6.3V4Z VGA@C275 1U_0402 _6.3V4Z VGA@
C332 1U_0402 _6.3V4Z VGA@C332 1U_0402 _6.3V4Z VGA@
C288 1U_0402 _6.3V4Z VGA@C288 1U_0402 _6.3V4Z VGA@
C330 1U_0402 _6.3V4Z VGA@C330 1U_0402 _6.3V4Z VGA@
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
L22 BLM18PG1 21SN1D_0603
L22 BLM18PG1 21SN1D_0603
C221 10U_060 3_6.3V6M VGA@C 221 10U_0603_6.3V6M VG A@
C237 1U_0402 _6.3V4Z VGA@C237 1U_0402 _6.3V4Z VGA@
C193 1U_0402 _6.3V4Z VGA@C193 1U_0402 _6.3V4Z VGA@
C199 1U_0402 _6.3V4Z VGA@C199 1U_0402 _6.3V4Z VGA@
C236 1U_0402 _6.3V4Z VGA@C236 1U_0402 _6.3V4Z VGA@
C213 1U_0402 _6.3V4Z VGA@C213 1U_0402 _6.3V4Z VGA@
C212 0.1U _0402_16V7K V GA@C212 0.1U_0402_16V7K VGA @
C232 0.1U _0402_16V7K V GA@C232 0.1U_0402_16V7K VGA @
1
+
+
C243
C243
330U_V_2.5VM_R9M
330U_V_2.5VM_R9M
2
VDDCI: Isolated (clean) core p ower for the l/O logic
+VDDCI
1U_0402_6.3V4Z
1U_0402_6.3V4Z
2
1
2
2
C347
C347
1
VGA@
VGA@
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
C356
C356
VGA@
VGA@
1U_0402_6.3V4Z
1U_0402_6.3V4Z
Title
Title
Title
Custom
Custom
Custom
1U_0402_6.3V4Z
1U_0402_6.3V4Z
2
1
2
C344
C344
VGA@
VGA@
C358
C358
1
VGA@
VGA@
10U_0603_6.3V6M
10U_0603_6.3V6M
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
M92 POWER
M92 POWER
M92 POWER
KBLG0 LA-4921P
KBLG0 LA-4921P
KBLG0 LA-4921P
1
+1.8VS_PX
VGA@
VGA@
12
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1
+
+
C333
C333
330U_V_2.5VM_R9M
VGA@
VGA@
VGA@
VGA@
L31 BLM 18PG121SN1D_0603
L31 BLM 18PG121SN1D_0603
330U_V_2.5VM_R9M
VGA@
VGA@
2
1 2
C337 1U_0402 _6.3V4Z VGA@C337 1U_0402 _6.3V4Z VGA@
1 2
C329 1U_0402 _6.3V4Z VGA@C329 1U_0402 _6.3V4Z VGA@
1 2
C353 1U_0402 _6.3V4Z VGA@C353 1U_0402 _6.3V4Z VGA@
1 2
C240 1U_0402 _6.3V4Z VGA@C240 1U_0402 _6.3V4Z VGA@
1 2
C322 1U_0402 _6.3V4Z VGA@C322 1U_0402 _6.3V4Z VGA@
1 2
C285 1U_0402 _6.3V4Z VGA@C285 1U_0402 _6.3V4Z VGA@
1 2
C321 1U_0402 _6.3V4Z VGA@C321 1U_0402 _6.3V4Z VGA@
1 2
C316 1U_0402 _6.3V4Z VGA@C316 1U_0402 _6.3V4Z VGA@
1 2
C251 1U_0402 _6.3V4Z VGA@C251 1U_0402 _6.3V4Z VGA@
1 2
C248 1U_0402 _6.3V4Z VGA@C248 1U_0402 _6.3V4Z VGA@
1 2
C296 1U_0402 _6.3V4Z VGA@C296 1U_0402 _6.3V4Z VGA@
1 2
C334 1U_0402 _6.3V4Z VGA@C334 1U_0402 _6.3V4Z VGA@
1 2
C297 1U_0402 _6.3V4Z VGA@C297 1U_0402 _6.3V4Z VGA@
1 2
C267 1U_0402 _6.3V4Z VGA@C267 1U_0402 _6.3V4Z VGA@
1 2
C268 1U_0402 _6.3V4Z VGA@C268 1U_0402 _6.3V4Z VGA@
1 2
C250 1U_0402 _6.3V4Z VGA@C250 1U_0402 _6.3V4Z VGA@
1 2
C261 1U_0402 _6.3V4Z VGA@C261 1U_0402 _6.3V4Z VGA@
1 2
C323 1U_0402 _6.3V4Z VGA@C323 1U_0402 _6.3V4Z VGA@
1 2
C315 1U_0402 _6.3V4Z VGA@C315 1U_0402 _6.3V4Z VGA@
1 2
C346 1U_0402 _6.3V4Z VGA@C346 1U_0402 _6.3V4Z VGA@
+VGA_CORE
12
18 57Thursday, January 15, 2009
18 57Thursday, January 15, 2009
18 57Thursday, January 15, 2009
1
+VGA_CORE
0.1
0.1
0.1
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