1
2
3
4
5
6
7
8
+3V/+5V S5
PG.39
+1.05V/+1.5V
A A
PG.40/45
CPU Core
PG.42~43
DDR4
PG.41
Charge
PG.38
VGA POWER
PG.46~47
B B
VCCGT/VCCSA
PG.44
INTEL SYSTEM DIAGRAM
PEG
PG.33
2400MT/s
DDR4 L
Channel A
2400MT/s
DDR4 L
Channel B
SATA2 6GB/s
INTEL
SkyLake-H
Processor : Daul / Quad Core
Power : 45 (Watt)
Package : BGA1400
Size : 42 x 28 (mm)
PG.2~8
DMI
eDP (5.4Gb/s)
SODIMM1
Max. 16GB
STD
PG.17
SODIMM2
Max. 16GB
STD
PG.18
HDD
DDI2
DDI1
eDP
GPU
N16P-GT
P19~P23
eDP Conn.
ITE6515
P28
PS8407
P30
X'TAL 27MHz
P29
VRAM
DDR3
VGA Conn.
HDMI Conn.
P24~P27
P29
P30
01
INTEL PCH
Lynx Point
PCI-E x 1
Port4 Port3
LAN
RTL8111GSH
10/100/1000
WLAN
BT COMBO
PG.34 PG.31
USB 2.0
PORT7
PCI-E x 4
C C
SATA0~1 6GB/s
NGFF SSD
PG.34
Power : Watt
Package : FCBGA837
Size : 23 x 23 (mm)
PG.9~15
Azalia
USB 3.0
PORT1,2
USB 2.0
USB3-1 & USB3-2
USB3.0 Ports
PG.36
PORT1,2
X2
Webcam
PG.29
PORT9
PORT5
DB IO Port
PG.36
Card Reader
PG.36
PORT10
PORT8
Touch Screen
PG.29
PG.37
FAN ROM
LPC
AUDIO
CODEC
G- Sensor
3
P35
ALC255
Speaker
PAGE 32
4
PG.32
Dual Digital MIC
PAGE 32
Universal HP
5
P32
PROJECT :ZRY
PROJECT :ZRY
PROJECT :ZRY
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
BLOCK DIAGRAM
BLOCK DIAGRAM
BLOCK DIAGRAM
Date: Sheet of
Date: Sheet of
Date: Sheet of
6
7
8
1A
1A
1A
14 9 Monday, September 07, 2015
14 9 Monday, September 07, 2015
14 9 Monday, September 07, 2015
KBC
ITE IT8987E/BX
LPC Interface
TPM
PAGE 33 NPCT650
SLG3NB3454
L
D D
1
GreenCLK
25MHz
TP KB
PG.35 PG.35 PG.35 PG.12
PAGE 33
2
5
4
3
2
1
Host CLK:
Trace length < 11000 MILS
Trace spacing = 15 ,20 MILS, Impendence 90 ohm
CLK_CPU_BCLKP 11
CLK_CPU_BCLKN 11
D D
H_PECI (50ohm)
Route on micro strip only
Spacing > 18 mils
Trace Length: 15 inch
CPU RESET#
C C
HPECI Ra,Ca n eed placement close to EC.
PCH_PECI 11
EC_PECI 37
CPU_PLTRST#R 11
PLTRST# 12,16,19,31,33,34,37
CPU_PLTRST# ( 50ohm)
Trace Length: 10~17 inches
R563 13/F_4
C802 *47P/50V_4
PROCHOT# (50ohm)
Trace Length <11 inches
THERMTRIP# (50ohm)
Trace Length: 1.1~12 inches
Ra
EC_PECI
Ca
H_PROCHOT# 37,38,42
C807
Cb
Change net name_20141203
PM_SYNC (50ohm)
Trace Length: 1~11.25 inches
R541 *1.5K/F_4
R542 *750/F_4
PM_THRMTRIP# 5,11,17,18
+VCCSTPLL
R626 1K_4
Rb need placment near PCH
47P/50V_4
PM_THRMTRIP#
Rb
+VCCSTPLL
CPU_PCI_BCLKP 11
CPU_PCI_BCLKN 11
CLK_DPLL_NSCCLKP 11
CLK_DPLL_NSCCLKN 11
R567 499/F_4
H_PROCHOT#_R
Cb need placment near VR
DDR_VTT_CNTL 17
PROCPWRGD (50ohm)
Trace Length: 1~11.25 inches
VCCST_PWRGD 16
PROCPWRGD 10
R553 *SHORT_4
SKTOCC_N_R 13
PM_SYNC 11
+VCCSTPLL
R571 49.9/F_4
R560 *10K_4
New CN to PCH pin Y44_20141203
H_PM_DOWN 11
R559 20_4
R14 need change to 20ohm
HWPD
CPU CORE SVID
Layout note: need routing together and ALERT need between CLK and DATA.
B B
CLOSE TO CPU
PLACE THE PU RESISTORS
H_CPU_SVIDALRT#
PLACE THE PU RESISTORS
CLOSE TO V R
PULL UP IS IN THE VR MODULE
VR_SVID_CLK_R
CLOSE TO CPU
PLACE THE PU RESISTORS
A A
H_CPU_SVIDDAT
R545 220/F_4
R540 *SHORT_4
5
*1000p/50V_4
+VCCSTPLL
+VCCSTPLL
C85
+VCCSTPLL
R538
56.2/F_4
C755
*0.1U/16V_4
R539
*54.9/F_4
R544
100/F_4
SVID ALERT
SVID CLK
R543 *SHORT_4
VR_SVID_ALERT# 42
VR_SVID_CLK 42
SVID DATA
VR_SVID_DATA 42
4
VCCST_PWRGD
R179 60.4/F_4
C417
*0.1u/16V_4
CPU thermal trip
IMVP_PW RGD 42
SKYLAKE Processor (CLK,MISC,JTAG)
SKYLAKE_HALO
U41E
CLK_CPU_BCLKP
CLK_CPU_BCLKN
CPU_PCI_BCLKP
CPU_PCI_BCLKN
CLK_DPLL_NSCCLKP
CLK_DPLL_NSCCLKN
H_CPU_SVIDALRT#
VR_SVID_CLK_R
H_CPU_SVIDDAT
DDR_VTT_CNTL
VCCST_PWRGD
PROCPWRGD
H_PM_DOWN_R
EC_PECI
R556 *SHORT_4
R181 *0_4
R180 *100K/F_4
H_PM_DOWN_R
+VCCSTPLL
R178
*1K_4
Shortpad change
to 60.4 ohm. 11/6
SKTOCC_N SKTOCC_N_R
CATERR#
+1.0V
R203
1K_4
U22
NC1VCC
2
A
GND3Y
*74AUP1G07GW
R182 *SHORT_4
B31
BCLKP
A32
BCLKN
D35
PCI_BCLKP
C36
PCI_BCLKN
E31
CLK24P
D31
CLK24N
BH31
VIDALERT#
BH32
VIDSCK
BH29
VIDSOUT
BR30
PROCHOT#
BT13
DDR_VTT_CNTL
H13
VCCST_PWRGD
BT31
PROCPWRGD
BP35
RESET#
BM34
PM_SYNC
BP31
PM_DOWN
BT34
PECI
J31
THERMTRIP#
BR33
SKTOCC#
BN1
PROC_SELECT#
BM30
CATERR#
SKL_H_BGA_BGA
CRB is via +1.05V PG VCCST PWRGD
+3V_S5
C420
0.1u/16V_4
VCCST_PWRGD_R
+VCCSTPLL
5
C441
*0.1u/16V_4
4
3
1 2
BGA1440
U21
5
VCC
4
Y
74AUP1G07GW
+3V
R200
*10K_4
5 OF 14
NC
A
GND
PROC_TRST#
PROC_PREQ#
PROC_PRDY#
CFG_RCOMP
1
2
3
IMVP_PW RGD_3V 10
CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[17]
CFG[16]
CFG[19]
CFG[18]
BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
PROC_TDO
PROC_TDI
PROC_TMS
PROC_TCK
BN25
BN27
BN26
BN28
BR20
BM20
BT20
BP20
BR23
BR22
BT23
BT22
BM19
BR19
BP19
BT19
BN23
BP23
BP22
BN22
BR27
BT27
BM31
BT30
BT28
BL32
BP28
BR28
BP30
BL30
BP27
BT25
VCCST_PWRGD_EN_L
IMVP_PW RGD_3V
PM_THRMTRIP#
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG17
CFG16
CFG18
CFG19
XDP_BPM0
XDP_BPM1
XDP_BPM2
XDP_BPM3
XDP_TDO_CPU
XDP_TDI_CPU
XDP_TMS_CPU
XDP_TRST#_CPU
XDP_TRST#
XDP_PREQ#
XDP_PRDY#
CFG_RCOMP
+VCCSTPLL
CFG0 16
CFG1 16
CFG2 8,16
CFG3 8,16
CFG4 8,16
CFG5 8,16
CFG6 8,16
CFG7 16
CFG8 16
CFG9 16
CFG10 8,16
CFG11 16
CFG12 8,16
CFG13 8,16
CFG14 16
CFG15 16
CFG17 16
CFG16 16
CFG18 16
CFG19 16
U53
TC7SH08FU
+VCCSTPLL
2
R186
*1K_4
1 3
Q23 MMBT3904 -7-F
XDP_BPM0 16
XDP_BPM1 16
TP17
TP18
XDP_TDO_CPU 16
XDP_TDI_CPU 16
XDP_TMS_CPU 16
R300 *0_4
XDP_TRST# 15,16
XDP_PREQ# 15,16
XDP_PRDY# 15,16
R129 49.9/F_4
+3V_S5
4
3 5
R969 *0_4
3
Q20
FDV301N
1
1 2
R191
1K_4
2
2
CPU XDP
C812 0.1u/16V_4
2
SUSB#
1
VCCST_PWRGD_EN
R184
*100K_4
Processor pull-up (CPU)
H_PROCHOT#
XDP_TDO_CPU
XDP_TMS_CPU
XDP_TDI_CPU
XDP_PREQ#
XDP_TRST#_CPU
XDP_TRST#
JTAGX_PCH 10,16
SUSB# 10,16,37,39
R566 1K_4
R578 51_4
R577 *51_4
R558 *51_4
R572 *51_4
R579 *51_4
R564 51_4
B2A
S0->S5 & S0->S3
Power of sequence 1us
SUSB# -> VCCST_PWRGD
R204 *0_4
R202 *SHORT_4
CPU VDDQ
Del R2574_20141217
Note: please keep plane is enough for VDDQ 2.8A
SYS_SHDN# 39,45
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
PROJECT :ZRY
PROJECT :ZRY
PROJECT :ZRY
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
02 -- SKYPAKE 1/20(eDP/DDI)
02 -- SKYPAKE 1/20(eDP/DDI)
02 -- SKYPAKE 1/20(eDP/DDI)
PCH_PWROK
HWPG
R205
10K_4
+1.2VSUS
1
+1.0V
R565 *SHORT_4
R570 *0_4
C403 0.1U/16V_4
C402 *0.1U/16V_4
02
+1.0V
+VCCSTPLL
PCH_PWROK 10,37
HWPG 10,37
Placement close to CPU.
24 9 Monday, September 07, 2015
24 9 Monday, September 07, 2015
24 9 Monday, September 07, 2015
1A
1A
1A
5
PEG_RX15 19
PEG_RX#15 19
PEG_RX14 19
PEG_RX#14 19
PEG_RX13 19
+VCCIO
PEG_RX#13 19
PEG_RX12 19
PEG_RX#12 19
PEG_RX11 19
PEG_RX#11 19
PEG_RX10 19
PEG_RX#10 19
PEG_RX9 19
PEG_RX#9 19
PEG_RX8 19
PEG_RX#8 19
PEG_RX7 19
PEG_RX#7 19
PEG_RX6 19
PEG_RX#6 19
PEG_RX5 19
PEG_RX#5 19
PEG_RX4 19
PEG_RX#4 19
PEG_RX3 19
PEG_RX#3 19
PEG_RX2 19
PEG_RX#2 19
PEG_RX1 19
PEG_RX#1 19
PEG_RX0 19
PEG_RX#0 19
DMI_RXP0 9
DMI_RXN0 9
DMI_RXP1 9
DMI_RXN1 9
DMI_RXP2 9
DMI_RXN2 9
DMI_RXP3 9
DMI_RXN3 9
D D
Lane Reversed
C C
dGPU PEG*16
PEG_RCOMP
Trace length < 400 MILS
Trace width = 12 MILS
Trace spacing = 15 MILS
DMI
4
SKYLAKE Processor (DMI, PEG,FDI )
E25
D25
E24
F24
E23
D23
E22
F22
E21
D21
E20
F20
E19
D19
E18
F18
D17
E17
F16
E16
D15
E15
F14
E14
D13
E13
F12
E12
D11
E11
F10
E10
R194 24.9/F_4
PEG_COMP
G2
D8
E8
E6
F6
D5
E5
J8
J9
PEG_RXP[0]
PEG_RXN[0]
PEG_RXP[1]
PEG_RXN[1]
PEG_RXP[2]
PEG_RXN[2]
PEG_RXP[3]
PEG_RXN[3]
PEG_RXP[4]
PEG_RXN[4]
PEG_RXP[5]
PEG_RXN[5]
PEG_RXP[6]
PEG_RXN[6]
PEG_RXP[7]
PEG_RXN[7]
PEG_RXP[8]
PEG_RXN[8]
PEG_RXP[9]
PEG_RXN[9]
PEG_RXP[10]
PEG_RXN[10]
PEG_RXP[11]
PEG_RXN[11]
PEG_RXP[12]
PEG_RXN[12]
PEG_RXP[13]
PEG_RXN[13]
PEG_RXP[14]
PEG_RXN[14]
PEG_RXP[15]
PEG_RXN[15]
PEG_RCOMP
DMI_RXP[0]
DMI_RXN[0]
DMI_RXP[1]
DMI_RXN[1]
DMI_RXP[2]
DMI_RXN[2]
DMI_RXP[3]
DMI_RXN[3]
SKYLAKE_HALO
U41C
SKL_H_BGA_BGA
BGA1440
3 OF 14
PEG_TXP[0]
PEG_TXN[0]
PEG_TXP[1]
PEG_TXN[1]
PEG_TXP[2]
PEG_TXN[2]
PEG_TXP[3]
PEG_TXN[3]
PEG_TXP[4]
PEG_TXN[4]
PEG_TXP[5]
PEG_TXN[5]
PEG_TXP[6]
PEG_TXN[6]
PEG_TXP[7]
PEG_TXN[7]
PEG_TXP[8]
PEG_TXN[8]
PEG_TXP[9]
PEG_TXN[9]
PEG_TXP[10]
PEG_TXN[10]
PEG_TXP[11]
PEG_TXN[11]
PEG_TXP[12]
PEG_TXN[12]
PEG_TXP[13]
PEG_TXN[13]
PEG_TXP[14]
PEG_TXN[14]
PEG_TXP[15]
PEG_TXN[15]
DMI_TXP[0]
DMI_TXN[0]
DMI_TXP[1]
DMI_TXN[1]
DMI_TXP[2]
DMI_TXN[2]
DMI_TXP[3]
DMI_TXN[3]
B25
A25
B24
C24
B23
A23
B22
C22
B21
A21
B20
C20
B19
A19
B18
C18
A17
B17
C16
B16
A15
B15
C14
B14
A13
B13
C12
B12
A11
B11
C10
B10
B8
A8
C6
B6
B5
A5
D4
B4
C_PEG_TX15
C_PEG_TX#15
C_PEG_TX14
C_PEG_TX#14
C_PEG_TX13
C_PEG_TX#13
C_PEG_TX12
C_PEG_TX#12
C_PEG_TX11
C_PEG_TX#11
C_PEG_TX10
C_PEG_TX#10
C_PEG_TX9
C_PEG_TX#9
C_PEG_TX8
C_PEG_TX#8
C_PEG_TX7
C_PEG_TX#7
C_PEG_TX6
C_PEG_TX#6
C_PEG_TX5
C_PEG_TX#5
C_PEG_TX4
C_PEG_TX#4
C_PEG_TX3
C_PEG_TX#3
C_PEG_TX2
C_PEG_TX#2
C_PEG_TX1
C_PEG_TX#1
C_PEG_TX0
C_PEG_TX#0
3
C1194 EV@0.22u/10V_4
C1195 EV@0.22u/10V_4
C1200 EV@0.22u/10V_4
C1198 EV@0.22u/10V_4
C1197 EV@0.22u/10V_4
C1196 EV@0.22u/10V_4
C1201 EV@0.22u/10V_4
C1199 EV@0.22u/10V_4
C1202 EV@0.22u/10V_4
C1203 EV@0.22u/10V_4
C1208 EV@0.22u/10V_4
C1206 EV@0.22u/10V_4
C1205 EV@0.22u/10V_4
C1204 EV@0.22u/10V_4
C1209 EV@0.22u/10V_4
C1207 EV@0.22u/10V_4
C813 EV@0.22u/10V_4
C811 EV@0.22u/10V_4
C814 EV@0.22u/10V_4
C815 EV@0.22u/10V_4
C817 EV@0.22u/10V_4
C816 EV@0.22u/10V_4
C819 EV@0.22u/10V_4
C818 EV@0.22u/10V_4
C822 EV@0.22u/10V_4
C820 EV@0.22u/10V_4
C823 EV@0.22u/10V_4
C825 EV@0.22u/10V_4
C827 EV@0.22u/10V_4
C826 EV@0.22u/10V_4
C828 EV@0.22u/10V_4
C830 EV@0.22u/10V_4
DMI_TXP0 9
DMI_TXN0 9
DMI_TXP1 9
DMI_TXN1 9
DMI_TXP2 9
DMI_TXN2 9
DMI_TXP3 9
DMI_TXN3 9
PEG_TX15 19
PEG_TX#15 19
PEG_TX14 19
PEG_TX#14 19
PEG_TX13 19
PEG_TX#13 19
PEG_TX12 19
PEG_TX#12 19
PEG_TX11 19
PEG_TX#11 19
PEG_TX10 19
PEG_TX#10 19
PEG_TX9 19
PEG_TX#9 19
PEG_TX8 19
PEG_TX#8 19
PEG_TX7 19
PEG_TX#7 19
PEG_TX6 19
PEG_TX#6 19
PEG_TX5 19
PEG_TX#5 19
PEG_TX4 19
PEG_TX#4 19
PEG_TX3 19
PEG_TX#3 19
PEG_TX2 19
PEG_TX#2 19
PEG_TX1 19
PEG_TX#1 19
PEG_TX0 19
PEG_TX#0 19
Lane Reversed
2
1
03
SKYLAKE_HALO
U41D
SKL_H_BGA_BGA
BGA1440
4 OF 14
EDP_TXP[0]
EDP_TXN[0]
EDP_TXP[1]
EDP_TXN[1]
EDP_TXN[2]
EDP_TXP[2]
EDP_TXN[3]
EDP_TXP[3]
EDP_AUXP
EDP_AUXN
EDP_DISP_UTIL
EDP_RCOMP
PROC_AUDIO_CLK
PROC_AUDIO_SDI
PROC_AUDIO_SDO
D29
E29
F28
E28
B29
A29
B28
C28
C26
B26
A33
D37
G27
G25
G29
B B
A A
5
HDMI
CRT
CRT_AUXP 28
CRT_AUXN 28
CRT_AUX_C
CRT_AUX#_C
4
K36
K37
J35
J34
H37
H36
J37
J38
D27
E27
H34
H33
F37
G38
F34
F35
E37
E36
F26
E26
C34
D34
B36
B34
F33
E33
C33
B33
A27
B27
DDI1_TXP[0]
DDI1_TXN[0]
DDI1_TXP[1]
DDI1_TXN[1]
DDI1_TXP[2]
DDI1_TXN[2]
DDI1_TXP[3]
DDI1_TXN[3]
DDI1_AUXP
DDI1_AUXN
DDI2_TXP[0]
DDI2_TXN[0]
DDI2_TXP[1]
DDI2_TXN[1]
DDI2_TXP[2]
DDI2_TXN[2]
DDI2_TXP[3]
DDI2_TXN[3]
DDI2_AUXP
DDI2_AUXN
DDI3_TXP[0]
DDI3_TXN[0]
DDI3_TXP[1]
DDI3_TXN[1]
DDI3_TXP[2]
DDI3_TXN[2]
DDI3_TXP[3]
DDI3_TXN[3]
DDI3_AUXP
DDI3_AUXN
IN_D2
IN_D2 30
IN_D2#
IN_D2# 30
IN_D1
IN_D1 30
IN_D1#
IN_D1# 30
IN_D0
IN_D0 30
IN_D0#
IN_D0# 30
IN_CLK
IN_CLK 30
IN_CLK#
IN_CLK# 30
CRT_TXP0 28
CRT_TXN0 28
CRT_TXP1 28
CRT_TXN1 28
R998 *short_4
R999 *short_4
eDP
EDP_TXP0 29
EDP_TXN0 29
EDP_TXP1 29
EDP_TXN1 29
EDP_TXN2 29
EDP_TXP2 29
EDP_TXN3 29
EDP_TXP3 29
EDP_AUXP 29
EDP_AUXN 29
EDP_DISP_UTIL
EDP_RCOMP
DP & PEG Compensation
eDP_RCOMP
Trace length < 100 Mils
Trace Width 20 Mils Trace Spacing 25 Mils
AUD_AZACPU_SO
TP87
R127 *SHORT_4
R126 20_4
3
R116 24.9/F_4
+VCCIO
+VCCIO 6 ,16,38,40,42, 45
+1.0V 2,5,6,10,1 6,40,45
AUD_AZACPU_SCLK 10
AUD_AZACPU_SDO 10
AUD_AZACPU_SDI 10
PROJECT :ZRY
PROJECT :ZRY
PROJECT :ZRY
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
SNB 1/5 (PCIE&DMI&FDI)
SNB 1/5 (PCIE&DMI&FDI)
SNB 1/5 (PCIE&DMI&FDI)
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
1
1A
1A
1A
34 9 Tuesday, Augu st 25, 2015
34 9 Tuesday, Augu st 25, 2015
34 9 Tuesday, Augu st 25, 2015
5
4
3
2
1
SKYLAKE Processor (DDR3)
D D
C C
B B
M_A_DQ[63:0] 17
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
U41A
BR6
DDR0_DQ[0]
BT6
DDR0_DQ[1]
BP3
DDR0_DQ[2]
BR3
DDR0_DQ[3]
BN5
DDR0_DQ[4]
BP6
DDR0_DQ[5]
BP2
DDR0_DQ[6]
BN3
DDR0_DQ[7]
BL4
DDR0_DQ[8]
BL5
DDR0_DQ[9]
BL2
DDR0_DQ[10]
BM1
DDR0_DQ[11]
BK4
DDR0_DQ[12]
BK5
DDR0_DQ[13]
BK1
DDR0_DQ[14]
BK2
DDR0_DQ[15]
BG4
DDR0_DQ[16]/DDR0_DQ[32]
BG5
DDR0_DQ[17]/DDR0_DQ[33]
BF4
DDR0_DQ[18]/DDR0_DQ[34]
BF5
DDR0_DQ[19]/DDR0_DQ[35]
BG2
DDR0_DQ[20]/DDR0_DQ[36]
BG1
DDR0_DQ[21]/DDR0_DQ[37]
BF1
DDR0_DQ[22]/DDR0_DQ[38]
BF2
DDR0_DQ[23]/DDR0_DQ[39]
BD2
DDR0_DQ[24]/DDR0_DQ[40]
BD1
DDR0_DQ[25]/DDR0_DQ[41]
BC4
DDR0_DQ[26]/DDR0_DQ[42]
BC5
DDR0_DQ[27]/DDR0_DQ[43]
BD5
DDR0_DQ[28]/DDR0_DQ[44]
BD4
DDR0_DQ[29]/DDR0_DQ[45]
BC1
DDR0_DQ[30]/DDR0_DQ[46]
BC2
DDR0_DQ[31]/DDR0_DQ[47]
AB1
DDR0_DQ[32]/DDR1_DQ[0]
AB2
DDR0_DQ[33]/DDR1_DQ[1]
AA4
DDR0_DQ[34]/DDR1_DQ[2]
AA5
DDR0_DQ[35]/DDR1_DQ[3]
AB5
DDR0_DQ[36]/DDR1_DQ[4]
AB4
DDR0_DQ[37]/DDR1_DQ[5]
AA2
DDR0_DQ[38]/DDR1_DQ[6]
AA1
DDR0_DQ[39]/DDR1_DQ[7]
V5
DDR0_DQ[40]/DDR1_DQ[8]
V2
DDR0_DQ[41]/DDR1_DQ[9]
U1
DDR0_DQ[42]/DDR1_DQ[10]
U2
DDR0_DQ[43]/DDR1_DQ[11]
V1
DDR0_DQ[44]/DDR1_DQ[12]
V4
DDR0_DQ[45]/DDR1_DQ[13]
U5
DDR0_DQ[46]/DDR1_DQ[14]
U4
DDR0_DQ[47]/DDR1_DQ[15]
R2
DDR0_DQ[48]/DDR1_DQ[32]
P5
DDR0_DQ[49]/DDR1_DQ[33]
R4
DDR0_DQ[50]/DDR1_DQ[34]
P4
DDR0_DQ[51]/DDR1_DQ[35]
R5
DDR0_DQ[52]/DDR1_DQ[36]
P2
DDR0_DQ[53]/DDR1_DQ[37]
R1
DDR0_DQ[54]/DDR1_DQ[38]
P1
DDR0_DQ[55]/DDR1_DQ[39]
M4
DDR0_DQ[56]/DDR1_DQ[40]
M1
DDR0_DQ[57]/DDR1_DQ[41]
L4
DDR0_DQ[58]/DDR1_DQ[42]
L2
DDR0_DQ[59]/DDR1_DQ[43]
M5
DDR0_DQ[60]/DDR1_DQ[44]
M2
DDR0_DQ[61]/DDR1_DQ[45]
L5
DDR0_DQ[62]/DDR1_DQ[46]
L1
DDR0_DQ[63]/DDR1_DQ[47]
BA2
DDR0_ECC[0]
BA1
DDR0_ECC[1]
AY4
DDR0_ECC[2]
AY5
DDR0_ECC[3]
BA5
DDR0_ECC[4]
BA4
DDR0_ECC[5]
AY1
DDR0_ECC[6]
AY2
DDR0_ECC[7]
DDR CHANNEL A
RSVD_V10 must be grounde d
SKL_H_BGA_BGA
SKYLAKE_HALO
BGA1440
DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]
DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]
DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0]
DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]
DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]
DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]
DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]
DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1]
DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]
DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5]
DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6]
DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]
DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8]
DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9]
DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]
DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]
DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12]
DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]
DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]
DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT#
DDR0_DQSN[2]/DDR0_DQSN[4]
DDR0_DQSN[3]/DDR0_DQSN[5]
DDR0_DQSN[4]/DDR1_DQSN[0]
DDR0_DQSN[5]/DDR1_DQSN[1]
DDR0_DQSN[6]/DDR1_DQSN[4]
DDR0_DQSN[7]/DDR1_DQSN[5]
DDR0_DQSP[2]/DDR0_DQSP[4]
DDR0_DQSP[3]/DDR0_DQSP[5]
DDR0_DQSP[4]/DDR1_DQSP[0]
DDR0_DQSP[5]/DDR1_DQSP[1]
DDR0_DQSP[6]/DDR1_DQSP[4]
DDR0_DQSP[7]/DDR1_DQSP[5]
1 OF 14
DDR0_CKP[0]
DDR0_CKN[0]
DDR0_CKP[1]
DDR0_CKN[1]
DDR0_CLKP[2]
DDR0_CLKN[2]
DDR0_CLKP[3]
DDR0_CLKN[3]
DDR0_CKE[0]
DDR0_CKE[1]
DDR0_CKE[2]
DDR0_CKE[3]
DDR0_CS#[0]
DDR0_CS#[1]
DDR0_CS#[2]
DDR0_CS#[3]
DDR0_ODT[0]
DDR0_ODT[1]
DDR0_ODT[2]
DDR0_ODT[3]
DDR0_MA[3]
DDR0_MA[4]
DDR0_PAR
DDR0_ALERT#
DDR0_DQSN[0]
DDR0_DQSN[1]
DDR0_DQSP[0]
DDR0_DQSP[1]
DDR0_DQSP[8]
DDR0_DQSN[8]
AG1
AG2
AK2
AK1
AL3
AK3
AL2
AL1
AT1
AT2
AT3
AT5
AD5
AE2
AD2
AE5
AD3
AE4
AE1
AD4
AH5
M_A_BA#0
AH1
M_A_BA#1
AU1
M_A_BG#0
AH4
AG4
AD1
AH3
M_A_A0
AP4
M_A_A1
AN4
M_A_A2
AP5
M_A_A3
AP2
M_A_A4
AP1
M_A_A5
AP3
M_A_A6
AN1
M_A_A7
AN3
M_A_A8
AT4
M_A_A9
AH2
M_A_A10
AN2
M_A_A11
AU4
M_A_A12
AE3
M_A_A13
AU2
M_A_BG#1
AU3
M_A_ACT# M_B_PARITY
AG3
M_A_PARITY
AU5
M_A_ALERT#
BR5
M_A_DQSN0
BL3
M_A_DQSN1
BG3
M_A_DQSN2
BD3
M_A_DQSN3
AA3
M_A_DQSN4
U3
M_A_DQSN5
P3
M_A_DQSN6
L3
M_A_DQSN7
BP5
M_A_DQSP0
BK3
M_A_DQSP1
BF3
M_A_DQSP2
BC3
M_A_DQSP3
AB3
M_A_DQSP4
V3
M_A_DQSP5
R3
M_A_DQSP6
M3
M_A_DQSP7
AY3
BA3
M_B_DQ[63:0] 18
M_A_CLKP0 17
M_A_CLKN0 17
M_A_CLKP1 17
M_A_CLKN1 17
M_A_CKE0 17
M_A_CKE1 17
M_A_CS#0 17
M_A_CS#1 17
M_A_ODT0_CPU 17
M_A_ODT1_CPU 17
M_A_BA#0 17
M_A_BA#1 17
M_A_BG#0 17
M_A_RAS# 17
M_A_WE# 17
M_A_CAS# 17
M_A_A[13:0] 17
M_A_BG#1 17
M_A_ACT# 17 M_B_PARITY 18
M_A_PARITY 17
M_A_ALERT# 17
M_A_DQSN[7:0] 17
M_A_DQSP[7:0] 17
R195 121/F_4
R193 75/F_4
R192 100/F_4
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
SM_RCOMP_0
SM_RCOMP_1
SM_RCOMP_2
U41B
BT11
DDR1_DQ[0]/DDR0_DQ[16]
BR11
DDR1_DQ[1]/DDR0_DQ[17]
BT8
DDR1_DQ[2]/DDR0_DQ[18]
BR8
DDR1_DQ[3]/DDR0_DQ[19]
BP11
DDR1_DQ[4]/DDR0_DQ[20]
BN11
DDR1_DQ[5]/DDR0_DQ[21]
BP8
DDR1_DQ[6]/DDR0_DQ[22]
BN8
DDR1_DQ[7]/DDR0_DQ[23]
BL12
DDR1_DQ[8]/DDR0_DQ[24]
BL11
DDR1_DQ[9]/DDR0_DQ[25]
BL8
DDR1_DQ[10]/DDR0_DQ[26]
BJ8
DDR1_DQ[11]/DDR0_DQ[27]
BJ11
DDR1_DQ[12]/DDR0_DQ[28]
BJ10
DDR1_DQ[13]/DDR0_DQ[29]
BL7
DDR1_DQ[14]/DDR0_DQ[30]
BJ7
DDR1_DQ[15]/DDR0_DQ[31]
BG11
DDR1_DQ[16]/DDR0_DQ[48]
BG10
DDR1_DQ[17]/DDR0_DQ[49]
BG8
DDR1_DQ[18]/DDR0_DQ[50]
BF8
DDR1_DQ[19]/DDR0_DQ[51]
BF11
DDR1_DQ[20]/DDR0_DQ[52]
BF10
DDR1_DQ[21]/DDR0_DQ[53]
BG7
DDR1_DQ[22]/DDR0_DQ[54]
BF7
DDR1_DQ[23]/DDR0_DQ[55]
BB11
DDR1_DQ[24]/DDR0_DQ[56]
BC11
DDR1_DQ[25]/DDR0_DQ[57]
BB8
DDR1_DQ[26]/DDR0_DQ[58]
BC8
DDR1_DQ[27]/DDR0_DQ[59]
BC10
DDR1_DQ[28]/DDR0_DQ[60]
BB10
DDR1_DQ[29]/DDR0_DQ[61]
BC7
DDR1_DQ[30]/DDR0_DQ[62]
BB7
DDR1_DQ[31]/DDR0_DQ[63]
AA11
DDR1_DQ[32]/DDR1_DQ[16]
AA10
DDR1_DQ[33]/DDR1_DQ[17]
AC11
DDR1_DQ[34]/DDR1_DQ[18]
AC10
DDR1_DQ[35]/DDR1_DQ[19]
AA7
DDR1_DQ[36]/DDR1_DQ[20]
AA8
DDR1_DQ[37]/DDR1_DQ[21]
AC8
DDR1_DQ[38]/DDR1_DQ[22]
AC7
DDR1_DQ[39]/DDR1_DQ[23]
W8
DDR1_DQ[40]/DDR1_DQ[24]
W7
DDR1_DQ[41]/DDR1_DQ[25]
V10
DDR1_DQ[42]/DDR1_DQ[26]
V11
DDR1_DQ[43]/DDR1_DQ[27]
W11
DDR1_DQ[44]/DDR1_DQ[28]
W10
DDR1_DQ[45]/DDR1_DQ[29]
V7
DDR1_DQ[46]/DDR1_DQ[30]
V8
DDR1_DQ[47]/DDR1_DQ[31]
R11
DDR1_DQ[48]
P11
DDR1_DQ[49]
P7
DDR1_DQ[50]
R8
DDR1_DQ[51]
R10
DDR1_DQ[52]
P10
DDR1_DQ[53]
R7
DDR1_DQ[54]
P8
DDR1_DQ[55]
L11
DDR1_DQ[56]
M11
DDR1_DQ[57]
L7
DDR1_DQ[58]
M8
DDR1_DQ[59]
L10
DDR1_DQ[60]
M10
DDR1_DQ[61]
M7
DDR1_DQ[62]
L8
DDR1_DQ[63]
AW11
DDR1_ECC[0]
AY11
DDR1_ECC[1]
AY8
DDR1_ECC[2]
AW8
DDR1_ECC[3]
AY10
DDR1_ECC[4]
AW10
DDR1_ECC[5]
AY7
DDR1_ECC[6]
AW7
DDR1_ECC[7]
G1
DDR_RCOMP[0]
H1
DDR_RCOMP[1]
J2
DDR_RCOMP[2]
SKL_H_BGA_BGA
DDR CHANNEL B
SKYLAKE_HALO
BGA1440
DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]
DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]
DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]
DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]
DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1]
DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0]
DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]
DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1]
DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]
DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5]
DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6]
DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]
DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8]
DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9]
DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]
DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]
DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12]
DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]
DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]
DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT#
DDR1_DQSN[0]/DDR0_DQSN[2]
DDR1_DQSN[1]/DDR0_DQSN[3]
DDR1_DQSN[2]/DDR0_DQSN[6]
DDR1_DQSN[3]/DDR0_DQSN[7]
DDR1_DQSN[4]/DDR1_DQSN[2]
DDR1_DQSN[5]/DDR1_DQSN[3]
DDR1_DQSP[0]/DDR0_DQSP[2]
DDR1_DQSP[1]/DDR0_DQSP[3]
DDR1_DQSP[2]/DDR0_DQSP[6]
DDR1_DQSP[3]/DDR0_DQSP[7]
DDR1_DQSP[4]/DDR1_DQSP[2]
DDR1_DQSP[5]/DDR1_DQSP[3]
2 OF 14
DDR1_CKP[0]
DDR1_CKN[0]
DDR1_CKN[1]
DDR1_CKP[1]
DDR1_CLKP[2]
DDR1_CLKN[2]
DDR1_CLKP[3]
DDR1_CLKN[3]
DDR1_CKE[0]
DDR1_CKE[1]
DDR1_CKE[2]
DDR1_CKE[3]
DDR1_CS#[0]
DDR1_CS#[1]
DDR1_CS#[2]
DDR1_CS#[3]
DDR1_ODT[0]
DDR1_ODT[1]
DDR1_ODT[2]
DDR1_ODT[3]
DDR1_MA[3]
DDR1_MA[4]
DDR1_PAR
DDR1_ALERT#
DDR1_DQSN[6]
DDR1_DQSN[7]
DDR1_DQSP[6]
DDR1_DQSP[7]
DDR1_DQSP[8]
DDR1_DQSN[8]
DDR_VREF_CA
DDR0_VREF_DQ
DDR1_VREF_DQ
AM9
AN9
AM8
AM7
AM11
AM10
AJ10
AJ11
AT8
AT10
AT7
AT11
AF11
AE7
AF10
AE10
AF7
AE8
AE9
AE11
AH10
AH11
AF8
AH8
AH9
AR9
AJ9
AK6
AK5
AL5
AL6
AM6
AN7
AN10
AN8
AR11
AH7
AN11
AR10
AF9
AR7
AT9
AJ7
AR8
BP9
BL9
BG9
BC9
AC9
W9
R9
M9
BR9
BJ9
BF9
BB9
AA9
V9
P9
L9
AW9
AY9
BN13
BP13
BR13
M_B_BA#0
M_B_BA#1
M_B_BG#0
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_BG#1
M_B_ACT#
M_B_ALERT#
M_B_DQSN0
M_B_DQSN1
M_B_DQSN2
M_B_DQSN3
M_B_DQSN4
M_B_DQSN5
M_B_DQSN6
M_B_DQSN7
M_B_DQSP0
M_B_DQSP1
M_B_DQSP2
M_B_DQSP3
M_B_DQSP4
M_B_DQSP5
M_B_DQSP6
M_B_DQSP7
SM_VREF
SMDDR_VREF_DQ0_M3
SMDDR_VREF_DQ1_M3
R146 *1K_4
R154 *1K_4
M_B_CLKP0 18
M_B_CLKN0 18
M_B_CLKN1 18
M_B_CLKP1 18
M_B_CKE0 18
M_B_CKE1 18
M_B_CS#0 18
M_B_CS#1 18
M_B_ODT0_CPU 18
M_B_ODT1_CPU 18
M_B_RAS# 18
M_B_WE# 18
M_B_CAS# 18
M_B_BA#0 18
M_B_BA#1 18
M_B_BG#0 18
M_B_A[13:0] 18
M_B_BG#1 18
M_B_ACT# 18
M_B_ALERT# 18
M_B_DQSN[7:0] 18
M_B_DQSP[7:0] 18
04
SM_VREF 17
TP74
SMDDR_VREF_DQ1_M3 18
A A
PROJECT :ZRY
PROJECT :ZRY
PROJECT :ZRY
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
5
4
3
2
SNB 2/5 (DDR3 I/F)
SNB 2/5 (DDR3 I/F)
SNB 2/5 (DDR3 I/F)
Date: Sheet of
Date: Sheet of
Date: Sheet of
1
1A
1A
1A
44 9 Tuesday, August 25, 2015
44 9 Tuesday, August 25, 2015
44 9 Tuesday, August 25, 2015
5
4
3
2
1
SKYLAKE Processor (POWER)
+1.5V 14,30,32,34,45
Follow SKL H EDS page 133 to 45W(GT4+OPC): +VCCGT=104A/12A (GTx)
Follow SKL H EDS page 133 to 45W(GT2): +VCCGT=55A
Follow SKL H DG page 574 to place Cap
D D
+
C C
B B
22uF x 14, 10uF x 35, 1uF x 68
C310
C200
22U/6.3V_6
22U/6.3V_6
PC197
330u/2V_7343
C753
C752
22U/6.3V_6
22U/6.3V_6
C763
C762
22U/6.3V_6
22U/6.3V_6
C765
C194
10U/6.3V_6
10U/6.3V_6
C326
C209
10U/6.3V_6
10U/6.3V_6
C328
C327
10U/6.3V_6
10U/6.3V_6
C361
C218
1U/6.3V_4
1U/6.3V_4
C383
C289
1U/6.3V_4
1U/6.3V_4
C251
C202
1U/6.3V_4
1U/6.3V_4
C191
22U/6.3V_6
C750
22U/6.3V_6
C224
22U/6.3V_6
C221
10U/6.3V_6
C207
10U/6.3V_6
C764
10U/6.3V_6
C227
1U/6.3V_4
C193
1U/6.3V_4
C791
1U/6.3V_4
C329
22U/6.3V_6
C775
22U/6.3V_6
C355
22U/6.3V_6
C213
10U/6.3V_6
C342
10U/6.3V_6
C188
10U/6.3V_6
C364
1U/6.3V_4
C394
1U/6.3V_4
C252
1U/6.3V_4
C307
22U/6.3V_6
C751
22U/6.3V_6
C352
22U/6.3V_6
C776
10U/6.3V_6
C339
10U/6.3V_6
C774
10U/6.3V_6
C216
1U/6.3V_4
C363
1U/6.3V_4
C351
1U/6.3V_4
C195
22U/6.3V_6
C308
22U/6.3V_6
C353
22U/6.3V_6
C773
10U/6.3V_6
C340
10U/6.3V_6
C760
10U/6.3V_6
C741
47U/6.3VS_8
C317
1U/6.3VS_4
C381
1U/6.3VS_4
C782
1U/6.3VS_4
+VCCGT 7,42,44
47U/6.3VS_8
C749
22U/6.3V_6
C309
22U/6.3V_6
C354
22U/6.3V_6
C225
10U/6.3V_6
C341
10U/6.3V_6
C772
10U/6.3V_6
C742
C229
1U/6.3V_4
C783
1U/6.3V_4
C279
1U/6.3V_4
+VCCGT
AJ29
AJ30
AJ31
AJ32
AJ33
AJ34
AJ35
AJ36
AK31
AK32
AK33
AK34
AK35
AK36
AK37
AK38
AL13
AL29
AL30
AL31
AL32
AL35
AL36
AL37
AL38
AM13
AM14
AM29
AM30
AM31
AM32
AM33
AM34
AM35
AM36
AN13
AN14
AN31
AN32
AN33
AN34
AN35
AN36
AN37
AN38
AP13
AP14
AP29
AP30
AP31
AP32
AP35
AP36
AP37
AP38
AR29
AR30
AR31
AR32
AR33
AR34
AR35
AR36
AT14
AT31
AT32
AT33
AT34
AT35
AT36
AT37
AT38
AU14
AU29
AU30
AU31
AU32
AU35
AU36
AU37
AU38
U41N
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
SKL_H_BGA_BGA
SKYLAKE_HALO
BGA1440
14 OF 14
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGT_SENSE
VSSGTX_SENSE
VSSGT_SENSE
VCCGTX_SENSE
AF29
AF30
AF31
AF32
AF33
AF34
AG13
AG14
AG31
AG32
AG33
AG34
AG35
AG36
AH13
AH14
AH29
AH30
AH31
AH32
AJ13
AJ14
AH38
AH35
AH37
AH36
R550
*100/F_4
R549
*100/F_4
4+4e, Support eDRAM Only, GTX 12A
Need caps. ..
+VCCGT
VCCGT_SENSE 42
TP86
VCCGTSS_SENSE 42
TP85
+VCCGT
C785
1U/6.3V_4
C332
1U/6.3V_4
C274
1U/6.3V_4
C793
1U/6.3V_4
C226
1U/6.3V_4
C362
1U/6.3V_4
C287
1U/6.3V_4
C292
1U/6.3V_4
C228
1U/6.3V_4
C276
1U/6.3V_4
C399
1U/6.3V_4
C794
1U/6.3V_4
C385
1U/6.3V_4
C346
1U/6.3V_4
C266
1U/6.3V_4
C395
1U/6.3V_4
C203
1U/6.3V_4
C360
1U/6.3V_4
+3VPCU
+1.2VSUS 2,6,10,17,18,41
IO Thrm Protect
R215
*16.5K/F_4
THRM_MOINTOR
C468
*0.1U/16V_4
1 2
C275
1U/6.3V_4
C784
1U/6.3V_4
C277
1U/6.3V_4
C250
1U/6.3V_4
C215
1U/6.3V_4
C792
1U/6.3V_4
1 2
R231
*3.3K/F_4
For 75 degree, 1.2 v limit, (HW)
R241
*100K_4 NTC
C325
1U/6.3VS_4
C254
1U/6.3VS_4
C217
1U/6.3VS_4
C396
1U/6.3VS_4
C278
1U/6.3VS_4
C397
1U/6.3VS_4
05
C453
*0.1U/16V_4
THRM_MOINTOR1 37
C288
C290
1U/6.3VS_4
1U/6.3V_4
C253
C291
1U/6.3VS_4
1U/6.3V_4
C249
C192
1U/6.3V_4
1U/6.3VS_4
C204
C384
1U/6.3VS_4
1U/6.3V_4
C365
C380
1U/6.3V_4
1U/6.3VS_4
C398
C382
1U/6.3V_4
1U/6.3VS_4
Local CPU Thermal Sensor
U40
2
Q38
8
SCLK
7
SDA
6
ALERT#
4
OVERT#
*TMP431ADGKR
CPU_THRMTRIP#
VCC
DXP
DXN
GND
VCC Output Decoupli ng Recommendations
A A
SMB_RUN_CLK 10, 16,17,18,35
SMB_RUN_DAT 10,16,17,18,35
CPU_THRMTRIP#
R555 10K/F_4
+3V
+1.0V
PM_THRMTRIP# 2,11,17,18
R562 *4.7K_4
1 3
*METR3904-G
5
4
3
2
C806 0.01U/50V _4
1
2
CPU_THERMDA
3
5
C809
2200P/50V_4
CPU_THERMDC
AL000431014 TMP431ADGKR(98h)
+3V
CPU Thermal Sensor
Q39
2
*METR3904-G
1 3
PROJECT :ZRY
PROJECT :ZRY
PROJECT :ZRY
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
SNB 3/5 (POWER)
SNB 3/5 (POWER)
SNB 3/5 (POWER)
Date: Sheet of
Date: Sheet of
Date: Sheet of
1
54 9 Monday, S eptember 07, 2015
54 9 Monday, S eptember 07, 2015
54 9 Monday, S eptember 07, 2015
1A
1A
1A
5
4
3
2
1
06
Follow SKL H EDS page 135 to 45W(GT2): VCCSA=11.1A (GTx)
D D
+VCCSA 42,44
C190
22U/6.3V_6
C787
10U/6.3V_6
C C
C205
10U/6.3V_6
C357
22u/6.3V_6
C788
22U/6.3V_6
C786
10U/6.3V_6
C766
1U/6.3V_4
C350
22u/6.3V_6
C373
1U/6.3V_4
C219
22U/6.3VS_6
C778
10U/6.3V_6
C208
1U/6.3V_4
C318
22U/6.3VS_6
C393
1U/6.3V_4
+VCCIO
Follow SKL H EDS P136 to 45W: VCCIO
+VCCIO = 0.95V
B B
+VDDQC +VCCSTG +VCCPLL_OC
C386
C273
10U/6.3V_6
+VCCIO
A A
C356
*1U/6.3V_ 4
C401
1U/6.3V_4
C359
*22U/6.3V _6
1U/6.3V_4
C789
22U/6.3VS_6
C181
10U/6.3V_6
C296
1U/6.3V_4
C331
22U/6.3VS_6
C344
10U/6.3V_6
C400
+VCCSA
K29
K30
K31
K32
K33
K34
K35
M29
M30
M31
M32
M33
M34
M35
M36
AG12
G15
G17
G19
G21
J30
L31
L32
L35
L36
L37
L38
H15
H16
H17
H19
H20
H21
H26
H27
J15
J16
J17
J19
J20
J21
J26
J27
SKYLAKE_HALO
U41I
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
1U/6.3V_4
BGA1440
11.1 A 2.8 A
5.5 A
SKL_H_BGA_BGA
C298
Close CPU Under CPU
0.26 A
9 OF 14
C297
1U/6.3V_4
0.12 A
0.145 A
VCCSA_SENSE
VSSSA_SENSE
VCCIO_SENSE
VSSIO_SENSE
+VCCPLL +VCCIO
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQC
VCCPLL_OC
VCCPLL_OC
VCCST
VCCSTG
VCCSTG
VCCPLL
VCCPLL
Follow SKL H EDS page 135 45W: VDDQ=2.8A
+1.2VSUS
AA6
AE12
AF5
AF6
AG5
AG9
AJ12
AL11
AP6
AP7
AR12
AR6
AT12
AW6
AY6
J5
J6
K12
K6
L12
L6
R6
T6
W6
Y12
BH13
G11
H30
H29
G30
H28
J28
M38
M37
H14
J14
+1.2VSUS 2,10,17,18,41
R151 *SH ORT_6
R156 *SH ORT_6
R115 *SHORT_ 6
R118 *0_ 6
R123 *SH ORT_6
C260
1U/6.3V_4
+1.2VSUS +VDDQC
C452
22U/6.3VS_6
C449
10U/6.3V_6
C451
10U/6.3V_6
+VCCIO
+VCCSTPLL
+1.0V
C421
22U/6.3VS_6
C460
10U/6.3V_6
C450
10U/6.3V_6
+VDDQC
+VCCPLL_OC
+VCCSTG
+VCCPLL
R551 *100/F_4
R546 *100/F_4
VCCIO_VCCSENSE
VSSIO_VSSSENSE
+VCCPLL_OC +1.2VSUS
+VCCSTG
+VCCPLL +VCCSTPLL
C447
22U/6.3VS_6
C459
10U/6.3V_6
C440
10U/6.3V_6
+VCCSTPLL
100 ohm near CPU
+VCCSA
VSA_SENSE 42
VSASS_SENSE 42
R144 *SHORT_4
R142 *SHORT_4
C444
22U/6.3VS_6
C422
10U/6.3V_6
C434
10U/6.3V_6
R145
100_4
R143
100_4
+
C502
*330U/2V _7343
C432
10U/6.3V_6
C416
10U/6.3V_6
+1.0V 2,5,10,16,40,45
+VCCSTPLL 2,10,40,42
5
4
3
EDRAM Only, PLACE CAPS IN ACK SIDE
BJ17
BJ19
BJ20
BK17
BK19
BK20
BL16
BL17
BL18
BL19
BL20
BL21
BM17
BN17
BJ23
BJ26
BJ27
BK23
BK26
BK27
BL23
BL24
BL25
BL26
BL27
BL28
BM24
BL15
BM16
BL22
BM22
BP15
BR15
BT15
BP16
BR16
BT16
BN15
BM15
BP17
BN16
TP91
TP24
TP29
TP28
TP30
TP27
CPU_OPC_COMP
R576 *49.9/F_4
CPU_OPCE_COMP
R133 *49.9/F_4
CPU_OPCE_COMP2
R132 *49.9/F_4
2
BM14
BL14
BJ35
BJ36
AT13
AW13
AU13
AY13
BT29
BR25
BP25
PROJECT :ZRY
PROJECT :ZRY
PROJECT :ZRY
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
SNB 4/5 (POWER & GND)
SNB 4/5 (POWER & GND)
SNB 4/5 (POWER & GND)
Date: Sheet of
Date: Sheet of
Date: Sheet of
SKYLAKE_HALO
U41J
BGA1440
VCCOPC
3.8 A
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
VCCOPC_SENSE
VSSOPC_SENSE
RSVD
RSVD
VCCEOPIO
2.8 A
VCCEOPIO
VCCEOPIO
RSVD
RSVD
RSVD
VCCEOPIO_SENSE
VSSEOPIO_SENSE
RSVD
RSVD
VCC_OPC_1P8
VCC_OPC_1P8
RSVD
RSVD
ZVM#
MSM#
ZVM2#
MSM2#
OPC_RCOMP
OPCE_RCOMP
OPCE_RCOMP2
SKL_H_BGA_BGA
0.05 A
10 OF 14
1
1A
1A
1A
64 9 Monday, September 07, 2015
64 9 Monday, September 07, 2015
64 9 Monday, September 07, 2015
5
4
3
2
1
AV29
AV30
AV31
AV32
AV33
AV34
AV35
AV36
AW14
AW31
AW32
AW33
AW34
AW35
AW36
AW37
AW38
AY29
AY30
AY31
AY32
AY35
AY36
AY37
AY38
BA13
BA14
BA29
BA30
BA31
BA32
BA33
BA34
BA35
BA36
BB13
BB14
BB31
BB32
BB33
BB34
BB35
BB36
BB37
BB38
BC29
BC30
BC31
BC32
BC35
BE33
BE34
BE35
BE36
07
+VCCGT
󱋨󱋨󱋨󱋨󲙵󲙵󲙵󲙵 net name
+VCCCORE
U41G
AC13
AC14
AC29
AC30
AC31
AC32
AC33
AC34
AC35
AC36
AD13
AD14
AD31
AD32
AD33
AD34
AD35
AD36
AD37
AD38
AA13
AA31
AA32
AA33
AA34
AA35
AA36
AA37
AA38
AB29
AB30
AB31
AB32
AB35
AB36
AB37
AB38
AE13
AE14
AE30
AE31
AE32
AE35
AE36
AE37
AE38
AF35
AF36
AF37
AF38
K13
K14
L13
N13
N14
N30
N31
N32
N35
N36
N37
N38
P13
SKYLAKE_HALO
BGA1440
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
SKL_H_BGA_BGA
7 OF 14
VCC_SENSE
VSS_SENSE
V32
VCC
V33
VCC
V34
VCC
V35
VCC
V36
VCC
V37
VCC
V38
VCC
W13
VCC
W14
VCC
W29
VCC
W30
VCC
W31
VCC
W32
VCC
W35
VCC
W36
VCC
W37
VCC
W38
VCC
Y29
VCC
Y30
VCC
Y31
VCC
Y32
VCC
Y33
VCC
Y34
VCC
Y35
VCC
Y36
VCC
L14
VCC
P29
VCC
P30
VCC
P31
VCC
P32
VCC
P33
VCC
P34
VCC
P35
VCC
P36
VCC
R13
VCC
R31
VCC
R32
VCC
R33
VCC
R34
VCC
R35
VCC
R36
VCC
R37
VCC
R38
VCC
T29
VCC
T30
VCC
T31
VCC
T32
VCC
T35
VCC
T36
VCC
T37
VCC
T38
VCC
U29
VCC
U30
VCC
U31
VCC
U32
VCC
U33
VCC
U34
VCC
U35
VCC
U36
VCC
V13
VCC
V14
VCC
V31
VCC
P14
VCC
AG37
AG38
D D
C757
C211
22U/6.3V_6
22U/6.3V_6
C C
B B
C185
22U/6.3V_6
C348
10U/6.3V_6
C183
1U/6.3V_4
C343
1U/6.3V_4
C770
22U/6.3V_6
C337
10U/6.3V_6
C189
1U/6.3V_4
C769
1U/6.3V_4
Follow SKL H EDS page 131 to 45W(GT2): VCC_CORE=68A
C323
22U/6.3V_6
C186
22U/6.3V_6
C324
22U/6.3V_6
C347
22U/6.3V_6
C758
10U/6.3V_6
C743
1U/6.3V_4
C201
1U/6.3V_4
C748
22U/6.3V_6
C197
22U/6.3V_6
C759
22U/6.3V_6
C777
22U/6.3V_6
C761
10U/6.3V_6
C199
1U/6.3V_4
C790
1U/6.3V_4
C322
22U/6.3V_6
C184
22U/6.3V_6
C223
22U/6.3V_6
C747
22U/6.3V_6
C312
10U/6.3V_6
C767
10U/6.3V_6
C179
1U/6.3V_4
C781
1U/6.3V_4
C313
22U/6.3V_6
C176
22U/6.3V_6
C212
22U/6.3V_6
C336
22U/6.3V_6
C210
10U/6.3V_6
C349
10U/6.3V_6
C780
1U/6.3V_4
C330
1U/6.3V_4
C744
22U/6.3V_6
C198
22U/6.3V_6
C314
22U/6.3V_6
C222
22U/6.3V_6
C771
10U/6.3V_6
C338
10U/6.3V_6
C315
1U/6.3VS_4
C321
1U/6.3VS_4
C178
47U/6.3VS_8
C196
22U/6.3V_6
C746
22U/6.3V_6
C220
22U/6.3V_6
C756
22U/6.3V_6
C768
10U/6.3V_6
C754
10U/6.3V_6
C174
1U/6.3V_4
C779
1U/6.3V_4
C177
47U/6.3VS_8
+VCCCORE 42,43
Follow SKL H DG page 573 to place Cap
22uF x 12, 10uF x 28, 1uF x 63
C388
C369
0.1U/10V_4
0.1U/10V_4
1 2
1 2
C282
C281
0.1U/10V_4
C180
0.1U/10V_4
C244
0.1U/10V_4
C245
0.1U/10V_4
0.1U/10V_4
1 2
C739
0.1U/10V_4
1 2
C376
0.1U/10V_4
1 2
C391
0.1U/10V_4
1 2
R548 *100_4
VCORE_SENSE 42
VCORESS_SENSE 42
R547 *100_4
1 2
1 2
1 2
1 2
C387
0.1U/10V_4
1 2
C371
0.1U/10V_4
1 2
C283
0.1U/10V_4
1 2
C379
0.1U/10V_4
1 2
C248
0.1U/10V_4
1 2
C247
C270
0.1U/10V_4
0.1U/10V_4
1 2
1 2
C284
C182
0.1U/10V_4
1 2
1 2
1 2
1 2
+VCCCORE
0.1U/10V_4
1 2
C745
C370
0.1U/10V_4
0.1U/10V_4
1 2
C740
C269
0.1U/10V_4
0.1U/10V_4
1 2
C392
C390
0.1U/10V_4
0.1U/10V_4
1 2
Sense resistor should be placed within 2
inches (50.8 mm) o f the processor soc ket
Trace Impendence 50 ohm
C378
0.1U/10V_4
1 2
C267
0.1U/10V_4
1 2
C375
0.1U/10V_4
1 2
C795
0.1U/10V_4
1 2
C206
0.1U/10V_4
1 2
C271
0.1U/10V_4
1 2
C377
0.1U/10V_4
1 2
C286
0.1U/10V_4
1 2
C175
0.1U/16V_4
1 2
C367
0.1U/10V_4
1 2
C374
0.1U/10V_4
1 2
C366
0.1U/10V_4
1 2
C214
0.1U/10V_4
1 2
C268
0.1U/10V_4
1 2
C368
0.1U/10V_4
1 2
C389
0.1U/10V_4
1 2
C272
0.1U/10V_4
1 2
C246
0.1U/10V_4
1 2
C187
0.1U/10V_4
1 2
C285
0.1U/10V_4
1 2
+VCCGT +VCCCORE
+VCCGT 5,42,44
U41H
SKYLAKE_HALO
BJ37
BJ38
BL36
BL37
BT37
BC36
BC37
BC38
BD13
BD14
BD29
BD30
BD31
BD32
BD33
BD34
BD35
BD36
BE31
BE32
BGA1440
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
SKL_H_BGA_BGA
8 OF 14
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
BG34
BG35
BG36
BH33
BH34
BH35
BH36
BH37
BH38
BM36
BM37
BN36
BN37
BN38
BP37
BP38
BR37
BE38
BF13
BF14
BF29
BF30
BF31
BF32
BF35
BF36
BF37
BF38
BG29
BG30
BG31
BG32
BG33
BE37
Change R2053 to NI_20141203
VCORE_SENSE VCORESS_SENSE
A A
5
4
R552 *49.9/F_4
PROJECT :ZRY
PROJECT :ZRY
PROJECT :ZRY
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
SNB 4/5 (POWER & GND)
SNB 4/5 (POWER & GND)
SNB 4/5 (POWER & GND)
Date: Sheet of
Date: Sheet of
3
2
Date: Sheet of
1
1A
1A
1A
74 9 Tuesday, Augu st 25, 2015
74 9 Tuesday, Augu st 25, 2015
74 9 Tuesday, Augu st 25, 2015
5
4
3
2
1
Haswell Processor (GND)
BA38
BA37
BA12
BA11
BA10
AY34
AY33
AY14
AY12
AW30
AW29
AW12
AW5
AW4
AW3
AW2
AW1
AV38
AV37
AU34
AU33
AU12
AU11
AU10
AT30
AT29
AR38
AR37
AR14
AR13
AP34
AP33
AP12
AP11
AP10
AN30
AN29
AN12
AM38
AM37
AM12
AM5
AM4
AM3
AM2
AM1
AL34
AL33
AL14
AL12
AL10
BB4
BB3
BB2
BB1
BA9
BA8
BA7
BA6
AU9
AU8
AU7
AU6
AT6
AR5
AR4
AR3
AR2
AR1
AP9
AP8
AN6
AN5
AL9
AL8
AL7
AL4
B9
U41M
SKYLAKE_HALO
BGA1440
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SKL_H_BGA_BGA
13 OF 14
AK30
VSS
AK29
VSS
AK4
VSS
AJ38
VSS
AJ37
VSS
AJ6
VSS
AJ5
VSS
AJ4
VSS
AJ3
VSS
AJ2
VSS
AJ1
VSS
AH34
VSS
AH33
VSS
AH12
VSS
AH6
VSS
AG30
VSS
AG29
VSS
AG11
VSS
AG10
VSS
AG8
VSS
AG7
VSS
AG6
VSS
AF14
VSS
AF13
VSS
AF12
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NCTFVSS
NCTFVSS
NCTFVSS
NCTFVSS
NCTFVSS
AF4
AF3
AF2
AF1
AE34
AE33
AE6
AD30
AD29
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AC38
AC37
AC12
AC6
AC5
AC4
AC3
AC2
AC1
AB34
AB33
AB6
AA30
AA29
AA12
A30
A28
A26
A24
A22
A20
A18
A16
A14
A12
A10
A9
A6
B37
B3
A34
A4
A3
PCH_2_CPU_TRIG 15
CFG[3] (PHYSICAL_DEBUG_E NABLED (DFX PRIVACY ))
0 Enable; SET DFX ENABLED BIT IN DEBUG
1 , Disable;
CFG3 2,16
CFG2 2,16
CFG4 2,16
CFG5 2,16
CFG6 2,16
CFG10 2,16
CFG12 2,16
CFG13 2,16
3
CFG3
CFG2
CFG4
CFG5
CFG6
CFG10
CFG12
CFG13
U41F
SKYLAKE_HALO
BGA1440
Y38
VSS
Y37
VSS
Y14
VSS
Y13
VSS
Y11
VSS
Y10
VSS
Y9
D D
C C
B B
W34
W33
W12
V30
V29
V12
U38
U37
T34
T33
T14
T13
T12
T11
T10
R30
R29
R12
P38
P37
P12
N34
N33
N12
N11
N10
M14
M13
M12
L34
L33
L30
L29
K38
K11
K10
Y8
Y7
W5
W4
W3
W2
W1
V6
U6
T9
T8
T7
T5
T4
T3
T2
T1
P6
N9
N8
N7
N6
N5
N4
N3
N2
N1
M6
K9
K8
K7
K5
K4
K3
K2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SKL_H_BGA_BGA
6 OF 14
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NCTFVSS
K1
J36
J33
J32
J25
J22
J18
J10
J7
J4
H35
H32
H25
H22
H18
H12
H11
G28
G26
G24
G23
G22
G20
G18
G16
G14
G12
G10
G9
G8
G6
G5
G4
F36
F31
F29
F27
F25
F23
F21
F19
F17
F15
F13
F11
F9
F8
F5
F4
F3
F2
E38
E35
E34
E9
E4
D33
D30
D28
D26
D24
D22
D20
D18
D16
D14
D12
D10
D9
D6
D3
C37
C31
C29
C27
D38
Processor Strapping
U41L
SKYLAKE_HALO
C17
C13
BT32
BT26
BT24
BT21
BT18
BT14
BT12
BT9
BT5
BR36
BR34
BR29
BR26
BR24
BR21
BR18
BR14
BR12
BR7
BP34
BP33
BP29
BP26
BP24
BP21
BP18
BP14
BP12
BP7
BN34
BN31
BN30
BN29
BN24
BN21
BN20
BN19
BN18
BN14
BN12
BN9
BN7
BN4
BN2
BM38
BM35
BM28
BM27
BM26
BM23
BM21
BM13
BM12
BM9
BM6
BM2
BL29
BK29
BK15
BK14
BJ32
BJ31
BJ25
BJ22
BH14
BH12
BH9
BH8
BH5
BH4
BH1
BG38
BG13
BG12
BF33
BF12
BE29
BE6
BD9
BC34
BC12
BB12
C9
BGA1440
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SKL_H_BGA_BGA
12 OF 14
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NCTFVSS
NCTFVSS
NCTFVSS
NCTFVSS
NCTFVSS
NCTFVSS
C25
C23
C21
C19
C15
C11
C8
C5
BM29
BM25
BM18
BM11
BM8
BM7
BM5
BM3
BL38
BL35
BL13
BL6
BK25
BK22
BK13
BK6
BJ30
BJ29
BJ15
BJ12
BH11
BH10
BH7
BH6
BH3
BH2
BG37
BG14
BG6
BF34
BF6
BE30
BE5
BE4
BE3
BE2
BE1
BD38
BD37
BD12
BD11
BD10
BD8
BD7
BD6
BC33
BC14
BC13
BC6
BB30
BB29
BB6
BB5
C2
BT36
BT35
BT4
BT3
BR38
The CFG signals have a default value of '1' if not terminated on the board.
1 0
A A
CFG2
(PEG Static Lane Reversal)
CFG4
(DP Presence Strap)
CFG7
(PEG Defer Training)
5
Normal Operation Lane Reversed
Disable; No physical DP attached to eDP
PEG train immediately following
xxRESETB de assertion
4
Enable; An ext DP device is connected to eDP
PEG wait for BIOS training
Haswell Processor (RESERVED, CFG)
U41K
BN35
BN33
BL34
AE29
AA14
BR35
BR31
BH30
BR1
BT2
H24
N29
R14
A36
A37
H23
E30
B30
C30
D1
E1
E3
E2
J24
J23
F30
G3
J3
R591 30_4
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
PROC_TRIGIN
PROC_TRIGOUT
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
SKL_H_BGA_BGA
TP95
TP98
TP96
TP97
TP93
CPU_2_PCH_TRIG_R
CPU_2_PCH_TRIG_R CPU_2_PCH_TRIG
CFG[6:5] (PCIE Port Bifurcation Straps)
R124 *1K_4
R128 1K_4
R580 1K_4
R582 *1K_4
R583 *1K_4
R581 *1K_4
R584 *1K_4
R585 *1K_4
11: (Default) x16 - Device 1 functions 1 and 2 disabled
10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled
01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
2
SKYLAKE_HALO
BGA1440
11 OF 14
CPU_2_PCH_TRIG 15
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
08
BM33
RSVD_TP
BL33
RSVD_TP
BJ14
RSVD_TP
BJ13
RSVD_TP
BK28
RSVD
BJ28
RSVD
BJ18
VSS
BJ16
RSVD_TP
BK16
RSVD_TP
BK24
RSVD_TP
BJ24
RSVD_TP
BK21
RSVD
BJ21
RSVD
BT17
RSVD
BR17
RSVD
BK18
VSS
BJ34
RSVD_TP
BJ33
RSVD_TP
G13
RSVD
AJ8
RSVD
BL31
RSVD
B2
NCTF
B38
NCTF
BP1
NCTF
BR2
NCTF
C1
NCTF
C38
NCTF
PROJECT :ZRY
PROJECT :ZRY
PROJECT :ZRY
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
SNB 5/5 (GND)
SNB 5/5 (GND)
SNB 5/5 (GND)
1
TP89
TP90
TP22
TP21
TP14
TP15
TP16
TP13
TP25 TP94
TP92
1A
1A
1A
84 9 Tuesday, September 08, 2015
84 9 Tuesday, September 08, 2015
84 9 Tuesday, September 08, 2015
5
4
3
2
1
U45B
DMI_TXN0 3
DMI_TXP0 3
DMI_RXN0 3
DMI_RXP0 3
DMI_TXN1 3
DMI_TXP1 3
DMI_RXN1 3
DMI_RXP1 3
D D
PCIE_RXN3_WLAN 34
WLAN
LAN
C C
PCIE_RXP3_WLAN 34
PCIE_TXN3_WLAN 34
PCIE_TXP3_WLAN 34
PCIE_RXN4_LAN 31
PCIE_RXP4_LAN 31
PCIE_TXN4_LAN 31
PCIE_TXP4_LAN 31
DMI_TXN2 3
DMI_TXP2 3
DMI_RXN2 3
DMI_RXP2 3
DMI_TXN3 3
DMI_TXP3 3
DMI_RXN3 3
DMI_RXP3 3
R690 100/F_4
C870 0.1U/16V_4
C872 0.1U/16V_4
C871 0.1U/16V_4
PCIECOMP_N
PCIECOMP_P
PCIE_TXN3_WLAN_C
PCIE_TXP3_WLAN_C
PCIE_TXN4_LAN_C
PCIE_TXP4_LAN_C
L27
DMI_RXN0
N27
DMI_RXP0
C27
DMI_TXN0
B27
DMI_TXP0
E24
DMI_RXN1
G24
DMI_RXP1
B28
DMI_TXN1
A28
DMI_TXP1
G27
DMI_RXN2
E26
DMI_RXP2
B29
DMI_TXN2
C29
DMI_TXP2
L29
DMI_RXN3
K29
DMI_RXP3
B30
DMI_TXN3
A30
DMI_TXP3
B18
PCIE_RCOMPN
C17
PCIE_RCOMPP
H15
PCIE1_RXN/USB3_7_RXN
G15
PCIE1_RXP/USB3_7_RXP
A16
PCIE1_TXN/USB3_7_TXN
B16
PCIE1_TXP/USB3_7_TXP
B19
PCIE2_TXN/USB3_8_TXN
C19
PCIE2_TXP/USB3_8_TXP
E17
PCIE2_RXN/USB3_8_RXN
G17
PCIE2_RXP/USB3_8_RXP
L17
PCIE3_RXN/USB3_9_RXN
K17
PCIE3_RXP/USB3_9_RXP
B20
PCIE3_TXN/USB3_9_TXN
C20
PCIE3_TXP/USB3_9_TXP
E20
PCIE4_RXN/USB3_10_RXN
G19
PCIE4_RXP/USB3_10_RXP
B21
PCIE4_TXN/USB3_10_TXN
A21
PCIE4_TXP/USB3_10_TXP
K19
PCIE5_RXN
L19
PCIE5_RXP
D22
PCIE5_TXN
C22
PCIE5_TXP
G22
PCIE6_RXN
E22
PCIE6_RXP
B22
PCIE6_TXN
A23
PCIE6_TXP
L22
PCIE7_RXN
K22
PCIE7_RXP
C23
PCIE7_TXN
B23
PCIE7_TXP
K24
PCIE8_RXN
L24
PCIE8_RXP
C24
PCIE8_TXN
B24
PCIE8_TXP
SPT_PCH_H
SPT-H_PCH
DMI
PCIe/USB 3
USB 2.0
GPP_E9/USB2_OC0#
GPP_E10/USB2_OC1#
GPP_E11/USB2_OC2#
GPP_E12/USB2_OC3#
GPP_F15/USB2_OCB_4
GPP_F16/USB2_OCB_5
GPP_F17/USB2_OCB_6
GPP_F18/USB2_OCB_7
2 OF 12
USB2N_1
USB2P_1
USB2N_2
USB2P_2
USB2N_3
USB2P_3
USB2N_4
USB2P_4
USB2N_5
USB2P_5
USB2N_6
USB2P_6
USB2N_7
USB2P_7
USB2N_8
USB2P_8
USB2N_9
USB2P_9
USB2N_10
USB2P_10
USB2N_11
USB2P_11
USB2N_12
USB2P_12
USB2N_13
USB2P_13
USB2N_14
USB2P_14
USB2_COMP
USB2_VBUSSENSE
RSVD_AB13
USB2_ID
GPD7/RSVD
AF5
AG7
AD5
AD7
AG8
AG10
AE1
AE2
AC2
AC3
AF2
AF3
AB3
AB2
AL8
AL7
AA1
AA2
AJ8
AJ7
W2
W3
AD3
AD2
V2
V1
Change DGPU_PRSNT# to GPU_EVENT#_20141203
AJ11
AJ13
AD43
USB_OC0#
AD42
USB_OC1#
AD39
USB_OC2#
AC44
USB_OC3#
Y43
USB_OC4#
Y41
USB_OC5#
W44
USB_OC6#
W43
USB_OC7#
AG3
USB2_COMP
AD10
AB13
AG2
BD14
USBP0- 36
USBP0+ 36
USBP1- 36
USBP1+ 36
USBP4- 36
USBP4+ 36
USBP6- 34
USBP6+ 34
USBP7- 29
USBP7+ 29
USBP8- 29
USBP8+ 29
USBP9- 36
USBP9+ 36
USB_OC0# 36
USB_OC1# 36
USB_OC2# 36
R641 113/F_4
R485 1K_4
R642 1K_4
MB USB3.0
MB USB3.0
DB USB2.0
BT
Touch Screen
CCD
Card reader
Port1
Port2
Port5
USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#
USB_OC4#
USB_OC5#
USB_OC6#
USB_OC7#
+3V_DEEP_SUS
R761 10K_4 C869 0.1U/16V_4
R760 10K_4
R759 10K_4
R782 10K_4
R758 10K_4
R781 10K_4
R780 10K_4
R757 10K_4
09
+3V
+3V
R250 10K_4
R756 10K_4
1A
1A
1A
94 9 Tuesday, August 25, 2015
94 9 Tuesday, August 25, 2015
94 9 Tuesday, August 25, 2015
USB
SPT-H_PCH
6 OF 12
LPC/eSPI
GPP_A5/LFRAME#/ESPI_CS0#
GPP_A6/SERIRQ/ESPI_CS1#
GPP_A7/PIRQA#/ESPI_ALERT0#
GPP_A0/RCIN#/ESPI_ALERT1#
GPP_A14/SUS_STAT#/ESPI_RESET#
GPP_A9/CLKOUT_LPC0/ESPI_CLK
GPP_A10/CLKOUT_LPC1
SATA
GPP_A1/LAD0/ESPI_IO0
GPP_A2/LAD1/ESPI_IO1
GPP_A3/LAD2/ESPI_IO2
GPP_A4/LAD3/ESPI_IO3
GPP_G19/SMI#
GPP_G18/NMI#
GPP_E6/DEVSLP2
GPP_E5/DEVSLP1
GPP_E4/DEVSLP0
GPP_F9/DEVSLP7
GPP_F8/DEVSLP6
GPP_F7/DEVSLP5
GPP_F6/DEVSLP4
GPP_F5/DEVSLP3
3
B B
USB3_TXN1 36
USB3_TXP1 36
USB3.0 (M/B-2)
USB3.0 (M/B-1)
A A
5
USB3_RXN1 36
USB3_RXP1 36
USB3_TXN0 36
USB3_TXP0 36
USB3_RXN0 36
USB3_RXP0 36
4
U45F
C11
USB3_1_TXN
B11
USB3_1_TXP
B7
USB3_1_RXN
A7
USB3_1_RXP
B12
USB3_2_TXN/SSIC_1_TXN
A12
USB3_2_TXP/SSIC_1_TXP
C8
USB3_2_RXN/SSIC_1_RXN
B8
USB3_2_RXP/SSIC_1_RXP
B15
USB3_6_TXN
C15
USB3_6_TXP
K15
USB3_6_RXN
K13
USB3_6_RXP
B14
USB3_5_TXN
C14
USB3_5_TXP
G13
USB3_5_RXN
H13
USB3_5_RXP
D13
USB3_3_TXP/SSIC_2_TXP
C13
USB3_3_TXN/SSIC_2_TXN
A9
USB3_3_RXP/SSIC_2_RXP
B10
USB3_3_RXN/SSIC_2_RXN
B13
USB3_4_TXP
A14
USB3_4_TXN
G11
USB3_4_RXP
E11
USB3_4_RXN
SPT_PCH_H
Add board ID_2 01 41203
AT22
AV22
AT19
BD16
BE16
BA17
IRQ_SERIRQ
AW17
BOARD_ID8
AT17
BC18
BC17
CLK_PCI_EC_R
AV19
CLK_PCI_LPC_R
M45
N43
AE45
AG43
AG42
AB39
AB36
AB43
AB42
AB41
DEVSLP2
DEVSLP1
DEVSLP0
SIO_EXT_SMI# 12,37
LPC_LAD0 33,34,37
LPC_LAD1 33,34,37
LPC_LAD2 33,34,37
LPC_LAD3 33,34,37
LPC_LFRAME# 33,34,37
TP105
DEVSLP0 33,34
IRQ_SERIRQ 33,37
SIO_RCIN# 37
ESPI_RST# 37
R688 22/F_4
R252 22/F_4
R253 22/F_4
2
EC19 18P/50V_4
EC5 18P/50V_4
EC6
18P/50V_4
CLK_PCI_EC 37
CLK_PCI_LPC 34
EMI(near PCH)
PCLK_TPM 33
EMI(near PCH)
IRQ_SERIRQ
SIO_RCIN#
SIO_EXT_SMI#
DEVSLP0
DEVSLP1
DEVSLP2
+3V_DEEP_SUS 10,12,13,14,16,17
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
R254 10K_4
R784 *10K_4
R763 *10K_4
R762 *10K_4
PROJECT :ZRY
PROJECT :ZRY
PROJECT :ZRY
PCH 1/6 (DMI/FDI/VIDEO)
PCH 1/6 (DMI/FDI/VIDEO)
PCH 1/6 (DMI/FDI/VIDEO)
1
R776 2.2K_4
R750 2.2K_4
R790 2.2K_4
R789 2.2K_4
R779 2.2K_4
R777 2.2K_4
R679 10K_4
R692 *10K_4
R696 *10K_4
C608 *220P/50V_4
C884 *220P/50V_4
R346 4.7K_4
+3V
R355 4.7K_4
+3V
+3VPCU
5
C858 *33P/50V_4
ACZ_BCLK
R670 33_4
ACZ_RST#
R659 33_4
ACZ_SDOUT
R662 33_4
ACZ_SYNC
R666 33_4
R667
*1M_4
SMB_ME0_CLK
SMB_ME0_DAT
SMB_ME1_CLK
SMB_ME1_DAT
SMB_PCH_CLK
SMB_PCH_DAT
PCH_BATLOW#
SUSWARN#
SUSACK#
+3V_S5
Q28
5
2
6
*2N7002DW
2ND_MBCLK
R340 *SHORT_4
2ND_MBDATA
R351 *SHORT_4
Q29
4 3
1
2N7002KDW
1B-1
On SKL voltage at VCCRTC does not exceed 3.2V
R658
*SHORT_4
1 2
BT1
R831
R828
*2.2K_4
*2.2K_4
4 3
SMB_ME1_CLK
1
SMB_ME1_DAT
SMB_ME1_CLK
SMB_ME1_DAT
+3V
5
SMB_PCH_DAT
2
6
SMB_PCH_CLK
+3V_RTC_2
+3V_RTC_1
R671 1K_4
+3V_RTC_[0:2]
Trace width = 20 mils
1 3
VCCRTC_3 VCCRTC_4
Q60
MMBT3904
2
+3V_DEEP_SUS
R664
*4.7K_4
ACZ_SDOUT
AUD_AZACPU_SDO 3
AUD_AZACPU_SDI 3
AUD_AZACPU_SCLK 3
DMIC_DATA0 32
DMIC_CLK0 32
RSMRST# 37 ACPRESENT 37
SMBALERT# 12
SML0ALERT# 12
SMB1ALERT# 12,35
Touch P ad
XDP
DDR3-L
CPU heat pipe loca l thermal sensor
DDR thermal sensor
+3V_RTC
D30
BAT54C
20MIL
R963 4.7K_4
HDA Bus(CLG)
PCH_AZ_CODEC_BITCLK 32
PCH_AZ_CODEC_RST# 32
PCH_AZ_CODEC_SDOUT 32
PCH_AZ_CODEC_SYNC 32
+3V_DEEP_SUS
D D
C C
B B
Add PU _20141212
RSMRST#
EC_PWROK
2ND_MBCLK 22, 37
2ND_MBDATA 22, 37
SMB_RUN_DAT 5,16,17,18,35
SMB_RUN_CLK 5,16,17,18,35
RTC Circuitry (RTC)
ME_WR# 12, 37
PCH_AZ_CODEC_SDIN0 32
SYS_PWROK
R233 *SHORT_4
SMBALERT#
SML0ALERT#
TP49
VGA
EC
+3V_RTC
Trace width = 30 mils
R639
20K/F_4
R657
20K/F_4
C856
1u/6.3V_4
R965 4.7K_4
4
R630 30_4
R631 *SHORT_4
R646 30_4
R764 *33_4
R306 *33_4
R242 *0_4
DSWROK_EC_R
SMB_PCH_CLK
SMB_PCH_DAT
SMB_ME0_CLK
SMB_ME0_DAT
SMB1ALERT#
SMB_ME1_CLK
SMB_ME1_DAT
C854
1u/6.3V_4
C855
1u/6.3V_4
+5V_S5
R962
68.1K/F_4
R964
150K/F_4
R665 1K_4
ACZ_BCLK
ACZ_RST#
ACZ_SDOUT
ACZ_SYNC
AUD_AZACPU_SDO_R
AUD_AZACPU_SDI_R
AUD_AZACPU_SCLK_R
DMIC_DATA0_R
DMIC_CLK0_R
RTC_RST#
SRTC_RST#
EC_PWROK_R
PCH_RSMRST#
Des cript i o n (iPD 2 0 K)
1 = Disable F las h De s cr i ptor Secur i ty (Ove r ride)
U45D
BA9
HDA_BCLK
BD8
HDA_RST#
BE7
HDA_SDI0
BC8
HDA_SDI1
BB7
HDA_SDO
BD9
HDA_SYNC
BD1
RSVD_BD1
BE2
RSVD_BE2
AM1
AN2
AM2
AL42
AN42
AM43
AJ33
AH44
AJ35
AJ38
AJ42
BC10
BB10
AW11
BA11
AV11
BB41
AW44
BB43
BA40
AY44
BB39
AT27
AW42
AW45
System PWR_OK(CLG)
AUDIO
DISPA_SDO
DISPA_SDI
DISPA_BCLK
GPP_D8/I2S0_SCLK
GPP_D7/I2S0_RXD
GPP_D6/I2S0_TXD
GPP_D5/I2S0_SFRM
GPP_D20/DMIC_DATA0
GPP_D19/DMIC_CLK0
GPP_D18/DMIC_DATA1
GPP_D17/DMIC_CLK1
RTCRST#
SRTCRST#
PCH_PWROK
RSMRST#
DSW_PWROK
GPP_C2/SMBALERT#
GPP_C0/SMBCLK
GPP_C1/SMBDATA
GPP_C5/SML0ALERT#
GPP_C3/SML0CLK
GPP_C4/SML0DATA
GPP_B23/SML1ALERT#/ PCHHOT#
GPP_C6/SML1CLK
GPP_C7/SML1DATA
SPT_PCH_H
SPT-H_PCH
GPP_A12/BMBUSY#/ISH_GP 6/SX_EXIT_HOLDOFF#
SMBUS
4 OF 12
0 = *Enable security in the Flash
ACZ_SDOUT
SYSPWOK
4
SYS_PWROK 16
SYS_PWROK
EC_PWROK_R
SYS_PWROK_R
U43
*TC7SH08FU
R620 *0_4
R619 *SHORT_4
Non Deep Sx
For HWPG Sequence
For HWPG Sequence
+1.0V
R819
4
U54
*TC7SH08FU
R970 0_4
*15K/F_4
+1.0V_PWRGD_G1
C895
*0.1U/16V_4
+3V_S5
C821 0.1u/16V_4
3 5
R820
*100K_4
2
SUSC#
1
SUSON_EC
RTC_RST#
1 2
J1
*JUMP
REV:E tPLT15(max 200us)
->SLP_S4# assertion to
VDDQ(+1.35VSUS) ramp
down start(SUSON)
RTC_RST# 16
SRTC_RST#
SUSON
SUSON 40,41 VRON 42
3
GPP_G17/ADR_COMPLETE
GPP_A13/SUSWARN#/SUS PWRDNACK
JTAG
+3V_S5
C851 *0.1u/16V_4
2
EC_PWROK
1
3 5
R243 *SHORT_4
R622 *0_4
R636 *0_4
+5V_S5
R808
*100K_4
+1.0V_PWRGD_G2
2
Q49
*METR3904-G
1 3
SUSON_EC 37
GPP_A8/CLKRUN#
GPD11/LANPHYPC
GPD9/SLP_WLAN#
DRAM_RESET#
GPP_B2/VRALERT#
GPP_B1
GPP_B0
GPP_B11
SYS_PWROK
WAKE#
GPD6/SLP_A#
SLP_LAN#
GPP_B12/SLP_S0#
GPD4/SLP_S3#
GPD5/SLP_S4#
GPD10/SLP_S5#
GPD8/SUSCLK
GPD0/BATLOW#
GPP_A15/SUSACK#
GPD2/LAN_WAKE#
GPD1/ACPRESENT
SLP_SUS#
GPD3/PWRBTN#
SYS_RESET#
GPP_B14/SPKR
PROCPWRGD
ITP_PMODE
JTAGX
JTAG_TMS
JTAG_TDO
JTAG_TDI
JTAG_TCK
EC_PWROK
+3V_S5
3
2
1
SYS_ R E SET#
GPP_B2
BB17
AW22
AR15
LAN_DISABLE
AV13
BC14
DRAM_RESET#
BD23
GPP_B2
AL27
AR27
N44
AN24
AY1
SYS_PWROK_R
BC13
PCIE_WAKE#
BC15
AV15
BC26
PCH_SLP_S0_N
AW15
BD15
BA13
AN15
SUSCLK
BD13
PCH_BATLOW#
BB19
SUSACK#
BD19
SUSWARN#
BD11
PCIE_LAN_WAKE#
BB15
ACPRESENT
BB13
SLP_SUS#_EC
AT13
DNBSWON#
AW1
SYS_RESET#
BD26
ACZ_SPKR
AM3
PROCPWRGD
AT2
AR3
AR2
JTAG_TMS_PCH
AP1
JTAG_TDO_PCH
AP2
JTAG_TDI_PCH
AN3
JTAG_TCK_PCH
EC_PWROK 37
IMVP_PWRGD_3V 2
R625
*10K_4
PCH_PWROK 2,37
R822
*10K_4
HWPG_R
R809 *0_4
Q48
R806
*2N7002K
*100K_4
REV:E   tPLT17(max
200us) ->SLP_S3#
assertion to IMVP
VR_ON(VRON) deassert ion
2
+3V
R210 10K_ 4
CLKRUN#
R651 1K_4
R716 10K_4
TP43
TP37
R635 *SHORT_4
TP102
R645 *10K_4
+1V_S5
R697 *0_4
R693 *0_4
R691 *SHORT_4
JTAG_TMS_PCH 16
JTAG_TDO_PCH 16
JTAG_TDI_PCH 16
JTAG_TCK_PCH 16
CLKRUN# 33,37
SYS_PWROK
PCIE_WAKE# 31,34
SLP_A# 16
PCH_SLP_S0_N 16,37
SUSB# 2,16,37,39
SUSC# 16,37
SLP_S5# 16
SUSCLK 34
SUSWARN#
PCIE_LAN_WAKE# 31
SLP_SUS#_EC 37
DNBSWON# 37
SYS_RESET# 16
ACZ_SPKR 12,32
PROCPWRGD 2
JTAGX_PCH 2,16
+1.2VSUS
1 2
R681
470_4
Add SS D _2014 1210
SUSACK#_EC 37
SUSWARN#_EC 37
DRAMRST
R682 *short_4
For DS3 Sequence
For DS3 -->Ra
Non-DS3 -->Rb
PCH_RSMRST#
DPWROK_C 37
Add PU _20141212
+3V_S5
+3V_S5
+3V
PCH_RSMRST#
DPWROK_C
SYS_PWROK_R
HWPG 2,37
+3V_S5 +3V_S5
C831 0.1u/16V_4
2
3 5
R972 0_4
SUSB#
1
VRON_EC
VRON_EC 37
4
U56
*TC7SH08FU
R678 1K_4
R680 10K_4
R689 10K_4
R262 *10K_4
R267 10K_4
R209 10K_4
PCIE_LAN_WAKE#
PCIE_WAKE#
R232 10K_4
R225 100K_4
DDR3_DRAMRST# 17,18
12
C868
*0.1u/16V_4
+1.0V
+VCCSTPLL
R623
R621
*0_4
*SHORT_4
R634
R633
*210/F_4
*210/F_4
R650
R649
*100/F_4
*100/F_4
Rb
R223 *SHORT_4
R224 *0_4
Ra
ACPRESENT
CLKRUN#
REV:E tPLT18(max 200 us)
->SLP_S3# assertion to
VCCIO VR(MAIND for +1 V_S5
to +VCCIO) disabled
MAINON 41,45
R632
51_4
JTAG_TMS_PCH
JTAG_TDI_PCH
JTAG_TDO_PCH
R648
*100/F_4
DSWROK_EC_R
4
U55
*TC7SH08FU
R971 0_4
JTAG_TCK_PCH
R647
*51_4
C824 0.1u/16V_4
3 5
1
10
2
SUSB#
1
MAINON_EC
MAINON_EC 37
A A
PROJECT :ZRY
PROJECT :ZRY
PROJECT :ZRY
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
5
4
3
Custom
PCH 2/6 (SATA/HDA/ SPI)
PCH 2/6 (SATA/HDA/ SPI)
PCH 2/6 (SATA/HDA/ SPI)
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
1
1A
1A
1A
10 49 Monday, September 07, 2015
10 49 Monday, September 07, 2015
10 49 Monday, September 07, 2015
5
D D
PEG_TXP11_L1 34
PEG_TXN11_L1 34
PEG_RXP11_L1 34
PEG_RXN11_L1 34
PEG_TXP12_L3 34
PEG_TXN12_L3 34
PEG_RXP12_L3 34
C C
TP100
C865 12P/50V_4
1
2
24MHZ +-30PPM
B B
R673
1M_4
Y4
4
3
C862 12P/50V_4
TP99
+1.0V_DEEP_SUS change to +1V_S5
Add XC LK_RN IAS# po rt_2 0141205
24M X'tral--->R2602 (Ra) Un-Install
XTAL24_IN
Green CLK--->R2602 (Ra) Install
XTAL24_OUT
CLK_PEGA_REQ# 19
PCIE_CLKREQ_WLAN# 34
CLK_PCIE_LAN_REQ # 31
PCIE_CLKREQ_NGFF1# 34
PEG_RXN12_L3 34
+1V_S5
R324 *SHORT_4
R276 *SHORT_4
R724 *SHORT_4
R458 *SHORT_4
CLK_DPLL_NSCCLKP 2
CLK_DPLL_NSCCLKN 2
CLK_CPU_BCLKP 2
CLK_CPU_BCLKN 2
R668 2.7K/F_4
RTC Clock 32.768KHz
A A
C861 18P/50 V_4
32.768KHz
C864 18P/50 V_4
Y3
RTC_X1
1 2
R675
10M_4
RTC_X2
5
4
PEG_TXP11_L1
PEG_TXN11_L1
PEG_RXP11_L1
PEG_RXN11_L1
PEG_TXP12_L3
PEG_TXN12_L3
PEG_RXP12_L3
PEG_RXN12_L3
XTAL24_OUT
XTAL24_IN
XCLK_RBIAS
RTC_X1
RTC_X2
PCIE_CLKREQ0#
PCIE_CLKREQ1#
PCIE_CLKREQ2#
PCIE_CLKREQ3#
PCIE_CLKREQ4#
PCIE_CLKREQ5#
PCIE_CLKREQ6#
PCIE_CLKREQ7#
PCIE_CLKREQ8#
PCIE_CLKREQ9#
PCIE_CLKREQ10#
PCIE_CLKREQ11#
PCIE_CLKREQ12#
PCIE_CLKREQ13#
PCIE_CLKREQ14#
PCIE_CLKREQ15#
4
U4 5 C
AV2
CL_CLK
AV3
CL_DATA
AW2
CL_RST#
R44
GPP_G8/FAN_PWM_0
R43
GPP_G9/FAN_PWM_1
U39
GPP_G10/FAN_PWM_2
N42
GPP_G11/FAN_PWM_3
U43
GPP_G0/FAN_TACH_0
U42
GPP_G1/FAN_TACH_1
U41
GPP_G2/FAN_TACH_2
M44
GPP_G3/FAN_TACH_3
U36
GPP_G4/FAN_TACH_4
P44
GPP_G5/FAN_TACH_5
T45
GPP_G6/FAN_TACH_6
T44
GPP_G7/FAN_TACH_7
B33
PCIE11_TXP
C33
PCIE11_TXN
K31
PCIE11_RXP
L31
PCIE11_RXN
AB33
GPP_F10/SCLOCK
AB35
GPP_F11/SLOAD
AA44
GPP_F13/SDATAOUT0
AA45
GPP_F12/SDATAOUT1
B38
PCIE14_TXN/SATA1B_T XN
C38
PCIE14_TXP/SATA1B_T XP
D39
PCIE14_RXN/SATA1B_RXN
E37
PCIE14_RXP/SATA1B_RXP
C36
PCIE13_TXN/SATA0B_T XN
B36
PCIE13_TXP/SATA0B_T XP
G35
PCIE13_RXN/SATA0B_RXN
E35
PCIE13_RXP/SATA0B_RXP
A35
PCIE12_TXP
B35
PCIE12_TXN
H33
PCIE12_RXP
G33
PCIE12_RXN
J45
PCIE20_TXP/SATA7_T XP
K44
PCIE20_TXN/SATA7_T XN
N38
PCIE20_RXP/SATA7_RXP
N39
PCIE20_RXN/SATA7_RXN
H44
PCIE19_TXP/SATA6_T XP
H43
PCIE19_TXN/SATA6_T XN
L39
PCIE19_RXP/SATA6_RXP
L37
PCIE19_RXN/SATA6_RXN
SPT_PCH_H
U45G
AR17
GPP_A16/CLKOUT_48
G1
CLKOUT_CPUNSSC_P
F1
CLKOUT_CPUNSSC
G2
CLKOUT_CPUBCLK_P
H2
CLKOUT_CPUBCLK
A5
XTAL24_OUT
A6
XTAL24_IN
E1
XCLK_BIASREF
BC9
RTCX1
BD10
RTCX2
BC24
GPP_B5/SRCCLKREQ0#
AW24
GPP_B6/SRCCLKREQ1#
AT24
GPP_B7/SRCCLKREQ2#
BD25
GPP_B8/SRCCLKREQ3#
BB24
GPP_B9/SRCCLKREQ4#
BE25
GPP_B10/SRCCLKREQ5#
AT33
GPP_H0/SRCCLKREQ6#
AR31
GPP_H1/SRCCLKREQ7#
BD32
GPP_H2/SRCCLKREQ8#
BC32
GPP_H3/SRCCLKREQ9#
BB31
GPP_H4/SRCCLKREQ10#
BC33
GPP_H5/SRCCLKREQ11#
BA33
GPP_H6/SRCCLKREQ12#
AW33
GPP_H7/SRCCLKREQ13#
BB33
GPP_H8/SRCCLKREQ14#
BD33
GPP_H9/SRCCLKREQ15#
R13
CLKOUT_PCIE_N15
R11
CLKOUT_PCIE_P15
P1
CLKOUT_PCIE_N14
R2
CLKOUT_PCIE_P14
W7
CLKOUT_PCIE_N13
Y5
CLKOUT_PCIE_P13
U2
CLKOUT_PCIE_N12
U3
CLKOUT_PCIE_P12
SPT_PCH_H
CLINK
SPT-H_PCH
FAN
SPT-H_PCH
PCIe/SATA
GPP_E0/SATAXPCIE0/SATAGP0
GPP_E1/SATAXPCIE1/SATAGP1
GPP_E2/SATAXPCIE2/SATAGP2
GPP_F0/SATAXPCIE3/SATAGP3
GPP_F1/SATAXPCIE4/SATAGP4
GPP_F2/SATAXPCIE5/SATAGP5
GPP_F3/SATAXPCIE6/SATAGP6
GPP_F4/SATAXPCIE7/SATAGP7
HOST
3 OF 12
CLKOUT_ITPXDP_P
CLKOUT_CPUPCIBCLK
CLKOUT_CPUPCIBCLK_P
CLKOUT_PCIE_N10
CLKOUT_PCIE_P10
CLKOUT_PCIE_N11
CLKOUT_PCIE_P11
7 OF 12
PCIE9_RXN/SATA0A_RXN
PCIE9_RXP/SATA0A_RXP
PCIE9_TXN/SATA0A_T XN
PCIE9_TXP/SATA0A_T XP
PCIE10_RXN/SATA1A_RXN
PCIE10_RXP/SATA1A_RXP
PCIE10_TXN/SATA1A_T XN
PCIE10_TXP/SATA1A_T XP
PCIE15_RXN/SATA2_RXN
PCIE15_RXP/SATA2_RXP
PCIE15_TXN/SATA2_T XN
PCIE15_TXP/SATA2_T XP
PCIE16_RXN/SATA3_RXN
PCIE16_RXP/SATA3_RXP
PCIE16_TXN/SATA3_T XN
PCIE16_TXP/SATA3_T XP
PCIE17_RXN/SATA4_RXN
PCIE17_RXP/SATA4_RXP
PCIE17_TXN/SATA4_T XN
PCIE17_TXP/SATA4_T XP
PCIE18_RXN/SATA5_RXN
PCIE18_RXP/SATA5_RXP
PCIE18_TXN/SATA5_T XN
PCIE18_TXP/SATA5_T XP
GPP_E8/SATALED#
GPP_F21/EDP_BKLTCTL
GPP_F20/EDP_BKLTEN
GPP_F19/EDP_VDDEN
THERMTRIP#
PLTRST_PROC #
CLKOUT_ITPXDP
CLKOUT_PCIE_N0
CLKOUT_PCIE_P0
CLKOUT_PCIE_N1
CLKOUT_PCIE_P1
CLKOUT_PCIE_N2
CLKOUT_PCIE_P2
CLKOUT_PCIE_N3
CLKOUT_PCIE_P3
CLKOUT_PCIE_N4
CLKOUT_PCIE_P4
CLKOUT_PCIE_N5
CLKOUT_PCIE_P5
CLKOUT_PCIE_N6
CLKOUT_PCIE_P6
CLKOUT_PCIE_N7
CLKOUT_PCIE_P7
CLKOUT_PCIE_N8
CLKOUT_PCIE_P8
CLKOUT_PCIE_N9
CLKOUT_PCIE_P9
PECI
PM_SYNC
PM_DOWN
L1
L2
J1
J2
N7
N8
L7
L5
D3
F2
E5
G4
D5
E6
D8
D7
R8
R7
U5
U7
W10
W11
N3
N2
P3
P2
R3
R4
3
G31
SATA_RXN3/PEG_RXN9_L0
H31
SATA_RXP3/PEG_RXP9_L0
C31
SATA_TXN3/PEG_TXN9_L0
B31
SATA_TXP3/PEG_TXP9_L0
G29
SATA_RXN1/PEG_RXN10_L2
E29
SATA_RXP1/PEG_RXP10_L2
C32
SATA_TXN1/PEG_TXN10_L2
B32
SATA_TXP1/PEG_TXP10_L2
F41
E41
B39
A39
D43
E42
A41
A40
H42
H40
E45
F45
K37
G37
G45
G44
AD44
AG36
AG35
AG39
AD35
AD31
AD38
AC43
AB44
W36
W35
W42
AJ3
PCH_THRMTRIP_R#
AL3
AJ4
PM_SYNC_R
AK2
AH2
H_PM_DOWN
CK_XDP_N_R
CK_XDP_P_R
3
SATA_LED#
R783 10K_4
GPIO37
GPIO34
GPIO35
GPIO36
R627 620_4
R643 30_4
R628 *SHORT_4
R661 *short_4
R656 *short_4
CPU_PCI_BCLKN 2
CPU_PCI_BCLKP 2
CLK_PCIE_VGA# 19
CLK_PCIE_VGA 19
TP47
TP42
CLK_PCIE_WL ANN 34
CLK_PCIE_WL ANP 34
CLK_PCIE_LANN 31
CLK_PCIE_LANP 3 1
TP39
TP40
TP44
TP41
TP69
TP68
CLK_PCIE_NGFF1_N 34
CLK_PCIE_NGFF1_P 34
TP110
+3V
R86 0_4
R85 *0_4
R461 *0_4
TP52
R459 *0_4
PCH_BRIGHT 29
PCH_BLON 29
EDP_VDD_EN 29
CK_XDP_N
CK_XDP_P
VGA
WLAN
LAN
NGFF SSD
SATA_RXN3/PEG_RXN9_L0 34
SATA_RXP3/PEG_RXP9_L0 34
SATA_TXN3/PEG_TXN9_L0 34
SATA_TXP3/PEG_TXP9_L0 34
SATA_RXN1/PEG_RXN10_L2 34
SATA_RXP1/PEG_RXP10_L2 34
SATA_TXN1/PEG_TXN10_L2 34
SATA_TXP1/PEG_TXP10_L2 34
SATA_RXN0 33
SATA_RXP0 33
SATA_TXN0 33
SATA_TXP0 33
PM_THRMTRIP# 2,5,17,18
PM_SYNC 2
CPU_PLTRST#R 2
H_PM_DOWN 2
CK_XDP_N 1 6
CK_XDP_P 16
2
M.2.SSD
HDD (SATA0 6Gb/s)
GPIO37
GPIO34
GPIO35
PCIE_CLKREQ4#
PCIE_CLKREQ1#
PCIE_CLKREQ0#
PCIE_CLKREQ2#
PCIE_CLKREQ3#
PCIE_CLKREQ5#
PCIE_CLKREQ6#
PCIE_CLKREQ7#
PCIE_CLKREQ8#
PCIE_CLKREQ9#
PCIE_CLKREQ10#
PCIE_CLKREQ11#
PCIE_CLKREQ12#
PCIE_CLKREQ13#
PCIE_CLKREQ14#
PCIE_CLKREQ15#
GPIO36
R10821 *10K_4
R719 *10K_4
R275 *10K_4
R718 10K_4
R278 10K_4
R723 10K_4
R721 *10K_4
R318 *10K_4
R317 10K_4
R736 *10K_4
R735 *10K_4
R731 *10K_4
R739 *10K_4
R315 *10K_4
R316 *10K_4
R738 *10K_4
R734 *10K_4
R10819 *10K_4
R10820 *10K_4
NGFF3_DET 34
R644
*10K_4
PCH_PECI 2
Change from I to NI(For SCH List) _20141212
2
1
+3V
R10814 10K _4
R10816 10K _4
R10817 10K _4
R10815 10K _4
R10818 *10K_4
+3V
PROJECT :ZRY
PROJECT :ZRY
PROJECT :ZRY
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
PCH 3/6 (PCIE/USB/CLK)
PCH 3/6 (PCIE/USB/CLK)
PCH 3/6 (PCIE/USB/CLK)
Date: Sheet of
Date: Sheet of
Date: Sheet of
1
11
11 49 Tuesday, Augu st 25, 2015
11 49 Tuesday, Augu st 25, 2015
11 49 Tuesday, Augu st 25, 2015
1A
1A
1A
5
PLTRST# Buffer
PLTRST#(CLG)
D D
SIO_EXT_SMI# 9,37
C C
TP103
PCH_SPI_SI
PCH_SPI_SO
PCH_SPI_CS0#
PCH_SPI_CLK
PCH_SPI_CS1#
PCH_SPI_IO2
PCH_SPI_IO3
SIO_EXT_SMI#
AW31
AG15
AG14
AF17
AE17
AR19
AN17
BB29
BE30
BD31
BC31
BC29
BD30
AT31
AN36
AL39
AN41
AN38
AH43
AG44
GPP_A11/PM E#
RSVD
RSVD
RSVD
RSVD
TP2
TP1
SPI0_MOSI
SPI0_MISO
SPI0_CS0#
SPI0_CLK
SPI0_CS1#
SPI0_IO2
SPI0_IO3
SPI0_CS2#
GPP_D1/SPI1_C LK
GPP_D0/SPI1_C S#
GPP_D3/SPI1_M OSI
GPP_D2/SPI1_M ISO
GPP_D22/SPI1_ IO3
GPP_D21/SPI1_ IO2
SPT_PCH_H
U45A
BD17
PCI_PME#
SP@ socket P/N: DFHS08FS023 only fo r A-TEST
Vender Size Quanta P/N Vender P/N
SPI ROM
Skylake
3.3V
Skylake
3.3V
EON
WND
PCH_SPI_CLK_EC 37
PCH_SPI_SI_EC 37
PCH_SPI_SO_EC 37
SPI_CS0#_UR_ME 37
B B
A A
16M
+3V_PCH_ME
AKE3EFP0N07
8M
AKE2EZN0Q00
8M
AKE3EZN0Q01
8M
AKE3DZN0N01
R694 10K_4
R774 *4M@33_4
R748 *4M@33_4
R698 *4M@33_4
R707 *SHORT_4
R711 *4M@0_4
SPI_CS0#_UR_ME
5
W25Q64FVSSIQ WND
GD25B64CSIGR GGD
EN25QH64-104HIP
W25Q128FVSIQ
PCH_SPI_CLK_R
PCH_SPI_SI_R
PCH_SPI_SO_R
PCH_SPI_CS0#
PCH_SPI_CS1#
only 0ohm option
SPT-H_PCH
1 OF 12
1A-13
PCH_SPI_SO
PCH_SPI_SO_EC
3.3K is original and for no
support fast read function
GPP_B13/PL TRST#
GPP_G16/GSXCL K
GPP_G12/GSXDOU T
GPP_G13/GSXS LOAD
GPP_G14/GSXDIN
GPP_G15/GSXS RESET#
GPP_E3/CPU_ GP0
GPP_E7/CPU_ GP1
GPP_B3/CPU_ GP2
GPP_B4/CPU_ GP3
GPP_H18/SML 4ALERT#
GPP_H17/SML 4DATA
GPP_H16/SML 4CLK
GPP_H15/SML 3ALERT#
GPP_H14/SML 3DATA
GPP_H13/SML 3CLK
GPP_H12/SML 2ALERT#
GPP_H11/SML 2DATA
GPP_H10/SML 2CLK
INTRUDER #
PCH SPI ROM(8M+4M)
15ohm CS01502JB12
33ohm CS03302JB29
PCH_SPI_CS0#
R708 8M4M@15_4
R709 8M@0_4
R710 1K_4
+3V_PCH_ME
PCH_SPI_CS1#
PCH_SPI_CLK
R747 *4M@33_4
R775 *4M@33_4
PCH_SPI_SI
PCH_SPI_SO
R712 *4M@33_4
C876 *22p/50V_4
PCH_SPI_CLK_R
PCH_SPI_SI_R
PCH_SPI_SO_R
+3V_PCH_ME
1A-3 2013/10/16 Add U34 flash 4M ROM reserve for ZQ0D.
BB27
P43
R39
R36
R42
R41
AF41
AE44
BC23
BD24
BC36
BE34
BD39
BB36
BA35
BC35
BD35
AW35
BD34
BE11
PCI_PLTRST#
DGPU_PW_CTRL#
SML4ALERT#
SMB_ME4_DAT
SMB_ME4_CLK
SML3ALERT#
SMB_ME3_DAT
SMB_ME3_CLK
SML2ALERT#
SMB_ME2_DAT
SMB_ME2_CLK
SM_INTRUDER#
SPI_SO_8M
SPI_WP_IO2_ME
PCH_SPI_IO2
PCH_SPI_IO3
R703 *1K_4
4
+3V_S5
U47
1
CS#
2
IO1/DO
3
IO2/W P#
4
GND
W25Q64FW -- 8MB
R713 *4M@33_4
R702 8M4M@15_4
R746 *4M@33_4
R773 8M4M@15_4
1
6
5
2
3
SPI_WP_IO2_EC
4
2
1
R305 *0_4
DGPU_PW_CTRL# 13
TP107
R677 1M_4
R754 *SHORT_6
VCC
IO3/HOLD #
CLK
IO0/DI
PCH_SPI_CLK_EC
PCH_SPI_SI_EC
U46
CE#
VDD
SCK
SI
SO
HOLD#
WP#
VSS
*4M@ROM-4M_EC
+3V
C518 0.1u/16V_4
4
U24
3 5
TC7SH08FU
+3V_RTC
+3V_PCH_ME
8
7
SPI_HOLD_IO3_ME
6
SPI_CLK_8M
5
SPI_SI_8M
R744 8M@15_4
R745 8M@15_4
SPI_HOLD_IO3_EC
SPI_HOLD_IO3_ME
8
7
SPI_HOLD_IO3_EC
4
3
PLTRST# 2,16,19,31,33,34,37
R307
100K_4
C873 0.1u/16V_4
R743 1K_4
R770 8M4M@15_4
R771 8M4M@15_4
SPI_WP_IO2_EC
SPI_WP_IO2_ME
reserve for SPI fast read
+3V_PCH_ME
R772 *1K_4 R729
C874
*4M@0.1u/16V_4
+3V_PCH_ME
PCH_SPI_CLK
PCH_SPI_SI
C875
*22p/50V_4
SMB_ME4_CLK
SMB_ME4_DAT
SMB_ME3_CLK
SMB_ME3_DAT
SMB_ME2_CLK
SMB_ME2_DAT
R749 499/F_4
R737 499/F_4
R741 499/F_4
R326 499/F_4
R742 499/F_4
R325 499/F_4
TLS CONFIDENTIALITY ENABLED
HIGH:T Enable Intel ME Crypto Transport Layer Security
(TLS) cipher suite (with confidentiality). (CRB)
LOW: Disable Intel ME Crypto Transport Layer Security
(TLS) cipher suite (no confidentiality). (Default)
SMBALERT# 10
3
+3V_DEEP_SUS
Add PCH Strap Pin_20141203
TOP SWAP OVERRIDE STRAP
HIGH:TOP SWAP ENABLED (CRB)
LOW:TOP SWAP DISABLED(DEFAULT)
ACZ_SPK R 10,32
NO REBOOT IF SAMPLED HIGH
HIGH:TOP SWAP ENABLED (CRB)
LOW: Disable "No Reboot" mode. (Default)
SMBALERT#
BBS_BIT1
+3V_DEEP_SUS
R333
4.7K_4
R332
*20K/F_4
BBS_BIT1 13
Change R2725 from I to N_20141212
+3V
R727
*150K/F_4
+3V
R337
4.7K_4
BOOT SELE CT STRAP
HIGH:LPC
LOW: SPI. (Default)
S_GPIO 13
R722
*20K/F_4
ESPI/LPC SELECT STRAP
HIGH:eSPI Is selected for EC.
LOW: LPC Is selected for EC. (Default)
SML0ALERT# 10
R336
*20K/F_4
RESERVED
This strap should sample HIGH.
There should NOT be any on-board device
driving it to opposite direction during
strap sampling.
PCH_SPI_SI
S_GPIO
SML0ALERT#
+3V_DEEP_SUS
*20K/F_4
R728
*4.7K_4
2
+3V_DEEP_SUS
R766
*4.7K_4
R767
*20K/F_4
+3V_DEEP_SUS
R335
*4.7K_4
R334
4.7K/F_4
TLS CONFIDENTIALITY ENABLED
HIGH: Flash Descriptor Security (override). This
strap should only be asserted high using external
pull-up in manufacturing/debug environments ONLY.(CRB)
LOW: security measures defined in the Flash
Descriptor. (Default)
2
RESERVED
This strap should sample HIGH.
There should NOT be any on-board device
driving it to opposite direction during
strap sampling.
PCH_SPI_SO
RESERVED
This strap should sample LOW.
There should NOT be any on-board device
driving it to opposite direction during
strap sampling.
SMB1ALERT# 10,35
RESERVED
This strap should sample HIGH.
There should NOT be any on-board device
driving it to opposite direction during
strap sampling.
RESERVED
This strap should sample HIGH.
There should NOT be any on-board device
driving it to opposite direction during
strap sampling.
ME_WR# 10, 37
SMB1ALERT#
ME_WR#
PCH_SPI_IO2
PCH_SPI_IO3
+3V_DEEP_SUS
R640
*1K_4
+3V_DEEP_SUS
R653
*1K_4
1
+3V_DEEP_SUS
R301
*20K/F_4
R298
*4.7K_4
R292
*4.7K_4
R294
*20K/F_4
+3V_DEEP_SUS
+3V_DEEP_SUS
ESPI FLASH SHARING MODE
HIGH:SLAVE ATTACEHD FLASH SHARING
LOW: 0: MASTER ATTACHED FLASH SHARING
This strap should sample LOW.
There should NOT be any on-board device
driving it to opposite direction during
strap sampling.
DFX TEST MODE QUALIFIER FOR OTHER DFX STRAP
WHEN SAMPLED LOW
PGDMON 15
DFX TEST MODE
XTAL INPUT IS SINGLE ENDED IF
SAMPLED LOW ELSE DIFFERENTIAL
R730
*20K/F_4
R726
*4.7K_4
R733
*20K/F_4
R732
*100_4
DGPU_PWROK 13,21
RING OSCILLATOR BYPASS
DGPU_HOLD_RST# 13,19
DGPU_PWR_EN 13,47
XTAL INPUT FREQUENCY[1]
PROJECT :ZRY
PROJECT :ZRY
PROJECT :ZRY
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
PCH 4/6 (GPIO/MISC)
PCH 4/6 (GPIO/MISC)
PCH 4/6 (GPIO/MISC)
Date: Sheet of
Date: Sheet of
Date: Sheet of
1
SML2ALERT#
PGDMON
DGPU_PWROK
DGPU_HOLD_RST#
DGPU_PWR_EN
+3V_DEEP_SUS
R751
*4.7K_4
R740
*20K/F_4
+3V_DEEP_SUS
R266
*1K_4
R264
*1K_4
+3V_DEEP_SUS
R288
*10K_4
12
R281
*10K_4
R293
*10K_4
R287
*10K_4
1A
1A
1A
12 49 Monday , S ept ember 07, 201 5
12 49 Monday , S ept ember 07, 201 5
12 49 Monday , S ept ember 07, 201 5
5
+3V
PCI_SERR#
R788 *10K_4
4
3
2
+3V _ D E EP_SU S 9,10,12,14, 1 6,17
1
13
Touchpad INT
TPD_INT#_D
D D
C C
S5 S5
TPD_INT# 35,37
+3V
+3V
DGPU_PW_CTRL# 12
20131015 For GC6 NV DG GC6_FB_EN PD. 1A-1
R274 10K_4
high UMA Only
low
R714 EV @100K_4
R196 EV@10K_4
R283 *10K_4
GPU power is control by PCH
GPIO (Discrete, SG or Optimize)
DGPU_PWROK PD on GPU side
R652 100K_4
R637 100K_4
100k pull-down on PCH side
Skylake-H Strapping Table
B B
Pin Name Strap description
GPP_B14 (SPKR)
GPP_B18
(GSPI0_MOSI)
GPP_C2
(SMBALERT#)
GPP_B22
(GSPI1_MOSI)
GPP_C5
(SML0ALERT#)
SPI0_MOSI
SPI0_MISO
GPP_B23
(SML1ALERT#
/PCHHOT#)
SPI0_IO2
SPI0_IO3
HDA_SDO /
I2S_TXD0
A A
GPP_E19
(DDPB_CTRLDATA)
GPP_E21
(DDPC_CTRLDATA)
+3V_S5
R769 TP D@10K_4
+3V
2
3
1
R778 *0_4
2N7002K
TPD_INT#_D
Q46
GPU Control PU/PD
R309 *10K_4
VGPU_EN
DGPU_PWR_EN
GC6_FB_EN
DGPU_HOLD_RST#
DGPU_PW_CTRL#
DGPU_PWROK
CRT_HPD
EDP_HPD
R624 *10K/F_4
R715 *IV@1K_4
R286 *10K_4
+3V
R201 *IV@10K_4
R282 *100K_4
R313 *10K_4
+3V
Top-Block Swap override PCH_PWROK
No reboot PCH_PWROK
TLS Confidentiality
Boot BIOS Strap Bit (BBS)
eSPI or LPC
Reserved
Reserved
Reserved
Reserved
Reserved
Flash Descriptor Security
Override / Intel ME Debug Mode
Display Port B Detected
Display Port C Detected
Sampled
RSMRST#
PCH_PWROK
RSMRST#
RSMRST#
RSMRST#
RSMRST#
RSMRST#
RSMRST#
PCH_PWROK
PCH_PWROK
PCH_PWROK
Add GPU Po wer Co ntr ol S iga nls
TP147
BBS_BIT1 12
PM_EXTTS#0 17
TP_INT_PCH 29
ACCEL_INTA# 35
EXTTS#1 17
S_GPIO 12
PCI_SERR#
R787 *100_4
Touch Screen
Touch PAD
I2C1_SCL 29
I2C1_SDA 29
I2C0_SCL 35
I2C0_SDA 35
waiting for define!
U45E
EDP_HPD
CRT_HPD
AW4
AY2
AV4
BA4
BD7
GPP_I0/DDPB_HPD0
GPP_I1/DDPC_HPD1
GPP_I2/DDPD_HPD2
GPP_I3/DDPE_HPD3
GPP_I4/EDP_HPD
SPT_PCH_H
INT_HDMI_HPD 30
CRT_HPD 28
TP38
SIO_EXT_SCI# 37
R230 10K_4
+3V_DEEP_SUS
EDP_HPD 29
Configuration note
0 = *Disable Top Swap (iPD 20K)
1 = Enable Top Swap Mode
0 = *Disable No Reboot (iPD 20K)
1 = Enable No Reboot Mode
0 = *Disable Intel ME Cryp to TLS(iPD 20K)
1 = Enable Intel ME Cryp to TLS
0 = *SPI (iPD 20K)
1 = LPC
0 = *LPC is selected for EC (iPD 20K)
1 = eSPI selected for EC
(iPU 15 ~ 40K)
(iPU 15 ~ 40K)
(iPD 20K)
(iPU 15 ~ 40K)
(iPU 15 ~ 40K)
0 = *Enable security in the Flash
Description (iPD 20K)
1 = Disable Flash Descriptor Security (Override)
0 = *Port B is not detected (iPD 20K)
1 =Port B is detected
0 = *Port C is not detected (iPD 20K)
1 =Port C is detected
U45K
AT29
ODD_PRSNT#
BBS_BIT1
ACCEL_INTA#
I2C1_SCL
I2C1_SDA
I2C0_SCL
I2C0_SDA
SPT-H_PCH
R725 *1K_4
R717 *1K_4
GSPI1_MOSI
GSPI0_MOSI
TPD_INT#_D
UART2_CTS
UART2_RTS
UART2_TXD
UART2_RXD
GPP_I7/DDPC_CTRLCLK
GPP_I8/DDPC_CTRLDAT A
GPP_I5/DDPB_CTRLCLK
GPP_I6/DDPB_CTRLDAT A
GPP_I9/DDPD_CTRLCLK
GPP_I10/DDPD_CTRLDAT A
5 OF 12
DGPU_EVENT# 22
GC6_FB_EN 19,22
DGPU_PWROK 12, 21
DGPU_PWR_EN 12,47
DGPU_HOLD_RST# 12,19
VGPU_EN 46
R768 *0_4
TP112
+3V
+3V
GSPI0_MOSI
GSPI1_MOSI
AW27
AM44
GPP_F14
GPP_F23
GPP_F22
GPP_G23
GPP_G22
GPP_G21
GPP_G20
GPP_H23
AR29
AV29
BC27
BD28
BD27
AR24
AV44
BA41
AU44
AV43
AU41
AT44
AT43
AU43
AN43
AN44
AR39
AR45
AR41
AR44
AR38
AT42
AJ44
GPP_B22/GSPI1_MOSI
GPP_B21/GSPI1_MISO
GPP_B20/GSPI1_CLK
GPP_B19/GSPI1_CS#
GPP_B18/GSPI0_MOSI
GPP_B17/GSPI0_MISO
GPP_B16/GSPI0_CLK
GPP_B15/GSPI0_CS#
GPP_C9/UART0_TXD
GPP_C8/UART0_RXD
GPP_C11/UART0_CTS#
GPP_C10/UART0_RTS#
GPP_C15/UART1_CTS#/I SH_UART1_CTS#
GPP_C14/UART1_RTS#/I SH_UART1_RTS#
GPP_C13/UART1_TXD/I SH_UART1_TXD
GPP_C12/UART1_RXD/IS H_UART1_RXD
GPP_C23/UART2_CTS#
GPP_C22/UART2_RTS#
GPP_C21/UART2_TXD
GPP_C20/UART2_RXD
GPP_C19/I2C1_SCL
GPP_C18/I2C1_SDA
GPP_C17/I2C0_SCL
GPP_C16/I2C0_SDA
GPP_D4/ISH_I2C2_SDA/IS H_I2C3_SDA
GPP_D23/ISH_I2C2_SCL/ISH _I2C3_SCL
SPT_PCH_H
BB3
BD6
BA5
BC4
BE5
BE6
Y44
V44
W39
L43
L44
U35
R35
BD36
SPT-H_PCH
GPP_D14/ISH_UART0_TX D/SML0BCLK/I2C2_SCL
GPP_D13/ISH_UART0_RXD /SML0BDATA/I2C2_S DA
11 OF 12
CRT_CLK
CRT_DATA
SKTOCC_N_R
HDMI_DDCCLK_SW 30
HDMI_DDCDATA_SW 30
TP50
TP36
SKTOCC_N_R 2
New CN to CPU_20141 203
CRT_CLK
R211 2.2K_4
CRT_DATA
R638 2.2K_4
GPP_D9
GPP_D10
GPP_D11
GPP_D12
GPP_D16/ISH_UART0_CT S#
GPP_D15/ISH_UART0_RT S#
GPP_H20/ISH_I2C0_SCL
GPP_H19/ISH_I2C0_SDA
GPP_H22/ISH_I2C1_SCL
GPP_H21/ISH_I2C1_SDA
GPP_A23/ISH_GP5
GPP_A22/ISH_GP4
GPP_A21/ISH_GP3
GPP_A20/ISH_GP2
GPP_A19/ISH_GP1
GPP_A18/ISH_GP0
GPP_A17/ISH_GP7
+3V
Board_ID4 29
BOARD_ID0
BOARD_ID1
BOARD_ID2
BOARD_ID3
BOARD_ID4
Board ID
R794 10K_4
R320 10K_4
R323 10K_4
R263 *10K_4
R704 10K_4
R700 *10K_4
R699 *10K_4
R991 *10K_4
R986 10K_4
R765 *IV@10K_4
Low
VRAM 2GB VRAM 4GB
Reserved
(Default)
TPM
No touch panel
High
Reserve
G-sensor No G-sensor
No TPM
touch panel
RAM_ID1
RAM_ID2
RAM_ID3
Board_ID0
Board_ID1
Board_ID2
Board_ID3
Board_ID4
Board_ID5
Board_ID6
SKU_ID0
R786 EV@10K_4
UMA Only
dGPU Only
AL44
SKU_ID0
AL36
RAM_ID3
AL35
RAM_ID2
AJ39
RAM_ID1
AJ43
AL43
AK44
AK45
BC38
BB38
BD38
BE39
BC22
BOARD_ID6
BD18
BOARD_ID5
BE21
BOARD_ID4
BD22
BOARD_ID3
BD21
BOARD_ID2
BB22
BOARD_ID1
BC19
BOARD_ID0
R785 *10K_4
R322 *10K_4
R327 *10K_4
R261 10K_4
R705 *10K_4
R701 10K_4
R706 10K_4
R695 10K_4
R990 10K_4
R987 *10K_4
SKU_ID0
0
1
+3V_DEEP_SUS
+3V_DEEP_SUS
VGA H/W
Signal
UMA
GPU
Setup
Menu
Hidden
Hidden
UMA boot
GPU boot
High Low
Reserved
BOARD_ID5
BOARD_ID6
Reserve UART FFC connect or for Win 7 debug
UART2_RXD
UART2_TXD
UART2_RTS
UART2_CTS
UART2_RXD
UART2_TXD
UART2_RTS
UART2_CTS
(Before C1)
(Default)
R802 *49.9K/F_4
R799 *49.9K/F_4
R798 *49.9K/F_4
R795 *49.9K/F_4
+5V
CN14
1
2
3
7
4 8
5
6
*UART Function
Reserved
(After C2)
Reserve Reserved
+3V_S5
5
4
3
PROJECT :ZRY
PROJECT :ZRY
PROJECT :ZRY
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
PCH 4/6 (GPIO/MISC )
PCH 4/6 (GPIO/MISC )
PCH 4/6 (GPIO/MISC )
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
1
1A
1A
1A
13 49 Tuesday, September 08, 2015
13 49 Tuesday, September 08, 2015
13 49 Tuesday, September 08, 2015
5
4
3
2
1
14
SPT-H_PCH
CORE
MPHY
USB
VCCGPIO
8 OF 12
VCCPRIM_1P0
VCCDSW_3P3
VCCPGPPA
VCCPGPPBCH
VCCPGPPBCH
VCCPGPPEF
VCCPGPPEF
VCCPGPPG
VCCPRIM_3P3
VCCPRIM_1P0
VCCATS
VCCRTCPRIM_3P3
VCCRTC
DCPRTC
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCSPI
VCCSPI
VCCSPI
VCCPGPPD
VCCPGPPD
VCCPGPPD
VCCPGPPD
VCCPRIM_3P3
VCCPRIM_3P3
VCCPRIM_3P3
0.0908A
AL22
0.403A
BA24
0.0879A
BA31
0.27262A
BC42
BD40
AJ41
0.14107A
AL41
0.1318A
AD41
0.2875A
AN5
AD15
+VCCPRIM_1.0V_AJ20_AD15
AD13
+VCCATS
BA20
+VCCRTCPRIM_3.3V
BA22
BA26
DCPRTC
AJ20
+VCCPRIM_1.0V_AJ20
AJ21
AJ23
AJ25
BE41
BE43
BE42
BC44
BA45
BC45
BB45
BD3
BE3
BE4
0.0121A
0.081A
+VCCPRIM_1.0V_AL22
+VCCPGPPA
+VCCPGPPEF
+VCCPRIM_3P3
C473 *0.1U/16V_4
0.0066A
0.002A
C509 0.1U/16V_4
C492 0.1U/16V_4
+VCCSPI
+VCCPGPPD
C467 *1U/6.3V_4
+3V_RTC
C487
1U/6.3V_4
R260 *SHOR T_6
R245 *SHORT_6
R244 *SHORT_6
R257 *SHORT_6
R221 *SHOR T_6
R277 *SHOR T_6
**Layout Note: +VCCPRIM_1P0 total :5.5167A**
R753 *SHOR T_6
R752 *SHORT_6
C488
0.1U/16V_4
C508 1U/6.3V_4
+VCCDSW3P3
C493 *1U /6.3V_4
+VCCPGPPBCH
C529 *0.1U/16 V_4
C879 *0.1U/16 V_4
+VCCPGPPG
+3V_DEEP_SUS
+3V_DEEP_SUS
+3V_DEEP_SUS
+3V_RTC
+3V_DEEP_SUS
+VCCRTCPRIM_3.3V
C480
1U/6.3V_4
+1V_S5
+VCCPGPPEF
+1V_S5
+1V_S5
+3V_DEEP_SUS
+3V_DEEP_SUS
C481
0.1U/16V_4 R247 *0_4
R314 *SHORT_ 6
+3V_DEEP_SUS
R328 *SHORT_ 6
+3V_DEEP_SUS
R793 *SHORT_6
R796 *SHORT_ 6
+3V_DEEP_SUS
+VCCPGPPEF
+VCCATS
C469
1U/6.3V_4
+3V_DEEP_SUS
C877
0.1U/16V_4
D D
Add R268 9 for NI to +1. 0V_D EEP_ SUS_2 0141 224
+1V_S5 +VCCDSW_1.0V
+1V_S5
C445
22U/6.3V_6
C C
+3V_S5
C446
22U/6.3V_6
R246 *SHORT_4
+1V_S5
R291 *0_6
+1V_S5
+1V_S5
+1V_S5
+1V_S5
+1V_S5
+1V_S5
+1V_S5
+1V_S5
+V3.3DX_1.5DX_ADO
R303 *SHORT_6
+VCCDSW_1.0V
R297 *SHORT_6
R321 *SHORT_6
R330 *SHORT_6
R302 *SHORT_6
R220 *SHORT_6
R222 *SHORT_6
R256 *SHORT_6
C472 1U/6.3V_4
C479 *1U/6.3V_4
+VCCPRIM_1.0V_AJ20_AA23
C491 *1U/6.3V_4
C504 1U/6.3V_4
R217 *SHOR T_6
R259 *SHOR T_6
R219 *SHOR T_6
R218 *SHOR T_6
R216 *SHOR T_6
C457 *1U/6.3V_4
C494 1U/6.3V_4
C489 22U/6.3V_6
0.0248A
C531 1U/6.3V_4
0.0248A
C539 1U/6.3V_4
C483 1U/6.3V_4
0.095A
0.533A
0.01A
0.01A
0.075A
0.0454A
0.0348A
0.0237A
0.0237A
0.0327A
+VCCAMPHY_1P0
+VCCAMPHYPLL_1P0
+VCCPCIE3PLL_1P0
+VCCHDAPLL_1P0
+VCCCLK1
+VCCCLK3
+VCCCLK4
+VCCCLK2
+VCCCLK5
+VCCAPLLEBB
+VCCPRIM_1.0V_AC17
+VCCUSB2PLL_1P0
+VCCDSW3P3
Change C2364 from NI to I _20141212
+1.5V
+V3.3DX_1.5DX_ADO
AA23
AA26
AA28
AC23
AC26
AC28
AE23
AE26
Y23
Y25
BA29
N17
R19
U20
V17
R17
U21
U23
U25
U26
V26
A43
B43
C44
C45
V28
AC17
AJ5
AL5
AN19
BA15
W15
K2
K3
U45H
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
DCPDSW_1P0
VCCCLK1
VCCCLK3
VCCCLK4
VCCCLK2
VCCCLK2
VCCCLK5
VCCCLK5
VCCMPHY_1P0
VCCMPHY_1P0
VCCMPHY_1P0
VCCMPHY_1P0
VCCMPHY_1P0
VCCMPHYPLL_1P0
VCCMPHYPLL_1P0
VCCPCIE3PLL_1P0
VCCPCIE3PLL_1P0
VCCAPLLEBB_1P0
VCCPRIM_1P0
VCCUSB2PLL_1P0
VCCUSB2PLL_1P0
VCCHDAPLL_1P0
VCCHDA
VCCDSW_3P3
SPT_PCH_H
B B
+3V
for DS3
R296 *SHO RT_4
R350
100K_4
SLP_SUS_ON 37
A A
C564
1U/6.3V_4
C555
*10P/50V _4
R347
1 2
*short_6
U27
5
IN
4
IN
3
ON/OFF
*IC(5P) G524 3AT11U-Lay
OUT
GND
5
4
3
+3V_DEEP_SUS +3V_S5
+3V_DEEP_SUS 9,10,12,13,16,17
1
2
C548
0.1U/10V_4
PROJECT :ZRY
PROJECT :ZRY
PROJECT :ZRY
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
PCH 5/6 (POWER)
PCH 5/6 (POWER)
PCH 5/6 (POWER)
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
1
1A
1A
1A
14 49 Tuesday, August 25, 2015
14 49 Tuesday, August 25, 2015
14 49 Tuesday, August 25, 2015
5
4
3
2
1
15
U45I
SPT-H_PCH
AC18
VSS
AN4
VSS
AN10
VSS
BE14
D D
C C
B B
BE18
BE23
BE28
BE32
BE37
BE40
BE9
M35
M42
AA17
AA18
AA20
AA21
AA25
AA29
AA4
AA42
AB10
C10
C28
C37
K10
K27
K33
K36
K42
K43
L12
L13
L15
L41
N10
N15
N19
N22
N24
N35
N36
N41
P17
P19
P22
P45
R10
R14
R22
R29
R33
R38
Y18
Y20
Y21
Y26
Y28
Y29
A18
A25
A32
A37
C2
J7
K4
L4
L8
N4
N5
R5
T1
T2
T4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SPT_PCH_H
9 OF 12
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AR5
AR7
U15
AL4
AE29
AE4
AE42
AF18
AF20
AF21
AF23
AF25
AF26
AF28
AF29
AG11
AG13
AG31
AG32
AG33
AG38
AG4
AH1
AH17
AH18
AH20
AH21
AH23
AH25
AH26
AH28
AH29
AH45
AJ10
AJ14
AJ15
AJ17
AJ18
AJ26
AJ28
AJ29
AJ31
AJ32
AJ36
AK4
AK42
AU7
AV17
AV24
AV27
AV31
AV33
AV6
AW13
AW19
AW29
AW37
AW9
AY38
AY45
B25
B3
B37
B40
B6
BA1
BB11
BB16
BB21
BB25
BB30
BB34
BC2
BD43
W14
W31
W32
W33
W38
C42
D10
D12
D15
D16
D17
D19
D21
D24
D25
D27
D29
D30
D31
D33
D35
D36
E13
E15
E31
E33
F44
G42
H17
H19
H22
H24
H27
H29
H35
J10
J11
J39
T42
U10
U11
U14
U17
U18
U28
U29
U31
U32
U33
U38
V18
V20
V21
V23
V25
V29
V45
W4
W8
Y17
F8
G9
H3
J3
J5
U4
U8
V3
SPT-H_PCH
U45L
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SPT_PCH_H
12 OF 12
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AB11
AB7
AB14
AB31
AB32
AB38
AB4
AB5
AC1
AC20
AC21
AC25
AC29
AC45
AB8
AD11
AD14
AB15
AD32
AD33
AD36
AD4
AD8
AE18
AE20
AE21
AE25
AE28
AL10
AL11
AL13
AL17
AL19
AL24
AL29
AL32
AL33
AL38
AM15
AM17
AM19
AM22
AM24
AM27
AM29
AM45
AN11
AN22
AN27
AN31
AN39
AN7
AN8
AP11
AP4
AR33
AR34
AR42
AR9
AT10
AT15
AT36
AT9
AU1
AU35
AU36
AU39
AU45
C4
BD2
BD45
BD44
BE44
BC1
D45
A42
B45
B44
BB1
A44
A4
A3
B2
A2
B1
C1
D1
U45J
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
RSVD
RSVD
SPT_PCH_H
SPT-H_PCH
AR22
W13
U13
P31
N31
P27
R27
N29
P29
AN29
R24
P24
AT3
AT4
AY5
AL2
AK1
PGDMON
PCH_2_CPU_TRIG_R
R629 30_4
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
PREQ#
PRDY#
CPU_TRST#
PCH_TRIGOUT
PCH_TRIGIN
10 OF 12
PCH_2_CPU_TRIG 8
PCH_2_CPU_TRIG PCH_2_CPU_TRIG_R
PGDMON 12
XDP_PREQ# 2,16
XDP_PRDY# 2,16
XDP_TRST# 2,16
CPU_2_PCH_TRIG 8
A A
+3VPCU 5,10,29,31,32,34,35,37,38,39,46,47
PROJECT :ZRY
PROJECT :ZRY
PROJECT :ZRY
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
5
4
3
2
PCH 6/6 (GND)
PCH 6/6 (GND)
PCH 6/6 (GND)
Date: Sheet of
Date: Sheet of
Date: Sheet of
1
1A
1A
1A
15 49 Tuesday, August 25, 2015
15 49 Tuesday, August 25, 2015
15 49 Tuesday, August 25, 2015