Acer Aspire Switch Alpha 12 Schematics

5

4

3

2

1

D D

C C

B B

A A

SYSTEM PAGE REF.

01. Block Diagram

02. SKU Table / Mount Table

03. CPU(1) _DDI / eDP
CPU(2)_LPDDR304.
CPU(3)_+VCCCORE05.

06. CPU(4)_+VCCGT

07. CPU(5)_+VDDQ/IO/SA

08. CPU(6)_CPU GND

09. CPU(7)_CFG/RSVD

16. LPDDR3(1)_MEMORY DOWN

17. LPDDR3(2)_MEMORY DOWN
LPDDR3(3)_CA/DQ Voltage18.

20. PCH(1)_SPI / LPC

21. PCH(2)_ISH / GPIO / I2C

22. PCH(3)_HDA / DMIC / SDIO

23. PCH(4)_USB / PCIE / SATA

24. PCH(5)_CLK / RTC/ CSI-2

25. PCH(6)_POWER MANAGEMENT

26. PCH(7)_POWER
PCH(9)_SPI / SMB28.
EC_IT8587E/FX30.

32. RST_Reset Circuit

36. Codec / Jack / SpK / DMIC

40. Micro SD CONN
ISH CONN41.

44. Debug CONN

45. LCM_EDP

50. THERMAL / NUT

51. SSD NGFF.
USB 3.0 Port52.

53. WLAN / WiGig / BT NGFF.
Camera 2M / 5M55.
IO CONN / POGO PIN56.
Discharge57.
DC_DC / BAT CONN60.

62. TPM

68. BYPASS EC SEQUENCE
Sensor / GMR70.

80_POWER_VCORE for U22
81_POWER_SYSTEM
82_POWER_+1.0VSUS
83_POWER_ DDR & VTT_UMA
84_POWER_1.8VSUS
88_POWER_CHARGER
89_POWER_ AC_PD_WC Input
90_POWER_DETECT
91_POWER_LOAD SWITCH
92_POWER_PROTECT
93_POWER_SIGNAL
94_POWER_FLOWCHART
95_USB_TYPE-C ANX7428
96_USB Type-C Receptacle
A01. Power Tree

5

Camera CONN
F-2M

Page 55

DMIC
KINGSTATE / KMM40301026-11DH

DMIC
KINGSTATE / KMM40301026-11DH

Page 36

Combo Jack

Speaker (CONN)
R/L 2W x2

Page 36

uSD CONN
( SDR104 )

Page 40

KeyBoard (POGO Pin)

Page 56

MIPI

I2C

SDIO

I/O DB

Battery LED
Dual Coloer (B/O)

Touch (I2C)

Power Buttom

Volume Up

Volume Down

Home Key

ALS

4

Panel (CONN)
eDPx4 (1.3)
12'' 2160x1440

Page 45

Touch Controller
Elan 5515 (CONN)

Page 45

Camera CONN
R-5M

Page 55

ISP
REALTEK / RTS5830-GR

Page 55

SPI

SPI ROM 512KB

Page 55

Audio Codec
Realtek / ALC255

Page 36

Card Reader
Realtek / RTS5229-GR

Page 40

TPM
Nuvoton / NPCT650

Page 62

Page 64

eDPx4

I2C(1)

CSI-2(0)

I2C(2)

USB2.0(7)

DMIC_CLK(0), DMIC_DAT(0)

HDA

PCIe(5)

LPC

USB2.0(4)

Docking Cable

WTB CONN

6 Pins

Skylake U

CPU

+

PCH

SPI

SPI ROM 8MB
W25Q64FVSSIQ
(MB+BIOS+EC)

USB2.0 +/-

DET 0/1

Power

3

LPDDR3

SATA(8)

6 Gb/s ( gen 3 )

PCIe(10)

PCIe(9)

USB2.0(5)

USB2.0(2)

USB3.0(2)

ISH_I2C(0)

LPC

USB3.0(3)

DDI(2)

USB2.0(3)

POGO CONN

6 Pins

LPDDR3
1600 / 1866 MHz
2Ch 4G/8G

Page 16~18

SSD CONN (M2 2280)
64 / 128 / 256 GB

Page 16~18

WiGig

WIGig / WiFi / BT

WLAN

Module Card
(M2 2230)

BT

USB3.0
USB CONN x1

EC
ITE / IT8587

SM Bus(1)

Cross Point Swtich
Analogix / ANX7428

SM Bus(0)

GPIO

GPIO

Debug CONN

EC KSI / KSO

EC KSI6 + KSI7

LPC 80 Port

Charger IC
TI / BQ24725ARGRR

Battery CONN
Smart Battery

37.6Whr

USB3.0
Type C CONN

2

AC Adapter
19V @ 2.37A

Battery 2S1P 36W

O.S Win10

Gyro+A

InvenSense/MPU-6500

Light Sensor

Capella/CM32181EA3OP

e-Compass

AKM/AK09911C

Page 70

Page 70

Page 70

Shutdown IC

GMT / G709T1UF

GMR Sensor

ALPS / HGDEDM013A

TTTiiitttllleee :::

PPPEEEGGGAAATTTRRROOONNN PPPRRROOOPPPRRRIIIEEETTTAAARRRYYY AAANNNDDD CCCOOONNNFFFIIIDDDEEENNNTTTIIIAAALLL

NNNBBBRRRDDDCCC///HHHWWW333

SSSiiizzzeee PPPrrrooo jjjeeecccttt NNNaaammmeee

HAWAIIHAWAIIHAWAII

DDD

DDDaaattteee::: SSShhheeeeeettt ooofff

1

EEEnnngggiiinnneeeeeerrr:::

Block DiagramBlock DiagramBlock Diagram

WWWiiillllllyyy___LLLiiiaaaooo

111 111000000TTThhhuuurrrsssdddaaayyy,,, MMMaaarrrccchhh 333111,,, 222000111666

RRReeevvv

000...000

HAWAII BLOCK DIAGRAM

5

4

3

2

1

Use As Signal NameEC GPIO EC GPIO Use As Signal NameUse As Signal NameEC GPIO Use As Signal NameEC GPIO

D D

SKU Table (B2 build)

C C

Mount Table

Optional

/1st_SSD

B B

/2nd_SSD

/MEM-CH1

/MEM-CH2

/E_SENSOR_HUB

/TPM

/Debug

/NON-IOAC

/USBSLP

/IOAC

/SEQS_EC

/BYPAS_EC

/ADSP

A A

5

/RTL

Mount?

V

X

V

V

V

V

V

V

V

X

X

V

V

X

SKU / Mount Table

SKU / Mount Table

SKU / Mount Table

Title :

Title :

PEGATRON PROPRIETARY AND CONFIDENTI AL

PEGATRON PROPRIETARY AND CONFIDENTI AL

PEGATRON PROPRIETARY AND CONFIDENTI AL

BG1-NB4

BG1-NB4

BG1-NB4

Size Project Name

Size Project Name

Size Project Name

C

C

C

HAWAII

HAWAII

Date: Sheet of

Date: Sheet of

4

3

2

Date: Sheet of

HAWAII

Engineer:

Engineer:

Engineer:

1

Title :

Willy_Liao

Willy_Liao

Willy_Liao

2 100Thursday, March 31, 2016

2 100Thursday, March 31, 2016

2 100Thursday, March 31, 2016

Rev

Rev

Rev

1.1

1.1

1.1

5

4

3

2

1

+VCCIO

+VCCST_CPU

+VCCSTG

D D

Remove DDI1 Port : HDMI

DDI2_TXN0[95]
DDI2_TXP0[95]
DDI2_TXN1[95]

DDI Port 2: USB_TYPE C_DP

C C

H_PECI_EC[30]

H_THRMTRIP#[32]

B B

VR_HOT#[80]

A A

+VCCIO

12

R0311
1KOhm

tx_r0402

H_PROCHOT#

5

DDI2_TXP1[95]
DDI2_TXN2[95]
DDI2_TXP2[95]
DDI2_TXN3[95]
DDI2_TXP3[95]

TP_RST[56]

1 2

R0301 24.9Ohm1%

tx_r0402

141024 follow PDG V1.0 Table 10-4
Rpu = 1K ohm 5%

1 2

R0314 499Ohm tx_r04021%

12

D

S

2 3

Rs = 500 ohm 5%

TP_INT[56]

R0341
0Ohm

tx_r0402_0ohm

Q0301
NX7002AK

G

1

12

R0312
1KOhm

tx_r0402

5%

H_PROCHOT# H_PROCHOT#_R

1 2

R0320 0Ohm

@

tx_r0402_0ohm

SKYLAKE-U symbol ReV0.53 #545316 / Ballout_Rev0_71 #543787 / PEGA local PN is 4201-0062000

U0301A

E55

DDI1_TXN[0]

F55

DDI1_TXP[0]

E58

DDI1_TXN[1]

F58

DDI1_TXP[1]

F53

DDI1_TXN[2]

G53

DDI1_TXP[2]

F56

DDI1_TXN[3]

G56

DDI1_TXP[3]

DDPC_CTRLCLK
DDPC_CTRLDATA

TP_RST

DP_COMP

R0315 43Ohm tx_r0402

SP0301

+3VS

12

R9617
10KOhm

tx_r0402

R0316 49.9Ohm tx_r04021%
R0317 49.9Ohm tx_r04021%
R0318 49.9Ohm tx_r04021%
R0319 49.9Ohm tx_r04021%

C50

DDI2_TXN[0]

D50

DDI2_TXP[0]

C52

DDI2_TXN[1]

D52

DDI2_TXP[1]

A50

DDI2_TXN[2]

B50

DDI2_TXP[2]

D51

DDI2_TXN[3]

C51

DDI2_TXP[3]

L13

GPP_E18/DDPB_CTRLCLK

L12

GPP_E19/DDPB_CTRLDATA

N7

GPP_E20/DDPC_CTRLCLK

N8

GPP_E21/DDPC_CTRLDATA

N11

GPP_E22

N12

GPP_E23

E52

eDP_RCOMP

940432

01T010000015

Closeer EC

1 2

1 2

@

1 2
1 2
1 2
1 2

DDI

DISPLAY SIDEBANDS

+VCCST_CPU+VCCSTG+VCCST_CPU

R0313

49.9Ohm

tx_r0402

1%

@

1 2

TP_CATERR#_R
H_PECI

H_THRMTRIP#_R

1

SKTOCC#

T0306

Remove XDP_BPM#

1

CPU_GP0

T0311

TP_INT

1

CPU_GP2

T0313

1

CPU_GP3

T0314

CPU_POPIRCOMP
PCH_POPIRCOMP
EDRAM_OPIO_RCOMP
EOPIO_RCOMP

EDP

R1.1

R0341由EC control
(depends on under-shoot measurement result),預預0ohm

觸觸觸觸觸觸觸觸觸觸觸觸觸

THRO_CPU [30]

4

70-200 ohm

觸是是是是

EDP_TXN[0]
EDP_TXP[0]
EDP_TXN[1]
EDP_TXP[1]
EDP_TXN[2]
EDP_TXP[2]
EDP_TXN[3]
EDP_TXP[3]

EDP_AUXN
EDP_AUXP

EDP_DISP_UTIL

DDI1_AUXN
DDI1_AUXP
DDI2_AUXN
DDI2_AUXP

RSVD_1
RSVD_2

GPP_E13/DDPB_HPD0
GPP_E14/DDPC_HPD1
GPP_E15/DDPD_HPD2
GPP_E16/DDPE_HPD3

GPP_E17/EDP_HPD

eDP_BKLTEN

eDP_BKLTCTL

eDP_VDDEN

U0301D

D63

CATERR#

A54

PECI

C65

PROCHOT#

C63

THERMTRIP#

A65

SKTOCC#

C55

BPM#[0]

D55

BPM#[1]

B54

BPM#[2]

C56

BPM#[3]

A6

GPP_E3/CPU_GP0

A7

GPP_E7/CPU_GP1

BA5

GPP_B3/CPU_GP2

AY5

GPP_B4/CPU_GP3

AT16

PROC_POPIRCOMP

AU16

PCH_OPIRCOMP

H66

OPCE_RCOMP

H65

OPC_RCOMP

940432

01T010000015

C47
C46
D46
C45
A45
B45
A47
B47

E45
F45

B52

G50
F50
E48
F48
G46
F46

L9

DDI1_HPD

L7

DDI2_HPD

L6

EXT_SMI#_R EXT_SMI#

N9

EXT_SCI#_R EXT_SCI#

L10

eDP_HPD

R12
R11
U13

CPU MISC

No Connect
543016 page 824

1 2

R0302 0Ohm

1 2

R0303 0Ohm

JTAG

PROC_TCK

PROC_TDI
PROC_TDO
PROC_TMS

PROC_TRST#

PCH_JTAG_TCK

PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS

PCH_TRST#

JTAGX

3

tx_r0402
tx_r0402

B61

XDP_TCLK

D60

XDP_TDI_CPU

A61

XDP_TDO_CPU

C60

XDP_TMS_CPU

B59

XDP_TRST_CPU_N

B56

PCH_JTAG_TCLK

D59

PCH_JTAG_TDI

A56

PCH_JTAG_TDO

C59

PCH_JTAG_TMS

C61

PCH_TRST_CPU_N XDP_TCLKXDP_TCLK_JTAGX

A59

XDP_TCLK_JTAGX

EDP_TXN0 [45]
EDP_TXP0 [45]
EDP_TXN1 [45]
EDP_TXP1 [45]
EDP_TXN2 [45]
EDP_TXP2 [45]
EDP_TXN3 [45]
EDP_TXP3 [45]

EDP_AUXN [45]

EDP_AUXP [45]

eDP x 4

-- WQHD 4 Lane

-- FHD 2 Lane

AUX For eDP

DDI2_AUXN [95]
DDI2_AUXP [95]

DDI2_HPD [95]
EXT_SMI# [30,44]
EXT_SCI# [30]
eDP_HPD [45]

LCD_BKLTEN_PCH [21,45]

LCD_BL_PWM_PCH [45]

EDP_VDD_EN [45]

+3VS +3VS

12

R0344
10KOhm

@

eDP_HPD

1

tx_r0402

12

R0346
100KOHM

tx_r0402

PCH_JTAG_TMS XDP_TMS_CPU

T0315

2

+3VS

DDPC_CTRLDATA

DDPC_CTRLCLK

EXT_SCI#

EXT_SMI#

+3VS

12

R0343
10KOhm

@

DDI1_HPD

tx_r0402

12

R0342
20KOhm

@

tx_r0402

XDP Less Default Mount

XDP_TDO_CPUPCH_JTAG_TDO

R0323 51Ohm

tx_r0402

XDP_TRST_CPU_NPCH_TRST_CPU_N

XDP_TDI_CPUPCH_JTAG_TDI

R0324 51Ohm

tx_r0402

XDP Less Default Mount

+VCCIO [7,9,91]

+VCCST_CPU [5,7,9,25,32]

+VCCSTG [5,7]

+3VS [4,20,21,22,23,24,30,32,36,40,41,44,45,50,51,53,55,56,57,62,70,91, 92]

+3VS

1 2

R0305 2.2kOHM

tx_r0402

1 2

R0340 2.2kOHM

tx_r0402

1 2

R0307 10KOHM

tx_r0402

1 2

R0308 10KOHM

tx_r0402

DDI2_HPD

R0337
100KOHM

tx_r0402

12

12

@

DDPB_CTRLDATA
DDPC_CTRLDATA
DDPD_CTRLDATA

- Internal weak pull down 20k ohm

- 0 : port is not detected
1 : port is deteccted

+3VS

12

R0345
10KOhm

tx_r0402

12

DDPB_HPD0
DDPC_HPD1
DP: 100Kohm pull down on PCH Side
HDMI: 20Kohm pull down

+VCCSTG

1

T0316

1

T0317

1

T0318

Modify to XDP less

PEGATRON PROPRIETARY AND CONFIDENTI AL

PEGATRON PROPRIETARY AND CONFIDENTI AL

PEGATRON PROPRIETARY AND CONFIDENTI AL

Size Project Name

Size Project Name

Size Project Name

C

C

C

Date: Sheet of

Date: Sheet of

Date: Sheet of

HAWAII

HAWAII

HAWAII

Engineer:

Engineer:

Engineer:

1

Title :

Title :

Title :

CPU(1)_DDI/eDP

CPU(1)_DDI/eDP

CPU(1)_DDI/eDP

Willy_Liao

Willy_Liao

Willy_Liao

3 100Thursday, March 31, 2016

3 100Thursday, March 31, 2016

3 100Thursday, March 31, 2016

Rev

Rev

Rev

0.0

0.0

0.0

5

T25S used Non-Interleave

U0301B

D D

NIL Channel A[0..15]NIL Channel A[32..47]NIL Channel B[0..15]NIL Channel B[32..47]

C C

M_A_D0
M_A_D1
M_A_D2
M_A_D3
M_A_D4
M_A_D5
M_A_D6
M_A_D7
M_A_D8
M_A_D9
M_A_D10
M_A_D11
M_A_D12
M_A_D13
M_A_D14
M_A_D15
M_A_D32
M_A_D33
M_A_D34
M_A_D35
M_A_D36
M_A_D37
M_A_D38
M_A_D39
M_A_D40
M_A_D41
M_A_D42
M_A_D43
M_A_D44
M_A_D45
M_A_D46
M_A_D47
M_B_D0
M_B_D1
M_B_D2
M_B_D3
M_B_D4
M_B_D5
M_B_D6
M_B_D7
M_B_D8
M_B_D9
M_B_D10
M_B_D11
M_B_D12
M_B_D13
M_B_D14
M_B_D15
M_B_D32
M_B_D33
M_B_D34
M_B_D35
M_B_D36
M_B_D37
M_B_D38
M_B_D39
M_B_D40
M_B_D41
M_B_D42
M_B_D43
M_B_D44
M_B_D45
M_B_D46
M_B_D47

AL71

AL68
AN68
AN69

AL70

AL69
AN70
AN71
AR70
AR68
AU71
AU68
AR71
AR69
AU70
AU69
BB65

AW65
AW63

AY63
BA65
AY65
BA63
BB63
BA61

AW61

BB59

AW59

BB61
AY61
BA59
AY59
AY39

AW39

AY37

AW37

BB39
BA39
BA37
BB37
AY35

AW35

AY33

AW33

BB35
BA35
BA33
BB33
AY31

AW31

AY29

AW29

BB31
BA31
BA29
BB29
AY27

AW27

AY25

AW25

BB27
BA27
BA25
BB25

IL Channel A[0..63]

DDR0_DQ[0]
DDR0_DQ[1]
DDR0_DQ[2]
DDR0_DQ[3]
DDR0_DQ[4]
DDR0_DQ[5]
DDR0_DQ[6]
DDR0_DQ[7]
DDR0_DQ[8]
DDR0_DQ[9]
DDR0_DQ[10]
DDR0_DQ[11]
DDR0_DQ[12]
DDR0_DQ[13]
DDR0_DQ[14]
DDR0_DQ[15]
DDR0_DQ[16]/DDR0_DQ[32]
DDR0_DQ[17]/DDR0_DQ[33]
DDR0_DQ[18]/DDR0_DQ[34]
DDR0_DQ[19]/DDR0_DQ[35]
DDR0_DQ[20]/DDR0_DQ[36]
DDR0_DQ[21]/DDR0_DQ[37]
DDR0_DQ[22]/DDR0_DQ[38]
DDR0_DQ[23]/DDR0_DQ[39]
DDR0_DQ[24]/DDR0_DQ[40]
DDR0_DQ[25]/DDR0_DQ[41]
DDR0_DQ[26]/DDR0_DQ[42]
DDR0_DQ[27]/DDR0_DQ[43]
DDR0_DQ[28]/DDR0_DQ[44]
DDR0_DQ[29]/DDR0_DQ[45]
DDR0_DQ[30]/DDR0_DQ[46]
DDR0_DQ[31]/DDR0_DQ[47]
DDR0_DQ[32]/DDR1_DQ[0]
DDR0_DQ[33]/DDR1_DQ[1]
DDR0_DQ[34]/DDR1_DQ[2]
DDR0_DQ[35]/DDR1_DQ[3]
DDR0_DQ[36]/DDR1_DQ[4]
DDR0_DQ[37]/DDR1_DQ[5]
DDR0_DQ[38]/DDR1_DQ[6]
DDR0_DQ[39]/DDR1_DQ[7]
DDR0_DQ[40]/DDR1_DQ[8]
DDR0_DQ[41]/DDR1_DQ[9]
DDR0_DQ[42]/DDR1_DQ[10]
DDR0_DQ[43]/DDR1_DQ[11]
DDR0_DQ[44]/DDR1_DQ[12]
DDR0_DQ[45]/DDR1_DQ[13]
DDR0_DQ[46]/DDR1_DQ[14]
DDR0_DQ[47]/DDR1_DQ[15]
DDR0_DQ[48]/DDR1_DQ[32]
DDR0_DQ[49]/DDR1_DQ[33]
DDR0_DQ[50]/DDR1_DQ[34]
DDR0_DQ[51]/DDR1_DQ[35]
DDR0_DQ[52]/DDR1_DQ[36]
DDR0_DQ[53]/DDR1_DQ[37]
DDR0_DQ[54]/DDR1_DQ[38]
DDR0_DQ[55]/DDR1_DQ[39]
DDR0_DQ[56]/DDR1_DQ[40]
DDR0_DQ[57]/DDR1_DQ[41]
DDR0_DQ[58]/DDR1_DQ[42]
DDR0_DQ[59]/DDR1_DQ[43]
DDR0_DQ[60]/DDR1_DQ[44]
DDR0_DQ[61]/DDR1_DQ[45]
DDR0_DQ[62]/DDR1_DQ[46]
DDR0_DQ[63]/DDR1_DQ[47]

940432

01T010000015

M_A_D[63:0][16] M_B_D[63:0][17]

NIL Channel A[0..15]
NIL Channel A[32..47]

DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5]
DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9]
DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6]
DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8]
DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]

DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0]
DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12]
DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]

DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT#
DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]

DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]

DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]

DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]

DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]

DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]

DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]

DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]

DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]

DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1]
DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]

NIL Channel B[0..15]
NIL Channel B[32..47]

IL Channel A DQS[0..7]

NIL Channel A
DQS[0,1,4,5]

NIL Channel B
DQS[0,1,4,5]

DDR CH - A

DDR0_DQSN[2]/DDR0_DQSN[4]
DDR0_DQSP[2]/DDR0_DQSP[4]
DDR0_DQSN[3]/DDR0_DQSN[5]
DDR0_DQSP[3]/DDR0_DQSP[5]
DDR0_DQSN[4]/DDR1_DQSN[0]
DDR0_DQSP[4]/DDR1_DQSP[0]
DDR0_DQSN[5]/DDR1_DQSN[1]
DDR0_DQSP[5]/DDR1_DQSP[1]
DDR0_DQSN[6]/DDR1_DQSN[4]
DDR0_DQSP[6]/DDR1_DQSP[4]
DDR0_DQSN[7]/DDR1_DQSN[5]
DDR0_DQSP[7]/DDR1_DQSP[5]

4

DDR0_CKN[0]
DDR0_CKP[0]
DDR0_CKN[1]
DDR0_CKP[1]

DDR0_CKE[0]
DDR0_CKE[1]
DDR0_CKE[2]
DDR0_CKE[3]

DDR0_CS#[0]
DDR0_CS#[1]
DDR0_ODT[0]
DDR0_ODT[1]

DDR0_MA[3]
DDR0_MA[4]

DDR0_DQSN[0]
DDR0_DQSP[0]
DDR0_DQSN[1]
DDR0_DQSP[1]

DDR0_ALERT#

DDR0_PAR

DDR_VREF_CA
DDR0_VREF_DQ
DDR1_VREF_DQ

DDR_VTT_CNTL

AU53
AT53
AU55
AT55

BA56
BB56
AW56
AY56

AU45
AU43
AT45
AT43

BA51
BB54
BA52
AY52
AW52
AY55
AW54
BA54
BA55
AY54

AU46
AU48
AT46
AU50
AU52
AY51
AT48
AT50
BB50
AY50
BA50
BB52

AM70
AM69
AT69
AT70
BA64
AY64
AY60
BA60
BA38
AY38
AY34
BA34
BA30
AY30
AY26
BA26

AW50
AT52

AY67
AY68
BA67

AW67

M_A_CAA[9:0] [16]

M_A_CAB[9:0] [16]

M_A_DQS#[7:0] [16]

M_A_DQS[7:0] [16]

M_A_DIM0_ODT0

M_A_CAA0
M_A_CAA1
M_A_CAA2
M_A_CAA3
M_A_CAA4
M_A_CAA5
M_A_CAA6
M_A_CAA7
M_A_CAA8
M_A_CAA9

M_A_CAB0
M_A_CAB1
M_A_CAB2
M_A_CAB3
M_A_CAB4
M_A_CAB5
M_A_CAB6
M_A_CAB7
M_A_CAB8
M_A_CAB9

M_A_DQS#0
M_A_DQS0
M_A_DQS#1
M_A_DQS1
M_A_DQS#4
M_A_DQS4
M_A_DQS#5
M_A_DQS5
M_B_DQS#0
M_B_DQS0
M_B_DQS#1
M_B_DQS1
M_B_DQS#4
M_B_DQS4
M_B_DQS#5
M_B_DQS5

DDR_PG_CTRL_S

M_A_DIM0_CLK#0 [16]
M_A_DIM0_CLK0 [16]
M_A_DIM0_CLK#1 [16]
M_A_DIM0_CLK1 [16]

M_A_DIM0_CKE0 [16]
M_A_DIM0_CKE1 [16]
M_A_DIM0_CKE2 [16]
M_A_DIM0_CKE3 [16]

M_A_DIM0_CS#0 [16]
M_A_DIM0_CS#1 [16]
M_A_DIM0_ODT0 [16]

DIMM_VREF_CA [18]
DIMM0_VREF_DQ [18]
DIMM1_VREF_DQ [18]

3

U0301C

IL Channel B[0..63]

AF65

M_A_D16
M_A_D17
M_A_D18
M_A_D19

M_A_D20
M_A_D21
M_A_D22
M_A_D23
M_A_D24
M_A_D25
M_A_D26
M_A_D27
M_A_D28
M_A_D29
M_A_D30

NIL Channel A[16..31]NIL Channel A[48..63]NIL Channel B[16..31]NIL Channel B[48..63]

M_A_D31
M_A_D48
M_A_D49
M_A_D50
M_A_D51
M_A_D52
M_A_D53
M_A_D54
M_A_D55
M_A_D56
M_A_D57
M_A_D58
M_A_D59
M_A_D60
M_A_D61
M_A_D62
M_A_D63

M_B_D16

M_B_D17

M_B_D18

M_B_D19

M_B_D20

M_B_D21

M_B_D22

M_B_D23

M_B_D24

M_B_D25

M_B_D26

M_B_D27

M_B_D28

M_B_D29

M_B_D30

M_B_D31

M_B_D48

M_B_D49

M_B_D50

M_B_D51

M_B_D52

M_B_D53

M_B_D54

M_B_D55

M_B_D56

M_B_D57

M_B_D58

M_B_D59

M_B_D60

M_B_D61

M_B_D62

M_B_D63

DDR1_DQ[0]/DDR0_DQ[16]

AF64

DDR1_DQ[1]/DDR0_DQ[17]

AK65

DDR1_DQ[2]/DDR0_DQ[18]

AK64

DDR1_DQ[3]/DDR0_DQ[19]

AF66

DDR1_DQ[4]/DDR0_DQ[20]

AF67

DDR1_DQ[5]/DDR0_DQ[21]

AK67

DDR1_DQ[6]/DDR0_DQ[22]

AK66

DDR1_DQ[7]/DDR0_DQ[23]

AF70

DDR1_DQ[8]/DDR0_DQ[24]

AF68

DDR1_DQ[9]/DDR0_DQ[25]

AH71

DDR1_DQ[10]/DDR0_DQ[26]

AH68

DDR1_DQ[11]/DDR0_DQ[27]

AF71

DDR1_DQ[12]/DDR0_DQ[28]

AF69

DDR1_DQ[13]/DDR0_DQ[29]

AH70

DDR1_DQ[14]/DDR0_DQ[30]

AH69

DDR1_DQ[15]/DDR0_DQ[31]

AT66

DDR1_DQ[16]/DDR0_DQ[48]

AU66

DDR1_DQ[17]/DDR0_DQ[49]

AP65

DDR1_DQ[18]/DDR0_DQ[50]

AN65

DDR1_DQ[19]/DDR0_DQ[51]

AN66

DDR1_DQ[20]/DDR0_DQ[52]

AP66

DDR1_DQ[21]/DDR0_DQ[53]

AT65

DDR1_DQ[22]/DDR0_DQ[54]

AU65

DDR1_DQ[23]/DDR0_DQ[55]

AT61

DDR1_DQ[24]/DDR0_DQ[56]

AU61

DDR1_DQ[25]/DDR0_DQ[57]

AP60

DDR1_DQ[26]/DDR0_DQ[58]

AN60

DDR1_DQ[27]/DDR0_DQ[59]

AN61

DDR1_DQ[28]/DDR0_DQ[60]

AP61

DDR1_DQ[29]/DDR0_DQ[61]

AT60

DDR1_DQ[30]/DDR0_DQ[62]

AU60

DDR1_DQ[31]/DDR0_DQ[63]

AU40

DDR1_DQ[32]/DDR1_DQ[16]

AT40

DDR1_DQ[33]/DDR1_DQ[17]

AT37

DDR1_DQ[34]/DDR1_DQ[18]

AU37

DDR1_DQ[35]/DDR1_DQ[19]

AR40

DDR1_DQ[36]/DDR1_DQ[20]

AP40

DDR1_DQ[37]/DDR1_DQ[21]

AP37

DDR1_DQ[38]/DDR1_DQ[22]

AR37

DDR1_DQ[39]/DDR1_DQ[23]

AT33

DDR1_DQ[40]/DDR1_DQ[24]

AU33

DDR1_DQ[41]/DDR1_DQ[25]

AU30

DDR1_DQ[42]/DDR1_DQ[26]

AT30

DDR1_DQ[43]/DDR1_DQ[27]

AR33

DDR1_DQ[44]/DDR1_DQ[28]

AP33

DDR1_DQ[45]/DDR1_DQ[29]

AR30

DDR1_DQ[46]/DDR1_DQ[30]

AP30

DDR1_DQ[47]/DDR1_DQ[31]

AU27

DDR1_DQ[48]

AT27

DDR1_DQ[49]

AT25

DDR1_DQ[50]

AU25

DDR1_DQ[51]

AP27

DDR1_DQ[52]

AN27

DDR1_DQ[53]

AN25

DDR1_DQ[54]

AP25

DDR1_DQ[55]

AT22

DDR1_DQ[56]

AU22

DDR1_DQ[57]

AU21

DDR1_DQ[58]

AT21

DDR1_DQ[59]

AN22

DDR1_DQ[60]

AP22

DDR1_DQ[61]

AP21

DDR1_DQ[62]

AN21

DDR1_DQ[63]

940432

01T010000015

SKL_ULT

NIL Channel A[16..31]
NIL Channel A[48..63]

NIL Channel B[16..31]
NIL Channel B[48..63]

IL Channel B DQS[0..7]

NIL Channel A
DQS[2,3,6,7]

NIL Channel B
DQS[2,3,6,7]

DDR CH - B

2

M_B_DQS#[7:0] [17]

M_B_DQS[7:0] [17]

M_B_CAA[9:0] [17]

M_B_CAB[9:0] [17]

DDR1_CKN[0]
DDR1_CKN[1]
DDR1_CKP[0]
DDR1_CKP[1]

DDR1_CKE[0]
DDR1_CKE[1]
DDR1_CKE[2]
DDR1_CKE[3]

DDR1_CS#[0]
DDR1_CS#[1]
DDR1_ODT[0]

DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5]
DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9]
DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6]
DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8]
DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]

DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0]
DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12]
DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]

DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT#
DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]

DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]

DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]

DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]

DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]

DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]

DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]

DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1]
DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]

DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1]
DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]

DDR1_ODT[1]

DDR1_MA[3]

DDR1_DQSN[0]/DDR0_DQSN[2]
DDR1_DQSP[0]/DDR0_DQSP[2]
DDR1_DQSN[1]/DDR0_DQSN[3]
DDR1_DQSP[1]/DDR0_DQSP[3]
DDR1_DQSN[2]/DDR0_DQSN[6]
DDR1_DQSP[2]/DDR0_DQSP[6]
DDR1_DQSN[3]/DDR0_DQSN[7]
DDR1_DQSP[3]/DDR0_DQSP[7]
DDR1_DQSN[4]/DDR1_DQSN[2]
DDR1_DQSP[4]/DDR1_DQSP[2]
DDR1_DQSN[5]/DDR1_DQSN[3]
DDR1_DQSP[5]/DDR1_DQSP[3]

DDR1_MA[4]

DDR1_DQSN[6]
DDR1_DQSP[6]
DDR1_DQSN[7]
DDR1_DQSP[7]

DDR1_ALERT#

DDR1_PAR
DRAM_RESET#
DDR_RCOMP[0]
DDR_RCOMP[1]
DDR_RCOMP[2]

AN45
AN46
AP45
AP46

AN56
AP55
AN55
AP53

BB42
AY42
BA42
AW42

AY48
AP50
BA48
BB48
AP48
AP52
AN50
AN48
AN53
AN52

BA43
AY43
AY44
AW44
BB44
AY47
BA44
AW46
AY46
BA46
BB46
BA47

AH66
AH65
AG69
AG70
AR66
AR65
AR61
AR60
AT38
AR38
AT32
AR32
AR25
AR27
AR22
AR21

AN43
AP43
AT13
AR18
AT18
AU18

+1.2V

+3VSUS

+3VS

M_B_DIM0_ODT0

M_B_CAA0
M_B_CAA1
M_B_CAA2
M_B_CAA3
M_B_CAA4
M_B_CAA5
M_B_CAA6
M_B_CAA7
M_B_CAA8
M_B_CAA9

M_B_CAB0
M_B_CAB1
M_B_CAB2
M_B_CAB3
M_B_CAB4
M_B_CAB5
M_B_CAB6
M_B_CAB7
M_B_CAB8
M_B_CAB9

M_A_DQS#2
M_A_DQS2
M_A_DQS#3
M_A_DQS3
M_A_DQS#6
M_A_DQS6
M_A_DQS#7
M_A_DQS7
M_B_DQS#2
M_B_DQS2
M_B_DQS#3
M_B_DQS3
M_B_DQS#6
M_B_DQS6
M_B_DQS#7
M_B_DQS7

DRAM_RESET#
SM_RCOMP_0

R0402 200Ohm1% tx_r0402

SM_RCOMP_1

R0403 80.6Ohm1% tx_r0402

SM_RCOMP_2

R0404 162Ohm1% tx_r0402

+1.2V [7,16,17,18,83]

+3VSUS [24,25,26,28,30,51,53,62, 68,81,84,92,95]

+3VS [3,20,21,22,23,24,30,32,36,40,41,44,45,50,51,53,55,56,57,62,70,91,92]

M_B_DIM0_CLK#0 [17]
M_B_DIM0_CLK#1 [17]
M_B_DIM0_CLK0 [17]
M_B_DIM0_CLK1 [17]

M_B_DIM0_CKE0 [17]
M_B_DIM0_CKE1 [17]
M_B_DIM0_CKE2 [17]
M_B_DIM0_CKE3 [17]

M_B_DIM0_CS#0 [17]
M_B_DIM0_CS#1 [17]
M_B_DIM0_ODT0 [17]

Controls reset to the memory subsystems,
and is used on DDR3L, DDR4
(not applicable to LPDDR3).

1 2
1 2
1 2

1

1

T0401

B B

12

C0402
10PF/50V

tx_c0402

+3VS+1.2V +3VSUS

12

R0412
220KOhm

tx_r0402

12

12

R0407
220KOhm

tx_r0402

@

R0411
2MOhm

tx_r0402

@

DDR_PG_CTRL [83]

DDR_VTT_CNTL to VTT
power ready < 35us (tCPU18)

2

Symbol U0301 B

BYTE 0
BYTE 1
BYTE 2
BYTE 3
BYTE 4
BYTE 5
BYTE 6
BYTE 7

A A

ChannelA DQ[0..63]
DQS/DQS#[0..7]

5

Non-interleavedinterleaved(Symbol default)

ChannelA DQ[0..15]
DQS/DQS#[0,1]

ChannelADQ[32..47]
DQS/DQS#[4,5]

ChannelB DQ[0..15]
DQS/DQS#[0,1]

ChannelB DQ[32..47]
DQS/DQS#[4,5]

12

C0401

0.1UF/16V

U0401

1

NC

2

A

3 4

12

R0406
10KOhm@

tx_r0402

4

GND

SN74AUP1G07DCKR

06T030000021

5

VCC

Y

3

tx_c0402

@

RF reserve

Symbol U0301 C

BYTE 0
BYTE 1
BYTE 2
BYTE 3
BYTE 4
BYTE 5
BYTE 6
BYTE 7

ChannelB DQ[0..63]
DQS/DQS#[0..7]

PEGATRON PROPRIETARY AND CONFIDENTI AL

PEGATRON PROPRIETARY AND CONFIDENTI AL

PEGATRON PROPRIETARY AND CONFIDENTI AL

BG1-NB4

BG1-NB4

BG1-NB4

Size Project Name

Size Project Name

Size Project Name

C

C

C

HAWAII

HAWAII

Date: Sheet of

Date: Sheet of

Date: Sheet of

HAWAII

Non-interleavedinterleaved(Symbol default)

ChannelA DQ[16..31]
DQS/DQS#[2,3]

ChannelADQ[48..63]
DQS/DQS#[6,7]

ChannelB DQ[16..31]
DQS/DQS#[2,3]

ChannelB DQ[48..63]
DQS/DQS#[6,7]

Title :

Title :

Title :

Engineer:

Engineer:

Engineer:

1

CPU(2)_DDR3L

CPU(2)_DDR3L

CPU(2)_DDR3L

Willy_Liao

Willy_Liao

Willy_Liao

4 100Thursday, March 31, 2016

4 100Thursday, March 31, 2016

4 100Thursday, March 31, 2016

Rev

Rev

Rev

0.0

0.0

0.0

5

4

3

2

1

D D

+VCORE +VCORE

12

C0506
10PF/50V

tx_c0201

RF reserve

SKL 2+2, +V1.8VS_EDRAM / +V_EDRAM_VR / +V_EOPIO_VR

C C

From Intel, SKL-U 2+2 reserve these pins PD to GND

Remove
R0528/R0529/R0530/R0531/R0532
R0533/R0534/R0535
Resistor change to Test Point

Delete for power layout limitation

T0510

T0511

T0512

T0513
T0514

T0515

T0516
T0517

1

1

1

1
1

1

1
1

RSVD NC

AK33
AK35
AK37
AK38
AK40

AL33
AL37

AL40
AM32
AM33
AM35
AM37
AM38

AK32

AB62

AC63
AE63

AE62
AG62

AL63

AJ62

A30
A34
A39
A44

G30

K32

P62
V62

H63

G61

U0301L

VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18

RSVD_3

RSVD_4

VCCOPC_1
VCCOPC_2
VCCOPC_3

VCC_OPC_1P8_1

VCC_OPC_1P8_2

VCCOPC_SENSE
VSSOPC_SENSE

VCCEOPIO_1
VCCEOPIO_2

VCCEOPIO_SENSE
VSSEOPIO_SENSE

940432

01T010000015

CPU POWER 1 OF 4

VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35
VCC_36

VCC_SENSE
VSS_SENSE

VIDALERT#

VIDSCK

VIDSOUT

VCCSTG

G32
G33
G35
G37
G38
G40
G42
J30
J33
J37
J40
K33
K35
K37
K38
K40
K42
K43

E32
E33

B63
A63
D64

G20

C0507
10PF/50V

tx_c0201

RF reserve

Pull H/L near CPU side

VIDALERT#
VIDSCK
VIDSOUT

+VCCFUSEPRG

NB_R0402_20MIL_SMALL

+VCORE

12

1 2

R0536 100Ohm

1%

tx_r0402

R0537 100Ohm

tx_r0402

VCORE_VCCSENSE [80]

VCORE_VSSSENSE [80]

1 2

1%

1 2

R0517 220Ohm1% tx_r0402

1 2

R0518 0Ohm t x_r0402_0ohm

1 2

R0519 0Ohm t x_r0402_0ohm

1 2

SP0505

@

+VCORE

+VCCSTG

CPU side VR side

+VCCST_CPU

12

+VCCST_CPU

12

R0520
56Ohm

tx_r0402

1%

R0521
100Ohm

tx_r0402

1%

+VCCSTG

+VCCST_CPU

VIDALERT#_R
VIDSCK_R

VIDSOUT_R

+VCCSTG [3,7]+VCORE [80]

+VCCST_CPU [3,7,9,25,32]

+VCCST_CPU

12

R0522

45.3Ohm

tx_r0402

1%

+VCCST_CPU

12

R0523
100Ohm

tx_r0402

1%

1 2

R0524 0Ohm

tx_r0402_0ohm

12

C0505
1UF/6.3V

tx_c0402

1 2

R0525 51Ohm1%

tx_r0402

1 2

R0526 10Ohm1%

tx_r0402

VR_SVID_ALERT# [80]

VR_SVID_CLK [80]

VR_SVID_DATA [80]

B B

A A

CPU(3)_+VCCCORE

CPU(3)_+VCCCORE

CPU(3)_+VCCCORE

Title :

Title :

PEGATRON PROPRIETARY AND CONFIDENTI AL

PEGATRON PROPRIETARY AND CONFIDENTI AL

PEGATRON PROPRIETARY AND CONFIDENTI AL

Size Project Name

Size Project Name

Size Project Name

C

C

C

HAWAII

HAWAII

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

HAWAII

Engineer:

Engineer:

Engineer:

1

Title :

Willy_Liao

Willy_Liao

Willy_Liao

5 100Thursday, March 31, 2016

5 100Thursday, March 31, 2016

5 100Thursday, March 31, 2016

Rev

Rev

Rev

0.0

0.0

0.0

5

4

3

2

1

+VCCGT

VccGTx is for 2+3e.

From Intel, SKL-U 2+2 reserve these pins PD to GND

2015/01/20
Remove R0601-R0608
Resistor change to Test Point

Delete for power layout limitation

N70
N71
R63
R64
R65
R66
R67
R68
R69
R70
R71
T62
U65
U68
U71
W63
W64
W65
W66
W67
W68
W69
W70
W71
Y62

AK42
AK43
AK45
AK46
AK48
AK50
AK52
AK53
AK55
AK56
AK58
AK60
AK70
AL43
AL46
AL50
AL53
AL56
AL60
AM48
AM50
AM52
AM53
AM56
AM58
AU58
AU63
BB57
BB66

AK62
AL61

+VCCGT

C0600
10PF/50V

tx_c0201

RF reserve

12

1

T0601

1

T0602

1

T0603

1

T0604

1

T0605

1

T0606

1

T0607

1

T0608

+VCCGT

D D

12

C0601
10PF/50V

tx_c0201

RF reserve

C C

+VCCGT

R0609
100Ohm

tx_r0402

1%

1 2

VCCGT_VCCSENSE[80]

VCCGT_VSSSENSE[80]

Pull H/L near CPU side

R0610
100Ohm

tx_r0402

1%

1 2

Pull H/L near CPU side

AA63
AA64
AA66
AA67
AA69
AA70
AA71
AC64
AC65
AC66
AC67
AC68
AC69
AC70
AC71

A48
A53
A58
A62
A66

J43
J45
J46
J48
J50
J52
J53
J55
J56
J58
J60
K48
K50
K52
K53
K55
K56
K58
K60
L62
L63
L64
L65
L66
L67
L68
L69
L70
L71
M62
N63
N64
N66
N67
N69

J70
J69

U0301M

CPU POWER 2 OF 4

VCCGT_1
VCCGT_2
VCCGT_3
VCCGT_4
VCCGT_5
VCCGT_6
VCCGT_7
VCCGT_8
VCCGT_9
VCCGT_10
VCCGT_11
VCCGT_12
VCCGT_13
VCCGT_14
VCCGT_15
VCCGT_16
VCCGT_17
VCCGT_18
VCCGT_19
VCCGT_20
VCCGT_21
VCCGT_22
VCCGT_23
VCCGT_24
VCCGT_25
VCCGT_26
VCCGT_27
VCCGT_28
VCCGT_29
VCCGT_30
VCCGT_31
VCCGT_32
VCCGT_33
VCCGT_34
VCCGT_35
VCCGT_36
VCCGT_37
VCCGT_38
VCCGT_39
VCCGT_40
VCCGT_41
VCCGT_42
VCCGT_43
VCCGT_44
VCCGT_45
VCCGT_46
VCCGT_47
VCCGT_48
VCCGT_49
VCCGT_50
VCCGT_51
VCCGT_52
VCCGT_53
VCCGT_54
VCCGT_55

VCCGT_SENSE
VSSGT_SENSE

940432

01T010000015

VCCGT_56
VCCGT_57
VCCGT_58
VCCGT_59
VCCGT_60
VCCGT_61
VCCGT_62
VCCGT_63
VCCGT_64
VCCGT_65
VCCGT_66
VCCGT_67
VCCGT_68
VCCGT_69
VCCGT_70
VCCGT_71
VCCGT_72
VCCGT_73
VCCGT_74
VCCGT_75
VCCGT_76
VCCGT_77
VCCGT_78
VCCGT_79
VCCGT_80

VccGTx_1
VccGTx_2
VccGTx_3
VccGTx_4
VccGTx_5
VccGTx_6
VccGTx_7
VccGTx_8

VccGTx_9
VccGTx_10
VccGTx_11
VccGTx_12
VccGTx_13
VccGTx_14
VccGTx_15
VccGTx_16
VccGTx_17
VccGTx_18
VccGTx_19
VccGTx_20
VccGTx_21
VccGTx_22
VccGTx_23
VccGTx_24
VccGTx_25
VccGTx_26
VccGTx_27
VccGTx_28
VccGTx_29

VCCGTx_SENSE
VSSGTx_SENSE

+VCCGT [80]

B B

A A

CPU(4)_+VCCGT

CPU(4)_+VCCGT

CPU(4)_+VCCGT

Title :

Title :

PEGATRON PROPRIETARY AND CONFIDENTI AL

PEGATRON PROPRIETARY AND CONFIDENTI AL

PEGATRON PROPRIETARY AND CONFIDENTI AL

Size Project Name

Size Project Name

Size Project Name

C

C

C

HAWAII

HAWAII

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

HAWAII

Engineer:

Engineer:

Engineer:

1

Title :

Willy_Liao

Willy_Liao

Willy_Liao

6 100Thursday, March 31, 2016

6 100Thursday, March 31, 2016

6 100Thursday, March 31, 2016

Rev

Rev

Rev

0.0

0.0

0.0

5

D D

4

3

+1.2V

+VCCST_CPU

+VCCSTG

+VCCIO

+VCCSA

2

+1.2V [4,16,17,18,83]

+VCCST_CPU [3,5,9,25,32]

+VCCSTG [3,5]

+VCCIO [3,9,91]

+VCCSA [80]

1

12

C0721
10PF/50V

tx_c0201

RF reserve

+VDDQ_CPU

12

C0701
10UF/6.3V

tx_c0603_t02_h39

12

C0702
10UF/6.3V

tx_c0603_t02_h39

12

C0703
10UF/6.3V

tx_c0603_t02_h39

12

C0704
10UF/6.3V

tx_c0603_t02_h39

+VDDQ_CPU

12

12

C0705

C0706

10UF/6.3V

10UF/6.3V

tx_c0603_t02_h39

tx_c0603_t02_h39

1 2

R0701 0Ohm

tx_r0402_0ohm

+VCCST_CPU

12

+VCCSTG

12

+VCCSFR_OC

12

+VCCSFR

12

C0701 - C0704 : Near by package
C0705 - C0710 : Underneath the package

12

12

C0707

C0708

1UF/6.3V

1UF/6.3V

tx_c0201 tx_c0201 tx_c0201 tx_c0201

+VDDQ_CPU_CLK

12

C0711

0.1UF/16V

tx_c0201

C0712
1UF/6.3V

tx_c0201

C0713

0.1UF/16V

tx_c0201

C0714

0.1UF/16V

tx_c0201

12

C0716

C0715

0.1UF/16V

0.1UF/16V

tx_c0201

tx_c0201

12

C0709
1UF/6.3V

12

C0710
1UF/6.3V

U0301N

CPU POWER 3 OF 4

AU23

VDDQ_1

AU28

VDDQ_2

AU35

VDDQ_3

AU42

VDDQ_4

BB23

VDDQ_5

BB32

VDDQ_6

BB41

VDDQ_7

BB47

VDDQ_8

BB51

VDDQ_9

AM40

VDDQC

A18

VCCST

A22

VCCSTG

AL23

VCCPLL_OC

K20

VccPLL_1

K21

VccPLL_2

940432

01T010000015

+1.0V

1 2

R0710 0Ohm

tx_r0402_0ohm

+1.0V +VCCSFR

1 2

R0711 0Ohm

tx_r0402_0ohm

+VCCIO

1 2

R0713 0Ohm

tx_r0402_0ohm

VCCIO_1
VCCIO_2
VCCIO_3
VCCIO_4
VCCIO_5
VCCIO_6
VCCIO_7

VCCSA_1
VCCSA_2
VCCSA_3
VCCSA_4
VCCSA_5
VCCSA_6
VCCSA_7
VCCSA_8

VCCSA_9
VCCSA_10
VCCSA_11
VCCSA_12
VCCSA_13
VCCSA_14

VCCIO_SENSE
VSSIO_SENSE

VSSSA_SENSE

VCCSA_SENSE

+VCCST_CPU

+VCCSTG

AK28
AK30
AL30
AL42
AM28
AM30
AM42

AK23
AK25
G23
G25
G27
G28
J22
J23
J27
K23
K25
K27
K28
K30

AM23
AM22

H21
H20

+VCCSA

VCCIO_VR_FB
VSSIO_VR_FB

1 2

R0702 100Ohm

1%

tx_r0402

1 2

R0703 100Ohm

1%

tx_r0402

Pull H/L near CPU side

141127 65u sec full load ready

141030 Merge Power PDDG0.91 Table5-1

141127 65u sec full load ready

12

12

C0718
1UF/6.3V

+VCCSA

+VCCIO

12

12

12

+VCCSFR_OC+1.2V

C0719
1UF/6.3V

R0714
1KOhm

tx_r0402

@

R0715
1KOhm

tx_r0402

@

C0717
1UF/6.3V

tx_c0201 tx_c0201 tx_c0201 tx_c0201

12

C0723
10PF/50V

tx_c0201

RF reserve

VCCSA_VSSSENSE [ 80]

VCCSA_VCCSENSE [80]

1 2

R0709 0Ohm

tx_r0402_0ohm

Remove +1.35V_LS

+VCCIO

12

C0720
1UF/6.3V

C0722
10PF/50V

tx_c0201

RF reserve

Reserved PH/PD

Refer to CRB 0.53

141030 Merge Power PDDG0.91 Table5-1

12

+1.2V

C C

B B

JP0701
3MM_OPEN_5MIL

2

112

@

JP0702
3MM_OPEN_5MIL

2

112

@

Remove +1.35V_LS

A A

CPU(5)_+VDDQ/IO/SA

CPU(5)_+VDDQ/IO/SA

CPU(5)_+VDDQ/IO/SA

Title :

Title :

reference 543977_543977_SKL_PDDG_Rev0_91

5

PEGATRON PROPRIETARY AND CONFIDENTI AL

PEGATRON PROPRIETARY AND CONFIDENTI AL

PEGATRON PROPRIETARY AND CONFIDENTI AL

Size Project Name

Size Project Name

Size Project Name

C

C

C

HAWAII

HAWAII

Date: Sheet of

Date: Sheet of

4

3

2

Date: Sheet of

HAWAII

Engineer:

Engineer:

Engineer:

1

Title :

Willy_Liao

Willy_Liao

Willy_Liao

7 100Thursday, March 31, 2016

7 100Thursday, March 31, 2016

7 100Thursday, March 31, 2016

Rev

Rev

Rev

0.0

0.0

0.0

5

4

3

2

1

F8
G10
G22
G43
G45
G48

G5
G52
G55
G58

G6
G60
G63
G66
H15
H18
H71

J11

J13

J25

J28

J32

J35

J38

J42

J8
K16
K18
K22
K61
K63
K64
K65
K66
K67
K68
K70
K71

L11
L16
L17

U0301R

GND 3 OF 3

VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
VSS_314
VSS_315
VSS_316
VSS_317
VSS_318

940432

01T010000015

VSS_319
VSS_320
VSS_321
VSS_322
VSS_323
VSS_324
VSS_325
VSS_326
VSS_327
VSS_328
VSS_329
VSS_330
VSS_331
VSS_332
VSS_333
VSS_334
VSS_335
VSS_336
VSS_337
VSS_338
VSS_339
VSS_340
VSS_341
VSS_342
VSS_343
VSS_344
VSS_345
VSS_346
VSS_347
VSS_348
VSS_349
VSS_350
VSS_351
VSS_352
VSS_353
VSS_354
VSS_355
VSS_356
VSS_357
VSS_358
VSS_359

L18
L2
L20
L4
L8
N10
N13
N19
N21
N6
N65
N68
P17
P19
P20
P21
R13
R6
T15
T17
T18
T2
T21
T4
U10
U63
U64
U66
U67
U69
U70
V16
V17
V18
W13
W6
W9
Y17
Y19
Y20
Y21

U0301P

GND 1 OF 3

A5

VSS_1

A67

VSS_2

A70

VSS_3

AA2

VSS_4

AA4

VSS_5

AA65

VSS_6

AA68

VSS_7

AB15

VSS_8

AB16

VSS_9

D D

C C

AB18
AB21

AD13
AD16
AD19
AD20
AD21
AD62

AE64
AE65
AE66
AE67
AE68
AE69

AF10
AF15
AF17

AF63
AG16
AG17
AG18
AG19
AG20
AG21
AG71
AH13

AH63
AH64
AH67

AK11
AK16
AK18
AK21
AK22
AK27
AK63
AK68
AK69

AJ15
AJ18
AJ20

AL28
AL32
AL35
AL38

AL45
AL48
AL52
AL55
AL58
AL64

AB8

AD8

AF1

AF2
AF4

AH6

AJ4

AK8
AL2

AL4

VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70

940432

01T010000015

VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98

VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140

AL65
AL66
AM13
AM21
AM25
AM27
AM43
AM45
AM46
AM55
AM60
AM61
AM68
AM71
AM8
AN20
AN23
AN28
AN30
AN32
AN33
AN35
AN37
AN38
AN40
AN42
AN58
AN63
AP10
AP18
AP20
AP23
AP28
AP32
AP35
AP38
AP42
AP58
AP63
AP68
AP70
AR11
AR15
AR16
AR20
AR23
AR28
AR35
AR42
AR43
AR45
AR46
AR48
AR5
AR50
AR52
AR53
AR55
AR58
AR63
AR8
AT2
AT20
AT23
AT28
AT35
AT4
AT42
AT56
AT58

AT63
AT68
AT71
AU10
AU15
AU20
AU32
AU38

AV68
AV69
AV70

AV71
AW10
AW12
AW14
AW16
AW18
AW21
AW23
AW26
AW28
AW30
AW32
AW34
AW36
AW38
AW41
AW43
AW45
AW47
AW49
AW51
AW53
AW55
AW57

AW6
AW60
AW62
AW64
AW66

AW8

AY66

BA10

BA14

BA18

BA23

BA28

BA32

BA36

BA45

AV1

B10
B14
B18
B22
B30
B34
B39
B44
B48
B53
B58
B62
B66
B71
BA1

BA2

F68

U0301Q

GND 2 OF 3

VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208

940432

01T010000015

VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233
VSS_234
VSS_235
VSS_236
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243
VSS_244
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
VSS_253
VSS_254
VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272
VSS_273
VSS_274
VSS_275
VSS_276
VSS_277

BA49
BA53
BA57
BA6
BA62
BA66
BA71
BB18
BB26
BB30
BB34
BB38
BB43
BB55
BB6
BB60
BB64
BB67
BB70
C1
C25
C5
D10
D11
D14
D18
D22
D25
D26
D30
D34
D39
D44
D45
D47
D48
D53
D58
D6
D62
D66
D69
E11
E15
E18
E21
E46
E50
E53
E56
E6
E65
E71
F1
F13
F2
F22
F23
F27
F28
F32
F33
F35
F37
F38
F4
F40
F42
BA41

B B

A A

CPU(6)_CPU GND

CPU(6)_CPU GND

CPU(6)_CPU GND

Title :

Title :

PEGATRON PROPRIETARY AND CONFIDENTI AL

PEGATRON PROPRIETARY AND CONFIDENTI AL

PEGATRON PROPRIETARY AND CONFIDENTI AL

Size Project Name

Size Project Name

Size Project Name

C

C

C

HAWAII

HAWAII

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

HAWAII

Engineer:

Engineer:

Engineer:

1

Title :

Willy_Liao

Willy_Liao

Willy_Liao

8 100Thursday, March 31, 2016

8 100Thursday, March 31, 2016

8 100Thursday, March 31, 2016

Rev

Rev

Rev

0.0

0.0

0.0

5

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10

T0901

1

CFG11
CFG12
CFG13
CFG14
CFG15

CFG16
CFG17

CFG18
CFG19

CFG_RCOMP

ITP_PMODE

D D

1

T0919

1

T0920

1

T0921

1

T0922

1 2

R0901 49.9Ohm1%

tx_r0402

Reserve TP for XDP

Remove SNN

BA70

C C

Intel confirm NC

T0917
T0918

1
1

RSVD_VSS_F65
RSVD_VSS_G65

BA68

Remove SNN

+VCCIO

12

R0905
0Ohm

tx_r0402_0ohm

@

+VCCIO_OUT_CFG_PU

B B

A A

1 2

R0906 10KOhm@

1 2

R0907 10KOhm@

1 2

R0908 10KOhm@

1 2

R0909 10KOhm@

1 2

R0910 10KOhm@

1 2

R0911 10KOhm@

1 2

R0912 10KOhm@

1 2

R0913 10KOhm@

1 2

R0914 10KOhm@

1 2

R0915 10KOhm@

1 2

R0916 10KOhm@

1 2

R0917 10KOhm@

1 2

R0918 10KOhm@

1 2

R0919 10KOhm@

1 2

R0920 10KOhm@

1 2

R0921 10KOhm@

1%tx_r0402

1%tx_r0402

1%tx_r0402

1%tx_r0402

1%tx_r0402

1%tx_r0402

1%tx_r0402

1%tx_r0402

1%tx_r0402

1%tx_r0402

1%tx_r0402

1%tx_r0402

1%tx_r0402

1%tx_r0402

1%tx_r0402

1%tx_r0402

AL25
AL27

E68
B67
D65
D67
E70
C68
D68
C67
F71
G69
F70
G68
H70
G71
H69
G70

E63
F63

E66
F66

E60

AY2
AY1

D1
D3

K46
K45

C71
B70

F60

A52

J71
J68

F65
G65

F61
E61

E8

U0301S

CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]

CFG[16]
CFG[17]

CFG[18]
CFG[19]

CFG_RCOMP

ITP_PMODE

RSVD_5
RSVD_6

RSVD_7
RSVD_8

RSVD_9
RSVD_10

RSVD_11
RSVD_12

RSVD_13
RSVD_14

RSVD_15

RSVD_16

RSVD_TP_1
RSVD_TP_2

RSVD_17
RSVD_18

VSS_360
VSS_361

RSVD_19
RSVD_20

940432

01T010000015

4

RESERVED SIGNALS-1

CFG0

CFG1

CFG2

CFG3

CFG4

CFG5

CFG6

CFG7

CFG8

CFG9

CFG10

CFG11

CFG12

CFG13

CFG14

CFG15

1 2

R0922 1KOhm

@

tx_r0402

1 2

R0923 1KOhm

@

tx_r0402

1 2

R0924 1KOhm

@

tx_r0402

1 2

R0925 1KOhm

@

tx_r0402

1 2

R0926 1KOhm

tx_r0402

1 2

R0927 1KOhm

@

tx_r0402

1 2

R0928 1KOhm

@

tx_r0402

1 2

R0929 1KOhm

@

tx_r0402

RSVD_TP_3
RSVD_TP_4

RSVD_TP_5
RSVD_TP_6

RSVD_21
RSVD_22

RSVD_23
RSVD_24
RSVD_25
RSVD_26

RSVD_27
RSVD_28

RSVD_29

RSVD_30
RSVD_31

RSVD_32
RSVD_33

RSVD_34
RSVD_35

RSVD_36
RSVD_37

RSVD_38

RSVD_39
RSVD_40

RSVD_41
RSVD_42

VSS_362

ZVM#

RSVD_TP_7
RSVD_TP_8

MSM#

PROC_SELECT#

3

BB68
BB69

Remove SNN

AK13
AK12

BB2
BA3

AU5

TP5

AT5

TP6

D5
D4
B2
C2

B3
A3

AW1

E1
E2

BA4
BB4

A4
C4

BB5

TP4

A69
B69

AY3

D71
C70

C54
D54

AY4

TP1

BB3

TP2

AY71
AR56

AW71
AW70

AP56
C64

RSVD_AY3

Remove SNN

VSS_AY71

Remove SNN

SKL_CNL#

1 2

R0902 0Ohm

tx_r0402_0ohm

1 2

R0903 0Ohm

tx_r0402_0ohm

From Intel, SKL-U 2+2 remove these pins.

MOW WW48

1. Ball C64 which is PROC_SELECT# needs to be pulled to VCCST for
Cannonlake support via 100K ohm resistor and with no resistor populated
(floating pin) for Skylake.

1 2

R0904 100KOHM@

tx_r0402

+1.8VSUS

R0930 0Ohm tx_r0402_0ohm@
R0931 0Ohm tx_r0402_0ohm@

PDG 1.2
Placeholder only. Does not need to be stuffed.
Placement are required for future platform compatibility purpose only.

1 2
1 2

+VCCST_CPU

2

12

C0902

0.1UF/25V@

tx_c0402

+VCCIO [3,7,91]

+VCCST_CPU [3,5,7,25,32]

+1.8VSUS [26,84]

U0301T

AW69

RSVD_43

AW68

RSVD_44

AU56

RSVD_45

AW48

RSVD_46

C7

RSVD_47

U12

RSVD_48

U11

RSVD_49

H11

RSVD_50

940432

01T010000015

VCC_1P8_U12
VCC_1P8_U11

12

C0901

0.1UF/25V@

tx_c0402

+VCCIO

+VCCST_CPU

+1.8VSUS

SPARE

1

F6

RSVD_51

E3

RSVD_52

C11

RSVD_53

B11

RSVD_54

A11

RSVD_55

D12

RSVD_56

C12

RSVD_57

F52

RSVD_58

CPU(7)_CFG/RSVD

CPU(7)_CFG/RSVD

CPU(7)_CFG/RSVD

Title :

Title :

PEGATRON PROPRIETARY AND CONFIDENTI AL

PEGATRON PROPRIETARY AND CONFIDENTI AL

PEGATRON PROPRIETARY AND CONFIDENTI AL

Size Project Name

Size Project Name

Size Project Name

C

C

C

HAWAII

HAWAII

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

HAWAII

Engineer:

Engineer:

Engineer:

1

Title :

Willy_Liao

Willy_Liao

Willy_Liao

9 100Thursday, March 31, 2016

9 100Thursday, March 31, 2016

9 100Thursday, March 31, 2016

Rev

Rev

Rev

0.0

0.0

0.0

5

LPDDR3 Channel A

M_A_CAA[9:0][4]

M_A_DIM0_CLK0[4]

D D

M_A_DIM0_CLK#0[4]

M_A_DIM0_CKE0[4]
M_A_DIM0_CKE1[4]

M_A_DIM0_CS#0[4]
M_A_DIM0_CS#1[4]

M_A_DQS1[4]

B1

M_A_DQS#1[4]

M_A_DQS0[4]

B0

C C

B B

M_A_DQS#0[4]

M_A_DQS3[4]

B3

M_A_DQS#3[4]

M_A_DQS2[4]

B2

M_A_DQS#2[4]

M_A_CAA0
M_A_CAA1
M_A_CAA2
M_A_CAA3
M_A_CAA4
M_A_CAA5
M_A_CAA6
M_A_CAA7
M_A_CAA8
M_A_CAA9

U1601

R2

CA0

P2

CA1

N2

CA2

N3

CA3

M3

B1

CA4

F3

CA5

E3

CA6

E2

CA7

D2

CA8

C2

CA9

J3

B0

CK_t

J2

CK_c

K3

CKE0

K4

CKE1

L3

B3

CS0_n

L4

CS1_n

L8

DM0

G8

DM1

P8

DM2

D8

DM3

B2

A1

GND GND

GND

DNU_1

A2

DNU_5

A12

DNU_7

A13

DNU_9

B1

DNU_2

B13

DNU_10

T1

DNU_3

T13

DNU_11

U1

DNU_4

U2

DNU_6

U12

DNU_8

U13

DNU_12

L10

DQS0_t

L11

DQS0_c

G10

DQS1_t

G11

DQS1_c

P10

DQS2_t

P11

DQS2_c

D10

DQS3_t

D11

DQS3_c

B2

VSS_1

B5

VSS_10

C5

VSS_11

E4

VSS_6

E5

VSS_12

F5

VSS_13

H2

VSS_2

J12

VSS_19

K2

VSS_3

L6

VSS_18

M5

VSS_14

N4

VSS_7

N5

VSS_15

R4

VSS_8

R5

VSS_16

T2

VSS_4

T3

VSS_5

T4

VSS_9

T5

VSS_17

C3

VSSCA_1

D3

VSSCA_2

F4

VSSCA_5

G3

VSSCA_3

G4

VSSCA_6

J4

VSSCA_7

M4

VSSCA_8

P3

VSSCA_4

B6

VSSQ_1

B12

VSSQ_14

C6

VSSQ_2

D12

VSSQ_15

E6

VSSQ_3

F6

VSSQ_4

F12

VSSQ_16

G6

VSSQ_5

G9

VSSQ_10

H10

VSSQ_12

K10

VSSQ_13

L9

VSSQ_11

M6

VSSQ_6

M12

VSSQ_17

N6

VSSQ_7

P12

VSSQ_18

R6

VSSQ_8

T6

VSSQ_9

T12

VSSQ_19

H9CCNNNBLTMLAR-NTM

0315-011Q000

SKU1 0315-01GR0PB
SKU2 0315-01960PB
SKU3 0315-01GJ0PB
SKU4 0315-01A20PB

DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

VDD1_1
VDD1_3
VDD1_5
VDD1_7
VDD1_9
VDD1_2
VDD1_4
VDD1_6
VDD1_8

VDD1_10

VDD2_15
VDD2_17

VDD2_1
VDD2_3

VDD2_10

VDD2_4

VDD2_5
VDD2_11
VDD2_19

VDD2_6
VDD2_12

VDD2_7
VDD2_13
VDD2_20

VDD2_8

VDD2_2

VDD2_9
VDD2_14
VDD2_16
VDD2_18

VDDCA_1
VDDCA_2
VDDCA_5
VDDCA_3
VDDCA_4

VDDQ_8

VDDQ_12

VDDQ_1

VDDQ_13
VDDQ_14

VDDQ_2
VDDQ_5
VDDQ_9
VDDQ_6
VDDQ_7
VDDQ_3

VDDQ_10
VDDQ_15

VDDQ_4

VDDQ_16
VDDQ_17
VDDQ_11

Vref(CA)
Vref(DQ)

NC_2
NC_3
NC_1

P9

M_A_D8

DQ0

N9

M_A_D11

DQ1

N10

M_A_D13

DQ2

N11

M_A_D12

DQ3

M8

M_A_D14

DQ4

M9

M_A_D15

DQ5

M10

M_A_D9

DQ6

M11

M_A_D10

DQ7

F11

M_A_D4

DQ8

F10

M_A_D2

DQ9

F9

M_A_D5

F8

M_A_D6

E11

M_A_D7

E10

M_A_D0

E9

M_A_D3

D9

M_A_D1

T8

M_A_D28

T9

M_A_D25

T10

M_A_D27

T11

M_A_D30

R8

M_A_D24

R9

M_A_D29

R10

M_A_D26

R11

M_A_D31

C11

M_A_D22

C10

M_A_D16

C9

M_A_D17

C8

M_A_D18

B11

M_A_D21

B10

M_A_D20

B9

M_A_D23

B8

M_A_D19

A3
A4
A5
A6
A10
U3
U4
U5
U6
U10

A8
A9
D4
D5
D6
G5
H5
H6
H12
J5
J6
K5
K6
K12
L5
P4
P5
P6
U8
U9

F2
G2
H3
L2
M2

A11
C12
E8
E12
G12
H8
H9
H11
J9
J10
K8
K11
L12
N8
N12
R12
U11

H4
J11

J8

ODT

B3

R1601 243OHM tx_r0402 1%

ZQ0

B4

R1602 243OHM tx_r0402 1%

ZQ1

C4
K9
R3

12

C1658
10PF/50V

tx_c0402

@

Close To Memory Die

GND

12

C1659
10PF/50V

tx_c0402

@

Close To Memory Die Close To Memory Die

GND

+1.2V

+1.2V +1.2V

+V_VREF_CA_DIMM0
+V_VREF_DQ_DIMM0

M_A_DIM0_ODT0 [4]

1 2
1 2

4

M_A_D[15:8] [4]

M_A_D[7:0] [4]

M_A_D[31:24] [ 4]

M_A_D[23:16] [ 4]

+1.8V_DDR3 +1.8V_DDR3

+1.2V

GND

M_A_CAB[9:0][4]

M_A_DIM0_CLK1[4]
M_A_DIM0_CLK#1[4]

M_A_DIM0_CKE2[4]
M_A_DIM0_CKE3[4]

M_A_DIM0_CS#0
M_A_DIM0_CS#1

M_A_DQS4[4]

B4

M_A_DQS#4[4]

M_A_DQS5[4]

B5

M_A_DQS#5[4]

M_A_DQS6[4]

B6

M_A_DQS#6[4]

M_A_DQS7[4]

B7

M_A_DQS#7[4]

M_A_CAB0
M_A_CAB1
M_A_CAB2
M_A_CAB3
M_A_CAB4
M_A_CAB5
M_A_CAB6
M_A_CAB7
M_A_CAB8
M_A_CAB9

GND

R2
P2
N2
N3
M3
F3
E3
E2
D2
C2

J3
J2

K3
K4

L3
L4

L8
G8
P8
D8

A1

A2
A12
A13

B1
B13

T1
T13

U1

U2
U12
U13

L10
L11

G10
G11

P10
P11

D10
D11

B2

B5

C5

E4

E5

F5

H2

J12

K2

L6

M5

N4

N5

R4

R5

T2

T3

T4

T5

C3

D3

F4

G3

G4

J4
M4
P3

B6

B12

C6

D12

E6
F6

F12

G6
G9

H10
K10

L9
M6

M12

N6

P12

R6
T6

T12

3

U1602

CA0
CA1
CA2
CA3

B4

CA4
CA5
CA6
CA7
CA8
CA9

B5

CK_t
CK_c

CKE0
CKE1

B6

CS0_n
CS1_n

DM0
DM1
DM2
DM3

B7

DNU_1
DNU_5
DNU_7
DNU_9
DNU_2
DNU_10
DNU_3
DNU_11
DNU_4
DNU_6
DNU_8
DNU_12

DQS0_t
DQS0_c

DQS1_t
DQS1_c

DQS2_t
DQS2_c

DQS3_t
DQS3_c

VSS_1
VSS_10
VSS_11
VSS_6
VSS_12
VSS_13
VSS_2
VSS_19
VSS_3
VSS_18
VSS_14
VSS_7
VSS_15
VSS_8
VSS_16
VSS_4
VSS_5
VSS_9
VSS_17

VSSCA_1
VSSCA_2
VSSCA_5
VSSCA_3
VSSCA_6
VSSCA_7
VSSCA_8
VSSCA_4

VSSQ_1
VSSQ_14
VSSQ_2
VSSQ_15
VSSQ_3
VSSQ_4
VSSQ_16
VSSQ_5
VSSQ_10
VSSQ_12
VSSQ_13
VSSQ_11
VSSQ_6
VSSQ_17
VSSQ_7
VSSQ_18
VSSQ_8
VSSQ_9
VSSQ_19

H9CCNNNBLTMLAR-NTM

0315-011Q000

SKU1 0315-01GR0PB
SKU2 0315-01960PB
SKU3 0315-01GJ0PB
SKU4 0315-01A20PB

DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

VDD1_1
VDD1_3
VDD1_5
VDD1_7
VDD1_9
VDD1_2
VDD1_4
VDD1_6
VDD1_8

VDD1_10

VDD2_15
VDD2_17

VDD2_1
VDD2_3

VDD2_10

VDD2_4

VDD2_5
VDD2_11
VDD2_19

VDD2_6
VDD2_12

VDD2_7
VDD2_13
VDD2_20

VDD2_8

VDD2_2

VDD2_9
VDD2_14
VDD2_16
VDD2_18

VDDCA_1
VDDCA_2
VDDCA_5
VDDCA_3
VDDCA_4

VDDQ_8

VDDQ_12

VDDQ_1

VDDQ_13
VDDQ_14

VDDQ_2

VDDQ_5

VDDQ_9

VDDQ_6

VDDQ_7

VDDQ_3

VDDQ_10
VDDQ_15

VDDQ_4

VDDQ_16
VDDQ_17
VDDQ_11

Vref(CA)

Vref(DQ)

NC_2
NC_3
NC_1

P9

M_A_D32

DQ0

N9

M_A_D37

DQ1

N10

M_A_D39

DQ2

N11

M_A_D38

DQ3

M8

M_A_D33

DQ4

M9

M_A_D36

DQ5

M10

M_A_D35

DQ6

M11

M_A_D34

DQ7

F11

M_A_D47

DQ8

F10

M_A_D43

DQ9

F9

M_A_D46

F8

M_A_D44

E11

M_A_D41

E10

M_A_D40

E9

M_A_D42

D9

M_A_D45

T8

M_A_D53

T9

M_A_D50

T10

M_A_D48

T11

M_A_D54

R8

M_A_D51

R9

M_A_D52

R10

M_A_D49

R11

M_A_D55

C11

M_A_D63

C10

M_A_D59

C9

M_A_D57

C8

M_A_D60

B11

M_A_D62

B10

M_A_D58

B9

M_A_D56

B8

M_A_D61

A3
A4
A5
A6
A10
U3
U4
U5
U6
U10

A8
A9
D4
D5
D6
G5
H5
H6
H12
J5
J6
K5
K6
K12
L5
P4
P5
P6
U8
U9

F2
G2
H3
L2
M2

A11
C12
E8
E12
G12
H8
H9
H11
J9
J10
K8
K11
L12
N8
N12
R12
U11

H4
J11

J8

M_A_DIM0_ODT0

ODT

B3

R1603 243OHM tx_r0402 1%

ZQ0

B4

R1604 243OHM tx_r0402 1%

ZQ1

C4
K9
R3

12

C1660
10PF/50V

tx_c0402

@

GND

Close To Memory Die

12

C1661
10PF/50V

tx_c0402

@

GND

+1.2V

+V_VREF_CA_DIMM0
+V_VREF_DQ_DIMM0

1 2
1 2

M_A_D[39:32] [4]

M_A_D[47:40] [4]

M_A_D[55:48] [4]

M_A_D[63:56] [4]

+1.2V

2

+1.8V_DDR3

+1.8V_DDR3+1.8V

JP1602

2

112

1MM_OPEN_M1M2

@

+1.8V_DDR3

12

12

C1807
1UF/6.3V

tx_c0402

+1.2V

12

C1883
1UF/6.3V

tx_c0402

+0.6VS

12

C1834
1UF/6.3V

tx_c0402

+0.6VS

12

C1652
22uF/6.3V

tx_r0402_h28

@

R1.1

GND

Follow CRB RVP5, Only one 22uF Mount Per Channel

C1804
10UF/6.3V

tx_c0603_t02_h39

12

C1808
1UF/6.3V

tx_c0402

12

C1811
10UF/6.3V

tx_c0603_t02_h39

12

C1819
1UF/6.3V

tx_c0402

12

C1885
1UF/6.3V

tx_c0402

12

C1835
1UF/6.3V

tx_c0402

12

C1653
22uF/6.3V

tx_r0402_h28

@

12

C1805
10UF/6.3V

tx_c0603_t02_h39

12

C1809
1UF/6.3V

tx_c0402

GND

12

C1820
1UF/6.3V

tx_c0402

12

C1884
1UF/6.3V

tx_c0402

12

C1836
1UF/6.3V

tx_c0402

12

C1810
1UF/6.3V

tx_c0402

GND

12

C1853
10UF/6.3V

tx_c0603_t02_h39

12

C1821
1UF/6.3V

tx_c0402

12

C1886
1UF/6.3V

tx_c0402

12

C1837
1UF/6.3V

tx_c0402

12

C1654
22uF/6.3V

tx_r0402_h28

@

12

C1806
10UF/6.3V

tx_c0603_t02_h39

GND

12

12

12

C1822
1UF/6.3V

tx_c0402

C1830

0.1UF/6.3V

tx_c0201

C1838
1UF/6.3V

tx_c0402

12

C1655
22uF/6.3V

tx_r0402_h28

@

+V_VREF_CA_DIMM0

+V_VREF_DQ_DIMM0

12

C1875
1UF/6.3V

tx_c0402

12

C1831

0.1UF/6.3V

tx_c0201

12

C1839
1UF/6.3V

tx_c0402

12

M_A_DIM0_ODT0
M_A_DIM0_CS#0
M_A_DIM0_CS#1
M_A_DIM0_CKE0
M_A_DIM0_CKE1
M_A_DIM0_CKE2
M_A_DIM0_CKE3

M_A_DIM0_CLK0
M_A_DIM0_CLK#0
M_A_DIM0_CLK1
M_A_DIM0_CLK#1

12

C1877
1UF/6.3V

tx_c0402

12

12

C1840
1UF/6.3V

tx_c0402

C1656
22uF/6.3V

tx_r0402_h28

@

M_A_CAA0
M_A_CAA1
M_A_CAA2
M_A_CAA3
M_A_CAA4
M_A_CAA5
M_A_CAA6
M_A_CAA7
M_A_CAA8
M_A_CAA9

M_A_CAB0
M_A_CAB1
M_A_CAB2
M_A_CAB3
M_A_CAB4
M_A_CAB5
M_A_CAB6
M_A_CAB7
M_A_CAB8
M_A_CAB9

C1832

0.1UF/6.3V

tx_c0201

1

+1.8V

+1.2V

+0.6VS

R1605 68Ohm
R1606 68Ohm
R1607 68Ohm
R1608 68Ohm
R1609 68Ohm
R1610 68Ohm
R1611 68Ohm
R1612 68Ohm
R1613 68Ohm
R1614 68Ohm

R1615 68Ohm
R1616 68Ohm
R1617 68Ohm
R1618 68Ohm
R1619 68Ohm
R1620 68Ohm
R1621 68Ohm
R1622 68Ohm
R1623 68Ohm
R1624 68Ohm

R1629 80.6Ohm
R1628 80.6Ohm
R1627 80.6Ohm
R1625 80.6Ohm
R1626 80.6Ohm
R1635 80.6Ohm
R1634 80.6Ohm

R1630 37.4Ohm
R1631 37.4Ohm
R1632 37.4Ohm
R1633 37.4Ohm

12

12

C1878

C1876

1UF/6.3V

1UF/6.3V

tx_c0402

tx_c0402

GND

12

C1833

0.1UF/6.3V

tx_c0201

GND

12

12

C1842
22UF/6.3V

C1841

X5R/+/-20%

1UF/6.3V

tx_c0603_t02_h39

tx_c0402

12

C1657
22uF/6.3V

tx_r0402_h28

@

GND

+1.8V [57,91]

+1.8V_DDR3 [17]

+1.2V [4,7,17,18,83]

+0.6VS [17,57,83]

+V_VREF_CA_DIMM0 [18]

+V_VREF_DQ_DIMM0 [18]

12

GND

+0.6VS

C1843
22uF/6.3V

tx_r0402_h28

@

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2

+1.2V

A A

12

C1815
1UF/6.3V

tx_c0402

12

C1813
10UF/6.3V

tx_c0603_t02_h39

5

12

C1814
10UF/6.3V

tx_c0603_t02_h39

GND

+1.2V

12

C1816
1UF/6.3V

tx_c0402

+V_VREF_CA_DIMM0 +V_VREF_DQ_DIMM0

12

C1817
1UF/6.3V

tx_c0402

GND

12

12

GND GND GND GND

C1601

0.047UF/16V

tx_c0402

4

C1602

0.047UF/16V

tx_c0402

12

C1603

0.047UF/16V

tx_c0402

12

C1604

0.047UF/16V

tx_c0402

+1.2V

12

C1818
1UF/6.3V

tx_c0402

12

C1851

10UF/6.3V

tx_c0603_t02_h39

3

12

C1852
10UF/6.3V

tx_c0603_t02_h39

GND

+1.2V

12

C1824
1UF/6.3V

tx_c0402

12

C1825
1UF/6.3V

tx_c0402

GND

2

<Variant Name>

<Variant Name>

<Variant Name>

Title :

Title :

Title :

LPDDR3(1)_Channel A

LPDDR3(1)_Channel A

LPDDR3(1)_Channel A

Willy_Liao

Willy_Liao

Engineer:

Engineer:

HAWAII

HAWAII

HAWAII

Engineer:

1

Size Project Name

Size Project Name

Size Project Name

C

C

C

Date: Sheet of

Date: Sheet of

Date: Sheet of

Willy_Liao

16 100Thursday, March 31, 2016

16 100Thursday, March 31, 2016

16 100Thursday, March 31, 2016

Rev

Rev

Rev

0.0

0.0

0.0

5

LPDDR3 Channel B

M_B_CAA[9:0][4] M_B_CAB[9:0][4]

M_B_DIM0_CLK0[4]
M_B_DIM0_CLK#0[4]

D D

M_B_DIM0_CKE0[4]
M_B_DIM0_CKE1[4]

M_B_DIM0_CS#0[4]
M_B_DIM0_CS#1[4]

M_B_DQS0[4]

B0

M_B_DQS#0[4]

M_B_DQS1[4]

B1

M_B_DQS#1[4]

C C

B B

M_B_DQS2[4]

B2

M_B_DQS#2[4]

M_B_DQS3[4]

B3

M_B_DQS#3[4]

M_B_CAA0
M_B_CAA1
M_B_CAA2
M_B_CAA3
M_B_CAA4
M_B_CAA5
M_B_CAA6
M_B_CAA7
M_B_CAA8
M_B_CAA9

GND

U1701

R2

CA0

P2

CA1

N2

CA2

N3

CA3

M3

CA4

F3

CA5

E3

CA6

E2

CA7

D2

CA8

C2

CA9

J3

CK_t

J2

CK_c

K3

CKE0

K4

CKE1

L3

CS0_n

L4

CS1_n

L8

DM0

G8

DM1

P8

DM2

D8

DM3

A1

DNU_1

A2

DNU_5

A12

DNU_7

A13

DNU_9

B1

DNU_2

B13

DNU_10

T1

DNU_3

T13

DNU_11

U1

DNU_4

U2

DNU_6

U12

DNU_8

U13

DNU_12

L10

DQS0_t

L11

DQS0_c

G10

DQS1_t

G11

DQS1_c

P10

DQS2_t

P11

DQS2_c

D10

DQS3_t

D11

DQS3_c

B2

VSS_1

B5

VSS_10

C5

VSS_11

E4

VSS_6

E5

VSS_12

F5

VSS_13

H2

VSS_2

J12

VSS_19

K2

VSS_3

L6

VSS_18

M5

VSS_14

N4

VSS_7

N5

VSS_15

R4

VSS_8

R5

VSS_16

T2

VSS_4

T3

VSS_5

T4

VSS_9

T5

VSS_17

C3

VSSCA_1

D3

VSSCA_2

F4

VSSCA_5

G3

VSSCA_3

G4

VSSCA_6

J4

VSSCA_7

M4

VSSCA_8

P3

VSSCA_4

B6

VSSQ_1

B12

VSSQ_14

C6

VSSQ_2

D12

VSSQ_15

E6

VSSQ_3

F6

VSSQ_4

F12

VSSQ_16

G6

VSSQ_5

G9

VSSQ_10

H10

VSSQ_12

K10

VSSQ_13

L9

VSSQ_11

M6

VSSQ_6

M12

VSSQ_17

N6

VSSQ_7

P12

VSSQ_18

R6

VSSQ_8

T6

VSSQ_9

T12

VSSQ_19

H9CCNNNBLTMLAR-NTM

0315-011Q000

SKU1 0315-01GR0PB
SKU2 0315-01960PB
SKU3 0315-01GJ0PB
SKU4 0315-01A20PB

P9

M_B_D5

DQ0

N9

M_B_D3

DQ1

N10

M_B_D2

DQ2

N11

M_B_D4

DQ3

M8

DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

NC_2
NC_3
NC_1

M_B_D1

DQ4

M9

M_B_D6

DQ5

M10

M_B_D7

DQ6

M11

M_B_D0

DQ7

F11

M_B_D9

DQ8

F10

M_B_D12

DQ9

F9

M_B_D13

F8

M_B_D11

E11

M_B_D14

E10

M_B_D10

E9

M_B_D15

D9

M_B_D8

T8

M_B_D21

T9

M_B_D20

T10

M_B_D23

T11

M_B_D19

R8

M_B_D16

R9

M_B_D17

R10

M_B_D18

R11

M_B_D22

C11

M_B_D26

C10

M_B_D29

C9

M_B_D28

C8

M_B_D25

B11

M_B_D27

B10

M_B_D30

B9

M_B_D31

B8

M_B_D24

A3
A4
A5
A6
A10
U3
U4
U5
U6
U10

A8
A9
D4
D5
D6
G5
H5
H6
H12
J5
J6
K5
K6
K12
L5
P4
P5
P6
U8
U9

F2
G2
H3
L2
M2

A11
C12
E8
E12
G12
H8
H9
H11
J9
J10
K8
K11
L12
N8
N12
R12
U11

H4
J11

J8

ODT

B3

ZQ0

B4

ZQ1

C4
K9
R3

12

C1710
10PF/50V

tx_c0402

@

GND

12

C1711
10PF/50V

tx_c0402

@

GND

+1.2V

+1.2V +1.2V

+V_VREF_CA_DIMM1
+V_VREF_DQ_DIMM1

1 2

R1701 243OHM1%

1 2

R1702 243OHM1%

B0

B1

B2

B3

VDD1_1
VDD1_3
VDD1_5
VDD1_7
VDD1_9
VDD1_2
VDD1_4
VDD1_6
VDD1_8

VDD1_10

VDD2_15
VDD2_17

VDD2_1
VDD2_3

VDD2_10

VDD2_4

VDD2_5
VDD2_11
VDD2_19

VDD2_6
VDD2_12

VDD2_7
VDD2_13
VDD2_20

VDD2_8

VDD2_2

VDD2_9
VDD2_14
VDD2_16
VDD2_18

VDDCA_1
VDDCA_2
VDDCA_5
VDDCA_3
VDDCA_4

VDDQ_8

VDDQ_12

VDDQ_1

VDDQ_13
VDDQ_14

VDDQ_2
VDDQ_5
VDDQ_9
VDDQ_6
VDDQ_7
VDDQ_3

VDDQ_10
VDDQ_15

VDDQ_4

VDDQ_16
VDDQ_17
VDDQ_11

Vref(CA)
Vref(DQ)

4

M_B_D[7:0] [4]

M_B_D[15:8] [4]

M_B_DIM0_CLK1[4]

M_B_D[23:16] [ 4]

M_B_D[31:24] [ 4]

+1.8V_DDR3 +1.8V_DDR3

Close To Memory Die

+1.2V

Close To Memory Die

M_B_DIM0_ODT0 [4]

M_B_DIM0_CLK#1[4]

M_B_DIM0_CKE2[4]
M_B_DIM0_CKE3[4]

M_B_DIM0_CS#0
M_B_DIM0_CS#1

M_B_DQS4[4]

B4

M_B_DQS#4[4]

M_B_DQS5[4]

B5

M_B_DQS#5[4]

M_B_DQS6[4]

B6

M_B_DQS#6[4]

M_B_DQS7[4]

B7

M_B_DQS#7[4]

M_B_CAB0
M_B_CAB1
M_B_CAB2
M_B_CAB3
M_B_CAB4
M_B_CAB5
M_B_CAB6
M_B_CAB7
M_B_CAB8
M_B_CAB9

GNDGND

GND

R2
P2
N2
N3
M3
F3
E3
E2
D2
C2

J3
J2

K3
K4

L3
L4

L8
G8
P8
D8

A1

A2
A12
A13

B1
B13

T1
T13

U1

U2
U12
U13

L10
L11

G10
G11

P10
P11

D10
D11

B2

B5

C5

E4

E5

F5

H2

J12

K2

L6

M5

N4

N5

R4

R5

T2

T3

T4

T5

C3

D3

F4

G3

G4

J4
M4
P3

B6

B12

C6

D12

E6
F6

F12

G6
G9

H10
K10

L9
M6

M12

N6

P12

R6
T6

T12

3

U1702

CA0
CA1
CA2
CA3

B4

CA4
CA5
CA6
CA7
CA8
CA9

B5

CK_t
CK_c

CKE0
CKE1

B6

CS0_n
CS1_n

DM0
DM1
DM2
DM3

B7

DNU_1
DNU_5
DNU_7
DNU_9
DNU_2
DNU_10
DNU_3
DNU_11
DNU_4
DNU_6
DNU_8
DNU_12

DQS0_t
DQS0_c

DQS1_t
DQS1_c

DQS2_t
DQS2_c

DQS3_t
DQS3_c

VSS_1
VSS_10
VSS_11
VSS_6
VSS_12
VSS_13
VSS_2
VSS_19
VSS_3
VSS_18
VSS_14
VSS_7
VSS_15
VSS_8
VSS_16
VSS_4
VSS_5
VSS_9
VSS_17

VSSCA_1
VSSCA_2
VSSCA_5
VSSCA_3
VSSCA_6
VSSCA_7
VSSCA_8
VSSCA_4

VSSQ_1
VSSQ_14
VSSQ_2
VSSQ_15
VSSQ_3
VSSQ_4
VSSQ_16
VSSQ_5
VSSQ_10
VSSQ_12
VSSQ_13
VSSQ_11
VSSQ_6
VSSQ_17
VSSQ_7
VSSQ_18
VSSQ_8
VSSQ_9
VSSQ_19

H9CCNNNBLTMLAR-NTM

0315-011Q000

SKU1 0315-01GR0PB
SKU2 0315-01960PB
SKU3 0315-01GJ0PB
SKU4 0315-01A20PB

DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

VDD1_1
VDD1_3
VDD1_5
VDD1_7
VDD1_9
VDD1_2
VDD1_4
VDD1_6
VDD1_8

VDD1_10

VDD2_15
VDD2_17

VDD2_1
VDD2_3

VDD2_10

VDD2_4

VDD2_5
VDD2_11
VDD2_19

VDD2_6
VDD2_12

VDD2_7
VDD2_13
VDD2_20

VDD2_8

VDD2_2

VDD2_9
VDD2_14
VDD2_16
VDD2_18

VDDCA_1
VDDCA_2
VDDCA_5
VDDCA_3
VDDCA_4

VDDQ_8

VDDQ_12

VDDQ_1

VDDQ_13
VDDQ_14

VDDQ_2

VDDQ_5

VDDQ_9

VDDQ_6

VDDQ_7

VDDQ_3

VDDQ_10
VDDQ_15

VDDQ_4

VDDQ_16
VDDQ_17
VDDQ_11

Vref(CA)

Vref(DQ)

NC_2
NC_3
NC_1

P9

M_B_D35

DQ0

N9

M_B_D33

DQ1

N10

M_B_D38

DQ2

N11

M_B_D34

DQ3

M8

M_B_D32

DQ4

M9

M_B_D36

DQ5

M10

M_B_D37

DQ6

M11

M_B_D39

DQ7

F11

M_B_D46

DQ8

F10

M_B_D47

DQ9

F9

M_B_D44

F8

M_B_D45

E11

M_B_D42

E10

M_B_D41

E9

M_B_D40

D9

M_B_D43

T8

M_B_D52

T9

M_B_D48

T10

M_B_D54

T11

M_B_D51

R8

M_B_D53

R9

M_B_D49

R10

M_B_D55

R11

M_B_D50

C11

M_B_D60

C10

M_B_D61

C9

M_B_D59

C8

M_B_D62

B11

M_B_D57

B10

M_B_D56

B9

M_B_D58

B8

M_B_D63

A3
A4
A5
A6
A10
U3
U4
U5
U6
U10

A8
A9
D4
D5
D6
G5
H5
H6
H12
J5
J6
K5
K6
K12
L5
P4
P5
P6
U8
U9

F2
G2
H3
L2
M2

A11
C12
E8
E12
G12
H8
H9
H11
J9
J10
K8
K11
L12
N8
N12
R12
U11

H4
J11

J8

ODT

B3

ZQ0

B4

ZQ1

C4
K9
R3

M_B_DIM0_ODT0

1 2

R1703 243OHM1%

1 2

R1704 243OHM1%

12

C1712
10PF/50V

tx_c0402

@

GND

12

C1713
10PF/50V

tx_c0402

@

GND

+1.2V

+V_VREF_CA_DIMM1
+V_VREF_DQ_DIMM1

M_B_D[39:32] [4]

M_B_D[47:40] [4]

M_B_D[55:48] [4]

M_B_D[63:56] [4]

Close To Memory Die

+1.2V

Close To Memory Die

GNDGND

2

+1.8V_DDR3

12

12

C1823
1UF/6.3V

tx_c0402

+1.2V

12

C1879
1UF/6.3V

tx_c0402

+0.6VS

12

C1740
1UF/6.3V

tx_c0402

+0.6VS

12

C1752
22uF/6.3V

tx_r0402_h28

@

R1.1
Follow CRB RVP5, Only one 22uF Mount Per Channel

C1861
10UF/6.3V

tx_c0603_t02_h39

12

C1865
1UF/6.3V

tx_c0402

12

C1845
10UF/6.3V

tx_c0603_t02_h39

12

C1856
1UF/6.3V

tx_c0402

12

C1880
1UF/6.3V

tx_c0402

12

C1741
1UF/6.3V

tx_c0402

12

C1753
22uF/6.3V

tx_r0402_h28

@

12

C1849
10UF/6.3V

tx_c0603_t02_h39

12

C1863
1UF/6.3V

tx_c0402

12

C1862
1UF/6.3V

tx_c0402

12

C1881
1UF/6.3V

tx_c0402

12

C1742
1UF/6.3V

tx_c0402

12

GND

12

C1846
10UF/6.3V

tx_c0603_t02_h39

GND

12

12

12

12

C1750
22uF/6.3V

tx_r0402_h28

@

C1864
1UF/6.3V

tx_c0402

C1866
1UF/6.3V

tx_c0402

C1882
1UF/6.3V

tx_c0402

C1743
1UF/6.3V

tx_c0402

12

GND

C1850
10UF/6.3V

tx_c0603_t02_h39

12

C1867
1UF/6.3V

tx_c0402

12

C1826

0.1UF/6.3V

tx_c0201

12

C1746
1UF/6.3V

tx_c0402

12

C1755
22uF/6.3V

tx_r0402_h28

@

12

12

C1868
1UF/6.3V

tx_c0402

12

C1827

0.1UF/6.3V

tx_c0201

C1747
1UF/6.3V

tx_c0402

12

+1.8V_DDR3

+V_VREF_CA_DIMM1

+V_VREF_DQ_DIMM1

M_B_CAA0
M_B_CAA1
M_B_CAA2
M_B_CAA3
M_B_CAA4
M_B_CAA5
M_B_CAA6
M_B_CAA7
M_B_CAA8
M_B_CAA9

M_B_CAB0
M_B_CAB1
M_B_CAB2
M_B_CAB3
M_B_CAB4
M_B_CAB5
M_B_CAB6
M_B_CAB7
M_B_CAB8
M_B_CAB9

M_B_DIM0_ODT0
M_B_DIM0_CS#0
M_B_DIM0_CS#1
M_B_DIM0_CKE0
M_B_DIM0_CKE1
M_B_DIM0_CKE2
M_B_DIM0_CKE3

M_B_DIM0_CLK0
M_B_DIM0_CLK#0
M_B_DIM0_CLK1
M_B_DIM0_CLK#1

12

12

C1869
1UF/6.3V

tx_c0402

12

C1828

0.1UF/6.3V

tx_c0201

12

12

C1748
1UF/6.3V

tx_c0402

12

C1756
22uF/6.3V

tx_r0402_h28

@

GND

1

+1.2V

+0.6VS

R1705 68Ohm
R1706 68Ohm
R1707 68Ohm
R1708 68Ohm
R1709 68Ohm
R1710 68Ohm
R1711 68Ohm
R1712 68Ohm
R1713 68Ohm
R1714 68Ohm

R1715 68Ohm
R1716 68Ohm
R1717 68Ohm
R1718 68Ohm
R1719 68Ohm
R1720 68Ohm
R1721 68Ohm
R1722 68Ohm
R1723 68Ohm
R1724 68Ohm

R1729 80.6Ohm
R1728 80.6Ohm
R1727 80.6Ohm
R1725 80.6Ohm
R1726 80.6Ohm
R1734 80.6Ohm
R1735 80.6Ohm

R1730 37.4Ohm
R1731 37.4Ohm
R1733 37.4Ohm
R1732 37.4Ohm

12

C1873

C1870

1UF/6.3V

1UF/6.3V

tx_c0402

tx_c0402

GND

12

C1829

0.1UF/6.3V

tx_c0201

GND

12

C1754
22UF/6.3V

C1749

X5R/+/-20%

1UF/6.3V

tx_c0603_t02_h39

tx_c0402

C1757
22uF/6.3V

tx_r0402_h28

@

+1.8V_DDR3 [16]

+1.2V [4,7,16,18,83]

+0.6VS [16,57,83]

+V_VREF_CA_DIMM1 [18]

+V_VREF_DQ_DIMM1 [18]

12

GND

C1751
22uF/6.3V

tx_r0402_h28

@

+0.6VS

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2

+1.2V

A A

12

C1857
1UF/6.3V

tx_c0402

12

C1872
10UF/6.3V

tx_c0603_t02_h39

12

C1871
10UF/6.3V

tx_c0603_t02_h39

GND

5

+1.2V

12

C1858
1UF/6.3V

tx_c0402

+V_VREF_DQ_DIMM1+V_VREF_CA_DIMM1

12

C1859
1UF/6.3V

tx_c0402

GND

12

C1701

0.047UF/16V

tx_c0402

12

C1702

0.047UF/16V

tx_c0402

12

4

C1703

0.047UF/16V

tx_c0402

12

GNDGNDGNDGND

C1704

0.047UF/16V

tx_c0402

+1.2V

12

C1860
1UF/6.3V

tx_c0402

12

C1812
10UF/6.3V

tx_c0603_t02_h39

12

C1844
10UF/6.3V

tx_c0603_t02_h39

GND

3

+1.2V

12

C1854
1UF/6.3V

tx_c0402

12

C1855
1UF/6.3V

tx_c0402

<Variant Name>

<Variant Name>

GND

2

<Variant Name>

Title :

Title :

Title :

LPDDR3(2)_Channel B

LPDDR3(2)_Channel B

LPDDR3(2)_Channel B

Willy_Liao

Willy_Liao

Engineer:

Engineer:

HAWAII

HAWAII

HAWAII

Engineer:

1

Size Project Name

Size Project Name

Size Project Name

C

C

C

Date: Sheet of

Date: Sheet of

Date: Sheet of

Willy_Liao

17 100Thursday, March 31, 2016

17 100Thursday, March 31, 2016

17 100Thursday, March 31, 2016

Rev

Rev

Rev

0.0

0.0

0.0

5

4

3

2

1

+1.2V

+V_VREF_DQ_DIMM0

LPDDR3 Vref

D D

1 2

DIMM0_VREF_DQ[4]

12

12

C C

DIMM1_VREF_DQ[4]

12

12

B B

R1803 10Ohm

C1801

0.022UF/16V

tx_c0402

R1804

24.9Ohm

tx_r0402
1%

R1807 10Ohm

C1802

0.022UF/16V

tx_c0402

R1808

24.9Ohm

tx_r0402
1%

tx_r0402

1 2

tx_r0402

1%

1%

+1.2V

12

12

+1.2V

12

12

R1801

8.2KOhm

tx_r0402
1%

R1802

8.2KOhm

tx_r0402
1%

R1805

8.2KOhm

tx_r0402
1%

R1806

8.2KOhm

tx_r0402
1%

+V_VREF_DQ_DIMM0

+V_VREF_DQ_DIMM1

+V_VREF_CA_DIMM0

+V_VREF_DQ_DIMM1

+V_VREF_CA_DIMM1

+1.2V [4,7,16,17,83]

+V_VREF_DQ_DIMM0 [16]

+V_VREF_CA_DIMM0 [16]

+V_VREF_DQ_DIMM1 [17]

+V_VREF_CA_DIMM1 [17]

+1.2V

3

+V_VREF_CA_DIMM0

+V_VREF_CA_DIMM1

Title :

Title :

Title :

Engineer:

Engineer:

BG1-NB4

BG1-NB4

BG1-NB4

Size Projec t Name

Size Projec t Name

Size Projec t Name

B

B

B

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

HAWAII

HAWAII

HAWAII

Engineer:

LPDDR3(3)_CA/DQ

LPDDR3(3)_CA/DQ

LPDDR3(3)_CA/DQ

Willy_Liao

Willy_Liao

Willy_Liao

18 10 0Thursday, March 31, 2016

18 10 0Thursday, March 31, 2016

18 10 0Thursday, March 31, 2016

1

Rev

Rev

Rev

0.0

0.0

0.0

12

R1809

8.2KOhm

tx_r0402

12

1%

R1810

8.2KOhm

tx_r0402
1%

R1811

DIMM_VREF_CA[4]

12

C1803

0.022UF/16V

tx_c0402

A A

5

12

R1812

24.9Ohm

tx_r0402
1%

1 2

5.1OHM

10T220000087

DIMM_VREF_CA_R

4

1 2

SP1801 0Ohm

tx_r0402_short_12mil

1 2

SP1802 0Ohm

tx_r0402_short_12mil

5

4

3

2

1

+3VSUS_ORG

+3VS

U0301E

SPI - FLASH

D D

C C

B B

SPI_CLK[28]
SPI_SO[28]

SPI_SI[28]
SPI_WP#_IO2[28]
SPI_HOLD#_IO3[28]
SPI_CS#0[28]

12

C2003
10PF/50V

@

tx_c0402

RF reserve

GND

CL_CLK[53]
CL_DATA[53]
CL_RST#[53]

RCIN#[30]

INT_SERIRQ[30,44,62]

1 2

R2004 20KOhm@

GND

1 2

R2006 20KOhm@

GND

1 2

R2008 20KOhm@

GND

tx_r0402

tx_r0402

tx_r0402

T2011
T2001

T2016
T2017
T2018
T2019
T2020
T2021

1
1

1
1
1
1
1
1

WiGig_WAKE#

SPI_CS1#
SPI_CS2#

SPI1_CLK_1
SPI1_MISO
SPI1_MOSI
SPI1_IO2
SPI1_IO3
SPI1_CS#

AV2

SPI0_CLK

AW3

SPI0_MISO

AV3

SPI0_MOSI

AW2

SPI0_IO2

AU4

SPI0_IO3

AU3

SPI0_CS0#

AU2

SPI0_CS1#

AU1

SPI0_CS2#

M2

GPP_D1/SPI1_CLK

M3

GPP_D2/SPI1_MISO

J4

GPP_D3/SPI1_MOSI

V1

GPP_D21/SPI1_IO2

V2

GPP_D22/SPI1_IO3

M1

GPP_D0/SPI1_CS#

G3

CL_CLK

G2

CL_DATA

G1

CL_RST#

AW13

GPP_A0/RCIN#

AY11

GPP_A6/SERIRQ

940432

01T010000015

1 2

R2003 2.2kOHM

tx_r0402

CRB 0.53 reserve 150k ohm

1 2

R2005 4.7KOhm@

tx_r0402

CRB 0.53 reserve 150k ohm

1 2

R2007 4.7KOhm@

tx_r0402

SPI - TOUCH

C LINK

BBS [21]

+3VSUS_ORG

+3VSUS_ORG

+3VSUS_ORG

SMBALERT# - Internal weak pull down 20k ohm
TLS Confidentiality
0 : Disable (default)
1 : Enable

SML0ALERT# - Internal weak pull down 20 kohm
0 : LPC EC (default)
1 : eSPI EC

BBS - Internal weak pull down 20k ohm
Boot BIOS Strap
0 : SPI destination (default)
1 : LPC destination

LPC

SMBUS, SMLINK

GPP_A14/SUS_STAT#/ESPI_RESET#

GPP_C0/SMBCLK

GPP_C1/SMBDATA

GPP_C2/SMBALERT#

GPP_C3/SML0CLK

GPP_C4/SML0DATA

GPP_C5/SML0ALERT#

GPP_C6/SML1CLK

GPP_C7/SML1DATA

GPP_B23/SML1ALERT#/PCHHOT#

GPP_A1/LAD0/ESPI_IO0
GPP_A2/LAD1/ESPI_IO1
GPP_A3/LAD2/ESPI_IO2
GPP_A4/LAD3/ESPI_IO3

GPP_A5/LFRAME#/ESPI_CS#

GPP_A9/CLKOUT_LPC0/ESPI_CLK

GPP_A10/CLKOUT_LPC1

GPP_A8/CLKRUN#

R7
R8
R10

R9
W2
W1

W3
V3
AM7

AY13
BA13
BB13
AY12
BA12
BA11

AW9
AY9
AW11

SMB_CLK
SMB_DAT
SMBALERT#

SML1_DAT
SML1ALERT#

CLK_KBCPCI_PCH_R

CLK_LPC1

1

T2012

1

T2013

1

T2008

1

SML0_CLK_NFC
SML0_DAT_NFC
WiGig_WAKE#

SML1_CLK

PM_CLKRUN#

INT_SERIRQSMBALERT#

SMB_CLK

SMB_DAT

T2003

1

T2004

WiGig_WAKE# [53]

1

T2014

1

T2015

1

T2010

LPC_AD0 [30,44,62]
LPC_AD1 [30,44,62]
LPC_AD2 [30,44,62]
LPC_AD3 [30,44,62]
LPC_FRAME# [30,44,62]
PM_SUS_STAT# [62]

R2001 22OHM tx_r0201_h10 1%
R2002 22OHM tx_r0201_h10 1%/Debug
R2014 22OHM tx_r0201_h10 1%/TPM

PM_CLKRUN# [30,62]

Unmount R2013,R2009
Vendor Suggest Pull High Resistor Need To Close To TPM
PM_CLKRUN#, INT_SERIRQ Need To Pull 10Kohm To+3VS at Chipset Side

1 2

R2013 10KOhm tx_r0402

1 2

R2009 10KOhm tx_r0402

3 4

2.2KOHM

1 2

2.2KOHM

1 2
1 2
1 2

RN2001B

tx_2r4p0402_h18

RN2001A

tx_2r4p0402_h18

Reserve For Touch Pad

Reserve For NFC

To EC

TPM

C2001

10PF/50V

tx_c0402

@

+3VS

+3VSUS_ORG

Delete SML0 PU

SML1_DAT

SML1_CLK

SML1ALERT#

3 4

RN2002B

2.2KOHM

tx_2r4p0402_h18

1 2

RN2002A2.2KOHM

tx_2r4p0402_h18

1 2

R2012 150KOhm 1%

tx_r0402

MOW WW52
To enable Direct Connect Interface (DCI),
a 150K pull up resistor will need to be added to PCHHOT#
pin. This pin must be low during the rising edge of RSMRST#.

+3VSUS_ORG [21,22,23,25, 26]

+3VS [3,4,21,22,23,24,30,32,36,40,41,44,45,50,51,53,55,56,57,62,70,91,92]

CLK_KBCPCI_PCH [30]

CLK_DEBUG [44]
LPCCLK_TPM [62]

12

12

C2002
10PF/50V

tx_c0402

@

GNDGND

A A

PCH(1)_SPI/LPC

PCH(1)_SPI/LPC

PCH(1)_SPI/LPC

Title :

Title :

PEGATRON PROPRIETARY AND CONFIDENTI AL

PEGATRON PROPRIETARY AND CONFIDENTI AL

PEGATRON PROPRIETARY AND CONFIDENTI AL

BG1-NB4

BG1-NB4

BG1-NB4

Size Project Name

Size Project Name

Size Project Name

C

C

C

HAWAII

HAWAII

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

HAWAII

Engineer:

Engineer:

Engineer:

1

Title :

Willy_Liao

Willy_Liao

Willy_Liao

20 100Thursday, March 31, 2016

20 100Thursday, March 31, 2016

20 100Thursday, March 31, 2016

Rev

Rev

Rev

0.0

0.0

0.0

5

Microsoft* Windows* 7 System WHCK Requirement – OEM platforms are
required to include a supported OS debug interface, accessible by an enduser.
This allows developers to help in driver debug. The supported
Windows 7 debug interfaces are EHCI, 1394 port and COM port.

With skylake EHCI Removal, Potential Gap with Windows* 7 Kernel Debug
and OS Installation – Mitigation Required

D D

4

3

2

1

+3VS

U0301F

GPP_B15
GPP_B16
GPP_B17

C C

WiGig_RST#[53]

VDB_PD_EN_PCH#[57]

1 2

BBS[ 20]

To implement UART for WIN7 WHCK requirement if need

Please refer to Intel document #548689 - RVP5

WLAN_ON[30,53]

R1.2

Sensors

Touch Panel

Rear Camera (5M)

B B

+3VSUS_ORG +3VSUS_ORG +3VSUS_ORG +3VSUS_ORG +3VSUS_ORG

12

R2104
10KOhm

tx_r0402

@

12

R2105
10KOhm

tx_r0402

A A

GND GND GND

BT_ON/OFF#[30,53]

LCD_BKLTEN_PCH[3,45]

PCH_I2C0_SDA[30,70]

PCH_I2C0_SCL[30,70]

PCH_I2C1_SDA[56]

PCH_I2C1_SCL[ 56]

PCH_I2C2_SDA[55]

PCH_I2C2_SCL[ 55]

+3VSUS_ORG +3VSUS_ORG

12

12

12

R2106
10KOhm

tx_r0402

R2107
10KOhm

tx_r0402

@

R2152
10KOhm

tx_r0402

@

PCB_ID2 GPP_D14 GPP_C15MEM_ID3

12

R2153
10KOhm

tx_r0402

GND

R2126 0Ohm tx_r0402_0ohm@
R2127 0Ohm tx_r0402_0ohm@

R2149 0Ohm tx_r0402_0ohm

GPP_C14PCB_ID1

MB Version ID

PCB_ID2 PCB_ID1 PCB_ID0
(GPP_D14) (GPP_C14) (GPP_C13)
A1 Build 1 0 0
A2 Build 1 0 1
B1 Build 1 1 0
B2 Build 1 1 1
C1 Build 0 0 0
C2 Build 0 0 1
PPR Build 0 1 0

Hawaii (PPR build default)

5

R2102

1 2
1 2

1 2

CAM_5M_EN_RESET#[55]
CAM_5M_EN_PWR[55]

0Ohm tx_r0402_0ohm

reserve UART

T2109
T2110
T2111
T2144

T2112

1

T2133

1

T2134

B15 B16 B17 C15

12

R2108
10KOhm

tx_r0402

12

R2109
10KOhm

tx_r0402

@

GND

Memory ID

GPP_B18

WiGig_RST#
VDB_PD_EN_PCH#

BBS_R

1

GPP_C8

1

GPP_C9

1

GPP_C10

1

GPP_C11

WLAN_ON_PCH
BT_ON/OFF#_PCH
GPP_C22

1

GPP_C23

PCH_I2C0_SDA
PCH_I2C0_SCL

PCH_I2C1_SDA
PCH_I2C1_SCL

PCH_I2C2_SDA
PCH_I2C2_SCL

CAM_5M_EN_RESET#
CAM_5M_EN_PWR

PCH_I2C4_SDA
PCH_I2C4_SCL

12

R2115
10KOhm

tx_r0402

12

R2116
10KOhm

tx_r0402

@

4

12

R2119
10KOhm

tx_r0402

12

R2120
10KOhm

tx_r0402

@

GND

AN8

AP7
AP8

AR7

AM5
AN7

AP5

AN5

AB1
AB2
W4
AB3

AD1
AD2
AD3
AD4

U7
U6

U8
U9

AH9

AH10

AH11
AH12

AF11
AF12

12

R2117
10KOhm

tx_r0402

12

R2118
10KOhm

tx_r0402

@

GND

LPSS ISH

GPP_B15/GSPI0_CS#
GPP_B16/GSPI0_CLK
GPP_B17/GSPI0_MISO
GPP_B18/GSPI0_MOSI

GPP_B19/GSPI1_CS#
GPP_B20/GSPI1_CLK
GPP_B21/GSPI1_MISO
GPP_B22/GSPI1_MOSI

GPP_C8/UART0_RXD
GPP_C9/UART0_TXD
GPP_C10/UART0_RTS#
GPP_C11/UART0_CTS#

GPP_C20/UART2_RXD
GPP_C21/UART2_TXD
GPP_C22/UART2_RTS#
GPP_C23/UART2_CTS#

GPP_C16/I2C0_SDA
GPP_C17/I2C0_SCL

GPP_C18/I2C1_SDA
GPP_C19/I2C1_SCL

GPP_F4/I2C2_SDA
GPP_F5/I2C2_SCL

GPP_F6/I2C3_SDA
GPP_F7/I2C3_SCL

GPP_F8/I2C4_SDA
GPP_F9/I2C4_SCL

940432

01T010000015

MEM_ID0 GPP_B15

MEM_ID1 GPP_B16PCB_ID0 GPP_C13

MEM_ID2 GPP_B17

C 3.3V GPIO

F 1.8V GPIO

+3VSUS_ORG

Hawaii (C build default)(SKU3)

3

GPP_D9
GPP_D10
GPP_D11

D 3.3V GPIO

GPP_F10/I2C5_SDA/ISH_I2C2_SDA

GPP_F11/I2C5_SCL/ISH_I2C2_SCL

GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA

GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL

Sx_EXIT_HOLDOFF#/GPP_A12/BM_BUSY#/ISH_GP6

GPP_D15/ISH_UART0_RTS#

GPP_D16/ISH_UART0_CTS#/SML0BALERT#

GPP_C12/UART1_RXD/ISH_UART1_RXD

GPP_C13/UART1_TXD/ISH_UART1_TXD
GPP_C14/UART1_RTS#/ISH_UART1_RTS#
GPP_C15/UART1_CTS#/ISH_UART1_CTS#

GPP_D12

GPP_D5/ISH_I2C0_SDA

GPP_D6/ISH_I2C0_SCL

GPP_D7/ISH_I2C1_SDA

GPP_D8/ISH_I2C1_SCL

GPP_A18/ISH_GP0
GPP_A19/ISH_GP1
GPP_A20/ISH_GP2
GPP_A21/ISH_GP3
GPP_A22/ISH_GP4
GPP_A23/ISH_GP5

Reserved

12

R2154
10KOhm

tx_r0402

Panel_ID0 GPP_D15

12

R2155
10KOhm

tx_r0402

@

GND

Panel ID

Panel_ID0
(GPP_D14)
AUO 1
PVO 0

P2
P3

I2C0_MUX_SEL

P4

GPP_D11

P1

GPP_D12

M4

ISH_I2C0_SDA

N3

ISH_I2C0_SCL

N1

ISH_I2C1_SDA

N2

ISH_I2C1_SCL

AD11
AD12

U1

TP_IRQ#

U2

GPP_D14

U3

GPP_D15

U4

TCH_PNL_RPS#_PCH_R

AC1

GPP_C12

AC2

GPP_C13

AC3

GPP_C14

AB4

GPP_C15

AY8

GYRO_INT_PCH

BA8

ALS_INT_PCH

BB7

E_COMPASS_RSTN_PCH

BA7
AY7
AW7
AP13

Hawaii (B2 build default)

1 2

R2151 0Ohm tx_r0402_0ohm@

1 2

R2150 0Ohm tx_r0402_0ohm@

1

T2132

1

T2148

1

T2129

1

T2147

1 2

R2103 0Ohm tx_r0402_0ohm

2

+3VS [3,4,20,22,23,24,30,32,36,40,41,44,45,50,51,53,55,56,57,62,70,91, 92]

I2C0_MUX_SEL [30]

VOL_UP# [30,56]

VOL_DOWN# [30,56]

ISH_I2C0_SDA [41, 70]
ISH_I2C0_SCL [41,70]

ISH_I2C1_SDA [41]
ISH_I2C1_SCL [41]

OP_SD# [ 36]

GYRO_INT_PCH [70]
ALS_INT_PCH [56]

E_COMPASS_RSTN_PCH [70]

PCH_I2C0_SDA
PCH_I2C0_SCL

PCH_I2C2_SDA
PCH_I2C2_SCL

PCH_I2C4_SDA
PCH_I2C4_SCL

R2113 2.2kOHM tx_r0402
R2114 2.2kOHM tx_r0402

R2128 4.7KOhm tx_r0402
R2129 4.7KOhm tx_r0402

R2124 4.7KOhm tx_r0402@
R2125 4.7KOhm tx_r0402@

GPP_B18

GSPI0_MOSI / GPP_B18 - Internal weak pull down 20k ohm
0 : Disable No Reboot mode(default)
1 : Enable NO Reboot Enable mode

Internal SensorHub

Internal SensorHub debug port

1 2
1 2

1 2
1 2

1 2
1 2

1 2

R2112 4.7KOhm tx_r0402@

1 2

R2122 4.7KOhm tx_r0402@

+3VSUS_ORG

Default is GPO, to reserve pull high to +3VSUS_ORG

Title :

Title :

PEGATRON PROPRIETARY AND CONFIDENTI AL

PEGATRON PROPRIETARY AND CONFIDENTI AL

PEGATRON PROPRIETARY AND CONFIDENTI AL

BG1-NB4

BG1-NB4

BG1-NB4

Size Project Name

Size Project Name

Size Project Name

C

C

C

HAWAII

HAWAII

Date: Sheet of

Date: Sheet of

Date: Sheet of

HAWAII

Engineer:

Engineer:

Engineer:

1

Title :

+3VS

+1.8VS

+1.8VS

+3VS

PCH(2)_ISH

PCH(2)_ISH

PCH(2)_ISH

Willy_Liao

Willy_Liao

Willy_Liao

21 100Thursday, March 31, 2016

21 100Thursday, March 31, 2016

21 100Thursday, March 31, 2016

Rev

Rev

Rev

0.0

0.0

0.0

5

4

3

2

1

+VCCPAZIO

+3VS

D D

U0301G

AUDIO

1 2

HDA_SYNC[36]
HDA_BCLK[36]
HDA_SDO[36]
HDA_SDI0[36]

HDA_RST#[36]

12

C C

Reserved for iSST
Reserved for iSST

B B

R1.1 . RF Suggest

Close To PCH Side

DMIC_CLK0_PCH[36]

DMIC_DAT0_PCH[36]

DGL_DIR_PCH[56] CAM_5M_EN_CLK [55]

DGL_PWR_MUX_EN_PCH[56]

HDA_SPKR[36]

C2201
10PF/50V

tx_c0402

@

R2211 3 3Ohm tx_r0402
R2212 3 3Ohm tx_r0402

SP2201 0Ohm tx_r0402_short_12m il

1 2

SP2202 0Ohm tx_r0402_short_12m il

1 2

SP2203 0Ohm tx_r0402_short_12m il

1 2

SP2204 0Ohm tx_r0402_short_12m il

1 2

SP2205 0Ohm tx_r0402_short_12m il

12

C2202

2.2UF/6.3V

tx_c0402

@

GNDGND

1 2
1 2

1 2

SP2208 0Ohm

tx_r0402_short_12mil

GND

T2201

T2202

R2202 2 0KOhm@

HDA_SYNC_R
HDA_BCLK_R
HDA_SDO_R
HDA_SDI0_R

1

HDA_SDI1
HDA_RST#_R

1

GPP_D23

Remove SNN

DMIC_CLK0_PCH_R
DMIC_DAT0_PCH_R

SPKR

1 2

tx_r0402

BA22

HDA_SYNC/I2S0_SFRM

AY22

HDA_BLK/I2S0_SCLK

BB22

HDA_SDO/I2S0_TXD

BA21

HDA_SDI0/I2S0_RXD

AY21

HDA_SDI1/I2S1_RXD

AW22

HDA_RST#/I2S1_SCLK

J5

GPP_D23/I2S_MCLK

AY20

I2S1_SFRM

AW20

I2S1_TXD

AK7

GPP_F1/I2S2_SFRM

AK6

GPP_F0/I2S2_SCLK

AK9

GPP_F2/I2S2_TXD

AK10

GPP_F3/I2S2_RXD

H5

GPP_D19/DMIC_CLK0

D7

GPP_D20/DMIC_DATA0

D8

GPP_D17/DMIC_CLK1

C8

GPP_D18/DMIC_DATA1

AW5

GPP_B14/SPKR

940432

01T010000015

SPKR

1 2

R2209 4 .7KOhm@

tx_r0402

1 2

R2210 4 .7KOhm@

tx_r0402

+3VS

+3VSUS_ORG

SDIO/SDXC

GPP_A17/SD_PWR_EN#/ISH_GP7

SPKR - Internal weak pull down
0 : Disable TOP Swap mode (default)
1 : Enable Top Swap Enable

Default is GPO, to reserve pull high to +3VSUS_ORG

+3VSUS_ORG

GPP_G0/SD_CMD
GPP_G1/SD_DATA0
GPP_G2/SD_DATA1
GPP_G3/SD_DATA2
GPP_G4/SD_DATA3

GPP_G5/SD_CD#

GPP_G6/SD_CLK

GPP_G7/SD_WP

GPP_A16/SD_1P8_SEL

SD_RCOMP

GPP_F23

+VCCPAZIO [26]

+3VS [3,4,20,21,23,24,30,32,36,40,41,44,45,50,51,53,55,56,57 ,62,70,91,92]

+3VSUS_ORG [20,21,23,25,26]

AB11
AB13
AB12
W12
W11
W10
W8
W7

BA9
BB9

AB7

AF13

uSD_CMD
uSD_DATA0
uSD_DATA1
uSD_DATA2
uSD_DATA3
uSD_CD#
uSD_CLK

uSD_WP
uSD_PWR_EN#
uSD_1P8_SEL

SKL_SD_RCOMP

1

T2211

1

T2212

1

T2213

1

T2214

1

T2215

1

T2216

1

T2217

1

T2205

1

T2218

1

T2219

1 2

R2201 2 00Ohm1% tx_r0402

GND

+VCCPAZIO

CRB 0.53 reserve 150k ohm

1 2

R2203 4 .7KOhm@

tx_r0402

A A

5

4

HDA_SDO_R

3

2 1

tx_sod323_h39

D2201CH751H-40AGP

PCH_FLASH_DESCRIPTOR [30]

HDA_SDO - Internal weak pull down
FLASH DESCRIPTOR SECURITY OVERRRIDE
0 : Enable security measure defined in the Flash Descriptor
1 : Disable Flash Descriptor Security

PEGATRON PROPRIETARY AND CONFIDENTIAL

PEGATRON PROPRIETARY AND CONFIDENTIAL

PEGATRON PROPRIETARY AND CONFIDENTIAL

BG1-NB4

BG1-NB4

BG1-NB4

Size Projec t Name

Size Projec t Name

Size Projec t Name

B

B

B

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

HAWAII

HAWAII

HAWAII

Title :

Title :

Title :

Engineer:

Engineer:

Engineer:

1

PCH(3)_HDA/SDIO

PCH(3)_HDA/SDIO

PCH(3)_HDA/SDIO

Willy_Liao

Willy_Liao

Willy_Liao

22 10 0Thursday, March 31, 2016

22 10 0Thursday, March 31, 2016

22 10 0Thursday, March 31, 2016

Rev

Rev

Rev

0.0

0.0

0.0

5

D D

SATA_RXN1_SSD[51]

C C

SSD

WLAN

WiGig

SATA_RXP1_SSD[51]

SATA_TXN1_SSD[51]
SATA_TXP1_SSD[51]

PCIE_RXN9_WLAN[53]

PCIE_RXP9_WLAN[53]

PCIE_TXN9_WLAN[53]
PCIE_TXP9_WLAN[53]

PCIE_RXN_WiGig[53]

PCIE_RXP_WiGig[53]

PCIE_TXN_WiGig[53]
PCIE_TXP_WiGig[ 53]

PCIE_RCOMP PDG 0.9 need 100 ohm 0.1% / CRB 0.53 use 100 ohm +-1%

Reserve TP for XDP

B B

4

12

C2309 0.1UF/16V tx_c0402

12

C2310 0.1UF/16V tx_c0402

12

C2311 0.1UF/16V tx_c0402

12

C2312 0.1UF/16V tx_c0402

1 2

R2301 100Ohm 1%tx_r0402

1

PROC_PRDY#

T2323

1

PROV_PREQ#

T2324

PIRQA#

PCIE_TXN9_WLAN_C
PCIE_TXP9_WLAN_C

PCIE_TXN_WiGig_C
PCIE_TXP_WiGig_C

PCIE_RCOMPN
PCIE_RCOMPP

U0301H

PCIE/USB3/SATA

H13

PCIE1_RXN/USB3_5_RXN

G13

PCIE1_RXP/USB3_5_RXP

B17

PCIE1_TXN/USB3_5_TXN

A17

PCIE1_TXP/USB3_5_TXP

G11

PCIE2_RXN/USB3_6_RXN

F11

PCIE2_RXP/USB3_6_RXP

D16

PCIE2_TXN/USB3_6_TXN

C16

PCIE2_TXP/USB3_6_TXP

H16

PCIE3_RXN

G16

PCIE3_RXP

D17

PCIE3_TXN

C17

PCIE3_TXP

G15

PCIE4_RXN

F15

PCIE4_RXP

B19

PCIE4_TXN

A19

PCIE4_TXP

F16

PCIE5_RXN

E16

PCIE5_RXP

C19

PCIE5_TXN

D19

PCIE5_TXP

G18

PCIE6_RXN

F18

PCIE6_RXP

D20

PCIE6_TXN

C20

PCIE6_TXP

F20

PCIE7_RXN/SATA0_RXN

E20

PCIE7_RXP/SATA0_RXP

B21

PCIE7_TXN/SATA0_TXN

A21

PCIE7_TXP/SATA0_TXP

G21

PCIE8_RXN/SATA1A_RXN

F21

PCIE8_RXP/SATA1A_RXP

D21

PCIE8_TXN/SATA1A_TXN

C21

PCIE8_TXP/SATA1A_TXP

E22

PCIE9_RXN

E23

PCIE9_RXP

B23

PCIE9_TXN

A23

PCIE9_TXP

F25

PCIE10_RXN

E25

PCIE10_RXP

D23

PCIE10_TXN

C23

PCIE10_TXP

F5

PCIE_RCOMPN

E5

PCIE_RCOMPP

D56

PROC_PRDY#

D61

PROC_PREQ#

BB11

GPP_A7/PIRQA#

E28

PCIE11_RXN/SATA1B_RXN

E27

PCIE11_RXP/SATA1B_RXP

D24

PCIE11_TXN/SATA1B_TXN

C24

PCIE11_TXP/SATA1B_TXP

E30

PCIE12_RXN/SATA2_RXN

F30

PCIE12_RXP/SATA2_RXP

A25

PCIE12_TXN/SATA2_TXN

B25

PCIE12_TXP/SATA2_TXP

940432

01T010000015

3

SSIC / USB3

USB3_2_RXN/SSIC_RXN

USB3_2_RXP/SSIC_RXP
USB3_2_TXN/SSIC_TXN
USB3_2_TXP/SSIC_TXP

USB2

USB2_VBUSSENSE

GPP_E9/USB2_OC0#
GPP_E10/USB2_OC1#
GPP_E11/USB2_OC2#
GPP_E12/USB2_OC3#

(OD)

GPP_E4/DEVSLP0

(OD)

GPP_E5/DEVSLP1

(OD)

GPP_E6/DEVSLP2

GPP_E0/SATAXPCIE0/SATAGP0
GPP_E1/SATAXPCIE1/SATAGP1
GPP_E2/SATAXPCIE2/SATAGP2

GPP_E8/SATALED#

USB3_1_RXN
USB3_1_RXP
USB3_1_TXN
USB3_1_TXP

USB3_3_RXN
USB3_3_RXP
USB3_3_TXN
USB3_3_TXP

USB3_4_RXN
USB3_4_RXP
USB3_4_TXN
USB3_4_TXP

USB2N_1
USB2P_1

USB2N_2
USB2P_2

USB2N_3
USB2P_3

USB2N_4
USB2P_4

USB2N_5
USB2P_5

USB2N_6
USB2P_6

USB2N_7
USB2P_7

USB2N_8
USB2P_8

USB2N_9
USB2P_9

USB2N_10
USB2P_10

USB2_COMP

USB2_ID

H8
G8
C13
D13

J6
H6
B13
A13

J10
H10
B15
A15

E10
F10
C15
D15

AB9
AB10

AD6
AD7

AH3
AJ3

AD9
AD10

AJ1
AJ2

AF6
AF7

AH1
AH2

AF8
AF9

AG1
AG2

AH7
AH8

AB6
AG3
AG4

A9
C9
D9
B9

J1
J2
J3

H2
H3
G4

H1

2

USBCOMP
USB2_ID_OTG
USB2_VBUSSENSE_OTG

OC0#
OC1#
OC2#
OC3#

SATA_DEVSLP0
SATA_DEVSLP1

SATA_SSD0_PEDET_R
SATA_SSD1_PEDET_R

SATA_LED#

R2304 10KOhm tx_r0402@

OC0#
OC1#
OC2#
OC3#

PIRQA#

+3VSUS_ORG

+3VS

USB_PN2_30 [52]
USB_PP2_30 [52]

USB_PN3_PD [96]
USB_PP3_PD [96]

USB_PN4_20 [56]
USB_PP4_20 [56]

USB_PN5_BT [53]
USB_PP5_BT [53]

USB_PN7_CCD [55]
USB_PP7_CCD [55]

USB_PN8_CR [40]
USB_PP8_CR [40]

USB_PN9_PD [96]
USB_PP9_PD [96]

USB2_COMP PDG 1.0 R=113 +-1%

1 2

R2302 113Ohm1% tx_r0402

1 2

R2319 1KOhm tx_r0402

1 2

R2320 1KOhm tx_r0402

1 2

R2307 0Ohm tx_r0402_0ohm

1 2

R2308 0Ohm tx_r0402_0ohm

1 2

1

T2325

1 2

R2321 0Ohm tx_r0402_0ohm

1 2

R2309 0Ohm tx_r0402_0ohm

1 2

R2310 0Ohm tx_r0402_0ohm

1 2

R2322 0Ohm tx_r0402_0ohm

1 2

R2318 10KOhm

tx_r0402

3 4
7 8
1 2
5 6

1

+3VSUS_ORG [20,21,22,25, 26]

+3VS [3,4,20,21,22,24,30,32,36,40,41,44,45,50,51,53,55,56,57,62,70,91, 92]

USB3_RXN2 [52]
USB3_RXP2 [52]
USB3_TXN2 [52]

USB3_TXP2 [52]

USB3_RXN3 [95]
USB3_RXP3 [95]
USB3_TXN3 [95]

USB3_TXP3 [95]

USB3.0

USB3.0 Type C

USB3.0

USB3.0 Type C

Keyboard (POGO CONN.)

Bluetooth

Camera (Front)

Card Reader

USB3.0 Type C

SATA SSD

+3VSUS_ORG

1

T2327

SATA_DEVSLP1 [51]

1

T2328

SATA_SSD1_PEDET [51]

USB30 port2
POGO
Type C

MOW 5.1.3 If the platform does not

GND
GND

support Dual Role, then USB2_ID pin

GND

shall be connected directly to GND.

RN2301B

10KOhm

RN2301D

10KOhm

RN2301A

10KOhm

RN2301C

10KOhm

+3VS

1

T2326

+3VS

tx_4r8p0402_h22
tx_4r8p0402_h22
tx_4r8p0402_h22
tx_4r8p0402_h22

USB_OC1#_PCH [ 52]
USB_OC2#_PCH [ 56]
USB_OC3#_PCH [ 96]

C2315
10PF/50V

tx_c0201

RF reserve

12

Capture from 545659_545659_SKL_PCH_LP_EDS_Rev1_0_pub
Please refer the latest Doc.

Remove XDP

A A

PCH(4)_USB/PCIE/SATA

PCH(4)_USB/PCIE/SATA

PCH(4)_USB/PCIE/SATA

Title :

Title :

PEGATRON PROPRIETARY AND CONFIDENTI AL

PEGATRON PROPRIETARY AND CONFIDENTI AL

PEGATRON PROPRIETARY AND CONFIDENTI AL

BG1-NB4

BG1-NB4

BG1-NB4

Size Project Name

Size Project Name

Size Project Name

C

C

C

HAWAII

HAWAII

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

HAWAII

Engineer:

Engineer:

Engineer:

1

Title :

Willy_Liao

Willy_Liao

Willy_Liao

23 100Thursday, March 31, 2016

23 100Thursday, March 31, 2016

23 100Thursday, March 31, 2016

Rev

Rev

Rev

0.0

0.0

0.0

5

D D

Rear Camera (5M) Rear Camera (5M)

C C

Remove SNN

CLK_PC IE_WiG ig#_PC H[53]

WiGig

CLK_PC IE_WiG ig_PCH[53]
CLK_RE Q3_WiG ig#[53]

CLK_PC IE_WL AN#_PC H[53]

WLAN

B B

CLK_RE Q3_WiG ig#_R

CLK_RE Q3_WiG ig#_R

CLK_RE Q4_WL AN#_R

CLK_RE Q4_WL AN#_R

CLK_RE Q5_CR# _R

CLK_RE Q5_CR# _R

SRCCLKREQ#[5:0] (PDG v1.3 Page 835)

SRCCLKREQ#[5:0] (PDG v1.3 Page 835)

SRCCLKREQ#[5:0] (PDG v1.3 Page 835)SRCCLKREQ#[5:0] (PDG v1.3 Page 835)
Any un-used, disabled, must be left as no connects at the PCH side on the platform.

Any un-used, disabled, must be left as no connects at the PCH side on the platform.

Any un-used, disabled, must be left as no connects at the PCH side on the platform.Any un-used, disabled, must be left as no connects at the PCH side on the platform.
Any used, enabled, should connect to a PCIe* connector pin or a device down ball with a 10K Ohm ±10% external pull-up resistor to core rail.

Any used, enabled, should connect to a PCIe* connector pin or a device down ball with a 10K Ohm ±10% external pull-up resistor to core rail.

Any used, enabled, should connect to a PCIe* connector pin or a device down ball with a 10K Ohm ±10% external pull-up resistor to core rail.Any used, enabled, should connect to a PCIe* connector pin or a device down ball with a 10K Ohm ±10% external pull-up resistor to core rail.
CLKOUT_PCIE_P/N[5:0] (PDG v1.3 Page420)

CLKOUT_PCIE_P/N[5:0] (PDG v1.3 Page420)

CLKOUT_PCIE_P/N[5:0] (PDG v1.3 Page420)CLKOUT_PCIE_P/N[5:0] (PDG v1.3 Page420)
Any differential clock pair not being used must be left as no connect

Any differential clock pair not being used must be left as no connect

Any differential clock pair not being used must be left as no connectAny differential clock pair not being used must be left as no connect

A A

1 2

R2430 1 0KOhm tx_r0402

1 2

R2409 1 0KOhm tx_r0402@

1 2

R2412 1 0KOhm tx_r0402@

1 2

R2429 1 0KOhm tx_r0402

1 2

R2408 1 0KOhm tx_r0402@

1 2

R2411 1 0KOhm tx_r0402@

1 2

R2442 1 0KOhm tx_r0402

1 2

R2441 1 0KOhm tx_r0402@

1 2

R2440 1 0KOhm tx_r0402@

+3VSUS

+3VS

+3VSUS

+3VS

+3VSUS

+3VS

GND

GND

GND

CLK_PC IE_WL AN_PCH[53]
CLK_RE Q4_WL AN#[53]

4

MCSI_1_ DATA0_ DN[55]
MCSI_1_ DATA0_ DP[55]
MCSI_1_ DATA1_ DN[55]
MCSI_1_ DATA1_ DP[55]

1

T2401

1

T2402

1 2

SP2418 0Ohm tx_r0402_ short_12m il

1 2

SP2419 0Ohm tx_r0402_ short_12m il

1 2

R2434 0 Ohm tx_r0402_ 0ohm

1 2

SP2412 0Ohm tx_r0402_ short_12m il

1 2

SP2413 0Ohm tx_r0402_ short_12m il

1 2

R2433 0 Ohm tx_r0402_ 0ohm

M,2_SSD1 _SUSCLK[51]
M,2_WLA N_SUSCLK[53]

U0301I

CSI-2

A36

CSI2_DN0

B36

CSI2_DP0

C38

CSI2_DN1

D38

CSI2_DP1

C36

CSI2_DN2

D36

CSI2_DP2

A38

CSI2_DN3

B38

CSI2_DP3

C31

CSI2_DN4

D31

CSI2_DP4

C33

CSI2_DN5

D33

CSI2_DP5

A31

CSI2_DN6

B31

CSI2_DP6

A33

CSI2_DN7

B33

CSI2_DP7

A29

CSI2_DN8

B29

CSI2_DP8

C28

CSI2_DN9

D28

CSI2_DP9

A27

CSI2_DN10

B27

CSI2_DP10

C27

CSI2_DN11

D27

CSI2_DP11

940432

01T010 000015

U0301J

SNN_CLKO UT_PCIE _N0

SNN_CLKO UT_PCIE _N2

CLK_PC IE_WiG ig#_PC H_R
CLK_PC IE_WiG ig_PCH_ R
CLK_RE Q3_WiG ig#_R

CLK_PC IE_WL AN#_PC H_R
CLK_PC IE_WL AN_PCH_ R
CLK_RE Q4_WL AN#_R

CLK_RE Q5_CR# _R

D42

CLKOUT_PCIE_N0

C42

CLKOUT_PCIE_P0

AR10

GPP_B5/SRCCLKREQ0#

B42

CLKOUT_PCIE_N1

A42

CLKOUT_PCIE_P1

AT7

GPP_B6/SRCCLKREQ1#

D41

CLKOUT_PCIE_N2

C41

CLKOUT_PCIE_P2

AT8

GPP_B7/SRCCLKREQ2#

D40

CLKOUT_PCIE_N3

C40

CLKOUT_PCIE_P3

AT10

GPP_B8/SRCCLKREQ3#

B40

CLKOUT_PCIE_N4

A40

CLKOUT_PCIE_P4

AU8

GPP_B9/SRCCLKREQ4#

E40

CLKOUT_PCIE_N5

E38

CLKOUT_PCIE_P5

AU7

GPP_B10/SRCCLKREQ5#

940432

01T010 000015

2015.04.06 YenPin
Add CLOCK Buffer Schematic (CRB Page123)

R2426~R2428 Close To U2401 S USCLK is on the DSW well and i s available

GND

1 2

R2426 33Ohm tx_r0402@

1 2

R2427 33Ohm tx_r0402@

C2408 0.01UF/50V@

tx_c0402

GPP_F13/EMMC_DATA0
GPP_F14/EMMC_DATA1
GPP_F15/EMMC_DATA2
GPP_F16/EMMC_DATA3
GPP_F17/EMMC_DATA4
GPP_F18/EMMC_DATA5
GPP_F19/EMMC_DATA6
GPP_F20/EMMC_DATA7

CLOCK SIGNALS

12

GPP_F21/EMMC_RCLK

CSI2_CLKN0
CSI2_CLKP0
CSI2_CLKN1
CSI2_CLKP1
CSI2_CLKN2
CSI2_CLKP2
CSI2_CLKN3
CSI2_CLKP3

CSI2_COMP

GPP_D4/FLASHTRIG

EMMC

GPP_F22/EMMC_CLK

GPP_F12/EMMC_CMD

EMMC_RCOMP

CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P

XCLK_BIASREF

+VCCDSW

earlier in the boot sequence.

M,2_SSD1 _SUSCLK _R
M,2_WLA N_SUSCLK _R

GND

C37
D37
C32
D32
C29
D29
B26
A26

E13
B7

AP2
AP1
AP3
AN3
AN1
AN2
AM4
AM1

AM2
AM3
AP4

AT1

GPD8/SUSCLK

XTAL24_IN

XTAL24_OUT

RTCX1
RTCX2

SRTCRST#

RTCRST#

1
2
3
4

R2439 0Ohm

tx_r0402_ 0ohm

R2437 0Ohm

tx_r0402_ 0ohm

CSI2_C OMP
GPP_D4

EMMC_RCO MP

F43
E43

BA17

E37
E35

E42

AM18
AM20

AN18
AM16

U2401

VDD
Q0
Q1
GND1

ICS553 MILFT

06T100 000009

0610-00DF000

@

1 2

@

1 2

3

Delete XDP clk

OE

Q3
Q2

ICLK

SUSCLK_ PCH

XTAL_2 4M_IN
XTAL_2 4M_OUT

XCLK_B IASREF

XTAL_3 2K_X1
XTAL_3 2K_X2

SRTC_R ST#
RTC_RS T#

8
7
6
5

MCSI_1_ CLK_DN [55]
MCSI_1_ CLK_DP [5 5]

1 2

R2418 100Ohm tx_r04021%

1

1 2

R2419 200Ohm tx_r04021%

1 2

R2417 2.7KOHM tx_r0402 1%

1 2

R2422 60.4Ohm@ tx_r0402

SUSCLK_ PCH_BUF

SUSCLK_ PCH_BYP

T2403

PDG 0.9 - 2.7k +-1%

1 2

R2428 33Ohm

@

tx_r0402

1 2

R2438 33Ohm

tx_r0402

GND

GND

+VCCF24 NS_1P0

GND

SUSCLK_ PCH_R

12

R2432
1MOhm

tx_r0402

SP2401

1 2

0Ohm

tx_r0402_ short_12m il

SP2402

1 2

0Ohm

tx_r0402_ short_12m il

12

R2402
10MOhm

tx_r0402

SW_RT CRST[30]

XTAL_2 4M_OUT_R

12

R2436
1KOhm

@

tx_r0402

GND

+VCC_RT C

12

C2407
1UF/6.3V

tx_c0402

GND

13

2

X2401

4

24MHZ

XTAL 24 MHZ 10PF/3 0PPM SMD

XTAL_3 2K_X1_ R

X2403

32.768K HZ

1 2

+/-20ppm/9 PF
tx_xtal_2p_12 6x59

R2406 0Ohm

1 2

R2435 0Ohm

tx_r0402_ 0ohm

+VCCF24 NS_1P0

+VCC_RT C

+3VA

+3VS

+3VSUS

1 2

R2420 1KOhm

@

tx_r0402

D2401

2 1

CH751H-40 AGP

40V/30m A
tx_sod32 3_h39

1 2

C2401 10PF/50V

tx_c0201 NPO/+/-5%

C2402 10PF/50V

C2403 8PF/50V

tx_c0402

C2404 8PF/50V

tx_c0402

1 2

tx_r0402_ 0ohm

10KOhm

tx_r0201_ h10

SUSCLK_ PCH

2

+VCCF24 NS_1P0 [2 6]

+VCC_RT C [25,26,36 ]

+3VA [30,36,53,56 ,57,70,8 1,93,95]

+3VS [3,4,20,21,22 ,23,30,3 2,36,40,4 1,44,45 ,50,51,53 ,55,56,57 ,62,70,9 1,92]

+3VSUS [4,25,26 ,28,30,5 1,53,62,6 8,81,84 ,92,95]

+3VA

12

12

R2425

R2423

0Ohm

@

1.5KOHM

tx_r0402_ 0ohm

tx_r0402
1%

+RTC_AC

3.19V~3.18V VCCRTC is sourced from Vbatt in G3 or VCCDSW_3p3

12

R2424

45.3KOHM

tx_r0402
1%

GND

GND

GND

12

GND

tx_c0201

12

GND

12

GND

Q2401

G

1

12

R2407

NX7002A K

07T040 000001

1

JRST24 02

SGL_JUMP

@

2

1

D

JRST24 01

SGL_JUMP

@

2

S

2 3

GND GND

GND

in Non-G3 state, platform designers must ensure the
effective voltage at VCCRTC does not exceed 3.2V.

1 2

R2403 2 0KOhm

tx_r0402

12

C2405

1

2.2uF/6.3V

2

tx_c0201 _t0d09_ h15

GNDGND

1 2

R2404 2 0KOhm

tx_r0402

12

C2406

2.2uF/6.3V

1

tx_c0201 _t0d09_ h15

2

1

+VCC_RT C

PCH(5)_CLK

PCH(5)_CLK

PCH(5)_CLK

Title :

Title :

HAWAII

HAWAII

HAWAII

Title :

Engineer:

Engineer:

Engineer:

Willy_Liao

Willy_Liao

Willy_Liao

24 100Thursday, March 3 1, 2016

24 100Thursday, March 3 1, 2016

24 100Thursday, March 3 1, 2016

Rev

Rev

Rev

0.0

0.0

0.0

PEGATRON PROPRIETARY AND CONFIDENTIAL

PEGATRON PROPRIETARY AND CONFIDENTIAL

PEGATRON PROPRIETARY AND CONFIDENTIAL

BG1-NB4

BG1-NB4

BG1-NB4

Size Project Name

Size Project Name

Size Project Name

D

D

D

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

1